sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftargetH/translations/zh_CN/networking/device_drivers/ethernet/marvell/octeontx2modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetH/translations/zh_TW/networking/device_drivers/ethernet/marvell/octeontx2modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetH/translations/it_IT/networking/device_drivers/ethernet/marvell/octeontx2modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetH/translations/ja_JP/networking/device_drivers/ethernet/marvell/octeontx2modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetH/translations/ko_KR/networking/device_drivers/ethernet/marvell/octeontx2modnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetH/translations/pt_BR/networking/device_drivers/ethernet/marvell/octeontx2modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetH/translations/sp_SP/networking/device_drivers/ethernet/marvell/octeontx2modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h7SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)h]h7SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhb/var/lib/git/docbuild/linux/Documentation/networking/device_drivers/ethernet/marvell/octeontx2.rsthKubhsection)}(hhh](htitle)}(h$Marvell OcteonTx2 RVU Kernel Driversh]h$Marvell OcteonTx2 RVU Kernel Drivers}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h-Copyright (c) 2020 Marvell International Ltd.h]h-Copyright (c) 2020 Marvell International Ltd.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hContentsh]hContents}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh bullet_list)}(hhh](h list_item)}(h `Overview`_h]h)}(hjh]h reference)}(hjh]hOverview}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameOverviewrefidoverviewuh1j hj resolvedKubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h `Drivers`_h]h)}(hj.h]j )}(hj.h]hDrivers}(hj3hhhNhNubah}(h]h ]h"]h$]h&]nameDriversjdriversuh1j hj0jKubah}(h]h ]h"]h$]h&]uh1hhhhK hj,ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h`Basic packet flow`_h]h)}(hjQh]j )}(hjQh]hBasic packet flow}(hjVhhhNhNubah}(h]h ]h"]h$]h&]nameBasic packet flowjbasic-packet-flowuh1j hjSjKubah}(h]h ]h"]h$]h&]uh1hhhhKhjOubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h`Devlink health reporters`_h]h)}(hjth]j )}(hjth]hDevlink health reporters}(hjyhhhNhNubah}(h]h ]h"]h$]h&]nameDevlink health reportersjdevlink-health-reportersuh1j hjvjKubah}(h]h ]h"]h$]h&]uh1hhhhKhjrubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h`Quality of service`_h]h)}(hjh]j )}(hjh]hQuality of service}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameQuality of servicejquality-of-serviceuh1j hjjKubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h`RVU representors`_ h]h)}(h`RVU representors`_h]j )}(hjh]hRVU representors}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameRVU representorsjrvu-representorsuh1j hjjKubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK hhhhubeh}(h]contentsah ]h"]contentsah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hOverviewh]hOverview}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXResource virtualization unit (RVU) on Marvell's OcteonTX2 SOC maps HW resources from the network, crypto and other functional blocks into PCI-compatible physical and virtual functions. Each functional block again has multiple local functions (LFs) for provisioning to PCI devices. RVU supports multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs). PF0 is called the administrative / admin function (AF) and has privileges to provision RVU functional block's LFs to each of the PF/VF.h]hXResource virtualization unit (RVU) on Marvell’s OcteonTX2 SOC maps HW resources from the network, crypto and other functional blocks into PCI-compatible physical and virtual functions. Each functional block again has multiple local functions (LFs) for provisioning to PCI devices. RVU supports multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs). PF0 is called the administrative / admin function (AF) and has privileges to provision RVU functional block’s LFs to each of the PF/VF.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hRVU managed networking functional blocks - Network pool or buffer allocator (NPA) - Network interface controller (NIX) - Network parser CAM (NPC) - Schedule/Synchronize/Order unit (SSO) - Loopback interface (LBK) h](hterm)}(h(RVU managed networking functional blocksh]h(RVU managed networking functional blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK$hjubh definition)}(hhh]h)}(hhh](j)}(h&Network pool or buffer allocator (NPA)h]h)}(hj0h]h&Network pool or buffer allocator (NPA)}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj.ubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(h"Network interface controller (NIX)h]h)}(hjGh]h"Network interface controller (NIX)}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjEubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hNetwork parser CAM (NPC)h]h)}(hj^h]hNetwork parser CAM (NPC)}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hj\ubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(h%Schedule/Synchronize/Order unit (SSO)h]h)}(hjuh]h%Schedule/Synchronize/Order unit (SSO)}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjsubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hLoopback interface (LBK) h]h)}(hLoopback interface (LBK)h]hLoopback interface (LBK)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]jjuh1hhhhK hj(ubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhK$hj ubj)}(hRVU managed non-networking functional blocks - Crypto accelerator (CPT) - Scheduled timers unit (TIM) - Schedule/Synchronize/Order unit (SSO) Used for both networking and non networking usecases h](j)}(h,RVU managed non-networking functional blocksh]h,RVU managed non-networking functional blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK*hjubj')}(hhh]h)}(hhh](j)}(hCrypto accelerator (CPT)h]h)}(hjh]hCrypto accelerator (CPT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hScheduled timers unit (TIM)h]h)}(hjh]hScheduled timers unit (TIM)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h[Schedule/Synchronize/Order unit (SSO) Used for both networking and non networking usecases h]h)}(hZSchedule/Synchronize/Order unit (SSO) Used for both networking and non networking usecasesh]hZSchedule/Synchronize/Order unit (SSO) Used for both networking and non networking usecases}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhK*hj hhubj)}(hResource provisioning examples - A PF/VF with NIX-LF & NPA-LF resources works as a pure network device - A PF/VF with CPT-LF resource works as a pure crypto offload device. h](j)}(hResource provisioning examplesh]hResource provisioning examples}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK.hj$ubj')}(hhh]h)}(hhh](j)}(hEA PF/VF with NIX-LF & NPA-LF resources works as a pure network deviceh]h)}(hj>h]hEA PF/VF with NIX-LF & NPA-LF resources works as a pure network device}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hj<ubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hDA PF/VF with CPT-LF resource works as a pure crypto offload device. h]h)}(hCA PF/VF with CPT-LF resource works as a pure crypto offload device.h]hCA PF/VF with CPT-LF resource works as a pure crypto offload device.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjSubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]jjuh1hhhhK-hj6ubah}(h]h ]h"]h$]h&]uh1j&hj$ubeh}(h]h ]h"]h$]h&]uh1jhhhK.hj hhubeh}(h]h ]h"]h$]h&]uh1j hjhhhNhNubh)}(hKRVU functional blocks are highly configurable as per software requirements.h]hKRVU functional blocks are highly configurable as per software requirements.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjhhubj )}(hhh]j)}(hX`Firmware setups following stuff before kernel boots - Enables required number of RVU PFs based on number of physical links. - Number of VFs per PF are either static or configurable at compile time. Based on config, firmware assigns VFs to each of the PFs. - Also assigns MSIX vectors to each of PF and VFs. - These are not changed after kernel boot. h](j)}(h3Firmware setups following stuff before kernel bootsh]h3Firmware setups following stuff before kernel boots}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK7hjubj')}(hhh]h)}(hhh](j)}(hEEnables required number of RVU PFs based on number of physical links.h]h)}(hjh]hEEnables required number of RVU PFs based on number of physical links.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hNumber of VFs per PF are either static or configurable at compile time. Based on config, firmware assigns VFs to each of the PFs.h]h)}(hNumber of VFs per PF are either static or configurable at compile time. Based on config, firmware assigns VFs to each of the PFs.h]hNumber of VFs per PF are either static or configurable at compile time. Based on config, firmware assigns VFs to each of the PFs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h0Also assigns MSIX vectors to each of PF and VFs.h]h)}(hjh]h0Also assigns MSIX vectors to each of PF and VFs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h)These are not changed after kernel boot. h]h)}(h(These are not changed after kernel boot.h]h(These are not changed after kernel boot.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhK7hjubah}(h]h ]h"]h$]h&]uh1j hjhhhNhNubeh}(h]jah ]h"]overviewah$]h&]uh1hhhhhhhhK referencedKubh)}(hhh](h)}(hDriversh]hDrivers}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhhhK:ubh)}(hLinux kernel will have multiple drivers registering to different PF and VFs of RVU. Wrt networking there will be 3 flavours of drivers.h]hLinux kernel will have multiple drivers registering to different PF and VFs of RVU. Wrt networking there will be 3 flavours of drivers.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK ubah}(h]h ]h"]h$]h&]uh1jhj$ ubj)}(hReason in words h]h)}(hReason in wordsh]hReason in words}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU ubah}(h]h ]h"]h$]h&]uh1jhj$ ubeh}(h]h ]h"]h$]h&]jjuh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hhhMhjI hhubh)}(h For example::h]h For example:}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjI hhubj )}(hX~# devlink health dump show pci/0002:01:00.0 reporter hw_nix_intr NIX_AF_RVU: NIX RVU Interrupt Reg : 1 Unmap Slot Error ~# devlink health dump show pci/0002:01:00.0 reporter hw_nix_gen NIX_AF_GENERAL: NIX General Interrupt Reg : 1 Rx multicast pkt drop ~# devlink health dump show pci/0002:01:00.0 reporter hw_nix_err NIX_AF_ERR: NIX Error Interrupt Reg : 64 Rx on unmapped PF_FUNCh]hX~# devlink health dump show pci/0002:01:00.0 reporter hw_nix_intr NIX_AF_RVU: NIX RVU Interrupt Reg : 1 Unmap Slot Error ~# devlink health dump show pci/0002:01:00.0 reporter hw_nix_gen NIX_AF_GENERAL: NIX General Interrupt Reg : 1 Rx multicast pkt drop ~# devlink health dump show pci/0002:01:00.0 reporter hw_nix_err NIX_AF_ERR: NIX Error Interrupt Reg : 64 Rx on unmapped PF_FUNC}hj sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjI hhubeh}(h] nix-reportersah ]h"] nix reportersah$]h&]uh1hhjS hhhhhKubeh}(h]jah ]h"]devlink health reportersah$]h&]uh1hhhhhhhhKj)Kubh)}(hhh](h)}(hQuality of serviceh]hQuality of service}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM'ubh)}(hhh](h)}(h&Hardware algorithms used in schedulingh]h&Hardware algorithms used in scheduling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM+ubh)}(hXocteontx2 silicon and CN10K transmit interface consists of five transmit levels starting from SMQ/MDQ, TL4 to TL1. Each packet will traverse MDQ, TL4 to TL1 levels. Each level contains an array of queues to support scheduling and shaping. The hardware uses the below algorithms depending on the priority of scheduler queues. once the usercreates tc classes with different priorities, the driver configures schedulers allocated to the class with specified priority along with rate-limiting configuration.h]hXocteontx2 silicon and CN10K transmit interface consists of five transmit levels starting from SMQ/MDQ, TL4 to TL1. Each packet will traverse MDQ, TL4 to TL1 levels. Each level contains an array of queues to support scheduling and shaping. The hardware uses the below algorithms depending on the priority of scheduler queues. once the usercreates tc classes with different priorities, the driver configures schedulers allocated to the class with specified priority along with rate-limiting configuration.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj hhubj)}(hhh](j)}(hStrict Priority - Once packets are submitted to MDQ, hardware picks all active MDQs having different priority using strict priority. h](h)}(hStrict Priorityh]hStrict Priority}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj ubj )}(hy- Once packets are submitted to MDQ, hardware picks all active MDQs having different priority using strict priority. h]h)}(hhh]j)}(hsOnce packets are submitted to MDQ, hardware picks all active MDQs having different priority using strict priority. h]h)}(hrOnce packets are submitted to MDQ, hardware picks all active MDQs having different priority using strict priority.h]hrOnce packets are submitted to MDQ, hardware picks all active MDQs having different priority using strict priority.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]jjuh1hhhhM7hj ubah}(h]h ]h"]h$]h&]uh1j hhhM7hj ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h\Round Robin - Active MDQs having the same priority level are chosen using round robin. h](h)}(h Round Robinh]h Round Robin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hjubj )}(hL- Active MDQs having the same priority level are chosen using round robin. h]h)}(hhh]j)}(hJActive MDQs having the same priority level are chosen using round robin. h]h)}(hHActive MDQs having the same priority level are chosen using round robin.h]hHActive MDQs having the same priority level are chosen using round robin.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj3ubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]jjuh1hhhhM<hj,ubah}(h]h ]h"]h$]h&]uh1j hhhM<hjubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjuh1jhj hhhhhM5ubeh}(h]&hardware-algorithms-used-in-schedulingah ]h"]&hardware algorithms used in schedulingah$]h&]uh1hhj hhhhhM+ubh)}(hhh](h)}(hSetup HTB offloadh]hSetup HTB offload}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhhhhhM@ubj)}(hhh](j)}(hXEnable HW TC offload on the interface:: # ethtool -K hw-tc-offload on h](h)}(h'Enable HW TC offload on the interface::h]h&Enable HW TC offload on the interface:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMBhjubj )}(h)# ethtool -K hw-tc-offload onh]h)# ethtool -K hw-tc-offload on}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMDhjubeh}(h]h ]h"]h$]h&]uh1jhj|hhhhhNubj)}(hCreate htb root:: # tc qdisc add dev clsact # tc qdisc replace dev root handle 1: htb offload h](h)}(hCreate htb root::h]hCreate htb root:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjubj )}(hc# tc qdisc add dev clsact # tc qdisc replace dev root handle 1: htb offloadh]hc# tc qdisc add dev clsact # tc qdisc replace dev root handle 1: htb offload}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMHhjubeh}(h]h ]h"]h$]h&]uh1jhj|hhhhhNubj)}(hCreate tc classes with different priorities:: # tc class add dev parent 1: classid 1:1 htb rate 10Gbit prio 1 # tc class add dev parent 1: classid 1:2 htb rate 10Gbit prio 7 h](h)}(h-Create tc classes with different priorities::h]h,Create tc classes with different priorities:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjubj )}(h# tc class add dev parent 1: classid 1:1 htb rate 10Gbit prio 1 # tc class add dev parent 1: classid 1:2 htb rate 10Gbit prio 7h]h# tc class add dev parent 1: classid 1:1 htb rate 10Gbit prio 1 # tc class add dev parent 1: classid 1:2 htb rate 10Gbit prio 7}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMMhjubeh}(h]h ]h"]h$]h&]uh1jhj|hhhhhNubj)}(hXbCreate tc classes with same priorities and different quantum:: # tc class add dev parent 1: classid 1:1 htb rate 10Gbit prio 2 quantum 409600 # tc class add dev parent 1: classid 1:2 htb rate 10Gbit prio 2 quantum 188416 # tc class add dev parent 1: classid 1:3 htb rate 10Gbit prio 2 quantum 32768 h](h)}(h>Create tc classes with same priorities and different quantum::h]h=Create tc classes with same priorities and different quantum:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhjubj )}(hX# tc class add dev parent 1: classid 1:1 htb rate 10Gbit prio 2 quantum 409600 # tc class add dev parent 1: classid 1:2 htb rate 10Gbit prio 2 quantum 188416 # tc class add dev parent 1: classid 1:3 htb rate 10Gbit prio 2 quantum 32768h]hX# tc class add dev parent 1: classid 1:1 htb rate 10Gbit prio 2 quantum 409600 # tc class add dev parent 1: classid 1:2 htb rate 10Gbit prio 2 quantum 188416 # tc class add dev parent 1: classid 1:3 htb rate 10Gbit prio 2 quantum 32768}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMShjubeh}(h]h ]h"]h$]h&]uh1jhj|hhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjuh1jhjkhhhhhMBubeh}(h]setup-htb-offloadah ]h"]setup htb offloadah$]h&]uh1hhj hhhhhM@ubeh}(h]jah ]h"]quality of serviceah$]h&]uh1hhhhhhhhM'j)Kubh)}(hhh](h)}(hRVU Representorsh]hRVU Representors}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhhhM[ubh)}(hXRVU representor driver adds support for creation of representor devices for RVU PFs' VFs in the system. Representor devices are created when user enables the switchdev mode. Switchdev mode can be enabled either before or after setting up SRIOV numVFs. All representor devices share a single NIXLF but each has a dedicated Rx/Tx queues. RVU PF representor driver registers a separate netdev for each Rx/Tx queue pair.h]hXRVU representor driver adds support for creation of representor devices for RVU PFs’ VFs in the system. Representor devices are created when user enables the switchdev mode. Switchdev mode can be enabled either before or after setting up SRIOV numVFs. All representor devices share a single NIXLF but each has a dedicated Rx/Tx queues. RVU PF representor driver registers a separate netdev for each Rx/Tx queue pair.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hj,hhubh)}(hXCurrent HW does not support built-in switch which can do L2 learning and forwarding packets between representee and representor. Hence, packet path between representee and it's representor is achieved by setting up appropriate NPC MCAM filters. Transmit packets matching these filters will be loopbacked through hardware loopback channel/interface (i.e, instead of sending them out of MAC interface). Which will again match the installed filters and will be forwarded. This way representee => representor and representor => representee packet path is achieved. These rules get installed when representors are created and gets active/deactivate based on the representor/representee interface state.h]hXCurrent HW does not support built-in switch which can do L2 learning and forwarding packets between representee and representor. Hence, packet path between representee and it’s representor is achieved by setting up appropriate NPC MCAM filters. Transmit packets matching these filters will be loopbacked through hardware loopback channel/interface (i.e, instead of sending them out of MAC interface). Which will again match the installed filters and will be forwarded. This way representee => representor and representor => representee packet path is achieved. These rules get installed when representors are created and gets active/deactivate based on the representor/representee interface state.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehj,hhubh)}(hUsage example:h]hUsage example:}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMphj,hhubj )}(hX- Change device to switchdev mode:: # devlink dev eswitch set pci/0002:1c:00.0 mode switchdev - List of representor devices on the system:: # ip link show Rpf1vf0: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether f6:43:83:ee:26:21 brd ff:ff:ff:ff:ff:ff Rpf1vf1: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 12:b2:54:0e:24:54 brd ff:ff:ff:ff:ff:ff Rpf1vf2: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 4a:12:c4:4c:32:62 brd ff:ff:ff:ff:ff:ff Rpf1vf3: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether ca:cb:68:0e:e2:6e brd ff:ff:ff:ff:ff:ff Rpf2vf0: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 06:cc:ad:b4:f0:93 brd ff:ff:ff:ff:ff:ff h]h)}(hhh](j)}(hbChange device to switchdev mode:: # devlink dev eswitch set pci/0002:1c:00.0 mode switchdev h](h)}(h!Change device to switchdev mode::h]h Change device to switchdev mode:}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjnubj )}(h9# devlink dev eswitch set pci/0002:1c:00.0 mode switchdevh]h9# devlink dev eswitch set pci/0002:1c:00.0 mode switchdev}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMthjnubeh}(h]h ]h"]h$]h&]uh1jhjkubj)}(hXList of representor devices on the system:: # ip link show Rpf1vf0: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether f6:43:83:ee:26:21 brd ff:ff:ff:ff:ff:ff Rpf1vf1: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 12:b2:54:0e:24:54 brd ff:ff:ff:ff:ff:ff Rpf1vf2: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 4a:12:c4:4c:32:62 brd ff:ff:ff:ff:ff:ff Rpf1vf3: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether ca:cb:68:0e:e2:6e brd ff:ff:ff:ff:ff:ff Rpf2vf0: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 06:cc:ad:b4:f0:93 brd ff:ff:ff:ff:ff:ff :h](h)}(h+List of representor devices on the system::h]h*List of representor devices on the system:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjubj )}(hXV# ip link show Rpf1vf0: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether f6:43:83:ee:26:21 brd ff:ff:ff:ff:ff:ff Rpf1vf1: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 12:b2:54:0e:24:54 brd ff:ff:ff:ff:ff:ff Rpf1vf2: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 4a:12:c4:4c:32:62 brd ff:ff:ff:ff:ff:ff Rpf1vf3: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether ca:cb:68:0e:e2:6e brd ff:ff:ff:ff:ff:ff Rpf2vf0: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 06:cc:ad:b4:f0:93 brd ff:ff:ff:ff:ff:ffh]hXV# ip link show Rpf1vf0: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether f6:43:83:ee:26:21 brd ff:ff:ff:ff:ff:ff Rpf1vf1: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 12:b2:54:0e:24:54 brd ff:ff:ff:ff:ff:ff Rpf1vf2: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 4a:12:c4:4c:32:62 brd ff:ff:ff:ff:ff:ff Rpf1vf3: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether ca:cb:68:0e:e2:6e brd ff:ff:ff:ff:ff:ff Rpf2vf0: mtu 1500 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 1000 link/ether 06:cc:ad:b4:f0:93 brd ff:ff:ff:ff:ff:ff}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMxhjubeh}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]jjuh1hhhhMrhjgubah}(h]h ]h"]h$]h&]uh1j hhhMrhj,hhubh)}(hUTo delete the representors devices from the system. Change the device to legacy mode.h]hUTo delete the representors devices from the system. Change the device to legacy mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,hhubj )}(h`- Change device to legacy mode:: # devlink dev eswitch set pci/0002:1c:00.0 mode legacy h]h)}(hhh]j)}(h\Change device to legacy mode:: # devlink dev eswitch set pci/0002:1c:00.0 mode legacy h](h)}(hChange device to legacy mode::h]hChange device to legacy mode:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj )}(h6# devlink dev eswitch set pci/0002:1c:00.0 mode legacyh]h6# devlink dev eswitch set pci/0002:1c:00.0 mode legacy}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hhhMhj,hhubh)}(hRVU representors can be managed using devlink ports (see :ref:`Documentation/networking/devlink/devlink-port.rst `) interface.h](h9RVU representors can be managed using devlink ports (see }(hj hhhNhNubh)}(hG:ref:`Documentation/networking/devlink/devlink-port.rst `h]hinline)}(hjh]h1Documentation/networking/devlink/devlink-port.rst}(hjhhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc4networking/device_drivers/ethernet/marvell/octeontx2 refdomainj&reftyperef refexplicitrefwarn reftarget devlink_portuh1hhhhMhj ubh ) interface.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj,hhubj )}(hX- Show devlink ports of representors:: # devlink port pci/0002:1c:00.0/0: type eth netdev Rpf1vf0 flavour physical port 0 splittable false pci/0002:1c:00.0/1: type eth netdev Rpf1vf1 flavour pcivf controller 0 pfnum 1 vfnum 1 external false splittable false pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pfnum 1 vfnum 2 external false splittable false pci/0002:1c:00.0/3: type eth netdev Rpf1vf3 flavour pcivf controller 0 pfnum 1 vfnum 3 external false splittable false h]h)}(hhh]j)}(hXShow devlink ports of representors:: # devlink port pci/0002:1c:00.0/0: type eth netdev Rpf1vf0 flavour physical port 0 splittable false pci/0002:1c:00.0/1: type eth netdev Rpf1vf1 flavour pcivf controller 0 pfnum 1 vfnum 1 external false splittable false pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pfnum 1 vfnum 2 external false splittable false pci/0002:1c:00.0/3: type eth netdev Rpf1vf3 flavour pcivf controller 0 pfnum 1 vfnum 3 external false splittable false h](h)}(h$Show devlink ports of representors::h]h#Show devlink ports of representors:}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKubj )}(hX# devlink port pci/0002:1c:00.0/0: type eth netdev Rpf1vf0 flavour physical port 0 splittable false pci/0002:1c:00.0/1: type eth netdev Rpf1vf1 flavour pcivf controller 0 pfnum 1 vfnum 1 external false splittable false pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pfnum 1 vfnum 2 external false splittable false pci/0002:1c:00.0/3: type eth netdev Rpf1vf3 flavour pcivf controller 0 pfnum 1 vfnum 3 external false splittable falseh]hX# devlink port pci/0002:1c:00.0/0: type eth netdev Rpf1vf0 flavour physical port 0 splittable false pci/0002:1c:00.0/1: type eth netdev Rpf1vf1 flavour pcivf controller 0 pfnum 1 vfnum 1 external false splittable false pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pfnum 1 vfnum 2 external false splittable false pci/0002:1c:00.0/3: type eth netdev Rpf1vf3 flavour pcivf controller 0 pfnum 1 vfnum 3 external false splittable false}hj]sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjKubeh}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]jjuh1hhhhMhjDubah}(h]h ]h"]h$]h&]uh1j hhhMhj,hhubeh}(h]jah ]h"]rvu representorsah$]h&]uh1hhhhhhhhM[j)Kubh)}(hhh](h)}(hFunction attributesh]hFunction attributes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hThe RVU representor support function attributes for representors. Port function configuration of the representors are supported through devlink eswitch port.h]hThe RVU representor support function attributes for representors. Port function configuration of the representors are supported through devlink eswitch port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hMAC address setuph]hMAC address setup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hRVU representor driver support devlink port function attr mechanism to setup MAC address. (refer to Documentation/networking/devlink/devlink-port.rst)h]hRVU representor driver support devlink port function attr mechanism to setup MAC address. (refer to Documentation/networking/devlink/devlink-port.rst)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj )}(hX\- To setup MAC address for port 2:: # devlink port function set pci/0002:1c:00.0/2 hw_addr 5c:a1:1b:5e:43:11 # devlink port show pci/0002:1c:00.0/2 pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pfnum 1 vfnum 2 external false splittable false function: hw_addr 5c:a1:1b:5e:43:11 h]h)}(hhh]j)}(hXPTo setup MAC address for port 2:: # devlink port function set pci/0002:1c:00.0/2 hw_addr 5c:a1:1b:5e:43:11 # devlink port show pci/0002:1c:00.0/2 pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pfnum 1 vfnum 2 external false splittable false function: hw_addr 5c:a1:1b:5e:43:11 h](h)}(h!To setup MAC address for port 2::h]h To setup MAC address for port 2:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj )}(hX# devlink port function set pci/0002:1c:00.0/2 hw_addr 5c:a1:1b:5e:43:11 # devlink port show pci/0002:1c:00.0/2 pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pfnum 1 vfnum 2 external false splittable false function: hw_addr 5c:a1:1b:5e:43:11h]hX# devlink port function set pci/0002:1c:00.0/2 hw_addr 5c:a1:1b:5e:43:11 # devlink port show pci/0002:1c:00.0/2 pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pfnum 1 vfnum 2 external false splittable false function: hw_addr 5c:a1:1b:5e:43:11}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hhhMhjhhubeh}(h]mac-address-setupah ]h"]mac address setupah$]h&]uh1hhjhhhhhMubeh}(h]function-attributesah ]h"]function attributesah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h TC offloadh]h TC offload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(h^The rvu representor driver implements support for offloading tc rules using port representors.h]h^The rvu representor driver implements support for offloading tc rules using port representors.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj )}(hX- Drop packets with vlan id 3:: # tc filter add dev Rpf1vf0 protocol 802.1Q parent ffff: flower vlan_id 3 vlan_ethtype ipv4 skip_sw action drop - Redirect packets with vlan id 5 and IPv4 packets to eth1, after stripping vlan header.:: # tc filter add dev Rpf1vf0 ingress protocol 802.1Q flower vlan_id 5 vlan_ethtype ipv4 skip_sw action vlan pop action mirred ingress redirect dev eth1h]h)}(hhh](j)}(hDrop packets with vlan id 3:: # tc filter add dev Rpf1vf0 protocol 802.1Q parent ffff: flower vlan_id 3 vlan_ethtype ipv4 skip_sw action drop h](h)}(hDrop packets with vlan id 3::h]hDrop packets with vlan id 3:}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1ubj )}(ho# tc filter add dev Rpf1vf0 protocol 802.1Q parent ffff: flower vlan_id 3 vlan_ethtype ipv4 skip_sw action droph]ho# tc filter add dev Rpf1vf0 protocol 802.1Q parent ffff: flower vlan_id 3 vlan_ethtype ipv4 skip_sw action drop}hjCsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj1ubeh}(h]h ]h"]h$]h&]uh1jhj.ubj)}(hRedirect packets with vlan id 5 and IPv4 packets to eth1, after stripping vlan header.:: # tc filter add dev Rpf1vf0 ingress protocol 802.1Q flower vlan_id 5 vlan_ethtype ipv4 skip_sw action vlan pop action mirred ingress redirect dev eth1h](h)}(hXRedirect packets with vlan id 5 and IPv4 packets to eth1, after stripping vlan header.::h]hWRedirect packets with vlan id 5 and IPv4 packets to eth1, after stripping vlan header.:}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWubj )}(h# tc filter add dev Rpf1vf0 ingress protocol 802.1Q flower vlan_id 5 vlan_ethtype ipv4 skip_sw action vlan pop action mirred ingress redirect dev eth1h]h# tc filter add dev Rpf1vf0 ingress protocol 802.1Q flower vlan_id 5 vlan_ethtype ipv4 skip_sw action vlan pop action mirred ingress redirect dev eth1}hjisbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjWubeh}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]jjuh1hhhhMhj*ubah}(h]h ]h"]h$]h&]uh1j hhhMhj hhubeh}(h] tc-offloadah ]h"] tc offloadah$]h&]uh1hhhhhhhhMubeh}(h]$marvell-octeontx2-rvu-kernel-driversah ]h"]$marvell octeontx2 rvu kernel driversah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}(overview]jadrivers]j3abasic packet flow]jVadevlink health reporters]jyaquality of service]jarvu representors]jaurefids}nameids}(jjjjj&jjjBjzjwjjjjjP jejjjI jF j jjF jC j j j)jjhjej"jjjjjjjjju nametypes}(jjj&jjzjjjP jjI j jF j j)jhj"jjjjuh}(jhjhjjjBj*jwjIjj}jjjejjjjF jjjS jC jd j jI jj jej jjkjj,jjjjjj u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.