sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftargetA/translations/zh_CN/networking/device_drivers/ethernet/google/gvemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetA/translations/zh_TW/networking/device_drivers/ethernet/google/gvemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetA/translations/it_IT/networking/device_drivers/ethernet/google/gvemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetA/translations/ja_JP/networking/device_drivers/ethernet/google/gvemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetA/translations/ko_KR/networking/device_drivers/ethernet/google/gvemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetA/translations/sp_SP/networking/device_drivers/ethernet/google/gvemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h!SPDX-License-Identifier: GPL-2.0+h]h!SPDX-License-Identifier: GPL-2.0+}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh[/var/lib/git/docbuild/linux/Documentation/networking/device_drivers/ethernet/google/gve.rsthKubhsection)}(hhh](htitle)}(h>Linux kernel driver for Compute Engine Virtual Ethernet (gve):h]h>Linux kernel driver for Compute Engine Virtual Ethernet (gve):}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSupported Hardwareh]hSupported Hardware}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(htThe GVE driver binds to a single PCI device id used by the virtual Ethernet device found in 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]h"]h$]h&]uh1jhjoubj)}(hhh]h)}(h`0x0058`h]j)}(hjh]h0x0058}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjsubj)}(hhh](j)}(hhh]h)}(h Revision IDh]h Revision ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h`0x0`h]j)}(hjh]h0x0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjsubj)}(hhh](j)}(hhh]h)}(h Device Classh]h Device Class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h`0x200`h]j)}(hj h]h0x200}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hEtherneth]hEthernet}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj;ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jqhhubeh}(h]h ]h"]h$]h&]colsKuh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]supported-hardwareah ]h"]supported hardwareah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hPCI Barsh]hPCI Bars}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshhhhhKubh)}(hThe gVNIC PCI device exposes three 32-bit memory BARS: - Bar0 - Device configuration and status registers. - Bar1 - MSI-X vector table - Bar2 - IRQ, RX and TX doorbellsh]hThe gVNIC PCI device exposes three 32-bit memory BARS: - Bar0 - Device configuration and status registers. - Bar1 - MSI-X vector table - Bar2 - IRQ, RX and TX doorbells}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjshhubeh}(h]pci-barsah ]h"]pci barsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDevice Interactionsh]hDevice Interactions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK$ubhdefinition_list)}(hhh]hdefinition_list_item)}(hXSThe driver interacts with the device in the following ways: - Registers - A block of MMIO registers - See gve_register.h for more detail - Admin Queue - See description below - Reset - At any time the device can be reset - Interrupts - See supported interrupts below - Transmit and Receive Queues - See description below h](hterm)}(h;The driver interacts with the device in the following ways:h]h;The driver interacts with the device in the following ways:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK0hjubh definition)}(hhh]h bullet_list)}(hhh](h list_item)}(hLRegisters - A block of MMIO registers - See gve_register.h for more detailh]j)}(hhh]j)}(hJRegisters - A block of MMIO registers - See gve_register.h for more detailh](j)}(h Registersh]h Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK'hjubj)}(hhh]j)}(hhh](j)}(hA block of MMIO registersh]h)}(hjh]hA block of MMIO registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h"See gve_register.h for more detailh]h)}(hj h]h"See gve_register.h for more detail}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h$Admin Queue - See description belowh]j)}(hhh]j)}(h#Admin Queue - See description belowh](j)}(h Admin Queueh]h Admin Queue}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK)hjFubj)}(hhh]j)}(hhh]j)}(hSee description belowh]h)}(hj`h]hSee description below}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hj^ubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]j%j&uh1jhhhK*hjXubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhhhK)hjCubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h,Reset - At any time the device can be reseth]j)}(hhh]j)}(h+Reset - At any time the device can be reseth](j)}(hReseth]hReset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK+hjubj)}(hhh]j)}(hhh]j)}(h#At any time the device can be reseth]h)}(hjh]h#At any time the device can be reset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j%j&uh1jhhhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK+hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h,Interrupts - See supported interrupts belowh]j)}(hhh]j)}(h+Interrupts - See supported interrupts belowh](j)}(h Interruptsh]h Interrupts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK-hjubj)}(hhh]j)}(hhh]j)}(hSee supported interrupts belowh]h)}(hjh]hSee supported interrupts below}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j%j&uh1jhhhK.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK-hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h5Transmit and Receive Queues - See description below h]j)}(hhh]j)}(h4Transmit and Receive Queues - See description below h](j)}(hTransmit and Receive Queuesh]hTransmit and Receive Queues}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK0hjBubj)}(hhh]j)}(hhh]j)}(hSee description below h]h)}(hSee description belowh]hSee description below}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjZubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]j%j&uh1jhhhK0hjTubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhhhK0hj?ubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j%j&uh1jhhhK&hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK0hjubah}(h]h ]h"]h$]h&]uh1jhjhhhNhNubh)}(hhh](h)}(hDescriptor Formatsh]hDescriptor Formats}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK3ubh)}(hGVE supports two descriptor formats: GQI and DQO. These two formats have entirely different descriptors, which will be described below.h]hGVE supports two descriptor formats: GQI and DQO. These two formats have entirely different descriptors, which will be described below.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjhhubeh}(h]descriptor-formatsah ]h"]descriptor formatsah$]h&]uh1hhjhhhhhK3ubh)}(hhh](h)}(hAddressing Modeh]hAddressing Mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK8ubh)}(hGVE supports two addressing modes: QPL and RDA. QPL ("queue-page-list") mode communicates data through a set of pre-registered pages.h]hGVE supports two addressing modes: QPL and RDA. QPL (“queue-page-list”) mode communicates data through a set of pre-registered pages.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjhhubh)}(hFor RDA ("raw DMA addressing") mode, the set of pages is dynamic. Therefore, the packet buffers can be anywhere in guest memory.h]hFor RDA (“raw DMA addressing”) mode, the set of pages is dynamic. Therefore, the packet buffers can be anywhere in guest memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjhhubeh}(h]addressing-modeah ]h"]addressing modeah$]h&]uh1hhjhhhhhK8ubh)}(hhh](h)}(h Registersh]h Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKAubh)}(hAll registers are MMIO.h]hAll registers are MMIO.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjhhubh)}(hThe registers are used for initializing and configuring the device as well as querying device status in response to management interrupts.h]hThe registers are used for initializing and configuring the device as well as querying device status in response to management interrupts.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjhhubeh}(h] registersah ]h"] registersah$]h&]uh1hhjhhhhhKAubh)}(hhh](h)}(h Endiannessh]h Endianness}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhKHubj)}(hhh](j)}(h6Admin Queue messages and registers are all Big Endian.h]h)}(hjOh]h6Admin Queue messages and registers are all Big Endian.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjMubah}(h]h ]h"]h$]h&]uh1jhjJhhhhhNubj)}(h6GQI descriptors and datapath registers are Big Endian.h]h)}(hjfh]h6GQI descriptors and datapath registers are Big Endian.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjdubah}(h]h ]h"]h$]h&]uh1jhjJhhhhhNubj)}(h:DQO descriptors and datapath registers are Little Endian. h]h)}(h9DQO descriptors and datapath registers are Little Endian.h]h9DQO descriptors and datapath registers are Little Endian.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhj{ubah}(h]h ]h"]h$]h&]uh1jhjJhhhhhNubeh}(h]h ]h"]h$]h&]j%j&uh1jhhhKIhj9hhubeh}(h] endiannessah ]h"] endiannessah$]h&]uh1hhjhhhhhKHubh)}(hhh](h)}(hAdmin Queue (AQ)h]hAdmin Queue (AQ)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKNubh)}(hXHThe Admin Queue is a PAGE_SIZE memory block, treated as an array of AQ commands, used by the driver to issue commands to the device and set up resources.The driver and the device maintain a count of how many commands have been submitted and executed. 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