€•SŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ&/translations/zh_CN/misc-devices/uacce”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/zh_TW/misc-devices/uacce”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/it_IT/misc-devices/uacce”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ja_JP/misc-devices/uacce”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ko_KR/misc-devices/uacce”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/sp_SP/misc-devices/uacce”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1h¡hhhžhhŸŒ@/var/lib/git/docbuild/linux/Documentation/misc-devices/uacce.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒIntroduction of Uacce”h]”hŒIntroduction of Uacce”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ paragraph”“”)”}”(hXdUacce (Unified/User-space-access-intended Accelerator Framework) targets to provide Shared Virtual Addressing (SVA) between accelerators and processes. So accelerator can access any data structure of the main cpu. This differs from the data sharing between cpu and io device, which share only data content rather than address. Because of the unified address, hardware and user space of process can share the same virtual address in the communication. Uacce takes the hardware accelerator as a heterogeneous processor, while IOMMU share the same CPU page tables and as a result the same translation from va to pa.”h]”hXdUacce (Unified/User-space-access-intended Accelerator Framework) targets to provide Shared Virtual Addressing (SVA) between accelerators and processes. So accelerator can access any data structure of the main cpu. This differs from the data sharing between cpu and io device, which share only data content rather than address. Because of the unified address, hardware and user space of process can share the same virtual address in the communication. Uacce takes the hardware accelerator as a heterogeneous processor, while IOMMU share the same CPU page tables and as a result the same translation from va to pa.”…””}”(hhËhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhŒ literal_block”“”)”}”(hXÅ __________________________ __________________________ | | | | | User application (CPU) | | Hardware Accelerator | |__________________________| |__________________________| | | | va | va V V __________ __________ | | | | | MMU | | IOMMU | |__________| |__________| | | | | V pa V pa _______________________________________ | | | Memory | |_______________________________________|”h]”hXÅ __________________________ __________________________ | | | | | User application (CPU) | | Hardware Accelerator | |__________________________| |__________________________| | | | va | va V V __________ __________ | | | | | MMU | | IOMMU | |__________| |__________| | | | | V pa V pa _______________________________________ | | | Memory | |_______________________________________|”…””}”hhÛsbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1hÙhŸh³h Khh¶hžhubeh}”(h]”Œintroduction-of-uacce”ah ]”h"]”Œintroduction of uacce”ah$]”h&]”uh1h´hhhžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒ Architecture”h]”hŒ Architecture”…””}”(hhôhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hhñhžhhŸh³h K*ubhÊ)”}”(hŒ|Uacce is the kernel module, taking charge of iommu and address sharing. The user drivers and libraries are called WarpDrive.”h]”hŒ|Uacce is the kernel module, taking charge of iommu and address sharing. The user drivers and libraries are called WarpDrive.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K,hhñhžhubhÊ)”}”(hŒvThe uacce device, built around the IOMMU SVA API, can access multiple address spaces, including the one without PASID.”h]”hŒvThe uacce device, built around the IOMMU SVA API, can access multiple address spaces, including the one without PASID.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K/hhñhžhubhÊ)”}”(hŒ·A virtual concept, queue, is used for the communication. It provides a FIFO-like interface. And it maintains a unified address space between the application and all involved hardware.”h]”hŒ·A virtual concept, queue, is used for the communication. It provides a FIFO-like interface. And it maintains a unified address space between the application and all involved hardware.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K2hhñhžhubhÚ)”}”(hX‹ ___________________ ________________ | | user API | | | WarpDrive library | ------------> | user driver | |___________________| |________________| | | | | | queue fd | | | | | v | ___________________ _________ | | | | | | mmap memory | Other framework | | uacce | | r/w interface | crypto/nic/others | |_________| | |___________________| | | | | | register | register | | | | | | | | _________________ __________ | | | | | | | ------------- | Device Driver | | IOMMU | | |_________________| |__________| | | | | V | ___________________ | | | -------------------------- | Device(Hardware) | |___________________|”h]”hX‹ ___________________ ________________ | | user API | | | WarpDrive library | ------------> | user driver | |___________________| |________________| | | | | | queue fd | | | | | v | ___________________ _________ | | | | | | mmap memory | Other framework | | uacce | | r/w interface | crypto/nic/others | |_________| | |___________________| | | | | | register | register | | | | | | | | _________________ __________ | | | | | | | ------------- | Device Driver | | IOMMU | | |_________________| |__________| | | | | V | ___________________ | | | -------------------------- | Device(Hardware) | |___________________|”…””}”hj,sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1hÙhŸh³h K8hhñhžhubeh}”(h]”Œ architecture”ah ]”h"]”Œ architecture”ah$]”h&]”uh1h´hhhžhhŸh³h K*ubhµ)”}”(hhh]”(hº)”}”(hŒHow does it work”h]”hŒHow does it work”…””}”(hjEhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjBhžhhŸh³h KXubhÊ)”}”(hŒ,Uacce uses mmap and IOMMU to play the trick.”h]”hŒ,Uacce uses mmap and IOMMU to play the trick.”…””}”(hjShžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KZhjBhžhubhÊ)”}”(hXˆUacce creates a chrdev for every device registered to it. New queue is created when user application open the chrdev. The file descriptor is used as the user handle of the queue. The accelerator device present itself as an Uacce object, which exports as a chrdev to the user space. The user application communicates with the hardware by ioctl (as control path) or share memory (as data path).”h]”hXˆUacce creates a chrdev for every device registered to it. New queue is created when user application open the chrdev. The file descriptor is used as the user handle of the queue. The accelerator device present itself as an Uacce object, which exports as a chrdev to the user space. The user application communicates with the hardware by ioctl (as control path) or share memory (as data path).”…””}”(hjahžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K\hjBhžhubhÊ)”}”(hŒjThe control path to the hardware is via file operation, while data path is via mmap space of the queue fd.”h]”hŒjThe control path to the hardware is via file operation, while data path is via mmap space of the queue fd.”…””}”(hjohžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KchjBhžhubhÊ)”}”(hŒThe queue file address space:”h]”hŒThe queue file address space:”…””}”(hj}hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KfhjBhžhubhÚ)”}”(hŒÉ /** * enum uacce_qfrt: qfrt type * @UACCE_QFRT_MMIO: device mmio region * @UACCE_QFRT_DUS: device user share region */ enum uacce_qfrt { UACCE_QFRT_MMIO = 0, UACCE_QFRT_DUS = 1, };”h]”hŒÉ /** * enum uacce_qfrt: qfrt type * @UACCE_QFRT_MMIO: device mmio region * @UACCE_QFRT_DUS: device user share region */ enum uacce_qfrt { UACCE_QFRT_MMIO = 0, UACCE_QFRT_DUS = 1, };”…””}”hj‹sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1hÙhŸh³h KjhjBhžhubhÊ)”}”(hŒ~All regions are optional and differ from device type to type. Each region can be mmapped only once, otherwise -EEXIST returns.”h]”hŒ~All regions are optional and differ from device type to type. Each region can be mmapped only once, otherwise -EEXIST returns.”…””}”(hj™hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KthjBhžhubhÊ)”}”(hŒ¬The device mmio region is mapped to the hardware mmio space. It is generally used for doorbell or other notification to the hardware. It is not fast enough as data channel.”h]”hŒ¬The device mmio region is mapped to the hardware mmio space. It is generally used for doorbell or other notification to the hardware. It is not fast enough as data channel.”…””}”(hj§hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KwhjBhžhubhÊ)”}”(hŒ[The device user share region is used for share data buffer between user process and device.”h]”hŒ[The device user share region is used for share data buffer between user process and device.”…””}”(hjµhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K{hjBhžhubeh}”(h]”Œhow-does-it-work”ah ]”h"]”Œhow does it work”ah$]”h&]”uh1h´hhhžhhŸh³h KXubhµ)”}”(hhh]”(hº)”}”(hŒThe Uacce register API”h]”hŒThe Uacce register API”…””}”(hjÎhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjËhžhhŸh³h K€ubhÊ)”}”(hŒ'The register API is defined in uacce.h.”h]”hŒ'The register API is defined in uacce.h.”…””}”(hjÜhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K‚hjËhžhubhÚ)”}”(hŒrstruct uacce_interface { char name[UACCE_MAX_NAME_SIZE]; unsigned int flags; const struct uacce_ops *ops; };”h]”hŒrstruct uacce_interface { char name[UACCE_MAX_NAME_SIZE]; unsigned int flags; const struct uacce_ops *ops; };”…””}”hjêsbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1hÙhŸh³h K†hjËhžhubhÊ)”}”(hŒ@According to the IOMMU capability, uacce_interface flags can be:”h]”hŒ@According to the IOMMU capability, uacce_interface flags can be:”…””}”(hjøhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KŒhjËhžhubhÚ)”}”(hX²/** * UACCE Device flags: * UACCE_DEV_SVA: Shared Virtual Addresses * Support PASID * Support device page faults (PCI PRI or SMMU Stall) */ #define UACCE_DEV_SVA BIT(0) struct uacce_device *uacce_alloc(struct device *parent, struct uacce_interface *interface); int uacce_register(struct uacce_device *uacce); void uacce_remove(struct uacce_device *uacce);”h]”hX²/** * UACCE Device flags: * UACCE_DEV_SVA: Shared Virtual Addresses * Support PASID * Support device page faults (PCI PRI or SMMU Stall) */ #define UACCE_DEV_SVA BIT(0) struct uacce_device *uacce_alloc(struct device *parent, struct uacce_interface *interface); int uacce_register(struct uacce_device *uacce); void uacce_remove(struct uacce_device *uacce);”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1hÙhŸh³h KhjËhžhubhÊ)”}”(hŒuacce_register results can be:”h]”hŒuacce_register results can be:”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhjËhžhubhŒenumerated_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ2If uacce module is not compiled, ERR_PTR(-ENODEV) ”h]”hÊ)”}”(hŒ1If uacce module is not compiled, ERR_PTR(-ENODEV)”h]”hŒ1If uacce module is not compiled, ERR_PTR(-ENODEV)”…””}”(hj-hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KŸhj)ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj$hžhhŸh³h Nubj()”}”(hŒSucceed with the desired flags ”h]”hÊ)”}”(hŒSucceed with the desired flags”h]”hŒSucceed with the desired flags”…””}”(hjEhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K¡hjAubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj$hžhhŸh³h Nubj()”}”(hŒ/Succeed with the negotiated flags, for example ”h]”hÊ)”}”(hŒ.Succeed with the negotiated flags, for example”h]”hŒ.Succeed with the negotiated flags, for example”…””}”(hj]hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K£hjYubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj$hžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œ loweralpha”Œprefix”hŒsuffix”Œ.”uh1j"hjËhžhhŸh³h KŸubhŒ block_quote”“”)”}”(hŒ™uacce_interface.flags = UACCE_DEV_SVA but uacce->flags = ~UACCE_DEV_SVA So user driver need check return value as well as the negotiated uacce->flags. ”h]”(hÊ)”}”(hŒGuacce_interface.flags = UACCE_DEV_SVA but uacce->flags = ~UACCE_DEV_SVA”h]”hŒGuacce_interface.flags = UACCE_DEV_SVA but uacce->flags = ~UACCE_DEV_SVA”…””}”(hj‚hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K¥hj~ubhÊ)”}”(hŒNSo user driver need check return value as well as the negotiated uacce->flags.”h]”hŒNSo user driver need check return value as well as the negotiated uacce->flags.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K§hj~ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j|hŸh³h K¥hjËhžhubeh}”(h]”Œthe-uacce-register-api”ah ]”h"]”Œthe uacce register api”ah$]”h&]”uh1h´hhhžhhŸh³h K€ubhµ)”}”(hhh]”(hº)”}”(hŒThe user driver”h]”hŒThe user driver”…””}”(hj¯hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj¬hžhhŸh³h K«ubhÊ)”}”(hŒûThe queue file mmap space will need a user driver to wrap the communication protocol. Uacce provides some attributes in sysfs for the user driver to match the right accelerator accordingly. More details in Documentation/ABI/testing/sysfs-driver-uacce.”h]”hŒûThe queue file mmap space will need a user driver to wrap the communication protocol. Uacce provides some attributes in sysfs for the user driver to match the right accelerator accordingly. More details in Documentation/ABI/testing/sysfs-driver-uacce.”…””}”(hj½hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K­hj¬hžhubeh}”(h]”Œthe-user-driver”ah ]”h"]”Œthe user driver”ah$]”h&]”uh1h´hhhžhhŸh³h K«ubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jöŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(hîhëj?j<jÈjÅj©j¦jÐjÍuŒ nametypes”}”(hî‰j?‰jȉj©‰jЉuh}”(hëh¶j<hñjÅjBj¦jËjÍj¬uŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nhžhub.