isphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget2/translations/zh_CN/misc-devices/spear-pcie-gadgetmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/zh_TW/misc-devices/spear-pcie-gadgetmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/it_IT/misc-devices/spear-pcie-gadgetmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/ja_JP/misc-devices/spear-pcie-gadgetmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/ko_KR/misc-devices/spear-pcie-gadgetmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/sp_SP/misc-devices/spear-pcie-gadgetmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhL/var/lib/git/docbuild/linux/Documentation/misc-devices/spear-pcie-gadget.rsthKubhsection)}(hhh](htitle)}(hSpear PCIe Gadget Driverh]hSpear PCIe Gadget Driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hAuthorh]hAuthor}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h)Pratyush Anand (pratyush.anand@gmail.com)h](hPratyush Anand (}(hhhhhNhNubh reference)}(hpratyush.anand@gmail.comh]hpratyush.anand@gmail.com}(hhhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:pratyush.anand@gmail.comuh1hhhubh)}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubeh}(h]authorah ]h"]authorah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hLocationh]hLocation}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK ubh)}(h#driver/misc/spear13xx_pcie_gadget.ch]h#driver/misc/spear13xx_pcie_gadget.c}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjhhubeh}(h]locationah ]h"]locationah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hSupported Chip:h]hSupported Chip:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhKubh)}(hSPEAr1300 SPEAr1310h]hSPEAr1300 SPEAr1310}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj/hhubeh}(h]supported-chipah ]h"]supported chip:ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hMenuconfig option:h]hMenuconfig option:}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhhhhhKubhdefinition_list)}(hhh]hdefinition_list_item)}(hODevice Drivers Misc devices PCIe gadget support for SPEAr13XX platform h](hterm)}(hDevice Driversh]hDevice Drivers}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jrhhhKhjnubh definition)}(hhh]jh)}(hhh]jm)}(h8Misc devices PCIe gadget support for SPEAr13XX platform h](js)}(h Misc devicesh]h Misc devices}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhhhKhjubj)}(hhh]h)}(h*PCIe gadget support for SPEAr13XX platformh]h*PCIe gadget support for SPEAr13XX platform}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jlhhhKhjubah}(h]h ]h"]h$]h&]uh1jghjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jlhhhKhjiubah}(h]h ]h"]h$]h&]uh1jghjVhhhNhNubeh}(h]menuconfig-optionah ]h"]menuconfig option:ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hpurposeh]hpurpose}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX0This driver has several nodes which can be read/written by configfs interface. Its main purpose is to configure selected dual mode PCIe controller as device and then program its various registers to configure it as a particular device type. This driver can be used to show spear's PCIe device capability.h]hX2This driver has several nodes which can be read/written by configfs interface. Its main purpose is to configure selected dual mode PCIe controller as device and then program its various registers to configure it as a particular device type. This driver can be used to show spear’s PCIe device capability.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]purposeah ]h"]purposeah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDescription of different nodes:h]hDescription of different nodes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK"ubh)}(hhh](h)}(hread behavior of nodes:h]hread behavior of nodes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK%ubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j,hj)ubj-)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1j,hj)ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hlinkh]hlink}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjNubah}(h]h ]h"]h$]h&]uh1jLhjIubjM)}(hhh]h)}(hgives ltssm status.h]hgives ltssm status.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjeubah}(h]h ]h"]h$]h&]uh1jLhjIubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(hint_typeh]hint_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(htype of supported interrupth]htype of supported interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(h no_of_msih]h no_of_msi}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(hYzero if MSI is not enabled by host. A positive value is the number of MSI vector granted.h]hYzero if MSI is not enabled by host. A positive value is the number of MSI vector granted.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(h vendor_idh]h vendor_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(h"returns programmed vendor id (hex)h]h"returns programmed vendor id (hex)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hj ubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(h device_idh]h device_id}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hj*ubah}(h]h ]h"]h$]h&]uh1jLhj'ubjM)}(hhh]h)}(h!returns programmed device id(hex)h]h!returns programmed device id(hex)}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjAubah}(h]h ]h"]h$]h&]uh1jLhj'ubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(h bar0_size:h]h bar0_size:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjaubah}(h]h ]h"]h$]h&]uh1jLhj^ubjM)}(hhh]h)}(hreturns size of bar0 in hex.h]hreturns size of bar0 in hex.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjxubah}(h]h ]h"]h$]h&]uh1jLhj^ubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(h bar0_addressh]h bar0_address}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(h+returns address of bar0 mapped area in hex.h]h+returns address of bar0 mapped area in hex.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(hbar0_rw_offseth]hbar0_rw_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(h=returns offset of bar0 for which bar0_data will return value.h]h=returns offset of bar0 for which bar0_data will return value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(h bar0_datah]h bar0_data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(hreturns data at bar0_rw_offset.h]hreturns data at bar0_rw_offset.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjDubeh}(h]h ]h"]h$]h&]uh1jBhj)ubeh}(h]h ]h"]h$]h&]colsKuh1j'hj$ubah}(h]h ]h"]h$]h&]uh1j"hjhhhhhNubeh}(h]read-behavior-of-nodesah ]h"]read behavior of nodes:ah$]h&]uh1hhjhhhhhK%ubh)}(hhh](h)}(hwrite behavior of nodes:h]hwrite behavior of nodes:}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhhhhhK5ubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j,hjiubj-)}(hhh]h}(h]h ]h"]h$]h&]colwidthK@uh1j,hjiubjC)}(hhh](jH)}(hhh](jM)}(hhh]h)}(hlinkh]hlink}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(h(write UP to enable ltsmm DOWN to disableh]h(write UP to enable ltsmm DOWN to disable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjubjH)}(hhh](jM)}(hhh]h)}(hint_typeh]hint_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(hwrite interrupt type to be configured and (int_type could be INTA, MSI or NO_INT). Select MSI only when you have programmed no_of_msi node.h]hwrite interrupt type to be configured and (int_type could be INTA, MSI or NO_INT). Select MSI only when you have programmed no_of_msi node.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjubjH)}(hhh](jM)}(hhh]h)}(h no_of_msih]h no_of_msi}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjbubah}(h]h ]h"]h$]h&]uh1jLhj_ubjM)}(hhh]h)}(hwrite MSI vector to be sent.h]hwrite MSI vector to be sent.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjyubah}(h]h ]h"]h$]h&]uh1jLhj_ubeh}(h]h ]h"]h$]h&]uh1jGhjubjH)}(hhh](jM)}(hhh]h)}(h vendor_idh]h vendor_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(h&write vendor id(hex) to be programmed.h]h&write vendor id(hex) to be programmed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjubjH)}(hhh](jM)}(hhh]h)}(h device_idh]h device_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(h&write device id(hex) to be programmed.h]h&write device id(hex) to be programmed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjubjH)}(hhh](jM)}(hhh]h)}(h bar0_sizeh]h bar0_size}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(hAwrite size of bar0 in hex. default bar0 size is 1000 (hex) bytes.h]hAwrite size of bar0 in hex. default bar0 size is 1000 (hex) bytes.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjubjH)}(hhh](jM)}(hhh]h)}(h bar0_addressh]h bar0_address}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChj>ubah}(h]h ]h"]h$]h&]uh1jLhj;ubjM)}(hhh]h)}(hwrite address of bar0 mapped area in hex. (default mapping of bar0 is SYSRAM1(E0800000). Always program bar size before bar address. Kernel might modify bar size and address for alignment, so read back bar size and address after writing to cross check.h]hwrite address of bar0 mapped area in hex. (default mapping of bar0 is SYSRAM1(E0800000). Always program bar size before bar address. Kernel might modify bar size and address for alignment, so read back bar size and address after writing to cross check.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjUubah}(h]h ]h"]h$]h&]uh1jLhj;ubeh}(h]h ]h"]h$]h&]uh1jGhjubjH)}(hhh](jM)}(hhh]h)}(hbar0_rw_offseth]hbar0_rw_offset}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjuubah}(h]h ]h"]h$]h&]uh1jLhjrubjM)}(hhh]h)}(h;write offset of bar0 for which bar0_data will write value.h]h;write offset of bar0 for which bar0_data will write value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjubah}(h]h ]h"]h$]h&]uh1jLhjrubeh}(h]h ]h"]h$]h&]uh1jGhjubjH)}(hhh](jM)}(hhh]h)}(h bar0_datah]h bar0_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(h+write data to be written at bar0_rw_offset.h]h+write data to be written at bar0_rw_offset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjubeh}(h]h ]h"]h$]h&]uh1jBhjiubeh}(h]h ]h"]h$]h&]colsKuh1j'hjfubah}(h]h ]h"]h$]h&]uh1j"hjUhhhhhNubeh}(h]write-behavior-of-nodesah ]h"]write behavior of nodes:ah$]h&]uh1hhjhhhhhK5ubeh}(h]description-of-different-nodesah ]h"]description of different nodes:ah$]h&]uh1hhhhhhhhK"ubh)}(hhh](h)}(hNode programming exampleh]hNode programming example}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKLubh)}(hProgram all PCIe registers in such a way that when this device is connected to the PCIe host, then host sees this device as 1MB RAM.h]hProgram all PCIe registers in such a way that when this device is connected to the PCIe host, then host sees this device as 1MB RAM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjhhubh literal_block)}(h#mount -t configfs none /Configh]h#mount -t configfs none /Config}hj$sbah}(h]h ]h"]h$]h&]hhuh1j"hhhKShjhhubh)}(h For nth PCIe Device Controller::h]hFor nth PCIe Device Controller:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjhhubj#)}(h# cd /config/pcie_gadget.n/h]h# cd /config/pcie_gadget.n/}hj@sbah}(h]h ]h"]h$]h&]hhuh1j"hhhKWhjhhubh)}(hKNow you have all the nodes in this directory. program vendor id as 0x104a::h]hJNow you have all the nodes in this directory. program vendor id as 0x104a:}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjhhubj#)}(h# echo 104A >> vendor_idh]h# echo 104A >> vendor_id}hj\sbah}(h]h ]h"]h$]h&]hhuh1j"hhhK\hjhhubh)}(hprogram device id as 0xCD80::h]hprogram device id as 0xCD80:}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjhhubj#)}(h# echo CD80 >> device_idh]h# echo CD80 >> device_id}hjxsbah}(h]h ]h"]h$]h&]hhuh1j"hhhK`hjhhubh)}(hprogram BAR0 size as 1MB::h]hprogram BAR0 size as 1MB:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjhhubj#)}(h# echo 100000 >> bar0_sizeh]h# echo 100000 >> bar0_size}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKdhjhhubh)}(h check for programmed bar0 size::h]hcheck for programmed bar0 size:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjhhubj#)}(h# cat bar0_sizeh]h# cat bar0_size}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhhjhhubh)}(hXIProgram BAR0 Address as DDR (0x2100000). This is the physical address of memory, which is to be made visible to PCIe host. Similarly any other peripheral can also be made visible to PCIe host. E.g., if you program base address of UART as BAR0 address then when this device will be connected to a host, it will be visible as UART.h]hXIProgram BAR0 Address as DDR (0x2100000). This is the physical address of memory, which is to be made visible to PCIe host. Similarly any other peripheral can also be made visible to PCIe host. E.g., if you program base address of UART as BAR0 address then when this device will be connected to a host, it will be visible as UART.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjhhubj#)}(h# echo 2100000 >> bar0_addressh]h# echo 2100000 >> bar0_address}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKrhjhhubh)}(hprogram interrupt type : INTA::h]hprogram interrupt type : INTA:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjhhubj#)}(h# echo INTA >> int_typeh]h# echo INTA >> int_type}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKvhjhhubh)}(hgo for link up now::h]hgo for link up now:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjhhubj#)}(h# echo UP >> linkh]h# echo UP >> link}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKzhjhhubh)}(hIt will have to be insured that, once link up is done on gadget, then only host is initialized and start to search PCIe devices on its port.h]hIt will have to be insured that, once link up is done on gadget, then only host is initialized and start to search PCIe devices on its port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjhhubj#)}(h#/*wait till link is up*/ # cat linkh]h#/*wait till link is up*/ # cat link}hj sbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubh)}(hWait till it returns UP.h]hWait till it returns UP.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hTo assert INTA::h]hTo assert INTA:}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj#)}(h# echo 1 >> intah]h# echo 1 >> inta}hjJsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubh)}(hTo de-assert INTA::h]hTo de-assert INTA:}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj#)}(h# echo 0 >> intah]h# echo 0 >> inta}hjfsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubh)}(hKif MSI is to be used as interrupt, program no of msi vector needed (say4)::h]hJif MSI is to be used as interrupt, program no of msi vector needed (say4):}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj#)}(h# echo 4 >> no_of_msih]h# echo 4 >> no_of_msi}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubh)}(hselect MSI as interrupt type::h]hselect MSI as interrupt type:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj#)}(h# echo MSI >> int_typeh]h# echo MSI >> int_type}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubh)}(hgo for link up now::h]hgo for link up now:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj#)}(h# echo UP >> linkh]h# echo UP >> link}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubh)}(hwait till link is up::h]hwait till link is up:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj#)}(h # cat linkh]h # cat link}hjsbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubh)}(hdAn application can repetitively read this node till link is found UP. It can sleep between two read.h]hdAn application can repetitively read this node till link is found UP. It can sleep between two read.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hwait till msi is enabled::h]hwait till msi is enabled:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj#)}(h# cat no_of_msih]h# cat no_of_msi}hj sbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubh)}(h0Should return 4 (number of requested MSI vector)h]h0Should return 4 (number of requested MSI vector)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hto send msi vector 2::h]hto send msi vector 2:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj#)}(h# echo 2 >> send_msi # cd -h]h# echo 2 >> send_msi # cd -}hj* sbah}(h]h ]h"]h$]h&]hhuh1j"hhhKhjhhubeh}(h]node-programming-exampleah ]h"]node programming exampleah$]h&]uh1hhhhhhhhKLubeh}(h]spear-pcie-gadget-driverah ]h"]spear pcie gadget driverah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjLfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jE jB jjj,j)jSjPjjjjjjjRjOjjj= j: u nametypes}(jE jj,jSjjjjRjj= uh}(jB hjhj)jjPj/jjVjjjjjOjjjUj: ju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.