sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget(/translations/zh_CN/misc-devices/amd-sbimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/zh_TW/misc-devices/amd-sbimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/it_IT/misc-devices/amd-sbimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/ja_JP/misc-devices/amd-sbimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/ko_KR/misc-devices/amd-sbimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/pt_BR/misc-devices/amd-sbimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/sp_SP/misc-devices/amd-sbimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhB/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi.rsthKubhsection)}(hhh](htitle)}(hAMD SIDE BAND interfaceh]hAMD SIDE BAND interface}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXjSome AMD Zen based processors supports system management functionality via side-band interface (SBI) called Advanced Platform Management Link (APML). APML is an I2C/I3C based 2-wire processor target interface. APML is used to communicate with the Remote Management Interface (SB Remote Management Interface (SB-RMI) and SB Temperature Sensor Interface (SB-TSI)).h]hXjSome AMD Zen based processors supports system management functionality via side-band interface (SBI) called Advanced Platform Management Link (APML). APML is an I2C/I3C based 2-wire processor target interface. APML is used to communicate with the Remote Management Interface (SB Remote Management Interface (SB-RMI) and SB Temperature Sensor Interface (SB-TSI)).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hMore details on the interface can be found in chapter "5 Advanced Platform Management Link (APML)" of the family/model PPR [1]_.h](hMore details on the interface can be found in chapter “5 Advanced Platform Management Link (APML)” of the family/model PPR }(hhhhhNhNubhfootnote_reference)}(h[1]_h]h1}(hhhhhNhNubah}(h]id1ah ]h"]h$]h&]refidid2docnamemisc-devices/amd-sbiuh1hhhresolvedKubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhfootnote)}(h2https://docs.amd.com/v/u/en-US/55898_B1_pub_0_50 h](hlabel)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h0https://docs.amd.com/v/u/en-US/55898_B1_pub_0_50h]h reference)}(hj-h]h0https://docs.amd.com/v/u/en-US/55898_B1_pub_0_50}(hj1hhhNhNubah}(h]h ]h"]h$]h&]refurij-uh1j/hj+ubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]jah ]h"]1ah$]h&]jajj uh1jhhhKhhhhj Kubh)}(hhh](h)}(h SBRMI deviceh]h SBRMI device}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhKubh)}(hapml_sbrmi driver under the drivers/misc/amd-sbi creates miscdevice /dev/sbrmi-* to let user space programs run APML mailbox, CPUID, MCAMSR and register xfer commands.h]hapml_sbrmi driver under the drivers/misc/amd-sbi creates miscdevice /dev/sbrmi-* to let user space programs run APML mailbox, CPUID, MCAMSR and register xfer commands.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLhhubh)}(hRegister sets is common across APML protocols. IOCTL is providing synchronization among protocols as transactions may create race condition.h]hRegister sets is common across APML protocols. IOCTL is providing synchronization among protocols as transactions may create race condition.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLhhubh literal_block)}(h]$ ls -al /dev/sbrmi-3c crw------- 1 root root 10, 53 Jul 10 11:13 /dev/sbrmi-3ch]h]$ ls -al /dev/sbrmi-3c crw------- 1 root root 10, 53 Jul 10 11:13 /dev/sbrmi-3c}hj{sbah}(h]h ]h"]h$]h&]hhƌforcelanguagebashhighlight_args}uh1jyhhhKhjLhhubh)}(hyapml_sbrmi driver registers hwmon sensors for monitoring power_cap_max, current power consumption and managing power_cap.h]hyapml_sbrmi driver registers hwmon sensors for monitoring power_cap_max, current power consumption and managing power_cap.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjLhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hCharacteristics of the dev node: * Differnet xfer protocols are defined: * Mailbox * CPUID * MCA_MSR * Register xfer h](hterm)}(h Characteristics of the dev node:h]h Characteristics of the dev node:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK,hjubh definition)}(hhh]h bullet_list)}(hhh]h list_item)}(hfDiffernet xfer protocols are defined: * Mailbox * CPUID * MCA_MSR * Register xfer h]j)}(hhh]j)}(hRDiffernet xfer protocols are defined: * Mailbox * CPUID * MCA_MSR * Register xfer h](j)}(h%Differnet xfer protocols are defined:h]h%Differnet xfer protocols are defined:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK,hjubj)}(hhh]j)}(hhh](j)}(hMailboxh]h)}(hjh]hMailbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hCPUIDh]h)}(hjh]hCPUID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hMCA_MSRh]h)}(hjh]hMCA_MSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hRegister xfer h]h)}(h Register xferh]h Register xfer}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet*uh1jhhhK)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jEjFuh1jhhhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK,hjubj)}(hAccess restrictions: * Only root user is allowed to open the file. * APML Mailbox messages and Register xfer access are read-write, * CPUID and MCA_MSR access is read-only. h](j)}(hAccess restrictions:h]hAccess restrictions:}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK1hjqubj)}(hhh]j)}(hhh](j)}(h+Only root user is allowed to open the file.h]h)}(hjh]h+Only root user is allowed to open the file.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h>APML Mailbox messages and Register xfer access are read-write,h]h)}(hjh]h>APML Mailbox messages and Register xfer access are read-write,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h'CPUID and MCA_MSR access is read-only. h]h)}(h&CPUID and MCA_MSR access is read-only.h]h&CPUID and MCA_MSR access is read-only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jEjFuh1jhhhK/hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhhhK1hjhhubeh}(h]h ]h"]h$]h&]uh1jhjLhhhNhNubeh}(h] sbrmi-deviceah ]h"] sbrmi deviceah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h SBTSI deviceh]h SBTSI device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK4ubh)}(hsbtsi driver under the drivers/misc/amd-sbi creates miscdevice /dev/sbtsi-* to let user space programs run APML TSI register transfer commands.h]hsbtsi driver under the drivers/misc/amd-sbi creates miscdevice /dev/sbtsi-* to let user space programs run APML TSI register transfer commands.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjhhubh)}(hThe driver supports both I2C and I3C transports for SB-TSI targets. The transport is selected by the bus where the device is enumerated.h]hThe driver supports both I2C and I3C transports for SB-TSI targets. The transport is selected by the bus where the device is enumerated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjhhubj)}(hhh]j)}(hfMisc device: * In 1P socket 0: /dev/sbtsi-4c * In 2P socket 0: /dev/sbtsi-4c, socket 1: /dev/sbtsi-48 h](j)}(h Misc device:h]h Misc device:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK?hjubj)}(hhh]j)}(hhh](j)}(hIn 1P socket 0: /dev/sbtsi-4ch]h)}(hj9h]hIn 1P socket 0: /dev/sbtsi-4c}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hj7ubah}(h]h ]h"]h$]h&]uh1jhj4ubj)}(h7In 2P socket 0: /dev/sbtsi-4c, socket 1: /dev/sbtsi-48 h]h)}(h6In 2P socket 0: /dev/sbtsi-4c, socket 1: /dev/sbtsi-48h]h6In 2P socket 0: /dev/sbtsi-4c, socket 1: /dev/sbtsi-48}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjNubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]jEjFuh1jhhhK>hj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK?hjubah}(h]h ]h"]h$]h&]uh1jhjhhhNhNubjz)}(h]$ ls -al /dev/sbtsi-4c crw------- 1 root root 10, 116 Apr 2 05:22 /dev/sbtsi-4ch]h]$ ls -al /dev/sbtsi-4c crw------- 1 root root 10, 116 Apr 2 05:22 /dev/sbtsi-4c}hj~sbah}(h]h ]h"]h$]h&]hhjjbashj}uh1jyhhhKAhjhhubj)}(hhh]j)}(hvAccess restrictions: * Only root user is allowed to open the file. * APML TSI Register transfer access is read-write. h](j)}(hAccess restrictions:h]hAccess restrictions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKIhjubj)}(hhh]j)}(hhh](j)}(h+Only root user is allowed to open the file.h]h)}(hjh]h+Only root user is allowed to open the file.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h1APML TSI Register transfer access is read-write. h]h)}(h0APML TSI Register transfer access is read-write.h]h0APML TSI Register transfer access is read-write.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jEjFuh1jhhhKHhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKIhjubah}(h]h ]h"]h$]h&]uh1jhjhhhNhNubeh}(h] sbtsi-deviceah ]h"] sbtsi deviceah$]h&]uh1hhhhhhhhK4ubh)}(hhh](h)}(hSBTSI hwmon interfaceh]hSBTSI hwmon interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKLubh)}(hXThe sbtsi_temp auxiliary driver binds to the auxiliary device published by the core sbtsi driver on the auxiliary bus. The auxiliary device is named amd-sbtsi.temp-sensor., where is the device's transfer address: the client address for I2C, or the assigned-address for I3C.h]hXThe sbtsi_temp auxiliary driver binds to the auxiliary device published by the core sbtsi driver on the auxiliary bus. The auxiliary device is named amd-sbtsi.temp-sensor., where is the device’s transfer address: the client address for I2C, or the assigned-address for I3C.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjhhubh)}(hXNote that the auxiliary bus formats in decimal, whereas the /dev/sbtsi-* misc node formats its address in hex. The two therefore differ for the same device: an I2C/I3C sensor at address 0x4c appears as the misc node /dev/sbtsi-4c and the auxiliary device amd-sbtsi.temp-sensor.76.h]hXNote that the auxiliary bus formats in decimal, whereas the /dev/sbtsi-* misc node formats its address in hex. The two therefore differ for the same device: an I2C/I3C sensor at address 0x4c appears as the misc node /dev/sbtsi-4c and the auxiliary device amd-sbtsi.temp-sensor.76.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjhhubh)}(hIt registers a hwmon device, providing a standard Linux hwmon interface for reading CPU temperature and managing temperature limits.h]hIt registers a hwmon device, providing a standard Linux hwmon interface for reading CPU temperature and managing temperature limits.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjhhubh)}(hmThe hwmon device appears under ``/sys/class/hwmon/`` when both ``sbtsi.ko`` and ``sbtsi_temp.ko`` are loaded.h](hThe hwmon device appears under }(hj3hhhNhNubhliteral)}(h``/sys/class/hwmon/``h]h/sys/class/hwmon/}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj3ubh when both }(hj3hhhNhNubj<)}(h ``sbtsi.ko``h]hsbtsi.ko}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj3ubh and }(hj3hhhNhNubj<)}(h``sbtsi_temp.ko``h]h sbtsi_temp.ko}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj3ubh are loaded.}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK\hjhhubh)}(hVerify auxiliary bus device::h]hVerify auxiliary bus device:}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjhhubjz)}(hdls /sys/bus/auxiliary/devices/ # e.g. amd-sbtsi.temp-sensor.76 for an I2C/I3C sensor at address 0x4ch]hdls /sys/bus/auxiliary/devices/ # e.g. amd-sbtsi.temp-sensor.76 for an I2C/I3C sensor at address 0x4c}hjsbah}(h]h ]h"]h$]h&]hhuh1jyhhhKahjhhubh)}(hExample usage::h]hExample usage:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjhhubjz)}(h# Read current temperature cat /sys/class/hwmon/hwmon/temp1_input # Set high temperature limit to 70 °C echo 70000 > /sys/class/hwmon/hwmon/temp1_max # Verify cat /sys/class/hwmon/hwmon/temp1_maxh]h# Read current temperature cat /sys/class/hwmon/hwmon/temp1_input # Set high temperature limit to 70 °C echo 70000 > /sys/class/hwmon/hwmon/temp1_max # Verify cat /sys/class/hwmon/hwmon/temp1_max}hjsbah}(h]h ]h"]h$]h&]hhuh1jyhhhKfhjhhubeh}(h]sbtsi-hwmon-interfaceah ]h"]sbtsi hwmon interfaceah$]h&]uh1hhhhhhhhKLubh)}(hhh](h)}(h Driver IOCTLsh]h Driver IOCTLs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKpubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleSBRMI_IOCTL_MBOX_CMD (C macro)c.SBRMI_IOCTL_MBOX_CMDhNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(hSBRMI_IOCTL_MBOX_CMDh]hdesc_signature_line)}(hSBRMI_IOCTL_MBOX_CMDh]h desc_name)}(hSBRMI_IOCTL_MBOX_CMDh]h desc_sig_name)}(hjh]hSBRMI_IOCTL_MBOX_CMD}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjhhhhhKrubah}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1jsphinx_line_type declaratorhjhhhhhKrubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhhhKrhjhhubh desc_content)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhhhKrubeh}(h]h ](cmacroeh"]h$]h&]domainj,objtypej-desctypej-noindex noindexentrynocontentsentryuh1jhhhjhNhNubh)}(h**Parameters**h]hstrong)}(hj9h]h Parameters}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj7ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:115: ./include/uapi/misc/amd-apml.hhKYhjhhubj)}(hhh]j)}(h**struct** apml_mbox_msg Pointer to the :c:type:`struct apml_mbox_msg ` that will contain the protocol information h](j)}(h**struct** apml_mbox_msgh](j<)}(h **struct**h]hstruct}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hjXubh apml_mbox_msg}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:115: ./include/uapi/misc/amd-apml.hhK]hjTubj)}(hhh]h)}(hhPointer to the :c:type:`struct apml_mbox_msg ` that will contain the protocol informationh](hPointer to the }(hjxhhhNhNubh)}(h.:c:type:`struct apml_mbox_msg `h]j<)}(hjh]hstruct apml_mbox_msg}(hjhhhNhNubah}(h]h ](xrefj,c-typeeh"]h$]h&]uh1j;hjubah}(h]h ]h"]h$]h&]refdocj  refdomainj,reftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sb reftarget apml_mbox_msguh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:115: ./include/uapi/misc/amd-apml.hhK\hjxubh+ that will contain the protocol information}(hjxhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK\hjuubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jhjthK]hjQubah}(h]h ]h"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:115: ./include/uapi/misc/amd-apml.hhNubh)}(hX**Description** IOCTL command for APML messages using generic _IOWR The IOCTL provides userspace access to AMD sideband mailbox protocol - Mailbox message read/write(0x0~0xFF) - returning "-EFAULT" if none of the above "-EPROTOTYPE" error is returned to provide additional error detailsh](j<)}(h**Description**h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j;hjubhX IOCTL command for APML messages using generic _IOWR The IOCTL provides userspace access to AMD sideband mailbox protocol - Mailbox message read/write(0x0~0xFF) - returning “-EFAULT” if none of the above “-EPROTOTYPE” error is returned to provide additional error details}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:115: ./include/uapi/misc/amd-apml.hhK_hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jSBRMI_IOCTL_CPUID_CMD (C macro)c.SBRMI_IOCTL_CPUID_CMDhNtauh1jhjhhhNhNubj)}(hhh](j)}(hSBRMI_IOCTL_CPUID_CMDh]j)}(hSBRMI_IOCTL_CPUID_CMDh]j)}(hSBRMI_IOCTL_CPUID_CMDh]j)}(hjh]hSBRMI_IOCTL_CPUID_CMD}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhhhKuubah}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhhhKuubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhhhKuhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhhhKuubeh}(h]h ](j,macroeh"]h$]h&]j1j,j2j,j3j,j4j5j6uh1jhhhjhNhNubh)}(h**Parameters**h]j<)}(hj2h]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj0ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:118: ./include/uapi/misc/amd-apml.hhKkhjhhubj)}(hhh]j)}(h**struct** apml_cpuid_msg Pointer to the :c:type:`struct apml_cpuid_msg ` that will contain the protocol information h](j)}(h**struct** apml_cpuid_msgh](j<)}(h **struct**h]hstruct}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j;hjOubh apml_cpuid_msg}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:118: ./include/uapi/misc/amd-apml.hhKohjKubj)}(hhh]h)}(hjPointer to the :c:type:`struct apml_cpuid_msg ` that will contain the protocol informationh](hPointer to the }(hjohhhNhNubh)}(h0:c:type:`struct apml_cpuid_msg `h]j<)}(hjyh]hstruct apml_cpuid_msg}(hj{hhhNhNubah}(h]h ](jj,c-typeeh"]h$]h&]uh1j;hjwubah}(h]h ]h"]h$]h&]refdocj  refdomainj,reftypetype refexplicitrefwarnjjjapml_cpuid_msguh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:118: ./include/uapi/misc/amd-apml.hhKnhjoubh+ that will contain the protocol information}(hjohhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKnhjlubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjkhKohjHubah}(h]h ]h"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:118: ./include/uapi/misc/amd-apml.hhNubh)}(hXC**Description** IOCTL command for APML messages using generic _IOWR The IOCTL provides userspace access to AMD sideband cpuid protocol - CPUID protocol to get CPU details for Function/Ext Function at thread level - returning "-EFAULT" if none of the above "-EPROTOTYPE" error is returned to provide additional error detailsh](j<)}(h**Description**h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j;hjubhX< IOCTL command for APML messages using generic _IOWR The IOCTL provides userspace access to AMD sideband cpuid protocol - CPUID protocol to get CPU details for Function/Ext Function at thread level - returning “-EFAULT” if none of the above “-EPROTOTYPE” error is returned to provide additional error details}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:118: ./include/uapi/misc/amd-apml.hhKqhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j SBRMI_IOCTL_MCAMSR_CMD (C macro)c.SBRMI_IOCTL_MCAMSR_CMDhNtauh1jhjhhhNhNubj)}(hhh](j)}(hSBRMI_IOCTL_MCAMSR_CMDh]j)}(hSBRMI_IOCTL_MCAMSR_CMDh]j)}(hSBRMI_IOCTL_MCAMSR_CMDh]j)}(hjh]hSBRMI_IOCTL_MCAMSR_CMD}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhhhKxubah}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhhhKxubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhhhKxhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhhhKxubeh}(h]h ](j,macroeh"]h$]h&]j1j,j2jj3jj4j5j6uh1jhhhjhNhNubh)}(h**Parameters**h]j<)}(hjh]h Parameters}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:121: ./include/uapi/misc/amd-apml.hhK~hjhhubj)}(hhh]j)}(h**struct** apml_mcamsr_msg Pointer to the :c:type:`struct apml_mcamsr_msg ` that will contain the protocol information h](j)}(h**struct** apml_mcamsr_msgh](j<)}(h **struct**h]hstruct}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj<ubh apml_mcamsr_msg}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:121: ./include/uapi/misc/amd-apml.hhKhj8ubj)}(hhh]h)}(hlPointer to the :c:type:`struct apml_mcamsr_msg ` that will contain the protocol informationh](hPointer to the }(hj\hhhNhNubh)}(h2:c:type:`struct apml_mcamsr_msg `h]j<)}(hjfh]hstruct apml_mcamsr_msg}(hjhhhhNhNubah}(h]h ](jj,c-typeeh"]h$]h&]uh1j;hjdubah}(h]h ]h"]h$]h&]refdocj  refdomainj,reftypetype refexplicitrefwarnjjjapml_mcamsr_msguh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:121: ./include/uapi/misc/amd-apml.hhKhj\ubh+ that will contain the protocol information}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjYubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhjXhKhj5ubah}(h]h ]h"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:121: ./include/uapi/misc/amd-apml.hhNubh)}(hX=**Description** IOCTL command for APML messages using generic _IOWR The IOCTL provides userspace access to AMD sideband MCAMSR protocol - MCAMSR protocol to get MCA bank details for Function at thread level - returning "-EFAULT" if none of the above "-EPROTOTYPE" error is returned to provide additional error detailsh](j<)}(h**Description**h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j;hjubhX6 IOCTL command for APML messages using generic _IOWR The IOCTL provides userspace access to AMD sideband MCAMSR protocol - MCAMSR protocol to get MCA bank details for Function at thread level - returning “-EFAULT” if none of the above “-EPROTOTYPE” error is returned to provide additional error details}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:121: ./include/uapi/misc/amd-apml.hhKhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"SBRMI_IOCTL_REG_XFER_CMD (C macro)c.SBRMI_IOCTL_REG_XFER_CMDhNtauh1jhjhhhNhNubj)}(hhh](j)}(hSBRMI_IOCTL_REG_XFER_CMDh]j)}(hSBRMI_IOCTL_REG_XFER_CMDh]j)}(hSBRMI_IOCTL_REG_XFER_CMDh]j)}(hjh]hSBRMI_IOCTL_REG_XFER_CMD}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhhhK{ubah}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhhhK{ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhhhK{hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhhhK{ubeh}(h]h ](j,macroeh"]h$]h&]j1j,j2jj3jj4j5j6uh1jhhhjhNhNubh)}(h**Parameters**h]j<)}(hj h]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:124: ./include/uapi/misc/amd-apml.hhKhjhhubj)}(hhh]j)}(h**struct** apml_reg_xfer_msg Pointer to the :c:type:`struct apml_reg_xfer_msg ` that will contain the protocol information h](j)}(h**struct** apml_reg_xfer_msgh](j<)}(h **struct**h]hstruct}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj)ubh apml_reg_xfer_msg}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:124: ./include/uapi/misc/amd-apml.hhKhj%ubj)}(hhh]h)}(hpPointer to the :c:type:`struct apml_reg_xfer_msg ` that will contain the protocol informationh](hPointer to the }(hjIhhhNhNubh)}(h6:c:type:`struct apml_reg_xfer_msg `h]j<)}(hjSh]hstruct apml_reg_xfer_msg}(hjUhhhNhNubah}(h]h ](jj,c-typeeh"]h$]h&]uh1j;hjQubah}(h]h ]h"]h$]h&]refdocj  refdomainj,reftypetype refexplicitrefwarnjjjapml_reg_xfer_msguh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:124: ./include/uapi/misc/amd-apml.hhKhjIubh+ that will contain the protocol information}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjphKhjFubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhjEhKhj"ubah}(h]h ]h"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:124: ./include/uapi/misc/amd-apml.hhNubh)}(h**Description** IOCTL command for APML messages using generic _IOWR The IOCTL provides userspace access to AMD sideband register xfer protocol - Register xfer protocol to get/set hardware register for given offseth](j<)}(h**Description**h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j;hjubh IOCTL command for APML messages using generic _IOWR The IOCTL provides userspace access to AMD sideband register xfer protocol - Register xfer protocol to get/set hardware register for given offset}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:124: ./include/uapi/misc/amd-apml.hhKhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"SBTSI_IOCTL_REG_XFER_CMD (C macro)c.SBTSI_IOCTL_REG_XFER_CMDhNtauh1jhjhhhNhNubj)}(hhh](j)}(hSBTSI_IOCTL_REG_XFER_CMDh]j)}(hSBTSI_IOCTL_REG_XFER_CMDh]j)}(hSBTSI_IOCTL_REG_XFER_CMDh]j)}(hjh]hSBTSI_IOCTL_REG_XFER_CMD}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhhhK~ubah}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhhhK~ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhhhK~hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhhhK~ubeh}(h]h ](j,macroeh"]h$]h&]j1j,j2jj3jj4j5j6uh1jhhhjhNhNubh)}(h**Parameters**h]j<)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j;hjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:127: ./include/uapi/misc/amd-apml.hhKhjhhubj)}(hhh]j)}(h**struct** apml_tsi_xfer_msg Pointer to the :c:type:`struct apml_tsi_xfer_msg ` that will contain the protocol information h](j)}(h**struct** apml_tsi_xfer_msgh](j<)}(h **struct**h]hstruct}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj ubh apml_tsi_xfer_msg}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:127: ./include/uapi/misc/amd-apml.hhKhj ubj)}(hhh]h)}(hpPointer to the :c:type:`struct apml_tsi_xfer_msg ` that will contain the protocol informationh](hPointer to the }(hj6 hhhNhNubh)}(h6:c:type:`struct apml_tsi_xfer_msg `h]j<)}(hj@ h]hstruct apml_tsi_xfer_msg}(hjB hhhNhNubah}(h]h ](jj,c-typeeh"]h$]h&]uh1j;hj> ubah}(h]h ]h"]h$]h&]refdocj  refdomainj,reftypetype refexplicitrefwarnjjjapml_tsi_xfer_msguh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:127: ./include/uapi/misc/amd-apml.hhKhj6 ubh+ that will contain the protocol information}(hj6 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj] hKhj3 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj2 hKhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:127: ./include/uapi/misc/amd-apml.hhNubh)}(h**Description** IOCTL command for APML TSI messages using generic _IOWR The IOCTL provides userspace access to AMD sideband TSI register xfer protocol - TSI protocol to read/write temperature sensor registersh](j<)}(h**Description**h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj{ ubh IOCTL command for APML TSI messages using generic _IOWR The IOCTL provides userspace access to AMD sideband TSI register xfer protocol - TSI protocol to read/write temperature sensor registers}(hj{ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/misc-devices/amd-sbi:127: ./include/uapi/misc/amd-apml.hhKhjhhubeh}(h] driver-ioctlsah ]h"] driver ioctlsah$]h&]uh1hhhhhhhhKpubh)}(hhh](h)}(hUser-space usageh]hUser-space usage}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hYTo access side band interface from a C program. First, user need to include the headers::h]hXTo access side band interface from a C program. First, user need to include the headers:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubjz)}(h#include h]h#include }hj sbah}(h]h ]h"]h$]h&]hhuh1jyhhhKhj hhubh)}(hVWhich defines the supported IOCTL and data structure to be passed from the user space.h]hVWhich defines the supported IOCTL and data structure to be passed from the user space.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(h.Next thing, open the device file, as follows::h]h-Next thing, open the device file, as follows:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubjz)}(hcint file; file = open("/dev/sbrmi-*", O_RDWR); if (file < 0) { /* ERROR HANDLING */ exit(1); }h]hcint file; file = open("/dev/sbrmi-*", O_RDWR); if (file < 0) { /* ERROR HANDLING */ exit(1); }}hj sbah}(h]h ]h"]h$]h&]hhuh1jyhhhKhj hhubh)}(hTo open SB-TSI device::h]hTo open SB-TSI device:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubjz)}(hdint file; file = open("/dev/sbtsi-4c", O_RDWR); if (file < 0) { /* ERROR HANDLING */ exit(1); }h]hdint file; file = open("/dev/sbtsi-4c", O_RDWR); if (file < 0) { /* ERROR HANDLING */ exit(1); }}hj sbah}(h]h ]h"]h$]h&]hhuh1jyhhhKhj hhubh)}(h!The following IOCTLs are defined:h]h!The following IOCTLs are defined:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hX``#define SB_BASE_IOCTL_NR 0xF9`` ``#define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg)`` ``#define SBRMI_IOCTL_CPUID_CMD _IOWR(SB_BASE_IOCTL_NR, 1, struct apml_cpuid_msg)`` ``#define SBRMI_IOCTL_MCAMSR_CMD _IOWR(SB_BASE_IOCTL_NR, 2, struct apml_mcamsr_msg)`` ``#define SBRMI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 3, struct apml_reg_xfer_msg)`` ``#define SBTSI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 4, struct apml_tsi_xfer_msg)``h](j<)}(h.``#define SB_BASE_IOCTL_NR 0xF9``h]h*#define SB_BASE_IOCTL_NR 0xF9}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj! ubh }(hj! hhhNhNubj<)}(hZ``#define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg)``h]hV#define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg)}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj! ubh }hj! sbj<)}(h[``#define SBRMI_IOCTL_CPUID_CMD _IOWR(SB_BASE_IOCTL_NR, 1, struct apml_cpuid_msg)``h]hW#define SBRMI_IOCTL_CPUID_CMD _IOWR(SB_BASE_IOCTL_NR, 1, struct apml_cpuid_msg)}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj! ubh }hj! sbj<)}(h\``#define SBRMI_IOCTL_MCAMSR_CMD _IOWR(SB_BASE_IOCTL_NR, 2, struct apml_mcamsr_msg)``h]hX#define SBRMI_IOCTL_MCAMSR_CMD _IOWR(SB_BASE_IOCTL_NR, 2, struct apml_mcamsr_msg)}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj! ubh }hj! sbj<)}(h^``#define SBRMI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 3, struct apml_reg_xfer_msg)``h]hZ#define SBRMI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 3, struct apml_reg_xfer_msg)}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj! ubh }hj! sbj<)}(h^``#define SBTSI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 4, struct apml_tsi_xfer_msg)``h]hZ#define SBTSI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 4, struct apml_tsi_xfer_msg)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j;hj! 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