Jsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}(hhparenthuba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/mhi/mhimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}(hhhh2ubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/mhi/mhimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}(hhhhFubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/mhi/mhimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}(hhhhZubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/mhi/mhimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}(hhhhnubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/mhi/mhimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}(hhhhubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/mhi/mhimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}(hhhhubah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh5/var/lib/git/docbuild/linux/Documentation/mhi/mhi.rsthKubhsection)}(hhh](htitle)}(hMHI (Modem Host Interface)h]hMHI (Modem Host Interface)}(hhhhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h:This document provides information about the MHI protocol.h]h:This document provides information about the MHI protocol.}(hhhhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hXMHI is a protocol developed by Qualcomm Innovation Center, Inc. It is used by the host processors to control and communicate with modem devices over high speed peripheral buses or shared memory. Even though MHI can be easily adapted to any peripheral buses, it is primarily used with PCIe based devices. MHI provides logical channels over the physical buses and allows transporting the modem protocols, such as IP data packets, modem control messages, and diagnostics over at least one of those logical channels. Also, the MHI protocol provides data acknowledgment feature and manages the power state of the modems via one or more logical channels.h]hXMHI is a protocol developed by Qualcomm Innovation Center, Inc. It is used by the host processors to control and communicate with modem devices over high speed peripheral buses or shared memory. Even though MHI can be easily adapted to any peripheral buses, it is primarily used with PCIe based devices. MHI provides logical channels over the physical buses and allows transporting the modem protocols, such as IP data packets, modem control messages, and diagnostics over at least one of those logical channels. Also, the MHI protocol provides data acknowledgment feature and manages the power state of the modems via one or more logical channels.}(hhhhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h MHI Internalsh]h MHI Internals}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hMMIOh]hMMIO}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hMMIO (Memory mapped IO) consists of a set of registers in the device hardware, which are mapped to the host memory space by the peripheral buses like PCIe. Following are the major components of MMIO register space:h]hMMIO (Memory mapped IO) consists of a set of registers in the device hardware, which are mapped to the host memory space by the peripheral buses like PCIe. Following are the major components of MMIO register space:}(hj$hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h=MHI control registers: Access to MHI configurations registersh]h=MHI control registers: Access to MHI configurations registers}(hj2hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjhhubh)}(hMHI BHI registers: BHI (Boot Host Interface) registers are used by the host for downloading the firmware to the device before MHI initialization.h]hMHI BHI registers: BHI (Boot Host Interface) registers are used by the host for downloading the firmware to the device before MHI initialization.}(hj@hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjhhubh)}(h{Channel Doorbell array: Channel Doorbell (DB) registers used by the host to notify the device when there is new work to do.h]h{Channel Doorbell array: Channel Doorbell (DB) registers used by the host to notify the device when there is new work to do.}(hjNhjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjhhubh)}(hEvent Doorbell array: Associated with event context array, the Event Doorbell (DB) registers are used by the host to notify the device when new events are available.h]hEvent Doorbell array: Associated with event context array, the Event Doorbell (DB) registers are used by the host to notify the device when new events are available.}(hj\hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjhhubh)}(hDebug registers: A set of registers and counters used by the device to expose debugging information like performance, functional, and stability to the host.h]hDebug registers: A set of registers and counters used by the device to expose debugging information like performance, functional, and stability to the host.}(hjjhjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjhhubeh}(h]mmioah ]h"]mmioah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hData structuresh]hData structures}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhhhK0ubh)}(hAll data structures used by MHI are in the host system memory. Using the physical interface, the device accesses those data structures. MHI data structures and data buffers in the host system memory regions are mapped for the device.h]hAll data structures used by MHI are in the host system memory. Using the physical interface, the device accesses those data structures. MHI data structures and data buffers in the host system memory regions are mapped for the device.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hj~hhubh)}(h^Channel context array: All channel configurations are organized in channel context data array.h]h^Channel context array: All channel configurations are organized in channel context data array.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hj~hhubh)}(hTransfer rings: Used by the host to schedule work items for a channel. The transfer rings are organized as a circular queue of Transfer Descriptors (TD).h]hTransfer rings: Used by the host to schedule work items for a channel. The transfer rings are organized as a circular queue of Transfer Descriptors (TD).}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hj~hhubh)}(h\Event context array: All event configurations are organized in the event context data array.h]h\Event context array: All event configurations are organized in the event context data array.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hj~hhubh)}(h\Event rings: Used by the device to send completion and state transition messages to the hosth]h\Event rings: Used by the device to send completion and state transition messages to the host}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hj~hhubh)}(h^Command context array: All command configurations are organized in command context data array.h]h^Command context array: All command configurations are organized in command context data array.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChj~hhubh)}(hCommand rings: Used by the host to send MHI commands to the device. The command rings are organized as a circular queue of Command Descriptors (CD).h]hCommand rings: Used by the host to send MHI commands to the device. The command rings are organized as a circular queue of Command Descriptors (CD).}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhj~hhubeh}(h]data-structuresah ]h"]data structuresah$]h&]uh1hhjhhhhhK0ubh)}(hhh](h)}(hChannelsh]hChannels}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKJubh)}(hXMHI channels are logical, unidirectional data pipes between a host and a device. The concept of channels in MHI is similar to endpoints in USB. MHI supports up to 256 channels. However, specific device implementations may support less than the maximum number of channels allowed.h]hXMHI channels are logical, unidirectional data pipes between a host and a device. The concept of channels in MHI is similar to endpoints in USB. MHI supports up to 256 channels. However, specific device implementations may support less than the maximum number of channels allowed.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjhhubh)}(hX<Two unidirectional channels with their associated transfer rings form a bidirectional data pipe, which can be used by the upper-layer protocols to transport application data packets (such as IP packets, modem control messages, diagnostics messages, and so on). Each channel is associated with a single transfer ring.h]hX<Two unidirectional channels with their associated transfer rings form a bidirectional data pipe, which can be used by the upper-layer protocols to transport application data packets (such as IP packets, modem control messages, diagnostics messages, and so on). Each channel is associated with a single transfer ring.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjhhubeh}(h]channelsah ]h"]channelsah$]h&]uh1hhjhhhhhKJubh)}(hhh](h)}(hTransfer ringsh]hTransfer rings}(hj3hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhhhKXubh)}(hX/Transfers between the host and device are organized by channels and defined by Transfer Descriptors (TD). TDs are managed through transfer rings, which are defined for each channel between the device and host and reside in the host memory. TDs consist of one or more ring elements (or transfer blocks)::h]hX.Transfers between the host and device are organized by channels and defined by Transfer Descriptors (TD). TDs are managed through transfer rings, which are defined for each channel between the device and host and reside in the host memory. TDs consist of one or more ring elements (or transfer blocks):}(hX.Transfers between the host and device are organized by channels and defined by Transfer Descriptors (TD). TDs are managed through transfer rings, which are defined for each channel between the device and host and reside in the host memory. TDs consist of one or more ring elements (or transfer blocks):hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhj.hhubh literal_block)}(h[Read Pointer (RP)] ----------->[Ring Element] } TD [Write Pointer (WP)]- [Ring Element] - [Ring Element] --------->[Ring Element] [Ring Element]h]h[Read Pointer (RP)] ----------->[Ring Element] } TD [Write Pointer (WP)]- [Ring Element] - [Ring Element] --------->[Ring Element] [Ring Element]}(hhhjPubah}(h]h ]h"]h$]h&]hhuh1jNhhhK_hj.hhubh)}(h+Below is the basic usage of transfer rings:h]h+Below is the basic usage of transfer rings:}(hj`hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehj.hhubh bullet_list)}(hhh](h list_item)}(h(Host allocates memory for transfer ring.h]h)}(hjuh]h(Host allocates memory for transfer ring.}(hjuhjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghjsubah}(h]h ]h"]h$]h&]uh1jqhjnhhhhhNubjr)}(h]Host sets the base pointer, read pointer, and write pointer in corresponding channel context.h]h)}(h]Host sets the base pointer, read pointer, and write pointer in corresponding channel context.h]h]Host sets the base pointer, read pointer, and write pointer in corresponding channel context.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjubah}(h]h ]h"]h$]h&]uh1jqhjnhhhhhNubjr)}(h'Ring is considered empty when RP == WP.h]h)}(hjh]h'Ring is considered empty when RP == WP.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjubah}(h]h ]h"]h$]h&]uh1jqhjnhhhhhNubjr)}(h*Ring is considered full when WP + 1 == RP.h]h)}(hjh]h*Ring is considered full when WP + 1 == RP.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjubah}(h]h ]h"]h$]h&]uh1jqhjnhhhhhNubjr)}(h;RP indicates the next element to be serviced by the device.h]h)}(hjh]h;RP indicates the next element to be serviced by the device.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjubah}(h]h ]h"]h$]h&]uh1jqhjnhhhhhNubjr)}(hWhen the host has a new buffer to send, it updates the ring element with buffer information, increments the WP to the next element and rings the associated channel DB. h]h)}(hWhen the host has a new buffer to send, it updates the ring element with buffer information, increments the WP to the next element and rings the associated channel DB.h]hWhen the host has a new buffer to send, it updates the ring element with buffer information, increments the WP to the next element and rings the associated channel DB.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1jqhjnhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1jlhhhKghj.hhubeh}(h]transfer-ringsah ]h"]transfer ringsah$]h&]uh1hhjhhhhhKXubh)}(hhh](h)}(h Event ringsh]h Event rings}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKrubh)}(hX{Events from the device to host are organized in event rings and defined by Event Descriptors (ED). Event rings are used by the device to report events such as data transfer completion status, command completion status, and state changes to the host. Event rings are the array of EDs that resides in the host memory. EDs consist of one or more ring elements (or transfer blocks)::h]hXzEvents from the device to host are organized in event rings and defined by Event Descriptors (ED). Event rings are used by the device to report events such as data transfer completion status, command completion status, and state changes to the host. Event rings are the array of EDs that resides in the host memory. EDs consist of one or more ring elements (or transfer blocks):}(hXzEvents from the device to host are organized in event rings and defined by Event Descriptors (ED). Event rings are used by the device to report events such as data transfer completion status, command completion status, and state changes to the host. Event rings are the array of EDs that resides in the host memory. EDs consist of one or more ring elements (or transfer blocks):hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjhhubjO)}(h[Read Pointer (RP)] ----------->[Ring Element] } ED [Write Pointer (WP)]- [Ring Element] - [Ring Element] --------->[Ring Element] [Ring Element]h]h[Read Pointer (RP)] ----------->[Ring Element] } ED [Write Pointer (WP)]- [Ring Element] - [Ring Element] --------->[Ring Element] [Ring Element]}(hhhj/ubah}(h]h ]h"]h$]h&]hhuh1jNhhhKzhjhhubh)}(h(Below is the basic usage of event rings:h]h(Below is the basic usage of event rings:}(hj?hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjm)}(hhh](jr)}(h%Host allocates memory for event ring.h]h)}(hjPh]h%Host allocates memory for event ring.}(hjPhjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjNubah}(h]h ]h"]h$]h&]uh1jqhjKhhhhhNubjr)}(h]Host sets the base pointer, read pointer, and write pointer in corresponding channel context.h]h)}(h]Host sets the base pointer, read pointer, and write pointer in corresponding channel context.h]h]Host sets the base pointer, read pointer, and write pointer in corresponding channel context.}(hjkhjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjeubah}(h]h ]h"]h$]h&]uh1jqhjKhhhhhNubjr)}(h0Both host and device has a local copy of RP, WP.h]h)}(hjh]h0Both host and device has a local copy of RP, WP.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}ubah}(h]h ]h"]h$]h&]uh1jqhjKhhhhhNubjr)}(hBRing is considered empty (no events to service) when WP + 1 == RP.h]h)}(hjh]hBRing is considered empty (no events to service) when WP + 1 == RP.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjKhhhhhNubjr)}(h0Ring is considered full of events when RP == WP.h]h)}(hjh]h0Ring is considered full of events when RP == WP.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjKhhhhhNubjr)}(hWhen there is a new event the device needs to send, the device updates ED pointed by RP, increments the RP to the next element and triggers the interrupt. h]h)}(hWhen there is a new event the device needs to send, the device updates ED pointed by RP, increments the RP to the next element and triggers the interrupt.h]hWhen there is a new event the device needs to send, the device updates ED pointed by RP, increments the RP to the next element and triggers the interrupt.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjKhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jlhhhKhjhhubeh}(h] event-ringsah ]h"] event ringsah$]h&]uh1hhjhhhhhKrubh)}(hhh](h)}(h Ring Elementh]h Ring Element}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXA Ring Element is a data structure used to transfer a single block of data between the host and the device. Transfer ring element types contain a single buffer pointer, the size of the buffer, and additional control information. Other ring element types may only contain control and status information. For single buffer operations, a ring descriptor is composed of a single element. For large multi-buffer operations (such as scatter and gather), elements can be chained to form a longer descriptor.h]hXA Ring Element is a data structure used to transfer a single block of data between the host and the device. Transfer ring element types contain a single buffer pointer, the size of the buffer, and additional control information. Other ring element types may only contain control and status information. For single buffer operations, a ring descriptor is composed of a single element. For large multi-buffer operations (such as scatter and gather), elements can be chained to form a longer descriptor.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] ring-elementah ]h"] ring elementah$]h&]uh1hhjhhhhhKubeh}(h] mhi-internalsah ]h"] mhi internalsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hMHI Operationsh]hMHI Operations}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h MHI Statesh]h MHI States}(hj-hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhKubh)}(hhh](h)}(hMHI_STATE_RESETh]hMHI_STATE_RESET}(hj>hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhKubh)}(huMHI is in reset state after power-up or hardware reset. The host is not allowed to access device MMIO register space.h]huMHI is in reset state after power-up or hardware reset. The host is not allowed to access device MMIO register space.}(hjLhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj9hhubeh}(h]mhi-state-resetah ]h"]mhi_state_resetah$]h&]uh1hhj(hhhhhKubh)}(hhh](h)}(hMHI_STATE_READYh]hMHI_STATE_READY}(hjehjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hhhhhKubh)}(heMHI is ready for initialization. The host can start MHI initialization by programming MMIO registers.h]heMHI is ready for initialization. The host can start MHI initialization by programming MMIO registers.}(hjshjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj`hhubeh}(h]mhi-state-readyah ]h"]mhi_state_readyah$]h&]uh1hhj(hhhhhKubh)}(hhh](h)}(h MHI_STATE_M0h]h MHI_STATE_M0}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hkMHI is running and operational in the device. The host can start channels by issuing channel start command.h]hkMHI is running and operational in the device. The host can start channels by issuing channel start command.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] mhi-state-m0ah ]h"] mhi_state_m0ah$]h&]uh1hhj(hhhhhKubh)}(hhh](h)}(h MHI_STATE_M1h]h MHI_STATE_M1}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hMHI operation is suspended by the device. This state is entered when the device detects inactivity at the physical interface within a preset time.h]hMHI operation is suspended by the device. This state is entered when the device detects inactivity at the physical interface within a preset time.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] mhi-state-m1ah ]h"] mhi_state_m1ah$]h&]uh1hhj(hhhhhKubh)}(hhh](h)}(h MHI_STATE_M2h]h MHI_STATE_M2}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h`MHI is in low power state. MHI operation is suspended and the device may enter lower power mode.h]h`MHI is in low power state. MHI operation is suspended and the device may enter lower power mode.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] mhi-state-m2ah ]h"] mhi_state_m2ah$]h&]uh1hhj(hhhhhKubh)}(hhh](h)}(h MHI_STATE_M3h]h MHI_STATE_M3}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h^MHI operation stopped by the host. This state is entered when the host suspends MHI operation.h]h^MHI operation stopped by the host. This state is entered when the host suspends MHI operation.}(hjhj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] mhi-state-m3ah ]h"] mhi_state_m3ah$]h&]uh1hhj(hhhhhKubeh}(h] mhi-statesah ]h"] mhi statesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hMHI Initializationh]hMHI Initialization}(hj0hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhKubh)}(hAfter system boots, the device is enumerated over the physical interface. In the case of PCIe, the device is enumerated and assigned BAR-0 for the device's MMIO register space. To initialize the MHI in a device, the host performs the following operations:h]hXAfter system boots, the device is enumerated over the physical interface. In the case of PCIe, the device is enumerated and assigned BAR-0 for the device’s MMIO register space. To initialize the MHI in a device, the host performs the following operations:}(hj>hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+hhubjm)}(hhh](jr)}(h@Allocates the MHI context for event, channel and command arrays.h]h)}(hjOh]h@Allocates the MHI context for event, channel and command arrays.}(hjOhjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjMubah}(h]h ]h"]h$]h&]uh1jqhjJhhhhhNubjr)}(h7Initializes the context array, and prepares interrupts.h]h)}(hjfh]h7Initializes the context array, and prepares interrupts.}(hjfhjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdubah}(h]h ]h"]h$]h&]uh1jqhjJhhhhhNubjr)}(h*Waits until the device enters READY state.h]h)}(hj}h]h*Waits until the device enters READY state.}(hj}hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj{ubah}(h]h ]h"]h$]h&]uh1jqhjJhhhhhNubjr)}(h>Programs MHI MMIO registers and sets device into MHI_M0 state.h]h)}(hjh]h>Programs MHI MMIO registers and sets device into MHI_M0 state.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjJhhhhhNubjr)}(h(Waits for the device to enter M0 state. h]h)}(h'Waits for the device to enter M0 state.h]h'Waits for the device to enter M0 state.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjJhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jlhhhKhj+hhubeh}(h]mhi-initializationah ]h"]mhi initializationah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hMHI Data Transferh]hMHI Data Transfer}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hMHI data transfer is initiated by the host to transfer data to the device. Following are the sequence of operations performed by the host to transfer data to device:h]hMHI data transfer is initiated by the host to transfer data to the device. Following are the sequence of operations performed by the host to transfer data to device:}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjm)}(hhh](jr)}(h)Host prepares TD with buffer information.h]h)}(hjh]h)Host prepares TD with buffer information.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubjr)}(hBHost increments the WP of the corresponding channel transfer ring.h]h)}(hj h]hBHost increments the WP of the corresponding channel transfer ring.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubjr)}(h#Host rings the channel DB register.h]h)}(hj!h]h#Host rings the channel DB register.}(hj!hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubjr)}(h"Device wakes up to process the TD.h]h)}(hj8h]h"Device wakes up to process the TD.}(hj8hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6ubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubjr)}(hHDevice generates a completion event for the processed TD by updating ED.h]h)}(hjOh]hHDevice generates a completion event for the processed TD by updating ED.}(hjOhjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjMubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubjr)}(h9Device increments the RP of the corresponding event ring.h]h)}(hjfh]h9Device increments the RP of the corresponding event ring.}(hjfhjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubjr)}(h(Device triggers IRQ to wake up the host.h]h)}(hj}h]h(Device triggers IRQ to wake up the host.}(hj}hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj{ubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubjr)}(h=Host wakes up and checks the event ring for completion event.h]h)}(hjh]h=Host wakes up and checks the event ring for completion event.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubjr)}(hxHost updates the WP of the corresponding event ring to indicate that the data transfer has been completed successfully. h]h)}(hwHost updates the WP of the corresponding event ring to indicate that the data transfer has been completed successfully.h]hwHost updates the WP of the corresponding event ring to indicate that the data transfer has been completed successfully.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jqhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jlhhhKhjhhubeh}(h]mhi-data-transferah ]h"]mhi data transferah$]h&]uh1hhjhhhhhKubeh}(h]mhi-operationsah ]h"]mhi operationsah$]h&]uh1hhhhhhhhKubeh}(h]mhi-modem-host-interfaceah ]h"]mhi (modem host interface)ah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingUTF-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confapep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacefile_insertion_enabled raw_enabledKline_length_limitM'syntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_link embed_imagesenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jjhhjjj{jxjjj+j(j j jjj j jjj(j%j]jZjjjjjjjjj jjjjju nametypes}(jNhNjNj{NjNj+Nj NjNj NjNj(Nj]NjNjNjNjNj NjNjNuh}(jhhhjjjxjjj~j(jj j.jjj jjjj%j(jZj9jj`jjjjjjjjjj+jju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.