usphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/iio/ad7606modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/iio/ad7606modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/iio/ad7606modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/iio/ad7606modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/iio/ad7606modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/iio/ad7606modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h%SPDX-License-Identifier: GPL-2.0-onlyh]h%SPDX-License-Identifier: GPL-2.0-only}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh8/var/lib/git/docbuild/linux/Documentation/iio/ad7606.rsthKubhsection)}(hhh](htitle)}(h AD7606 driverh]h AD7606 driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h]ADC driver for Analog Devices Inc. AD7606 and similar devices. The module name is ``ad7606``.h](hRADC driver for Analog Devices Inc. AD7606 and similar devices. The module name is }(hhhhhNhNubhliteral)}(h ``ad7606``h]had7606}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hSupported devicesh]hSupported devices}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(h1The following chips are supported by this driver:h]h1The following chips are supported by this driver:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh bullet_list)}(hhh](h list_item)}(h:`AD7605 `_h]h)}(hjh](h reference)}(hjh]hAD7605}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAD7605refuri.https://www.analog.com/en/products/ad7605.htmluh1jhjubhtarget)}(h1 h]h}(h]ad7605ah ]h"]ad7605ah$]h&]refurij,uh1j- referencedKhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h:`AD7606 `_h]h)}(hjKh](j)}(hjKh]hAD7606}(hjPhhhNhNubah}(h]h ]h"]h$]h&]nameAD7606j+.https://www.analog.com/en/products/ad7606.htmluh1jhjMubj.)}(h1 h]h}(h]ad7606ah ]h"]ad7606ah$]h&]refurij_uh1j-j<KhjMubeh}(h]h ]h"]h$]h&]uh1hhhhKhjIubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h<`AD7606B `_h]h)}(hj{h](j)}(hj{h]hAD7606B}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAD7606Bj+/https://www.analog.com/en/products/ad7606b.htmluh1jhj}ubj.)}(h2 h]h}(h]ad7606bah ]h"]ad7606bah$]h&]refurijuh1j-j<Khj}ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjyubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h;`AD7616 `_ h]h)}(h:`AD7616 `_h](j)}(hjh]hAD7616}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAD7616j+.https://www.analog.com/en/products/ad7616.htmluh1jhjubj.)}(h1 h]h}(h]ad7616ah ]h"]ad7616ah$]h&]refurijuh1j-j<Khjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1j hhhKhhhhubeh}(h]supported-devicesah ]h"]supported devicesah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hSupported featuresh]hSupported features}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hSPI wiring modesh]hSPI wiring modes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hiThese ADCs can output data on several SDO lines (1/2/4/8). The driver currently supports only 1 SDO line.h]hiThese ADCs can output data on several SDO lines (1/2/4/8). The driver currently supports only 1 SDO line.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]spi-wiring-modesah ]h"]spi wiring modesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hSPI offload wiringh]hSPI offload wiring}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhKubh)}(hDWhen used with a SPI offload, the supported wiring configuration is:h]hDWhen used with a SPI offload, the supported wiring configuration is:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj"hhubh literal_block)}(hX+-------------+ +-------------+ | BUSY |-------->| TRIGGER | | CS |<--------| CS | | | | | | ADC | | SPI | | | | | | SDI |<--------| SDO | | DOUTA |-------->| SDI | | SCLK |<--------| SCLK | | | | | | | +-------------+ | CONVST |<--------| PWM | +-------------+ +-------------+h]hX+-------------+ +-------------+ | BUSY |-------->| TRIGGER | | CS |<--------| CS | | | | | | ADC | | SPI | | | | | | SDI |<--------| SDO | | DOUTA |-------->| SDI | | SCLK |<--------| SCLK | | | | | | | +-------------+ | CONVST |<--------| PWM | +-------------+ +-------------+}hjCsbah}(h]h ]h"]h$]h&]hhforcelanguagenonehighlight_args}uh1jAhhhK!hj"hhubh)}(hXIn this case, the ``pwms`` property is required. The ``#trigger-source-cells = <1>`` property is also required to connect back to the SPI offload. The SPI offload will have ``trigger-sources`` property with a cell to indicate the busy signal: ``<&ad7606 AD4695_TRIGGER_EVENT_BUSY>``.h](hIn this case, the }(hjVhhhNhNubh)}(h``pwms``h]hpwms}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVubh property is required. The }(hjVhhhNhNubh)}(h``#trigger-source-cells = <1>``h]h#trigger-source-cells = <1>}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVubhY property is also required to connect back to the SPI offload. The SPI offload will have }(hjVhhhNhNubh)}(h``trigger-sources``h]htrigger-sources}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVubh3 property with a cell to indicate the busy signal: }(hjVhhhNhNubh)}(h'``<&ad7606 AD4695_TRIGGER_EVENT_BUSY>``h]h#<&ad7606 AD4695_TRIGGER_EVENT_BUSY>}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVubh.}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK1hj"hhubhseealso)}(h`SPI offload support`_h]h)}(hjh]j)}(hjh]hSPI offload support}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameSPI offload supportrefidspi-offload-supportuh1jhjresolvedKubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubah}(h]h ]h"]h$]h&]uh1jhj"hhhhhNubeh}(h]spi-offload-wiringah ]h"]spi offload wiringah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hParallel wiring modeh]hParallel wiring mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK;ubh)}(hThere is also a parallel interface, with 16 lines (that can be reduced to 8 in byte mode). The parallel interface is selected by declaring the device as platform in the device tree (with no io-backends node defined, see below).h]hThere is also a parallel interface, with 16 lines (that can be reduced to 8 in byte mode). The parallel interface is selected by declaring the device as platform in the device tree (with no io-backends node defined, see below).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjhhubeh}(h]parallel-wiring-modeah ]h"]parallel wiring modeah$]h&]uh1hhjhhhhhK;ubh)}(hhh](h)}(hIIO-backend modeh]hIIO-backend mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKBubh)}(hThis mode allows to reach the best sample rates, but it requires an external hardware (eg HDL or APU) to handle the low level communication. The backend mode is enabled when through the definition of the "io-backends" property in the device tree.h]hThis mode allows to reach the best sample rates, but it requires an external hardware (eg HDL or APU) to handle the low level communication. The backend mode is enabled when through the definition of the “io-backends” property in the device tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjhhubh)}(hThe reference configuration for the current implementation of IIO-backend mode is the HDL reference provided by ADI: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdlh](huThe reference configuration for the current implementation of IIO-backend mode is the HDL reference provided by ADI: }(hj!hhhNhNubj)}(hBhttps://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdlh]hBhttps://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl}(hj)hhhNhNubah}(h]h ]h"]h$]h&]refurij+uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhhhKIhjhhubh)}(hxThis implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWM connected to the conversion trigger pin.h]hxThis implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWM connected to the conversion trigger pin.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjhhubjB)}(hX+---+ +---------------------------- | | +-------+ |AD76xx | A | controls | | | | D |-------------->| PWM |-------------->| cnvst | 7 | | | | | 6 | +-------+ | | 0 | controls +-----------+-----------+ | | 6 |---------->| | |<--| frstdata | | | Backend | Backend |<--| busy | D | | Driver | | | | R | | | |-->| clk | I | requests |+---------+| DMA | | | V |----------->| Buffer ||<---- |<=>| DATA | E | |+---------+| | | | R | +-----------+-----------+ | | |-------------------------------------->| reset/configuration gpios +---+ +-----------------------------h]hX+---+ +---------------------------- | | +-------+ |AD76xx | A | controls | | | | D |-------------->| PWM |-------------->| cnvst | 7 | | | | | 6 | +-------+ | | 0 | controls +-----------+-----------+ | | 6 |---------->| | |<--| frstdata | | | Backend | Backend |<--| busy | D | | Driver | | | | R | | | |-->| clk | I | requests |+---------+| DMA | | | V |----------->| Buffer ||<---- |<=>| DATA | E | |+---------+| | | | R | +-----------+-----------+ | | |-------------------------------------->| reset/configuration gpios +---+ +-----------------------------}hjLsbah}(h]h ]h"]h$]h&]hhjQjRjSjT}uh1jAhhhKPhjhhubeh}(h]iio-backend-modeah ]h"]iio-backend modeah$]h&]uh1hhjhhhhhKBubh)}(hhh](h)}(hSoftware and hardware modesh]hSoftware and hardware modes}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchhhhhKfubh)}(hvWhile all the AD7606/AD7616 series parts can be configured using GPIOs, some of them can be configured using register.h]hvWhile all the AD7606/AD7616 series parts can be configured using GPIOs, some of them can be configured using register.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjchhubh)}(hThe chips that support software mode have more values available for configuring the device, as well as more settings, and allow to control the range and calibration per channel.h]hThe chips that support software mode have more values available for configuring the device, as well as more settings, and allow to control the range and calibration per channel.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjchhubhdefinition_list)}(hhh]hdefinition_list_item)}(hKThe following settings are available per channel in software mode: - Scale h](hterm)}(hBThe following settings are available per channel in software mode:h]hBThe following settings are available per channel in software mode:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKphjubh definition)}(hhh]j )}(hhh]j)}(hScale h]h)}(hScaleh]hScale}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j-uh1j hhhKphjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKphjubah}(h]h ]h"]h$]h&]uh1jhjchhhNhNubh)}(hHAlso, there is a broader choice of oversampling ratios in software mode.h]hHAlso, there is a broader choice of oversampling ratios in software mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjchhubeh}(h]software-and-hardware-modesah ]h"]software and hardware modesah$]h&]uh1hhjhhhhhKfubh)}(hhh](h)}(hConversion triggeringh]hConversion triggering}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKuubh)}(h5The conversion can be triggered by two distinct ways:h]h5The conversion can be triggered by two distinct ways:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjhhubh block_quote)}(hX- A GPIO is connected to the conversion trigger pin, and this GPIO is controlled by the driver directly. In this configuration, the driver sets back the conversion trigger pin to high as soon as it has read all the conversions. - An external source is connected to the conversion trigger pin. In the current implementation, it must be a PWM. In this configuration, the driver does not control directly the conversion trigger pin. Instead, it can control the PWM's frequency. This trigger is enabled only for iio-backend. h]j )}(hhh](j)}(hA GPIO is connected to the conversion trigger pin, and this GPIO is controlled by the driver directly. In this configuration, the driver sets back the conversion trigger pin to high as soon as it has read all the conversions. h]h)}(hA GPIO is connected to the conversion trigger pin, and this GPIO is controlled by the driver directly. In this configuration, the driver sets back the conversion trigger pin to high as soon as it has read all the conversions.h]hA GPIO is connected to the conversion trigger pin, and this GPIO is controlled by the driver directly. In this configuration, the driver sets back the conversion trigger pin to high as soon as it has read all the conversions.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhj"ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hX#An external source is connected to the conversion trigger pin. In the current implementation, it must be a PWM. In this configuration, the driver does not control directly the conversion trigger pin. Instead, it can control the PWM's frequency. This trigger is enabled only for iio-backend. h]h)}(hX"An external source is connected to the conversion trigger pin. In the current implementation, it must be a PWM. In this configuration, the driver does not control directly the conversion trigger pin. Instead, it can control the PWM's frequency. This trigger is enabled only for iio-backend.h]hX$An external source is connected to the conversion trigger pin. In the current implementation, it must be a PWM. In this configuration, the driver does not control directly the conversion trigger pin. Instead, it can control the PWM’s frequency. This trigger is enabled only for iio-backend.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1j hhhKyhjubah}(h]h ]h"]h$]h&]uh1jhhhKyhjhhubeh}(h]conversion-triggeringah ]h"]conversion triggeringah$]h&]uh1hhjhhhhhKuubh)}(hhh](h)}(hReference voltageh]hReference voltage}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhhhhhKubh)}(h32 possible reference voltage sources are supported:h]h32 possible reference voltage sources are supported:}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjfhhubj)}(h8- Internal reference (2.5V) - External reference (2.5V) h]j )}(hhh](j)}(hInternal reference (2.5V)h]h)}(hjh]hInternal reference (2.5V)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hExternal reference (2.5V) h]h)}(hExternal reference (2.5V)h]hExternal reference (2.5V)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1j hhhKhjubah}(h]h ]h"]h$]h&]uh1jhhhKhjfhhubh)}(hThe source is determined by the device tree. If ``refin-supply`` is present, then the external reference is used, otherwise the internal reference is used.h](h0The source is determined by the device tree. If }(hjhhhNhNubh)}(h``refin-supply``h]h refin-supply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh[ is present, then the external reference is used, otherwise the internal reference is used.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjfhhubeh}(h]reference-voltageah ]h"]reference voltageah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h Oversamplingh]h Oversampling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThis family supports oversampling to improve SNR. In software mode, the following ratios are available: 1 (oversampling disabled)/2/4/8/16/32/64/128/256.h]hThis family supports oversampling to improve SNR. In software mode, the following ratios are available: 1 (oversampling disabled)/2/4/8/16/32/64/128/256.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] oversamplingah ]h"] oversamplingah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hUnimplemented featuresh]hUnimplemented features}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj )}(hhh](j)}(h2/4/8 SDO linesh]h)}(hj,h]h2/4/8 SDO lines}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj*ubah}(h]h ]h"]h$]h&]uh1jhj'hhhhhNubj)}(hCRC indicationh]h)}(hjCh]hCRC indication}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjAubah}(h]h ]h"]h$]h&]uh1jhj'hhhhhNubj)}(h Calibration h]h)}(h Calibrationh]h Calibration}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjXubah}(h]h ]h"]h$]h&]uh1jhj'hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1j hhhKhjhhubeh}(h]unimplemented-featuresah ]h"]unimplemented featuresah$]h&]uh1hhjhhhhhKubeh}(h]supported-featuresah ]h"]supported featuresah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSPI offload supporth]hSPI offload support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hTo be able to achieve the maximum sample rate, the driver can be used with the `AXI SPI Engine`_ to provide SPI offload support.h](hOTo be able to achieve the maximum sample rate, the driver can be used with the }(hjhhhNhNubj)}(h`AXI SPI Engine`_h]hAXI SPI Engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAXI SPI Enginej+Dhttps://analogdevicesinc.github.io/hdl/library/spi_engine/index.htmluh1jhjjKubh to provide SPI offload support.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj.)}(hX.. _AXI SPI Engine: https://analogdevicesinc.github.io/hdl/library/spi_engine/index.htmlh]h}(h]axi-spi-engineah ]h"]axi spi engineah$]h&]j+juh1j-hKhjhhhhj<Kubh)}(hBWhen SPI offload is being used, some attributes will be different.h]hBWhen SPI offload is being used, some attributes will be different.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj )}(hhh](j)}(h!``trigger`` directory is removed.h]h)}(hjh](h)}(h ``trigger``h]htrigger}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh directory is removed.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hF``sampling_frequency`` attribute is added for setting the sample rate.h]h)}(hjh](h)}(h``sampling_frequency``h]hsampling_frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh0 attribute is added for setting the sample rate.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h!``timestamp`` channel is removed.h]h)}(hj#h](h)}(h ``timestamp``h]h timestamp}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubh channel is removed.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj!ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hsBuffer data format may be different compared to when offload is not used, e.g. the ``in_voltage0_type`` attribute. h]h)}(hrBuffer data format may be different compared to when offload is not used, e.g. the ``in_voltage0_type`` attribute.h](hSBuffer data format may be different compared to when offload is not used, e.g. the }(hjJhhhNhNubh)}(h``in_voltage0_type``h]hin_voltage0_type}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubh attribute.}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjFubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1j hhhKhjhhubeh}(h]jah ]h"]spi offload supportah$]h&]uh1hhhhhhhhKj<Kubh)}(hhh](h)}(hDevice buffersh]hDevice buffers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hhhhhKubh)}(hhh](h)}(hIIO triggered bufferh]hIIO triggered buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX=This driver supports IIO triggered buffers, with a "built in" trigger, i.e the trigger is allocated and linked by the driver, and a new conversion is triggered as soon as the samples are transferred, and a timestamp channel is added to make up for the potential jitter induced by the delays in the interrupt handling.h]hXAThis driver supports IIO triggered buffers, with a “built in” trigger, i.e the trigger is allocated and linked by the driver, and a new conversion is triggered as soon as the samples are transferred, and a timestamp channel is added to make up for the potential jitter induced by the delays in the interrupt handling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]iio-triggered-bufferah ]h"]iio triggered bufferah$]h&]uh1hhj}hhhhhKubh)}(hhh](h)}(hIIO backend bufferh]hIIO backend buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXkWhen IIO backend is used, the trigger is not needed, and the sample rate is considered as stable. There is no timestamp channel. The communication is delegated to an external logic, called a backend, and the backend's driver handles the buffer. When this mode is enabled, the driver cannot control the conversion pin, because the busy pin is bound to the backend.h]hXmWhen IIO backend is used, the trigger is not needed, and the sample rate is considered as stable. There is no timestamp channel. The communication is delegated to an external logic, called a backend, and the backend’s driver handles the buffer. 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