€•ÌOŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ/translations/zh_CN/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/zh_TW/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/it_IT/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/ja_JP/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/ko_KR/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/pt_BR/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/sp_SP/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ%SPDX-License-Identifier: GPL-2.0-only”h]”hŒ%SPDX-License-Identifier: GPL-2.0-only”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³Œ8/var/lib/git/docbuild/linux/Documentation/iio/ad7191.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ AD7191 driver”h]”hŒ AD7191 driver”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ paragraph”“”)”}”(hŒ,Device driver for Analog Devices AD7191 ADC.”h]”hŒ,Device driver for Analog Devices AD7191 ADC.”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒSupported devices”h]”hŒSupported devices”…””}”(hhðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhíh²hh³hÇh´K ubhŒ bullet_list”“”)”}”(hhh]”hŒ list_item”“”)”}”(hŒ*`AD7191 `_ ”h]”hÞ)”}”(hŒ)`AD7191 `_”h]”(hŒ reference”“”)”}”(hj h]”hŒAD7191”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒAD7191”Œrefuri”Œhttps://www.analog.com/AD7191”uh1j hj ubhŒtarget”“”)”}”(hŒ ”h]”h}”(h]”Œad7191”ah ]”h"]”Œad7191”ah$]”h&]”Œrefuri”juh1j Œ referenced”Khj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjh²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1hþh³hÇh´K hhíh²hubhÞ)”}”(hŒ¾The AD7191 is a high precision, low noise, 24-bit Σ-Δ ADC with integrated PGA. It features two differential input channels, an internal temperature sensor, and configurable sampling rates.”h]”hŒ¾The AD7191 is a high precision, low noise, 24-bit Σ-Δ ADC with integrated PGA. It features two differential input channels, an internal temperature sensor, and configurable sampling rates.”…””}”(hjDh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhíh²hubeh}”(h]”Œsupported-devices”ah ]”h"]”Œsupported devices”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Devicetree”h]”hŒ Devicetree”…””}”(hj]h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjZh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒPin Configuration”h]”hŒPin Configuration”…””}”(hjnh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjkh²hh³hÇh´KubhÞ)”}”(hXThe driver supports both pin-strapped and GPIO-controlled configurations for ODR (Output Data Rate) and PGA (Programmable Gain Amplifier) settings. These configurations are mutually exclusive - you must use either pin-strapped or GPIO control for each setting, not both.”h]”hXThe driver supports both pin-strapped and GPIO-controlled configurations for ODR (Output Data Rate) and PGA (Programmable Gain Amplifier) settings. These configurations are mutually exclusive - you must use either pin-strapped or GPIO control for each setting, not both.”…””}”(hj|h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjkh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒODR Configuration”h]”hŒODR Configuration”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjŠh²hh³hÇh´KubhÞ)”}”(hŒGThe ODR can be configured either through GPIO control or pin-strapping:”h]”hŒGThe ODR can be configured either through GPIO control or pin-strapping:”…””}”(hj›h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hjŠh²hubhÿ)”}”(hhh]”(j)”}”(hŒLWhen using GPIO control, specify the "odr-gpios" property in the device tree”h]”hÞ)”}”(hj®h]”hŒPWhen using GPIO control, specify the “odr-gpios†property in the device tree”…””}”(hj°h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K"hj¬ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj©h²hh³hÇh´Nubj)”}”(hŒXFor pin-strapped configuration, specify the "adi,odr-value" property in the device tree ”h]”hÞ)”}”(hŒWFor pin-strapped configuration, specify the "adi,odr-value" property in the device tree”h]”hŒ[For pin-strapped configuration, specify the “adi,odr-value†property in the device tree”…””}”(hjÇh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K#hjÃubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj©h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jBŒ-”uh1hþh³hÇh´K"hjŠh²hubhÞ)”}”(hŒAvailable ODR settings:”h]”hŒAvailable ODR settings:”…””}”(hjâh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K&hjŠh²hubhŒ block_quote”“”)”}”(hŒe- 120 Hz (ODR1=0, ODR2=0) - 60 Hz (ODR1=0, ODR2=1) - 50 Hz (ODR1=1, ODR2=0) - 10 Hz (ODR1=1, ODR2=1) ”h]”hÿ)”}”(hhh]”(j)”}”(hŒ120 Hz (ODR1=0, ODR2=0)”h]”hÞ)”}”(hjûh]”hŒ120 Hz (ODR1=0, ODR2=0)”…””}”(hjýh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K(hjùubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjöubj)”}”(hŒ60 Hz (ODR1=0, ODR2=1)”h]”hÞ)”}”(hjh]”hŒ60 Hz (ODR1=0, ODR2=1)”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K)hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjöubj)”}”(hŒ50 Hz (ODR1=1, ODR2=0)”h]”hÞ)”}”(hj)h]”hŒ50 Hz (ODR1=1, ODR2=0)”…””}”(hj+h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K*hj'ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjöubj)”}”(hŒ10 Hz (ODR1=1, ODR2=1) ”h]”hÞ)”}”(hŒ10 Hz (ODR1=1, ODR2=1)”h]”hŒ10 Hz (ODR1=1, ODR2=1)”…””}”(hjBh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K+hj>ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjöubeh}”(h]”h ]”h"]”h$]”h&]”jBjáuh1hþh³hÇh´K(hjòubah}”(h]”h ]”h"]”h$]”h&]”uh1jðh³hÇh´K(hjŠh²hubeh}”(h]”Œodr-configuration”ah ]”h"]”Œodr configuration”ah$]”h&]”uh1hÈhjkh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒPGA Configuration”h]”hŒPGA Configuration”…””}”(hjmh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjjh²hh³hÇh´K.ubhÞ)”}”(hŒGThe PGA can be configured either through GPIO control or pin-strapping:”h]”hŒGThe PGA can be configured either through GPIO control or pin-strapping:”…””}”(hj{h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K0hjjh²hubhÿ)”}”(hhh]”(j)”}”(hŒLWhen using GPIO control, specify the "pga-gpios" property in the device tree”h]”hÞ)”}”(hjŽh]”hŒPWhen using GPIO control, specify the “pga-gpios†property in the device tree”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K2hjŒubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj‰h²hh³hÇh´Nubj)”}”(hŒXFor pin-strapped configuration, specify the "adi,pga-value" property in the device tree ”h]”hÞ)”}”(hŒWFor pin-strapped configuration, specify the "adi,pga-value" property in the device tree”h]”hŒ[For pin-strapped configuration, specify the “adi,pga-value†property in the device tree”…””}”(hj§h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K3hj£ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj‰h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jBjáuh1hþh³hÇh´K2hjjh²hubhÞ)”}”(hŒAvailable PGA gain settings:”h]”hŒAvailable PGA gain settings:”…””}”(hjÁh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K6hjjh²hubjñ)”}”(hŒ[- 1x (PGA1=0, PGA2=0) - 8x (PGA1=0, PGA2=1) - 64x (PGA1=1, PGA2=0) - 128x (PGA1=1, PGA2=1) ”h]”hÿ)”}”(hhh]”(j)”}”(hŒ1x (PGA1=0, PGA2=0)”h]”hÞ)”}”(hjØh]”hŒ1x (PGA1=0, PGA2=0)”…””}”(hjÚh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K8hjÖubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÓubj)”}”(hŒ8x (PGA1=0, PGA2=1)”h]”hÞ)”}”(hjïh]”hŒ8x (PGA1=0, PGA2=1)”…””}”(hjñh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K9hjíubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÓubj)”}”(hŒ64x (PGA1=1, PGA2=0)”h]”hÞ)”}”(hjh]”hŒ64x (PGA1=1, PGA2=0)”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K:hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÓubj)”}”(hŒ128x (PGA1=1, PGA2=1) ”h]”hÞ)”}”(hŒ128x (PGA1=1, PGA2=1)”h]”hŒ128x (PGA1=1, PGA2=1)”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K;hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÓubeh}”(h]”h ]”h"]”h$]”h&]”jBjáuh1hþh³hÇh´K8hjÏubah}”(h]”h ]”h"]”h$]”h&]”uh1jðh³hÇh´K8hjjh²hubeh}”(h]”Œpga-configuration”ah ]”h"]”Œpga configuration”ah$]”h&]”uh1hÈhjkh²hh³hÇh´K.ubeh}”(h]”Œpin-configuration”ah ]”h"]”Œpin configuration”ah$]”h&]”uh1hÈhjZh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒClock Configuration”h]”hŒClock Configuration”…””}”(hjRh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjOh²hh³hÇh´K>ubhÞ)”}”(hŒ=The AD7191 supports both internal and external clock sources:”h]”hŒ=The AD7191 supports both internal and external clock sources:”…””}”(hj`h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K@hjOh²hubhÿ)”}”(hhh]”(j)”}”(hŒQWhen CLKSEL pin is ACTIVE: Uses internal 4.92MHz clock (no clock property needed)”h]”hÞ)”}”(hŒQWhen CLKSEL pin is ACTIVE: Uses internal 4.92MHz clock (no clock property needed)”h]”hŒQWhen CLKSEL pin is ACTIVE: Uses internal 4.92MHz clock (no clock property needed)”…””}”(hjuh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KBhjqubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjnh²hh³hÇh´Nubj)”}”(hXWhen CLKSEL pin is INACTIVE: Requires external clock source - Can be a crystal between MCLK1 and MCLK2 pins - Or a CMOS-compatible clock driving MCLK1 pin and MCLK2 left unconnected - Must specify the "clocks" property in device tree when using external clock ”h]”hÞ)”}”(hXWhen CLKSEL pin is INACTIVE: Requires external clock source - Can be a crystal between MCLK1 and MCLK2 pins - Or a CMOS-compatible clock driving MCLK1 pin and MCLK2 left unconnected - Must specify the "clocks" property in device tree when using external clock”h]”hXWhen CLKSEL pin is INACTIVE: Requires external clock source - Can be a crystal between MCLK1 and MCLK2 pins - Or a CMOS-compatible clock driving MCLK1 pin and MCLK2 left unconnected - Must specify the “clocks†property in device tree when using external clock”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KDhj‰ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjnh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jBjáuh1hþh³hÇh´KBhjOh²hubeh}”(h]”Œclock-configuration”ah ]”h"]”Œclock configuration”ah$]”h&]”uh1hÈhjZh²hh³hÇh´K>ubhÉ)”}”(hhh]”(hÎ)”}”(hŒSPI Interface Requirements”h]”hŒSPI Interface Requirements”…””}”(hj²h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj¯h²hh³hÇh´KJubhÞ)”}”(hŒ3The AD7191 has specific SPI interface requirements:”h]”hŒ3The AD7191 has specific SPI interface requirements:”…””}”(hjÀh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KLhj¯h²hubhÿ)”}”(hhh]”(j)”}”(hŒ@The DOUT/RDY output is dual-purpose and requires SPI bus locking”h]”hÞ)”}”(hjÓh]”hŒ@The DOUT/RDY output is dual-purpose and requires SPI bus locking”…””}”(hjÕh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KNhjÑubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÎh²hh³hÇh´Nubj)”}”(hŒ7DOUT/RDY must be connected to an interrupt-capable GPIO”h]”hÞ)”}”(hjêh]”hŒ7DOUT/RDY must be connected to an interrupt-capable GPIO”…””}”(hjìh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KOhjèubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÎh²hh³hÇh´Nubj)”}”(hŒNThe SPI controller's chip select must be connected to the PDOWN pin of the ADC”h]”hÞ)”}”(hjh]”hŒPThe SPI controller’s chip select must be connected to the PDOWN pin of the ADC”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KPhjÿubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÎh²hh³hÇh´Nubj)”}”(hŒMWhen CS (PDOWN) is high, the device powers down and resets internal circuitry”h]”hÞ)”}”(hjh]”hŒMWhen CS (PDOWN) is high, the device powers down and resets internal circuitry”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KQhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÎh²hh³hÇh´Nubj)”}”(hŒ2SPI mode 3 operation (CPOL=1, CPHA=1) is required ”h]”hÞ)”}”(hŒ1SPI mode 3 operation (CPOL=1, CPHA=1) is required”h]”hŒ1SPI mode 3 operation (CPOL=1, CPHA=1) is required”…””}”(hj1h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KRhj-ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÎh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jBjáuh1hþh³hÇh´KNhj¯h²hubeh}”(h]”Œspi-interface-requirements”ah ]”h"]”Œspi interface requirements”ah$]”h&]”uh1hÈhjZh²hh³hÇh´KJubhÉ)”}”(hhh]”(hÎ)”}”(hŒPower Supply Requirements”h]”hŒPower Supply Requirements”…””}”(hjVh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjSh²hh³hÇh´KUubhÞ)”}”(hŒ1The device requires the following power supplies:”h]”hŒ1The device requires the following power supplies:”…””}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KWhjSh²hubhÿ)”}”(hhh]”(j)”}”(hŒAVdd: Analog power supply”h]”hÞ)”}”(hjwh]”hŒAVdd: Analog power supply”…””}”(hjyh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KYhjuubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrh²hh³hÇh´Nubj)”}”(hŒDVdd: Digital power supply”h]”hÞ)”}”(hjŽh]”hŒDVdd: Digital power supply”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KZhjŒubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrh²hh³hÇh´Nubj)”}”(hŒ*Vref: Reference voltage supply (external) ”h]”hÞ)”}”(hŒ)Vref: Reference voltage supply (external)”h]”hŒ)Vref: Reference voltage supply (external)”…””}”(hj§h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K[hj£ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jBjáuh1hþh³hÇh´KYhjSh²hubhÞ)”}”(hŒ8All power supplies must be specified in the device tree.”h]”hŒ8All power supplies must be specified in the device tree.”…””}”(hjÁh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K]hjSh²hubeh}”(h]”Œpower-supply-requirements”ah ]”h"]”Œpower supply requirements”ah$]”h&]”uh1hÈhjZh²hh³hÇh´KUubeh}”(h]”Œ devicetree”ah ]”h"]”Œ devicetree”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒChannel Configuration”h]”hŒChannel Configuration”…””}”(hjâh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjßh²hh³hÇh´K`ubhÞ)”}”(hŒ#The device provides three channels:”h]”hŒ#The device provides three channels:”…””}”(hjðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kbhjßh²hubhŒenumerated_list”“”)”}”(hhh]”(j)”}”(hŒnTemperature Sensor - 24-bit unsigned - Internal temperature measurement - Temperature in millidegrees Celsius ”h]”hÞ)”}”(hŒmTemperature Sensor - 24-bit unsigned - Internal temperature measurement - Temperature in millidegrees Celsius”h]”hŒmTemperature Sensor - 24-bit unsigned - Internal temperature measurement - Temperature in millidegrees Celsius”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kdhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjh²hh³hÇh´Nubj)”}”(hŒpDifferential Input (AIN1-AIN2) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA ”h]”hÞ)”}”(hŒoDifferential Input (AIN1-AIN2) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA”h]”hŒoDifferential Input (AIN1-AIN2) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kihjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjh²hh³hÇh´Nubj)”}”(hŒpDifferential Input (AIN3-AIN4) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA ”h]”hÞ)”}”(hŒoDifferential Input (AIN3-AIN4) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA”h]”hŒoDifferential Input (AIN3-AIN4) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA”…””}”(hj7h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Knhj3ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ.”uh1jþhjßh²hh³hÇh´Kdubeh}”(h]”Œchannel-configuration”ah ]”h"]”Œchannel configuration”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K`ubhÉ)”}”(hhh]”(hÎ)”}”(hŒBuffer Support”h]”hŒBuffer Support”…””}”(hjah²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj^h²hh³hÇh´KtubhÞ)”}”(hŒ‚This driver supports IIO triggered buffers. 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