€•NŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ/translations/zh_CN/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/zh_TW/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/it_IT/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/ja_JP/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/ko_KR/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ/translations/sp_SP/iio/ad7191”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ%SPDX-License-Identifier: GPL-2.0-only”h]”hŒ%SPDX-License-Identifier: GPL-2.0-only”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1h¡hhhžhhŸŒ8/var/lib/git/docbuild/linux/Documentation/iio/ad7191.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ AD7191 driver”h]”hŒ AD7191 driver”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ paragraph”“”)”}”(hŒ,Device driver for Analog Devices AD7191 ADC.”h]”hŒ,Device driver for Analog Devices AD7191 ADC.”…””}”(hhËhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒSupported devices”h]”hŒSupported devices”…””}”(hhÜhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hhÙhžhhŸh³h K ubhŒ bullet_list”“”)”}”(hhh]”hŒ list_item”“”)”}”(hŒ*`AD7191 `_ ”h]”hÊ)”}”(hŒ)`AD7191 `_”h]”(hŒ reference”“”)”}”(hh÷h]”hŒAD7191”…””}”(hhûhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒAD7191”Œrefuri”Œhttps://www.analog.com/AD7191”uh1hùhhõubhŒtarget”“”)”}”(hŒ ”h]”h}”(h]”Œad7191”ah ]”h"]”Œad7191”ah$]”h&]”Œrefuri”j uh1j Œ referenced”Khhõubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hhñubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhhìhžhhŸh³h Nubah}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1hêhŸh³h K hhÙhžhubhÊ)”}”(hŒ¾The AD7191 is a high precision, low noise, 24-bit Σ-Δ ADC with integrated PGA. It features two differential input channels, an internal temperature sensor, and configurable sampling rates.”h]”hŒ¾The AD7191 is a high precision, low noise, 24-bit Σ-Δ ADC with integrated PGA. It features two differential input channels, an internal temperature sensor, and configurable sampling rates.”…””}”(hj0hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhhÙhžhubeh}”(h]”Œsupported-devices”ah ]”h"]”Œsupported devices”ah$]”h&]”uh1h´hh¶hžhhŸh³h K ubhµ)”}”(hhh]”(hº)”}”(hŒ Devicetree”h]”hŒ Devicetree”…””}”(hjIhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjFhžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒPin Configuration”h]”hŒPin Configuration”…””}”(hjZhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjWhžhhŸh³h KubhÊ)”}”(hXThe driver supports both pin-strapped and GPIO-controlled configurations for ODR (Output Data Rate) and PGA (Programmable Gain Amplifier) settings. These configurations are mutually exclusive - you must use either pin-strapped or GPIO control for each setting, not both.”h]”hXThe driver supports both pin-strapped and GPIO-controlled configurations for ODR (Output Data Rate) and PGA (Programmable Gain Amplifier) settings. These configurations are mutually exclusive - you must use either pin-strapped or GPIO control for each setting, not both.”…””}”(hjhhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhjWhžhubhµ)”}”(hhh]”(hº)”}”(hŒODR Configuration”h]”hŒODR Configuration”…””}”(hjyhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjvhžhhŸh³h KubhÊ)”}”(hŒGThe ODR can be configured either through GPIO control or pin-strapping:”h]”hŒGThe ODR can be configured either through GPIO control or pin-strapping:”…””}”(hj‡hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hjvhžhubhë)”}”(hhh]”(hð)”}”(hŒLWhen using GPIO control, specify the "odr-gpios" property in the device tree”h]”hÊ)”}”(hjšh]”hŒPWhen using GPIO control, specify the “odr-gpios†property in the device tree”…””}”(hjœhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K"hj˜ubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj•hžhhŸh³h Nubhð)”}”(hŒXFor pin-strapped configuration, specify the "adi,odr-value" property in the device tree ”h]”hÊ)”}”(hŒWFor pin-strapped configuration, specify the "adi,odr-value" property in the device tree”h]”hŒ[For pin-strapped configuration, specify the “adi,odr-value†property in the device tree”…””}”(hj³hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K#hj¯ubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj•hžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”j.Œ-”uh1hêhŸh³h K"hjvhžhubhÊ)”}”(hŒAvailable ODR settings:”h]”hŒAvailable ODR settings:”…””}”(hjÎhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K&hjvhžhubhŒ block_quote”“”)”}”(hŒe- 120 Hz (ODR1=0, ODR2=0) - 60 Hz (ODR1=0, ODR2=1) - 50 Hz (ODR1=1, ODR2=0) - 10 Hz (ODR1=1, ODR2=1) ”h]”hë)”}”(hhh]”(hð)”}”(hŒ120 Hz (ODR1=0, ODR2=0)”h]”hÊ)”}”(hjçh]”hŒ120 Hz (ODR1=0, ODR2=0)”…””}”(hjéhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K(hjåubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjâubhð)”}”(hŒ60 Hz (ODR1=0, ODR2=1)”h]”hÊ)”}”(hjþh]”hŒ60 Hz (ODR1=0, ODR2=1)”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K)hjüubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjâubhð)”}”(hŒ50 Hz (ODR1=1, ODR2=0)”h]”hÊ)”}”(hjh]”hŒ50 Hz (ODR1=1, ODR2=0)”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K*hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjâubhð)”}”(hŒ10 Hz (ODR1=1, ODR2=1) ”h]”hÊ)”}”(hŒ10 Hz (ODR1=1, ODR2=1)”h]”hŒ10 Hz (ODR1=1, ODR2=1)”…””}”(hj.hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K+hj*ubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjâubeh}”(h]”h ]”h"]”h$]”h&]”j.jÍuh1hêhŸh³h K(hjÞubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜhŸh³h K(hjvhžhubeh}”(h]”Œodr-configuration”ah ]”h"]”Œodr configuration”ah$]”h&]”uh1h´hjWhžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒPGA Configuration”h]”hŒPGA Configuration”…””}”(hjYhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjVhžhhŸh³h K.ubhÊ)”}”(hŒGThe PGA can be configured either through GPIO control or pin-strapping:”h]”hŒGThe PGA can be configured either through GPIO control or pin-strapping:”…””}”(hjghžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K0hjVhžhubhë)”}”(hhh]”(hð)”}”(hŒLWhen using GPIO control, specify the "pga-gpios" property in the device tree”h]”hÊ)”}”(hjzh]”hŒPWhen using GPIO control, specify the “pga-gpios†property in the device tree”…””}”(hj|hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K2hjxubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjuhžhhŸh³h Nubhð)”}”(hŒXFor pin-strapped configuration, specify the "adi,pga-value" property in the device tree ”h]”hÊ)”}”(hŒWFor pin-strapped configuration, specify the "adi,pga-value" property in the device tree”h]”hŒ[For pin-strapped configuration, specify the “adi,pga-value†property in the device tree”…””}”(hj“hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K3hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjuhžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”j.jÍuh1hêhŸh³h K2hjVhžhubhÊ)”}”(hŒAvailable PGA gain settings:”h]”hŒAvailable PGA gain settings:”…””}”(hj­hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K6hjVhžhubjÝ)”}”(hŒ[- 1x (PGA1=0, PGA2=0) - 8x (PGA1=0, PGA2=1) - 64x (PGA1=1, PGA2=0) - 128x (PGA1=1, PGA2=1) ”h]”hë)”}”(hhh]”(hð)”}”(hŒ1x (PGA1=0, PGA2=0)”h]”hÊ)”}”(hjÄh]”hŒ1x (PGA1=0, PGA2=0)”…””}”(hjÆhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K8hjÂubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj¿ubhð)”}”(hŒ8x (PGA1=0, PGA2=1)”h]”hÊ)”}”(hjÛh]”hŒ8x (PGA1=0, PGA2=1)”…””}”(hjÝhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K9hjÙubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj¿ubhð)”}”(hŒ64x (PGA1=1, PGA2=0)”h]”hÊ)”}”(hjòh]”hŒ64x (PGA1=1, PGA2=0)”…””}”(hjôhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K:hjðubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj¿ubhð)”}”(hŒ128x (PGA1=1, PGA2=1) ”h]”hÊ)”}”(hŒ128x (PGA1=1, PGA2=1)”h]”hŒ128x (PGA1=1, PGA2=1)”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K;hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj¿ubeh}”(h]”h ]”h"]”h$]”h&]”j.jÍuh1hêhŸh³h K8hj»ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜhŸh³h K8hjVhžhubeh}”(h]”Œpga-configuration”ah ]”h"]”Œpga configuration”ah$]”h&]”uh1h´hjWhžhhŸh³h K.ubeh}”(h]”Œpin-configuration”ah ]”h"]”Œpin configuration”ah$]”h&]”uh1h´hjFhžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒClock Configuration”h]”hŒClock Configuration”…””}”(hj>hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj;hžhhŸh³h K>ubhÊ)”}”(hŒ=The AD7191 supports both internal and external clock sources:”h]”hŒ=The AD7191 supports both internal and external clock sources:”…””}”(hjLhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K@hj;hžhubhë)”}”(hhh]”(hð)”}”(hŒSWhen CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property needed)”h]”hÊ)”}”(hŒSWhen CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property needed)”h]”hŒSWhen CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property needed)”…””}”(hjahžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KBhj]ubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjZhžhhŸh³h Nubhð)”}”(hŒêWhen CLKSEL pin is tied HIGH: Requires external clock source - Can be a crystal between MCLK1 and MCLK2 pins - Or a CMOS-compatible clock driving MCLK2 pin - Must specify the "clocks" property in device tree when using external clock ”h]”hÊ)”}”(hŒéWhen CLKSEL pin is tied HIGH: Requires external clock source - Can be a crystal between MCLK1 and MCLK2 pins - Or a CMOS-compatible clock driving MCLK2 pin - Must specify the "clocks" property in device tree when using external clock”h]”hŒíWhen CLKSEL pin is tied HIGH: Requires external clock source - Can be a crystal between MCLK1 and MCLK2 pins - Or a CMOS-compatible clock driving MCLK2 pin - Must specify the “clocks†property in device tree when using external clock”…””}”(hjyhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KDhjuubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjZhžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”j.jÍuh1hêhŸh³h KBhj;hžhubeh}”(h]”Œclock-configuration”ah ]”h"]”Œclock configuration”ah$]”h&]”uh1h´hjFhžhhŸh³h K>ubhµ)”}”(hhh]”(hº)”}”(hŒSPI Interface Requirements”h]”hŒSPI Interface Requirements”…””}”(hjžhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj›hžhhŸh³h KJubhÊ)”}”(hŒ3The AD7191 has specific SPI interface requirements:”h]”hŒ3The AD7191 has specific SPI interface requirements:”…””}”(hj¬hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KLhj›hžhubhë)”}”(hhh]”(hð)”}”(hŒ@The DOUT/RDY output is dual-purpose and requires SPI bus locking”h]”hÊ)”}”(hj¿h]”hŒ@The DOUT/RDY output is dual-purpose and requires SPI bus locking”…””}”(hjÁhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KNhj½ubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjºhžhhŸh³h Nubhð)”}”(hŒ7DOUT/RDY must be connected to an interrupt-capable GPIO”h]”hÊ)”}”(hjÖh]”hŒ7DOUT/RDY must be connected to an interrupt-capable GPIO”…””}”(hjØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KOhjÔubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjºhžhhŸh³h Nubhð)”}”(hŒNThe SPI controller's chip select must be connected to the PDOWN pin of the ADC”h]”hÊ)”}”(hjíh]”hŒPThe SPI controller’s chip select must be connected to the PDOWN pin of the ADC”…””}”(hjïhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KPhjëubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjºhžhhŸh³h Nubhð)”}”(hŒMWhen CS (PDOWN) is high, the device powers down and resets internal circuitry”h]”hÊ)”}”(hjh]”hŒMWhen CS (PDOWN) is high, the device powers down and resets internal circuitry”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KQhjubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjºhžhhŸh³h Nubhð)”}”(hŒ2SPI mode 3 operation (CPOL=1, CPHA=1) is required ”h]”hÊ)”}”(hŒ1SPI mode 3 operation (CPOL=1, CPHA=1) is required”h]”hŒ1SPI mode 3 operation (CPOL=1, CPHA=1) is required”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KRhjubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjºhžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”j.jÍuh1hêhŸh³h KNhj›hžhubeh}”(h]”Œspi-interface-requirements”ah ]”h"]”Œspi interface requirements”ah$]”h&]”uh1h´hjFhžhhŸh³h KJubhµ)”}”(hhh]”(hº)”}”(hŒPower Supply Requirements”h]”hŒPower Supply Requirements”…””}”(hjBhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj?hžhhŸh³h KUubhÊ)”}”(hŒ1The device requires the following power supplies:”h]”hŒ1The device requires the following power supplies:”…””}”(hjPhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KWhj?hžhubhë)”}”(hhh]”(hð)”}”(hŒAVdd: Analog power supply”h]”hÊ)”}”(hjch]”hŒAVdd: Analog power supply”…””}”(hjehžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KYhjaubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj^hžhhŸh³h Nubhð)”}”(hŒDVdd: Digital power supply”h]”hÊ)”}”(hjzh]”hŒDVdd: Digital power supply”…””}”(hj|hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KZhjxubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj^hžhhŸh³h Nubhð)”}”(hŒ*Vref: Reference voltage supply (external) ”h]”hÊ)”}”(hŒ)Vref: Reference voltage supply (external)”h]”hŒ)Vref: Reference voltage supply (external)”…””}”(hj“hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K[hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhj^hžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”j.jÍuh1hêhŸh³h KYhj?hžhubhÊ)”}”(hŒ8All power supplies must be specified in the device tree.”h]”hŒ8All power supplies must be specified in the device tree.”…””}”(hj­hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K]hj?hžhubeh}”(h]”Œpower-supply-requirements”ah ]”h"]”Œpower supply requirements”ah$]”h&]”uh1h´hjFhžhhŸh³h KUubeh}”(h]”Œ devicetree”ah ]”h"]”Œ devicetree”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒChannel Configuration”h]”hŒChannel Configuration”…””}”(hjÎhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjËhžhhŸh³h K`ubhÊ)”}”(hŒ#The device provides three channels:”h]”hŒ#The device provides three channels:”…””}”(hjÜhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KbhjËhžhubhŒenumerated_list”“”)”}”(hhh]”(hð)”}”(hŒnTemperature Sensor - 24-bit unsigned - Internal temperature measurement - Temperature in millidegrees Celsius ”h]”hÊ)”}”(hŒmTemperature Sensor - 24-bit unsigned - Internal temperature measurement - Temperature in millidegrees Celsius”h]”hŒmTemperature Sensor - 24-bit unsigned - Internal temperature measurement - Temperature in millidegrees Celsius”…””}”(hjóhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kdhjïubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjìhžhhŸh³h Nubhð)”}”(hŒpDifferential Input (AIN1-AIN2) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA ”h]”hÊ)”}”(hŒoDifferential Input (AIN1-AIN2) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA”h]”hŒoDifferential Input (AIN1-AIN2) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kihjubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjìhžhhŸh³h Nubhð)”}”(hŒpDifferential Input (AIN3-AIN4) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA ”h]”hÊ)”}”(hŒoDifferential Input (AIN3-AIN4) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA”h]”hŒoDifferential Input (AIN3-AIN4) - 24-bit unsigned - Differential voltage measurement - Configurable gain via PGA”…””}”(hj#hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Knhjubah}”(h]”h ]”h"]”h$]”h&]”uh1hïhjìhžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ.”uh1jêhjËhžhhŸh³h Kdubeh}”(h]”Œchannel-configuration”ah ]”h"]”Œchannel configuration”ah$]”h&]”uh1h´hh¶hžhhŸh³h K`ubhµ)”}”(hhh]”(hº)”}”(hŒBuffer Support”h]”hŒBuffer Support”…””}”(hjMhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjJhžhhŸh³h KtubhÊ)”}”(hŒ‚This driver supports IIO triggered buffers. See Documentation/iio/iio_devbuf.rst for more information about IIO triggered buffers.”h]”hŒ‚This driver supports IIO triggered buffers. See Documentation/iio/iio_devbuf.rst for more information about IIO triggered buffers.”…””}”(hj[hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KvhjJhžhubeh}”(h]”Œbuffer-support”ah ]”h"]”Œbuffer support”ah$]”h&]”uh1h´hh¶hžhhŸh³h Ktubeh}”(h]”Œ ad7191-driver”ah ]”h"]”Œ ad7191 driver”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jœŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jvjsjCj@jjjÈjÅj8j5jSjPj0j-j˜j•j<j9jÀj½jGjDjnjkuŒ nametypes”}”(jv‰jC‰jˆjȉj8‰jS‰j0‰j˜‰j<‰jÀ‰jG‰jn‰uh}”(jsh¶j@hÙjjjÅjFj5jWjPjvj-jVj•j;j9j›j½j?jDjËjkjJuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nhžhub.