sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/iio/ad4695modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/iio/ad4695modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/iio/ad4695modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/iio/ad4695modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/iio/ad4695modnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/pt_BR/iio/ad4695modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/iio/ad4695modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h%SPDX-License-Identifier: GPL-2.0-onlyh]h%SPDX-License-Identifier: GPL-2.0-only}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh8/var/lib/git/docbuild/linux/Documentation/iio/ad4695.rsthKubhsection)}(hhh](htitle)}(h AD4695 driverh]h AD4695 driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h]ADC driver for Analog Devices Inc. AD4695 and similar devices. The module name is ``ad4695``.h](hRADC driver for Analog Devices Inc. AD4695 and similar devices. The module name is }(hhhhhNhNubhliteral)}(h ``ad4695``h]had4695}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hSupported devicesh]hSupported devices}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK ubh)}(h1The following chips are supported by this driver:h]h1The following chips are supported by this driver:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh bullet_list)}(hhh](h list_item)}(h)`AD4695 `_h]h)}(hj)h](h reference)}(hj)h]hAD4695}(hj0hhhNhNubah}(h]h ]h"]h$]h&]nameAD4695refurihttps://www.analog.com/AD4695uh1j.hj+ubhtarget)}(h h]h}(h]ad4695ah ]h"]ad4695ah$]h&]refurij@uh1jA referencedKhj+ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj'ubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubj&)}(h)`AD4696 `_h]h)}(hj_h](j/)}(hj_h]hAD4696}(hjdhhhNhNubah}(h]h ]h"]h$]h&]nameAD4696j?https://www.analog.com/AD4696uh1j.hjaubjB)}(h h]h}(h]ad4696ah ]h"]ad4696ah$]h&]refurijsuh1jAjPKhjaubeh}(h]h ]h"]h$]h&]uh1hhhhKhj]ubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubj&)}(h)`AD4697 `_h]h)}(hjh](j/)}(hjh]hAD4697}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAD4697j?https://www.analog.com/AD4697uh1j.hjubjB)}(h h]h}(h]ad4697ah ]h"]ad4697ah$]h&]refurijuh1jAjPKhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubj&)}(h+`AD4698 `_ h]h)}(h)`AD4698 `_h](j/)}(hjh]hAD4698}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAD4698j?https://www.analog.com/AD4698uh1j.hjubjB)}(h h]h}(h]ad4698ah ]h"]ad4698ah$]h&]refurijuh1jAjPKhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1j hhhKhjhhubeh}(h]supported-devicesah ]h"]supported devicesah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hSupported featuresh]hSupported features}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hSPI wiring modesh]hSPI wiring modes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hEThe driver currently supports the following SPI wiring configuration:h]hEThe driver currently supports the following SPI wiring configuration:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(h 4-wire modeh]h 4-wire mode}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhhhKubh)}(hJIn this mode, CNV and CS are tied together and there is a single SDO line.h]hJIn this mode, CNV and CS are tied together and there is a single SDO line.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hj.hhubh literal_block)}(hXg+-------------+ +-------------+ | CS |<-+------| CS | | CNV |<-+ | | | ADC | | HOST | | | | | | SDI |<--------| SDO | | SDO |-------->| SDI | | SCLK |<--------| SCLK | +-------------+ +-------------+h]hXg+-------------+ +-------------+ | CS |<-+------| CS | | CNV |<-+ | | | ADC | | HOST | | | | | | SDI |<--------| SDO | | SDO |-------->| SDI | | SCLK |<--------| SCLK | +-------------+ +-------------+}hjOsbah}(h]h ]h"]h$]h&]hhƌforcelanguagenonehighlight_args}uh1jMhhhK#hj.hhubh)}(haTo use this mode, in the device tree, omit the ``cnv-gpios`` and ``spi-rx-bus-width`` properties.h](h/To use this mode, in the device tree, omit the }(hjbhhhNhNubh)}(h ``cnv-gpios``h]h cnv-gpios}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbubh and }(hjbhhhNhNubh)}(h``spi-rx-bus-width``h]hspi-rx-bus-width}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbubh properties.}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK/hj.hhubeh}(h] wire-modeah ]h"] 4-wire modeah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hSPI offload wiringh]hSPI offload wiring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK3ubh)}(hDWhen used with a SPI offload, the supported wiring configuration is:h]hDWhen used with a SPI offload, the supported wiring configuration is:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjhhubjN)}(hX/+-------------+ +-------------+ | GP0/BUSY |-------->| TRIGGER | | CS |<--------| CS | | | | | | ADC | | SPI | | | | | | SDI |<--------| SDO | | SDO |-------->| SDI | | SCLK |<--------| SCLK | | | | | | | +-------------+ | CNV |<-----+--| PWM | | | +--| GPIO | +-------------+ +-------------+h]hX/+-------------+ +-------------+ | GP0/BUSY |-------->| TRIGGER | | CS |<--------| CS | | | | | | ADC | | SPI | | | | | | SDI |<--------| SDO | | SDO |-------->| SDI | | SCLK |<--------| SCLK | | | | | | | +-------------+ | CNV |<-----+--| PWM | | | +--| GPIO | +-------------+ +-------------+}hjsbah}(h]h ]h"]h$]h&]hhj]j^j_j`}uh1jMhhhK7hjhhubh)}(hXjIn this case, both the ``cnv-gpios`` and ``pwms`` properties are required. The ``#trigger-source-cells = <2>`` property is also required to connect back to the SPI offload. The SPI offload will have ``trigger-sources`` property with cells to indicate the busy signal and which GPx pin is used, e.g ``<&ad4695 AD4695_TRIGGER_EVENT_BUSY AD4695_TRIGGER_PIN_GP0>``.h](hIn this case, both the }(hjhhhNhNubh)}(h ``cnv-gpios``h]h cnv-gpios}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh and }(hjhhhNhNubh)}(h``pwms``h]hpwms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh properties are required. The }(hjhhhNhNubh)}(h``#trigger-source-cells = <2>``h]h#trigger-source-cells = <2>}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhY property is also required to connect back to the SPI offload. The SPI offload will have }(hjhhhNhNubh)}(h``trigger-sources``h]htrigger-sources}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhP property with cells to indicate the busy signal and which GPx pin is used, e.g }(hjhhhNhNubh)}(h>``<&ad4695 AD4695_TRIGGER_EVENT_BUSY AD4695_TRIGGER_PIN_GP0>``h]h:<&ad4695 AD4695_TRIGGER_EVENT_BUSY AD4695_TRIGGER_PIN_GP0>}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKHhjhhubhseealso)}(h`SPI offload support`_h]h)}(hj6h]j/)}(hj6h]hSPI offload support}(hj;hhhNhNubah}(h]h ]h"]h$]h&]nameSPI offload supportrefidspi-offload-supportuh1j.hj8resolvedKubah}(h]h ]h"]h$]h&]uh1hhhhKNhj4ubah}(h]h ]h"]h$]h&]uh1j2hjhhhhhNubeh}(h]spi-offload-wiringah ]h"]spi offload wiringah$]h&]uh1hhjhhhhhK3jPKubeh}(h]spi-wiring-modesah ]h"]spi wiring modesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hChannel configurationh]hChannel configuration}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihhhhhKQubh)}(hSince the chip supports multiple ways to configure each channel, this must be described in the device tree based on what is actually wired up to the inputs.h]hSince the chip supports multiple ways to configure each channel, this must be described in the device tree based on what is actually wired up to the inputs.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjihhubh)}(h'There are three typical configurations:h]h'There are three typical configurations:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjihhubh)}(hxAn ``INx`` pin is used as the positive input with the ``REFGND``, ``COM`` or the next ``INx`` pin as the negative input.h](hAn }(hjhhhNhNubh)}(h``INx``h]hINx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh, pin is used as the positive input with the }(hjhhhNhNubh)}(h ``REFGND``h]hREFGND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh, }(hjhhhNhNubh)}(h``COM``h]hCOM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh or the next }(hjhhhNhNubh)}(h``INx``h]hINx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh pin as the negative input.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKXhjihhubh)}(hhh](h)}(hPairing with REFGNDh]hPairing with REFGND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK\ubh)}(hEach ``INx`` pin can be used as a pseudo-differential input in conjunction with the ``REFGND`` pin. The device tree will look like this:h](hEach }(hjhhhNhNubh)}(h``INx``h]hINx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhH pin can be used as a pseudo-differential input in conjunction with the }(hjhhhNhNubh)}(h ``REFGND``h]hREFGND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh* pin. The device tree will look like this:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK^hjhhubjN)}(h'channel@0 { reg = <0>; /* IN0 */ };h]h'channel@0 { reg = <0>; /* IN0 */ };}hj/sbah}(h]h ]h"]h$]h&]hhj]j^j_j`}uh1jMhhhKahjhhubh)}(hmIf no other channel properties are needed (e.g. ``adi,no-high-z``), the channel node can be omitted entirely.h](h0If no other channel properties are needed (e.g. }(hj>hhhNhNubh)}(h``adi,no-high-z``h]h adi,no-high-z}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>ubh,), the channel node can be omitted entirely.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKghjhhubh)}(hThis will appear on the IIO bus as the ``voltage0`` channel. The processed value (*raw × scale*) will be the voltage present on the ``IN0`` pin relative to ``REFGND``. (Offset is always 0 when pairing with ``REFGND``.)h](h'This will appear on the IIO bus as the }(hj^hhhNhNubh)}(h ``voltage0``h]hvoltage0}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^ubh channel. The processed value (}(hj^hhhNhNubhemphasis)}(h*raw × scale*h]h raw × scale}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jxhj^ubh%) will be the voltage present on the }(hj^hhhNhNubh)}(h``IN0``h]hIN0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^ubh pin relative to }(hj^hhhNhNubh)}(h ``REFGND``h]hREFGND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^ubh(. (Offset is always 0 when pairing with }(hj^hhhNhNubh)}(h ``REFGND``h]hREFGND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^ubh.)}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKjhjhhubeh}(h]pairing-with-refgndah ]h"]pairing with refgndah$]h&]uh1hhjihhhhhK\ubh)}(hhh](h)}(hPairing with COMh]hPairing with COM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKoubh)}(hEach ``INx`` pin can be used as a pseudo-differential input in conjunction with the ``COM`` pin. The device tree will look like this:h](hEach }(hjhhhNhNubh)}(h``INx``h]hINx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhH pin can be used as a pseudo-differential input in conjunction with the }(hjhhhNhNubh)}(h``COM``h]hCOM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh* pin. The device tree will look like this:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKqhjhhubjN)}(hcom-supply = <&vref_div_2>; channel@1 { reg = <1>; /* IN1 */ common-mode-channel = ; bipolar; };h]hcom-supply = <&vref_div_2>; channel@1 { reg = <1>; /* IN1 */ common-mode-channel = ; bipolar; };}hjsbah}(h]h ]h"]h$]h&]hhj]j^j_j`}uh1jMhhhKthjhhubh)}(hThis will appear on the IIO bus as the ``voltage1`` channel. The processed value (*(raw + offset) × scale*) will be the voltage measured on the ``IN1`` pin relative to ``REFGND``. (The offset is determined by the ``com-supply`` voltage.)h](h'This will appear on the IIO bus as the }(hj"hhhNhNubh)}(h ``voltage1``h]hvoltage1}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubh channel. The processed value (}(hj"hhhNhNubjy)}(h*(raw + offset) × scale*h]h(raw + offset) × scale}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jxhj"ubh&) will be the voltage measured on the }(hj"hhhNhNubh)}(h``IN1``h]hIN1}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubh pin relative to }(hj"hhhNhNubh)}(h ``REFGND``h]hREFGND}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubh#. (The offset is determined by the }(hj"hhhNhNubh)}(h``com-supply``h]h com-supply}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubh voltage.)}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK~hjhhubh)}(hThe macro comes from:h]hThe macro comes from:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjN)}(h+#include h]h+#include }hjsbah}(h]h ]h"]h$]h&]hhj]j^j_j`}uh1jMhhhKhjhhubeh}(h]pairing-with-comah ]h"]pairing with comah$]h&]uh1hhjihhhhhKoubh)}(hhh](h)}(hPairing two INx pinsh]hPairing two INx pins}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hAn even-numbered ``INx`` pin and the following odd-numbered ``INx`` pin can be used as a pseudo-differential input. The device tree for using ``IN2`` as the positive input and ``IN3`` as the negative input will look like this:h](hAn even-numbered }(hjhhhNhNubh)}(h``INx``h]hINx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh$ pin and the following odd-numbered }(hjhhhNhNubh)}(h``INx``h]hINx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhK pin can be used as a pseudo-differential input. The device tree for using }(hjhhhNhNubh)}(h``IN2``h]hIN2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh as the positive input and }(hjhhhNhNubh)}(h``IN3``h]hIN3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh+ as the negative input will look like this:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjN)}(hzin3-supply = <&vref_div_2>; channel@2 { reg = <2>; /* IN2 */ common-mode-channel = <3>; /* IN3 */ bipolar; };h]hzin3-supply = <&vref_div_2>; channel@2 { reg = <2>; /* IN2 */ common-mode-channel = <3>; /* IN3 */ bipolar; };}hjsbah}(h]h ]h"]h$]h&]hhj]j^j_j`}uh1jMhhhKhjhhubh)}(hThis will appear on the IIO bus as the ``voltage2`` channel. The processed value (*(raw + offset) × scale*) will be the voltage measured on the ``IN1`` pin relative to ``REFGND``. (Offset is determined by the ``in3-supply`` voltage.)h](h'This will appear on the IIO bus as the }(hj%hhhNhNubh)}(h ``voltage2``h]hvoltage2}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubh channel. The processed value (}(hj%hhhNhNubjy)}(h*(raw + offset) × scale*h]h(raw + offset) × scale}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jxhj%ubh&) will be the voltage measured on the }(hj%hhhNhNubh)}(h``IN1``h]hIN1}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubh pin relative to }(hj%hhhNhNubh)}(h ``REFGND``h]hREFGND}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubh. (Offset is determined by the }(hj%hhhNhNubh)}(h``in3-supply``h]h in3-supply}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubh voltage.)}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]pairing-two-inx-pinsah ]h"]pairing two inx pinsah$]h&]uh1hhjihhhhhKubeh}(h]channel-configurationah ]h"]channel configurationah$]h&]uh1hhjhhhhhKQubh)}(hhh](h)}(h VCC supplyh]h VCC supply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXVThe chip supports being powered by an external LDO via the ``VCC`` input or an internal LDO via the ``LDO_IN`` input. The driver looks at the device tree to determine which is being used. If ``ldo-supply`` is present, then the internal LDO is used. If ``vcc-supply`` is present, then the external LDO is used and the internal LDO is disabled.h](h;The chip supports being powered by an external LDO via the }(hjhhhNhNubh)}(h``VCC``h]hVCC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh" input or an internal LDO via the }(hjhhhNhNubh)}(h ``LDO_IN``h]hLDO_IN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhQ input. The driver looks at the device tree to determine which is being used. If }(hjhhhNhNubh)}(h``ldo-supply``h]h ldo-supply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh/ is present, then the internal LDO is used. If }(hjhhhNhNubh)}(h``vcc-supply``h]h vcc-supply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhL is present, then the external LDO is used and the internal LDO is disabled.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] vcc-supplyah ]h"] vcc supplyah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hReference voltageh]hReference voltage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hXThe chip supports an external reference voltage via the ``REF`` input or an internal buffered reference voltage via the ``REFIN`` input. The driver looks at the device tree to determine which is being used. If ``ref-supply`` is present, then the external reference voltage is used and the internal buffer is disabled. If ``refin-supply`` is present, then the internal buffered reference voltage is used.h](h8The chip supports an external reference voltage via the }(hjhhhNhNubh)}(h``REF``h]hREF}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh9 input or an internal buffered reference voltage via the }(hjhhhNhNubh)}(h ``REFIN``h]hREFIN}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhQ input. The driver looks at the device tree to determine which is being used. If }(hjhhhNhNubh)}(h``ref-supply``h]h ref-supply}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubha is present, then the external reference voltage is used and the internal buffer is disabled. If }(hjhhhNhNubh)}(h``refin-supply``h]h refin-supply}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhB is present, then the internal buffered reference voltage is used.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]reference-voltageah ]h"]reference voltageah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hGain/offset calibrationh]hGain/offset calibration}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hhhhhKubh)}(hSystem calibration is supported using the channel gain and offset registers via the ``calibscale`` and ``calibbias`` attributes respectively.h](hTSystem calibration is supported using the channel gain and offset registers via the }(hjhhhNhNubh)}(h``calibscale``h]h calibscale}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh and }(hjhhhNhNubh)}(h ``calibbias``h]h calibbias}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh attributes respectively.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj{hhubeh}(h]gain-offset-calibrationah ]h"]gain/offset calibrationah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h Oversamplingh]h Oversampling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXYThe chip supports per-channel oversampling when SPI offload is being used, with available oversampling ratios (OSR) of 1 (default), 4, 16, and 64. Enabling oversampling on a channel raises the effective number of bits of sampled data to 17 (OSR == 4), 18 (16), or 19 (64), respectively. This can be set via the ``oversampling_ratio`` attribute.h](hX8The chip supports per-channel oversampling when SPI offload is being used, with available oversampling ratios (OSR) of 1 (default), 4, 16, and 64. Enabling oversampling on a channel raises the effective number of bits of sampled data to 17 (OSR == 4), 18 (16), or 19 (64), respectively. This can be set via the }(hjhhhNhNubh)}(h``oversampling_ratio``h]hoversampling_ratio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh attribute.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXSetting the oversampling ratio for a channel also changes the sample rate for that channel, since it requires multiple conversions per 1 sample. Specifically, the new sampling frequency is the PWM sampling frequency divided by the particular OSR. This is set automatically by the driver when setting the ``oversampling_ratio`` attribute. For example, if the device's current ``sampling_frequency`` is 10000 and an OSR of 4 is set on channel ``voltage0``, the new reported sampling rate for that channel will be 2500 (ignoring PWM API rounding), while all others will remain at 10000. Subsequently setting the sampling frequency to a higher value on that channel will adjust the CNV trigger period for all channels, e.g. if ``voltage0``'s sampling frequency is adjusted from 2500 (with an OSR of 4) to 10000, the value reported by ``in_voltage0_sampling_frequency`` will be 10000, but all other channels will now report 40000.h](hX0Setting the oversampling ratio for a channel also changes the sample rate for that channel, since it requires multiple conversions per 1 sample. Specifically, the new sampling frequency is the PWM sampling frequency divided by the particular OSR. This is set automatically by the driver when setting the }(hjhhhNhNubh)}(h``oversampling_ratio``h]hoversampling_ratio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh3 attribute. For example, if the device’s current }(hjhhhNhNubh)}(h``sampling_frequency``h]hsampling_frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh, is 10000 and an OSR of 4 is set on channel }(hjhhhNhNubh)}(h ``voltage0``h]hvoltage0}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhX, the new reported sampling rate for that channel will be 2500 (ignoring PWM API rounding), while all others will remain at 10000. Subsequently setting the sampling frequency to a higher value on that channel will adjust the CNV trigger period for all channels, e.g. if }(hjhhhNhNubh)}(h ``voltage0``h]hvoltage0}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubha’s sampling frequency is adjusted from 2500 (with an OSR of 4) to 10000, the value reported by }(hjhhhNhNubh)}(h"``in_voltage0_sampling_frequency``h]hin_voltage0_sampling_frequency}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh= will be 10000, but all other channels will now report 40000.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hFor simplicity, the sampling frequency of the device should be set (considering the highest desired OSR value to be used) first, before configuring oversampling for specific channels.h]hFor simplicity, the sampling frequency of the device should be set (considering the highest desired OSR value to be used) first, before configuring oversampling for specific channels.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] oversamplingah ]h"] oversamplingah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hUnimplemented featuresh]hUnimplemented features}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhhhhhKubj!)}(hhh](j&)}(hAdditional wiring modesh]h)}(hjh]hAdditional wiring modes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hjhhhhhNubj&)}(hThreshold eventsh]h)}(hjh]hThreshold events}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hjhhhhhNubj&)}(h GPIO supporth]h)}(hjh]h GPIO support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hjhhhhhNubj&)}(h CRC support h]h)}(h CRC supporth]h CRC support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hjhhhhhNubeh}(h]h ]h"]h$]h&]j-uh1j hhhKhjuhhubeh}(h]unimplemented-featuresah ]h"]unimplemented featuresah$]h&]uh1hhjhhhhhKubeh}(h]supported-featuresah ]h"]supported featuresah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSPI offload supporth]hSPI offload support}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hTo be able to achieve the maximum sample rate, the driver can be used with the `AXI SPI Engine`_ to provide SPI offload support.h](hOTo be able to achieve the maximum sample rate, the driver can be used with the }(hj hhhNhNubj/)}(h`AXI SPI Engine`_h]hAXI SPI Engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameAXI SPI Enginej?Dhttp://analogdevicesinc.github.io/hdl/projects/ad469x_fmc/index.htmluh1j.hj jLKubh to provide SPI offload support.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjB)}(hX.. _AXI SPI Engine: http://analogdevicesinc.github.io/hdl/projects/ad469x_fmc/index.htmlh]h}(h]axi-spi-engineah ]h"]axi spi engineah$]h&]j?j& uh1jAhKhjhhhhjPKubj3)}(h`SPI offload wiring`_h]h)}(hj? h]j/)}(hj? h]hSPI offload wiring}(hjD hhhNhNubah}(h]h ]h"]h$]h&]nameSPI offload wiringjJj[uh1j.hjA jLKubah}(h]h ]h"]h$]h&]uh1hhhhKhj= ubah}(h]h ]h"]h$]h&]uh1j2hjhhhhhNubh)}(hBWhen SPI offload is being used, some attributes will be different.h]hBWhen SPI offload is being used, some attributes will be different.}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj!)}(hhh](j&)}(h!``trigger`` directory is removed.h]h)}(hjr h](h)}(h ``trigger``h]htrigger}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt ubh directory is removed.}(hjt hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjp ubah}(h]h ]h"]h$]h&]uh1j%hjm hhhhhNubj&)}(hT``in_voltage0_sampling_frequency`` attributes are added for setting the sample rate.h]h)}(hT``in_voltage0_sampling_frequency`` attributes are added for setting the sample rate.h](h)}(h"``in_voltage0_sampling_frequency``h]hin_voltage0_sampling_frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh2 attributes are added for setting the sample rate.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j%hjm hhhhhNubj&)}(hc``in_voltage0_sampling_frequency_available`` attributes are added for querying the max sample rate.h]h)}(hc``in_voltage0_sampling_frequency_available`` attributes are added for querying the max sample rate.h](h)}(h,``in_voltage0_sampling_frequency_available``h]h(in_voltage0_sampling_frequency_available}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh7 attributes are added for querying the max sample rate.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j%hjm hhhhhNubj&)}(h!``timestamp`` channel is removed.h]h)}(hj h](h)}(h ``timestamp``h]h timestamp}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh channel is removed.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j%hjm hhhhhNubj&)}(h{Buffer data format may be different compared to when offload is not used, e.g. the ``buffer0/in_voltage0_type`` attribute. h]h)}(hzBuffer data format may be different compared to when offload is not used, e.g. the ``buffer0/in_voltage0_type`` attribute.h](hSBuffer data format may be different compared to when offload is not used, e.g. the }(hj hhhNhNubh)}(h``buffer0/in_voltage0_type``h]hbuffer0/in_voltage0_type}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh attribute.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j%hjm hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1j hhhKhjhhubeh}(h]jKah ]h"]spi offload supportah$]h&]uh1hhhhhhhhKjPKubh)}(hhh](h)}(hDevice buffersh]hDevice buffers}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj= hhhhhKubh)}(hThis driver supports hardware triggered buffers. This uses the "advanced sequencer" feature of the chip to trigger a burst of conversions.h]hThis driver supports hardware triggered buffers. This uses the “advanced sequencer” feature of the chip to trigger a burst of conversions.}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj= hhubh)}(h8Also see :doc:`iio_devbuf` for more general information.h](h Also see }(hj\ hhhNhNubh)}(h:doc:`iio_devbuf`h]hinline)}(hjf h]h iio_devbuf}(hjj hhhNhNubah}(h]h ](xrefstdstd-doceh"]h$]h&]uh1jh hjd ubah}(h]h ]h"]h$]h&]refdoc iio/ad4695 refdomainju reftypedoc refexplicitrefwarn reftarget iio_devbufuh1hhhhKhj\ ubh for more general information.}(hj\ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj= hhubh)}(hhh](h)}(h(Effective sample rate for buffered readsh]h(Effective sample rate for buffered reads}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hWhen SPI offload is not used, the sample rate is determined by the trigger that is manually configured in userspace. All enabled channels will be read in a burst when the trigger is received.h]hWhen SPI offload is not used, the sample rate is determined by the trigger that is manually configured in userspace. All enabled channels will be read in a burst when the trigger is received.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hX~When SPI offload is used, the sample rate is configured per channel. All channels will have the same rate, so only one ``in_voltageY_sampling_frequency`` attribute needs to be set. Since this rate determines the delay between each individual conversion, the effective sample rate for each sample is actually the sum of the periods of each enabled channel in a buffered read. In other words, it is the value of the ``in_voltageY_sampling_frequency`` attribute divided by the number of enabled channels. So if 4 channels are enabled, with the ``in_voltageY_sampling_frequency`` attributes set to 1 MHz, the effective sample rate is 250 kHz.h](hwWhen SPI offload is used, the sample rate is configured per channel. All channels will have the same rate, so only one }(hj hhhNhNubh)}(h"``in_voltageY_sampling_frequency``h]hin_voltageY_sampling_frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubhX attribute needs to be set. Since this rate determines the delay between each individual conversion, the effective sample rate for each sample is actually the sum of the periods of each enabled channel in a buffered read. In other words, it is the value of the }(hj hhhNhNubh)}(h"``in_voltageY_sampling_frequency``h]hin_voltageY_sampling_frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh] attribute divided by the number of enabled channels. So if 4 channels are enabled, with the }(hj hhhNhNubh)}(h"``in_voltageY_sampling_frequency``h]hin_voltageY_sampling_frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh? attributes set to 1 MHz, the effective sample rate is 250 kHz.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hXWith oversampling enabled, the effective sample rate also depends on the OSR assigned to each channel. For example, if one of the 4 channels mentioned in the previous case is configured with an OSR of 4, the effective sample rate for that channel becomes (1 MHz / 4 ) = 250 kHz. The effective sample rate for all four channels is then 1 / ( (3 / 1 MHz) + ( 1 / 250 kHz) ) ~= 142.9 kHz. Note that in this case "sample" refers to one read of all enabled channels (i.e. one full cycle through the auto-sequencer).h]hXWith oversampling enabled, the effective sample rate also depends on the OSR assigned to each channel. For example, if one of the 4 channels mentioned in the previous case is configured with an OSR of 4, the effective sample rate for that channel becomes (1 MHz / 4 ) = 250 kHz. The effective sample rate for all four channels is then 1 / ( (3 / 1 MHz) + ( 1 / 250 kHz) ) ~= 142.9 kHz. Note that in this case “sample” refers to one read of all enabled channels (i.e. one full cycle through the auto-sequencer).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubeh}(h](effective-sample-rate-for-buffered-readsah ]h"](effective sample rate for buffered readsah$]h&]uh1hhj= hhhhhKubeh}(h]device-buffersah ]h"]device buffersah$]h&]uh1hhhhhhhhKubeh}(h] ad4695-driverah ]h"] ad4695 driverah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj? error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}(spi offload support]j;aaxi spi engine]j aspi offload wiring]jD aurefids}nameids}(j j jjjLjIj}jzjjjjjjjfjcjjj^j[jjjjjjjjj jjxjujjjrjojjj: jKj: j7 j j j j u nametypes}(j jjLj}jjjjfjj^jjjjj jxjjrjj: j: j j uh}(j hjjjIjCjzjtjjjjjjjcjjj.j[jjjijjjjjjjjjuj jj{jojjjujKjj7 j1 j j= j j u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.