sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/iio/ad4030modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/pt_BR/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/iio/ad4030modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h%SPDX-License-Identifier: GPL-2.0-onlyh]h%SPDX-License-Identifier: GPL-2.0-only}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh8/var/lib/git/docbuild/linux/Documentation/iio/ad4030.rsthKubhsection)}(hhh](htitle)}(h AD4030 driverh]h AD4030 driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h]ADC driver for Analog Devices Inc. AD4030 and similar devices. The module name is ``ad4030``.h](hRADC driver for Analog Devices Inc. AD4030 and similar devices. The module name is }(hhhhhNhNubhliteral)}(h ``ad4030``h]had4030}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hSupported devicesh]hSupported devices}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK ubh)}(h1The following chips are supported by this driver:h]h1The following chips are supported by this driver:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh bullet_list)}(hhh](h list_item)}(h/`AD4030-24 `_h]h)}(hj)h](h reference)}(hj)h]h AD4030-24}(hj0hhhNhNubah}(h]h ]h"]h$]h&]name AD4030-24refuri https://www.analog.com/AD4030-24uh1j.hj+ubhtarget)}(h# h]h}(h] ad4030-24ah ]h"] ad4030-24ah$]h&]refurij@uh1jA referencedKhj+ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj'ubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubj&)}(h/`AD4032-24 `_h]h)}(hj_h](j/)}(hj_h]h AD4032-24}(hjdhhhNhNubah}(h]h ]h"]h$]h&]name AD4032-24j? https://www.analog.com/AD4032-24uh1j.hjaubjB)}(h# h]h}(h] ad4032-24ah ]h"] ad4032-24ah$]h&]refurijsuh1jAjPKhjaubeh}(h]h ]h"]h$]h&]uh1hhhhKhj]ubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubj&)}(h/`AD4630-16 `_h]h)}(hjh](j/)}(hjh]h AD4630-16}(hjhhhNhNubah}(h]h ]h"]h$]h&]name AD4630-16j? https://www.analog.com/AD4630-16uh1j.hjubjB)}(h# h]h}(h] ad4630-16ah ]h"] ad4630-16ah$]h&]refurijuh1jAjPKhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubj&)}(h/`AD4630-24 `_h]h)}(hjh](j/)}(hjh]h AD4630-24}(hjhhhNhNubah}(h]h ]h"]h$]h&]name AD4630-24j? https://www.analog.com/AD4630-24uh1j.hjubjB)}(h# h]h}(h] ad4630-24ah ]h"] ad4630-24ah$]h&]refurijuh1jAjPKhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubj&)}(h/`AD4632-16 `_h]h)}(hjh](j/)}(hjh]h AD4632-16}(hjhhhNhNubah}(h]h ]h"]h$]h&]name AD4632-16j? https://www.analog.com/AD4632-16uh1j.hjubjB)}(h# h]h}(h] ad4632-16ah ]h"] ad4632-16ah$]h&]refurijuh1jAjPKhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubj&)}(h0`AD4632-24 `_ h]h)}(h/`AD4632-24 `_h](j/)}(hj#h]h AD4632-24}(hj%hhhNhNubah}(h]h ]h"]h$]h&]name AD4632-24j? https://www.analog.com/AD4632-24uh1j.hj!ubjB)}(h# h]h}(h] ad4632-24ah ]h"] ad4632-24ah$]h&]refurij4uh1jAjPKhj!ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hj"hhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1j hhhKhjhhubeh}(h]supported-devicesah ]h"]supported devicesah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h IIO channelsh]h IIO channels}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhKubh)}(hQEach "hardware" channel as described in the datasheet is split in 2 IIO channels:h]hUEach “hardware” channel as described in the datasheet is split in 2 IIO channels:}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj^hhubj!)}(hhh](j&)}(h%One channel for the differential datah]h)}(hjh]h%One channel for the differential data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hj}hhhhhNubj&)}(h!One channel for the common byte. h]h)}(h One channel for the common byte.h]h One channel for the common byte.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hj}hhhhhNubeh}(h]h ]h"]h$]h&]jT-uh1j hhhKhj^hhubh)}(hMThe possible IIO channels depending on the numbers of "hardware" channel are:h]hQThe possible IIO channels depending on the numbers of “hardware” channel are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj^hhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(h 1 channel ADCh]h 1 channel ADC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h2 channels ADCh]h2 channels ADC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubhtbody)}(hhh]j)}(hhh](j)}(hhh]j!)}(hhh](j&)}(h voltage0-voltage1 (differential)h]h)}(hj:h]h voltage0-voltage1 (differential)}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hj8ubah}(h]h ]h"]h$]h&]uh1j%hj5ubj&)}(hvoltage2 (common-mode) h]h)}(hvoltage2 (common-mode)h]hvoltage2 (common-mode)}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjOubah}(h]h ]h"]h$]h&]uh1j%hj5ubeh}(h]h ]h"]h$]h&]jTjuh1j hhhK%hj2ubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(hhh]j!)}(hhh](j&)}(h voltage0-voltage1 (differential)h]h)}(hj{h]h voltage0-voltage1 (differential)}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjyubah}(h]h ]h"]h$]h&]uh1j%hjvubj&)}(h voltage2-voltage3 (differential)h]h)}(hjh]h voltage2-voltage3 (differential)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1j%hjvubj&)}(hvoltage4 (common-mode)h]h)}(hjh]hvoltage4 (common-mode)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1j%hjvubj&)}(hvoltage5 (common-mode)h]h)}(hjh]hvoltage5 (common-mode)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1j%hjvubeh}(h]h ]h"]h$]h&]jTjuh1j hhhK%hjsubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1j*hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhj^hhhNhNubh)}(hhh](h)}(hLabelsh]hLabels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK,ubh)}(hFor ease of use, the IIO channels provide a label. For a differential channel, the label is ``differentialN`` where ``N`` is the "hardware" channel id. For a common-mode channel, the label is ``common-modeN`` where ``N`` is the "hardware" channel id.h](h\For ease of use, the IIO channels provide a label. For a differential channel, the label is }(hj hhhNhNubh)}(h``differentialN``h]h differentialN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh where }(hj hhhNhNubh)}(h``N``h]hN}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubhK is the “hardware” channel id. For a common-mode channel, the label is }(hj hhhNhNubh)}(h``common-modeN``h]h common-modeN}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh where }hj sbh)}(h``N``h]hN}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh" is the “hardware” channel id.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK.hjhhubh)}(hThe possible labels are:h]hThe possible labels are:}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjhhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjrubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjrubj)}(hhh]j)}(hhh](j)}(hhh]h)}(h 1 channel ADCh]h 1 channel ADC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h2 channels ADCh]h2 channels ADC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjrubj+)}(hhh]j)}(hhh](j)}(hhh]j!)}(hhh](j&)}(h differential0h]h)}(hjh]h differential0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1j%hjubj&)}(hcommon-mode0 h]h)}(h common-mode0h]h common-mode0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1j%hjubeh}(h]h ]h"]h$]h&]jTjuh1j hhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j!)}(hhh](j&)}(h differential0h]h)}(hjh]h differential0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1j%hjubj&)}(h differential1h]h)}(hj/h]h differential1}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hj-ubah}(h]h ]h"]h$]h&]uh1j%hjubj&)}(h common-mode0h]h)}(hjFh]h common-mode0}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjDubah}(h]h ]h"]h$]h&]uh1j%hjubj&)}(h common-mode1h]h)}(hj]h]h common-mode1}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hj[ubah}(h]h ]h"]h$]h&]uh1j%hjubeh}(h]h ]h"]h$]h&]jTjuh1j hhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j*hjrubeh}(h]h ]h"]h$]h&]colsKuh1jhjoubah}(h]h ]h"]h$]h&]uh1jhjhhhNhNubeh}(h]labelsah ]h"]labelsah$]h&]uh1hhj^hhhhhK,ubeh}(h] iio-channelsah ]h"] iio channelsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSupported featuresh]hSupported features}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK?ubh)}(hhh](h)}(hSPI wiring modesh]hSPI wiring modes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKBubh)}(hFThe driver currently supports the following SPI wiring configurations:h]hFThe driver currently supports the following SPI wiring configurations:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjhhubh)}(hhh](h)}(h One lane modeh]h One lane mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKGubh)}(hIn this mode, each channel has its own SDO line to send the conversion results. At the moment this mode can only be used on AD4030 which has one channel so only one SDO line is used.h]hIn this mode, each channel has its own SDO line to send the conversion results. At the moment this mode can only be used on AD4030 which has one channel so only one SDO line is used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjhhubh literal_block)}(hXg+-------------+ +-------------+ | ADC | | HOST | | | | | | CNV |<--------| CNV | | CS |<--------| CS | | SDI |<--------| SDO | | SDO0 |-------->| SDI | | SCLK |<--------| SCLK | +-------------+ +-------------+h]hXg+-------------+ +-------------+ | ADC | | HOST | | | | | | CNV |<--------| CNV | | CS |<--------| CS | | SDI |<--------| SDO | | SDO0 |-------->| SDI | | SCLK |<--------| SCLK | +-------------+ +-------------+}hjsbah}(h]h ]h"]h$]h&]hhƌforcelanguagenonehighlight_args}uh1jhhhKMhjhhubeh}(h] one-lane-modeah ]h"] one lane modeah$]h&]uh1hhjhhhhhKGjPKubh)}(hhh](h)}(hInterleaved modeh]hInterleaved mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKZubh)}(hIn this mode, both channels conversion results are bit interleaved one SDO line. As such the wiring is the same as `One lane mode`_.h](hsIn this mode, both channels conversion results are bit interleaved one SDO line. As such the wiring is the same as }(hj$hhhNhNubj/)}(h`One lane mode`_h]h One lane mode}(hj,hhhNhNubah}(h]h ]h"]h$]h&]name One lane moderefidj uh1j.hj$resolvedKubh.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK\hjhhubeh}(h]interleaved-modeah ]h"]interleaved modeah$]h&]uh1hhjhhhhhKZubh)}(hhh](h)}(hSPI offload wiringh]hSPI offload wiring}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhhhhhK`ubj)}(hXW+-------------+ +-------------+ | CNV |<-----+--| GPIO | | | +--| PWM0 | | | | | | | +--| PWM1 | | | | +-------------+ | | +->| TRIGGER | | CS |<--------| CS | | | | | | ADC | | SPI | | | | | | SDI |<--------| SDO | | SDO |-------->| SDI | | SCLK |<--------| SCLK | +-------------+ +-------------+h]hXW+-------------+ +-------------+ | CNV |<-----+--| GPIO | | | +--| PWM0 | | | | | | | +--| PWM1 | | | | +-------------+ | | +->| TRIGGER | | CS |<--------| CS | | | | | | ADC | | SPI | | | | | | SDI |<--------| SDO | | SDO |-------->| SDI | | SCLK |<--------| SCLK | +-------------+ +-------------+}hjasbah}(h]h ]h"]h$]h&]hhjjjj }uh1jhhhKbhjPhhubh)}(hX In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required. The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin. The SPI offload will have a ``trigger-sources`` property to indicate the SPI offload (PWM) trigger source. For AD4030 and similar ADCs, there are two possible data transfer zones for sample N. One of them (zone 1) starts after the data conversion for sample N is complete while the other one (zone 2) starts 9.8 nanoseconds after the rising edge of CNV for sample N + 1.h](hIn this mode, both the }(hjphhhNhNubh)}(h ``cnv-gpios``h]h cnv-gpios}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpubh and a }(hjphhhNhNubh)}(h``pwms``h]hpwms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpubh properties are required. The }(hjphhhNhNubh)}(h``pwms``h]hpwms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpubh^ property specifies the PWM that is connected to the ADC CNV pin. The SPI offload will have a }(hjphhhNhNubh)}(h``trigger-sources``h]htrigger-sources}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpubhXC property to indicate the SPI offload (PWM) trigger source. For AD4030 and similar ADCs, there are two possible data transfer zones for sample N. One of them (zone 1) starts after the data conversion for sample N is complete while the other one (zone 2) starts 9.8 nanoseconds after the rising edge of CNV for sample N + 1.}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKthjPhhubh)}(hXThe configuration depicted in the above diagram is intended to perform data transfer in zone 2. To achieve high sample rates while meeting ADC timing requirements, an offset is added between the rising edges of PWM0 and PWM1 to delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This requires a specialized PWM controller that can provide such an offset. The `AD4630-FMC HDL project`_, for example, can be configured to sample AD4030 data during zone 2 data read window.h](hXxThe configuration depicted in the above diagram is intended to perform data transfer in zone 2. To achieve high sample rates while meeting ADC timing requirements, an offset is added between the rising edges of PWM0 and PWM1 to delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This requires a specialized PWM controller that can provide such an offset. The }(hjhhhNhNubj/)}(h`AD4630-FMC HDL project`_h]hAD4630-FMC HDL project}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAD4630-FMC HDL projectj?Ehttps://analogdevicesinc.github.io/hdl/projects/ad4630_fmc/index.htmluh1j.hjj=KubhV, for example, can be configured to sample AD4030 data during zone 2 data read window.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK|hjPhhubjB)}(ha.. _AD4630-FMC HDL project: https://analogdevicesinc.github.io/hdl/projects/ad4630_fmc/index.htmlh]h}(h]ad4630-fmc-hdl-projectah ]h"]ad4630-fmc hdl projectah$]h&]j?juh1jAhKhjPhhhhjPKubeh}(h]spi-offload-wiringah ]h"]spi offload wiringah$]h&]uh1hhjhhhhhK`ubeh}(h]spi-wiring-modesah ]h"]spi wiring modesah$]h&]uh1hhjhhhhhKBubh)}(hhh](h)}(hSPI Clock modeh]hSPI Clock mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h(Only the SPI clocking mode is supported.h]h(Only the SPI clocking mode is supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]spi-clock-modeah ]h"]spi clock modeah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h Output modesh]h Output modes}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhhhKubh)}(hX6There are more exposed IIO channels than channels as describe in the devices datasheet. This is due to the `Differential data + common-mode`_ encoding 2 types of information in one conversion result. As such a "device" channel provides 2 IIO channels, one for the differential data and one for the common byte.h](hkThere are more exposed IIO channels than channels as describe in the devices datasheet. This is due to the }(hj=hhhNhNubj/)}(h"`Differential data + common-mode`_h]hDifferential data + common-mode}(hjEhhhNhNubah}(h]h ]h"]h$]h&]nameDifferential data + common-modej<differential-data-common-modeuh1j.hj=j=Kubh encoding 2 types of information in one conversion result. As such a “device” channel provides 2 IIO channels, one for the differential data and one for the common byte.}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj,hhubh)}(hhh](h)}(hDifferential datah]hDifferential data}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hhhhhKubh)}(hThis mode is selected when:h]hThis mode is selected when:}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj`hhubj!)}(hhh](j&)}(h9Only differential channels are enabled in a buffered readh]h)}(hjh]h9Only differential channels are enabled in a buffered read}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hjhhhhhNubj&)}(h#Oversampling attribute is set to 1 h]h)}(h"Oversampling attribute is set to 1h]h"Oversampling attribute is set to 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hjhhhhhNubeh}(h]h ]h"]h$]h&]jTjuh1j hhhKhj`hhubeh}(h]differential-dataah ]h"]differential dataah$]h&]uh1hhj,hhhhhKubh)}(hhh](h)}(hDifferential data + common-modeh]hDifferential data + common-mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThis mode is selected when:h]hThis mode is selected when:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj!)}(hhh](j&)}(hDDifferential and common-mode channels are enabled in a buffered readh]h)}(hjh]hDDifferential and common-mode channels are enabled in a buffered read}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hjhhhhhNubj&)}(h#Oversampling attribute is set to 1 h]h)}(h"Oversampling attribute is set to 1h]h"Oversampling attribute is set to 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j%hjhhhhhNubeh}(h]h ]h"]h$]h&]jTjuh1j hhhKhjhhubh)}(hlFor the 24-bits chips, this mode is also available with 16-bits differential data but is not selectable yet.h]hlFor the 24-bits chips, this mode is also available with 16-bits differential data but is not selectable yet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]jUah ]h"]differential data + common-modeah$]h&]uh1hhj,hhhhhKjPKubh)}(hhh](h)}(hAveraged differential datah]hAveraged differential data}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhKubh)}(hThis mode is selected when:h]hThis mode is selected when:}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+hhubj!)}(hhh](j&)}(hBOnly differential channels are selected enabled in a buffered readh]h)}(hjOh]hBOnly differential channels are selected enabled in a buffered read}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjMubah}(h]h ]h"]h$]h&]uh1j%hjJhhhhhNubj&)}(h)Oversampling attribute is greater than 1 h]h)}(h(Oversampling attribute is greater than 1h]h(Oversampling attribute is greater than 1}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdubah}(h]h ]h"]h$]h&]uh1j%hjJhhhhhNubeh}(h]h ]h"]h$]h&]jTjuh1j hhhKhj+hhubeh}(h]averaged-differential-dataah ]h"]averaged differential dataah$]h&]uh1hhj,hhhhhKubeh}(h] output-modesah ]h"] output modesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hDigital Gain and Offseth]hDigital Gain and Offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hEach differential data channel has a 16-bits unsigned configurable hardware gain applied to it. By default it's equal to 1. Note that applying gain can cause numerical saturation.h]hEach differential data channel has a 16-bits unsigned configurable hardware gain applied to it. By default it’s equal to 1. Note that applying gain can cause numerical saturation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX Each differential data channel has a signed configurable hardware offset. For the ADCs ending in ``-24``, the gain is encoded on 24-bits. Likewise, the ADCs ending in ``-16`` have a gain encoded on 16-bits. Note that applying an offset can cause numerical saturation.h](haEach differential data channel has a signed configurable hardware offset. For the ADCs ending in }(hjhhhNhNubh)}(h``-24``h]h-24}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh?, the gain is encoded on 24-bits. Likewise, the ADCs ending in }(hjhhhNhNubh)}(h``-16``h]h-16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh] have a gain encoded on 16-bits. Note that applying an offset can cause numerical saturation.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhThe final differential data returned by the ADC is computed by first applying the gain, then the offset.h]hhThe final differential data returned by the ADC is computed by first applying the gain, then the offset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hyThe gain is controlled by the ``calibscale`` IIO attribute while the offset is controlled by the ``calibbias`` attribute.h](hThe gain is controlled by the }(hjhhhNhNubh)}(h``calibscale``h]h calibscale}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh5 IIO attribute while the offset is controlled by the }(hjhhhNhNubh)}(h ``calibbias``h]h calibbias}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh attribute.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]digital-gain-and-offsetah ]h"]digital gain and offsetah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hReference voltageh]hReference voltage}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+ hhhhhKubh)}(hXThe chip supports an external reference voltage via the ``REF`` input or an internal buffered reference voltage via the ``REFIN`` input. The driver looks at the device tree to determine which is being used. If ``ref-supply`` is present, then the external reference voltage is used and the internal buffer is disabled. If ``refin-supply`` is present, then the internal buffered reference voltage is used.h](h8The chip supports an external reference voltage via the }(hj< hhhNhNubh)}(h``REF``h]hREF}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj< ubh9 input or an internal buffered reference voltage via the }(hj< hhhNhNubh)}(h ``REFIN``h]hREFIN}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj< ubhQ input. The driver looks at the device tree to determine which is being used. If }(hj< hhhNhNubh)}(h``ref-supply``h]h ref-supply}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj< ubha is present, then the external reference voltage is used and the internal buffer is disabled. If }(hj< hhhNhNubh)}(h``refin-supply``h]h refin-supply}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj< ubhB is present, then the internal buffered reference voltage is used.}(hj< hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj+ hhubeh}(h]reference-voltageah ]h"]reference voltageah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hReseth]hReset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hBoth hardware and software reset are supported. The driver looks first at the device tree to see if the ``reset-gpio`` is populated. If not present, the driver will fallback to a software reset by wiring to the device's registers.h](hhBoth hardware and software reset are supported. The driver looks first at the device tree to see if the }(hj hhhNhNubh)}(h``reset-gpio``h]h reset-gpio}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubhr is populated. If not present, the driver will fallback to a software reset by wiring to the device’s registers.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]resetah ]h"]resetah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hUnimplemented featuresh]hUnimplemented features}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubj!)}(hhh](j&)}(h``BUSY`` indicationh]h)}(hj h](h)}(h``BUSY``h]hBUSY}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh indication}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j%hj hhhhhNubj&)}(hAdditional wiring modesh]h)}(hj h]hAdditional wiring modes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j%hj hhhhhNubj&)}(hAdditional clock modesh]h)}(hj% h]hAdditional clock modes}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj# ubah}(h]h ]h"]h$]h&]uh1j%hj hhhhhNubj&)}(h9Differential data 16-bits + common-mode for 24-bits chipsh]h)}(hj< h]h9Differential data 16-bits + common-mode for 24-bits chips}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj: ubah}(h]h ]h"]h$]h&]uh1j%hj hhhhhNubj&)}(hOverrange eventsh]h)}(hjS h]hOverrange events}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjQ ubah}(h]h ]h"]h$]h&]uh1j%hj hhhhhNubj&)}(h Test patternsh]h)}(hjj h]h Test patterns}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjh ubah}(h]h ]h"]h$]h&]uh1j%hj hhhhhNubeh}(h]h ]h"]h$]h&]jTjuh1j hhhKhj hhubeh}(h]unimplemented-featuresah ]h"]unimplemented featuresah$]h&]uh1hhjhhhhhKubeh}(h]supported-featuresah ]h"]supported featuresah$]h&]uh1hhhhhhhhK?ubeh}(h] ad4030-driverah ]h"] ad4030 driverah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}( one lane mode]j,aad4630-fmc hdl project]jadifferential data + common-mode]jEaurefids}nameids}(j j j[jXjLjIj}jzjjjjj j j>j;jjjjj j jjjj jMjJjjjjj)j&jjjjj(jUjjj( j% j j j j j j u nametypes}(j j[jLj}jjj j>jjj jjjMjjj)jjj(jj( j j j uh}(j hjXjjIjCjzjtjjjjj jj;j5jj^jjj jjjj jjJjjjPjjj&jjj,jj`jUjjj+j% jj j+ j j j j u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.