zsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/iio/ad4030modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/iio/ad4030modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/iio/ad4030modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h%SPDX-License-Identifier: GPL-2.0-onlyh]h%SPDX-License-Identifier: GPL-2.0-only}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh8/var/lib/git/docbuild/linux/Documentation/iio/ad4030.rsthKubhsection)}(hhh](htitle)}(h AD4030 driverh]h AD4030 driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h]ADC driver for Analog Devices Inc. AD4030 and similar devices. The module name is ``ad4030``.h](hRADC driver for Analog Devices Inc. AD4030 and similar devices. The module name is }(hhhhhNhNubhliteral)}(h ``ad4030``h]had4030}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hSupported devicesh]hSupported devices}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(h1The following chips are supported by this driver:h]h1The following chips are supported by this driver:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(h/`AD4030-24 `_h]h)}(hjh](h reference)}(hjh]h AD4030-24}(hjhhhNhNubah}(h]h ]h"]h$]h&]name AD4030-24refuri https://www.analog.com/AD4030-24uh1jhjubhtarget)}(h# h]h}(h] ad4030-24ah ]h"] ad4030-24ah$]h&]refurij,uh1j- referencedKhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h/`AD4032-24 `_h]h)}(hjKh](j)}(hjKh]h AD4032-24}(hjPhhhNhNubah}(h]h ]h"]h$]h&]name AD4032-24j+ https://www.analog.com/AD4032-24uh1jhjMubj.)}(h# h]h}(h] ad4032-24ah ]h"] ad4032-24ah$]h&]refurij_uh1j-j<KhjMubeh}(h]h ]h"]h$]h&]uh1hhhhKhjIubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h/`AD4630-16 `_h]h)}(hj{h](j)}(hj{h]h AD4630-16}(hjhhhNhNubah}(h]h ]h"]h$]h&]name AD4630-16j+ https://www.analog.com/AD4630-16uh1jhj}ubj.)}(h# h]h}(h] ad4630-16ah ]h"] ad4630-16ah$]h&]refurijuh1j-j<Khj}ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjyubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h/`AD4630-24 `_h]h)}(hjh](j)}(hjh]h AD4630-24}(hjhhhNhNubah}(h]h ]h"]h$]h&]name AD4630-24j+ https://www.analog.com/AD4630-24uh1jhjubj.)}(h# h]h}(h] ad4630-24ah ]h"] ad4630-24ah$]h&]refurijuh1j-j<Khjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h/`AD4632-16 `_h]h)}(hjh](j)}(hjh]h AD4632-16}(hjhhhNhNubah}(h]h ]h"]h$]h&]name AD4632-16j+ https://www.analog.com/AD4632-16uh1jhjubj.)}(h# h]h}(h] ad4632-16ah ]h"] ad4632-16ah$]h&]refurijuh1j-j<Khjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h0`AD4632-24 `_ h]h)}(h/`AD4632-24 `_h](j)}(hjh]h AD4632-24}(hjhhhNhNubah}(h]h ]h"]h$]h&]name AD4632-24j+ https://www.analog.com/AD4632-24uh1jhj ubj.)}(h# h]h}(h] ad4632-24ah ]h"] ad4632-24ah$]h&]refurij uh1j-j<Khj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1j hhhKhhhhubeh}(h]supported-devicesah ]h"]supported devicesah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h IIO channelsh]h IIO channels}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhhhhhKubh)}(hQEach "hardware" channel as described in the datasheet is split in 2 IIO channels:h]hUEach “hardware” channel as described in the datasheet is split in 2 IIO channels:}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJhhubj )}(hhh](j)}(h%One channel for the differential datah]h)}(hjnh]h%One channel for the differential data}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjlubah}(h]h ]h"]h$]h&]uh1jhjihhhhhNubj)}(h!One channel for the common byte. h]h)}(h One channel for the common byte.h]h One channel for the common byte.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjihhhhhNubeh}(h]h ]h"]h$]h&]j@-uh1j hhhKhjJhhubh)}(hMThe possible IIO channels depending on the numbers of "hardware" channel are:h]hQThe possible IIO channels depending on the numbers of “hardware” channel are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjJhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(h 1 channel ADCh]h 1 channel ADC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h2 channels ADCh]h2 channels ADC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubhtbody)}(hhh]j)}(hhh](j)}(hhh]j )}(hhh](j)}(h voltage0-voltage1 (differential)h]h)}(hj&h]h voltage0-voltage1 (differential)}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hj$ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hvoltage2 (common-mode) h]h)}(hvoltage2 (common-mode)h]hvoltage2 (common-mode)}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hj;ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]j@juh1j hhhK%hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j )}(hhh](j)}(h voltage0-voltage1 (differential)h]h)}(hjgh]h voltage0-voltage1 (differential)}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjeubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(h voltage2-voltage3 (differential)h]h)}(hj~h]h voltage2-voltage3 (differential)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hj|ubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(hvoltage4 (common-mode)h]h)}(hjh]hvoltage4 (common-mode)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(hvoltage5 (common-mode)h]h)}(hjh]hvoltage5 (common-mode)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]j@juh1j hhhK%hj_ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjJhhhNhNubh)}(hhh](h)}(hLabelsh]hLabels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK,ubh)}(hFor ease of use, the IIO channels provide a label. For a differential channel, the label is ``differentialN`` where ``N`` is the "hardware" channel id. For a common-mode channel, the label is ``common-modeN`` where ``N`` is the "hardware" channel id.h](h\For ease of use, the IIO channels provide a label. For a differential channel, the label is }(hjhhhNhNubh)}(h``differentialN``h]h differentialN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh where }(hjhhhNhNubh)}(h``N``h]hN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhK is the “hardware” channel id. For a common-mode channel, the label is }(hjhhhNhNubh)}(h``common-modeN``h]h common-modeN}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh where }hjsbh)}(h``N``h]hN}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh" is the “hardware” channel id.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK.hjhhubh)}(hThe possible labels are:h]hThe possible labels are:}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjhhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj^ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj^ubj)}(hhh]j)}(hhh](j)}(hhh]h)}(h 1 channel ADCh]h 1 channel ADC}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hj{ubah}(h]h ]h"]h$]h&]uh1jhjxubj)}(hhh]h)}(h2 channels ADCh]h2 channels ADC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhj^ubj)}(hhh]j)}(hhh](j)}(hhh]j )}(hhh](j)}(h differential0h]h)}(hjh]h differential0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hcommon-mode0 h]h)}(h common-mode0h]h common-mode0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j@juh1j hhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j )}(hhh](j)}(h differential0h]h)}(hjh]h differential0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h differential1h]h)}(hjh]h differential1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h common-mode0h]h)}(hj2h]h common-mode0}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hj0ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h common-mode1h]h)}(hjIh]h common-mode1}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjGubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j@juh1j hhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]colsKuh1jhj[ubah}(h]h ]h"]h$]h&]uh1jhjhhhNhNubeh}(h]labelsah ]h"]labelsah$]h&]uh1hhjJhhhhhK,ubeh}(h] iio-channelsah ]h"] iio channelsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSupported featuresh]hSupported features}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK?ubh)}(hhh](h)}(hSPI wiring modesh]hSPI wiring modes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKBubh)}(hFThe driver currently supports the following SPI wiring configurations:h]hFThe driver currently supports the following SPI wiring configurations:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjhhubh)}(hhh](h)}(h One lane modeh]h One lane mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKGubh)}(hIn this mode, each channel has its own SDO line to send the conversion results. At the moment this mode can only be used on AD4030 which has one channel so only one SDO line is used.h]hIn this mode, each channel has its own SDO line to send the conversion results. At the moment this mode can only be used on AD4030 which has one channel so only one SDO line is used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjhhubh literal_block)}(hXg+-------------+ +-------------+ | ADC | | HOST | | | | | | CNV |<--------| CNV | | CS |<--------| CS | | SDI |<--------| SDO | | SDO0 |-------->| SDI | | SCLK |<--------| SCLK | +-------------+ +-------------+h]hXg+-------------+ +-------------+ | ADC | | HOST | | | | | | CNV |<--------| CNV | | CS |<--------| CS | | SDI |<--------| SDO | | SDO0 |-------->| SDI | | SCLK |<--------| SCLK | +-------------+ +-------------+}hjsbah}(h]h ]h"]h$]h&]hhforcelanguagenonehighlight_args}uh1jhhhKMhjhhubeh}(h] one-lane-modeah ]h"] one lane modeah$]h&]uh1hhjhhhhhKGj<Kubh)}(hhh](h)}(hInterleaved modeh]hInterleaved mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKZubh)}(hIn this mode, both channels conversion results are bit interleaved one SDO line. As such the wiring is the same as `One lane mode`_.h](hsIn this mode, both channels conversion results are bit interleaved one SDO line. As such the wiring is the same as }(hjhhhNhNubj)}(h`One lane mode`_h]h One lane mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]name One lane moderefidjuh1jhjresolvedKubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK\hjhhubeh}(h]interleaved-modeah ]h"]interleaved modeah$]h&]uh1hhjhhhhhKZubeh}(h]spi-wiring-modesah ]h"]spi wiring modesah$]h&]uh1hhjhhhhhKBubh)}(hhh](h)}(hSPI Clock modeh]hSPI Clock mode}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhK`ubh)}(h(Only the SPI clocking mode is supported.h]h(Only the SPI clocking mode is supported.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjDhhubeh}(h]spi-clock-modeah ]h"]spi clock modeah$]h&]uh1hhjhhhhhK`ubh)}(hhh](h)}(h Output modesh]h Output modes}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhhhhhKeubh)}(hX6There are more exposed IIO channels than channels as describe in the devices datasheet. This is due to the `Differential data + common-mode`_ encoding 2 types of information in one conversion result. As such a "device" channel provides 2 IIO channels, one for the differential data and one for the common byte.h](hkThere are more exposed IIO channels than channels as describe in the devices datasheet. This is due to the }(hj|hhhNhNubj)}(h"`Differential data + common-mode`_h]hDifferential data + common-mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameDifferential data + common-modej(differential-data-common-modeuh1jhj|j)Kubh encoding 2 types of information in one conversion result. As such a “device” channel provides 2 IIO channels, one for the differential data and one for the common byte.}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKghjkhhubh)}(hhh](h)}(hDifferential datah]hDifferential data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKnubh)}(hThis mode is selected when:h]hThis mode is selected when:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjhhubj )}(hhh](j)}(h9Only differential channels are enabled in a buffered readh]h)}(hjh]h9Only differential channels are enabled in a buffered read}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h#Oversampling attribute is set to 1 h]h)}(h"Oversampling attribute is set to 1h]h"Oversampling attribute is set to 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j@juh1j hhhKrhjhhubeh}(h]differential-dataah ]h"]differential dataah$]h&]uh1hhjkhhhhhKnubh)}(hhh](h)}(hDifferential data + common-modeh]hDifferential data + common-mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKvubh)}(hThis mode is selected when:h]hThis mode is selected when:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjhhubj )}(hhh](j)}(hDDifferential and common-mode channels are enabled in a buffered readh]h)}(hj"h]hDDifferential and common-mode channels are enabled in a buffered read}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h#Oversampling attribute is set to 1 h]h)}(h"Oversampling attribute is set to 1h]h"Oversampling attribute is set to 1}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hj7ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j@juh1j hhhKzhjhhubh)}(hlFor the 24-bits chips, this mode is also available with 16-bits differential data but is not selectable yet.h]hlFor the 24-bits chips, this mode is also available with 16-bits differential data but is not selectable yet.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjhhubeh}(h]jah ]h"]differential data + common-modeah$]h&]uh1hhjkhhhhhKvj<Kubh)}(hhh](h)}(hAveraged differential datah]hAveraged differential data}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhhhhhKubh)}(hThis mode is selected when:h]hThis mode is selected when:}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjjhhubj )}(hhh](j)}(hBOnly differential channels are selected enabled in a buffered readh]h)}(hjh]hBOnly differential channels are selected enabled in a buffered read}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h)Oversampling attribute is greater than 1 h]h)}(h(Oversampling attribute is greater than 1h]h(Oversampling attribute is greater than 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j@juh1j hhhKhjjhhubeh}(h]averaged-differential-dataah ]h"]averaged differential dataah$]h&]uh1hhjkhhhhhKubeh}(h] output-modesah ]h"] output modesah$]h&]uh1hhjhhhhhKeubh)}(hhh](h)}(hDigital Gain and Offseth]hDigital Gain and Offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hEach differential data channel has a 16-bits unsigned configurable hardware gain applied to it. By default it's equal to 1. Note that applying gain can cause numerical saturation.h]hEach differential data channel has a 16-bits unsigned configurable hardware gain applied to it. By default it’s equal to 1. Note that applying gain can cause numerical saturation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX Each differential data channel has a signed configurable hardware offset. For the ADCs ending in ``-24``, the gain is encoded on 24-bits. Likewise, the ADCs ending in ``-16`` have a gain encoded on 16-bits. Note that applying an offset can cause numerical saturation.h](haEach differential data channel has a signed configurable hardware offset. For the ADCs ending in }(hjhhhNhNubh)}(h``-24``h]h-24}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh?, the gain is encoded on 24-bits. Likewise, the ADCs ending in }(hjhhhNhNubh)}(h``-16``h]h-16}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh] have a gain encoded on 16-bits. Note that applying an offset can cause numerical saturation.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhThe final differential data returned by the ADC is computed by first applying the gain, then the offset.h]hhThe final differential data returned by the ADC is computed by first applying the gain, then the offset.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hyThe gain is controlled by the ``calibscale`` IIO attribute while the offset is controlled by the ``calibbias`` attribute.h](hThe gain is controlled by the }(hj0hhhNhNubh)}(h``calibscale``h]h calibscale}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubh5 IIO attribute while the offset is controlled by the }(hj0hhhNhNubh)}(h ``calibbias``h]h calibbias}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubh attribute.}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]digital-gain-and-offsetah ]h"]digital gain and offsetah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hReference voltageh]hReference voltage}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhhhhhKubh)}(hXThe chip supports an external reference voltage via the ``REF`` input or an internal buffered reference voltage via the ``REFIN`` input. The driver looks at the device tree to determine which is being used. If ``ref-supply`` is present, then the external reference voltage is used and the internal buffer is disabled. If ``refin-supply`` is present, then the internal buffered reference voltage is used.h](h8The chip supports an external reference voltage via the }(hj{hhhNhNubh)}(h``REF``h]hREF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubh9 input or an internal buffered reference voltage via the }(hj{hhhNhNubh)}(h ``REFIN``h]hREFIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubhQ input. The driver looks at the device tree to determine which is being used. If }(hj{hhhNhNubh)}(h``ref-supply``h]h ref-supply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubha is present, then the external reference voltage is used and the internal buffer is disabled. If }(hj{hhhNhNubh)}(h``refin-supply``h]h refin-supply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubhB is present, then the internal buffered reference voltage is used.}(hj{hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjjhhubeh}(h]reference-voltageah ]h"]reference voltageah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hReseth]hReset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hBoth hardware and software reset are supported. The driver looks first at the device tree to see if the ``reset-gpio`` is populated. If not present, the driver will fallback to a software reset by wiring to the device's registers.h](hhBoth hardware and software reset are supported. The driver looks first at the device tree to see if the }(hjhhhNhNubh)}(h``reset-gpio``h]h reset-gpio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhr is populated. If not present, the driver will fallback to a software reset by wiring to the device’s registers.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]resetah ]h"]resetah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hUnimplemented featuresh]hUnimplemented features}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubj )}(hhh](j)}(h``BUSY`` indicationh]h)}(hj( h](h)}(h``BUSY``h]hBUSY}(hj- hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj* ubh indication}(hj* hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj& ubah}(h]h ]h"]h$]h&]uh1jhj# hhhhhNubj)}(hAdditional wiring modesh]h)}(hjM h]hAdditional wiring modes}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjK ubah}(h]h ]h"]h$]h&]uh1jhj# hhhhhNubj)}(hAdditional clock modesh]h)}(hjd h]hAdditional clock modes}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjb ubah}(h]h ]h"]h$]h&]uh1jhj# hhhhhNubj)}(h9Differential data 16-bits + common-mode for 24-bits chipsh]h)}(hj{ h]h9Differential data 16-bits + common-mode for 24-bits chips}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjy ubah}(h]h ]h"]h$]h&]uh1jhj# hhhhhNubj)}(hOverrange eventsh]h)}(hj h]hOverrange events}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj# hhhhhNubj)}(h Test patternsh]h)}(hj h]h Test patterns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj# hhhhhNubeh}(h]h ]h"]h$]h&]j@juh1j hhhKhj hhubeh}(h]unimplemented-featuresah ]h"]unimplemented featuresah$]h&]uh1hhjhhhhhKubeh}(h]supported-featuresah ]h"]supported featuresah$]h&]uh1hhhhhhhhK?ubeh}(h] ad4030-driverah ]h"] ad4030 driverah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}( one lane mode]jadifferential data + common-mode]jaurefids}nameids}(j j jGjDj8j5jijfjjjjjjj*j'jjjjj j jAj>jjj9j6jhjejjjjjgjjjjgjdjjj j j j u nametypes}(j jGj8jijjjj*jjj jAjj9jhjjjgjjgjj j uh}(j hjDhj5j/jfj`jjjjjjj'j!jjJjjj jj>jjjj6jjejDjjkjjjjjjjjdjjjjj jj j u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.