psphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/i2c/smbus-protocolmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/i2c/smbus-protocolmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/i2c/smbus-protocolmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/i2c/smbus-protocolmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/i2c/smbus-protocolmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/i2c/smbus-protocolmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hThe SMBus Protocolh]hThe SMBus Protocol}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/i2c/smbus-protocol.rsthKubh paragraph)}(hThe following is a summary of the SMBus protocol. It applies to all revisions of the protocol (1.0, 1.1, and 2.0). Certain protocol features which are not supported by this package are briefly described at the end of this document.h]hThe following is a summary of the SMBus protocol. It applies to all revisions of the protocol (1.0, 1.1, and 2.0). Certain protocol features which are not supported by this package are briefly described at the end of this document.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hSome adapters understand only the SMBus (System Management Bus) protocol, which is a subset from the I2C protocol. Fortunately, many devices use only the same subset, which makes it possible to put them on an SMBus.h]hSome adapters understand only the SMBus (System Management Bus) protocol, which is a subset from the I2C protocol. Fortunately, many devices use only the same subset, which makes it possible to put them on an SMBus.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXIf you write a driver for some I2C device, please try to use the SMBus commands if at all possible (if the device uses only that subset of the I2C protocol). This makes it possible to use the device driver on both SMBus adapters and I2C adapters (the SMBus command set is automatically translated to I2C on I2C adapters, but plain I2C commands can not be handled at all on most pure SMBus adapters).h]hXIf you write a driver for some I2C device, please try to use the SMBus commands if at all possible (if the device uses only that subset of the I2C protocol). This makes it possible to use the device driver on both SMBus adapters and I2C adapters (the SMBus command set is automatically translated to I2C on I2C adapters, but plain I2C commands can not be handled at all on most pure SMBus adapters).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXWBelow is a list of SMBus protocol operations, and the functions executing them. Note that the names used in the SMBus protocol specifications usually don't match these function names. For some of the operations which pass a single data byte, the functions using SMBus protocol operation names execute a different protocol operation entirely.h]hXYBelow is a list of SMBus protocol operations, and the functions executing them. Note that the names used in the SMBus protocol specifications usually don’t match these function names. For some of the operations which pass a single data byte, the functions using SMBus protocol operation names execute a different protocol operation entirely.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXCEach transaction type corresponds to a functionality flag. Before calling a transaction function, a device driver should always check (just once) for the corresponding functionality flag to ensure that the underlying I2C adapter supports the transaction in question. See Documentation/i2c/functionality.rst for the details.h]hXCEach transaction type corresponds to a functionality flag. Before calling a transaction function, a device driver should always check (just once) for the corresponding functionality flag to ensure that the underlying I2C adapter supports the transaction in question. See Documentation/i2c/functionality.rst for the details.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hKey to symbolsh]hKey to symbols}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK#ubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK=uh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hSh]hS}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hj<ubah}(h]h ]h"]h$]h&]uh1j:hj7ubj;)}(hhh]h)}(hStart conditionh]hStart condition}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjSubah}(h]h ]h"]h$]h&]uh1j:hj7ubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(hSrh]hSr}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjsubah}(h]h ]h"]h$]h&]uh1j:hjpubj;)}(hhh]h)}(hARepeated start condition, used to switch from write to read mode.h]hARepeated start condition, used to switch from write to read mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1j:hjpubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(hPh]hP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1j:hjubj;)}(hhh]h)}(hStop conditionh]hStop condition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(h Rd/Wr (1 bit)h]h Rd/Wr (1 bit)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1j:hjubj;)}(hhh]h)}(h)Read/Write bit. Rd equals 1, Wr equals 0.h]h)Read/Write bit. Rd equals 1, Wr equals 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(h A, NA (1 bit)h]h A, NA (1 bit)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1j:hjubj;)}(hhh]h)}(h0Acknowledge (ACK) and Not Acknowledge (NACK) bith]h0Acknowledge (ACK) and Not Acknowledge (NACK) bit}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hj/ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(hAddr (7 bits)h]hAddr (7 bits)}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjOubah}(h]h ]h"]h$]h&]uh1j:hjLubj;)}(hhh]h)}(hNI2C 7 bit address. Note that this can be expanded to get a 10 bit I2C address.h]hNI2C 7 bit address. Note that this can be expanded to get a 10 bit I2C address.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjfubah}(h]h ]h"]h$]h&]uh1j:hjLubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(hComm (8 bits)h]hComm (8 bits)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1j:hjubj;)}(hhh]h)}(hGCommand byte, a data byte which often selects a register on the device.h]hGCommand byte, a data byte which often selects a register on the device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(hData (8 bits)h]hData (8 bits)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1j:hjubj;)}(hhh]h)}(hYA plain data byte. DataLow and DataHigh represent the low and high byte of a 16 bit word.h]hYA plain data byte. DataLow and DataHigh represent the low and high byte of a 16 bit word.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(hCount (8 bits)h]hCount (8 bits)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1j:hjubj;)}(hhh]h)}(h7A data byte containing the length of a block operation.h]h7A data byte containing the length of a block operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hj ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]uh1j5hj2ubj6)}(hhh](j;)}(hhh]h)}(h[..]h]h[..]}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hj+ubah}(h]h ]h"]h$]h&]uh1j:hj(ubj;)}(hhh]h)}(hEData sent by I2C device, as opposed to data sent by the host adapter.h]hEData sent by I2C device, as opposed to data sent by the host adapter.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjBubah}(h]h ]h"]h$]h&]uh1j:hj(ubeh}(h]h ]h"]h$]h&]uh1j5hj2ubeh}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhhhhhNubeh}(h]key-to-symbolsah ]h"]key to symbolsah$]h&]uh1hhhhhhhhK#ubh)}(hhh](h)}(hSMBus Quick Commandh]hSMBus Quick Command}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhhhhhK:ubh)}(hFThis sends a single bit to the device, at the place of the Rd/Wr bit::h]hEThis sends a single bit to the device, at the place of the Rd/Wr bit:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjzhhubh)}(h(Functionality flag: I2C_FUNC_SMBUS_QUICKh]h(Functionality flag: I2C_FUNC_SMBUS_QUICK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjzhhubeh}(h]smbus-quick-commandah ]h"]smbus quick commandah$]h&]uh1hhhhhhhhK:ubh)}(hhh](h)}(hSMBus Receive Byteh]hSMBus Receive Byte}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKDubh)}(h$Implemented by i2c_smbus_read_byte()h]h$Implemented by i2c_smbus_read_byte()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhjhhubh)}(hThis reads a single byte from a device, without specifying a device register. Some devices are so simple that this interface is enough; for others, it is a shorthand if you want to read the same register as in the previous SMBus command::h]hThis reads a single byte from a device, without specifying a device register. Some devices are so simple that this interface is enough; for others, it is a shorthand if you want to read the same register as in the previous SMBus command:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjhhubj)}(hS Addr Rd [A] [Data] NA Ph]hS Addr Rd [A] [Data] NA P}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKMhjhhubh)}(h,Functionality flag: I2C_FUNC_SMBUS_READ_BYTEh]h,Functionality flag: I2C_FUNC_SMBUS_READ_BYTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjhhubeh}(h]smbus-receive-byteah ]h"]smbus receive byteah$]h&]uh1hhhhhhhhKDubh)}(hhh](h)}(hSMBus Send Byteh]hSMBus Send Byte}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKSubh)}(h%Implemented by i2c_smbus_write_byte()h]h%Implemented by i2c_smbus_write_byte()}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjhhubh)}(hzThis operation is the reverse of Receive Byte: it sends a single byte to a device. See Receive Byte for more information.h]hzThis operation is the reverse of Receive Byte: it sends a single byte to a device. See Receive Byte for more information.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjhhubj)}(hS Addr Wr [A] Data [A] Ph]hS Addr Wr [A] Data [A] P}hj?sbah}(h]h ]h"]h$]h&]jjuh1jhhhK\hjhhubh)}(h-Functionality flag: I2C_FUNC_SMBUS_WRITE_BYTEh]h-Functionality flag: I2C_FUNC_SMBUS_WRITE_BYTE}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjhhubeh}(h]smbus-send-byteah ]h"]smbus send byteah$]h&]uh1hhhhhhhhKSubh)}(hhh](h)}(hSMBus Read Byteh]hSMBus Read Byte}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchhhhhKbubh)}(h)Implemented by i2c_smbus_read_byte_data()h]h)Implemented by i2c_smbus_read_byte_data()}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjchhubh)}(huThis reads a single byte from a device, from a designated register. The register is specified through the Comm byte::h]htThis reads a single byte from a device, from a designated register. The register is specified through the Comm byte:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjchhubj)}(h1S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA Ph]h1S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKihjchhubh)}(h1Functionality flag: I2C_FUNC_SMBUS_READ_BYTE_DATAh]h1Functionality flag: I2C_FUNC_SMBUS_READ_BYTE_DATA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjchhubeh}(h]smbus-read-byteah ]h"]smbus read byteah$]h&]uh1hhhhhhhhKbubh)}(hhh](h)}(hSMBus Read Wordh]hSMBus Read Word}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKoubh)}(h)Implemented by i2c_smbus_read_word_data()h]h)Implemented by i2c_smbus_read_word_data()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhjhhubh)}(hThis operation is very like Read Byte; again, data is read from a device, from a designated register that is specified through the Comm byte. But this time, the data is a complete word (16 bits)::h]hThis operation is very like Read Byte; again, data is read from a device, from a designated register that is specified through the Comm byte. But this time, the data is a complete word (16 bits):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjhhubj)}(hAS Addr Wr [A] Comm [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA Ph]hAS Addr Wr [A] Comm [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA P}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKwhjhhubh)}(h1Functionality flag: I2C_FUNC_SMBUS_READ_WORD_DATAh]h1Functionality flag: I2C_FUNC_SMBUS_READ_WORD_DATA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjhhubh)}(hNote the convenience function i2c_smbus_read_word_swapped() is available for reads where the two data bytes are the other way around (not SMBus compliant, but very popular.)h]hNote the convenience function i2c_smbus_read_word_swapped() is available for reads where the two data bytes are the other way around (not SMBus compliant, but very popular.)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjhhubeh}(h]smbus-read-wordah ]h"]smbus read wordah$]h&]uh1hhhhhhhhKoubh)}(hhh](h)}(hSMBus Write Byteh]hSMBus Write Byte}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h*Implemented by i2c_smbus_write_byte_data()h]h*Implemented by i2c_smbus_write_byte_data()}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThis writes a single byte to a device, to a designated register. The register is specified through the Comm byte. This is the opposite of the Read Byte operation.h]hThis writes a single byte to a device, to a designated register. The register is specified through the Comm byte. This is the opposite of the Read Byte operation.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h!S Addr Wr [A] Comm [A] Data [A] Ph]h!S Addr Wr [A] Comm [A] Data [A] P}hj@sbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h2Functionality flag: I2C_FUNC_SMBUS_WRITE_BYTE_DATAh]h2Functionality flag: I2C_FUNC_SMBUS_WRITE_BYTE_DATA}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]smbus-write-byteah ]h"]smbus write byteah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSMBus Write Wordh]hSMBus Write Word}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhhhhhKubh)}(h*Implemented by i2c_smbus_write_word_data()h]h*Implemented by i2c_smbus_write_word_data()}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubh)}(hThis is the opposite of the Read Word operation. 16 bits of data are written to a device, to the designated register that is specified through the Comm byte::h]hThis is the opposite of the Read Word operation. 16 bits of data are written to a device, to the designated register that is specified through the Comm byte:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubj)}(h1S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] Ph]h1S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjdhhubh)}(h2Functionality flag: I2C_FUNC_SMBUS_WRITE_WORD_DATAh]h2Functionality flag: I2C_FUNC_SMBUS_WRITE_WORD_DATA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubh)}(hNote the convenience function i2c_smbus_write_word_swapped() is available for writes where the two data bytes are the other way around (not SMBus compliant, but very popular.)h]hNote the convenience function i2c_smbus_write_word_swapped() is available for writes where the two data bytes are the other way around (not SMBus compliant, but very popular.)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubeh}(h]smbus-write-wordah ]h"]smbus write wordah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSMBus Process Callh]hSMBus Process Call}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThis command selects a device register (through the Comm byte), sends 16 bits of data to it, and reads 16 bits of data in return::h]hThis command selects a device register (through the Comm byte), sends 16 bits of data to it, and reads 16 bits of data in return:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hvS Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA Ph]hvS Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA P}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h,Functionality flag: I2C_FUNC_SMBUS_PROC_CALLh]h,Functionality flag: I2C_FUNC_SMBUS_PROC_CALL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]smbus-process-callah ]h"]smbus process callah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSMBus Block Readh]hSMBus Block Read}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h*Implemented by i2c_smbus_read_block_data()h]h*Implemented by i2c_smbus_read_block_data()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThis command reads a block of up to 32 bytes from a device, from a designated register that is specified through the Comm byte. The amount of data is specified by the device in the Count byte.h]hThis command reads a block of up to 32 bytes from a device, from a designated register that is specified through the Comm byte. The amount of data is specified by the device in the Count byte.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h]S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA Ph]h]S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P}hj3sbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h2Functionality flag: I2C_FUNC_SMBUS_READ_BLOCK_DATAh]h2Functionality flag: I2C_FUNC_SMBUS_READ_BLOCK_DATA}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]smbus-block-readah ]h"]smbus block readah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSMBus Block Writeh]hSMBus Block Write}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhhhhhKubh)}(h+Implemented by i2c_smbus_write_block_data()h]h+Implemented by i2c_smbus_write_block_data()}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjWhhubh)}(hThe opposite of the Block Read command, this writes up to 32 bytes to a device, to a designated register that is specified through the Comm byte. The amount of data is specified in the Count byte.h]hThe opposite of the Block Read command, this writes up to 32 bytes to a device, to a designated register that is specified through the Comm byte. The amount of data is specified in the Count byte.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjWhhubj)}(hES Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] Ph]hES Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjWhhubh)}(h3Functionality flag: I2C_FUNC_SMBUS_WRITE_BLOCK_DATAh]h3Functionality flag: I2C_FUNC_SMBUS_WRITE_BLOCK_DATA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjWhhubeh}(h]smbus-block-writeah ]h"]smbus block writeah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h+SMBus Block Write - Block Read Process Callh]h+SMBus Block Write - Block Read Process Call}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h`SMBus Block Write - Block Read Process Call was introduced in Revision 2.0 of the specification.h]h`SMBus Block Write - Block Read Process Call was introduced in Revision 2.0 of the specification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThis command selects a device register (through the Comm byte), sends 1 to 31 bytes of data to it, and reads 1 to 31 bytes of data in return::h]hThis command selects a device register (through the Comm byte), sends 1 to 31 bytes of data to it, and reads 1 to 31 bytes of data in return:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hqS Addr Wr [A] Comm [A] Count [A] Data [A] ... Sr Addr Rd [A] [Count] A [Data] ... A Ph]hqS Addr Wr [A] Comm [A] Count [A] Data [A] ... Sr Addr Rd [A] [Count] A [Data] ... A P}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h2Functionality flag: I2C_FUNC_SMBUS_BLOCK_PROC_CALLh]h2Functionality flag: I2C_FUNC_SMBUS_BLOCK_PROC_CALL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h])smbus-block-write-block-read-process-callah ]h"]+smbus block write - block read process callah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSMBus Host Notifyh]hSMBus Host Notify}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThis command is sent from a SMBus device acting as a master to the SMBus host acting as a slave. It is the same form as Write Word, with the command code replaced by the alerting device's address.h]hThis command is sent from a SMBus device acting as a master to the SMBus host acting as a slave. It is the same form as Write Word, with the command code replaced by the alerting device’s address.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h>[S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]h]h>[S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h=This is implemented in the following way in the Linux kernel:h]h=This is implemented in the following way in the Linux kernel:}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh bullet_list)}(hhh](h list_item)}(hYI2C bus drivers which support SMBus Host Notify should report I2C_FUNC_SMBUS_HOST_NOTIFY.h]h)}(hYI2C bus drivers which support SMBus Host Notify should report I2C_FUNC_SMBUS_HOST_NOTIFY.h]hYI2C bus drivers which support SMBus Host Notify should report I2C_FUNC_SMBUS_HOST_NOTIFY.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj;ubah}(h]h ]h"]h$]h&]uh1j9hj6hhhhhNubj:)}(hVI2C bus drivers trigger SMBus Host Notify by a call to i2c_handle_smbus_host_notify().h]h)}(hVI2C bus drivers trigger SMBus Host Notify by a call to i2c_handle_smbus_host_notify().h]hVI2C bus drivers trigger SMBus Host Notify by a call to i2c_handle_smbus_host_notify().}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjSubah}(h]h ]h"]h$]h&]uh1j9hj6hhhhhNubj:)}(hI2C drivers for devices which can trigger SMBus Host Notify will have client->irq assigned to a Host Notify IRQ if no one else specified another. h]h)}(hI2C drivers for devices which can trigger SMBus Host Notify will have client->irq assigned to a Host Notify IRQ if no one else specified another.h]hI2C drivers for devices which can trigger SMBus Host Notify will have client->irq assigned to a Host Notify IRQ if no one else specified another.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubah}(h]h ]h"]h$]h&]uh1j9hj6hhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1j4hhhKhjhhubh)}(hIThere is currently no way to retrieve the data parameter from the client.h]hIThere is currently no way to retrieve the data parameter from the client.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]smbus-host-notifyah ]h"]smbus host notifyah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hPacket Error Checking (PEC)h]hPacket Error Checking (PEC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hJPacket Error Checking was introduced in Revision 1.1 of the specification.h]hJPacket Error Checking was introduced in Revision 1.1 of the specification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hdPEC adds a CRC-8 error-checking byte to transfers using it, immediately before the terminating STOP.h]hdPEC adds a CRC-8 error-checking byte to transfers using it, immediately before the terminating STOP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]packet-error-checking-pecah ]h"]packet error checking (pec)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h!Address Resolution Protocol (ARP)h]h!Address Resolution Protocol (ARP)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hThe Address Resolution Protocol was introduced in Revision 2.0 of the specification. It is a higher-layer protocol which uses the messages above.h]hThe Address Resolution Protocol was introduced in Revision 2.0 of the specification. It is a higher-layer protocol which uses the messages above.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hARP adds device enumeration and dynamic address assignment to the protocol. All ARP communications use slave address 0x61 and require PEC checksums.h]hARP adds device enumeration and dynamic address assignment to the protocol. All ARP communications use slave address 0x61 and require PEC checksums.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]address-resolution-protocol-arpah ]h"]!address resolution protocol (arp)ah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h SMBus Alerth]h SMBus Alert}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM ubh)}(h@SMBus Alert was introduced in Revision 1.0 of the specification.h]h@SMBus Alert was introduced in Revision 1.0 of the specification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hThe SMBus alert protocol allows several SMBus slave devices to share a single interrupt pin on the SMBus master, while still allowing the master to know which slave triggered the interrupt.h]hThe SMBus alert protocol allows several SMBus slave devices to share a single interrupt pin on the SMBus master, while still allowing the master to know which slave triggered the interrupt.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(h:This is implemented the following way in the Linux kernel:h]h:This is implemented the following way in the Linux kernel:}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj5)}(hhh](j:)}(hrI2C bus drivers which support SMBus alert should call i2c_new_smbus_alert_device() to install SMBus alert support.h]h)}(hrI2C bus drivers which support SMBus alert should call i2c_new_smbus_alert_device() to install SMBus alert support.h]hrI2C bus drivers which support SMBus alert should call i2c_new_smbus_alert_device() to install SMBus alert support.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjIubah}(h]h ]h"]h$]h&]uh1j9hjFhhhhhNubj:)}(hhI2C drivers for devices which can trigger SMBus alerts should implement the optional alert() callback. h]h)}(hfI2C drivers for devices which can trigger SMBus alerts should implement the optional alert() callback.h]hfI2C drivers for devices which can trigger SMBus alerts should implement the optional alert() callback.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjaubah}(h]h ]h"]h$]h&]uh1j9hjFhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1j4hhhMhj hhubeh}(h] smbus-alertah ]h"] smbus alertah$]h&]uh1hhhhhhhhM ubh)}(hhh](h)}(hI2C Block Transactionsh]hI2C Block Transactions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hX The following I2C block transactions are similar to the SMBus Block Read and Write operations, except these do not have a Count byte. They are supported by the SMBus layer and are described here for completeness, but they are *NOT* defined by the SMBus specification.h](hThe following I2C block transactions are similar to the SMBus Block Read and Write operations, except these do not have a Count byte. They are supported by the SMBus layer and are described here for completeness, but they are }(hjhhhNhNubhemphasis)}(h*NOT*h]hNOT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh$ defined by the SMBus specification.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hsI2C block transactions do not limit the number of bytes transferred but the SMBus layer places a limit of 32 bytes.h]hsI2C block transactions do not limit the number of bytes transferred but the SMBus layer places a limit of 32 bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubeh}(h]i2c-block-transactionsah ]h"]i2c block transactionsah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hI2C Block Readh]hI2C Block Read}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM)ubh)}(h.Implemented by i2c_smbus_read_i2c_block_data()h]h.Implemented by i2c_smbus_read_i2c_block_data()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hjhhubh)}(hwThis command reads a block of bytes from a device, from a designated register that is specified through the Comm byte::h]hvThis command reads a block of bytes from a device, from a designated register that is specified through the Comm byte:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjhhubj)}(hSS Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] A [Data] A ... A [Data] NA Ph]hSS Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] A [Data] A ... A [Data] NA P}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhM0hjhhubh)}(h1Functionality flag: I2C_FUNC_SMBUS_READ_I2C_BLOCKh]h1Functionality flag: I2C_FUNC_SMBUS_READ_I2C_BLOCK}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hjhhubeh}(h]i2c-block-readah ]h"]i2c block readah$]h&]uh1hhhhhhhhM)ubh)}(hhh](h)}(hI2C Block Writeh]hI2C Block Write}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj! hhhhhM7ubh)}(h/Implemented by i2c_smbus_write_i2c_block_data()h]h/Implemented by i2c_smbus_write_i2c_block_data()}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj! hhubh)}(hThe opposite of the Block Read command, this writes bytes to a device, to a designated register that is specified through the Comm byte. Note that command lengths of 0, 2, or more bytes are supported as they are indistinguishable from data.h]hThe opposite of the Block Read command, this writes bytes to a device, to a designated register that is specified through the Comm byte. Note that command lengths of 0, 2, or more bytes are supported as they are indistinguishable from data.}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hj! hhubj)}(h;S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] Ph]h;S Addr Wr [A] Comm [A] Data [A] Data [A] ... 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