esphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget$/translations/zh_CN/i2c/i2c-topologymodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/zh_TW/i2c/i2c-topologymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/it_IT/i2c/i2c-topologymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/ja_JP/i2c/i2c-topologymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/ko_KR/i2c/i2c-topologymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/sp_SP/i2c/i2c-topologymodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h I2C muxes and complex topologiesh]h I2C muxes and complex topologies}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh>/var/lib/git/docbuild/linux/Documentation/i2c/i2c-topology.rsthKubh paragraph)}(hThere are a couple of reasons for building more complex I2C topologies than a straight-forward I2C bus with one adapter and one or more devices.h]hThere are a couple of reasons for building more complex I2C topologies than a straight-forward I2C bus with one adapter and one or more devices.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hSome example use cases are:h]hSome example use cases are:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhenumerated_list)}(hhh](h list_item)}(h>A mux may be needed on the bus to prevent address collisions. h]h)}(h=A mux may be needed on the bus to prevent address collisions.h]h=A mux may be needed on the bus to prevent address collisions.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hThe bus may be accessible from some external bus master, and arbitration may be needed to determine if it is ok to access the bus. h]h)}(hThe bus may be accessible from some external bus master, and arbitration may be needed to determine if it is ok to access the bus.h]hThe bus may be accessible from some external bus master, and arbitration may be needed to determine if it is ok to access the bus.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hA device (particularly RF tuners) may want to avoid the digital noise from the I2C bus, at least most of the time, and sits behind a gate that has to be operated before the device can be accessed. h]h)}(hA device (particularly RF tuners) may want to avoid the digital noise from the I2C bus, at least most of the time, and sits behind a gate that has to be operated before the device can be accessed.h]hA device (particularly RF tuners) may want to avoid the digital noise from the I2C bus, at least most of the time, and sits behind a gate that has to be operated before the device can be accessed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1hhhhhhhhK ubh)}(hqSeveral types of hardware components such as I2C muxes, I2C gates and I2C arbitrators allow to handle such needs.h]hqSeveral types of hardware components such as I2C muxes, I2C gates and I2C arbitrators allow to handle such needs.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hX[These components are represented as I2C adapter trees by Linux, where each adapter has a parent adapter (except the root adapter) and zero or more child adapters. The root adapter is the actual adapter that issues I2C transfers, and all adapters with a parent are part of an "i2c-mux" object (quoted, since it can also be an arbitrator or a gate).h]hX_These components are represented as I2C adapter trees by Linux, where each adapter has a parent adapter (except the root adapter) and zero or more child adapters. The root adapter is the actual adapter that issues I2C transfers, and all adapters with a parent are part of an “i2c-mux” object (quoted, since it can also be an arbitrator or a gate).}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXDepending of the particular mux driver, something happens when there is an I2C transfer on one of its child adapters. The mux driver can obviously operate a mux, but it can also do arbitration with an external bus master or open a gate. The mux driver has two operations for this, select and deselect. select is called before the transfer and (the optional) deselect is called after the transfer.h]hXDepending of the particular mux driver, something happens when there is an I2C transfer on one of its child adapters. The mux driver can obviously operate a mux, but it can also do arbitration with an external bus master or open a gate. The mux driver has two operations for this, select and deselect. select is called before the transfer and (the optional) deselect is called after the transfer.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hLockingh]hLocking}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhhhhhK%ubh)}(hhThere are two variants of locking available to I2C muxes, they can be mux-locked or parent-locked muxes.h]hhThere are two variants of locking available to I2C muxes, they can be mux-locked or parent-locked muxes.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjYhhubh)}(hhh](h)}(hMux-locked muxesh]hMux-locked muxes}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhhhhhK,ubh)}(hX$Mux-locked muxes does not lock the entire parent adapter during the full select-transfer-deselect transaction, only the muxes on the parent adapter are locked. Mux-locked muxes are mostly interesting if the select and/or deselect operations must use I2C transfers to complete their tasks. Since the parent adapter is not fully locked during the full transaction, unrelated I2C transfers may interleave the different stages of the transaction. This has the benefit that the mux driver may be easier and cleaner to implement, but it has some caveats.h]hX$Mux-locked muxes does not lock the entire parent adapter during the full select-transfer-deselect transaction, only the muxes on the parent adapter are locked. Mux-locked muxes are mostly interesting if the select and/or deselect operations must use I2C transfers to complete their tasks. Since the parent adapter is not fully locked during the full transaction, unrelated I2C transfers may interleave the different stages of the transaction. This has the benefit that the mux driver may be easier and cleaner to implement, but it has some caveats.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjxhhubh)}(hhh](h)}(hMux-locked Exampleh]hMux-locked Example}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK8ubh literal_block)}(hX5 .----------. .--------. .--------. | mux- |-----| dev D1 | | root |--+--| locked | '--------' '--------' | | mux M1 |--. .--------. | '----------' '--| dev D2 | | .--------. '--------' '--| dev D3 | '--------'h]hX5 .----------. .--------. .--------. | mux- |-----| dev D1 | | root |--+--| locked | '--------' '--------' | | mux M1 |--. .--------. | '----------' '--| dev D2 | | .--------. '--------' '--| dev D3 | '--------'}hjsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jhhhKselect to ready the mux. 4. M1 (presumably) does some I2C transfers as part of its select. These transfers are normal I2C transfers that locks the parent adapter. 5. M1 feeds the I2C transfer from step 1 to its parent adapter as a normal I2C transfer that locks the parent adapter. 6. M1 calls ->deselect, if it has one. 7. Same rules as in step 4, but for ->deselect. 8. M1 unlocks muxes on its parent. h]h)}(hhh](h)}(h%Someone issues an I2C transfer to D1.h]h)}(hjh]h%Someone issues an I2C transfer to D1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h=M1 locks muxes on its parent (the root adapter in this case).h]h)}(hjh]h=M1 locks muxes on its parent (the root adapter in this case).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h#M1 calls ->select to ready the mux.h]h)}(hjh]h#M1 calls ->select to ready the mux.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hM1 (presumably) does some I2C transfers as part of its select. These transfers are normal I2C transfers that locks the parent adapter.h]h)}(hM1 (presumably) does some I2C transfers as part of its select. These transfers are normal I2C transfers that locks the parent adapter.h]hM1 (presumably) does some I2C transfers as part of its select. These transfers are normal I2C transfers that locks the parent adapter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hsM1 feeds the I2C transfer from step 1 to its parent adapter as a normal I2C transfer that locks the parent adapter.h]h)}(hsM1 feeds the I2C transfer from step 1 to its parent adapter as a normal I2C transfer that locks the parent adapter.h]hsM1 feeds the I2C transfer from step 1 to its parent adapter as a normal I2C transfer that locks the parent adapter.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhj.ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h#M1 calls ->deselect, if it has one.h]h)}(hjHh]h#M1 calls ->deselect, if it has one.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjFubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h,Same rules as in step 4, but for ->deselect.h]h)}(hj_h]h,Same rules as in step 4, but for ->deselect.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhj]ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h M1 unlocks muxes on its parent. h]h)}(hM1 unlocks muxes on its parent.h]hM1 unlocks muxes on its parent.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjtubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j*j+j,hj-j.uh1hhjubah}(h]h ]h"]h$]h&]uh1jhhhKGhjhhubh)}(hThis means that accesses to D2 are lockout out for the full duration of the entire operation. But accesses to D3 are possibly interleaved at any point.h]hThis means that accesses to D2 are lockout out for the full duration of the entire operation. But accesses to D3 are possibly interleaved at any point.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjhhubeh}(h]mux-locked-exampleah ]h"]mux-locked exampleah$]h&]uh1hhjxhhhhhK8ubh)}(hhh](h)}(hMux-locked caveatsh]hMux-locked caveats}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKXubh)}(hDWhen using a mux-locked mux, be aware of the following restrictions:h]hDWhen using a mux-locked mux, be aware of the following restrictions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjhhubhdefinition_list)}(hhh](hdefinition_list_item)}(h[ML1] If you build a topology with a mux-locked mux being the parent of a parent-locked mux, this might break the expectation from the parent-locked mux that the root adapter is locked during the transaction. h](hterm)}(h[ML1]h]h[ML1]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK`hjubh definition)}(hhh]h)}(hIf you build a topology with a mux-locked mux being the parent of a parent-locked mux, this might break the expectation from the parent-locked mux that the root adapter is locked during the transaction.h]hIf you build a topology with a mux-locked mux being the parent of a parent-locked mux, this might break the expectation from the parent-locked mux that the root adapter is locked during the transaction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK`hjubj)}(hXU[ML2] It is not safe to build arbitrary topologies with two (or more) mux-locked muxes that are not siblings, when there are address collisions between the devices on the child adapters of these non-sibling muxes. I.e. the select-transfer-deselect transaction targeting e.g. device address 0x42 behind mux-one may be interleaved with a similar operation targeting device address 0x42 behind mux-two. The intent with such a topology would in this hypothetical example be that mux-one and mux-two should not be selected simultaneously, but mux-locked muxes do not guarantee that in all topologies. h](j)}(h[ML2]h]h[ML2]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKmhjubj)}(hhh](h)}(hIt is not safe to build arbitrary topologies with two (or more) mux-locked muxes that are not siblings, when there are address collisions between the devices on the child adapters of these non-sibling muxes.h]hIt is not safe to build arbitrary topologies with two (or more) mux-locked muxes that are not siblings, when there are address collisions between the devices on the child adapters of these non-sibling muxes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchjubh)}(hX}I.e. the select-transfer-deselect transaction targeting e.g. device address 0x42 behind mux-one may be interleaved with a similar operation targeting device address 0x42 behind mux-two. The intent with such a topology would in this hypothetical example be that mux-one and mux-two should not be selected simultaneously, but mux-locked muxes do not guarantee that in all topologies.h]hX}I.e. the select-transfer-deselect transaction targeting e.g. device address 0x42 behind mux-one may be interleaved with a similar operation targeting device address 0x42 behind mux-two. The intent with such a topology would in this hypothetical example be that mux-one and mux-two should not be selected simultaneously, but mux-locked muxes do not guarantee that in all topologies.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKmhjhhubj)}(h[ML3] A mux-locked mux cannot be used by a driver for auto-closing gates/muxes, i.e. something that closes automatically after a given number (one, in most cases) of I2C transfers. Unrelated I2C transfers may creep in and close prematurely. h](j)}(h[ML3]h]h[ML3]}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKshjDubj)}(hhh]h)}(hA mux-locked mux cannot be used by a driver for auto-closing gates/muxes, i.e. something that closes automatically after a given number (one, in most cases) of I2C transfers. Unrelated I2C transfers may creep in and close prematurely.h]hA mux-locked mux cannot be used by a driver for auto-closing gates/muxes, i.e. something that closes automatically after a given number (one, in most cases) of I2C transfers. Unrelated I2C transfers may creep in and close prematurely.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjVubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhhhKshjhhubj)}(hX0[ML4] If any non-I2C operation in the mux driver changes the I2C mux state, the driver has to lock the root adapter during that operation. Otherwise garbage may appear on the bus as seen from devices behind the mux, when an unrelated I2C transfer is in flight during the non-I2C mux-changing operation. h](j)}(h[ML4]h]h[ML4]}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK{hjsubj)}(hhh]h)}(hX(If any non-I2C operation in the mux driver changes the I2C mux state, the driver has to lock the root adapter during that operation. Otherwise garbage may appear on the bus as seen from devices behind the mux, when an unrelated I2C transfer is in flight during the non-I2C mux-changing operation.h]hX(If any non-I2C operation in the mux driver changes the I2C mux state, the driver has to lock the root adapter during that operation. Otherwise garbage may appear on the bus as seen from devices behind the mux, when an unrelated I2C transfer is in flight during the non-I2C mux-changing operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhhhK{hjhhubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]mux-locked-caveatsah ]h"]mux-locked caveatsah$]h&]uh1hhjxhhhhhKXubeh}(h]mux-locked-muxesah ]h"]mux-locked muxesah$]h&]uh1hhjYhhhhhK,ubh)}(hhh](h)}(hParent-locked muxesh]hParent-locked muxes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK~ubh)}(hX<Parent-locked muxes lock the parent adapter during the full select- transfer-deselect transaction. The implication is that the mux driver has to ensure that any and all I2C transfers through that parent adapter during the transaction are unlocked I2C transfers (using e.g. __i2c_transfer), or a deadlock will follow.h]hX<Parent-locked muxes lock the parent adapter during the full select- transfer-deselect transaction. The implication is that the mux driver has to ensure that any and all I2C transfers through that parent adapter during the transaction are unlocked I2C transfers (using e.g. __i2c_transfer), or a deadlock will follow.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hParent-locked Exampleh]hParent-locked Example}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj)}(hX5 .----------. .--------. .--------. | parent- |-----| dev D1 | | root |--+--| locked | '--------' '--------' | | mux M1 |--. .--------. | '----------' '--| dev D2 | | .--------. '--------' '--| dev D3 | '--------'h]hX5 .----------. .--------. .--------. | parent- |-----| dev D1 | | root |--+--| locked | '--------' '--------' | | mux M1 |--. .--------. | '----------' '--| dev D2 | | .--------. '--------' '--| dev D3 | '--------'}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h,When there is an access to D1, this happens:h]h,When there is an access to D1, this happens:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hX1. Someone issues an I2C transfer to D1. 2. M1 locks muxes on its parent (the root adapter in this case). 3. M1 locks its parent adapter. 4. M1 calls ->select to ready the mux. 5. If M1 does any I2C transfers (on this root adapter) as part of its select, those transfers must be unlocked I2C transfers so that they do not deadlock the root adapter. 6. M1 feeds the I2C transfer from step 1 to the root adapter as an unlocked I2C transfer, so that it does not deadlock the parent adapter. 7. M1 calls ->deselect, if it has one. 8. Same rules as in step 5, but for ->deselect. 9. M1 unlocks its parent adapter. 10. M1 unlocks muxes on its parent. h]h)}(hhh](h)}(h%Someone issues an I2C transfer to D1.h]h)}(hj h]h%Someone issues an I2C transfer to D1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h=M1 locks muxes on its parent (the root adapter in this case).h]h)}(hj$h]h=M1 locks muxes on its parent (the root adapter in this case).}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj"ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hM1 locks its parent adapter.h]h)}(hj;h]hM1 locks its parent adapter.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj9ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h#M1 calls ->select to ready the mux.h]h)}(hjRh]h#M1 calls ->select to ready the mux.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjPubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hIf M1 does any I2C transfers (on this root adapter) as part of its select, those transfers must be unlocked I2C transfers so that they do not deadlock the root adapter.h]h)}(hIf M1 does any I2C transfers (on this root adapter) as part of its select, those transfers must be unlocked I2C transfers so that they do not deadlock the root adapter.h]hIf M1 does any I2C transfers (on this root adapter) as part of its select, those transfers must be unlocked I2C transfers so that they do not deadlock the root adapter.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjgubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hM1 feeds the I2C transfer from step 1 to the root adapter as an unlocked I2C transfer, so that it does not deadlock the parent adapter.h]h)}(hM1 feeds the I2C transfer from step 1 to the root adapter as an unlocked I2C transfer, so that it does not deadlock the parent adapter.h]hM1 feeds the I2C transfer from step 1 to the root adapter as an unlocked I2C transfer, so that it does not deadlock the parent adapter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h#M1 calls ->deselect, if it has one.h]h)}(hjh]h#M1 calls ->deselect, if it has one.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h,Same rules as in step 5, but for ->deselect.h]h)}(hjh]h,Same rules as in step 5, but for ->deselect.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hM1 unlocks its parent adapter.h]h)}(hjh]hM1 unlocks its parent adapter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h M1 unlocks muxes on its parent. h]h)}(hM1 unlocks muxes on its parent.h]hM1 unlocks muxes on its parent.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j*j+j,hj-j.uh1hhjubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubh)}(hhThis means that accesses to both D2 and D3 are locked out for the full duration of the entire operation.h]hhThis means that accesses to both D2 and D3 are locked out for the full duration of the entire operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]parent-locked-exampleah ]h"]parent-locked exampleah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hParent-locked Caveatsh]hParent-locked Caveats}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hGWhen using a parent-locked mux, be aware of the following restrictions:h]hGWhen using a parent-locked mux, be aware of the following restrictions:}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hX[PL1] If you build a topology with a parent-locked mux being the child of another mux, this might break a possible assumption from the child mux that the root adapter is unused between its select op and the actual transfer (e.g. if the child mux is auto-closing and the parent mux issues I2C transfers as part of its select). This is especially the case if the parent mux is mux-locked, but it may also happen if the parent mux is parent-locked. h](j)}(h[PL1]h]h[PL1]}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj8ubj)}(hhh]h)}(hXIf you build a topology with a parent-locked mux being the child of another mux, this might break a possible assumption from the child mux that the root adapter is unused between its select op and the actual transfer (e.g. if the child mux is auto-closing and the parent mux issues I2C transfers as part of its select). This is especially the case if the parent mux is mux-locked, but it may also happen if the parent mux is parent-locked.h]hXIf you build a topology with a parent-locked mux being the child of another mux, this might break a possible assumption from the child mux that the root adapter is unused between its select op and the actual transfer (e.g. if the child mux is auto-closing and the parent mux issues I2C transfers as part of its select). This is especially the case if the parent mux is mux-locked, but it may also happen if the parent mux is parent-locked.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj5ubj)}(hX[PL2] If select/deselect calls out to other subsystems such as gpio, pinctrl, regmap or iio, it is essential that any I2C transfers caused by these subsystems are unlocked. This can be convoluted to accomplish, maybe even impossible if an acceptably clean solution is sought. h](j)}(h[PL2]h]h[PL2]}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjgubj)}(hhh]h)}(hX If select/deselect calls out to other subsystems such as gpio, pinctrl, regmap or iio, it is essential that any I2C transfers caused by these subsystems are unlocked. This can be convoluted to accomplish, maybe even impossible if an acceptably clean solution is sought.h]hX If select/deselect calls out to other subsystems such as gpio, pinctrl, regmap or iio, it is essential that any I2C transfers caused by these subsystems are unlocked. This can be convoluted to accomplish, maybe even impossible if an acceptably clean solution is sought.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjyubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jhhhKhj5hhubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]parent-locked-caveatsah ]h"]parent-locked caveatsah$]h&]uh1hhjhhhhhKubeh}(h]parent-locked-muxesah ]h"]parent-locked muxesah$]h&]uh1hhjYhhhhhK~ubeh}(h]lockingah ]h"]lockingah$]h&]uh1hhhhhhhhK%ubh)}(hhh](h)}(hComplex Examplesh]hComplex Examples}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h0Parent-locked mux as parent of parent-locked muxh]h0Parent-locked mux as parent of parent-locked mux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h.This is a useful topology, but it can be bad::h]h-This is a useful topology, but it can be bad:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hX .----------. .----------. .--------. .--------. | parent- |-----| parent- |-----| dev D1 | | root |--+--| locked | | locked | '--------' '--------' | | mux M1 |--. | mux M2 |--. .--------. | '----------' | '----------' '--| dev D2 | | .--------. | .--------. '--------' '--| dev D4 | '--| dev D3 | '--------' '--------'h]hX .----------. .----------. .--------. .--------. | parent- |-----| parent- |-----| dev D1 | | root |--+--| locked | | locked | '--------' '--------' | | mux M1 |--. | mux M2 |--. .--------. | '----------' | '----------' '--| dev D2 | | .--------. | .--------. '--------' '--| dev D4 | '--| dev D3 | '--------' '--------'}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hWhen any device is accessed, all other devices are locked out for the full duration of the operation (both muxes lock their parent, and specifically when M2 requests its parent to lock, M1 passes the buck to the root adapter).h]hWhen any device is accessed, all other devices are locked out for the full duration of the operation (both muxes lock their parent, and specifically when M2 requests its parent to lock, M1 passes the buck to the root adapter).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThis topology is bad if M2 is an auto-closing mux and M1->select issues any unlocked I2C transfers on the root adapter that may leak through and be seen by the M2 adapter, thus closing M2 prematurely.h]hThis topology is bad if M2 is an auto-closing mux and M1->select issues any unlocked I2C transfers on the root adapter that may leak through and be seen by the M2 adapter, thus closing M2 prematurely.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]0parent-locked-mux-as-parent-of-parent-locked-muxah ]h"]0parent-locked mux as parent of parent-locked muxah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h*Mux-locked mux as parent of mux-locked muxh]h*Mux-locked mux as parent of mux-locked mux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThis is a good topology::h]hThis is a good topology:}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hX .----------. .----------. .--------. .--------. | mux- |-----| mux- |-----| dev D1 | | root |--+--| locked | | locked | '--------' '--------' | | mux M1 |--. | mux M2 |--. .--------. | '----------' | '----------' '--| dev D2 | | .--------. | .--------. '--------' '--| dev D4 | '--| dev D3 | '--------' '--------'h]hX .----------. .----------. .--------. .--------. | mux- |-----| mux- |-----| dev D1 | | root |--+--| locked | | locked | '--------' '--------' | | mux M1 |--. | mux M2 |--. .--------. | '----------' | '----------' '--| dev D2 | | .--------. | .--------. '--------' '--| dev D4 | '--| dev D3 | '--------' '--------'}hj5sbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hWhen device D1 is accessed, accesses to D2 are locked out for the full duration of the operation (muxes on the top child adapter of M1 are locked). But accesses to D3 and D4 are possibly interleaved at any point.h]hWhen device D1 is accessed, accesses to D2 are locked out for the full duration of the operation (muxes on the top child adapter of M1 are locked). But accesses to D3 and D4 are possibly interleaved at any point.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hVAccesses to D3 locks out D1 and D2, but accesses to D4 are still possibly interleaved.h]hVAccesses to D3 locks out D1 and D2, but accesses to D4 are still possibly interleaved.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]*mux-locked-mux-as-parent-of-mux-locked-muxah ]h"]*mux-locked mux as parent of mux-locked muxah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h-Mux-locked mux as parent of parent-locked muxh]h-Mux-locked mux as parent of parent-locked mux}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghhhhhKubh)}(h!This is probably a bad topology::h]h This is probably a bad topology:}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjghhubj)}(hX .----------. .----------. .--------. .--------. | mux- |-----| parent- |-----| dev D1 | | root |--+--| locked | | locked | '--------' '--------' | | mux M1 |--. | mux M2 |--. .--------. | '----------' | '----------' '--| dev D2 | | .--------. | .--------. '--------' '--| dev D4 | '--| dev D3 | '--------' '--------'h]hX .----------. .----------. .--------. .--------. | mux- |-----| parent- |-----| dev D1 | | root |--+--| locked | | locked | '--------' '--------' | | mux M1 |--. | mux M2 |--. .--------. | '----------' | '----------' '--| dev D2 | | .--------. | .--------. '--------' '--| dev D4 | '--| dev D3 | '--------' '--------'}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjghhubh)}(hWhen device D1 is accessed, accesses to D2 and D3 are locked out for the full duration of the operation (M1 locks child muxes on the root adapter). But accesses to D4 are possibly interleaved at any point.h]hWhen device D1 is accessed, accesses to D2 and D3 are locked out for the full duration of the operation (M1 locks child muxes on the root adapter). But accesses to D4 are possibly interleaved at any point.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjghhubh)}(hXyThis kind of topology is generally not suitable and should probably be avoided. The reason is that M2 probably assumes that there will be no I2C transfers during its calls to ->select and ->deselect, and if there are, any such transfers might appear on the slave side of M2 as partial I2C transfers, i.e. garbage or worse. This might cause device lockups and/or other problems.h]hXyThis kind of topology is generally not suitable and should probably be avoided. The reason is that M2 probably assumes that there will be no I2C transfers during its calls to ->select and ->deselect, and if there are, any such transfers might appear on the slave side of M2 as partial I2C transfers, i.e. garbage or worse. This might cause device lockups and/or other problems.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjghhubh)}(hThe topology is especially troublesome if M2 is an auto-closing mux. In that case, any interleaved accesses to D4 might close M2 prematurely, as might any I2C transfers part of M1->select.h]hThe topology is especially troublesome if M2 is an auto-closing mux. In that case, any interleaved accesses to D4 might close M2 prematurely, as might any I2C transfers part of M1->select.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjghhubh)}(hiBut if M2 is not making the above stated assumption, and if M2 is not auto-closing, the topology is fine.h]hiBut if M2 is not making the above stated assumption, and if M2 is not auto-closing, the topology is fine.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjghhubeh}(h]-mux-locked-mux-as-parent-of-parent-locked-muxah ]h"]-mux-locked mux as parent of parent-locked muxah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h-Parent-locked mux as parent of mux-locked muxh]h-Parent-locked mux as parent of mux-locked mux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hThis is a good topology::h]hThis is a good topology:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hX .----------. .----------. .--------. .--------. | parent- |-----| mux- |-----| dev D1 | | root |--+--| locked | | locked | '--------' '--------' | | mux M1 |--. | mux M2 |--. .--------. | '----------' | '----------' '--| dev D2 | | .--------. | .--------. '--------' '--| dev D4 | '--| dev D3 | '--------' '--------'h]hX .----------. .----------. .--------. .--------. | parent- |-----| mux- |-----| dev D1 | | root |--+--| locked | | locked | '--------' '--------' | | mux M1 |--. | mux M2 |--. .--------. | '----------' | '----------' '--| dev D2 | | .--------. | .--------. '--------' '--| dev D4 | '--| dev D3 | '--------' '--------'}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhMhjhhubh)}(hWhen D1 is accessed, accesses to D2 are locked out for the full duration of the operation (muxes on the top child adapter of M1 are locked). Accesses to D3 and D4 are possibly interleaved at any point, just as is expected for mux-locked muxes.h]hWhen D1 is accessed, accesses to D2 are locked out for the full duration of the operation (muxes on the top child adapter of M1 are locked). Accesses to D3 and D4 are possibly interleaved at any point, just as is expected for mux-locked muxes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hWhen D3 or D4 are accessed, everything else is locked out. For D3 accesses, M1 locks the root adapter. For D4 accesses, the root adapter is locked directly.h]hWhen D3 or D4 are accessed, everything else is locked out. For D3 accesses, M1 locks the root adapter. For D4 accesses, the root adapter is locked directly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubeh}(h]-parent-locked-mux-as-parent-of-mux-locked-muxah ]h"]-parent-locked mux as parent of mux-locked muxah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hTwo mux-locked sibling muxesh]hTwo mux-locked sibling muxes}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhhhM+ubh)}(hThis is a good topology::h]hThis is a good topology:}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj%hhubj)}(hX7 .--------. .----------. .--| dev D1 | | mux- |--' '--------' .--| locked | .--------. | | mux M1 |-----| dev D2 | | '----------' '--------' | .----------. .--------. .--------. | | mux- |-----| dev D3 | | root |--+--| locked | '--------' '--------' | | mux M2 |--. .--------. | '----------' '--| dev D4 | | .--------. '--------' '--| dev D5 | '--------'h]hX7 .--------. .----------. .--| dev D1 | | mux- |--' '--------' .--| locked | .--------. | | mux M1 |-----| dev D2 | | '----------' '--------' | .----------. .--------. .--------. | | mux- |-----| dev D3 | | root |--+--| locked | '--------' '--------' | | mux M2 |--. .--------. | '----------' '--| dev D4 | | .--------. '--------' '--| dev D5 | '--------'}hjDsbah}(h]h ]h"]h$]h&]jjuh1jhhhM/hj%hhubh)}(hqWhen D1 is accessed, accesses to D2, D3 and D4 are locked out. But accesses to D5 may be interleaved at any time.h]hqWhen D1 is accessed, accesses to D2, D3 and D4 are locked out. But accesses to D5 may be interleaved at any time.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj%hhubeh}(h]two-mux-locked-sibling-muxesah ]h"]two mux-locked sibling muxesah$]h&]uh1hhjhhhhhM+ubh)}(hhh](h)}(hTwo parent-locked sibling muxesh]hTwo parent-locked sibling muxes}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhhMCubh)}(hThis is a good topology::h]hThis is a good topology:}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjhhhubj)}(hX7 .--------. .----------. .--| dev D1 | | parent- |--' '--------' .--| locked | .--------. | | mux M1 |-----| dev D2 | | '----------' '--------' | .----------. .--------. .--------. | | parent- |-----| dev D3 | | root |--+--| locked | '--------' '--------' | | mux M2 |--. .--------. | '----------' '--| dev D4 | | .--------. '--------' '--| dev D5 | '--------'h]hX7 .--------. .----------. .--| dev D1 | | parent- |--' '--------' .--| locked | .--------. | | mux M1 |-----| dev D2 | | '----------' '--------' | .----------. .--------. .--------. | | parent- |-----| dev D3 | | root |--+--| locked | '--------' '--------' | | mux M2 |--. .--------. | '----------' '--| dev D4 | | .--------. '--------' '--| dev D5 | '--------'}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhMGhjhhhubh)}(hJWhen any device is accessed, accesses to all other devices are locked out.h]hJWhen any device is accessed, accesses to all other devices are locked out.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjhhhubeh}(h]two-parent-locked-sibling-muxesah ]h"]two parent-locked sibling muxesah$]h&]uh1hhjhhhhhMCubh)}(hhh](h)}(h*Mux-locked and parent-locked sibling muxesh]h*Mux-locked and parent-locked sibling muxes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM[ubh)}(hThis is a good topology::h]hThis is a good topology:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjhhubj)}(hX7 .--------. .----------. .--| dev D1 | | mux- |--' '--------' .--| locked | .--------. | | mux M1 |-----| dev D2 | | '----------' '--------' | .----------. .--------. .--------. | | parent- |-----| dev D3 | | root |--+--| locked | '--------' '--------' | | mux M2 |--. .--------. | '----------' '--| dev D4 | | .--------. '--------' '--| dev D5 | '--------'h]hX7 .--------. .----------. .--| dev D1 | | mux- |--' '--------' .--| locked | .--------. | | mux M1 |-----| dev D2 | | '----------' '--------' | .----------. .--------. .--------. | | parent- |-----| dev D3 | | root |--+--| locked | '--------' '--------' | | mux M2 |--. .--------. | '----------' '--| dev D4 | | .--------. '--------' '--| dev D5 | '--------'}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhM_hjhhubh)}(hWhen D1 or D2 are accessed, accesses to D3 and D4 are locked out while accesses to D5 may interleave. When D3 or D4 are accessed, accesses to all other devices are locked out.h]hWhen D1 or D2 are accessed, accesses to D3 and D4 are locked out while accesses to D5 may interleave. When D3 or D4 are accessed, accesses to all other devices are locked out.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhjhhubeh}(h]*mux-locked-and-parent-locked-sibling-muxesah ]h"]*mux-locked and parent-locked sibling muxesah$]h&]uh1hhjhhhhhM[ubeh}(h]complex-examplesah ]h"]complex examplesah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h#Mux type of existing device driversh]h#Mux type of existing device drivers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMtubh)}(hWhether a device is mux-locked or parent-locked depends on its implementation. The following list was correct at the time of writing:h]hWhether a device is mux-locked or parent-locked depends on its implementation. The following list was correct at the time of writing:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjhhubh)}(hIn drivers/i2c/muxes/:h]hIn drivers/i2c/muxes/:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j-hj*ubj.)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1j-hj*ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hi2c-arb-gpio-challengeh]hi2c-arb-gpio-challenge}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjOubah}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh]h)}(h Parent-lockedh]h Parent-locked}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjfubah}(h]h ]h"]h$]h&]uh1jMhjJubeh}(h]h ]h"]h$]h&]uh1jHhjEubjI)}(hhh](jN)}(hhh]h)}(h i2c-mux-gpioh]h i2c-mux-gpio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjubah}(h]h ]h"]h$]h&]uh1jMhjubjN)}(hhh]h)}(hxNormally parent-locked, mux-locked iff all involved gpio pins are controlled by the same I2C root adapter that they mux.h]hxNormally parent-locked, mux-locked iff all involved gpio pins are controlled by the same I2C root adapter that they mux.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjubah}(h]h ]h"]h$]h&]uh1jMhjubeh}(h]h ]h"]h$]h&]uh1jHhjEubjI)}(hhh](jN)}(hhh]h)}(h i2c-mux-gpmuxh]h i2c-mux-gpmux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jMhjubjN)}(hhh]h)}(h@Normally parent-locked, mux-locked iff specified in device-tree.h]h@Normally parent-locked, mux-locked iff specified in device-tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jMhjubeh}(h]h ]h"]h$]h&]uh1jHhjEubjI)}(hhh](jN)}(hhh]h)}(hi2c-mux-ltc4306h]hi2c-mux-ltc4306}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jMhjubjN)}(hhh]h)}(h Mux-lockedh]h Mux-locked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhjubeh}(h]h ]h"]h$]h&]uh1jHhjEubjI)}(hhh](jN)}(hhh]h)}(hi2c-mux-mlxcpldh]hi2c-mux-mlxcpld}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ ubah}(h]h ]h"]h$]h&]uh1jMhj( ubjN)}(hhh]h)}(h Parent-lockedh]h Parent-locked}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjB ubah}(h]h ]h"]h$]h&]uh1jMhj( ubeh}(h]h ]h"]h$]h&]uh1jHhjEubjI)}(hhh](jN)}(hhh]h)}(hi2c-mux-pca9541h]hi2c-mux-pca9541}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjb ubah}(h]h ]h"]h$]h&]uh1jMhj_ ubjN)}(hhh]h)}(h Parent-lockedh]h Parent-locked}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjy ubah}(h]h ]h"]h$]h&]uh1jMhj_ ubeh}(h]h ]h"]h$]h&]uh1jHhjEubjI)}(hhh](jN)}(hhh]h)}(hi2c-mux-pca954xh]hi2c-mux-pca954x}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubjN)}(hhh]h)}(h Parent-lockedh]h Parent-locked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubeh}(h]h ]h"]h$]h&]uh1jHhjEubjI)}(hhh](jN)}(hhh]h)}(hi2c-mux-pinctrlh]hi2c-mux-pinctrl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubjN)}(hhh]h)}(h~Normally parent-locked, mux-locked iff all involved pinctrl devices are controlled by the same I2C root adapter that they mux.h]h~Normally parent-locked, mux-locked iff all involved pinctrl devices are controlled by the same I2C root adapter that they mux.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubeh}(h]h ]h"]h$]h&]uh1jHhjEubjI)}(hhh](jN)}(hhh]h)}(h i2c-mux-regh]h i2c-mux-reg}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubjN)}(hhh]h)}(h Parent-lockedh]h Parent-locked}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubeh}(h]h ]h"]h$]h&]uh1jHhjEubeh}(h]h ]h"]h$]h&]uh1jChj*ubeh}(h]h ]h"]h$]h&]colsKuh1j(hj%ubah}(h]h ]h"]h$]h&]uh1j#hjhhhhhNubh)}(hIn drivers/iio/:h]hIn drivers/iio/:}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj$)}(hhh]j))}(hhh](j.)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j-hj_ ubj.)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1j-hj_ ubjD)}(hhh](jI)}(hhh](jN)}(hhh]h)}(h gyro/mpu3050h]h gyro/mpu3050}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj| ubah}(h]h ]h"]h$]h&]uh1jMhjy ubjN)}(hhh]h)}(h Mux-lockedh]h Mux-locked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhjy ubeh}(h]h ]h"]h$]h&]uh1jHhjv ubjI)}(hhh](jN)}(hhh]h)}(himu/inv_mpu6050/h]himu/inv_mpu6050/}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubjN)}(hhh]h)}(h Mux-lockedh]h Mux-locked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubeh}(h]h ]h"]h$]h&]uh1jHhjv ubeh}(h]h ]h"]h$]h&]uh1jChj_ ubeh}(h]h ]h"]h$]h&]colsKuh1j(hj\ ubah}(h]h ]h"]h$]h&]uh1j#hjhhhhhNubh)}(hIn drivers/media/:h]hIn drivers/media/:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj$)}(hhh]j))}(hhh](j.)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j-hj ubj.)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1j-hj ubjD)}(hhh](jI)}(hhh](jN)}(hhh]h)}(hdvb-frontends/lgdt3306ah]hdvb-frontends/lgdt3306a}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj( ubah}(h]h ]h"]h$]h&]uh1jMhj% ubjN)}(hhh]h)}(h Mux-lockedh]h Mux-locked}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj? ubah}(h]h ]h"]h$]h&]uh1jMhj% ubeh}(h]h ]h"]h$]h&]uh1jHhj" ubjI)}(hhh](jN)}(hhh]h)}(hdvb-frontends/m88ds3103h]hdvb-frontends/m88ds3103}(hjb hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_ ubah}(h]h ]h"]h$]h&]uh1jMhj\ ubjN)}(hhh]h)}(h Parent-lockedh]h Parent-locked}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjv ubah}(h]h ]h"]h$]h&]uh1jMhj\ ubeh}(h]h ]h"]h$]h&]uh1jHhj" ubjI)}(hhh](jN)}(hhh]h)}(hdvb-frontends/rtl2830h]hdvb-frontends/rtl2830}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubjN)}(hhh]h)}(h Parent-lockedh]h Parent-locked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubeh}(h]h ]h"]h$]h&]uh1jHhj" ubjI)}(hhh](jN)}(hhh]h)}(hdvb-frontends/rtl2832h]hdvb-frontends/rtl2832}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubjN)}(hhh]h)}(h Mux-lockedh]h Mux-locked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubeh}(h]h ]h"]h$]h&]uh1jHhj" ubjI)}(hhh](jN)}(hhh]h)}(hdvb-frontends/si2168h]hdvb-frontends/si2168}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubjN)}(hhh]h)}(h Mux-lockedh]h Mux-locked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jMhj ubeh}(h]h ]h"]h$]h&]uh1jHhj" ubjI)}(hhh](jN)}(hhh]h)}(h usb/cx231xx/h]h usb/cx231xx/}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj; ubah}(h]h ]h"]h$]h&]uh1jMhj8 ubjN)}(hhh]h)}(h Parent-lockedh]h Parent-locked}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjR ubah}(h]h ]h"]h$]h&]uh1jMhj8 ubeh}(h]h ]h"]h$]h&]uh1jHhj" ubeh}(h]h ]h"]h$]h&]uh1jChj ubeh}(h]h ]h"]h$]h&]colsKuh1j(hj ubah}(h]h ]h"]h$]h&]uh1j#hjhhhhhNubeh}(h]#mux-type-of-existing-device-driversah ]h"]#mux type of existing device driversah$]h&]uh1hhhhhhhhMtubeh}(h] i2c-muxes-and-complex-topologiesah ]h"] i2c muxes and complex topologiesah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjMfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j j jjjjjjjjjjjjjjjjjjjdjajjj"jjejbjjjjj j u nametypes}(j jjjjjjjjjjdjj"jejjj uh}(j hjjYjjxjjjjjjjjjjjjjjjajjjgjjjbj%jjhjjj ju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.