€•¸f      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ(/translations/zh_CN/i2c/busses/i2c-piix4”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/zh_TW/i2c/busses/i2c-piix4”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/it_IT/i2c/busses/i2c-piix4”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/ja_JP/i2c/busses/i2c-piix4”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/ko_KR/i2c/busses/i2c-piix4”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/sp_SP/i2c/busses/i2c-piix4”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒKernel driver i2c-piix4”h]”hŒKernel driver i2c-piix4”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒB/var/lib/git/docbuild/linux/Documentation/i2c/busses/i2c-piix4.rst”h KubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hXo  Supported adapters:
* Intel 82371AB PIIX4 and PIIX4E
* Intel 82443MX (440MX)
  Datasheet: Publicly available at the Intel website
* ServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges
  Datasheet: Only available via NDA from ServerWorks
* ATI IXP200, IXP300, IXP400, SB600, SB700 and SB800 southbridges
  Datasheet: Not publicly available
  SB700 register reference available at:
  http://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf
* AMD SP5100 (SB700 derivative found on some server mainboards)
  Datasheet: Publicly available at the AMD website
  http://support.amd.com/us/Embedded_TechDocs/44413.pdf
* AMD Hudson-2, ML, CZ
  Datasheet: Not publicly available
* Hygon CZ
  Datasheet: Not publicly available
* Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
  Datasheet: Publicly available at the SMSC website http://www.smsc.com
”h]”(hŒterm”“”)”}”(hŒSupported adapters:”h]”hŒSupported adapters:”…””}”(hhÄhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÂhŸh¶h Khh¾ubhŒ
definition”“”)”}”(hhh]”hŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒIntel 82371AB PIIX4 and PIIX4E”h]”hŒ	paragraph”“”)”}”(hhàh]”hŒIntel 82371AB PIIX4 and PIIX4E”…””}”(hhähžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h KhhÞubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhhÙubhÝ)”}”(hŒHIntel 82443MX (440MX)
Datasheet: Publicly available at the Intel website”h]”hã)”}”(hŒHIntel 82443MX (440MX)
Datasheet: Publicly available at the Intel website”h]”hŒHIntel 82443MX (440MX)
Datasheet: Publicly available at the Intel website”…””}”(hhûhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Khh÷ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhhÙubhÝ)”}”(hŒqServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges
Datasheet: Only available via NDA from ServerWorks”h]”hã)”}”(hŒqServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges
Datasheet: Only available via NDA from ServerWorks”h]”hŒqServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges
Datasheet: Only available via NDA from ServerWorks”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K	hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhhÙubhÝ)”}”(hŒÑATI IXP200, IXP300, IXP400, SB600, SB700 and SB800 southbridges
Datasheet: Not publicly available
SB700 register reference available at:
http://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf”h]”hã)”}”(hŒÑATI IXP200, IXP300, IXP400, SB600, SB700 and SB800 southbridges
Datasheet: Not publicly available
SB700 register reference available at:
http://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf”h]”(hŒ‰ATI IXP200, IXP300, IXP400, SB600, SB700 and SB800 southbridges
Datasheet: Not publicly available
SB700 register reference available at:
”…””}”(hj+  hžhhŸNh NubhŒ	reference”“”)”}”(hŒHhttp://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf”h]”hŒHhttp://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf”…””}”(hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j7  uh1j3  hj+  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Khj'  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhhÙubhÝ)”}”(hŒ¤AMD SP5100 (SB700 derivative found on some server mainboards)
Datasheet: Publicly available at the AMD website
http://support.amd.com/us/Embedded_TechDocs/44413.pdf”h]”hã)”}”(hŒ¤AMD SP5100 (SB700 derivative found on some server mainboards)
Datasheet: Publicly available at the AMD website
http://support.amd.com/us/Embedded_TechDocs/44413.pdf”h]”(hŒoAMD SP5100 (SB700 derivative found on some server mainboards)
Datasheet: Publicly available at the AMD website
”…””}”(hjT  hžhhŸNh Nubj4  )”}”(hŒ5http://support.amd.com/us/Embedded_TechDocs/44413.pdf”h]”hŒ5http://support.amd.com/us/Embedded_TechDocs/44413.pdf”…””}”(hj\  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j^  uh1j3  hjT  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h KhjP  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhhÙubhÝ)”}”(hŒ6AMD Hudson-2, ML, CZ
Datasheet: Not publicly available”h]”hã)”}”(hŒ6AMD Hudson-2, ML, CZ
Datasheet: Not publicly available”h]”hŒ6AMD Hudson-2, ML, CZ
Datasheet: Not publicly available”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Khjw  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhhÙubhÝ)”}”(hŒ*Hygon CZ
Datasheet: Not publicly available”h]”hã)”}”(hŒ*Hygon CZ
Datasheet: Not publicly available”h]”hŒ*Hygon CZ
Datasheet: Not publicly available”…””}”(hj“  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhhÙubhÝ)”}”(hŒ„Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
Datasheet: Publicly available at the SMSC website http://www.smsc.com
”h]”hã)”}”(hŒƒStandard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
Datasheet: Publicly available at the SMSC website http://www.smsc.com”h]”(hŒpStandard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
Datasheet: Publicly available at the SMSC website ”…””}”(hj«  hžhhŸNh Nubj4  )”}”(hŒhttp://www.smsc.com”h]”hŒhttp://www.smsc.com”…””}”(hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jµ  uh1j3  hj«  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Khj§  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhhÙubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1h×hŸh¶h KhhÔubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhh¾ubeh}”(h]”h ]”h"]”h$]”h&]”uh1h¼hŸh¶h Khh¹ubh½)”}”(hŒTAuthors:
- Frodo Looijaard <frodol@dds.nl>
- Philip Edelbrock <phil@netroedge.com>

”h]”(hÃ)”}”(hŒAuthors:”h]”hŒAuthors:”…””}”(hjæ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÂhŸh¶h Khjâ  ubhÓ)”}”(hhh]”hØ)”}”(hhh]”(hÝ)”}”(hŒFrodo Looijaard <frodol@dds.nl>”h]”hã)”}”(hjü  h]”(hŒFrodo Looijaard <”…””}”(hjþ  hžhhŸNh Nubj4  )”}”(hŒfrodol@dds.nl”h]”hŒfrodol@dds.nl”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:frodol@dds.nl”uh1j3  hjþ  ubhŒ>”…””}”(hjþ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Khjú  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhj÷  ubhÝ)”}”(hŒ'Philip Edelbrock <phil@netroedge.com>

”h]”hã)”}”(hŒ%Philip Edelbrock <phil@netroedge.com>”h]”(hŒPhilip Edelbrock <”…””}”(hj)  hžhhŸNh Nubj4  )”}”(hŒphil@netroedge.com”h]”hŒphil@netroedge.com”…””}”(hj1  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:phil@netroedge.com”uh1j3  hj)  ubhŒ>”…””}”(hj)  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Khj%  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhj÷  ubeh}”(h]”h ]”h"]”h$]”h&]”jÔ  Œ-”uh1h×hŸh¶h Khjô  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjâ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1h¼hŸh¶h Khh¹hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hh£hžhhŸNh Nubh¢)”}”(hhh]”(h§)”}”(hŒModule Parameters”h]”hŒModule Parameters”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjj  hžhhŸh¶h KubhØ)”}”(hhh]”(hÝ)”}”(hŒ0force: int
Forcibly enable the PIIX4. DANGEROUS!”h]”hã)”}”(hŒ0force: int
Forcibly enable the PIIX4. DANGEROUS!”h]”hŒ0force: int
Forcibly enable the PIIX4. DANGEROUS!”…””}”(hj‚  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K!hj~  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhj{  hžhhŸh¶h NubhÝ)”}”(hŒVforce_addr: int
Forcibly enable the PIIX4 at the given address. EXTREMELY DANGEROUS!

”h]”hã)”}”(hŒTforce_addr: int
Forcibly enable the PIIX4 at the given address. EXTREMELY DANGEROUS!”h]”hŒTforce_addr: int
Forcibly enable the PIIX4 at the given address. EXTREMELY DANGEROUS!”…””}”(hjš  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K#hj–  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhj{  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jÔ  jÕ  uh1h×hŸh¶h K!hjj  hžhubeh}”(h]”Œmodule-parameters”ah ]”h"]”Œmodule parameters”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒDescription”h]”hŒDescription”…””}”(hj¿  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¼  hžhhŸh¶h K(ubhã)”}”(hXç  The PIIX4 (properly known as the 82371AB) is an Intel chip with a lot of
functionality. Among other things, it implements the PCI bus. One of its
minor functions is implementing a System Management Bus. This is a true
SMBus - you can not access it on I2C levels. The good news is that it
natively understands SMBus commands and you do not have to worry about
timing problems. The bad news is that non-SMBus devices connected to it can
confuse it mightily. Yes, this is known to happen...”h]”hXç  The PIIX4 (properly known as the 82371AB) is an Intel chip with a lot of
functionality. Among other things, it implements the PCI bus. One of its
minor functions is implementing a System Management Bus. This is a true
SMBus - you can not access it on I2C levels. The good news is that it
natively understands SMBus commands and you do not have to worry about
timing problems. The bad news is that non-SMBus devices connected to it can
confuse it mightily. Yes, this is known to happen...”…””}”(hjÍ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K*hj¼  hžhubhã)”}”(hŒ@Do ``lspci -v`` and see whether it contains an entry like this::”h]”(hŒDo ”…””}”(hjÛ  hžhhŸNh NubhŒliteral”“”)”}”(hŒ``lspci -v``”h]”hŒlspci -v”…””}”(hjå  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jã  hjÛ  ubhŒ0 and see whether it contains an entry like this:”…””}”(hjÛ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K2hj¼  hžhubhŒliteral_block”“”)”}”(hŒk0000:00:02.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02)
             Flags: medium devsel, IRQ 9”h]”hŒk0000:00:02.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02)
             Flags: medium devsel, IRQ 9”…””}”hjÿ  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jý  hŸh¶h K4hj¼  hžhubhã)”}”(hX
  Bus and device numbers may differ, but the function number must be
identical (like many PCI devices, the PIIX4 incorporates a number of
different 'functions', which can be considered as separate devices). If you
find such an entry, you have a PIIX4 SMBus controller.”h]”hX  Bus and device numbers may differ, but the function number must be
identical (like many PCI devices, the PIIX4 incorporates a number of
different â€˜functionsâ€™, which can be considered as separate devices). If you
find such an entry, you have a PIIX4 SMBus controller.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K7hj¼  hžhubhã)”}”(hX0  On some computers (most notably, some Dells), the SMBus is disabled by
default. If you use the insmod parameter 'force=1', the kernel module will
try to enable it. THIS IS VERY DANGEROUS! If the BIOS did not set up a
correct address for this module, you could get in big trouble (read:
crashes, data corruption, etc.). Try this only as a last resort (try BIOS
updates first, for example), and backup first! An even more dangerous
option is 'force_addr=<IOPORT>'. This will not only enable the PIIX4 like
'force' does, but it will also set a new base I/O port address. The SMBus
parts of the PIIX4 needs a range of 8 of these addresses to function
correctly. If these addresses are already reserved by some other device,
you will get into big trouble! DON'T USE THIS IF YOU ARE NOT VERY SURE
ABOUT WHAT YOU ARE DOING!”h]”hX>  On some computers (most notably, some Dells), the SMBus is disabled by
default. If you use the insmod parameter â€˜force=1â€™, the kernel module will
try to enable it. THIS IS VERY DANGEROUS! If the BIOS did not set up a
correct address for this module, you could get in big trouble (read:
crashes, data corruption, etc.). Try this only as a last resort (try BIOS
updates first, for example), and backup first! An even more dangerous
option is â€˜force_addr=<IOPORT>â€™. This will not only enable the PIIX4 like
â€˜forceâ€™ does, but it will also set a new base I/O port address. The SMBus
parts of the PIIX4 needs a range of 8 of these addresses to function
correctly. If these addresses are already reserved by some other device,
you will get into big trouble! DONâ€™T USE THIS IF YOU ARE NOT VERY SURE
ABOUT WHAT YOU ARE DOING!”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K<hj¼  hžhubhã)”}”(hŒ±The PIIX4E is just an new version of the PIIX4; it is supported as well.
The PIIX/PIIX3 does not implement an SMBus or I2C bus, so you can't use
this driver on those mainboards.”h]”hŒ³The PIIX4E is just an new version of the PIIX4; it is supported as well.
The PIIX/PIIX3 does not implement an SMBus or I2C bus, so you canâ€™t use
this driver on those mainboards.”…””}”(hj+  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h KIhj¼  hžhubhã)”}”(hŒqThe ServerWorks Southbridges, the Intel 440MX, and the Victory66 are
identical to the PIIX4 in I2C/SMBus support.”h]”hŒqThe ServerWorks Southbridges, the Intel 440MX, and the Victory66 are
identical to the PIIX4 in I2C/SMBus support.”…””}”(hj9  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h KMhj¼  hžhubhã)”}”(hŒãThe AMD SB700, SB800, SP5100 and Hudson-2 chipsets implement two
PIIX4-compatible SMBus controllers. If your BIOS initializes the
secondary controller, it will be detected by this driver as
an "Auxiliary SMBus Host Controller".”h]”hŒçThe AMD SB700, SB800, SP5100 and Hudson-2 chipsets implement two
PIIX4-compatible SMBus controllers. If your BIOS initializes the
secondary controller, it will be detected by this driver as
an â€œAuxiliary SMBus Host Controllerâ€.”…””}”(hjG  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h KPhj¼  hžhubhã)”}”(hŒ¦If you own Force CPCI735 motherboard or other OSB4 based systems you may need
to change the SMBus Interrupt Select register so the SMBus controller uses
the SMI mode.”h]”hŒ¦If you own Force CPCI735 motherboard or other OSB4 based systems you may need
to change the SMBus Interrupt Select register so the SMBus controller uses
the SMI mode.”…””}”(hjU  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h KUhj¼  hžhubhŒenumerated_list”“”)”}”(hhh]”(hÝ)”}”(hX:  Use ``lspci`` command and locate the PCI device with the SMBus controller:
00:0f.0 ISA bridge: ServerWorks OSB4 South Bridge (rev 4f)
The line may vary for different chipsets. Please consult the driver source
for all possible PCI ids (and ``lspci -n`` to match them). Let's assume the
device is located at 00:0f.0.”h]”hã)”}”(hX:  Use ``lspci`` command and locate the PCI device with the SMBus controller:
00:0f.0 ISA bridge: ServerWorks OSB4 South Bridge (rev 4f)
The line may vary for different chipsets. Please consult the driver source
for all possible PCI ids (and ``lspci -n`` to match them). Let's assume the
device is located at 00:0f.0.”h]”(hŒUse ”…””}”(hjl  hžhhŸNh Nubjä  )”}”(hŒ	``lspci``”h]”hŒlspci”…””}”(hjt  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jã  hjl  ubhŒâ command and locate the PCI device with the SMBus controller:
00:0f.0 ISA bridge: ServerWorks OSB4 South Bridge (rev 4f)
The line may vary for different chipsets. Please consult the driver source
for all possible PCI ids (and ”…””}”(hjl  hžhhŸNh Nubjä  )”}”(hŒ``lspci -n``”h]”hŒlspci -n”…””}”(hj†  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jã  hjl  ubhŒA to match them). Letâ€™s assume the
device is located at 00:0f.0.”…””}”(hjl  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h KYhjh  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhje  hžhhŸh¶h NubhÝ)”}”(hŒÂNow you just need to change the value in 0xD2 register. Get it first with
command: ``lspci -xxx -s 00:0f.0``
If the value is 0x3 then you need to change it to 0x1:
``setpci  -s 00:0f.0 d2.b=1``
”h]”hã)”}”(hŒÁNow you just need to change the value in 0xD2 register. Get it first with
command: ``lspci -xxx -s 00:0f.0``
If the value is 0x3 then you need to change it to 0x1:
``setpci  -s 00:0f.0 d2.b=1``”h]”(hŒSNow you just need to change the value in 0xD2 register. Get it first with
command: ”…””}”(hj¨  hžhhŸNh Nubjä  )”}”(hŒ``lspci -xxx -s 00:0f.0``”h]”hŒlspci -xxx -s 00:0f.0”…””}”(hj°  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jã  hj¨  ubhŒ8
If the value is 0x3 then you need to change it to 0x1:
”…””}”(hj¨  hžhhŸNh Nubjä  )”}”(hŒ``setpci  -s 00:0f.0 d2.b=1``”h]”hŒsetpci  -s 00:0f.0 d2.b=1”…””}”(hjÂ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jã  hj¨  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K^hj¤  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhje  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ)”uh1jc  hj¼  hžhhŸh¶h KYubhã)”}”(hŒePlease note that you don't need to do that in all cases, just when the SMBus is
not working properly.”h]”hŒgPlease note that you donâ€™t need to do that in all cases, just when the SMBus is
not working properly.”…””}”(hjç  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Kchj¼  hžhubeh}”(h]”Œdescription”ah ]”h"]”Œdescription”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K(ubh¢)”}”(hhh]”(h§)”}”(hŒHardware-specific issues”h]”hŒHardware-specific issues”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjý  hžhhŸh¶h Khubhã)”}”(hX±  This driver will refuse to load on IBM systems with an Intel PIIX4 SMBus.
Some of these machines have an RFID EEPROM (24RF08) connected to the SMBus,
which can easily get corrupted due to a state machine bug. These are mostly
Thinkpad laptops, but desktop systems may also be affected. We have no list
of all affected systems, so the only safe solution was to prevent access to
the SMBus on all IBM systems (detected using DMI data.)”h]”hX±  This driver will refuse to load on IBM systems with an Intel PIIX4 SMBus.
Some of these machines have an RFID EEPROM (24RF08) connected to the SMBus,
which can easily get corrupted due to a state machine bug. These are mostly
Thinkpad laptops, but desktop systems may also be affected. We have no list
of all affected systems, so the only safe solution was to prevent access to
the SMBus on all IBM systems (detected using DMI data.)”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Kjhjý  hžhubeh}”(h]”Œhardware-specific-issues”ah ]”h"]”Œhardware-specific issues”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Khubh¢)”}”(hhh]”(h§)”}”(hŒDescription in the ACPI code”h]”hŒDescription in the ACPI code”…””}”(hj'  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj$  hžhhŸh¶h Ksubhã)”}”(hŒSDevice driver for the PIIX4 chip creates a separate I2C bus for each of its
ports::”h]”hŒRDevice driver for the PIIX4 chip creates a separate I2C bus for each of its
ports:”…””}”(hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Kuhj$  hžhubjþ  )”}”(hŒâ$ i2cdetect -l
...
i2c-7   unknown         SMBus PIIX4 adapter port 0 at 0b00      N/A
i2c-8   unknown         SMBus PIIX4 adapter port 2 at 0b00      N/A
i2c-9   unknown         SMBus PIIX4 adapter port 1 at 0b20      N/A
...”h]”hŒâ$ i2cdetect -l
...
i2c-7   unknown         SMBus PIIX4 adapter port 0 at 0b00      N/A
i2c-8   unknown         SMBus PIIX4 adapter port 2 at 0b00      N/A
i2c-9   unknown         SMBus PIIX4 adapter port 1 at 0b20      N/A
...”…””}”hjC  sbah}”(h]”h ]”h"]”h$]”h&]”j  j  uh1jý  hŸh¶h Kxhj$  hžhubhã)”}”(hŒˆTherefore if you want to access one of these busses in the ACPI code, port
subdevices are needed to be declared inside the PIIX device::”h]”hŒ‡Therefore if you want to access one of these busses in the ACPI code, port
subdevices are needed to be declared inside the PIIX device:”…””}”(hjQ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h Khj$  hžhubjþ  )”}”(hŒËScope (\_SB_.PCI0.SMBS)
{
    Name (_ADR, 0x00140000)

    Device (SMB0) {
        Name (_ADR, 0)
    }
    Device (SMB1) {
        Name (_ADR, 1)
    }
    Device (SMB2) {
        Name (_ADR, 2)
    }
}”h]”hŒËScope (\_SB_.PCI0.SMBS)
{
    Name (_ADR, 0x00140000)

    Device (SMB0) {
        Name (_ADR, 0)
    }
    Device (SMB1) {
        Name (_ADR, 1)
    }
    Device (SMB2) {
        Name (_ADR, 2)
    }
}”…””}”hj_  sbah}”(h]”h ]”h"]”h$]”h&]”j  j  uh1jý  hŸh¶h K‚hj$  hžhubhã)”}”(hX`  If this is not the case for your UEFI firmware and you don't have access to the
source code, you can use ACPI SSDT Overlays to provide the missing parts. Just
keep in mind that in this case you would need to load your extra SSDT table
before the piix4 driver starts, i.e. you should provide SSDT via initrd or EFI
variable methods and not via configfs.”h]”hXb  If this is not the case for your UEFI firmware and you donâ€™t have access to the
source code, you can use ACPI SSDT Overlays to provide the missing parts. Just
keep in mind that in this case you would need to load your extra SSDT table
before the piix4 driver starts, i.e. you should provide SSDT via initrd or EFI
variable methods and not via configfs.”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K‘hj$  hžhubhã)”}”(hŒ‘As an example of usage here is the ACPI snippet code that would assign jc42
driver to the 0x1C device on the I2C bus created by the PIIX port 0::”h]”hŒAs an example of usage here is the ACPI snippet code that would assign jc42
driver to the 0x1C device on the I2C bus created by the PIIX port 0:”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hâhŸh¶h K—hj$  hžhubjþ  )”}”(hX  Device (JC42) {
    Name (_HID, "PRP0001")
    Name (_DDN, "JC42 Temperature sensor")
    Name (_CRS, ResourceTemplate () {
        I2cSerialBusV2 (
            0x001c,
            ControllerInitiated,
            100000,
            AddressingMode7Bit,
            "\\_SB.PCI0.SMBS.SMB0",
            0
        )
    })

    Name (_DSD, Package () {
        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
        Package () {
            Package () { "compatible", Package() { "jedec,jc-42.4-temp" } },
        }
    })
}”h]”hX  Device (JC42) {
    Name (_HID, "PRP0001")
    Name (_DDN, "JC42 Temperature sensor")
    Name (_CRS, ResourceTemplate () {
        I2cSerialBusV2 (
            0x001c,
            ControllerInitiated,
            100000,
            AddressingMode7Bit,
            "\\_SB.PCI0.SMBS.SMB0",
            0
        )
    })

    Name (_DSD, Package () {
        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
        Package () {
            Package () { "compatible", Package() { "jedec,jc-42.4-temp" } },
        }
    })
}”…””}”hj‰  sbah}”(h]”h ]”h"]”h$]”h&]”j  j  uh1jý  hŸh¶h Kšhj$  hžhubeh}”(h]”Œdescription-in-the-acpi-code”ah ]”h"]”Œdescription in the acpi code”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Ksubeh}”(h]”Œkernel-driver-i2c-piix4”ah ]”h"]”Œkernel driver i2c-piix4”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jÊ  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j¤  j¡  j¹  j¶  jú  j÷  j!  j  jœ  j™  uŒ	nametypes”}”(j¤  ‰j¹  ‰jú  ‰j!  ‰jœ  ‰uh}”(j¡  h£j¶  jj  j÷  j¼  j  jý  j™  j$  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.