1Osphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/pt_BR/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hDriver i2c-mlxcpldh]hDriver i2c-mlxcpld}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/i2c/busses/i2c-mlxcpld.rsthKubh paragraph)}(h.Author: Michael Shych h](hAuthor: Michael Shych <}(hhhhhNhNubh reference)}(hmichaelsh@mellanox.comh]hmichaelsh@mellanox.com}(hhhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:michaelsh@mellanox.comuh1hhhubh>}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hNThis is the Mellanox I2C controller logic, implemented in Lattice CPLD device.h]hNThis is the Mellanox I2C controller logic, implemented in Lattice CPLD device.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hDDevice supports: - Master mode. - One physical bus. - Polling mode. h](hterm)}(hDevice supports:h]hDevice supports:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhK hjubh definition)}(hhh]h bullet_list)}(hhh](h list_item)}(h Master mode.h]h)}(hj(h]h Master mode.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj&ubah}(h]h ]h"]h$]h&]uh1j$hj!ubj%)}(hOne physical bus.h]h)}(hj?h]hOne physical bus.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj=ubah}(h]h ]h"]h$]h&]uh1j$hj!ubj%)}(hPolling mode. h]h)}(h Polling mode.h]h Polling mode.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjTubah}(h]h ]h"]h$]h&]uh1j$hj!ubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubh)}(hThis controller is equipped within the next Mellanox systems: "msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", "msn2740", "msn2100".h]hThis controller is equipped within the next Mellanox systems: “msx6710”, “msx6720”, “msb7700”, “msn2700”, “msx1410”, “msn2410”, “msb7800”, “msn2740”, “msn2100”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubj)}(hhh]j)}(hzThe next transaction types are supported: - Receive Byte/Block. - Send Byte/Block. - Read Byte/Block. - Write Byte/Block. h](j )}(h)The next transaction types are supported:h]h)The next transaction types are supported:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhKhjubj)}(hhh]j )}(hhh](j%)}(hReceive Byte/Block.h]h)}(hjh]hReceive Byte/Block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjubj%)}(hSend Byte/Block.h]h)}(hjh]hSend Byte/Block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjubj%)}(hRead Byte/Block.h]h)}(hjh]hRead Byte/Block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjubj%)}(hWrite Byte/Block. h]h)}(hWrite Byte/Block.h]hWrite Byte/Block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]jrjsuh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubh)}(h Registers:h]h Registers:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j<hj9ubj=)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j<hj9ubj=)}(hhh]h}(h]h ]h"]h$]h&]colwidthKGuh1j<hj9ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hCPBLTYh]hCPBLTY}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhubah}(h]h ]h"]h$]h&]uh1jfhjcubjg)}(hhh]h)}(h0x0h]h0x0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jfhjcubjg)}(hhh]j )}(hhh]j%)}(hcapability reg. Bits [6:5] - transaction length. b01 - 72B is supported, 36B in other case. Bit 7 - SMBus block read support.h]j)}(hhh]j)}(h}capability reg. Bits [6:5] - transaction length. b01 - 72B is supported, 36B in other case. Bit 7 - SMBus block read support.h](j )}(hcapability reg.h]hcapability reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhKhjubj)}(hhh]h)}(hmBits [6:5] - transaction length. b01 - 72B is supported, 36B in other case. Bit 7 - SMBus block read support.h]hmBits [6:5] - transaction length. b01 - 72B is supported, 36B in other case. Bit 7 - SMBus block read support.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1j$hjubah}(h]h ]h"]h$]h&]jrjsuh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jfhjcubeh}(h]h ]h"]h$]h&]uh1jahj^ubjb)}(hhh](jg)}(hhh]h)}(hCTRLh]hCTRL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]h)}(h0x1h]h0x1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj ubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]j )}(hhh]j%)}(h(control reg. Resets all the registers.h]j)}(hhh]j)}(h&control reg. Resets all the registers.h](j )}(h control reg.h]h control reg.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhK hj.ubj)}(hhh]h)}(hResets all the registers.h]hResets all the registers.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hj@ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhhhK hj+ubah}(h]h ]h"]h$]h&]uh1hhj'ubah}(h]h ]h"]h$]h&]uh1j$hj$ubah}(h]h ]h"]h$]h&]jrjsuh1jhhhK hj!ubah}(h]h ]h"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]uh1jahj^ubjb)}(hhh](jg)}(hhh]h)}(hHALF_CYCh]hHALF_CYC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hj~ubah}(h]h ]h"]h$]h&]uh1jfhj{ubjg)}(hhh]h)}(h0x4h]h0x4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1jfhj{ubjg)}(hhh]j )}(hhh]j%)}(hTcycle reg. Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK units).h]j)}(hhh]j)}(hPcycle reg. Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK units).h](j )}(h cycle reg.h]h cycle reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhK#hjubj)}(hhh]h)}(hEConfigure the width of I2C SCL half clock cycle (in 4 LPC_CLK units).h]hEConfigure the width of I2C SCL half clock cycle (in 4 LPC_CLK units).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK#hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1j$hjubah}(h]h ]h"]h$]h&]jrjsuh1jhhhK"hjubah}(h]h ]h"]h$]h&]uh1jfhj{ubeh}(h]h ]h"]h$]h&]uh1jahj^ubjb)}(hhh](jg)}(hhh]h)}(hI2C_HOLDh]hI2C_HOLD}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hj ubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]h)}(h0x5h]h0x5}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hj ubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]j )}(hhh]j%)}(h\hold reg. OE (output enable) is delayed by value set to this register (in LPC_CLK units)h]j)}(hhh]j)}(hXhold reg. OE (output enable) is delayed by value set to this register (in LPC_CLK units)h](j )}(h hold reg.h]h hold reg.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhK&hjDubj)}(hhh]h)}(hNOE (output enable) is delayed by value set to this register (in LPC_CLK units)h]hNOE (output enable) is delayed by value set to this register (in LPC_CLK units)}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjVubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhhhK&hjAubah}(h]h ]h"]h$]h&]uh1hhj=ubah}(h]h ]h"]h$]h&]uh1j$hj:ubah}(h]h ]h"]h$]h&]jrjsuh1jhhhK%hj7ubah}(h]h ]h"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]uh1jahj^ubjb)}(hhh](jg)}(hhh]h)}(hCMDh]hCMD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]h}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]h)}(h0x6 - command reg. Bit 0, 0 = write, 1 = read. Bits [7:1] - the 7bit Address of the I2C device. It should be written last as it triggers an I2C transaction.h]h0x6 - command reg. Bit 0, 0 = write, 1 = read. Bits [7:1] - the 7bit Address of the I2C device. It should be written last as it triggers an I2C transaction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]uh1jahj^ubjb)}(hhh](jg)}(hhh]h)}(hNUM_DATAh]hNUM_DATA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]h)}(h0x7h]h0x7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]j )}(hhh]j%)}(hBdata size reg. Number of data bytes to write in read transactionh]j)}(hhh]j)}(h@data size reg. Number of data bytes to write in read transactionh](j )}(hdata size reg.h]hdata size reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhK,hjubj)}(hhh]h)}(h1Number of data bytes to write in read transactionh]h1Number of data bytes to write in read transaction}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK,hj ubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1j$hjubah}(h]h ]h"]h$]h&]jrjsuh1jhhhK,hjubah}(h]h ]h"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]uh1jahj^ubjb)}(hhh](jg)}(hhh]h)}(hNUM_ADDRh]hNUM_ADDR}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hj_ubah}(h]h ]h"]h$]h&]uh1jfhj\ubjg)}(hhh]h)}(h0x8h]h0x8}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjvubah}(h]h ]h"]h$]h&]uh1jfhj\ubjg)}(hhh]j )}(hhh]j%)}(hDaddress reg. Number of address bytes to write in read transaction.h]j)}(hhh]j)}(hBaddress reg. Number of address bytes to write in read transaction.h](j )}(h address reg.h]h address reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhK.hjubj)}(hhh]h)}(h5Number of address bytes to write in read transaction.h]h5Number of address bytes to write in read transaction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK.hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1j$hjubah}(h]h ]h"]h$]h&]jrjsuh1jhhhK.hjubah}(h]h ]h"]h$]h&]uh1jfhj\ubeh}(h]h ]h"]h$]h&]uh1jahj^ubjb)}(hhh](jg)}(hhh]h)}(hSTATUSh]hSTATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]h)}(h0x9h]h0x9}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jfhjubjg)}(hhh]j )}(hhh]j%)}(hCstatus reg. Bit 0 - transaction is completed. Bit 4 - ACK/NACK.h]j)}(hhh]j)}(h?status reg. Bit 0 - transaction is completed. Bit 4 - ACK/NACK.h](j )}(h status reg.h]h status reg.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhK1hj%ubj)}(hhh]h)}(h3Bit 0 - transaction is completed. Bit 4 - ACK/NACK.h]h3Bit 0 - transaction is completed. Bit 4 - ACK/NACK.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hj7ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhhhK1hj"ubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1j$hjubah}(h]h ]h"]h$]h&]jrjsuh1jhhhK0hjubah}(h]h ]h"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]uh1jahj^ubjb)}(hhh](jg)}(hhh]h)}(hDATAxh]hDATAx}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjuubah}(h]h ]h"]h$]h&]uh1jfhjrubjg)}(hhh]h)}(h0xah]h0xa}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1jfhjrubjg)}(hhh]j )}(hhh]j%)}(hX/0x54 - 68 bytes data buffer regs. For write transaction address is specified in four first bytes (DATA1 - DATA4), data starting from DATA4. For read transactions address is sent in a separate transaction and specified in the four first bytes (DATA0 - DATA3). Data is read starting from DATA0.h]j)}(hhh]j)}(hX%0x54 - 68 bytes data buffer regs. For write transaction address is specified in four first bytes (DATA1 - DATA4), data starting from DATA4. For read transactions address is sent in a separate transaction and specified in the four first bytes (DATA0 - DATA3). Data is read starting from DATA0.h](j )}(h"0x54 - 68 bytes data buffer regs.h]h"0x54 - 68 bytes data buffer regs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhK7hjubj)}(hhh]h)}(hXFor write transaction address is specified in four first bytes (DATA1 - DATA4), data starting from DATA4. For read transactions address is sent in a separate transaction and specified in the four first bytes (DATA0 - DATA3). Data is read starting from DATA0.h]hXFor write transaction address is specified in four first bytes (DATA1 - DATA4), data starting from DATA4. For read transactions address is sent in a separate transaction and specified in the four first bytes (DATA0 - DATA3). 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