Msphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/i2c/busses/i2c-mlxcpldmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hDriver i2c-mlxcpldh]hDriver i2c-mlxcpld}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/i2c/busses/i2c-mlxcpld.rsthKubh paragraph)}(h.Author: Michael Shych h](hAuthor: Michael Shych <}(hhhhhNhNubh reference)}(hmichaelsh@mellanox.comh]hmichaelsh@mellanox.com}(hhhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:michaelsh@mellanox.comuh1hhhubh>}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hNThis is the Mellanox I2C controller logic, implemented in Lattice CPLD device.h]hNThis is the Mellanox I2C controller logic, implemented in Lattice CPLD device.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hDDevice supports: - Master mode. - One physical bus. - Polling mode. h](hterm)}(hDevice supports:h]hDevice supports:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubh definition)}(hhh]h bullet_list)}(hhh](h list_item)}(h Master mode.h]h)}(hjh]h Master mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hOne physical bus.h]h)}(hj+h]hOne physical bus.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj)ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hPolling mode. h]h)}(h Polling mode.h]h Polling mode.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj@ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]bullet-uh1j hhhK hjubah}(h]h ]h"]h$]h&]uh1jhhubeh}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubh)}(hThis controller is equipped within the next Mellanox systems: "msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", "msn2740", "msn2100".h]hThis controller is equipped within the next Mellanox systems: “msx6710”, “msx6720”, “msb7700”, “msn2700”, “msx1410”, “msn2410”, “msb7800”, “msn2740”, “msn2100”.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh]h)}(hzThe next transaction types are supported: - Receive Byte/Block. - Send Byte/Block. - Read Byte/Block. - Write Byte/Block. h](h)}(h)The next transaction types are supported:h]h)The next transaction types are supported:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(hhh]j )}(hhh](j)}(hReceive Byte/Block.h]h)}(hjh]hReceive Byte/Block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hSend Byte/Block.h]h)}(hjh]hSend Byte/Block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hRead Byte/Block.h]h)}(hjh]hRead Byte/Block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hWrite Byte/Block. h]h)}(hWrite Byte/Block.h]hWrite Byte/Block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j^j_uh1j hhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubh)}(h Registers:h]h Registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j(hj%ubj))}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j(hj%ubj))}(hhh]h}(h]h ]h"]h$]h&]colwidthKGuh1j(hj%ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hCPBLTYh]hCPBLTY}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjTubah}(h]h ]h"]h$]h&]uh1jRhjOubjS)}(hhh]h)}(h0x0h]h0x0}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubah}(h]h ]h"]h$]h&]uh1jRhjOubjS)}(hhh]j )}(hhh]j)}(hcapability reg. Bits [6:5] - transaction length. b01 - 72B is supported, 36B in other case. Bit 7 - SMBus block read support.h]h)}(hhh]h)}(h}capability reg. Bits [6:5] - transaction length. b01 - 72B is supported, 36B in other case. Bit 7 - SMBus block read support.h](h)}(hcapability reg.h]hcapability reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(hhh]h)}(hmBits [6:5] - transaction length. b01 - 72B is supported, 36B in other case. Bit 7 - SMBus block read support.h]hmBits [6:5] - transaction length. b01 - 72B is supported, 36B in other case. Bit 7 - SMBus block read support.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j^j_uh1j hhhKhjubah}(h]h ]h"]h$]h&]uh1jRhjOubeh}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh](jS)}(hhh]h)}(hCTRLh]hCTRL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jRhjubjS)}(hhh]h)}(h0x1h]h0x1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jRhjubjS)}(hhh]j )}(hhh]j)}(h(control reg. Resets all the registers.h]h)}(hhh]h)}(h&control reg. Resets all the registers.h](h)}(h control reg.h]h control reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubj)}(hhh]h)}(hResets all the registers.h]hResets all the registers.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j^j_uh1j hhhK hj ubah}(h]h ]h"]h$]h&]uh1jRhjubeh}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh](jS)}(hhh]h)}(hHALF_CYCh]hHALF_CYC}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjjubah}(h]h ]h"]h$]h&]uh1jRhjgubjS)}(hhh]h)}(h0x4h]h0x4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1jRhjgubjS)}(hhh]j )}(hhh]j)}(hTcycle reg. Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK units).h]h)}(hhh]h)}(hPcycle reg. Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK units).h](h)}(h cycle reg.h]h cycle reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubj)}(hhh]h)}(hEConfigure the width of I2C SCL half clock cycle (in 4 LPC_CLK units).h]hEConfigure the width of I2C SCL half clock cycle (in 4 LPC_CLK units).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j^j_uh1j hhhK"hjubah}(h]h ]h"]h$]h&]uh1jRhjgubeh}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh](jS)}(hhh]h)}(hI2C_HOLDh]hI2C_HOLD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jRhjubjS)}(hhh]h)}(h0x5h]h0x5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hj ubah}(h]h ]h"]h$]h&]uh1jRhjubjS)}(hhh]j )}(hhh]j)}(h\hold reg. OE (output enable) is delayed by value set to this register (in LPC_CLK units)h]h)}(hhh]h)}(hXhold reg. OE (output enable) is delayed by value set to this register (in LPC_CLK units)h](h)}(h hold reg.h]h hold reg.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hj0ubj)}(hhh]h)}(hNOE (output enable) is delayed by value set to this register (in LPC_CLK units)h]hNOE (output enable) is delayed by value set to this register (in LPC_CLK units)}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjBubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1hhhhK&hj-ubah}(h]h ]h"]h$]h&]uh1hhj)ubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]j^j_uh1j hhhK%hj#ubah}(h]h ]h"]h$]h&]uh1jRhjubeh}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh](jS)}(hhh]h)}(hCMDh]hCMD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jRhj}ubjS)}(hhh]h}(h]h ]h"]h$]h&]uh1jRhj}ubjS)}(hhh]h)}(h0x6 - command reg. Bit 0, 0 = write, 1 = read. Bits [7:1] - the 7bit Address of the I2C device. It should be written last as it triggers an I2C transaction.h]h0x6 - command reg. Bit 0, 0 = write, 1 = read. Bits [7:1] - the 7bit Address of the I2C device. It should be written last as it triggers an I2C transaction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jRhj}ubeh}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh](jS)}(hhh]h)}(hNUM_DATAh]hNUM_DATA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jRhjubjS)}(hhh]h)}(h0x7h]h0x7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jRhjubjS)}(hhh]j )}(hhh]j)}(hBdata size reg. Number of data bytes to write in read transactionh]h)}(hhh]h)}(h@data size reg. Number of data bytes to write in read transactionh](h)}(hdata size reg.h]hdata size reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubj)}(hhh]h)}(h1Number of data bytes to write in read transactionh]h1Number of data bytes to write in read transaction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j^j_uh1j hhhK,hjubah}(h]h ]h"]h$]h&]uh1jRhjubeh}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh](jS)}(hhh]h)}(hNUM_ADDRh]hNUM_ADDR}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjKubah}(h]h ]h"]h$]h&]uh1jRhjHubjS)}(hhh]h)}(h0x8h]h0x8}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjbubah}(h]h ]h"]h$]h&]uh1jRhjHubjS)}(hhh]j )}(hhh]j)}(hDaddress reg. Number of address bytes to write in read transaction.h]h)}(hhh]h)}(hBaddress reg. Number of address bytes to write in read transaction.h](h)}(h address reg.h]h address reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubj)}(hhh]h)}(h5Number of address bytes to write in read transaction.h]h5Number of address bytes to write in read transaction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]j^j_uh1j hhhK.hjyubah}(h]h ]h"]h$]h&]uh1jRhjHubeh}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh](jS)}(hhh]h)}(hSTATUSh]hSTATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jRhjubjS)}(hhh]h)}(h0x9h]h0x9}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jRhjubjS)}(hhh]j )}(hhh]j)}(hCstatus reg. Bit 0 - transaction is completed. Bit 4 - ACK/NACK.h]h)}(hhh]h)}(h?status reg. Bit 0 - transaction is completed. Bit 4 - ACK/NACK.h](h)}(h status reg.h]h status reg.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubj)}(hhh]h)}(h3Bit 0 - transaction is completed. Bit 4 - ACK/NACK.h]h3Bit 0 - transaction is completed. Bit 4 - ACK/NACK.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j^j_uh1j hhhK0hjubah}(h]h ]h"]h$]h&]uh1jRhjubeh}(h]h ]h"]h$]h&]uh1jMhjJubjN)}(hhh](jS)}(hhh]h)}(hDATAxh]hDATAx}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjaubah}(h]h ]h"]h$]h&]uh1jRhj^ubjS)}(hhh]h)}(h0xah]h0xa}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjxubah}(h]h ]h"]h$]h&]uh1jRhj^ubjS)}(hhh]j )}(hhh]j)}(hX/0x54 - 68 bytes data buffer regs. For write transaction address is specified in four first bytes (DATA1 - DATA4), data starting from DATA4. For read transactions address is sent in a separate transaction and specified in the four first bytes (DATA0 - DATA3). Data is read starting from DATA0.h]h)}(hhh]h)}(hX%0x54 - 68 bytes data buffer regs. For write transaction address is specified in four first bytes (DATA1 - DATA4), data starting from DATA4. For read transactions address is sent in a separate transaction and specified in the four first bytes (DATA0 - DATA3). Data is read starting from DATA0.h](h)}(h"0x54 - 68 bytes data buffer regs.h]h"0x54 - 68 bytes data buffer regs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubj)}(hhh]h)}(hXFor write transaction address is specified in four first bytes (DATA1 - DATA4), data starting from DATA4. For read transactions address is sent in a separate transaction and specified in the four first bytes (DATA0 - DATA3). Data is read starting from DATA0.h]hXFor write transaction address is specified in four first bytes (DATA1 - DATA4), data starting from DATA4. For read transactions address is sent in a separate transaction and specified in the four first bytes (DATA0 - DATA3). Data is read starting from DATA0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK7hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j^j_uh1j hhhK3hjubah}(h]h ]h"]h$]h&]uh1jRhj^ubeh}(h]h ]h"]h$]h&]uh1jMhjJubeh}(h]h ]h"]h$]h&]uh1jHhj%ubeh}(h]h ]h"]h$]h&]colsKuh1j#hj ubah}(h]h ]h"]h$]h&]uh1jhhhhhNhNubeh}(h]driver-i2c-mlxcpldah ]h"]driver i2c-mlxcpldah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjRfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj&error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}jjs nametypes}jsh}jhs footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.