sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget'/translations/zh_CN/i2c/busses/i2c-i801modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/zh_TW/i2c/busses/i2c-i801modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/it_IT/i2c/busses/i2c-i801modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/ja_JP/i2c/busses/i2c-i801modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/ko_KR/i2c/busses/i2c-i801modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/sp_SP/i2c/busses/i2c-i801modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hKernel driver i2c-i801h]hKernel driver i2c-i801}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhA/var/lib/git/docbuild/linux/Documentation/i2c/busses/i2c-i801.rsthKubhdefinition_list)}(hhh]hdefinition_list_item)}(hX-Supported adapters: * Intel 82801AA and 82801AB (ICH and ICH0 - part of the '810' and '810E' chipsets) * Intel 82801BA (ICH2 - part of the '815E' chipset) * Intel 82801CA/CAM (ICH3) * Intel 82801DB (ICH4) (HW PEC supported) * Intel 82801EB/ER (ICH5) (HW PEC supported) * Intel 6300ESB * Intel 82801FB/FR/FW/FRW (ICH6) * Intel 82801G (ICH7) * Intel 631xESB/632xESB (ESB2) * Intel 82801H (ICH8) * Intel 82801I (ICH9) * Intel EP80579 (Tolapai) * Intel 82801JI (ICH10) * Intel 5/3400 Series (PCH) * Intel 6 Series (PCH) * Intel Patsburg (PCH) * Intel DH89xxCC (PCH) * Intel Panther Point (PCH) * Intel Lynx Point (PCH) * Intel Avoton (SOC) * Intel Wellsburg (PCH) * Intel Coleto Creek (PCH) * Intel Wildcat Point (PCH) * Intel BayTrail (SOC) * Intel Braswell (SOC) * Intel Sunrise Point (PCH) * Intel Kaby Lake (PCH) * Intel DNV (SOC) * Intel Broxton (SOC) * Intel Lewisburg (PCH) * Intel Gemini Lake (SOC) * Intel Cannon Lake (PCH) * Intel Cedar Fork (PCH) * Intel Ice Lake (PCH) * Intel Comet Lake (PCH) * Intel Elkhart Lake (PCH) * Intel Tiger Lake (PCH) * Intel Jasper Lake (SOC) * Intel Emmitsburg (PCH) * Intel Alder Lake (PCH) * Intel Raptor Lake (PCH) * Intel Meteor Lake (SOC and PCH) * Intel Birch Stream (SOC) * Intel Arrow Lake (SOC) * Intel Panther Lake (SOC) Datasheets: Publicly available at the Intel website h](hterm)}(hSupported adapters:h]hSupported adapters:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hhubh definition)}(hhh](h bullet_list)}(hhh](h list_item)}(hPIntel 82801AA and 82801AB (ICH and ICH0 - part of the '810' and '810E' chipsets)h]h paragraph)}(hPIntel 82801AA and 82801AB (ICH and ICH0 - part of the '810' and '810E' chipsets)h]hXIntel 82801AA and 82801AB (ICH and ICH0 - part of the ‘810’ and ‘810E’ chipsets)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(h1Intel 82801BA (ICH2 - part of the '815E' chipset)h]h)}(hhh]h5Intel 82801BA (ICH2 - part of the ‘815E’ chipset)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 82801CA/CAM (ICH3)h]h)}(hjh]hIntel 82801CA/CAM (ICH3)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(h'Intel 82801DB (ICH4) (HW PEC supported)h]h)}(hj(h]h'Intel 82801DB (ICH4) (HW PEC supported)}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj&ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(h*Intel 82801EB/ER (ICH5) (HW PEC supported)h]h)}(hj?h]h*Intel 82801EB/ER (ICH5) (HW PEC supported)}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj=ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(h Intel 6300ESBh]h)}(hjVh]h Intel 6300ESB}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjTubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 82801FB/FR/FW/FRW (ICH6)h]h)}(hjmh]hIntel 82801FB/FR/FW/FRW (ICH6)}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 82801G (ICH7)h]h)}(hjh]hIntel 82801G (ICH7)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 631xESB/632xESB (ESB2)h]h)}(hjh]hIntel 631xESB/632xESB (ESB2)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 82801H (ICH8)h]h)}(hjh]hIntel 82801H (ICH8)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 82801I (ICH9)h]h)}(hjh]hIntel 82801I (ICH9)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel EP80579 (Tolapai)h]h)}(hjh]hIntel EP80579 (Tolapai)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 82801JI (ICH10)h]h)}(hjh]hIntel 82801JI (ICH10)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 5/3400 Series (PCH)h]h)}(hjh]hIntel 5/3400 Series (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel 6 Series (PCH)h]h)}(hj%h]hIntel 6 Series (PCH)}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj#ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Patsburg (PCH)h]h)}(hj<h]hIntel Patsburg (PCH)}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj:ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel DH89xxCC (PCH)h]h)}(hjSh]hIntel DH89xxCC (PCH)}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjQubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Panther Point (PCH)h]h)}(hjjh]hIntel Panther Point (PCH)}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Lynx Point (PCH)h]h)}(hjh]hIntel Lynx Point (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Avoton (SOC)h]h)}(hjh]hIntel Avoton (SOC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Wellsburg (PCH)h]h)}(hjh]hIntel Wellsburg (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Coleto Creek (PCH)h]h)}(hjh]hIntel Coleto Creek (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Wildcat Point (PCH)h]h)}(hjh]hIntel Wildcat Point (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel BayTrail (SOC)h]h)}(hjh]hIntel BayTrail (SOC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Braswell (SOC)h]h)}(hj h]hIntel Braswell (SOC)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Sunrise Point (PCH)h]h)}(hj"h]hIntel Sunrise Point (PCH)}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hj ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Kaby Lake (PCH)h]h)}(hj9h]hIntel Kaby Lake (PCH)}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hj7ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel DNV (SOC)h]h)}(hjPh]hIntel DNV (SOC)}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjNubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Broxton (SOC)h]h)}(hjgh]hIntel Broxton (SOC)}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjeubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Lewisburg (PCH)h]h)}(hj~h]hIntel Lewisburg (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hj|ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Gemini Lake (SOC)h]h)}(hjh]hIntel Gemini Lake (SOC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Cannon Lake (PCH)h]h)}(hjh]hIntel Cannon Lake (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Cedar Fork (PCH)h]h)}(hjh]hIntel Cedar Fork (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Ice Lake (PCH)h]h)}(hjh]hIntel Ice Lake (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Comet Lake (PCH)h]h)}(hjh]hIntel Comet Lake (PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Elkhart Lake (PCH)h]h)}(hjh]hIntel Elkhart Lake (PCH)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Tiger Lake (PCH)h]h)}(hjh]hIntel Tiger Lake (PCH)}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Jasper Lake (SOC)h]h)}(hj6h]hIntel Jasper Lake (SOC)}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hj4ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Emmitsburg (PCH)h]h)}(hjMh]hIntel Emmitsburg (PCH)}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjKubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Alder Lake (PCH)h]h)}(hjdh]hIntel Alder Lake (PCH)}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjbubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Raptor Lake (PCH)h]h)}(hj{h]hIntel Raptor Lake (PCH)}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjyubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Meteor Lake (SOC and PCH)h]h)}(hjh]hIntel Meteor Lake (SOC and PCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Birch Stream (SOC)h]h)}(hjh]hIntel Birch Stream (SOC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Arrow Lake (SOC)h]h)}(hjh]hIntel Arrow Lake (SOC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hIntel Panther Lake (SOC) h]h)}(hIntel Panther Lake (SOC)h]hIntel Panther Lake (SOC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]bullet*uh1hhhhKhhubh block_quote)}(h4Datasheets: Publicly available at the Intel website h]h)}(h3Datasheets: Publicly available at the Intel websiteh]h3Datasheets: Publicly available at the Intel website}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jhhhK6hhubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhK6hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hOn Intel Patsburg and later chipsets, both the normal host SMBus controller and the additional 'Integrated Device Function' controllers are supported.h]hOn Intel Patsburg and later chipsets, both the normal host SMBus controller and the additional ‘Integrated Device Function’ controllers are supported.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hhhhubh)}(hhh]h)}(hTAuthors: - Mark Studebaker - Jean Delvare h](h)}(hAuthors:h]hAuthors:}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hj2ubh)}(hhh]h)}(hhh](h)}(h%Mark Studebaker h]h)}(hjLh](hMark Studebaker <}(hjNhhhNhNubh reference)}(hmdsxyz123@yahoo.comh]hmdsxyz123@yahoo.com}(hjWhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:mdsxyz123@yahoo.comuh1jUhjNubh>}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK h]h)}(hJean Delvare h](hJean Delvare <}(hj{hhhNhNubjV)}(hjdelvare@suse.deh]hjdelvare@suse.de}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:jdelvare@suse.deuh1jUhj{ubh>}(hj{hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK=hjwubah}(h]h ]h"]h$]h&]uh1hhjGubeh}(h]h ]h"]h$]h&]j-uh1hhhhKhj/ubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubh)}(hhh](h)}(hModule Parametersh]hModule Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKAubh)}(hhh]h)}(hdisable_features (bit vector) h]h)}(hdisable_features (bit vector)h]hdisable_features (bit vector)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubah}(h]h ]h"]h$]h&]jjuh1hhhhKChjhhubh)}(hDisable selected features normally supported by the device. This makes it possible to work around possible driver or hardware bugs if the feature in question doesn't work as intended for whatever reason. Bit values:h]hDisable selected features normally supported by the device. This makes it possible to work around possible driver or hardware bugs if the feature in question doesn’t work as intended for whatever reason. Bit values:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKEhjhhubj)}(hX==== ========================================= 0x01 disable SMBus PEC 0x02 disable the block buffer 0x08 disable the I2C block read functionality 0x10 don't use interrupts 0x20 disable SMBus Host Notify ==== ========================================= h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthK)uh1j hjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h0x01h]h0x01}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhj,ubah}(h]h ]h"]h$]h&]uh1j*hj'ubj+)}(hhh]h)}(hdisable SMBus PECh]hdisable SMBus PEC}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjCubah}(h]h ]h"]h$]h&]uh1j*hj'ubeh}(h]h ]h"]h$]h&]uh1j%hj"ubj&)}(hhh](j+)}(hhh]h)}(h0x02h]h0x02}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjcubah}(h]h ]h"]h$]h&]uh1j*hj`ubj+)}(hhh]h)}(hdisable the block bufferh]hdisable the block buffer}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjzubah}(h]h ]h"]h$]h&]uh1j*hj`ubeh}(h]h ]h"]h$]h&]uh1j%hj"ubj&)}(hhh](j+)}(hhh]h)}(h0x08h]h0x08}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjubah}(h]h ]h"]h$]h&]uh1j*hjubj+)}(hhh]h)}(h(disable the I2C block read functionalityh]h(disable the I2C block read functionality}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjubah}(h]h ]h"]h$]h&]uh1j*hjubeh}(h]h ]h"]h$]h&]uh1j%hj"ubj&)}(hhh](j+)}(hhh]h)}(h0x10h]h0x10}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjubah}(h]h ]h"]h$]h&]uh1j*hjubj+)}(hhh]h)}(hdon't use interruptsh]hdon’t use interrupts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjubah}(h]h ]h"]h$]h&]uh1j*hjubeh}(h]h ]h"]h$]h&]uh1j%hj"ubj&)}(hhh](j+)}(hhh]h)}(h0x20h]h0x20}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1j*hjubj+)}(hhh]h)}(hdisable SMBus Host Notifyh]hdisable SMBus Host Notify}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1j*hjubeh}(h]h ]h"]h$]h&]uh1j%hj"ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhKIhjhhubeh}(h]module-parametersah ]h"]module parametersah$]h&]uh1hhhhhhhhKAubh)}(hhh](h)}(h Descriptionh]h Description}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hhhhhKSubh)}(hXThe ICH (properly known as the 82801AA), ICH0 (82801AB), ICH2 (82801BA), ICH3 (82801CA/CAM) and later devices (PCH) are Intel chips that are a part of Intel's '810' chipset for Celeron-based PCs, '810E' chipset for Pentium-based PCs, '815E' chipset, and others.h]hXThe ICH (properly known as the 82801AA), ICH0 (82801AB), ICH2 (82801BA), ICH3 (82801CA/CAM) and later devices (PCH) are Intel chips that are a part of Intel’s ‘810’ chipset for Celeron-based PCs, ‘810E’ chipset for Pentium-based PCs, ‘815E’ chipset, and others.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhj]hhubh)}(hThe ICH chips contain at least SEVEN separate PCI functions in TWO logical PCI devices. An output of lspci will show something similar to the following::h]hThe ICH chips contain at least SEVEN separate PCI functions in TWO logical PCI devices. An output of lspci will show something similar to the following:}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhj]hhubh literal_block)}(hXd00:1e.0 PCI bridge: Intel Corporation: Unknown device 2418 (rev 01) 00:1f.0 ISA bridge: Intel Corporation: Unknown device 2410 (rev 01) 00:1f.1 IDE interface: Intel Corporation: Unknown device 2411 (rev 01) 00:1f.2 USB Controller: Intel Corporation: Unknown device 2412 (rev 01) 00:1f.3 Unknown class [0c05]: Intel Corporation: Unknown device 2413 (rev 01)h]hXd00:1e.0 PCI bridge: Intel Corporation: Unknown device 2418 (rev 01) 00:1f.0 ISA bridge: Intel Corporation: Unknown device 2410 (rev 01) 00:1f.1 IDE interface: Intel Corporation: Unknown device 2411 (rev 01) 00:1f.2 USB Controller: Intel Corporation: Unknown device 2412 (rev 01) 00:1f.3 Unknown class [0c05]: Intel Corporation: Unknown device 2413 (rev 01)}hjsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jhhhK^hj]hhubh)}(hWThe SMBus controller is function 3 in device 1f. Class 0c05 is SMBus Serial Controller.h]hWThe SMBus controller is function 3 in device 1f. Class 0c05 is SMBus Serial Controller.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhj]hhubh)}(hXThe ICH chips are quite similar to Intel's PIIX4 chip, at least in the SMBus controller.h]hZThe ICH chips are quite similar to Intel’s PIIX4 chip, at least in the SMBus controller.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghj]hhubeh}(h] descriptionah ]h"] descriptionah$]h&]uh1hhhhhhhhKSubh)}(hhh](h)}(hProcess Call Supporth]hProcess Call Support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKlubh)}(hFBlock process call is supported on the 82801EB (ICH5) and later chips.h]hFBlock process call is supported on the 82801EB (ICH5) and later chips.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjhhubeh}(h]process-call-supportah ]h"]process call supportah$]h&]uh1hhhhhhhhKlubh)}(hhh](h)}(hI2C Block Read Supporth]hI2C Block Read Support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKrubh)}(hBI2C block read is supported on the 82801EB (ICH5) and later chips.h]hBI2C block read is supported on the 82801EB (ICH5) and later chips.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjhhubeh}(h]i2c-block-read-supportah ]h"]i2c block read supportah$]h&]uh1hhhhhhhhKrubh)}(hhh](h)}(hSMBus 2.0 Supporth]hSMBus 2.0 Support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKxubh)}(hFThe 82801DB (ICH4) and later chips support several SMBus 2.0 features.h]hFThe 82801DB (ICH4) and later chips support several SMBus 2.0 features.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhjhhubeh}(h]smbus-2-0-supportah ]h"]smbus 2.0 supportah$]h&]uh1hhhhhhhhKxubh)}(hhh](h)}(hInterrupt Supporth]hInterrupt Support}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhK~ubh)}(hIPCI interrupt support is supported on the 82801EB (ICH5) and later chips.h]hIPCI interrupt support is supported on the 82801EB (ICH5) and later chips.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5hhubeh}(h]interrupt-supportah ]h"]interrupt supportah$]h&]uh1hhhhhhhhK~ubh)}(hhh](h)}(hHidden ICH SMBush]hHidden ICH SMBus}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hhhhhKubh)}(hX^If your system has an Intel ICH south bridge, but you do NOT see the SMBus device at 00:1f.3 in lspci, and you can't figure out any way in the BIOS to enable it, it means it has been hidden by the BIOS code. Asus is well known for first doing this on their P4B motherboard, and many other boards after that. Some vendor machines are affected as well.h]hX`If your system has an Intel ICH south bridge, but you do NOT see the SMBus device at 00:1f.3 in lspci, and you can’t figure out any way in the BIOS to enable it, it means it has been hidden by the BIOS code. Asus is well known for first doing this on their P4B motherboard, and many other boards after that. Some vendor machines are affected as well.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubh)}(hXThe first thing to try is the "i2c-scmi" ACPI driver. It could be that the SMBus was hidden on purpose because it'll be driven by ACPI. If the i2c-scmi driver works for you, just forget about the i2c-i801 driver and don't try to unhide the ICH SMBus. Even if i2c-scmi doesn't work, you better make sure that the SMBus isn't used by the ACPI code. Try loading the "fan" and "thermal" drivers, and check in /sys/class/thermal. If you find a thermal zone with type "acpitz", it's likely that the ACPI is accessing the SMBus and it's safer not to unhide it. Only once you are certain that ACPI isn't using the SMBus, you can attempt to unhide it.h]hXThe first thing to try is the “i2c-scmi” ACPI driver. It could be that the SMBus was hidden on purpose because it’ll be driven by ACPI. If the i2c-scmi driver works for you, just forget about the i2c-i801 driver and don’t try to unhide the ICH SMBus. Even if i2c-scmi doesn’t work, you better make sure that the SMBus isn’t used by the ACPI code. Try loading the “fan” and “thermal” drivers, and check in /sys/class/thermal. If you find a thermal zone with type “acpitz”, it’s likely that the ACPI is accessing the SMBus and it’s safer not to unhide it. Only once you are certain that ACPI isn’t using the SMBus, you can attempt to unhide it.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubh)}(hXIn order to unhide the SMBus, we need to change the value of a PCI register before the kernel enumerates the PCI devices. This is done in drivers/pci/quirks.c, where all affected boards must be listed (see function asus_hides_smbus_hostbridge.) If the SMBus device is missing, and you think there's something interesting on the SMBus (e.g. a hardware monitoring chip), you need to add your board to the list.h]hXIn order to unhide the SMBus, we need to change the value of a PCI register before the kernel enumerates the PCI devices. This is done in drivers/pci/quirks.c, where all affected boards must be listed (see function asus_hides_smbus_hostbridge.) If the SMBus device is missing, and you think there’s something interesting on the SMBus (e.g. a hardware monitoring chip), you need to add your board to the list.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubh)}(hThe motherboard is identified using the subvendor and subdevice IDs of the host bridge PCI device. Get yours with ``lspci -n -v -s 00:00.0``::h](hrThe motherboard is identified using the subvendor and subdevice IDs of the host bridge PCI device. Get yours with }(hjhhhNhNubhliteral)}(h``lspci -n -v -s 00:00.0``h]hlspci -n -v -s 00:00.0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubj)}(hX00:00.0 Class 0600: 8086:2570 (rev 02) Subsystem: 1043:80f2 Flags: bus master, fast devsel, latency 0 Memory at fc000000 (32-bit, prefetchable) [size=32M] Capabilities: [e4] #09 [2106] Capabilities: [a0] AGP version 3.0h]hX00:00.0 Class 0600: 8086:2570 (rev 02) Subsystem: 1043:80f2 Flags: bus master, fast devsel, latency 0 Memory at fc000000 (32-bit, prefetchable) [size=32M] Capabilities: [e4] #09 [2106] Capabilities: [a0] AGP version 3.0}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhj\hhubh)}(hXHere the host bridge ID is 2570 (82865G/PE/P), the subvendor ID is 1043 (Asus) and the subdevice ID is 80f2 (P4P800-X). You can find the symbolic names for the bridge ID and the subvendor ID in include/linux/pci_ids.h, and then add a case for your subdevice ID at the right place in drivers/pci/quirks.c. Then please give it very good testing, to make sure that the unhidden SMBus doesn't conflict with e.g. ACPI.h]hXHere the host bridge ID is 2570 (82865G/PE/P), the subvendor ID is 1043 (Asus) and the subdevice ID is 80f2 (P4P800-X). You can find the symbolic names for the bridge ID and the subvendor ID in include/linux/pci_ids.h, and then add a case for your subdevice ID at the right place in drivers/pci/quirks.c. Then please give it very good testing, to make sure that the unhidden SMBus doesn’t conflict with e.g. ACPI.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubh)}(hIf it works, proves useful (i.e. there are usable chips on the SMBus) and seems safe, please submit a patch for inclusion into the kernel.h]hIf it works, proves useful (i.e. there are usable chips on the SMBus) and seems safe, please submit a patch for inclusion into the kernel.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubh)}(hXANote: There's a useful script in lm_sensors 2.10.2 and later, named unhide_ICH_SMBus (in prog/hotplug), which uses the fakephp driver to temporarily unhide the SMBus without having to patch and recompile your kernel. It's very convenient if you just want to check if there's anything interesting on your hidden ICH SMBus.h]hXGNote: There’s a useful script in lm_sensors 2.10.2 and later, named unhide_ICH_SMBus (in prog/hotplug), which uses the fakephp driver to temporarily unhide the SMBus without having to patch and recompile your kernel. It’s very convenient if you just want to check if there’s anything interesting on your hidden ICH SMBus.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubh transition)}(hL----------------------------------------------------------------------------h]h}(h]h ]h"]h$]h&]uh1jhhhKhj\hhubh)}(hzThe lm_sensors project gratefully acknowledges the support of Texas Instruments in the initial development of this driver.h]hzThe lm_sensors project gratefully acknowledges the support of Texas Instruments in the initial development of this driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubh)}(hThe lm_sensors project gratefully acknowledges the support of Intel in the development of SMBus 2.0 / ICH4 features of this driver.h]hThe lm_sensors project gratefully acknowledges the support of Intel in the development of SMBus 2.0 / ICH4 features of this driver.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubeh}(h]hidden-ich-smbusah ]h"]hidden ich smbusah$]h&]uh1hhhhhhhhKubeh}(h]kernel-driver-i2c-i801ah ]h"]kernel driver i2c-i801ah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksj*footnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjK error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j& j# jZjWjjjjj jj2j/jYjVj j u nametypes}(j& jZjjj j2jYj uh}(j# hjWjjj]jjjjj/jjVj5j j\u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.