€•V+      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ$/translations/zh_CN/hwmon/sbtsi_temp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/zh_TW/hwmon/sbtsi_temp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/it_IT/hwmon/sbtsi_temp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/ja_JP/hwmon/sbtsi_temp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/ko_KR/hwmon/sbtsi_temp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/sp_SP/hwmon/sbtsi_temp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ)SPDX-License-Identifier: GPL-2.0-or-later”h]”hŒ)SPDX-License-Identifier: GPL-2.0-or-later”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1h¡hhhžhhŸŒ>/var/lib/git/docbuild/linux/Documentation/hwmon/sbtsi_temp.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒKernel driver sbtsi_temp”h]”hŒKernel driver sbtsi_temp”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ	paragraph”“”)”}”(hŒSupported hardware:”h]”hŒSupported hardware:”…””}”(hhËhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhŒblock_quote”“”)”}”(hX¸  * Sideband interface (SBI) Temperature Sensor Interface (SB-TSI)
  compliant AMD SoC temperature device.

  Prefix: 'sbtsi_temp'

  Addresses scanned: This driver doesn't support address scanning.

  To instantiate this driver on an AMD CPU with SB-TSI
  support, the i2c bus number would be the bus connected from the board
  management controller (BMC) to the CPU. The i2c address is specified in
  Section 6.3.1 of the SoC register reference: The SB-TSI address is normally
  98h for socket 0 and 90h for socket 1, but it could vary based on hardware
  address select pins.

  Datasheet: The SB-TSI interface and protocol is available as part of
             the open source SoC register reference at:

             https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf

             The Advanced Platform Management Link (APML) Specification is
             available at:

             http://developer.amd.com/wordpress/media/2012/10/41918.pdf
”h]”hŒbullet_list”“”)”}”(hhh]”hŒ	list_item”“”)”}”(hX˜  Sideband interface (SBI) Temperature Sensor Interface (SB-TSI)
compliant AMD SoC temperature device.

Prefix: 'sbtsi_temp'

Addresses scanned: This driver doesn't support address scanning.

To instantiate this driver on an AMD CPU with SB-TSI
support, the i2c bus number would be the bus connected from the board
management controller (BMC) to the CPU. The i2c address is specified in
Section 6.3.1 of the SoC register reference: The SB-TSI address is normally
98h for socket 0 and 90h for socket 1, but it could vary based on hardware
address select pins.

Datasheet: The SB-TSI interface and protocol is available as part of
           the open source SoC register reference at:

           https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf

           The Advanced Platform Management Link (APML) Specification is
           available at:

           http://developer.amd.com/wordpress/media/2012/10/41918.pdf
”h]”(hÊ)”}”(hŒdSideband interface (SBI) Temperature Sensor Interface (SB-TSI)
compliant AMD SoC temperature device.”h]”hŒdSideband interface (SBI) Temperature Sensor Interface (SB-TSI)
compliant AMD SoC temperature device.”…””}”(hhêhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhhæubhÊ)”}”(hŒPrefix: 'sbtsi_temp'”h]”hŒPrefix: â€˜sbtsi_tempâ€™”…””}”(hhøhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhhæubhÊ)”}”(hŒ@Addresses scanned: This driver doesn't support address scanning.”h]”hŒBAddresses scanned: This driver doesnâ€™t support address scanning.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhhæubhÊ)”}”(hXn  To instantiate this driver on an AMD CPU with SB-TSI
support, the i2c bus number would be the bus connected from the board
management controller (BMC) to the CPU. The i2c address is specified in
Section 6.3.1 of the SoC register reference: The SB-TSI address is normally
98h for socket 0 and 90h for socket 1, but it could vary based on hardware
address select pins.”h]”hXn  To instantiate this driver on an AMD CPU with SB-TSI
support, the i2c bus number would be the bus connected from the board
management controller (BMC) to the CPU. The i2c address is specified in
Section 6.3.1 of the SoC register reference: The SB-TSI address is normally
98h for socket 0 and 90h for socket 1, but it could vary based on hardware
address select pins.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhhæubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hX3  Datasheet: The SB-TSI interface and protocol is available as part of
the open source SoC register reference at:

https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf

The Advanced Platform Management Link (APML) Specification is
available at:

http://developer.amd.com/wordpress/media/2012/10/41918.pdf
”h]”(hŒterm”“”)”}”(hŒDDatasheet: The SB-TSI interface and protocol is available as part of”h]”hŒDDatasheet: The SB-TSI interface and protocol is available as part of”…””}”(hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h Khj)  ubhŒ
definition”“”)”}”(hhh]”(hÊ)”}”(hŒ*the open source SoC register reference at:”h]”hŒ*the open source SoC register reference at:”…””}”(hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj?  ubhÊ)”}”(hŒ8https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf”h]”hŒ	reference”“”)”}”(hjR  h]”hŒ8https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf”…””}”(hjV  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jR  uh1jT  hjP  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj?  ubhÊ)”}”(hŒKThe Advanced Platform Management Link (APML) Specification is
available at:”h]”hŒKThe Advanced Platform Management Link (APML) Specification is
available at:”…””}”(hjj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj?  ubhÊ)”}”(hŒ:http://developer.amd.com/wordpress/media/2012/10/41918.pdf”h]”jU  )”}”(hjz  h]”hŒ:http://developer.amd.com/wordpress/media/2012/10/41918.pdf”…””}”(hj|  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jz  uh1jT  hjx  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj?  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j=  hj)  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h Khj$  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j"  hhæubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähháubah}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1hßhŸh³h KhhÛubah}”(h]”h ]”h"]”h$]”h&]”uh1hÙhŸh³h Khh¶hžhubhÊ)”}”(hŒ!Author: Kun Yi <kunyi@google.com>”h]”(hŒAuthor: Kun Yi <”…””}”(hj¶  hžhhŸNh NubjU  )”}”(hŒkunyi@google.com”h]”hŒkunyi@google.com”…””}”(hj¾  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:kunyi@google.com”uh1jT  hj¶  ubhŒ>”…””}”(hj¶  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒDescription”h]”hŒDescription”…””}”(hjÛ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjØ  hžhhŸh³h K#ubhÊ)”}”(hX˜  The SBI temperature sensor interface (SB-TSI) is an emulation of the software
and physical interface of a typical 8-pin remote temperature sensor (RTS) on
AMD SoCs. It implements one temperature sensor with readings and limit
registers encode the temperature in increments of 0.125 from 0 to 255.875.
Limits can be set through the writable thresholds, and if reached will trigger
corresponding alert signals.”h]”hX˜  The SBI temperature sensor interface (SB-TSI) is an emulation of the software
and physical interface of a typical 8-pin remote temperature sensor (RTS) on
AMD SoCs. It implements one temperature sensor with readings and limit
registers encode the temperature in increments of 0.125 from 0 to 255.875.
Limits can be set through the writable thresholds, and if reached will trigger
corresponding alert signals.”…””}”(hjé  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K%hjØ  hžhubeh}”(h]”Œdescription”ah ]”h"]”Œdescription”ah$]”h&]”uh1h´hh¶hžhhŸh³h K#ubeh}”(h]”Œkernel-driver-sbtsi-temp”ah ]”h"]”Œkernel driver sbtsi_temp”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
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id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.