Isphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/hwmon/sbrmimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/hwmon/sbrmimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/hwmon/sbrmimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/hwmon/sbrmimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/hwmon/sbrmimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/hwmon/sbrmimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h)SPDX-License-Identifier: GPL-2.0-or-laterh]h)SPDX-License-Identifier: GPL-2.0-or-later}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh9/var/lib/git/docbuild/linux/Documentation/hwmon/sbrmi.rsthKubhsection)}(hhh](htitle)}(hKernel driver sbrmih]hKernel driver sbrmi}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hSupported hardware:h]hSupported hardware:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hXX* Sideband Remote Management Interface (SB-RMI) compliant AMD SoC device connected to the BMC via the APML. Prefix: 'sbrmi' Addresses scanned: This driver doesn't support address scanning. To instantiate this driver on an AMD CPU with SB-RMI support, the i2c bus number would be the bus connected from the board management controller (BMC) to the CPU. The SMBus address is really 7 bits. Some vendors and the SMBus specification show the address as 8 bits, left justified with the R/W bit as a write (0) making bit 0. Some vendors use only the 7 bits to describe the address. As mentioned in AMD's APML specification, The SB-RMI address is normally 78h(0111 100W) or 3Ch(011 1100) for socket 0 and 70h(0111 000W) or 38h(011 1000) for socket 1, but it could vary based on hardware address select pins. Datasheet: The SB-RMI interface and protocol along with the Advanced Platform Management Link (APML) Specification is available as part of the open source SoC register reference at: https://www.amd.com/en/support/tech-docs?keyword=55898 h]h bullet_list)}(hhh]h list_item)}(hX2Sideband Remote Management Interface (SB-RMI) compliant AMD SoC device connected to the BMC via the APML. Prefix: 'sbrmi' Addresses scanned: This driver doesn't support address scanning. To instantiate this driver on an AMD CPU with SB-RMI support, the i2c bus number would be the bus connected from the board management controller (BMC) to the CPU. The SMBus address is really 7 bits. Some vendors and the SMBus specification show the address as 8 bits, left justified with the R/W bit as a write (0) making bit 0. Some vendors use only the 7 bits to describe the address. As mentioned in AMD's APML specification, The SB-RMI address is normally 78h(0111 100W) or 3Ch(011 1100) for socket 0 and 70h(0111 000W) or 38h(011 1000) for socket 1, but it could vary based on hardware address select pins. Datasheet: The SB-RMI interface and protocol along with the Advanced Platform Management Link (APML) Specification is available as part of the open source SoC register reference at: https://www.amd.com/en/support/tech-docs?keyword=55898 h](h)}(hiSideband Remote Management Interface (SB-RMI) compliant AMD SoC device connected to the BMC via the APML.h]hiSideband Remote Management Interface (SB-RMI) compliant AMD SoC device connected to the BMC via the APML.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubh)}(hPrefix: 'sbrmi'h]hPrefix: ‘sbrmi’}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubh)}(h@Addresses scanned: This driver doesn't support address scanning.h]hBAddresses scanned: This driver doesn’t support address scanning.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubh)}(hXcTo instantiate this driver on an AMD CPU with SB-RMI support, the i2c bus number would be the bus connected from the board management controller (BMC) to the CPU. The SMBus address is really 7 bits. Some vendors and the SMBus specification show the address as 8 bits, left justified with the R/W bit as a write (0) making bit 0. Some vendors use only the 7 bits to describe the address. As mentioned in AMD's APML specification, The SB-RMI address is normally 78h(0111 100W) or 3Ch(011 1100) for socket 0 and 70h(0111 000W) or 38h(011 1000) for socket 1, but it could vary based on hardware address select pins.h]hXeTo instantiate this driver on an AMD CPU with SB-RMI support, the i2c bus number would be the bus connected from the board management controller (BMC) to the CPU. The SMBus address is really 7 bits. Some vendors and the SMBus specification show the address as 8 bits, left justified with the R/W bit as a write (0) making bit 0. Some vendors use only the 7 bits to describe the address. As mentioned in AMD’s APML specification, The SB-RMI address is normally 78h(0111 100W) or 3Ch(011 1100) for socket 0 and 70h(0111 000W) or 38h(011 1000) for socket 1, but it could vary based on hardware address select pins.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hDatasheet: The SB-RMI interface and protocol along with the Advanced Platform Management Link (APML) Specification is available as part of the open source SoC register reference at: https://www.amd.com/en/support/tech-docs?keyword=55898 h](hterm)}(hDDatasheet: The SB-RMI interface and protocol along with the Advancedh]hDDatasheet: The SB-RMI interface and protocol along with the Advanced}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j-hhhKhj)ubh definition)}(hhh](h)}(hpPlatform Management Link (APML) Specification is available as part of the open source SoC register reference at:h]hpPlatform Management Link (APML) Specification is available as part of the open source SoC register reference at:}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj?ubh)}(h6https://www.amd.com/en/support/tech-docs?keyword=55898h]h reference)}(hjRh]h6https://www.amd.com/en/support/tech-docs?keyword=55898}(hjVhhhNhNubah}(h]h ]h"]h$]h&]refurijRuh1jThjPubah}(h]h ]h"]h$]h&]uh1hhhhKhj?ubeh}(h]h ]h"]h$]h&]uh1j=hj)ubeh}(h]h ]h"]h$]h&]uh1j'hhhKhj$ubah}(h]h ]h"]h$]h&]uh1j"hhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]bullet*uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h+Author: Akshay Gupta h](hAuthor: Akshay Gupta <}(hjhhhNhNubjU)}(hakshay.gupta@amd.comh]hakshay.gupta@amd.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:akshay.gupta@amd.comuh1jThjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK!hhhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK$ubh)}(hXThe APML provides a way to communicate with the SB Remote Management interface (SB-RMI) module from the external SMBus master that can be used to report socket power on AMD platforms using mailbox command and resembles a typical 8-pin remote power sensor's I2C interface to BMC.h]hXThe APML provides a way to communicate with the SB Remote Management interface (SB-RMI) module from the external SMBus master that can be used to report socket power on AMD platforms using mailbox command and resembles a typical 8-pin remote power sensor’s I2C interface to BMC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubh)}(hFThis driver implements current power with power cap and power cap max.h]hFThis driver implements current power with power cap and power cap max.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjhhubeh}(h] descriptionah ]h"] descriptionah$]h&]uh1hhhhhhhhK$ubh)}(hhh](h)}(hsysfs-Interfaceh]hsysfs-Interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK.ubh)}(hPower sensors can be queried and set via the standard ``hwmon`` interface on ``sysfs``, under the directory ``/sys/class/hwmon/hwmonX`` for some value of ``X`` (search for the ``X`` such that ``/sys/class/hwmon/hwmonX/name`` has content ``sbrmi``)h](h6Power sensors can be queried and set via the standard }(hjhhhNhNubhliteral)}(h ``hwmon``h]hhwmon}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh interface on }(hjhhhNhNubj)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, under the directory }(hjhhhNhNubj)}(h``/sys/class/hwmon/hwmonX``h]h/sys/class/hwmon/hwmonX}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh for some value of }(hjhhhNhNubj)}(h``X``h]hX}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (search for the }(hjhhhNhNubj)}(h``X``h]hX}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh such that }(hjhhhNhNubj)}(h ``/sys/class/hwmon/hwmonX/name``h]h/sys/class/hwmon/hwmonX/name}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh has content }(hjhhhNhNubj)}(h ``sbrmi``h]hsbrmi}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK/hjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK8uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPermh]hPerm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubhtbody)}(hhh](j)}(hhh](j)}(hhh]h)}(h power1_inputh]h power1_input}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hROh]hRO}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hj,ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCurrent Power consumedh]hCurrent Power consumed}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjCubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h power1_caph]h power1_cap}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjcubah}(h]h ]h"]h$]h&]uh1jhj`ubj)}(hhh]h)}(hRWh]hRW}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjzubah}(h]h ]h"]h$]h&]uh1jhj`ubj)}(hhh]h)}(h3Power limit can be set between 0 and power1_cap_maxh]h3Power limit can be set between 0 and power1_cap_max}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hpower1_cap_maxh]hpower1_cap_max}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hROh]hRO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h8Maximum powerlimit calculated and reported by the SMU FWh]h8Maximum powerlimit calculated and reported by the SMU FW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubh)}(hThe following example show how the 'Power' attribute from the i2c-addresses can be monitored using the userspace utilities like ``sensors`` binary::h](hThe following example show how the ‘Power’ attribute from the i2c-addresses can be monitored using the userspace utilities like }(hjhhhNhNubj)}(h ``sensors``h]hsensors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh binary:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK /sys/class/hwmon/hwmon1/power1_cap # cat /sys/class/hwmon/hwmon1/power1_cap 180000000h](j.)}(hNAlso, Below shows how get and set the values from sysfs entries individually::h]hNAlso, Below shows how get and set the values from sysfs entries individually::}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j-hhhKNhjBubj>)}(hhh](h)}(h6# cat /sys/class/hwmon/hwmon1/power1_cap_max 225000000h]h6# cat /sys/class/hwmon/hwmon1/power1_cap_max 225000000}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjTubh)}(hh# echo 180000000 > /sys/class/hwmon/hwmon1/power1_cap # cat /sys/class/hwmon/hwmon1/power1_cap 180000000h]hh# echo 180000000 > /sys/class/hwmon/hwmon1/power1_cap # cat /sys/class/hwmon/hwmon1/power1_cap 180000000}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjTubeh}(h]h ]h"]h$]h&]uh1j=hjBubeh}(h]h ]h"]h$]h&]uh1j'hhhKNhj?ubah}(h]h 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