sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget!/translations/zh_CN/hwmon/mpq8646modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget!/translations/zh_TW/hwmon/mpq8646modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget!/translations/it_IT/hwmon/mpq8646modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget!/translations/ja_JP/hwmon/mpq8646modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget!/translations/ko_KR/hwmon/mpq8646modnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget!/translations/pt_BR/hwmon/mpq8646modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget!/translations/sp_SP/hwmon/mpq8646modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h%SPDX-License-Identifier: GPL-2.0-onlyh]h%SPDX-License-Identifier: GPL-2.0-only}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh;/var/lib/git/docbuild/linux/Documentation/hwmon/mpq8646.rsthKubh)}(hACopyright (c) 2026 Free Mobile - Vincent Jardin h]hACopyright (c) 2026 Free Mobile - Vincent Jardin }hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(hKernel driver mpq8646h]hKernel driver mpq8646}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hSupported chips:h]hSupported chips:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(h#* MPS MPQ8646 Prefix: 'mpq8646' h]h bullet_list)}(hhh]h list_item)}(hMPS MPQ8646 Prefix: 'mpq8646' h](h)}(h MPS MPQ8646h]h MPS MPQ8646}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubh)}(hPrefix: 'mpq8646'h]hPrefix: ‘mpq8646’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]bullet*uh1jhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubhdefinition_list)}(hhh]hdefinition_list_item)}(h+Author: - Vincent Jardin h](hterm)}(hAuthor:h]hAuthor:}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhKhjCubh definition)}(hhh]j)}(hhh]j)}(h!Vincent Jardin h]h)}(h Vincent Jardin h](hVincent Jardin <}(hjchhhNhNubh reference)}(hvjardin@free.frh]hvjardin@free.fr}(hjmhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:vjardin@free.fruh1jkhjcubh>}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj_ubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]j4-uh1jhhhKhjYubah}(h]h ]h"]h$]h&]uh1jWhjCubeh}(h]h ]h"]h$]h&]uh1jAhhhKhj>ubah}(h]h ]h"]h$]h&]uh1j<hhhhhNhNubh)}(hhh](h)}(h Chip-identityh]h Chip-identity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(haSupport the boards that are designed with the MPS MPQ8646 probed thanks to``MFR_MODEL`` register.h]haSupport the boards that are designed with the MPS MPQ8646 probed thanks to``MFR_MODEL`` register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h5This driver targets the MPQ8646 silicon specifically.h]h5This driver targets the MPQ8646 silicon specifically.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] chip-identityah ]h"] chip-identityah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXFThe MPQ8646 is a fully integrated, PMBus-compatible, high-frequency, synchronous buck converter. It offers a compact solution that achieves up high Amps output current per phase, with excellent load and line regulation over a wide input supply range. The chip operates at high efficiency over a wide output current load range.h]hXFThe MPQ8646 is a fully integrated, PMBus-compatible, high-frequency, synchronous buck converter. It offers a compact solution that achieves up high Amps output current per phase, with excellent load and line regulation over a wide input supply range. The chip operates at high efficiency over a wide output current load range.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hTThe PMBus interface provides converter configurations and key parameters monitoring.h]hTThe PMBus interface provides converter configurations and key parameters monitoring.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjhhubh)}(hXGThe device adopts MPS's proprietary multi-phase digital constant-on-time (MCOT) control, which provides fast transient response and eases loop stabilization. The MCOT scheme also allows multiple devices or channels to be connected in parallel with excellent current sharing and phase interleaving for high-current applications.h]hXIThe device adopts MPS’s proprietary multi-phase digital constant-on-time (MCOT) control, which provides fast transient response and eases loop stabilization. The MCOT scheme also allows multiple devices or channels to be connected in parallel with excellent current sharing and phase interleaving for high-current applications.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjhhubh)}(hFully integrated protection features include over-current protection (OCP), over-voltage protection (OVP), under-voltage protection (UVP), and over-temperature protection (OTP).h]hFully integrated protection features include over-current protection (OCP), over-voltage protection (OVP), under-voltage protection (UVP), and over-temperature protection (OTP).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjhhubh)}(hThis device is compliant with:h]hThis device is compliant with:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjhhubj)}(hhh]j)}(hPMBus rev 1.3 interface. h]h)}(hPMBus rev 1.3 interface.h]hPMBus rev 1.3 interface.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hj5ubah}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubah}(h]h ]h"]h$]h&]j4juh1jhhhK1hjhhubh)}(hTThe driver exports the following attributes via the 'sysfs' files for input voltage:h]hXThe driver exports the following attributes via the ‘sysfs’ files for input voltage:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjhhubj)}(hhh](j)}(h in1_inputh]h)}(hjfh]h in1_input}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjdubah}(h]h ]h"]h$]h&]uh1jhjahhhhhNubj)}(h in1_labelh]h)}(hj}h]h in1_label}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hj{ubah}(h]h ]h"]h$]h&]uh1jhjahhhhhNubj)}(hin1_maxh]h)}(hjh]hin1_max}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjahhhhhNubj)}(h in1_max_alarmh]h)}(hjh]h in1_max_alarm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjahhhhhNubj)}(hin1_minh]h)}(hjh]hin1_min}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjahhhhhNubj)}(h in1_min_alarmh]h)}(hjh]h in1_min_alarm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjubah}(h]h ]h"]h$]h&]uh1jhjahhhhhNubj)}(hin1_crith]h)}(hjh]hin1_crit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK ``OPERATION`` (0x01)h]h)}(hj h](j)}(h``regulator_enable()``h]hregulator_enable()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh / }(hjhhhNhNubj)}(h``regulator_disable()``h]hregulator_disable()}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh -> }(hjhhhNhNubj)}(h ``OPERATION``h]h OPERATION}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (0x01)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKvhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h6``regulator_set_voltage()`` -> ``VOUT_COMMAND`` (0x21)h]h)}(hjUh](j)}(h``regulator_set_voltage()``h]hregulator_set_voltage()}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh -> }(hjWhhhNhNubj)}(h``VOUT_COMMAND``h]h VOUT_COMMAND}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh (0x21)}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKwhjSubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h3``regulator_get_voltage()`` -> ``READ_VOUT`` (0x8B)h]h)}(hjh](j)}(h``regulator_get_voltage()``h]hregulator_get_voltage()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh -> }(hjhhhNhNubj)}(h ``READ_VOUT``h]h READ_VOUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (0x8B)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKxhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h7``regulator_is_enabled()`` -> ``OPERATION`` bit-decode h]h)}(h6``regulator_is_enabled()`` -> ``OPERATION`` bit-decodeh](j)}(h``regulator_is_enabled()``h]hregulator_is_enabled()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh -> }(hjhhhNhNubj)}(h ``OPERATION``h]h OPERATION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh bit-decode}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j4juh1jhhhKvhjhhubh)}(hThe single regulator descriptor is named ``"vout"`` (page 0). For a multi-page configuration the descriptor table can be extended in the driver.h](h)The single regulator descriptor is named }(hjhhhNhNubj)}(h ``"vout"``h]h"vout"}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh] (page 0). For a multi-page configuration the descriptor table can be extended in the driver.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK{hjhhubeh}(h]regulator-framework-integrationah ]h"]regulator framework integrationah$]h&]uh1hhhhhhhhKpubh)}(hhh](h)}(hIn-driver alarm-poll fallbackh]hIn-driver alarm-poll fallback}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhKubh)}(hXOn boards where the chip's ``SMBALERT#`` pin is unavailable to the SoC, ``pmbus_core::pmbus_irq_setup`` cannot deliver SMBALERT-driven ``poll(POLLPRI)`` wakes or ``udev change@...`` events on the ``inX_alarm`` files. The driver provides a ``delayed_work``-based polling fallback that periodically invokes the pmbus core fault check, ``pmbus_check_and_notify_faults()``, which sends the notifications and then clears the latched faults, exactly like the ``SMBALERT#`` interrupt path. The frequency of polling is tunable:h](hOn boards where the chip’s }(hj8hhhNhNubj)}(h ``SMBALERT#``h]h SMBALERT#}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh pin is unavailable to the SoC, }(hj8hhhNhNubj)}(h``pmbus_core::pmbus_irq_setup``h]hpmbus_core::pmbus_irq_setup}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh cannot deliver SMBALERT-driven }(hj8hhhNhNubj)}(h``poll(POLLPRI)``h]h poll(POLLPRI)}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh wakes or }(hj8hhhNhNubj)}(h``udev change@...``h]hudev change@...}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh events on the }(hj8hhhNhNubj)}(h ``inX_alarm``h]h inX_alarm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh files. The driver provides a }(hj8hhhNhNubj)}(h``delayed_work``h]h delayed_work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubhN-based polling fallback that periodically invokes the pmbus core fault check, }(hj8hhhNhNubj)}(h#``pmbus_check_and_notify_faults()``h]hpmbus_check_and_notify_faults()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubhU, which sends the notifications and then clears the latched faults, exactly like the }(hj8hhhNhNubj)}(h ``SMBALERT#``h]h SMBALERT#}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh5 interrupt path. The frequency of polling is tunable:}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj'hhubh literal_block)}(hC/sys/kernel/debug/i2c/i2c-/-/alarm_poll_interval_msh]hC/sys/kernel/debug/i2c/i2c-/-/alarm_poll_interval_ms}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj'hhubh)}(hThe default is 1000 ms.h]hThe default is 1000 ms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj'hhubh)}(hSet it to 0 to disable. The worker self-suppresses when ``client->irq != 0`` (i.e. when DT supplies an ``interrupts = <...>`` property on the regulator node), so adding ``SMBALERT#`` wiring is a zero-driver-change uplift on a future board rev.h](h8Set it to 0 to disable. The worker self-suppresses when }(hjhhhNhNubj)}(h``client->irq != 0``h]hclient->irq != 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (i.e. when DT supplies an }(hjhhhNhNubj)}(h``interrupts = <...>``h]hinterrupts = <...>}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh- property on the regulator node), so adding }(hjhhhNhNubj)}(h ``SMBALERT#``h]h SMBALERT#}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh= wiring is a zero-driver-change uplift on a future board rev.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj'hhubeh}(h]in-driver-alarm-poll-fallbackah ]h"]in-driver alarm-poll fallbackah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h!MPS post-mortem (PROTECTION_LAST)h]h!MPS post-mortem (PROTECTION_LAST)}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ hhhhhKubh)}(hThe MPQ8646 silicon keeps a single 16-bit NVM-backed record of the last protection event in ``PROTECTION_LAST`` (0xFB). It survives chip power/reset. The following debugfs entries expose it:h](h\The MPQ8646 silicon keeps a single 16-bit NVM-backed record of the last protection event in }(hjQ hhhNhNubj)}(h``PROTECTION_LAST``h]hPROTECTION_LAST}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ ubhO (0xFB). It survives chip power/reset. The following debugfs entries expose it:}(hjQ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@ hhubj)}(h/sys/kernel/debug/i2c/i2c-/-/protection_last (RO) /sys/kernel/debug/i2c/i2c-/-/status_decoded (RO)h]h/sys/kernel/debug/i2c/i2c-/-/protection_last (RO) /sys/kernel/debug/i2c/i2c-/-/status_decoded (RO)}hjq sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj@ hhubh)}(hX.``protection_last`` decodes the 16-bit value based on the datasheet fault names (``INIT_FAULT``, ``NVM_CRC_ERROR``, ``NVM_FAULT``, ``OC_PHASE_FAULT``, ``OTP_SELF_FAULT``, ``SWITCH_PRD_FAULT``, ``VIN_OV_FAULT``, ``VOUT_OV_FAULT``, ``VOUT_UV_FAULT``, ``OC_TOT_FAULT``, ``VIN_UVLO_FAULT``, ``DRMOS_OTP``).h](j)}(h``protection_last``h]hprotection_last}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh> decodes the 16-bit value based on the datasheet fault names (}(hj hhhNhNubj)}(h``INIT_FAULT``h]h INIT_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }(hj hhhNhNubj)}(h``NVM_CRC_ERROR``h]h NVM_CRC_ERROR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h ``NVM_FAULT``h]h NVM_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }(hj hhhNhNubj)}(h``OC_PHASE_FAULT``h]hOC_PHASE_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h``OTP_SELF_FAULT``h]hOTP_SELF_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h``SWITCH_PRD_FAULT``h]hSWITCH_PRD_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h``VIN_OV_FAULT``h]h VIN_OV_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h``VOUT_OV_FAULT``h]h VOUT_OV_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h``VOUT_UV_FAULT``h]h VOUT_UV_FAULT}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h``OC_TOT_FAULT``h]h OC_TOT_FAULT}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h``VIN_UVLO_FAULT``h]hVIN_UVLO_FAULT}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }hj sbj)}(h ``DRMOS_OTP``h]h DRMOS_OTP}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@ hhubh)}(h``status_decoded`` reads ``STATUS_WORD`` (0x79) and renders the 16 bits with MPS-extension labels (bit12 = ``NVM_SUMMARY``, bit8 = ``WATCH_DOG``, bit0 = ``DRMOS_FAULT``) instead of the PMBus 1.3 spec generic names.h](j)}(h``status_decoded``h]hstatus_decoded}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs ubh reads }(hjs hhhNhNubj)}(h``STATUS_WORD``h]h STATUS_WORD}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs ubhC (0x79) and renders the 16 bits with MPS-extension labels (bit12 = }(hjs hhhNhNubj)}(h``NVM_SUMMARY``h]h NVM_SUMMARY}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs ubh , bit8 = }(hjs hhhNhNubj)}(h ``WATCH_DOG``h]h WATCH_DOG}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs ubh , bit0 = }(hjs hhhNhNubj)}(h``DRMOS_FAULT``h]h DRMOS_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs ubh.) instead of the PMBus 1.3 spec generic names.}(hjs hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@ hhubeh}(h]mps-post-mortem-protection-lastah ]h"]!mps post-mortem (protection_last)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hNVMEM snapshoth]hNVMEM snapshot}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hX!When ``CONFIG_NVMEM=y`` is set, the chip's NVM-backed observability registers are exposed as a single 16-byte read-only ``nvmem_device`` at ``/sys/bus/nvmem/devices//nvmem``. Layout (little-endian for 16-bit fields, zero-fill on per-entry read failure and for the reserved tail):h](hWhen }(hj hhhNhNubj)}(h``CONFIG_NVMEM=y``h]hCONFIG_NVMEM=y}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhc is set, the chip’s NVM-backed observability registers are exposed as a single 16-byte read-only }(hj hhhNhNubj)}(h``nvmem_device``h]h nvmem_device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh at }(hj hhhNhNubj)}(h+``/sys/bus/nvmem/devices//nvmem``h]h'/sys/bus/nvmem/devices//nvmem}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhj. Layout (little-endian for 16-bit fields, zero-fill on per-entry read failure and for the reserved tail):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj)}(hoffset 0..1 PROTECTION_LAST (0xFB) word offset 2..3 MFR_RETRY_TIMES (0xF4) word offset 4..5 MFR_CONFIG_ID (0xC0) word offset 6..7 MFR_VBOOT_CFG (0xFC) word offset 8 MFR_SILICON_REV (0xC3) byte offset 9..15 reserved (zero)h]hoffset 0..1 PROTECTION_LAST (0xFB) word offset 2..3 MFR_RETRY_TIMES (0xF4) word offset 4..5 MFR_CONFIG_ID (0xC0) word offset 6..7 MFR_VBOOT_CFG (0xFC) word offset 8 MFR_SILICON_REV (0xC3) byte offset 9..15 reserved (zero)}hj4 sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj hhubh)}(hBSuitable for single-``cat`` post-mortem capture by a fleet daemon.h](hSuitable for single-}(hjB hhhNhNubj)}(h``cat``h]hcat}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB ubh' post-mortem capture by a fleet daemon.}(hjB hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]nvmem-snapshotah ]h"]nvmem snapshotah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDiagnostics and introspectionh]hDiagnostics and introspection}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj hhhhhKubh)}(hX+When ``CONFIG_DEBUG_FS=y`` is set, the driver adds a read-only decode surface to the client's pmbus debugfs directory, ``/sys/kernel/debug/i2c/i2c-/-/``. The driver intentionally exposes no raw register poke/peek debugfs; use i2c-dev (``i2cget``/``i2cset``/``i2ctransfer``) for that.h](hWhen }(hj{ hhhNhNubj)}(h``CONFIG_DEBUG_FS=y``h]hCONFIG_DEBUG_FS=y}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ ubh_ is set, the driver adds a read-only decode surface to the client’s pmbus debugfs directory, }(hj{ hhhNhNubj)}(h1``/sys/kernel/debug/i2c/i2c-/-/``h]h-/sys/kernel/debug/i2c/i2c-/-/}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ ubhS. The driver intentionally exposes no raw register poke/peek debugfs; use i2c-dev (}(hj{ hhhNhNubj)}(h ``i2cget``h]hi2cget}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ ubh/}(hj{ hhhNhNubj)}(h ``i2cset``h]hi2cset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ ubh/}hj{ sbj)}(h``i2ctransfer``h]h i2ctransfer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ ubh ) for that.}(hj{ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjj hhubh)}(h%Identity / observability (read-only):h]h%Identity / observability (read-only):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjj hhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1j hj ubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hFileh]hFile}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj' ubah}(h]h ]h"]h$]h&]uh1j% hj" ubj& )}(hhh]h)}(hPMBus / MFR cmdh]hPMBus / MFR cmd}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj> ubah}(h]h ]h"]h$]h&]uh1j% hj" ubj& )}(hhh]h)}(h Descriptionh]h Description}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjU ubah}(h]h ]h"]h$]h&]uh1j% hj" ubeh}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1j hj ubhtbody)}(hhh](j! )}(hhh](j& )}(hhh]h)}(h``mfr_config_id``h]j)}(hj h]h mfr_config_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj} ubj& )}(hhh]h)}(h 0xC0 (word)h]h 0xC0 (word)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj} ubj& )}(hhh]h)}(hboard / SKU NVM identifierh]hboard / SKU NVM identifier}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj} ubeh}(h]h ]h"]h$]h&]uh1j hjz ubj! )}(hhh](j& )}(hhh]h)}(h``mfr_config_code_rev``h]j)}(hj h]hmfr_config_code_rev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj ubj& )}(hhh]h)}(h 0xC1 (word)h]h 0xC1 (word)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj ubj& )}(hhh]h)}(h8NVM image revision (PART_RECOG + config code rev fields)h]h8NVM image revision (PART_RECOG + config code rev fields)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj ubeh}(h]h ]h"]h$]h&]uh1j hjz ubj! )}(hhh](j& )}(hhh]h)}(h``mfr_silicon_rev``h]j)}(hj3 h]hmfr_silicon_rev}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1 ubah}(h]h ]h"]h$]h&]uh1hhhhKhj. ubah}(h]h ]h"]h$]h&]uh1j% hj+ ubj& )}(hhh]h)}(h 0xC3 (byte)h]h 0xC3 (byte)}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjN ubah}(h]h ]h"]h$]h&]uh1j% hj+ ubj& )}(hhh]h)}(h die revisionh]h die revision}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhje ubah}(h]h ]h"]h$]h&]uh1j% hj+ ubeh}(h]h ]h"]h$]h&]uh1j hjz ubj! )}(hhh](j& )}(hhh]h)}(h``mfr_retry_times``h]j)}(hj h]hmfr_retry_times}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj ubj& )}(hhh]h)}(h 0xF4 (word)h]h 0xF4 (word)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj ubj& )}(hhh]h)}(hXper-fault-class recovery-mode configuration (NOT a retry count). Four 4-bit fields [15:12]=OTP, [11:8]=VOUT_OV, [7:4]=VOUT_UV, [3:0]=OCP. Each field: 0x0=latch-off, 0x1..0xE=retry N times then latch off, 0xF=hiccup (retry indefinitely). The chip exposes no in-NVM retry-event counter; track transitions externally if needed (poll ``protection_last`` or watch ``inX_alarm`` / ``temp1_alarm`` ``poll(POLLPRI)`` wakes).h](hXJper-fault-class recovery-mode configuration (NOT a retry count). Four 4-bit fields [15:12]=OTP, [11:8]=VOUT_OV, [7:4]=VOUT_UV, [3:0]=OCP. Each field: 0x0=latch-off, 0x1..0xE=retry N times then latch off, 0xF=hiccup (retry indefinitely). The chip exposes no in-NVM retry-event counter; track transitions externally if needed (poll }(hj hhhNhNubj)}(h``protection_last``h]hprotection_last}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh or watch }(hj hhhNhNubj)}(h ``inX_alarm``h]h inX_alarm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh / }(hj hhhNhNubj)}(h``temp1_alarm``h]h temp1_alarm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh }(hj hhhNhNubj)}(h``poll(POLLPRI)``h]h poll(POLLPRI)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh wakes).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j% hj ubeh}(h]h ]h"]h$]h&]uh1j hjz ubj! )}(hhh](j& )}(hhh]h)}(h``mfr_vboot_cfg``h]j)}(hj)h]h mfr_vboot_cfg}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hhhhKhj$ubah}(h]h ]h"]h$]h&]uh1j% hj!ubj& )}(hhh]h)}(h 0xFC (word)h]h 0xFC (word)}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjDubah}(h]h ]h"]h$]h&]uh1j% hj!ubj& )}(hhh]h)}(hADDR/VBOOT latched at PORh]hADDR/VBOOT latched at POR}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj[ubah}(h]h ]h"]h$]h&]uh1j% hj!ubeh}(h]h ]h"]h$]h&]uh1j hjz ubeh}(h]h ]h"]h$]h&]uh1jx hj ubeh}(h]h ]h"]h$]h&]colsKuh1j hj ubah}(h]h ]h"]h$]h&]uh1j hjj hhhhhNubh)}(h Timing / UVLO knobs (read-only):h]h Timing / UVLO knobs (read-only):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjj hhubj )}(hhh]j )}(hhh](j )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1j hjubj )}(hhh]j! )}(hhh](j& )}(hhh]h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h PMBus cmdh]h PMBus cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1j hjubjy )}(hhh](j! )}(hhh](j& )}(hhh]h)}(h ``vin_on``h]j)}(hjh]hvin_on}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h 0x35 (word)h]h 0x35 (word)}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj:ubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(hUVLO turn-on thresholdh]hUVLO turn-on threshold}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjQubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h ``vin_off``h]j)}(hjvh]hvin_off}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1hhhhKhjqubah}(h]h ]h"]h$]h&]uh1j% hjnubj& )}(hhh]h)}(h 0x36 (word)h]h 0x36 (word)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjnubj& )}(hhh]h)}(hUVLO turn-off thresholdh]hUVLO turn-off threshold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjnubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h ``ton_delay``h]j)}(hjh]h ton_delay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h 0x60 (word)h]h 0x60 (word)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(hsoft-start delayh]hsoft-start delay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h ``ton_rise``h]j)}(hj$h]hton_rise}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h 0x61 (word)h]h 0x61 (word)}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj?ubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(hsoft-start ramp timeh]hsoft-start ramp time}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjVubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``toff_delay``h]j)}(hj{h]h toff_delay}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hhhhKhjvubah}(h]h ]h"]h$]h&]uh1j% hjsubj& )}(hhh]h)}(h 0x64 (word)h]h 0x64 (word)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjsubj& )}(hhh]h)}(hsoft-stop delayh]hsoft-stop delay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjsubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h ``toff_fall``h]j)}(hjh]h toff_fall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h 0x65 (word)h]h 0x65 (word)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(hsoft-stop ramp timeh]hsoft-stop ramp time}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jx hjubeh}(h]h ]h"]h$]h&]colsKuh1j hjubah}(h]h ]h"]h$]h&]uh1j hjj hhhhhNubh)}(hThe only writable entry is ``alarm_poll_interval_ms`` (the alarm-poll worker cadence, see above), it is driver-local and never touches the chip.h](hThe only writable entry is }(hj4hhhNhNubj)}(h``alarm_poll_interval_ms``h]halarm_poll_interval_ms}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh[ (the alarm-poll worker cadence, see above), it is driver-local and never touches the chip.}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjj hhubeh}(h]diagnostics-and-introspectionah ]h"]diagnostics and introspectionah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hUnsafe provisioningh]hUnsafe provisioning}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hhhhhKubh)}(hXAvailable only when ``CONFIG_SENSORS_MPQ8646_DEBUG_UNSAFE=y`` (``default n``, it is for boards bring up only). They WRITE to the regulator. On many designs the MPQ8646 powers the main CPU core rail, so a wrong write can brown out the board or persist a bad setpoint into finite-cycle NVM. WARNING: Some wrong register writes can and likely will physically damage or destroy the chip and/or the board. An explicit warning banner is printed at probe time when this option is enabled.h](hAvailable only when }(hjmhhhNhNubj)}(h)``CONFIG_SENSORS_MPQ8646_DEBUG_UNSAFE=y``h]h%CONFIG_SENSORS_MPQ8646_DEBUG_UNSAFE=y}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubh (}(hjmhhhNhNubj)}(h ``default n``h]h default n}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubhX, it is for boards bring up only). They WRITE to the regulator. On many designs the MPQ8646 powers the main CPU core rail, so a wrong write can brown out the board or persist a bad setpoint into finite-cycle NVM. WARNING: Some wrong register writes can and likely will physically damage or destroy the chip and/or the board. An explicit warning banner is printed at probe time when this option is enabled.}(hjmhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj\hhubj )}(hhh]j )}(hhh](j )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthK9uh1j hjubj )}(hhh]j! )}(hhh](j& )}(hhh]h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(hPMBus / MFR cmdh]hPMBus / MFR cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1j hjubjy )}(hhh](j! )}(hhh](j& )}(hhh]h)}(h ``store_all``h]j)}(hj%h]h store_all}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h0x15h]h0x15}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h3STORE_USER_ALL Send-Byte (commit RAM config to NVM)h]h3STORE_USER_ALL Send-Byte (commit RAM config to NVM)}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``restore_all``h]j)}(hj|h]h restore_all}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1hhhhMhjwubah}(h]h ]h"]h$]h&]uh1j% hjtubj& )}(hhh]h)}(h0x16h]h0x16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hjtubj& )}(hhh]h)}(h9RESTORE_USER_ALL Send-Byte (revert RAM to last-NVM image)h]h9RESTORE_USER_ALL Send-Byte (revert RAM to last-NVM image)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hjtubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``clear_protection_last``h]j)}(hjh]hclear_protection_last}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h0x08h]h0x08}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(hCLEAR_LAST_FAULT Send-Byteh]hCLEAR_LAST_FAULT Send-Byte}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``clear_protection_last_force``h]j)}(hj*h]hclear_protection_last_force}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1hhhhM hj%ubah}(h]h ]h"]h$]h&]uh1j% hj"ubj& )}(hhh]h)}(h--h]h--}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjEubah}(h]h ]h"]h$]h&]uh1j% hj"ubj& )}(hhh]h)}(h!gated CLEAR_LAST_FAULT, see belowh]h!gated CLEAR_LAST_FAULT, see below}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj\ubah}(h]h ]h"]h$]h&]uh1j% hj"ubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``on_off_config``h]j)}(hjh]h on_off_config}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1j% hjyubj& )}(hhh]h)}(h 0x02 (byte)h]h 0x02 (byte)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j% hjyubj& )}(hhh]h)}(h1PMBus vs CTRL-pin on/off source + active polarityh]h1PMBus vs CTRL-pin on/off source + active polarity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j% hjyubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``vout_margin_high``h]j)}(hjh]hvout_margin_high}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h 0x25 (word)h]h 0x25 (word)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(hmargin-high VOUT setpointh]hmargin-high VOUT setpoint}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``vout_margin_low``h]j)}(hj/h]hvout_margin_low}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1hhhhM hj*ubah}(h]h ]h"]h$]h&]uh1j% hj'ubj& )}(hhh]h)}(h 0x26 (word)h]h 0x26 (word)}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjJubah}(h]h ]h"]h$]h&]uh1j% hj'ubj& )}(hhh]h)}(hmargin-low VOUT setpointh]hmargin-low VOUT setpoint}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjaubah}(h]h ]h"]h$]h&]uh1j% hj'ubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``mfr_pmbus_lock``h]j)}(hjh]hmfr_pmbus_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hj~ubj& )}(hhh]h)}(h 0xEE (word)h]h 0xEE (word)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hj~ubj& )}(hhh]h)}(hprogrammable PMBus write-lockh]hprogrammable PMBus write-lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hj~ubeh}(h]h ]h"]h$]h&]uh1j hjubj! )}(hhh](j& )}(hhh]h)}(h``mfr_product_rev_user``h]j)}(hjh]hmfr_product_rev_user}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h 0xC2 (word)h]h 0xC2 (word)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hjubj& )}(hhh]h)}(h"user-programmable product revisionh]h"user-programmable product revision}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j% hjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jx hjubeh}(h]h ]h"]h$]h&]colsKuh1j hjubah}(h]h ]h"]h$]h&]uh1j hj\hhhhhNubh)}(h``clear_protection_last`` writes ``CLEAR_LAST_FAULT`` (0x08) Send-Byte. The chip silently no-ops unless ``MFR_CFG_EXT`` (0xF5) bit[6] is set.h](j)}(h``clear_protection_last``h]hclear_protection_last}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh writes }(hj?hhhNhNubj)}(h``CLEAR_LAST_FAULT``h]hCLEAR_LAST_FAULT}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh3 (0x08) Send-Byte. The chip silently no-ops unless }(hj?hhhNhNubj)}(h``MFR_CFG_EXT``h]h MFR_CFG_EXT}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh (0xF5) bit[6] is set.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj\hhubh)}(hX``clear_protection_last_force`` performs the unlock with the following six-step dancing:h](j)}(h``clear_protection_last_force``h]hclear_protection_last_force}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh9 performs the unlock with the following six-step dancing:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj\hhubhenumerated_list)}(hhh](j)}(hDread ``WRITE_PROTECT`` (0x10) and ``MFR_CFG_EXT`` (0xF5) for restoreh]h)}(hjh](hread }(hjhhhNhNubj)}(h``WRITE_PROTECT``h]h WRITE_PROTECT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (0x10) and }(hjhhhNhNubj)}(h``MFR_CFG_EXT``h]h MFR_CFG_EXT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (0xF5) for restore}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hclear ``WRITE_PROTECT`` if seth]h)}(hjh](hclear }(hjhhhNhNubj)}(h``WRITE_PROTECT``h]h WRITE_PROTECT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh if set}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h5set ``MFR_CFG_EXT`` bit[6] = 1, preserving other bitsh]h)}(hjh](hset }(hjhhhNhNubj)}(h``MFR_CFG_EXT``h]h MFR_CFG_EXT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh" bit[6] = 1, preserving other bits}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h send ``CLEAR_LAST_FAULT`` (0x08)h]h)}(hj/h](hsend }(hj1hhhNhNubj)}(h``CLEAR_LAST_FAULT``h]hCLEAR_LAST_FAULT}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubh (0x08)}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(harestore ``MFR_CFG_EXT`` (with retry to handle the chip's undocumented post-NVM-write busy window)h]h)}(harestore ``MFR_CFG_EXT`` (with retry to handle the chip's undocumented post-NVM-write busy window)h](hrestore }(hjZhhhNhNubj)}(h``MFR_CFG_EXT``h]h MFR_CFG_EXT}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubhL (with retry to handle the chip’s undocumented post-NVM-write busy window)}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjVubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hrestore ``WRITE_PROTECT`` h]h)}(hrestore ``WRITE_PROTECT``h](hrestore }(hjhhhNhNubj)}(h``WRITE_PROTECT``h]h WRITE_PROTECT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhj\hhhhhMubeh}(h]unsafe-provisioningah ]h"]unsafe provisioningah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Devicetreeh]h Devicetree}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM!ubh)}(hWThe driver uses ``compatible = "mps,mpq8646"``. There are some few optional properties:h](hThe driver uses }(hjhhhNhNubj)}(h``compatible = "mps,mpq8646"``h]hcompatible = "mps,mpq8646"}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh). There are some few optional properties:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubj)}(hhh](j)}(h``mps,vout-fb-divider-ratio-permille`` : it writes ``VOUT_SCALE_LOOP`` (0x29) at probe to compensate for an external resistor divider in the VOUT feedback path. The valid range is 11-bit.h]h)}(h``mps,vout-fb-divider-ratio-permille`` : it writes ``VOUT_SCALE_LOOP`` (0x29) at probe to compensate for an external resistor divider in the VOUT feedback path. The valid range is 11-bit.h](j)}(h&``mps,vout-fb-divider-ratio-permille``h]h"mps,vout-fb-divider-ratio-permille}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh : it writes }(hjhhhNhNubj)}(h``VOUT_SCALE_LOOP``h]hVOUT_SCALE_LOOP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhu (0x29) at probe to compensate for an external resistor divider in the VOUT feedback path. The valid range is 11-bit.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM&hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h``interrupts = <...>`` : if the board routes the chip's ``SMBALERT#`` pin to a SoC GPIO, declaring it here lights up ``pmbus_core::pmbus_irq_setup`` and disables the in-driver alarm-poll fallbackh]h)}(h``interrupts = <...>`` : if the board routes the chip's ``SMBALERT#`` pin to a SoC GPIO, declaring it here lights up ``pmbus_core::pmbus_irq_setup`` and disables the in-driver alarm-poll fallbackh](j)}(h``interrupts = <...>``h]hinterrupts = <...>}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubh$ : if the board routes the chip’s }(hj)hhhNhNubj)}(h ``SMBALERT#``h]h SMBALERT#}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubh0 pin to a SoC GPIO, declaring it here lights up }(hj)hhhNhNubj)}(h``pmbus_core::pmbus_irq_setup``h]hpmbus_core::pmbus_irq_setup}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubh/ and disables the in-driver alarm-poll fallback}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM)hj%ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j4juh1jhhhM&hjhhubeh}(h] devicetreeah ]h"] devicetreeah$]h&]uh1hhhhhhhhM!ubeh}(h]kernel-driver-mpq8646ah ]h"]kernel driver mpq8646ah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksj% footnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids'}(jjjjjjjgjjj$j!j= j: j j jg jd jYjVjjjzjwu nametypes}(jjjjjj$j= j jg jYjjzuh}(jhjjjgjjjmj!jj: j'j j@ jd j jVjj jj\jwju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]hsystem_message)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]levelKtypeINFOlineM sourcehuh1j hjEubatransform_messages] transformerN include_log] decorationNhhub.