[sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget"/translations/zh_CN/hwmon/max31827modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/zh_TW/hwmon/max31827modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/it_IT/hwmon/max31827modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/ja_JP/hwmon/max31827modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/ko_KR/hwmon/max31827modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/sp_SP/hwmon/max31827modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh h](hterm)}(hAuthors:h]hAuthors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK"hjubh definition)}(hhh]h)}(hhh]h)}(h)Daniel Matyas h]h)}(h(Daniel Matyas h](hDaniel Matyas <}(hjhhhNhNubh reference)}(hdaniel.matyas@analog.comh]hdaniel.matyas@analog.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:daniel.matyas@analog.comuh1jhjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]j-uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK"hjubah}(h]h ]h"]h$]h&]uh1jhhhhhNhNubh)}(hhh](h)}(h Descriptionh]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhK%ubh)}(hX"The chips supported by this driver are quite similar. The only difference between them is found in the default power-on behaviour of the chips. While the MAX31827's fault queue is set to 1, the other two chip's fault queue is set to 4. Besides this, the MAX31829's alarm active state is high, while the other two chip's alarms are active on low. It is important to note that the chips can be configured to operate in the same manner with 1 write operation to the configuration register. From here on, we will refer to all these chips as MAX31827.h]hX*The chips supported by this driver are quite similar. The only difference between them is found in the default power-on behaviour of the chips. While the MAX31827’s fault queue is set to 1, the other two chip’s fault queue is set to 4. Besides this, the MAX31829’s alarm active state is high, while the other two chip’s alarms are active on low. It is important to note that the chips can be configured to operate in the same manner with 1 write operation to the configuration register. From here on, we will refer to all these chips as MAX31827.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hj$hhubh)}(hMAX31827 implements a temperature sensor with a 6 WLP packaging scheme. This sensor measures the temperature of the chip itself.h]hMAX31827 implements a temperature sensor with a 6 WLP packaging scheme. This sensor measures the temperature of the chip itself.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hj$hhubh)}(hMAX31827 has low and over temperature alarms with an effective value and a hysteresis value: -40 and -30 degrees for under temperature alarm and +100 and +90 degrees for over temperature alarm.h]hMAX31827 has low and over temperature alarms with an effective value and a hysteresis value: -40 and -30 degrees for under temperature alarm and +100 and +90 degrees for over temperature alarm.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hj$hhubh)}(hXThe alarm can be configured in comparator and interrupt mode from the devicetree. In Comparator mode, the OT/UT status bits have a value of 1 when the temperature rises above the TH value or falls below TL, which is also subject to the Fault Queue selection. OT status returns to 0 when the temperature drops below the TH_HYST value or when shutdown mode is entered. Similarly, UT status returns to 0 when the temperature rises above TL_HYST value or when shutdown mode is entered.h]hXThe alarm can be configured in comparator and interrupt mode from the devicetree. In Comparator mode, the OT/UT status bits have a value of 1 when the temperature rises above the TH value or falls below TL, which is also subject to the Fault Queue selection. OT status returns to 0 when the temperature drops below the TH_HYST value or when shutdown mode is entered. Similarly, UT status returns to 0 when the temperature rises above TL_HYST value or when shutdown mode is entered.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hj$hhubh)}(hXIn interrupt mode exceeding TH also sets OT status to 1, which remains set until a read operation is performed on the configuration/status register (max or min attribute); at this point, it returns to 0. Once OT status is set to 1 from exceeding TH and reset, it is set to 1 again only when the temperature drops below TH_HYST. The output remains asserted until it is reset by a read. It is set again if the temperature rises above TH, and so on. The same logic applies to the operation of the UT status bit.h]hXIn interrupt mode exceeding TH also sets OT status to 1, which remains set until a read operation is performed on the configuration/status register (max or min attribute); at this point, it returns to 0. Once OT status is set to 1 from exceeding TH and reset, it is set to 1 again only when the temperature drops below TH_HYST. The output remains asserted until it is reset by a read. It is set again if the temperature rises above TH, and so on. The same logic applies to the operation of the UT status bit.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hj$hhubh)}(hXnPutting the MAX31827 into shutdown mode also resets the OT/UT status bits. Note that if the mode is changed while OT/UT status bits are set, an OT/UT status reset may be required before it begins to behave normally. To prevent this, it is recommended to perform a read of the configuration/status register to clear the status bits before changing the operating mode.h]hXnPutting the MAX31827 into shutdown mode also resets the OT/UT status bits. Note that if the mode is changed while OT/UT status bits are set, an OT/UT status reset may be required before it begins to behave normally. To prevent this, it is recommended to perform a read of the configuration/status register to clear the status bits before changing the operating mode.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhj$hhubh)}(hXTThe conversions can be manual with the one-shot functionality and automatic with a set frequency. When powered on, the chip measures temperatures with 1 conv/s. The conversion rate can be modified with update_interval attribute of the chip. Conversion/second = 1/update_interval. Thus, the available options according to the data sheet are:h]hXTThe conversions can be manual with the one-shot functionality and automatic with a set frequency. When powered on, the chip measures temperatures with 1 conv/s. The conversion rate can be modified with update_interval attribute of the chip. Conversion/second = 1/update_interval. Thus, the available options according to the data sheet are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhj$hhubh)}(hhh](h)}(h64000 (ms) = 1 conv/64 sech]h)}(hjh]h64000 (ms) = 1 conv/64 sec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h32000 (ms) = 1 conv/32 sech]h)}(hjh]h32000 (ms) = 1 conv/32 sec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h16000 (ms) = 1 conv/16 sech]h)}(hjh]h16000 (ms) = 1 conv/16 sec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h4000 (ms) = 1 conv/4 sech]h)}(hjh]h4000 (ms) = 1 conv/4 sec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h 1000 (ms) = 1 conv/sec (default)h]h)}(hjh]h 1000 (ms) = 1 conv/sec (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h250 (ms) = 4 conv/sech]h)}(hjh]h250 (ms) = 4 conv/sec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h125 (ms) = 8 conv/sec h]h)}(h125 (ms) = 8 conv/sech]h125 (ms) = 8 conv/sec}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhj$ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKShj$hhubh)}(hEnabling the device when it is already enabled has the side effect of setting the conversion frequency to 1 conv/s. The conversion time varies depending on the resolution.h]hEnabling the device when it is already enabled has the side effect of setting the conversion frequency to 1 conv/s. The conversion time varies depending on the resolution.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hj$hhubh)}(hbThe conversion time doubles with every bit of increased resolution. The available resolutions are:h]hbThe conversion time doubles with every bit of increased resolution. The available resolutions are:}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hj$hhubh)}(hhh](h)}(h 8 bit -> 8.75 ms conversion timeh]h)}(hjch]h 8 bit -> 8.75 ms conversion time}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjaubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhNubh)}(h 9 bit -> 17.5 ms conversion timeh]h)}(hjzh]h 9 bit -> 17.5 ms conversion time}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchjxubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhNubh)}(h10 bit -> 35 ms conversion timeh]h)}(hjh]h10 bit -> 35 ms conversion time}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhNubh)}(h+12 bit (default) -> 140 ms conversion time h]h)}(h*12 bit (default) -> 140 ms conversion timeh]h*12 bit (default) -> 140 ms conversion time}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKbhj$hhubh)}(hrThere is a temp1_resolution attribute which indicates the unit change in the input temperature in milli-degrees C.h]hrThere is a temp1_resolution attribute which indicates the unit change in the input temperature in milli-degrees C.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghj$hhubh)}(hhh](h)}(h1000 mC -> 8 bith]h)}(hjh]h1000 mC -> 8 bit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h500 mC -> 9 bith]h)}(hjh]h500 mC -> 9 bit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h250 mC -> 10 bith]h)}(hjh]h250 mC -> 10 bit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hJ62 mC -> 12 bit (default) - actually this is 62.5, but the fil returns 62 h]h)}(hI62 mC -> 12 bit (default) - actually this is 62.5, but the fil returns 62h]hI62 mC -> 12 bit (default) - actually this is 62.5, but the fil returns 62}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKjhj$hhubh)}(hX When chip is in shutdown mode and a read operation is requested, one-shot is triggered, the device waits for ms, and only after that is the temperature value register read. Note that the conversion times are rounded up to the nearest possible integer.h]hX When chip is in shutdown mode and a read operation is requested, one-shot is triggered, the device waits for ms, and only after that is the temperature value register read. Note that the conversion times are rounded up to the nearest possible integer.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohj$hhubh)}(hXThe LSB of the temperature values is 0.0625 degrees Celsius, but the values of the temperatures are displayed in milli-degrees. This means, that some data is lost. The step between 2 consecutive values is 62 or 63. This effect can be seen in the writing of alarm values too. For positive numbers the user-input value will always be rounded down to the nearest possible value, for negative numbers the user-input will always be rounded up to the nearest possible value.h]hXThe LSB of the temperature values is 0.0625 degrees Celsius, but the values of the temperatures are displayed in milli-degrees. This means, that some data is lost. The step between 2 consecutive values is 62 or 63. This effect can be seen in the writing of alarm values too. For positive numbers the user-input value will always be rounded down to the nearest possible value, for negative numbers the user-input will always be rounded up to the nearest possible value.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthj$hhubh)}(h]Bus timeout resets the I2C-compatible interface when SCL is low for more than 30ms (nominal).h]h]Bus timeout resets the I2C-compatible interface when SCL is low for more than 30ms (nominal).}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hj$hhubh)}(hAlarm polarity determines if the active state of the alarm is low or high. The behavior for both settings is dependent on the Fault Queue setting. The ALARM pin is an open-drain output and requires a pullup resistor to operate.h]hAlarm polarity determines if the active state of the alarm is low or high. The behavior for both settings is dependent on the Fault Queue setting. The ALARM pin is an open-drain output and requires a pullup resistor to operate.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hj$hhubh)}(hThe Fault Queue bits select how many consecutive temperature faults must occur before overtemperature or undertemperature faults are indicated in the corresponding status bits.h]hThe Fault Queue bits select how many consecutive temperature faults must occur before overtemperature or undertemperature faults are indicated in the corresponding status bits.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj$hhubeh}(h] descriptionah ]h"] descriptionah$]h&]uh1hhhhhhhhK%ubh)}(hhh](h)}(h PEC Supporth]h PEC Support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hMWhen reading a register value, the PEC byte is computed and sent by the chip.h]hMWhen reading a register value, the PEC byte is computed and sent by the chip.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hPEC on word data transaction represents a significant increase in bandwidth usage (+33% for both write and reads) in normal conditions.h]hPEC on word data transaction represents a significant increase in bandwidth usage (+33% for both write and reads) in normal conditions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hSince this operation implies there will be an extra delay to each transaction, PEC can be disabled or enabled through sysfs. Just write 1 to the "pec" file for enabling PEC and 0 for disabling it.h]hSince this operation implies there will be an extra delay to each transaction, PEC can be disabled or enabled through sysfs. Just write 1 to the “pec” file for enabling PEC and 0 for disabling it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] pec-supportah ]h"] pec supportah$]h&]uh1hhhhhhhhKubeh}(h]kernel-driver-max31827ah ]h"]kernel driver max31827ah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jjjjjju nametypes}(jjjuh}(jhjj$jju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.