sTsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget-/translations/zh_CN/hwmon/intel-m10-bmc-hwmonmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/zh_TW/hwmon/intel-m10-bmc-hwmonmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/it_IT/hwmon/intel-m10-bmc-hwmonmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ja_JP/hwmon/intel-m10-bmc-hwmonmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ko_KR/hwmon/intel-m10-bmc-hwmonmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/sp_SP/hwmon/intel-m10-bmc-hwmonmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhG/var/lib/git/docbuild/linux/Documentation/hwmon/intel-m10-bmc-hwmon.rsthKubhsection)}(hhh](htitle)}(h!Kernel driver intel-m10-bmc-hwmonh]h!Kernel driver intel-m10-bmc-hwmon}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hSupported chips:h]hSupported chips:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hC* Intel MAX 10 BMC for Intel PAC N3000 Prefix: 'n3000bmc-hwmon' h]h bullet_list)}(hhh]h list_item)}(h?Intel MAX 10 BMC for Intel PAC N3000 Prefix: 'n3000bmc-hwmon' h](h)}(h$Intel MAX 10 BMC for Intel PAC N3000h]h$Intel MAX 10 BMC for Intel PAC N3000}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubh)}(hPrefix: 'n3000bmc-hwmon'h]hPrefix: ‘n3000bmc-hwmon’}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]bullet*uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h%Author: Xu Yilun h](hAuthor: Xu Yilun <}(hjhhhNhNubh reference)}(hyilun.xu@intel.comh]hyilun.xu@intel.com}(hj$hhhNhNubah}(h]h ]h"]h$]h&]refurimailto:yilun.xu@intel.comuh1j"hjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hhhhhKubh)}(hX This driver adds the temperature, voltage, current and power reading support for the Intel MAX 10 Board Management Controller (BMC) chip. The BMC chip is integrated in some Intel Programmable Acceleration Cards (PAC). It connects to a set of sensor chips to monitor the sensor data of different components on the board. The BMC firmware is responsible for sensor data sampling and recording in shared registers. The host driver reads the sensor data from these shared registers and exposes them to users as hwmon interfaces.h]hX This driver adds the temperature, voltage, current and power reading support for the Intel MAX 10 Board Management Controller (BMC) chip. The BMC chip is integrated in some Intel Programmable Acceleration Cards (PAC). It connects to a set of sensor chips to monitor the sensor data of different components on the board. The BMC firmware is responsible for sensor data sampling and recording in shared registers. The host driver reads the sensor data from these shared registers and exposes them to users as hwmon interfaces.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj>hhubh)}(hXThe BMC chip is implemented using the Intel MAX 10 CPLD. It could be reprogramed to some variants in order to support different Intel PACs. The driver is designed to be able to distinguish between the variants, but now it only supports the BMC for Intel PAC N3000.h]hXThe BMC chip is implemented using the Intel MAX 10 CPLD. It could be reprogramed to some variants in order to support different Intel PACs. The driver is designed to be able to distinguish between the variants, but now it only supports the BMC for Intel PAC N3000.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj>hhubeh}(h] descriptionah ]h"] descriptionah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSysfs attributesh]hSysfs attributes}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshhhhhK"ubh)}(h'The following attributes are supported:h]h'The following attributes are supported:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjshhubh)}(hhh]h)}(h&Intel MAX 10 BMC for Intel PAC N3000: h]h)}(h%Intel MAX 10 BMC for Intel PAC N3000:h]h%Intel MAX 10 BMC for Intel PAC N3000:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubah}(h]h ]h"]h$]h&]j-uh1hhhhK&hjshhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK7uh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h tempX_inputh]h tempX_input}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h7Temperature of the component (specified by tempX_label)h]h7Temperature of the component (specified by tempX_label)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h tempX_maxh]h tempX_max}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h-Temperature maximum setpoint of the componenth]h-Temperature maximum setpoint of the component}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h tempX_crith]h tempX_crit}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjNubah}(h]h ]h"]h$]h&]uh1jhjKubj)}(hhh]h)}(h.Temperature critical setpoint of the componenth]h.Temperature critical setpoint of the component}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjeubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(htempX_max_hysth]htempX_max_hyst}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h3Hysteresis for temperature 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by inX_label)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h in0_labelh]h in0_label}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h"QSFP0 Supply Voltage"h]h“QSFP0 Supply Voltage”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h in1_labelh]h in1_label}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h"QSFP1 Supply Voltage"h]h“QSFP1 Supply Voltage”}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h in2_labelh]h in2_label}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjPubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(h"FPGA Core Voltage"h]h“FPGA Core Voltage”}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjgubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h in3_labelh]h in3_label}(hjhhhNhNubah}(h]h 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citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.