sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/gpu/zynqmpmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/pt_BR/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h!SPDX-License-Identifier: GPL-2.0+h]h!SPDX-License-Identifier: GPL-2.0+}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh8/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp.rsthKubhsection)}(hhh](htitle)}(h/Xilinx ZynqMP Ultrascale+ DisplayPort Subsystemh]h/Xilinx ZynqMP Ultrascale+ DisplayPort Subsystem}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThis subsystem handles DisplayPort video and audio output on the ZynqMP. It supports in-memory framebuffers with the DisplayPort DMA controller (xilinx-dpdma), as well as "live" video and audio from the programmable logic (PL). This subsystem can perform several transformations, including color space conversion, alpha blending, and audio mixing, although not all features are currently supported.h]hXThis subsystem handles DisplayPort video and audio output on the ZynqMP. It supports in-memory framebuffers with the DisplayPort DMA controller (xilinx-dpdma), as well as “live” video and audio from the programmable logic (PL). This subsystem can perform several transformations, including color space conversion, alpha blending, and audio mixing, although not all features are currently supported.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hdebugfsh]hdebugfs}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hTo support debugging and compliance testing, several test modes can be enabled though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/ control the DisplayPort test modes:h]hTo support debugging and compliance testing, several test modes can be enabled though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/ control the DisplayPort test modes:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hXactive: Writing a 1 to this file will activate test mode, and writing a 0 will deactivate test mode. Writing a 1 or 0 when the test mode is already active/inactive will re-activate/re-deactivate test mode. When test mode is inactive, changes made to other files will have no (immediate) effect, although the settings will be saved for when test mode is activated. When test mode is active, changes made to other files will apply immediately. h](hterm)}(hactive:h]hactive:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubh definition)}(hhh]h)}(hXWriting a 1 to this file will activate test mode, and writing a 0 will deactivate test mode. Writing a 1 or 0 when the test mode is already active/inactive will re-activate/re-deactivate test mode. When test mode is inactive, changes made to other files will have no (immediate) effect, although the settings will be saved for when test mode is activated. When test mode is active, changes made to other files will apply immediately.h]hXWriting a 1 to this file will activate test mode, and writing a 0 will deactivate test mode. Writing a 1 or 0 when the test mode is already active/inactive will re-activate/re-deactivate test mode. When test mode is inactive, changes made to other files will have no (immediate) effect, although the settings will be saved for when test mode is activated. When test mode is active, changes made to other files will apply immediately.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj)ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(h"custom: Custom test pattern value h](j)}(hcustom:h]hcustom:}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjFubj()}(hhh]h)}(hCustom test pattern valueh]hCustom test pattern value}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjXubah}(h]h ]h"]h$]h&]uh1j'hjFubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hYdownspread: Enable/disable clock downspreading (spread-spectrum clocking) by writing 1/0 h](j)}(h downspread:h]h downspread:}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK#hjuubj()}(hhh]h)}(hLEnable/disable clock downspreading (spread-spectrum clocking) by writing 1/0h]hLEnable/disable clock downspreading (spread-spectrum clocking) by writing 1/0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1j'hjuubeh}(h]h ]h"]h$]h&]uh1jhhhK#hjhhubj)}(h*enhanced: Enable/disable enhanced framing h](j)}(h enhanced:h]h enhanced:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK&hjubj()}(hhh]h)}(hEnable/disable enhanced framingh]hEnable/disable enhanced framing}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhhhK&hjhhubj)}(hignore_aux_errors: Ignore AUX errors when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active) and affect all AUX transfers. h](j)}(hignore_aux_errors:h]hignore_aux_errors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK+hjubj()}(hhh]h)}(hIgnore AUX errors when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active) and affect all AUX transfers.h]hIgnore AUX errors when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active) and affect all AUX transfers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhhhK+hjhhubj)}(hignore_hpd: Ignore hotplug events (such as cable removals or monitor link retraining requests) when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active). h](j)}(h ignore_hpd:h]h ignore_hpd:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK0hjubj()}(hhh]h)}(hIgnore hotplug events (such as cable removals or monitor link retraining requests) when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active).h]hIgnore hotplug events (such as cable removals or monitor link retraining requests) when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhhhK0hjhhubj)}(hIlaneX_preemphasis: Preemphasis from 0 (lowest) to 2 (highest) for lane X h](j)}(hlaneX_preemphasis:h]hlaneX_preemphasis:}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK3hj1ubj()}(hhh]h)}(h5Preemphasis from 0 (lowest) to 2 (highest) for lane Xh]h5Preemphasis from 0 (lowest) to 2 (highest) for lane X}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjCubah}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ]h"]h$]h&]uh1jhhhK3hjhhubj)}(hElaneX_swing: Voltage swing from 0 (lowest) to 3 (highest) for lane X h](j)}(h laneX_swing:h]h laneX_swing:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK6hj`ubj()}(hhh]h)}(h7Voltage swing from 0 (lowest) to 3 (highest) for lane Xh]h7Voltage swing from 0 (lowest) to 3 (highest) for lane X}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjrubah}(h]h ]h"]h$]h&]uh1j'hj`ubeh}(h]h ]h"]h$]h&]uh1jhhhK6hjhhubj)}(h+lanes: Number of lanes to use (1, 2, or 4) h](j)}(hlanes:h]hlanes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK9hjubj()}(hhh]h)}(h#Number of lanes to use (1, 2, or 4)h]h#Number of lanes to use (1, 2, or 4)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhhhK9hjhhubj)}(hXApattern: Test pattern. May be one of: video Use regular video input symbol-error Symbol error measurement pattern prbs7 Output of the PRBS7 (x^7 + x^6 + 1) polynomial 80bit-custom A custom 80-bit pattern cp2520 HBR2 compliance eye pattern tps1 Link training symbol pattern TPS1 (/D10.2/) tps2 Link training symbol pattern TPS2 tps3 Link training symbol pattern TPS3 (for HBR2) h](j)}(hpattern:h]hpattern:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKThjubj()}(hhh](h)}(hTest pattern. May be one of:h]hTest pattern. May be one of:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhhhKThjhhubj)}(horate: Rate in hertz. One of * 5400000000 (HBR2) * 2700000000 (HBR) * 1620000000 (RBR) h](j)}(hrate:h]hrate:}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK[hjzubj()}(hhh](h)}(hRate in hertz. One ofh]hRate in hertz. One of}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubj)}(h:* 5400000000 (HBR2) * 2700000000 (HBR) * 1620000000 (RBR) h]h bullet_list)}(hhh](h list_item)}(h5400000000 (HBR2)h]h)}(hjh]h5400000000 (HBR2)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h2700000000 (HBR)h]h)}(hjh]h2700000000 (HBR)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h1620000000 (RBR) h]h)}(h1620000000 (RBR)h]h1620000000 (RBR)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet*uh1jhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhhhKYhjubeh}(h]h ]h"]h$]h&]uh1j'hjzubeh}(h]h ]h"]h$]h&]uh1jhhhK[hjhhubeh}(h]h ]h"]h$]h&]uh1j hhhhhhhNubh)}(hGYou can dump the displayport test settings with the following command::h]hFYou can dump the displayport test settings with the following command:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hhhhubh literal_block)}(hfor prop in /sys/kernel/debug/dri/1/DP-1/test/*; do printf '%-17s ' ${prop##*/} if [ ${prop##*/} = custom ]; then hexdump -C $prop | head -1 else cat $prop fi doneh]hfor prop in /sys/kernel/debug/dri/1/DP-1/test/*; do printf '%-17s ' ${prop##*/} if [ ${prop##*/} = custom ]; then hexdump -C $prop | head -1 else cat $prop fi done}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK_hhhhubh)}(h&The output could look something like::h]h%The output could look something like:}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhhubj)}(hXWactive 1 custom 00000000 00 00 00 00 00 00 00 00 00 00 |..........| downspread 0 enhanced 1 ignore_aux_errors 1 ignore_hpd 1 lane0_preemphasis 0 lane0_swing 3 lane1_preemphasis 0 lane1_swing 3 lanes 2 pattern prbs7 rate 1620000000h]hXWactive 1 custom 00000000 00 00 00 00 00 00 00 00 00 00 |..........| downspread 0 enhanced 1 ignore_aux_errors 1 ignore_hpd 1 lane0_preemphasis 0 lane0_swing 3 lane1_preemphasis 0 lane1_swing 3 lanes 2 pattern prbs7 rate 1620000000}hj:sbah}(h]h ]h"]h$]h&]hhuh1jhhhKjhhhhubh)}(hThe recommended test procedure is to connect the board to a monitor, configure test mode, activate test mode, and then disconnect the cable and connect it to your test equipment of choice. For example, one sequence of commands could be::h]hThe recommended test procedure is to connect the board to a monitor, configure test mode, activate test mode, and then disconnect the cable and connect it to your test equipment of choice. For example, one sequence of commands could be:}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhhhhubj)}(hXGecho 1 > /sys/kernel/debug/dri/1/DP-1/test/enhanced echo tps1 > /sys/kernel/debug/dri/1/DP-1/test/pattern echo 1620000000 > /sys/kernel/debug/dri/1/DP-1/test/rate echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_aux_errors echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_hpd echo 1 > /sys/kernel/debug/dri/1/DP-1/test/activeh]hXGecho 1 > /sys/kernel/debug/dri/1/DP-1/test/enhanced echo tps1 > /sys/kernel/debug/dri/1/DP-1/test/pattern echo 1620000000 > /sys/kernel/debug/dri/1/DP-1/test/rate echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_aux_errors echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_hpd echo 1 > /sys/kernel/debug/dri/1/DP-1/test/active}hjVsbah}(h]h ]h"]h$]h&]hhuh1jhhhK}hhhhubh)}(h@at which point the cable could be disconnected from the monitor.h]h@at which point the cable could be disconnected from the monitor.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]debugfsah ]h"]debugfsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Internalsh]h Internals}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhhhhhKubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlezynqmp_dpsub_layer_id (C enum)c.zynqmp_dpsub_layer_idhNtauh1jhjzhhhNhNubhdesc)}(hhh](hdesc_signature)}(hzynqmp_dpsub_layer_idh]hdesc_signature_line)}(henum zynqmp_dpsub_layer_idh](hdesc_sig_keyword)}(henumh]henum}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hzynqmp_dpsub_layer_idh]h desc_sig_name)}(hjh]hzynqmp_dpsub_layer_id}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(hLayer identifierh]hLayer identifier}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK$hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](cenumeh"]h$]h&]domainjobjtypej desctypej noindex noindexentrynocontentsentryuh1jhhhjzhNhNubh container)}(hd**Constants** ``ZYNQMP_DPSUB_LAYER_VID`` Video layer ``ZYNQMP_DPSUB_LAYER_GFX`` Graphics layerh](h)}(h **Constants**h]hstrong)}(hj2h]h Constants}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj0ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK(hj,ubj )}(hhh](j)}(h'``ZYNQMP_DPSUB_LAYER_VID`` Video layer h](j)}(h``ZYNQMP_DPSUB_LAYER_VID``h]hliteral)}(hjSh]hZYNQMP_DPSUB_LAYER_VID}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjQubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK+hjMubj()}(hhh]h)}(h Video layerh]h Video layer}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhK+hjkubah}(h]h ]h"]h$]h&]uh1j'hjMubeh}(h]h ]h"]h$]h&]uh1jhjjhK+hjJubj)}(h)``ZYNQMP_DPSUB_LAYER_GFX`` Graphics layerh](j)}(h``ZYNQMP_DPSUB_LAYER_GFX``h]jV)}(hjh]hZYNQMP_DPSUB_LAYER_GFX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK-hjubj()}(hhh]h)}(hGraphics layerh]hGraphics layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK.hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhK-hjJubeh}(h]h ]h"]h$]h&]uh1j hj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dpsub (C struct)c.zynqmp_dpsubhNtauh1jhjzhhhNhNubj)}(hhh](j)}(h zynqmp_dpsubh]j)}(hstruct zynqmp_dpsubh](j)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(h zynqmp_dpsubh]j)}(hjh]h zynqmp_dpsub}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hZynqMP DisplayPort Subsystemh]hZynqMP DisplayPort Subsystem}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK/hj(hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]j$jj%jCj&jCj'j(j)uh1jhhhjzhNhNubj+)}(hX**Definition**:: struct zynqmp_dpsub { struct device *dev; struct clk *apb_clk; struct clk *vid_clk; bool vid_clk_from_ps; struct clk *aud_clk; bool aud_clk_from_ps; unsigned int connected_ports; bool dma_enabled; struct zynqmp_dpsub_drm *drm; struct drm_bridge *bridge; struct zynqmp_disp *disp; struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; struct zynqmp_dp *dp; unsigned int dma_align; struct zynqmp_dpsub_audio *audio; }; **Members** ``dev`` The physical device ``apb_clk`` The APB clock ``vid_clk`` Video clock ``vid_clk_from_ps`` True of the video clock comes from PS, false from PL ``aud_clk`` Audio clock ``aud_clk_from_ps`` True of the audio clock comes from PS, false from PL ``connected_ports`` Bitmask of connected ports in the device tree ``dma_enabled`` True if the DMA interface is enabled, false if the DPSUB is driven by the live input ``drm`` The DRM/KMS device data ``bridge`` The DP encoder bridge ``disp`` The display controller ``layers`` Video and graphics layers ``dp`` The DisplayPort controller ``dma_align`` DMA alignment constraint (must be a power of 2) ``audio`` DP audio datah](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjKubh:}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK3hjGubj)}(hXstruct zynqmp_dpsub { struct device *dev; struct clk *apb_clk; struct clk *vid_clk; bool vid_clk_from_ps; struct clk *aud_clk; bool aud_clk_from_ps; unsigned int connected_ports; bool dma_enabled; struct zynqmp_dpsub_drm *drm; struct drm_bridge *bridge; struct zynqmp_disp *disp; struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; struct zynqmp_dp *dp; unsigned int dma_align; struct zynqmp_dpsub_audio *audio; };h]hXstruct zynqmp_dpsub { struct device *dev; struct clk *apb_clk; struct clk *vid_clk; bool vid_clk_from_ps; struct clk *aud_clk; bool aud_clk_from_ps; unsigned int connected_ports; bool dma_enabled; struct zynqmp_dpsub_drm *drm; struct drm_bridge *bridge; struct zynqmp_disp *disp; struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; struct zynqmp_dp *dp; unsigned int dma_align; struct zynqmp_dpsub_audio *audio; };}hjhsbah}(h]h ]h"]h$]h&]hhuh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK5hjGubh)}(h **Members**h]j5)}(hjyh]hMembers}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjwubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhKGhjGubj )}(hhh](j)}(h``dev`` The physical device h](j)}(h``dev``h]jV)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK1hjubj()}(hhh]h)}(hThe physical deviceh]hThe physical device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK1hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhK1hjubj)}(h``apb_clk`` The APB clock h](j)}(h ``apb_clk``h]jV)}(hjh]hapb_clk}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK2hjubj()}(hhh]h)}(h The APB clockh]h The APB clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK2hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhK2hjubj)}(h``vid_clk`` Video clock h](j)}(h ``vid_clk``h]jV)}(hj h]hvid_clk}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK3hjubj()}(hhh]h)}(h Video clockh]h Video clock}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK3hj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhK3hjubj)}(hI``vid_clk_from_ps`` True of the video clock comes from PS, false from PL h](j)}(h``vid_clk_from_ps``h]jV)}(hjCh]hvid_clk_from_ps}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjAubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK4hj=ubj()}(hhh]h)}(h4True of the video clock comes from PS, false from PLh]h4True of the video clock comes from PS, false from PL}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhK4hjYubah}(h]h ]h"]h$]h&]uh1j'hj=ubeh}(h]h ]h"]h$]h&]uh1jhjXhK4hjubj)}(h``aud_clk`` Audio clock h](j)}(h ``aud_clk``h]jV)}(hj|h]haud_clk}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjzubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK5hjvubj()}(hhh]h)}(h Audio clockh]h Audio clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK5hjubah}(h]h ]h"]h$]h&]uh1j'hjvubeh}(h]h ]h"]h$]h&]uh1jhjhK5hjubj)}(hI``aud_clk_from_ps`` True of the audio clock comes from PS, false from PL h](j)}(h``aud_clk_from_ps``h]jV)}(hjh]haud_clk_from_ps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK6hjubj()}(hhh]h)}(h4True of the audio clock comes from PS, false from PLh]h4True of the audio clock comes from PS, false from PL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK6hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhK6hjubj)}(hB``connected_ports`` Bitmask of connected ports in the device tree h](j)}(h``connected_ports``h]jV)}(hjh]hconnected_ports}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK7hjubj()}(hhh]h)}(h-Bitmask of connected ports in the device treeh]h-Bitmask of connected ports in the device tree}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK7hj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hK7hjubj)}(he``dma_enabled`` True if the DMA interface is enabled, false if the DPSUB is driven by the live input h](j)}(h``dma_enabled``h]jV)}(hj' h]h dma_enabled}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj% ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK9hj! ubj()}(hhh]h)}(hTTrue if the DMA interface is enabled, false if the DPSUB is driven by the live inputh]hTTrue if the DMA interface is enabled, false if the DPSUB is driven by the live input}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK8hj= ubah}(h]h ]h"]h$]h&]uh1j'hj! ubeh}(h]h ]h"]h$]h&]uh1jhj< hK9hjubj)}(h ``drm`` The DRM/KMS device data h](j)}(h``drm``h]jV)}(hja h]hdrm}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj_ ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK:hj[ ubj()}(hhh]h)}(hThe DRM/KMS device datah]hThe DRM/KMS device data}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv hK:hjw ubah}(h]h ]h"]h$]h&]uh1j'hj[ ubeh}(h]h ]h"]h$]h&]uh1jhjv hK:hjubj)}(h!``bridge`` The DP encoder bridge h](j)}(h ``bridge``h]jV)}(hj h]hbridge}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK;hj ubj()}(hhh]h)}(hThe DP encoder bridgeh]hThe DP encoder bridge}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK;hj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hK;hjubj)}(h ``disp`` The display controller h](j)}(h``disp``h]jV)}(hj h]hdisp}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhKhj? ubj()}(hhh]h)}(hThe DisplayPort controllerh]hThe DisplayPort controller}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ hK>hj[ ubah}(h]h ]h"]h$]h&]uh1j'hj? ubeh}(h]h ]h"]h$]h&]uh1jhjZ hK>hjubj)}(h>``dma_align`` DMA alignment constraint (must be a power of 2) h](j)}(h ``dma_align``h]jV)}(hj~ h]h dma_align}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj| ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK?hjx ubj()}(hhh]h)}(h/DMA alignment constraint (must be a power of 2)h]h/DMA alignment constraint (must be a power of 2)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK?hj ubah}(h]h ]h"]h$]h&]uh1j'hjx ubeh}(h]h ]h"]h$]h&]uh1jhj hK?hjubj)}(h``audio`` DP audio datah](j)}(h ``audio``h]jV)}(hj h]haudio}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK?hj ubj()}(hhh]h)}(h DP audio datah]h DP audio data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK@hj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hK?hjubeh}(h]h ]h"]h$]h&]uh1j hjGubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dpsub_drm (C struct)c.zynqmp_dpsub_drmhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_dpsub_drmh]j)}(hstruct zynqmp_dpsub_drmh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hzynqmp_dpsub_drmh]j)}(hj h]hzynqmp_dpsub_drm}(hj1 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj- ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj)}(hhh]h)}(h)ZynqMP DisplayPort Subsystem DRM/KMS datah]h)ZynqMP DisplayPort Subsystem DRM/KMS data}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhjP hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]j$jj%jk j&jk j'j(j)uh1jhhhjzhNhNubj+)}(hX**Definition**:: struct zynqmp_dpsub_drm { struct zynqmp_dpsub *dpsub; struct drm_device dev; struct drm_plane planes[ZYNQMP_DPSUB_NUM_LAYERS]; struct drm_crtc crtc; struct drm_encoder encoder; }; **Members** ``dpsub`` Backpointer to the DisplayPort subsystem ``dev`` The DRM/KMS device ``planes`` The DRM planes ``crtc`` The DRM CRTC ``encoder`` The dummy DRM encoderh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjs ubh:}(hjs hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhjo ubj)}(hstruct zynqmp_dpsub_drm { struct zynqmp_dpsub *dpsub; struct drm_device dev; struct drm_plane planes[ZYNQMP_DPSUB_NUM_LAYERS]; struct drm_crtc crtc; struct drm_encoder encoder; };h]hstruct zynqmp_dpsub_drm { struct zynqmp_dpsub *dpsub; struct drm_device dev; struct drm_plane planes[ZYNQMP_DPSUB_NUM_LAYERS]; struct drm_crtc crtc; struct drm_encoder encoder; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhjo ubh)}(h **Members**h]j5)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj ubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhK'hjo ubj )}(hhh](j)}(h3``dpsub`` Backpointer to the DisplayPort subsystem h](j)}(h ``dpsub``h]jV)}(hj h]hdpsub}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubj()}(hhh]h)}(h(Backpointer to the DisplayPort subsystemh]h(Backpointer to the DisplayPort subsystem}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h``dev`` The DRM/KMS device h](j)}(h``dev``h]jV)}(hj h]hdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubj()}(hhh]h)}(hThe DRM/KMS deviceh]hThe DRM/KMS device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h``planes`` The DRM planes h](j)}(h ``planes``h]jV)}(hj2 h]hplanes}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj0 ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj, ubj()}(hhh]h)}(hThe DRM planesh]hThe DRM planes}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjG hKhjH ubah}(h]h ]h"]h$]h&]uh1j'hj, ubeh}(h]h ]h"]h$]h&]uh1jhjG hKhj ubj)}(h``crtc`` The DRM CRTC h](j)}(h``crtc``h]jV)}(hjk h]hcrtc}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhji ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhje ubj()}(hhh]h)}(h The DRM CRTCh]h The DRM CRTC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j'hje ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h!``encoder`` The dummy DRM encoderh](j)}(h ``encoder``h]jV)}(hj h]hencoder}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubj()}(hhh]h)}(hThe dummy DRM encoderh]hThe dummy DRM encoder}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubeh}(h]h ]h"]h$]h&]uh1j hjo ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j zynqmp_dpsub_layer_mode (C enum)c.zynqmp_dpsub_layer_modehNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_dpsub_layer_modeh]j)}(henum zynqmp_dpsub_layer_modeh](j)}(hjh]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hzynqmp_dpsub_layer_modeh]j)}(hj h]hzynqmp_dpsub_layer_mode}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj)}(hhh]h)}(h Layer modeh]h Layer mode}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKEhj= hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jenumeh"]h$]h&]j$jj%jX j&jX j'j(j)uh1jhhhjzhNhNubj+)}(hx**Constants** ``ZYNQMP_DPSUB_LAYER_NONLIVE`` non-live (memory) mode ``ZYNQMP_DPSUB_LAYER_LIVE`` live (stream) modeh](h)}(h **Constants**h]j5)}(hjb h]h Constants}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj` ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKIhj\ ubj )}(hhh](j)}(h6``ZYNQMP_DPSUB_LAYER_NONLIVE`` non-live (memory) mode h](j)}(h``ZYNQMP_DPSUB_LAYER_NONLIVE``h]jV)}(hj h]hZYNQMP_DPSUB_LAYER_NONLIVE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKLhj{ ubj()}(hhh]h)}(hnon-live (memory) modeh]hnon-live (memory) mode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKLhj ubah}(h]h ]h"]h$]h&]uh1j'hj{ ubeh}(h]h ]h"]h$]h&]uh1jhj hKLhjx ubj)}(h.``ZYNQMP_DPSUB_LAYER_LIVE`` live (stream) modeh](j)}(h``ZYNQMP_DPSUB_LAYER_LIVE``h]jV)}(hj h]hZYNQMP_DPSUB_LAYER_LIVE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKNhj ubj()}(hhh]h)}(hlive (stream) modeh]hlive (stream) mode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKOhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKNhjx ubeh}(h]h ]h"]h$]h&]uh1j hj\ ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_disp_format (C struct)c.zynqmp_disp_formathNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_disp_formath]j)}(hstruct zynqmp_disp_formath](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKTubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj!hKTubj)}(hzynqmp_disp_formath]j)}(hjh]hzynqmp_disp_format}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj!hKTubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj!hKTubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj!hKThj hhubj)}(hhh]h)}(h$Display subsystem format informationh]h$Display subsystem format information}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKOhjShhubah}(h]h ]h"]h$]h&]uh1jhj hhhj!hKTubeh}(h]h ](jstructeh"]h$]h&]j$jj%jnj&jnj'j(j)uh1jhhhjzhNhNubj+)}(hXy**Definition**:: struct zynqmp_disp_format { u32 drm_fmt; u32 bus_fmt; u32 buf_fmt; bool swap; const u32 *sf; }; **Members** ``drm_fmt`` DRM format (4CC) ``bus_fmt`` Media bus format ``buf_fmt`` AV buffer format ``swap`` Flag to swap R & B for RGB formats, and U & V for YUV formats ``sf`` Scaling factors for color componentsh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjvubh:}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKShjrubj)}(hsstruct zynqmp_disp_format { u32 drm_fmt; u32 bus_fmt; u32 buf_fmt; bool swap; const u32 *sf; };h]hsstruct zynqmp_disp_format { u32 drm_fmt; u32 bus_fmt; u32 buf_fmt; bool swap; const u32 *sf; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKUhjrubh)}(h **Members**h]j5)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK]hjrubj )}(hhh](j)}(h``drm_fmt`` DRM format (4CC) h](j)}(h ``drm_fmt``h]jV)}(hjh]hdrm_fmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKQhjubj()}(hhh]h)}(hDRM format (4CC)h]hDRM format (4CC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKQhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKQhjubj)}(h``bus_fmt`` Media bus format h](j)}(h ``bus_fmt``h]jV)}(hjh]hbus_fmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKRhjubj()}(hhh]h)}(hMedia bus formath]hMedia bus format}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKRhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKRhjubj)}(h``buf_fmt`` AV buffer format h](j)}(h ``buf_fmt``h]jV)}(hj5h]hbuf_fmt}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj3ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKShj/ubj()}(hhh]h)}(hAV buffer formath]hAV buffer format}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhKShjKubah}(h]h ]h"]h$]h&]uh1j'hj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhKShjubj)}(hG``swap`` Flag to swap R & B for RGB formats, and U & V for YUV formats h](j)}(h``swap``h]jV)}(hjnh]hswap}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjlubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKThjhubj()}(hhh]h)}(h=Flag to swap R & B for RGB formats, and U & V for YUV formatsh]h=Flag to swap R & B for RGB formats, and U & V for YUV formats}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKThjubah}(h]h ]h"]h$]h&]uh1j'hjhubeh}(h]h ]h"]h$]h&]uh1jhjhKThjubj)}(h+``sf`` Scaling factors for color componentsh](j)}(h``sf``h]jV)}(hjh]hsf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKThjubj()}(hhh]h)}(h$Scaling factors for color componentsh]h$Scaling factors for color components}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKUhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKThjubeh}(h]h ]h"]h$]h&]uh1j hjrubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j zynqmp_disp_layer_dma (C struct)c.zynqmp_disp_layer_dmahNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_disp_layer_dmah]j)}(hstruct zynqmp_disp_layer_dmah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK[ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhK[ubj)}(hzynqmp_disp_layer_dmah]j)}(hjh]hzynqmp_disp_layer_dma}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhK[ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhK[ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhK[hjhhubj)}(hhh]h)}(h)DMA channel for one data plane of a layerh]h)DMA channel for one data plane of a layer}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK_hj@hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhK[ubeh}(h]h ](jstructeh"]h$]h&]j$jj%j[j&j[j'j(j)uh1jhhhjzhNhNubj+)}(hX!**Definition**:: struct zynqmp_disp_layer_dma { struct dma_chan *chan; struct dma_interleaved_template xt; struct data_chunk sgl; }; **Members** ``chan`` DMA channel ``xt`` Interleaved DMA descriptor template ``sgl`` Data chunk for dma_interleaved_templateh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjcubh:}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKchj_ubj)}(hstruct zynqmp_disp_layer_dma { struct dma_chan *chan; struct dma_interleaved_template xt; struct data_chunk sgl; };h]hstruct zynqmp_disp_layer_dma { struct dma_chan *chan; struct dma_interleaved_template xt; struct data_chunk sgl; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKehj_ubh)}(h **Members**h]j5)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKkhj_ubj )}(hhh](j)}(h``chan`` DMA channel h](j)}(h``chan``h]jV)}(hjh]hchan}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKahjubj()}(hhh]h)}(h DMA channelh]h DMA channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKahjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKahjubj)}(h+``xt`` Interleaved DMA descriptor template h](j)}(h``xt``h]jV)}(hjh]hxt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKbhjubj()}(hhh]h)}(h#Interleaved DMA descriptor templateh]h#Interleaved DMA descriptor template}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKbhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKbhjubj)}(h/``sgl`` Data chunk for dma_interleaved_templateh](j)}(h``sgl``h]jV)}(hj"h]hsgl}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKbhjubj()}(hhh]h)}(h'Data chunk for dma_interleaved_templateh]h'Data chunk for dma_interleaved_template}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKchj8ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj7hKbhjubeh}(h]h ]h"]h$]h&]uh1j hj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!zynqmp_disp_layer_info (C struct)c.zynqmp_disp_layer_infohNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_disp_layer_infoh]j)}(hstruct zynqmp_disp_layer_infoh](j)}(hjh]hstruct}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKiubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxhhhjhKiubj)}(hzynqmp_disp_layer_infoh]j)}(hjvh]hzynqmp_disp_layer_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjxhhhjhKiubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjthhhjhKiubah}(h]joah ](jjeh"]h$]h&]jj)jhuh1jhjhKihjqhhubj)}(hhh]h)}(hStatic layer informationh]hStatic layer information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKkhjhhubah}(h]h ]h"]h$]h&]uh1jhjqhhhjhKiubeh}(h]h ](jstructeh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(hXE**Definition**:: struct zynqmp_disp_layer_info { const struct zynqmp_disp_format *formats; unsigned int num_formats; unsigned int num_channels; }; **Members** ``formats`` Array of supported formats ``num_formats`` Number of formats in **formats** array ``num_channels`` Number of DMA channelsh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKohjubj)}(hstruct zynqmp_disp_layer_info { const struct zynqmp_disp_format *formats; unsigned int num_formats; unsigned int num_channels; };h]hstruct zynqmp_disp_layer_info { const struct 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]h"]h$]h&]uh1jUhjbubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKnhj^ubj()}(hhh]h)}(h&Number of formats in **formats** arrayh](hNumber of formats in }(hj}hhhNhNubj5)}(h **formats**h]hformats}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj}ubh array}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjyhKnhjzubah}(h]h ]h"]h$]h&]uh1j'hj^ubeh}(h]h ]h"]h$]h&]uh1jhjyhKnhj"ubj)}(h'``num_channels`` Number of DMA channelsh](j)}(h``num_channels``h]jV)}(hjh]h num_channels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKnhjubj()}(hhh]h)}(hNumber of DMA channelsh]hNumber of DMA channels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKohjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKnhj"ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_disp_layer (C struct)c.zynqmp_disp_layerhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_disp_layerh]j)}(hstruct zynqmp_disp_layerh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKuubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKuubj)}(hzynqmp_disp_layerh]j)}(hjh]hzynqmp_disp_layer}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKuubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhKuubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKuhjhhubj)}(hhh]h)}(h Display layerh]h Display layer}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKwhjHhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKuubeh}(h]h ](jstructeh"]h$]h&]j$jj%jcj&jcj'j(j)uh1jhhhjzhNhNubj+)}(hX**Definition**:: struct zynqmp_disp_layer { enum zynqmp_dpsub_layer_id id; struct zynqmp_disp *disp; const struct zynqmp_disp_layer_info *info; struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; const struct zynqmp_disp_format *disp_fmt; const struct drm_format_info *drm_fmt; enum zynqmp_dpsub_layer_mode mode; }; **Members** ``id`` Layer ID ``disp`` Back pointer to struct zynqmp_disp ``info`` Static layer information ``dmas`` DMA channels ``disp_fmt`` Current format information ``drm_fmt`` Current DRM format information ``mode`` Current operation modeh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjkubh:}(hjkhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK{hjgubj)}(hXUstruct zynqmp_disp_layer { enum zynqmp_dpsub_layer_id id; struct zynqmp_disp *disp; const struct zynqmp_disp_layer_info *info; struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; const struct zynqmp_disp_format *disp_fmt; const struct drm_format_info *drm_fmt; enum zynqmp_dpsub_layer_mode mode; };h]hXUstruct zynqmp_disp_layer { enum zynqmp_dpsub_layer_id id; struct zynqmp_disp *disp; const struct zynqmp_disp_layer_info *info; struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; const struct zynqmp_disp_format *disp_fmt; const struct drm_format_info *drm_fmt; enum zynqmp_dpsub_layer_mode mode; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK}hjgubh)}(h **Members**h]j5)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjgubj )}(hhh](j)}(h``id`` Layer ID h](j)}(h``id``h]jV)}(hjh]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKyhjubj()}(hhh]h)}(hLayer IDh]hLayer ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKyhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKyhjubj)}(h,``disp`` Back pointer to struct zynqmp_disp h](j)}(h``disp``h]jV)}(hjh]hdisp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKzhjubj()}(hhh]h)}(h"Back pointer to struct zynqmp_disph]h"Back pointer to struct zynqmp_disp}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKzhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKzhjubj)}(h"``info`` Static layer information h](j)}(h``info``h]jV)}(hj*h]hinfo}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj(ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK{hj$ubj()}(hhh]h)}(hStatic layer informationh]hStatic layer information}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hK{hj@ubah}(h]h ]h"]h$]h&]uh1j'hj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hK{hjubj)}(h``dmas`` DMA channels h](j)}(h``dmas``h]jV)}(hjch]hdmas}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjaubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK|hj]ubj()}(hhh]h)}(h DMA channelsh]h DMA channels}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhK|hjyubah}(h]h ]h"]h$]h&]uh1j'hj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhK|hjubj)}(h(``disp_fmt`` Current format information h](j)}(h ``disp_fmt``h]jV)}(hjh]hdisp_fmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK}hjubj()}(hhh]h)}(hCurrent format informationh]hCurrent format information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK}hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhK}hjubj)}(h+``drm_fmt`` Current DRM format information h](j)}(h ``drm_fmt``h]jV)}(hjh]hdrm_fmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK~hjubj()}(hhh]h)}(hCurrent DRM format informationh]hCurrent DRM format information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK~hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhK~hjubj)}(h``mode`` Current operation modeh](j)}(h``mode``h]jV)}(hjh]hmode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK~hjubj()}(hhh]h)}(hCurrent operation modeh]hCurrent operation mode}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhj$ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj#hK~hjubeh}(h]h ]h"]h$]h&]uh1j hjgubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_disp (C struct) c.zynqmp_disphNtauh1jhjzhhhNhNubj)}(hhh](j)}(h zynqmp_disph]j)}(hstruct zynqmp_disph](j)}(hjh]hstruct}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhhjuhKubj)}(h zynqmp_disph]j)}(hjbh]h zynqmp_disp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjdhhhjuhKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj`hhhjuhKubah}(h]j[ah ](jjeh"]h$]h&]jj)jhuh1jhjuhKhj]hhubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhj]hhhjuhKubeh}(h]h ](jstructeh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(hX**Definition**:: struct zynqmp_disp { struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *blend; void __iomem *avbuf; struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS]; }; **Members** ``dev`` Device structure ``dpsub`` Display subsystem ``blend`` Register I/O base address for the blender ``avbuf`` Register I/O base address for the audio/video buffer manager ``layers`` Layers (planes)h](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubj)}(hstruct zynqmp_disp { struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *blend; void __iomem *avbuf; struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS]; };h]hstruct zynqmp_disp { struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *blend; void __iomem *avbuf; struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS]; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubh)}(h **Members**h]j5)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubj )}(hhh](j)}(h``dev`` Device structure h](j)}(h``dev``h]jV)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubj()}(hhh]h)}(hDevice structureh]hDevice structure}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hKhj-ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj,hKhjubj)}(h``dpsub`` Display subsystem h](j)}(h ``dpsub``h]jV)}(hjPh]hdpsub}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjJubj()}(hhh]h)}(hDisplay subsystemh]hDisplay subsystem}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehKhjfubah}(h]h ]h"]h$]h&]uh1j'hjJubeh}(h]h ]h"]h$]h&]uh1jhjehKhjubj)}(h4``blend`` Register I/O base address for the blender h](j)}(h ``blend``h]jV)}(hjh]hblend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubj()}(hhh]h)}(h)Register I/O base address for the blenderh]h)Register I/O base address for the blender}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hG``avbuf`` Register I/O base address for the audio/video buffer manager h](j)}(h ``avbuf``h]jV)}(hjh]havbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubj()}(hhh]h)}(hubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMhjZubah}(h]h ]h"]h$]h&]uh1j'hj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhMhj;ubah}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j5)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj}ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hjubh)}(h-Enable all (video and audio) buffer channels.h]h-Enable all (video and audio) buffer channels.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/zynqmp_disp_avbuf_disable_channels (C function)$c.zynqmp_disp_avbuf_disable_channelshNtauh1jhjzhhhNhNubj)}(hhh](j)}(hBvoid zynqmp_disp_avbuf_disable_channels (struct zynqmp_disp *disp)h]j)}(hAvoid zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp)h](jV)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM"ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM"ubj)}(h"zynqmp_disp_avbuf_disable_channelsh]j)}(h"zynqmp_disp_avbuf_disable_channelsh]h"zynqmp_disp_avbuf_disable_channels}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM"ubj)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj!modnameN classnameNjj)}j]j)}jjsb$c.zynqmp_disp_avbuf_disable_channelsasbuh1hhjubj)}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdisph]hdisp}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM"ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhM"ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM"hjhhubj)}(hhh]h)}(hDisable buffer channelsh]hDisable buffer channels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM"hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM"ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Disable all (video and audio) buffer channels.h](h)}(h**Parameters**h]j5)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM&hjubj )}(hhh]j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hjh]hstruct zynqmp_disp *disp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM#hjubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM#hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM#hjubah}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j5)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM%hjubh)}(h.Disable all (video and audio) buffer channels.h]h.Disable all (video and audio) buffer channels.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM$hjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_avbuf_enable_audio (C function) c.zynqmp_disp_avbuf_enable_audiohNtauh1jhjzhhhNhNubj)}(hhh](j)}(h>void zynqmp_disp_avbuf_enable_audio (struct zynqmp_disp *disp)h]j)}(h=void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp)h](jV)}(hvoidh]hvoid}(hjE hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjA hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM1ubj)}(h h]h }(hjT hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA hhhjS hM1ubj)}(hzynqmp_disp_avbuf_enable_audioh]j)}(hzynqmp_disp_avbuf_enable_audioh]hzynqmp_disp_avbuf_enable_audio}(hjf hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjb ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjA hhhjS hM1ubj)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jjh sb c.zynqmp_disp_avbuf_enable_audioasbuh1hhj~ ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ ubj)}(hdisph]hdisp}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjz ubah}(h]h ]h"]h$]h&]hhuh1jhjA hhhjS hM1ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj= hhhjS hM1ubah}(h]j8 ah ](jjeh"]h$]h&]jj)jhuh1jhjS hM1hj: hhubj)}(hhh]h)}(h Enable audioh]h Enable audio}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM1hj!hhubah}(h]h ]h"]h$]h&]uh1jhj: hhhjS hM1ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j!j&j!j'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Enable all audio buffers with a non-live (memory) source.h](h)}(h**Parameters**h]j5)}(hj'!h]h Parameters}(hj)!hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj%!ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM5hj!!ubj )}(hhh]j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hjF!h]hstruct zynqmp_disp *disp}(hjH!hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjD!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM2hj@!ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj_!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[!hM2hj\!ubah}(h]h ]h"]h$]h&]uh1j'hj@!ubeh}(h]h ]h"]h$]h&]uh1jhj[!hM2hj=!ubah}(h]h ]h"]h$]h&]uh1j hj!!ubh)}(h**Description**h]j5)}(hj!h]h Description}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj!ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM4hj!!ubh)}(h9Enable all audio buffers with a non-live (memory) source.h]h9Enable all audio buffers with a non-live (memory) source.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM3hj!!ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,zynqmp_disp_avbuf_disable_audio (C function)!c.zynqmp_disp_avbuf_disable_audiohNtauh1jhjzhhhNhNubj)}(hhh](j)}(h?void zynqmp_disp_avbuf_disable_audio (struct zynqmp_disp *disp)h]j)}(h>void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp)h](jV)}(hvoidh]hvoid}(hj!hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj!hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMBubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!hhhj!hMBubj)}(hzynqmp_disp_avbuf_disable_audioh]j)}(hzynqmp_disp_avbuf_disable_audioh]hzynqmp_disp_avbuf_disable_audio}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj!hhhj!hMBubj)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj!"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj#"modnameN classnameNjj)}j]j)}jj!sb!c.zynqmp_disp_avbuf_disable_audioasbuh1hhj!ubj)}(h h]h }(hjA"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(hjh]h*}(hjO"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(hdisph]hdisp}(hj\"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj!ubah}(h]h ]h"]h$]h&]hhuh1jhj!hhhj!hMBubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj!hhhj!hMBubah}(h]j!ah ](jjeh"]h$]h&]jj)jhuh1jhj!hMBhj!hhubj)}(hhh]h)}(h Disable audioh]h Disable audio}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMBhj"hhubah}(h]h ]h"]h$]h&]uh1jhj!hhhj!hMBubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j"j&j"j'j(j)uh1jhhhjzhNhNubj+)}(hn**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Disable all audio buffers.h](h)}(h**Parameters**h]j5)}(hj"h]h Parameters}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj"ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMFhj"ubj )}(hhh]j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj"h]hstruct zynqmp_disp *disp}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj"ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMChj"ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMChj"ubah}(h]h ]h"]h$]h&]uh1j'hj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hMChj"ubah}(h]h ]h"]h$]h&]uh1j hj"ubh)}(h**Description**h]j5)}(hj#h]h Description}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj#ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMEhj"ubh)}(hDisable all audio buffers.h]hDisable all audio buffers.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMDhj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_avbuf_enable_video (C function) c.zynqmp_disp_avbuf_enable_videohNtauh1jhjzhhhNhNubj)}(hhh](j)}(h_void zynqmp_disp_avbuf_enable_video (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h^void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jV)}(hvoidh]hvoid}(hjG#hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjC#hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMSubj)}(h h]h }(hjV#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjC#hhhjU#hMSubj)}(hzynqmp_disp_avbuf_enable_videoh]j)}(hzynqmp_disp_avbuf_enable_videoh]hzynqmp_disp_avbuf_enable_video}(hjh#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjd#ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjC#hhhjU#hMSubj)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj#modnameN classnameNjj)}j]j)}jjj#sb c.zynqmp_disp_avbuf_enable_videoasbuh1hhj#ubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hdisph]hdisp}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj|#ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj$modnameN classnameNjj)}j]j# c.zynqmp_disp_avbuf_enable_videoasbuh1hhj#ubj)}(h h]h }(hj2$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hjh]h*}(hj@$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hlayerh]hlayer}(hjM$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj|#ubeh}(h]h ]h"]h$]h&]hhuh1jhjC#hhhjU#hMSubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj?#hhhjU#hMSubah}(h]j:#ah ](jjeh"]h$]h&]jj)jhuh1jhjU#hMShj<#hhubj)}(hhh]h)}(hEnable a video layerh]hEnable a video layer}(hjw$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMShjt$hhubah}(h]h ]h"]h$]h&]uh1jhj<#hhhjU#hMSubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j$j&j$j'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer **Description** Enable the video/graphics buffer for **layer**.h](h)}(h**Parameters**h]j5)}(hj$h]h Parameters}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj$ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMWhj$ubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj$h]hstruct zynqmp_disp *disp}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMThj$ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMThj$ubah}(h]h ]h"]h$]h&]uh1j'hj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hMThj$ubj)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj$h]hstruct zynqmp_disp_layer *layer}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMUhj$ubj()}(hhh]h)}(h The layerh]h The layer}(hj %hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMUhj%ubah}(h]h ]h"]h$]h&]uh1j'hj$ubeh}(h]h ]h"]h$]h&]uh1jhj%hMUhj$ubeh}(h]h ]h"]h$]h&]uh1j hj$ubh)}(h**Description**h]j5)}(hj,%h]h Description}(hj.%hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj*%ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMWhj$ubh)}(h/Enable the video/graphics buffer for **layer**.h](h%Enable the video/graphics buffer for }(hjB%hhhNhNubj5)}(h **layer**h]hlayer}(hjJ%hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjB%ubh.}(hjB%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMVhj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,zynqmp_disp_avbuf_disable_video (C function)!c.zynqmp_disp_avbuf_disable_videohNtauh1jhjzhhhNhNubj)}(hhh](j)}(h`void zynqmp_disp_avbuf_disable_video (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h_void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jV)}(hvoidh]hvoid}(hj%hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj%hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMqubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhhj%hMqubj)}(hzynqmp_disp_avbuf_disable_videoh]j)}(hzynqmp_disp_avbuf_disable_videoh]hzynqmp_disp_avbuf_disable_video}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj%hhhj%hMqubj)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj%modnameN classnameNjj)}j]j)}jj%sb!c.zynqmp_disp_avbuf_disable_videoasbuh1hhj%ubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(hjh]h*}(hj &hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(hdisph]hdisp}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj2&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.&ubj)}(h h]h }(hj?&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.&ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjP&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjM&ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjR&modnameN classnameNjj)}j]j%!c.zynqmp_disp_avbuf_disable_videoasbuh1hhj.&ubj)}(h h]h }(hjn&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.&ubj)}(hjh]h*}(hj|&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.&ubj)}(hlayerh]hlayer}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%ubeh}(h]h ]h"]h$]h&]hhuh1jhj%hhhj%hMqubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj{%hhhj%hMqubah}(h]jv%ah ](jjeh"]h$]h&]jj)jhuh1jhj%hMqhjx%hhubj)}(hhh]h)}(hDisable a video layerh]hDisable a video layer}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMqhj&hhubah}(h]h ]h"]h$]h&]uh1jhjx%hhhj%hMqubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j&j&j&j'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer **Description** Disable the video/graphics buffer for **layer**.h](h)}(h**Parameters**h]j5)}(hj&h]h Parameters}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj&ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMuhj&ubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj&h]hstruct zynqmp_disp *disp}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj&ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMrhj&ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj 'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 'hMrhj 'ubah}(h]h ]h"]h$]h&]uh1j'hj&ubeh}(h]h ]h"]h$]h&]uh1jhj 'hMrhj&ubj)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj-'h]hstruct zynqmp_disp_layer *layer}(hj/'hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj+'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMshj''ubj()}(hhh]h)}(h The layerh]h The layer}(hjF'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB'hMshjC'ubah}(h]h ]h"]h$]h&]uh1j'hj''ubeh}(h]h ]h"]h$]h&]uh1jhjB'hMshj&ubeh}(h]h ]h"]h$]h&]uh1j hj&ubh)}(h**Description**h]j5)}(hjh'h]h Description}(hjj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjf'ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMuhj&ubh)}(h0Disable the video/graphics buffer for **layer**.h](h&Disable the video/graphics buffer for }(hj~'hhhNhNubj5)}(h **layer**h]hlayer}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj~'ubh.}(hj~'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMthj&ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_disp_avbuf_enable (C function)c.zynqmp_disp_avbuf_enablehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h8void zynqmp_disp_avbuf_enable (struct zynqmp_disp *disp)h]j)}(h7void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp)h](jV)}(hvoidh]hvoid}(hj'hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj'hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'hhhj'hMubj)}(hzynqmp_disp_avbuf_enableh]j)}(hzynqmp_disp_avbuf_enableh]hzynqmp_disp_avbuf_enable}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj'hhhj'hMubj)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj)}(h h]h }(hj (hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj(modnameN classnameNjj)}j]j)}jj'sbc.zynqmp_disp_avbuf_enableasbuh1hhj'ubj)}(h h]h }(hj:(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj)}(hjh]h*}(hjH(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj)}(hdisph]hdisp}(hjU(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj'ubah}(h]h ]h"]h$]h&]hhuh1jhj'hhhj'hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj'hhhj'hMubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1jhj'hMhj'hhubj)}(hhh]h)}(hEnable the video pipeh]hEnable the video pipe}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj|(hhubah}(h]h ]h"]h$]h&]uh1jhj'hhhj'hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j(j&j(j'j(j)uh1jhhhjzhNhNubj+)}(hs**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** De-assert the video pipe reset.h](h)}(h**Parameters**h]j5)}(hj(h]h Parameters}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj(ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj(ubj )}(hhh]j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj(h]hstruct zynqmp_disp *disp}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj(ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj(ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hMhj(ubah}(h]h ]h"]h$]h&]uh1j'hj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhj(ubah}(h]h ]h"]h$]h&]uh1j hj(ubh)}(h**Description**h]j5)}(hj(h]h Description}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj(ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj(ubh)}(hDe-assert the video pipe reset.h]hDe-assert the video pipe reset.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&zynqmp_disp_avbuf_disable (C function)c.zynqmp_disp_avbuf_disablehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h9void zynqmp_disp_avbuf_disable (struct zynqmp_disp *disp)h]j)}(h8void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp)h](jV)}(hvoidh]hvoid}(hj@)hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj<)hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hjO)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<)hhhjN)hMubj)}(hzynqmp_disp_avbuf_disableh]j)}(hzynqmp_disp_avbuf_disableh]hzynqmp_disp_avbuf_disable}(hja)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj])ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj<)hhhjN)hMubj)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj})hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy)ubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy)ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj)modnameN classnameNjj)}j]j)}jjc)sbc.zynqmp_disp_avbuf_disableasbuh1hhjy)ubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy)ubj)}(hjh]h*}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy)ubj)}(hdisph]hdisp}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy)ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhju)ubah}(h]h ]h"]h$]h&]hhuh1jhj<)hhhjN)hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj8)hhhjN)hMubah}(h]j3)ah ](jjeh"]h$]h&]jj)jhuh1jhjN)hMhj5)hhubj)}(hhh]h)}(hDisable the video pipeh]hDisable the video pipe}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj)hhubah}(h]h ]h"]h$]h&]uh1jhj5)hhhjN)hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j*j&j*j'j(j)uh1jhhhjzhNhNubj+)}(hp**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Assert the video pipe reset.h](h)}(h**Parameters**h]j5)}(hj"*h]h Parameters}(hj$*hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj *ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj*ubj )}(hhh]j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hjA*h]hstruct zynqmp_disp *disp}(hjC*hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj?*ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj;*ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjZ*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV*hMhjW*ubah}(h]h ]h"]h$]h&]uh1j'hj;*ubeh}(h]h ]h"]h$]h&]uh1jhjV*hMhj8*ubah}(h]h ]h"]h$]h&]uh1j hj*ubh)}(h**Description**h]j5)}(hj|*h]h Description}(hj~*hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjz*ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj*ubh)}(hAssert the video pipe reset.h]hAssert the video pipe reset.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j0zynqmp_disp_blend_set_output_format (C function)%c.zynqmp_disp_blend_set_output_formathNtauh1jhjzhhhNhNubj)}(hhh](j)}(hdvoid zynqmp_disp_blend_set_output_format (struct zynqmp_disp *disp, enum zynqmp_dpsub_format format)h]j)}(hcvoid zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp, enum zynqmp_dpsub_format format)h](jV)}(hvoidh]hvoid}(hj*hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj*hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*hhhj*hMubj)}(h#zynqmp_disp_blend_set_output_formath]j)}(h#zynqmp_disp_blend_set_output_formath]h#zynqmp_disp_blend_set_output_format}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj*hhhj*hMubj)}(h;(struct zynqmp_disp *disp, enum zynqmp_dpsub_format format)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj)}(h h]h }(hj +hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj+modnameN classnameNjj)}j]j)}jj*sb%c.zynqmp_disp_blend_set_output_formatasbuh1hhj*ubj)}(h h]h }(hj<+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj)}(hjh]h*}(hjJ+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj)}(hdisph]hdisp}(hjW+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubj)}(henum zynqmp_dpsub_format formath](j)}(hjh]henum}(hjp+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl+ubj)}(h h]h }(hj}+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl+ubh)}(hhh]j)}(hzynqmp_dpsub_formath]hzynqmp_dpsub_format}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj+modnameN classnameNjj)}j]j8+%c.zynqmp_disp_blend_set_output_formatasbuh1hhjl+ubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl+ubj)}(hformath]hformat}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubeh}(h]h ]h"]h$]h&]hhuh1jhj*hhhj*hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj*hhhj*hMubah}(h]j*ah ](jjeh"]h$]h&]jj)jhuh1jhj*hMhj*hhubj)}(hhh]h)}(h$Set the output format of the blenderh]h$Set the output format of the blender}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj+hhubah}(h]h ]h"]h$]h&]uh1jhj*hhhj*hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j+j&j+j'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``enum zynqmp_dpsub_format format`` Output format **Description** Set the output format of the blender to **format**.h](h)}(h**Parameters**h]j5)}(hj,h]h Parameters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj,ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj,ubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj%,h]hstruct zynqmp_disp *disp}(hj',hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj#,ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj,ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj>,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:,hMhj;,ubah}(h]h ]h"]h$]h&]uh1j'hj,ubeh}(h]h ]h"]h$]h&]uh1jhj:,hMhj,ubj)}(h2``enum zynqmp_dpsub_format format`` Output format h](j)}(h#``enum zynqmp_dpsub_format format``h]jV)}(hj^,h]henum zynqmp_dpsub_format format}(hj`,hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj\,ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjX,ubj()}(hhh]h)}(h Output formath]h Output format}(hjw,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs,hMhjt,ubah}(h]h ]h"]h$]h&]uh1j'hjX,ubeh}(h]h ]h"]h$]h&]uh1jhjs,hMhj,ubeh}(h]h ]h"]h$]h&]uh1j hj,ubh)}(h**Description**h]j5)}(hj,h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj,ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj,ubh)}(h3Set the output format of the blender to **format**.h](h(Set the output format of the blender to }(hj,hhhNhNubj5)}(h **format**h]hformat}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj,ubh.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_blend_set_bg_color (C function) c.zynqmp_disp_blend_set_bg_colorhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hXvoid zynqmp_disp_blend_set_bg_color (struct zynqmp_disp *disp, u32 rcr, u32 gy, u32 bcb)h]j)}(hWvoid zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp, u32 rcr, u32 gy, u32 bcb)h](jV)}(hvoidh]hvoid}(hj,hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj,hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,hhhj,hMubj)}(hzynqmp_disp_blend_set_bg_colorh]j)}(hzynqmp_disp_blend_set_bg_colorh]hzynqmp_disp_blend_set_bg_color}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj -ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj,hhhj,hMubj)}(h4(struct zynqmp_disp *disp, u32 rcr, u32 gy, u32 bcb)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj--hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)-ubj)}(h h]h }(hj:-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)-ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjK-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjH-ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjM-modnameN classnameNjj)}j]j)}jj-sb c.zynqmp_disp_blend_set_bg_colorasbuh1hhj)-ubj)}(h h]h }(hjk-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)-ubj)}(hjh]h*}(hjy-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)-ubj)}(hdisph]hdisp}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)-ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%-ubj)}(hu32 rcrh](h)}(hhh]j)}(hu32h]hu32}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj-modnameN classnameNjj)}j]jg- c.zynqmp_disp_blend_set_bg_colorasbuh1hhj-ubj)}(h h]h }(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hrcrh]hrcr}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%-ubj)}(hu32 gyh](h)}(hhh]j)}(hu32h]hu32}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj-modnameN classnameNjj)}j]jg- c.zynqmp_disp_blend_set_bg_colorasbuh1hhj-ubj)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hgyh]hgy}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%-ubj)}(hu32 bcbh](h)}(hhh]j)}(hu32h]hu32}(hj2.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/.ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj4.modnameN classnameNjj)}j]jg- c.zynqmp_disp_blend_set_bg_colorasbuh1hhj+.ubj)}(h h]h }(hjP.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+.ubj)}(hbcbh]hbcb}(hj^.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+.ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%-ubeh}(h]h ]h"]h$]h&]hhuh1jhj,hhhj,hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj,hhhj,hMubah}(h]j,ah ](jjeh"]h$]h&]jj)jhuh1jhj,hMhj,hhubj)}(hhh]h)}(hSet the background colorh]hSet the background color}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj.hhubah}(h]h ]h"]h$]h&]uh1jhj,hhhj,hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j.j&j.j'j(j)uh1jhhhjzhNhNubj+)}(hXo**Parameters** ``struct zynqmp_disp *disp`` Display controller ``u32 rcr`` Red/Cr color component ``u32 gy`` Green/Y color component ``u32 bcb`` Blue/Cb color component **Description** Set the background color to (**rcr**, **gy**, **bcb**), corresponding to the R, G and B or Cr, Y and Cb components respectively depending on the selected output format.h](h)}(h**Parameters**h]j5)}(hj.h]h Parameters}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj.ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hj.ubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj.h]hstruct zynqmp_disp *disp}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj.ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj.ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj.ubah}(h]h ]h"]h$]h&]uh1j'hj.ubeh}(h]h ]h"]h$]h&]uh1jhj.hMhj.ubj)}(h#``u32 rcr`` Red/Cr color component h](j)}(h ``u32 rcr``h]jV)}(hj/h]hu32 rcr}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hj.ubj()}(hhh]h)}(hRed/Cr color componenth]hRed/Cr color component}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hM hj/ubah}(h]h ]h"]h$]h&]uh1j'hj.ubeh}(h]h ]h"]h$]h&]uh1jhj/hM hj.ubj)}(h#``u32 gy`` Green/Y color component h](j)}(h ``u32 gy``h]jV)}(hj;/h]hu32 gy}(hj=/hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj9/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hj5/ubj()}(hhh]h)}(hGreen/Y color componenth]hGreen/Y color component}(hjT/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP/hM hjQ/ubah}(h]h ]h"]h$]h&]uh1j'hj5/ubeh}(h]h ]h"]h$]h&]uh1jhjP/hM hj.ubj)}(h$``u32 bcb`` Blue/Cb color component h](j)}(h ``u32 bcb``h]jV)}(hjt/h]hu32 bcb}(hjv/hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjr/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hjn/ubj()}(hhh]h)}(hBlue/Cb color componenth]hBlue/Cb color component}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hM hj/ubah}(h]h ]h"]h$]h&]uh1j'hjn/ubeh}(h]h ]h"]h$]h&]uh1jhj/hM hj.ubeh}(h]h ]h"]h$]h&]uh1j hj.ubh)}(h**Description**h]j5)}(hj/h]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj/ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hj.ubh)}(hSet the background color to (**rcr**, **gy**, **bcb**), corresponding to the R, G and B or Cr, Y and Cb components respectively depending on the selected output format.h](hSet the background color to (}(hj/hhhNhNubj5)}(h**rcr**h]hrcr}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj/ubh, }(hj/hhhNhNubj5)}(h**gy**h]hgy}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj/ubh, }hj/sbj5)}(h**bcb**h]hbcb}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj/ubhs), corresponding to the R, G and B or Cr, Y and Cb components respectively depending on the selected output format.}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hj.ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/zynqmp_disp_blend_set_global_alpha (C function)$c.zynqmp_disp_blend_set_global_alphahNtauh1jhjzhhhNhNubj)}(hhh](j)}(hZvoid zynqmp_disp_blend_set_global_alpha (struct zynqmp_disp *disp, bool enable, u32 alpha)h]j)}(hYvoid zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, bool enable, u32 alpha)h](jV)}(hvoidh]hvoid}(hj*0hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj&0hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj90hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&0hhhj80hMubj)}(h"zynqmp_disp_blend_set_global_alphah]j)}(h"zynqmp_disp_blend_set_global_alphah]h"zynqmp_disp_blend_set_global_alpha}(hjK0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG0ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj&0hhhj80hMubj)}(h2(struct zynqmp_disp *disp, bool enable, u32 alpha)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjg0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc0ubj)}(h h]h }(hjt0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc0ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj0modnameN classnameNjj)}j]j)}jjM0sb$c.zynqmp_disp_blend_set_global_alphaasbuh1hhjc0ubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc0ubj)}(hjh]h*}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc0ubj)}(hdisph]hdisp}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc0ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj_0ubj)}(h bool enableh](jV)}(hj+h]hbool}(hj0hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj0ubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubj)}(henableh]henable}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj_0ubj)}(h u32 alphah](h)}(hhh]j)}(hu32h]hu32}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 1ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj1modnameN classnameNjj)}j]j0$c.zynqmp_disp_blend_set_global_alphaasbuh1hhj 1ubj)}(h h]h }(hj.1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 1ubj)}(halphah]halpha}(hj<1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 1ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj_0ubeh}(h]h ]h"]h$]h&]hhuh1jhj&0hhhj80hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj"0hhhj80hMubah}(h]j0ah ](jjeh"]h$]h&]jj)jhuh1jhj80hMhj0hhubj)}(hhh]h)}(hConfigure global alpha blendingh]hConfigure global alpha blending}(hjf1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjc1hhubah}(h]h ]h"]h$]h&]uh1jhj0hhhj80hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j~1j&j~1j'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``bool enable`` True to enable global alpha blending ``u32 alpha`` Global alpha value (ignored if **enabled** is false)h](h)}(h**Parameters**h]j5)}(hj1h]h Parameters}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj1ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj1ubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj1h]hstruct zynqmp_disp *disp}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj1ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj1ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj1ubah}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hMhj1ubj)}(h5``bool enable`` True to enable global alpha blending h](j)}(h``bool enable``h]jV)}(hj1h]h bool enable}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj1ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj1ubj()}(hhh]h)}(h$True to enable global alpha blendingh]h$True to enable global alpha blending}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj1ubah}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hMhj1ubj)}(hB``u32 alpha`` Global alpha value (ignored if **enabled** is false)h](j)}(h ``u32 alpha``h]jV)}(hj2h]h u32 alpha}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj2ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj2ubj()}(hhh]h)}(h4Global alpha value (ignored if **enabled** is false)h](hGlobal alpha value (ignored if }(hj22hhhNhNubj5)}(h **enabled**h]henabled}(hj:2hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj22ubh is false)}(hj22hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj/2ubah}(h]h ]h"]h$]h&]uh1j'hj2ubeh}(h]h ]h"]h$]h&]uh1jhj.2hMhj1ubeh}(h]h ]h"]h$]h&]uh1j hj1ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,zynqmp_disp_blend_layer_set_csc (C function)!c.zynqmp_disp_blend_layer_set_cschNtauh1jhjzhhhNhNubj)}(hhh](j)}(hvoid zynqmp_disp_blend_layer_set_csc (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer, const u16 *coeffs, const u32 *offsets)h]j)}(hvoid zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer, const u16 *coeffs, const u32 *offsets)h](jV)}(hvoidh]hvoid}(hj2hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj2hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM(ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhj2hM(ubj)}(hzynqmp_disp_blend_layer_set_csch]j)}(hzynqmp_disp_blend_layer_set_csch]hzynqmp_disp_blend_layer_set_csc}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj2hhhj2hM(ubj)}(hb(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer, const u16 *coeffs, const u32 *offsets)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj2modnameN classnameNjj)}j]j)}jj2sb!c.zynqmp_disp_blend_layer_set_cscasbuh1hhj2ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(hjh]h*}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(hdisph]hdisp}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj43hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj03ubj)}(h h]h }(hjA3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj03ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjR3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO3ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjT3modnameN classnameNjj)}j]j2!c.zynqmp_disp_blend_layer_set_cscasbuh1hhj03ubj)}(h h]h }(hjp3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj03ubj)}(hjh]h*}(hj~3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj03ubj)}(hlayerh]hlayer}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj03ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubj)}(hconst u16 *coeffsh](j)}(hjh]hconst}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubh)}(hhh]j)}(hu16h]hu16}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj3modnameN classnameNjj)}j]j2!c.zynqmp_disp_blend_layer_set_cscasbuh1hhj3ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hjh]h*}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hcoeffsh]hcoeffs}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubj)}(hconst u32 *offsetsh](j)}(hjh]hconst}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj)}(h h]h }(hj!4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubh)}(hhh]j)}(hu32h]hu32}(hj24hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/4ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj44modnameN classnameNjj)}j]j2!c.zynqmp_disp_blend_layer_set_cscasbuh1hhj4ubj)}(h h]h }(hjP4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj)}(hjh]h*}(hj^4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj)}(hoffsetsh]hoffsets}(hjk4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubeh}(h]h ]h"]h$]h&]hhuh1jhj2hhhj2hM(ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj}2hhhj2hM(ubah}(h]jx2ah ](jjeh"]h$]h&]jj)jhuh1jhj2hM(hjz2hhubj)}(hhh]h)}(h)Configure colorspace conversion for layerh]h)Configure colorspace conversion for layer}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM(hj4hhubah}(h]h ]h"]h$]h&]uh1jhjz2hhhj2hM(ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j4j&j4j'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer ``const u16 *coeffs`` Colorspace conversion matrix ``const u32 *offsets`` Colorspace conversion offsets **Description** Configure the input colorspace conversion matrix and offsets for the **layer**. Columns of the matrix are automatically swapped based on the input format to handle RGB and YCrCb components permutations.h](h)}(h**Parameters**h]j5)}(hj4h]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj4ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM,hj4ubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj4h]hstruct zynqmp_disp *disp}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj4ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM)hj4ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hM)hj4ubah}(h]h ]h"]h$]h&]uh1j'hj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hM)hj4ubj)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj5h]hstruct zynqmp_disp_layer *layer}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj 5ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM*hj 5ubj()}(hhh]h)}(h The layerh]h The layer}(hj(5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$5hM*hj%5ubah}(h]h ]h"]h$]h&]uh1j'hj 5ubeh}(h]h ]h"]h$]h&]uh1jhj$5hM*hj4ubj)}(h3``const u16 *coeffs`` Colorspace conversion matrix h](j)}(h``const u16 *coeffs``h]jV)}(hjH5h]hconst u16 *coeffs}(hjJ5hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjF5ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM+hjB5ubj()}(hhh]h)}(hColorspace conversion matrixh]hColorspace conversion matrix}(hja5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]5hM+hj^5ubah}(h]h ]h"]h$]h&]uh1j'hjB5ubeh}(h]h ]h"]h$]h&]uh1jhj]5hM+hj4ubj)}(h5``const u32 *offsets`` Colorspace conversion offsets h](j)}(h``const u32 *offsets``h]jV)}(hj5h]hconst u32 *offsets}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj5ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM,hj{5ubj()}(hhh]h)}(hColorspace conversion offsetsh]hColorspace conversion offsets}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hM,hj5ubah}(h]h ]h"]h$]h&]uh1j'hj{5ubeh}(h]h ]h"]h$]h&]uh1jhj5hM,hj4ubeh}(h]h ]h"]h$]h&]uh1j hj4ubh)}(h**Description**h]j5)}(hj5h]h Description}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj5ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM.hj4ubh)}(hConfigure the input colorspace conversion matrix and offsets for the **layer**. Columns of the matrix are automatically swapped based on the input format to handle RGB and YCrCb components permutations.h](hEConfigure the input colorspace conversion matrix and offsets for the }(hj5hhhNhNubj5)}(h **layer**h]hlayer}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj5ubh|. Columns of the matrix are automatically swapped based on the input format to handle RGB and YCrCb components permutations.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM-hj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_blend_layer_enable (C function) c.zynqmp_disp_blend_layer_enablehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h_void zynqmp_disp_blend_layer_enable (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h^void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jV)}(hvoidh]hvoid}(hj6hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj6hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM\ubj)}(h h]h }(hj"6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhj!6hM\ubj)}(hzynqmp_disp_blend_layer_enableh]j)}(hzynqmp_disp_blend_layer_enableh]hzynqmp_disp_blend_layer_enable}(hj46hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj06ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj6hhhj!6hM\ubj)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjP6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL6ubj)}(h h]h }(hj]6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL6ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjn6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjk6ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjp6modnameN classnameNjj)}j]j)}jj66sb c.zynqmp_disp_blend_layer_enableasbuh1hhjL6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL6ubj)}(hjh]h*}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL6ubj)}(hdisph]hdisp}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL6ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjH6ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj6modnameN classnameNjj)}j]j6 c.zynqmp_disp_blend_layer_enableasbuh1hhj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(hjh]h*}(hj 7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(hlayerh]hlayer}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjH6ubeh}(h]h ]h"]h$]h&]hhuh1jhj6hhhj!6hM\ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj 6hhhj!6hM\ubah}(h]j6ah ](jjeh"]h$]h&]jj)jhuh1jhj!6hM\hj6hhubj)}(hhh]h)}(hEnable a layerh]hEnable a layer}(hjC7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM\hj@7hhubah}(h]h ]h"]h$]h&]uh1jhj6hhhj!6hM\ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j[7j&j[7j'j(j)uh1jhhhjzhNhNubj+)}(hr**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layerh](h)}(h**Parameters**h]j5)}(hje7h]h Parameters}(hjg7hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjc7ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM`hj_7ubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj7h]hstruct zynqmp_disp *disp}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj7ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM]hj~7ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hM]hj7ubah}(h]h ]h"]h$]h&]uh1j'hj~7ubeh}(h]h ]h"]h$]h&]uh1jhj7hM]hj{7ubj)}(h-``struct zynqmp_disp_layer *layer`` The layerh](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj7h]hstruct zynqmp_disp_layer *layer}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj7ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM_hj7ubj()}(hhh]h)}(h The layerh]h The layer}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM^hj7ubah}(h]h ]h"]h$]h&]uh1j'hj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hM_hj{7ubeh}(h]h ]h"]h$]h&]uh1j hj_7ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,zynqmp_disp_blend_layer_disable (C function)!c.zynqmp_disp_blend_layer_disablehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h`void zynqmp_disp_blend_layer_disable (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h_void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jV)}(hvoidh]hvoid}(hj8hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj8hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj&8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8hhhj%8hMubj)}(hzynqmp_disp_blend_layer_disableh]j)}(hzynqmp_disp_blend_layer_disableh]hzynqmp_disp_blend_layer_disable}(hj88hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj48ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj8hhhj%8hMubj)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjT8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP8ubj)}(h h]h }(hja8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP8ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjr8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjo8ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjt8modnameN classnameNjj)}j]j)}jj:8sb!c.zynqmp_disp_blend_layer_disableasbuh1hhjP8ubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP8ubj)}(hjh]h*}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP8ubj)}(hdisph]hdisp}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP8ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjL8ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj8modnameN classnameNjj)}j]j8!c.zynqmp_disp_blend_layer_disableasbuh1hhj8ubj)}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(hjh]h*}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(hlayerh]hlayer}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjL8ubeh}(h]h ]h"]h$]h&]hhuh1jhj8hhhj%8hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj8hhhj%8hMubah}(h]j 8ah ](jjeh"]h$]h&]jj)jhuh1jhj%8hMhj 8hhubj)}(hhh]h)}(hDisable a layerh]hDisable a layer}(hjG9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjD9hhubah}(h]h ]h"]h$]h&]uh1jhj 8hhhj%8hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j_9j&j_9j'j(j)uh1jhhhjzhNhNubj+)}(hr**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layerh](h)}(h**Parameters**h]j5)}(hji9h]h Parameters}(hjk9hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjg9ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjc9ubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj9h]hstruct zynqmp_disp *disp}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj9ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj9ubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1j'hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj9ubj)}(h-``struct zynqmp_disp_layer *layer`` The layerh](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj9h]hstruct zynqmp_disp_layer *layer}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj9ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj9ubj()}(hhh]h)}(h The layerh]h The layer}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj9ubah}(h]h ]h"]h$]h&]uh1j'hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj9ubeh}(h]h ]h"]h$]h&]uh1j hjc9ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*zynqmp_disp_layer_find_format (C function)c.zynqmp_disp_layer_find_formathNtauh1jhjzhhhNhNubj)}(hhh](j)}(hnconst struct zynqmp_disp_format * zynqmp_disp_layer_find_format (struct zynqmp_disp_layer *layer, u32 drm_fmt)h]j)}(hlconst struct zynqmp_disp_format *zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, u32 drm_fmt)h](j)}(hjh]hconst}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj):hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj(:hMubj)}(hjh]hstruct}(hj7:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj(:hMubj)}(h h]h }(hjD:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj(:hMubh)}(hhh]j)}(hzynqmp_disp_formath]hzynqmp_disp_format}(hjU:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjR:ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjW:modnameN classnameNjj)}j]j)}jzynqmp_disp_layer_find_formatsbc.zynqmp_disp_layer_find_formatasbuh1hhj:hhhj(:hMubj)}(h h]h }(hjv:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj(:hMubj)}(hjh]h*}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj(:hMubj)}(hzynqmp_disp_layer_find_formath]j)}(hjs:h]hzynqmp_disp_layer_find_format}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj:hhhj(:hMubj)}(h.(struct zynqmp_disp_layer *layer, u32 drm_fmt)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj:modnameN classnameNjj)}j]jq:c.zynqmp_disp_layer_find_formatasbuh1hhj:ubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hjh]h*}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hlayerh]hlayer}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj:ubj)}(h u32 drm_fmth](h)}(hhh]j)}(hu32h]hu32}(hj#;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ;ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj%;modnameN classnameNjj)}j]jq:c.zynqmp_disp_layer_find_formatasbuh1hhj;ubj)}(h h]h }(hjA;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj)}(hdrm_fmth]hdrm_fmt}(hjO;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj:ubeh}(h]h ]h"]h$]h&]hhuh1jhj:hhhj(:hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj:hhhj(:hMubah}(h]j:ah ](jjeh"]h$]h&]jj)jhuh1jhj(:hMhj:hhubj)}(hhh]h)}(h(Find format information for a DRM formath]h(Find format information for a DRM format}(hjy;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjv;hhubah}(h]h ]h"]h$]h&]uh1jhj:hhhj(:hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j;j&j;j'j(j)uh1jhhhjzhNhNubj+)}(hXb**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``u32 drm_fmt`` DRM format to search **Description** Search display subsystem format information corresponding to the given DRM format **drm_fmt** for the **layer**, and return a pointer to the format descriptor. **Return** A pointer to the format descriptor if found, NULL otherwiseh](h)}(h**Parameters**h]j5)}(hj;h]h Parameters}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj;ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj;ubj )}(hhh](j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj;h]hstruct zynqmp_disp_layer *layer}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj;ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj;ubj()}(hhh]h)}(h The layerh]h The layer}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1j'hj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj;ubj)}(h%``u32 drm_fmt`` DRM format to search h](j)}(h``u32 drm_fmt``h]jV)}(hj;h]h u32 drm_fmt}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj;ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj;ubj()}(hhh]h)}(hDRM format to searchh]hDRM format to search}(hj <hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhj <ubah}(h]h ]h"]h$]h&]uh1j'hj;ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj;ubeh}(h]h ]h"]h$]h&]uh1j hj;ubh)}(h**Description**h]j5)}(hj.<h]h Description}(hj0<hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj,<ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj;ubh)}(hSearch display subsystem format information corresponding to the given DRM format **drm_fmt** for the **layer**, and return a pointer to the format descriptor.h](hRSearch display subsystem format information corresponding to the given DRM format }(hjD<hhhNhNubj5)}(h **drm_fmt**h]hdrm_fmt}(hjL<hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjD<ubh for the }(hjD<hhhNhNubj5)}(h **layer**h]hlayer}(hj^<hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjD<ubh0, and return a pointer to the format descriptor.}(hjD<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj;ubh)}(h **Return**h]j5)}(hjy<h]hReturn}(hj{<hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjw<ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj;ubh)}(h;A pointer to the format descriptor if found, NULL otherwiseh]h;A pointer to the format descriptor if found, NULL otherwise}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj;ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/zynqmp_disp_layer_find_live_format (C function)$c.zynqmp_disp_layer_find_live_formathNtauh1jhjzhhhNhNubj)}(hhh](j)}(h|const struct zynqmp_disp_format * zynqmp_disp_layer_find_live_format (struct zynqmp_disp_layer *layer, u32 media_bus_format)h]j)}(hzconst struct zynqmp_disp_format *zynqmp_disp_layer_find_live_format(struct zynqmp_disp_layer *layer, u32 media_bus_format)h](j)}(hjh]hconst}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubj)}(hjh]hstruct}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubj)}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubh)}(hhh]j)}(hzynqmp_disp_formath]hzynqmp_disp_format}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj<modnameN classnameNjj)}j]j)}j"zynqmp_disp_layer_find_live_formatsb$c.zynqmp_disp_layer_find_live_formatasbuh1hhj<hhhj<hMubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubj)}(hjh]h*}(hj'=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubj)}(h"zynqmp_disp_layer_find_live_formath]j)}(hj=h]h"zynqmp_disp_layer_find_live_format}(hj8=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4=ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj<hhhj<hMubj)}(h7(struct zynqmp_disp_layer *layer, u32 media_bus_format)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjS=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO=ubj)}(h h]h }(hj`=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO=ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjq=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn=ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjs=modnameN classnameNjj)}j]j=$c.zynqmp_disp_layer_find_live_formatasbuh1hhjO=ubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO=ubj)}(hjh]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO=ubj)}(hlayerh]hlayer}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO=ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjK=ubj)}(hu32 media_bus_formath](h)}(hhh]j)}(hu32h]hu32}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj=modnameN classnameNjj)}j]j=$c.zynqmp_disp_layer_find_live_formatasbuh1hhj=ubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubj)}(hmedia_bus_formath]hmedia_bus_format}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjK=ubeh}(h]h ]h"]h$]h&]hhuh1jhj<hhhj<hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj<hhhj<hMubah}(h]j<ah ](jjeh"]h$]h&]jj)jhuh1jhj<hMhj<hhubj)}(hhh]h)}(h2Find format information for given media bus formath]h2Find format information for given media bus format}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj>hhubah}(h]h ]h"]h$]h&]uh1jhj<hhhj<hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j4>j&j4>j'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``u32 media_bus_format`` Media bus format to search **Description** Search display subsystem format information corresponding to the given media bus format **media_bus_format** for the **layer**, and return a pointer to the format descriptor. **Return** A pointer to the format descriptor if found, NULL otherwiseh](h)}(h**Parameters**h]j5)}(hj>>h]h Parameters}(hj@>hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj<>ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj8>ubj )}(hhh](j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj]>h]hstruct zynqmp_disp_layer *layer}(hj_>hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj[>ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjW>ubj()}(hhh]h)}(h The layerh]h The layer}(hjv>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjr>hMhjs>ubah}(h]h ]h"]h$]h&]uh1j'hjW>ubeh}(h]h ]h"]h$]h&]uh1jhjr>hMhjT>ubj)}(h4``u32 media_bus_format`` Media bus format to search h](j)}(h``u32 media_bus_format``h]jV)}(hj>h]hu32 media_bus_format}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj>ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj>ubj()}(hhh]h)}(hMedia bus format to searchh]hMedia bus format to search}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj>ubah}(h]h ]h"]h$]h&]uh1j'hj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhjT>ubeh}(h]h ]h"]h$]h&]uh1j hj8>ubh)}(h**Description**h]j5)}(hj>h]h Description}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj>ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj8>ubh)}(hSearch display subsystem format information corresponding to the given media bus format **media_bus_format** for the **layer**, and return a pointer to the format descriptor.h](hXSearch display subsystem format information corresponding to the given media bus format }(hj>hhhNhNubj5)}(h**media_bus_format**h]hmedia_bus_format}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj>ubh for the }(hj>hhhNhNubj5)}(h **layer**h]hlayer}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj>ubh0, and return a pointer to the format descriptor.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj8>ubh)}(h **Return**h]j5)}(hj?h]hReturn}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj?ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj8>ubh)}(h;A pointer to the format descriptor if found, NULL otherwiseh]h;A pointer to the format descriptor if found, NULL otherwise}(hj2?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj8>ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*zynqmp_disp_layer_drm_formats (C function)c.zynqmp_disp_layer_drm_formatshNtauh1jhjzhhhNhNubj)}(hhh](j)}(h`u32 * zynqmp_disp_layer_drm_formats (struct zynqmp_disp_layer *layer, unsigned int *num_formats)h]j)}(h^u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, unsigned int *num_formats)h](h)}(hhh]j)}(hu32h]hu32}(hjd?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhja?ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjf?modnameN classnameNjj)}j]j)}jzynqmp_disp_layer_drm_formatssbc.zynqmp_disp_layer_drm_formatsasbuh1hhj]?hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]?hhhj?hMubj)}(hjh]h*}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]?hhhj?hMubj)}(hzynqmp_disp_layer_drm_formatsh]j)}(hj?h]hzynqmp_disp_layer_drm_formats}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]?hhhj?hMubj)}(h<(struct zynqmp_disp_layer *layer, unsigned int *num_formats)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj)}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj?modnameN classnameNjj)}j]j?c.zynqmp_disp_layer_drm_formatsasbuh1hhj?ubj)}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj)}(hjh]h*}(hj @hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj)}(hlayerh]hlayer}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubj)}(hunsigned int *num_formatsh](jV)}(hunsignedh]hunsigned}(hj0@hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj,@ubj)}(h h]h }(hj>@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,@ubjV)}(hinth]hint}(hjL@hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj,@ubj)}(h h]h }(hjZ@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,@ubj)}(hjh]h*}(hjh@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,@ubj)}(h num_formatsh]h num_formats}(hju@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,@ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubeh}(h]h ]h"]h$]h&]hhuh1jhj]?hhhj?hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjY?hhhj?hMubah}(h]jT?ah ](jjeh"]h$]h&]jj)jhuh1jhj?hMhjV?hhubj)}(hhh]h)}(h-Return the DRM formats supported by the layerh]h-Return the DRM formats supported by the layer}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@hhubah}(h]h ]h"]h$]h&]uh1jhjV?hhhj?hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j@j&j@j'j(j)uh1jhhhjzhNhNubj+)}(hX0**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``unsigned int *num_formats`` Pointer to the returned number of formats **NOTE** This function doesn't make sense for live video layers and will always return an empty list in such cases. zynqmp_disp_live_layer_formats() should be used to query a list of media bus formats supported by the live video input layer. **Return** A newly allocated u32 array that stores all the DRM formats supported by the layer. The number of formats in the array is returned through the num_formats argument.h](h)}(h**Parameters**h]j5)}(hj@h]h Parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj@ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubj )}(hhh](j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj@h]hstruct zynqmp_disp_layer *layer}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj@ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubj()}(hhh]h)}(h The layerh]h The layer}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1j'hj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj@ubj)}(hH``unsigned int *num_formats`` Pointer to the returned number of formats h](j)}(h``unsigned int *num_formats``h]jV)}(hjAh]hunsigned int *num_formats}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjAubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjAubj()}(hhh]h)}(h)Pointer to the returned number of formatsh]h)Pointer to the returned number of formats}(hj2AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.AhMhj/Aubah}(h]h ]h"]h$]h&]uh1j'hjAubeh}(h]h ]h"]h$]h&]uh1jhj.AhMhj@ubeh}(h]h ]h"]h$]h&]uh1j hj@ubh)}(h**NOTE**h]j5)}(hjTAh]hNOTE}(hjVAhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjRAubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubh)}(hThis function doesn't make sense for live video layers and will always return an empty list in such cases. zynqmp_disp_live_layer_formats() should be used to query a list of media bus formats supported by the live video input layer.h]hThis function doesn’t make sense for live video layers and will always return an empty list in such cases. zynqmp_disp_live_layer_formats() should be used to query a list of media bus formats supported by the live video input layer.}(hjjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubh)}(h **Return**h]j5)}(hj{Ah]hReturn}(hj}AhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjyAubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubh)}(hA newly allocated u32 array that stores all the DRM formats supported by the layer. The number of formats in the array is returned through the num_formats argument.h]hA newly allocated u32 array that stores all the DRM formats supported by the layer. The number of formats in the array is returned through the num_formats argument.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_live_layer_formats (C function) c.zynqmp_disp_live_layer_formatshNtauh1jhjzhhhNhNubj)}(hhh](j)}(hau32 * zynqmp_disp_live_layer_formats (struct zynqmp_disp_layer *layer, unsigned int *num_formats)h]j)}(h_u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer, unsigned int *num_formats)h](h)}(hhh]j)}(hu32h]hu32}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjAmodnameN classnameNjj)}j]j)}jzynqmp_disp_live_layer_formatssb c.zynqmp_disp_live_layer_formatsasbuh1hhjAhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhjAhMubj)}(hjh]h*}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhjAhMubj)}(hzynqmp_disp_live_layer_formatsh]j)}(hjAh]hzynqmp_disp_live_layer_formats}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ](jjeh"]h$]h&]hhuh1jhjAhhhjAhMubj)}(h<(struct zynqmp_disp_layer *layer, unsigned int *num_formats)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(h h]h }(hj,BhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj=BhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:Bubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj?BmodnameN classnameNjj)}j]jA c.zynqmp_disp_live_layer_formatsasbuh1hhjBubj)}(h h]h }(hj[BhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(hjh]h*}(hjiBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(hlayerh]hlayer}(hjvBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjBubj)}(hunsigned int *num_formatsh](jV)}(hunsignedh]hunsigned}(hjBhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjBubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubjV)}(hinth]hint}(hjBhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjBubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(hjh]h*}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(h num_formatsh]h num_formats}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjBubeh}(h]h ]h"]h$]h&]hhuh1jhjAhhhjAhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjAhhhjAhMubah}(h]jAah ](jjeh"]h$]h&]jj)jhuh1jhjAhMhjAhhubj)}(hhh]h)}(h>Return the media bus formats supported by the live video layerh]h>Return the media bus formats supported by the live video layer}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjBhhubah}(h]h ]h"]h$]h&]uh1jhjAhhhjAhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jCj&jCj'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``unsigned int *num_formats`` Pointer to the returned number of formats **NOTE** This function should be used only for live video input layers. **Return** A newly allocated u32 array of media bus formats supported by the layer. The number of formats in the array is returned through the **num_formats** argument.h](h)}(h**Parameters**h]j5)}(hj Ch]h Parameters}(hj"ChhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjCubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubj )}(hhh](j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj?Ch]hstruct zynqmp_disp_layer *layer}(hjAChhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj=Cubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj9Cubj()}(hhh]h)}(h The layerh]h The layer}(hjXChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTChMhjUCubah}(h]h ]h"]h$]h&]uh1j'hj9Cubeh}(h]h ]h"]h$]h&]uh1jhjTChMhj6Cubj)}(hH``unsigned int *num_formats`` Pointer to the returned number of formats h](j)}(h``unsigned int *num_formats``h]jV)}(hjxCh]hunsigned int *num_formats}(hjzChhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjvCubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjrCubj()}(hhh]h)}(h)Pointer to the returned number of formatsh]h)Pointer to the returned number of formats}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMhjCubah}(h]h ]h"]h$]h&]uh1j'hjrCubeh}(h]h ]h"]h$]h&]uh1jhjChMhj6Cubeh}(h]h ]h"]h$]h&]uh1j hjCubh)}(h**NOTE**h]j5)}(hjCh]hNOTE}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjCubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubh)}(h>This function should be used only for live video input layers.h]h>This function should be used only for live video input layers.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubh)}(h **Return**h]j5)}(hjCh]hReturn}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjCubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubh)}(hA newly allocated u32 array of media bus formats supported by the layer. The number of formats in the array is returned through the **num_formats** argument.h](hA newly allocated u32 array of media bus formats supported by the layer. The number of formats in the array is returned through the }(hjChhhNhNubj5)}(h**num_formats**h]h num_formats}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjCubh argument.}(hjChhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_disp_layer_enable (C function)c.zynqmp_disp_layer_enablehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h?void zynqmp_disp_layer_enable (struct zynqmp_disp_layer *layer)h]j)}(h>void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer)h](jV)}(hvoidh]hvoid}(hj1DhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj-Dhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj@DhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-Dhhhj?DhMubj)}(hzynqmp_disp_layer_enableh]j)}(hzynqmp_disp_layer_enableh]hzynqmp_disp_layer_enable}(hjRDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNDubah}(h]h ](jjeh"]h$]h&]hhuh1jhj-Dhhhj?DhMubj)}(h!(struct zynqmp_disp_layer *layer)h]j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjnDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjDubj)}(h h]h }(hj{DhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjDubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjDmodnameN classnameNjj)}j]j)}jjTDsbc.zynqmp_disp_layer_enableasbuh1hhjjDubj)}(h h]h }(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjDubj)}(hjh]h*}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjDubj)}(hlayerh]hlayer}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjDubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjfDubah}(h]h ]h"]h$]h&]hhuh1jhj-Dhhhj?DhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj)Dhhhj?DhMubah}(h]j$Dah ](jjeh"]h$]h&]jj)jhuh1jhj?DhMhj&Dhhubj)}(hhh]h)}(hEnable a layerh]hEnable a layer}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjDhhubah}(h]h ]h"]h$]h&]uh1jhj&Dhhhj?DhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j Ej&j Ej'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp_layer *layer`` The layer **Description** Enable the **layer** in the audio/video buffer manager and the blender. DMA channels are started separately by zynqmp_disp_layer_update().h](h)}(h**Parameters**h]j5)}(hjEh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjEubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj Eubj )}(hhh]j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hj2Eh]hstruct zynqmp_disp_layer *layer}(hj4EhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj0Eubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj,Eubj()}(hhh]h)}(h The layerh]h The layer}(hjKEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGEhMhjHEubah}(h]h ]h"]h$]h&]uh1j'hj,Eubeh}(h]h ]h"]h$]h&]uh1jhjGEhMhj)Eubah}(h]h ]h"]h$]h&]uh1j hj Eubh)}(h**Description**h]j5)}(hjmEh]h Description}(hjoEhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjkEubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj Eubh)}(hEnable the **layer** in the audio/video buffer manager and the blender. DMA channels are started separately by zynqmp_disp_layer_update().h](h Enable the }(hjEhhhNhNubj5)}(h **layer**h]hlayer}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjEubhv in the audio/video buffer manager and the blender. DMA channels are started separately by zynqmp_disp_layer_update().}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj Eubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&zynqmp_disp_layer_disable (C function)c.zynqmp_disp_layer_disablehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h@void zynqmp_disp_layer_disable (struct zynqmp_disp_layer *layer)h]j)}(h?void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer)h](jV)}(hvoidh]hvoid}(hjEhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjEhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEhhhjEhMubj)}(hzynqmp_disp_layer_disableh]j)}(hzynqmp_disp_layer_disableh]hzynqmp_disp_layer_disable}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ](jjeh"]h$]h&]hhuh1jhjEhhhjEhMubj)}(h!(struct zynqmp_disp_layer *layer)h]j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj!FmodnameN classnameNjj)}j]j)}jjEsbc.zynqmp_disp_layer_disableasbuh1hhjEubj)}(h h]h }(hj?FhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(hjh]h*}(hjMFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(hlayerh]hlayer}(hjZFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjEubah}(h]h ]h"]h$]h&]hhuh1jhjEhhhjEhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjEhhhjEhMubah}(h]jEah ](jjeh"]h$]h&]jj)jhuh1jhjEhMhjEhhubj)}(hhh]h)}(hDisable the layerh]hDisable the layer}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjFhhubah}(h]h ]h"]h$]h&]uh1jhjEhhhjEhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jFj&jFj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp_layer *layer`` The layer **Description** Disable the layer by stopping its DMA channels and disabling it in the audio/video buffer manager and the blender.h](h)}(h**Parameters**h]j5)}(hjFh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjFubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM#hjFubj )}(hhh]j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hjFh]hstruct zynqmp_disp_layer *layer}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjFubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hjFubj()}(hhh]h)}(h The layerh]h The layer}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhM hjFubah}(h]h ]h"]h$]h&]uh1j'hjFubeh}(h]h ]h"]h$]h&]uh1jhjFhM hjFubah}(h]h ]h"]h$]h&]uh1j hjFubh)}(h**Description**h]j5)}(hjGh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjFubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM"hjFubh)}(hrDisable the layer by stopping its DMA channels and disabling it in the audio/video buffer manager and the blender.h]hrDisable the layer by stopping its DMA channels and disabling it in the audio/video buffer manager and the blender.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM!hjFubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)zynqmp_disp_layer_set_format (C function)c.zynqmp_disp_layer_set_formathNtauh1jhjzhhhNhNubj)}(hhh](j)}(hgvoid zynqmp_disp_layer_set_format (struct zynqmp_disp_layer *layer, const struct drm_format_info *info)h]j)}(hfvoid zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, const struct drm_format_info *info)h](jV)}(hvoidh]hvoid}(hjEGhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjAGhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM3ubj)}(h h]h }(hjTGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAGhhhjSGhM3ubj)}(hzynqmp_disp_layer_set_formath]j)}(hzynqmp_disp_layer_set_formath]hzynqmp_disp_layer_set_format}(hjfGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbGubah}(h]h ](jjeh"]h$]h&]hhuh1jhjAGhhhjSGhM3ubj)}(hE(struct zynqmp_disp_layer *layer, const struct drm_format_info *info)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Gubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Gubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjGmodnameN classnameNjj)}j]j)}jjhGsbc.zynqmp_disp_layer_set_formatasbuh1hhj~Gubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Gubj)}(hjh]h*}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Gubj)}(hlayerh]hlayer}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Gubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjzGubj)}(h"const struct drm_format_info *infoh](j)}(hjh]hconst}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(h h]h }(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(hjh]hstruct}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(h h]h }(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubh)}(hhh]j)}(hdrm_format_infoh]hdrm_format_info}(hj-HhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*Hubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj/HmodnameN classnameNjj)}j]jGc.zynqmp_disp_layer_set_formatasbuh1hhjGubj)}(h h]h }(hjKHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(hjh]h*}(hjYHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(hinfoh]hinfo}(hjfHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjzGubeh}(h]h ]h"]h$]h&]hhuh1jhjAGhhhjSGhM3ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj=GhhhjSGhM3ubah}(h]j8Gah ](jjeh"]h$]h&]jj)jhuh1jhjSGhM3hj:Ghhubj)}(hhh]h)}(hSet the layer formath]hSet the layer format}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM3hjHhhubah}(h]h ]h"]h$]h&]uh1jhj:GhhhjSGhM3ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jHj&jHj'j(j)uh1jhhhjzhNhNubj+)}(hX"**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``const struct drm_format_info *info`` The format info **NOTE** Use zynqmp_disp_layer_set_live_format() to set media bus format for live video layers. Set the format for **layer** to **info**. The layer must be disabled.h](h)}(h**Parameters**h]j5)}(hjHh]h Parameters}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjHubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM7hjHubj )}(hhh](j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hjHh]hstruct zynqmp_disp_layer *layer}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjHubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM4hjHubj()}(hhh]h)}(h The layerh]h The layer}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhM4hjHubah}(h]h ]h"]h$]h&]uh1j'hjHubeh}(h]h ]h"]h$]h&]uh1jhjHhM4hjHubj)}(h7``const struct drm_format_info *info`` The format info h](j)}(h&``const struct drm_format_info *info``h]jV)}(hj Ih]h"const struct drm_format_info *info}(hj IhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjIubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM5hjIubj()}(hhh]h)}(hThe format infoh]hThe format info}(hj#IhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhM5hj Iubah}(h]h ]h"]h$]h&]uh1j'hjIubeh}(h]h ]h"]h$]h&]uh1jhjIhM5hjHubeh}(h]h ]h"]h$]h&]uh1j hjHubh)}(h**NOTE**h]j5)}(hjEIh]hNOTE}(hjGIhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjCIubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM7hjHubh)}(hVUse zynqmp_disp_layer_set_live_format() to set media bus format for live video layers.h]hVUse zynqmp_disp_layer_set_live_format() to set media bus format for live video layers.}(hj[IhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM7hjHubh)}(hESet the format for **layer** to **info**. The layer must be disabled.h](hSet the format for }(hjjIhhhNhNubj5)}(h **layer**h]hlayer}(hjrIhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjjIubh to }(hjjIhhhNhNubj5)}(h**info**h]hinfo}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjjIubh. The layer must be disabled.}(hjjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM:hjHubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.zynqmp_disp_layer_set_live_format (C function)#c.zynqmp_disp_layer_set_live_formathNtauh1jhjzhhhNhNubj)}(hhh](j)}(h^void zynqmp_disp_layer_set_live_format (struct zynqmp_disp_layer *layer, u32 media_bus_format)h]j)}(h]void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer, u32 media_bus_format)h](jV)}(hvoidh]hvoid}(hjIhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjIhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM_ubj)}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhhjIhM_ubj)}(h!zynqmp_disp_layer_set_live_formath]j)}(h!zynqmp_disp_layer_set_live_formath]h!zynqmp_disp_layer_set_live_format}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubah}(h]h ](jjeh"]h$]h&]hhuh1jhjIhhhjIhM_ubj)}(h7(struct zynqmp_disp_layer *layer, u32 media_bus_format)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjJmodnameN classnameNjj)}j]j)}jjIsb#c.zynqmp_disp_layer_set_live_formatasbuh1hhjIubj)}(h h]h }(hj8JhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(hjh]h*}(hjFJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(hlayerh]hlayer}(hjSJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjIubj)}(hu32 media_bus_formath](h)}(hhh]j)}(hu32h]hu32}(hjoJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlJubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjqJmodnameN classnameNjj)}j]j4J#c.zynqmp_disp_layer_set_live_formatasbuh1hhjhJubj)}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhJubj)}(hmedia_bus_formath]hmedia_bus_format}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhJubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjIubeh}(h]h ]h"]h$]h&]hhuh1jhjIhhhjIhM_ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjIhhhjIhM_ubah}(h]jIah ](jjeh"]h$]h&]jj)jhuh1jhjIhM_hjIhhubj)}(hhh]h)}(hSet the live video layer formath]hSet the live video layer format}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM_hjJhhubah}(h]h ]h"]h$]h&]uh1jhjIhhhjIhM_ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jJj&jJj'j(j)uh1jhhhjzhNhNubj+)}(hX?**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``u32 media_bus_format`` Media bus format to set **NOTE** This function should not be used to set format for non-live video layer. Use zynqmp_disp_layer_set_format() instead. Set the display format for the live **layer**. The layer must be disabled.h](h)}(h**Parameters**h]j5)}(hjJh]h Parameters}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjJubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMchjJubj )}(hhh](j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hjKh]hstruct zynqmp_disp_layer *layer}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjKubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM`hjKubj()}(hhh]h)}(h The layerh]h The layer}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM`hjKubah}(h]h ]h"]h$]h&]uh1j'hjKubeh}(h]h ]h"]h$]h&]uh1jhjKhM`hjJubj)}(h1``u32 media_bus_format`` Media bus format to set h](j)}(h``u32 media_bus_format``h]jV)}(hj?Kh]hu32 media_bus_format}(hjAKhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj=Kubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMahj9Kubj()}(hhh]h)}(hMedia bus format to seth]hMedia bus format to set}(hjXKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTKhMahjUKubah}(h]h ]h"]h$]h&]uh1j'hj9Kubeh}(h]h ]h"]h$]h&]uh1jhjTKhMahjJubeh}(h]h ]h"]h$]h&]uh1j hjJubh)}(h**NOTE**h]j5)}(hjzKh]hNOTE}(hj|KhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjxKubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMchjJubh)}(htThis function should not be used to set format for non-live video layer. Use zynqmp_disp_layer_set_format() instead.h]htThis function should not be used to set format for non-live video layer. Use zynqmp_disp_layer_set_format() instead.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMchjJubh)}(hJSet the display format for the live **layer**. The layer must be disabled.h](h$Set the display format for the live }(hjKhhhNhNubj5)}(h **layer**h]hlayer}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjKubh. The layer must be disabled.}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMfhjJubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_disp_layer_update (C function)c.zynqmp_disp_layer_updatehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h]int zynqmp_disp_layer_update (struct zynqmp_disp_layer *layer, struct drm_plane_state *state)h]j)}(h\int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, struct drm_plane_state *state)h](jV)}(hinth]hint}(hjKhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjKhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMyubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKhhhjKhMyubj)}(hzynqmp_disp_layer_updateh]j)}(hzynqmp_disp_layer_updateh]hzynqmp_disp_layer_update}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubah}(h]h ](jjeh"]h$]h&]hhuh1jhjKhhhjKhMyubj)}(h@(struct zynqmp_disp_layer *layer, struct drm_plane_state *state)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(h h]h }(hj*LhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj;LhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8Lubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj=LmodnameN classnameNjj)}j]j)}jjLsbc.zynqmp_disp_layer_updateasbuh1hhjLubj)}(h h]h }(hj[LhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(hjh]h*}(hjiLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(hlayerh]hlayer}(hjvLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjLubj)}(hstruct drm_plane_state *stateh](j)}(hjh]hstruct}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubh)}(hhh]j)}(hdrm_plane_stateh]hdrm_plane_state}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjLmodnameN classnameNjj)}j]jWLc.zynqmp_disp_layer_updateasbuh1hhjLubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(hjh]h*}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(hstateh]hstate}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjLubeh}(h]h ]h"]h$]h&]hhuh1jhjKhhhjKhMyubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjKhhhjKhMyubah}(h]jKah ](jjeh"]h$]h&]jj)jhuh1jhjKhMyhjKhhubj)}(hhh]h)}(hUpdate the layer framebufferh]hUpdate the layer framebuffer}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMyhj Mhhubah}(h]h ]h"]h$]h&]uh1jhjKhhhjKhMyubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j(Mj&j(Mj'j(j)uh1jhhhjzhNhNubj+)}(hX5**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``struct drm_plane_state *state`` The plane state **Description** Update the framebuffer for the layer by issuing a new DMA engine transaction for the new framebuffer. **Return** 0 on success, or the DMA descriptor failure error otherwiseh](h)}(h**Parameters**h]j5)}(hj2Mh]h Parameters}(hj4MhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj0Mubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM}hj,Mubj )}(hhh](j)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hjQMh]hstruct zynqmp_disp_layer *layer}(hjSMhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjOMubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMzhjKMubj()}(hhh]h)}(h The layerh]h The layer}(hjjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfMhMzhjgMubah}(h]h ]h"]h$]h&]uh1j'hjKMubeh}(h]h ]h"]h$]h&]uh1jhjfMhMzhjHMubj)}(h2``struct drm_plane_state *state`` The plane state h](j)}(h!``struct drm_plane_state *state``h]jV)}(hjMh]hstruct drm_plane_state *state}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjMubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM{hjMubj()}(hhh]h)}(hThe plane stateh]hThe plane state}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhM{hjMubah}(h]h ]h"]h$]h&]uh1j'hjMubeh}(h]h ]h"]h$]h&]uh1jhjMhM{hjHMubeh}(h]h ]h"]h$]h&]uh1j hj,Mubh)}(h**Description**h]j5)}(hjMh]h Description}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjMubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM}hj,Mubh)}(heUpdate the framebuffer for the layer by issuing a new DMA engine transaction for the new framebuffer.h]heUpdate the framebuffer for the layer by issuing a new DMA engine transaction for the new framebuffer.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM|hj,Mubh)}(h **Return**h]j5)}(hjMh]hReturn}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjMubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj,Mubh)}(h;0 on success, or the DMA descriptor failure error otherwiseh]h;0 on success, or the DMA descriptor failure error otherwise}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj,Mubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*zynqmp_disp_layer_release_dma (C function)c.zynqmp_disp_layer_release_dmahNtauh1jhjzhhhNhNubj)}(hhh](j)}(h^void zynqmp_disp_layer_release_dma (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h]void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jV)}(hvoidh]hvoid}(hj1NhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj-Nhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj@NhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-Nhhhj?NhMubj)}(hzynqmp_disp_layer_release_dmah]j)}(hzynqmp_disp_layer_release_dmah]hzynqmp_disp_layer_release_dma}(hjRNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNNubah}(h]h ](jjeh"]h$]h&]hhuh1jhj-Nhhhj?NhMubj)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjnNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjNubj)}(h h]h }(hj{NhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjNubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjNmodnameN classnameNjj)}j]j)}jjTNsbc.zynqmp_disp_layer_release_dmaasbuh1hhjjNubj)}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjNubj)}(hjh]h*}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjNubj)}(hdisph]hdisp}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjNubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjfNubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubj)}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjOmodnameN classnameNjj)}j]jNc.zynqmp_disp_layer_release_dmaasbuh1hhjNubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubj)}(hjh]h*}(hj*OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubj)}(hlayerh]hlayer}(hj7OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjfNubeh}(h]h ]h"]h$]h&]hhuh1jhj-Nhhhj?NhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj)Nhhhj?NhMubah}(h]j$Nah ](jjeh"]h$]h&]jj)jhuh1jhj?NhMhj&Nhhubj)}(hhh]h)}(h Release DMA channels for a layerh]h Release DMA channels for a layer}(hjaOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj^Ohhubah}(h]h ]h"]h$]h&]uh1jhj&Nhhhj?NhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jyOj&jyOj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer **Description** Release the DMA channels associated with **layer**.h](h)}(h**Parameters**h]j5)}(hjOh]h Parameters}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjOubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj}Oubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hjOh]hstruct zynqmp_disp *disp}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjOubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjOubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhMhjOubah}(h]h ]h"]h$]h&]uh1j'hjOubeh}(h]h ]h"]h$]h&]uh1jhjOhMhjOubj)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hjOh]hstruct zynqmp_disp_layer *layer}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjOubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjOubj()}(hhh]h)}(h The layerh]h The layer}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhMhjOubah}(h]h ]h"]h$]h&]uh1j'hjOubeh}(h]h ]h"]h$]h&]uh1jhjOhMhjOubeh}(h]h ]h"]h$]h&]uh1j hj}Oubh)}(h**Description**h]j5)}(hjPh]h Description}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjPubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj}Oubh)}(h3Release the DMA channels associated with **layer**.h](h)Release the DMA channels associated with }(hj,PhhhNhNubj5)}(h **layer**h]hlayer}(hj4PhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj,Pubh.}(hj,PhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj}Oubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'zynqmp_disp_destroy_layers (C function)c.zynqmp_disp_destroy_layershNtauh1jhjzhhhNhNubj)}(hhh](j)}(h:void zynqmp_disp_destroy_layers (struct zynqmp_disp *disp)h]j)}(h9void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp)h](jV)}(hvoidh]hvoid}(hjmPhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjiPhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj|PhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiPhhhj{PhMubj)}(hzynqmp_disp_destroy_layersh]j)}(hzynqmp_disp_destroy_layersh]hzynqmp_disp_destroy_layers}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubah}(h]h ](jjeh"]h$]h&]hhuh1jhjiPhhhj{PhMubj)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjPmodnameN classnameNjj)}j]j)}jjPsbc.zynqmp_disp_destroy_layersasbuh1hhjPubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubj)}(hjh]h*}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubj)}(hdisph]hdisp}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjPubah}(h]h ]h"]h$]h&]hhuh1jhjiPhhhj{PhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjePhhhj{PhMubah}(h]j`Pah ](jjeh"]h$]h&]jj)jhuh1jhj{PhMhjbPhhubj)}(hhh]h)}(hDestroy all layersh]hDestroy all layers}(hj-QhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj*Qhhubah}(h]h ]h"]h$]h&]uh1jhjbPhhhj{PhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jEQj&jEQj'j(j)uh1jhhhjzhNhNubj+)}(hA**Parameters** ``struct zynqmp_disp *disp`` Display controllerh](h)}(h**Parameters**h]j5)}(hjOQh]h Parameters}(hjQQhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjMQubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjIQubj )}(hhh]j)}(h/``struct zynqmp_disp *disp`` Display controllerh](j)}(h``struct zynqmp_disp *disp``h]jV)}(hjnQh]hstruct zynqmp_disp *disp}(hjpQhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjlQubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjhQubj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjQubah}(h]h ]h"]h$]h&]uh1j'hjhQubeh}(h]h ]h"]h$]h&]uh1jhjQhMhjeQubah}(h]h ]h"]h$]h&]uh1j hjIQubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*zynqmp_disp_layer_request_dma (C function)c.zynqmp_disp_layer_request_dmahNtauh1jhjzhhhNhNubj)}(hhh](j)}(h]int zynqmp_disp_layer_request_dma (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h\int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jV)}(hinth]hint}(hjQhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjQhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQhhhjQhMubj)}(hzynqmp_disp_layer_request_dmah]j)}(hzynqmp_disp_layer_request_dmah]hzynqmp_disp_layer_request_dma}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ](jjeh"]h$]h&]hhuh1jhjQhhhjQhMubj)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj#RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Rubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj%RmodnameN classnameNjj)}j]j)}jjQsbc.zynqmp_disp_layer_request_dmaasbuh1hhjRubj)}(h h]h }(hjCRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(hjh]h*}(hjQRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(hdisph]hdisp}(hj^RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjQubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjwRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsRubj)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsRubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjRmodnameN classnameNjj)}j]j?Rc.zynqmp_disp_layer_request_dmaasbuh1hhjsRubj)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsRubj)}(hjh]h*}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsRubj)}(hlayerh]hlayer}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsRubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjQubeh}(h]h ]h"]h$]h&]hhuh1jhjQhhhjQhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjQhhhjQhMubah}(h]jQah ](jjeh"]h$]h&]jj)jhuh1jhjQhMhjQhhubj)}(hhh]h)}(h Request DMA channels for a layerh]h Request DMA channels for a layer}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjRhhubah}(h]h ]h"]h$]h&]uh1jhjQhhhjQhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jSj&jSj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer **Description** Request all DMA engine channels needed by **layer**. **Return** 0 on success, or the DMA channel request error otherwiseh](h)}(h**Parameters**h]j5)}(hjSh]h Parameters}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjSubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjSubj )}(hhh](j)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jV)}(hj9Sh]hstruct zynqmp_disp *disp}(hj;ShhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj7Subah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj3Subj()}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjRShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNShMhjOSubah}(h]h ]h"]h$]h&]uh1j'hj3Subeh}(h]h ]h"]h$]h&]uh1jhjNShMhj0Subj)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jV)}(hjrSh]hstruct zynqmp_disp_layer *layer}(hjtShhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjpSubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjlSubj()}(hhh]h)}(h The layerh]h The layer}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMhjSubah}(h]h ]h"]h$]h&]uh1j'hjlSubeh}(h]h ]h"]h$]h&]uh1jhjShMhj0Subeh}(h]h ]h"]h$]h&]uh1j hjSubh)}(h**Description**h]j5)}(hjSh]h Description}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjSubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjSubh)}(h4Request all DMA engine channels needed by **layer**.h](h*Request all DMA engine channels needed by }(hjShhhNhNubj5)}(h **layer**h]hlayer}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjSubh.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjSubh)}(h **Return**h]j5)}(hjSh]hReturn}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjSubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjSubh)}(h80 on success, or the DMA channel request error otherwiseh]h80 on success, or the DMA channel request error otherwise}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&zynqmp_disp_create_layers (C function)c.zynqmp_disp_create_layershNtauh1jhjzhhhNhNubj)}(hhh](j)}(h8int zynqmp_disp_create_layers (struct zynqmp_disp *disp)h]j)}(h7int zynqmp_disp_create_layers(struct zynqmp_disp *disp)h](jV)}(hinth]hint}(hj+ThhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj'Thhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj:ThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'Thhhj9ThMubj)}(hzynqmp_disp_create_layersh]j)}(hzynqmp_disp_create_layersh]hzynqmp_disp_create_layers}(hjLThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHTubah}(h]h ](jjeh"]h$]h&]hhuh1jhj'Thhhj9ThMubj)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjhThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdTubj)}(h h]h }(hjuThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdTubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjTmodnameN classnameNjj)}j]j)}jjNTsbc.zynqmp_disp_create_layersasbuh1hhjdTubj)}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdTubj)}(hjh]h*}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdTubj)}(hdisph]hdisp}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdTubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj`Tubah}(h]h ]h"]h$]h&]hhuh1jhj'Thhhj9ThMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj#Thhhj9ThMubah}(h]jTah ](jjeh"]h$]h&]jj)jhuh1jhj9ThMhj Thhubj)}(hhh]h)}(h Create and initialize all layersh]h Create and initialize all layers}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjThhubah}(h]h ]h"]h$]h&]uh1jhj Thhhj9ThMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jUj&jUj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller **Return** 0 on success, or the DMA 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}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj VmodnameN classnameNjj)}j]j)}jjUsbc.zynqmp_disp_enableasbuh1hhjUubj)}(h h]h }(hj'VhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubj)}(hjh]h*}(hj5VhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubj)}(hdisph]hdisp}(hjBVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjUubah}(h]h ]h"]h$]h&]hhuh1jhjUhhhjUhM;ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjUhhhjUhM;ubah}(h]jUah ](jjeh"]h$]h&]jj)jhuh1jhjUhM;hjUhhubj)}(hhh]h)}(hEnable the display controllerh]hEnable the display controller}(hjlVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM;hjiVhhubah}(h]h ]h"]h$]h&]uh1jhjUhhhjUhM;ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jVj&jVj'j(j)uh1jhhhjzhNhNubj+)}(hA**Parameters** ``struct zynqmp_disp *disp`` Display controllerh](h)}(h**Parameters**h]j5)}(hjVh]h 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]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjZubj )}(hhh](j)}(h``max_rate`` maximum link rate h](j)}(h ``max_rate``h]jV)}(hj[h]hmax_rate}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj[ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chKhj[ubj()}(hhh]h)}(hmaximum link rateh]hmaximum link rate}(hj5[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1[hKhj2[ubah}(h]h ]h"]h$]h&]uh1j'hj[ubeh}(h]h ]h"]h$]h&]uh1jhj1[hKhj[ubj)}(h%``max_lanes`` maximum number of lanesh](j)}(h ``max_lanes``h]jV)}(hjU[h]h max_lanes}(hjW[hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjS[ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chKhjO[ubj()}(hhh]h)}(hmaximum number of lanesh]hmaximum number of lanes}(hjn[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chKhjk[ubah}(h]h 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\j'j(j)uh1jhhhjzhNhNubj+)}(hX0**Definition**:: struct zynqmp_dp_mode { const char *fmt; int pclock; u8 bw_code; u8 lane_cnt; }; **Members** ``fmt`` format identifier string ``pclock`` pixel clock frequency of current mode ``bw_code`` code for bandwidth(link rate) ``lane_cnt`` number of lanesh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj\ubh:}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj \ubj)}(h`struct zynqmp_dp_mode { const char *fmt; int pclock; u8 bw_code; u8 lane_cnt; };h]h`struct zynqmp_dp_mode { const char *fmt; int pclock; u8 bw_code; u8 lane_cnt; };}hj.\sbah}(h]h ]h"]h$]h&]hhuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hj \ubh)}(h **Members**h]j5)}(hj?\h]hMembers}(hjA\hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj=\ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj \ubj )}(hhh](j)}(h!``fmt`` format identifier string h](j)}(h``fmt``h]jV)}(hj^\h]hfmt}(hj`\hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj\\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjX\ubj()}(hhh]h)}(hformat identifier stringh]hformat identifier string}(hjw\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs\hMhjt\ubah}(h]h ]h"]h$]h&]uh1j'hjX\ubeh}(h]h ]h"]h$]h&]uh1jhjs\hMhjU\ubj)}(h1``pclock`` pixel clock frequency of current mode h](j)}(h ``pclock``h]jV)}(hj\h]hpclock}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj\ubj()}(hhh]h)}(h%pixel clock frequency of current modeh]h%pixel clock frequency of current mode}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMhj\ubah}(h]h ]h"]h$]h&]uh1j'hj\ubeh}(h]h ]h"]h$]h&]uh1jhj\hMhjU\ubj)}(h*``bw_code`` code for bandwidth(link rate) h](j)}(h ``bw_code``h]jV)}(hj\h]hbw_code}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj\ubj()}(hhh]h)}(hcode for bandwidth(link rate)h]hcode for bandwidth(link rate)}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMhj\ubah}(h]h ]h"]h$]h&]uh1j'hj\ubeh}(h]h ]h"]h$]h&]uh1jhj\hMhjU\ubj)}(h``lane_cnt`` number of lanesh](j)}(h ``lane_cnt``h]jV)}(hj ]h]hlane_cnt}(hj ]hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj]ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]ubj()}(hhh]h)}(hnumber of lanesh]hnumber of lanes}(hj"]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]ubah}(h]h ]h"]h$]h&]uh1j'hj]ubeh}(h]h ]h"]h$]h&]uh1jhj]hMhjU\ubeh}(h]h ]h"]h$]h&]uh1j hj \ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_config (C struct)c.zynqmp_dp_confighNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_dp_configh]j)}(hstruct zynqmp_dp_configh](j)}(hjh]hstruct}(hjc]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_]hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM ubj)}(h h]h }(hjq]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_]hhhjp]hM ubj)}(hzynqmp_dp_configh]j)}(hj]]h]hzynqmp_dp_config}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj_]hhhjp]hM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj[]hhhjp]hM ubah}(h]jV]ah ](jjeh"]h$]h&]jj)jhuh1jhjp]hM hjX]hhubj)}(hhh]h)}(h%Configuration of DisplayPort from DTSh]h%Configuration of DisplayPort from DTS}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]hhubah}(h]h ]h"]h$]h&]uh1jhjX]hhhjp]hM ubeh}(h]h ](jstructeh"]h$]h&]j$jj%j]j&j]j'j(j)uh1jhhhjzhNhNubj+)}(h**Definition**:: struct zynqmp_dp_config { u8 misc0; u8 misc1; u8 bpp; }; **Members** ``misc0`` misc0 configuration (per DP v1.2 spec) ``misc1`` misc1 configuration (per DP v1.2 spec) ``bpp`` bits per pixelh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj]ubh:}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]ubj)}(hDstruct zynqmp_dp_config { u8 misc0; u8 misc1; u8 bpp; };h]hDstruct zynqmp_dp_config { u8 misc0; u8 misc1; u8 bpp; };}hj]sbah}(h]h ]h"]h$]h&]hhuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]ubh)}(h **Members**h]j5)}(hj]h]hMembers}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj]ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]ubj )}(hhh](j)}(h1``misc0`` misc0 configuration (per DP v1.2 spec) h](j)}(h ``misc0``h]jV)}(hj^h]hmisc0}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj ^ubj()}(hhh]h)}(h&misc0 configuration (per DP v1.2 spec)h]h&misc0 configuration (per DP v1.2 spec)}(hj+^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'^hMhj(^ubah}(h]h ]h"]h$]h&]uh1j'hj ^ubeh}(h]h ]h"]h$]h&]uh1jhj'^hMhj ^ubj)}(h1``misc1`` misc1 configuration (per DP v1.2 spec) h](j)}(h ``misc1``h]jV)}(hjK^h]hmisc1}(hjM^hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjI^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjE^ubj()}(hhh]h)}(h&misc1 configuration (per DP v1.2 spec)h]h&misc1 configuration (per DP v1.2 spec)}(hjd^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`^hMhja^ubah}(h]h ]h"]h$]h&]uh1j'hjE^ubeh}(h]h ]h"]h$]h&]uh1jhj`^hMhj ^ubj)}(h``bpp`` bits per pixelh](j)}(h``bpp``h]jV)}(hj^h]hbpp}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj~^ubj()}(hhh]h)}(hbits per pixelh]hbits per pixel}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj^ubah}(h]h ]h"]h$]h&]uh1j'hj~^ubeh}(h]h ]h"]h$]h&]uh1jhj^hMhj ^ubeh}(h]h ]h"]h$]h&]uh1j hj]ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jtest_pattern (C enum)c.test_patternhNtauh1jhjzhhhNhNubj)}(hhh](j)}(h test_patternh]j)}(henum test_patternh](j)}(hjh]henum}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhj^hMubj)}(h test_patternh]j)}(hj^h]h test_pattern}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj^hhhj^hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj^hhhj^hMubah}(h]j^ah ](jjeh"]h$]h&]jj)jhuh1jhj^hMhj^hhubj)}(hhh]h)}(hTest patterns for test testingh]hTest patterns for test testing}(hj _hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj_hhubah}(h]h ]h"]h$]h&]uh1jhj^hhhj^hMubeh}(h]h ](jenumeh"]h$]h&]j$jj%j8_j&j8_j'j(j)uh1jhhhjzhNhNubj+)}(hX**Constants** ``TEST_VIDEO`` Use regular video input ``TEST_TPS1`` Link training symbol pattern TPS1 (/D10.2/) ``TEST_TPS2`` Link training symbol pattern TPS2 ``TEST_TPS3`` Link training symbol pattern TPS3 (for HBR2) ``TEST_SYMBOL_ERROR`` Symbol error measurement pattern ``TEST_PRBS7`` Output of the PRBS7 (x^7 + x^6 + 1) polynomial ``TEST_80BIT_CUSTOM`` A custom 80-bit pattern ``TEST_CP2520`` HBR2 compliance eye patternh](h)}(h **Constants**h]j5)}(hjB_h]h Constants}(hjD_hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj@_ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM!hj<_ubj )}(hhh](j)}(h'``TEST_VIDEO`` Use regular video input h](j)}(h``TEST_VIDEO``h]jV)}(hja_h]h TEST_VIDEO}(hjc_hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj__ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM$hj[_ubj()}(hhh]h)}(hUse regular video inputh]hUse regular video input}(hjz_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv_hM$hjw_ubah}(h]h ]h"]h$]h&]uh1j'hj[_ubeh}(h]h ]h"]h$]h&]uh1jhjv_hM$hjX_ubj)}(h:``TEST_TPS1`` Link training symbol pattern TPS1 (/D10.2/) h](j)}(h ``TEST_TPS1``h]jV)}(hj_h]h TEST_TPS1}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM'hj_ubj()}(hhh]h)}(h+Link training symbol pattern TPS1 (/D10.2/)h]h+Link training symbol pattern TPS1 (/D10.2/)}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM'hj_ubah}(h]h ]h"]h$]h&]uh1j'hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM'hjX_ubj)}(h0``TEST_TPS2`` Link training symbol pattern TPS2 h](j)}(h ``TEST_TPS2``h]jV)}(hj_h]h TEST_TPS2}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM*hj_ubj()}(hhh]h)}(h!Link training symbol pattern TPS2h]h!Link training symbol pattern TPS2}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM*hj_ubah}(h]h ]h"]h$]h&]uh1j'hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM*hjX_ubj)}(h;``TEST_TPS3`` Link training symbol pattern TPS3 (for HBR2) h](j)}(h ``TEST_TPS3``h]jV)}(hj `h]h TEST_TPS3}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj `ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM-hj`ubj()}(hhh]h)}(h,Link training symbol pattern TPS3 (for HBR2)h]h,Link training symbol pattern TPS3 (for HBR2)}(hj%`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!`hM-hj"`ubah}(h]h ]h"]h$]h&]uh1j'hj`ubeh}(h]h ]h"]h$]h&]uh1jhj!`hM-hjX_ubj)}(h7``TEST_SYMBOL_ERROR`` Symbol error measurement pattern h](j)}(h``TEST_SYMBOL_ERROR``h]jV)}(hjE`h]hTEST_SYMBOL_ERROR}(hjG`hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjC`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM0hj?`ubj()}(hhh]h)}(h Symbol error measurement patternh]h Symbol error measurement pattern}(hj^`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ`hM0hj[`ubah}(h]h ]h"]h$]h&]uh1j'hj?`ubeh}(h]h ]h"]h$]h&]uh1jhjZ`hM0hjX_ubj)}(h>``TEST_PRBS7`` Output of the PRBS7 (x^7 + x^6 + 1) polynomial h](j)}(h``TEST_PRBS7``h]jV)}(hj~`h]h TEST_PRBS7}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj|`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM3hjx`ubj()}(hhh]h)}(h.Output of the PRBS7 (x^7 + x^6 + 1) polynomialh]h.Output of the PRBS7 (x^7 + x^6 + 1) polynomial}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hM3hj`ubah}(h]h ]h"]h$]h&]uh1j'hjx`ubeh}(h]h ]h"]h$]h&]uh1jhj`hM3hjX_ubj)}(h.``TEST_80BIT_CUSTOM`` A custom 80-bit pattern h](j)}(h``TEST_80BIT_CUSTOM``h]jV)}(hj`h]hTEST_80BIT_CUSTOM}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM6hj`ubj()}(hhh]h)}(hA custom 80-bit patternh]hA custom 80-bit pattern}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hM6hj`ubah}(h]h ]h"]h$]h&]uh1j'hj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hM6hjX_ubj)}(h+``TEST_CP2520`` HBR2 compliance eye patternh](j)}(h``TEST_CP2520``h]jV)}(hj`h]h TEST_CP2520}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM8hj`ubj()}(hhh]h)}(hHBR2 compliance eye patternh]hHBR2 compliance eye pattern}(hj ahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM9hjaubah}(h]h ]h"]h$]h&]uh1j'hj`ubeh}(h]h ]h"]h$]h&]uh1jhjahM8hjX_ubeh}(h]h ]h"]h$]h&]uh1j hj<_ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_test (C struct)c.zynqmp_dp_testhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_dp_testh]j)}(hstruct zynqmp_dp_testh](j)}(hjh]hstruct}(hjJahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFahhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM>ubj)}(h h]h }(hjXahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFahhhjWahM>ubj)}(hzynqmp_dp_testh]j)}(hjDah]hzynqmp_dp_test}(hjjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfaubah}(h]h ](jjeh"]h$]h&]hhuh1jhjFahhhjWahM>ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjBahhhjWahM>ubah}(h]j=aah ](jjeh"]h$]h&]jj)jhuh1jhjWahM>hj?ahhubj)}(hhh]h)}(hConfiguration for test modeh]hConfiguration for test mode}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM>hjahhubah}(h]h ]h"]h$]h&]uh1jhj?ahhhjWahM>ubeh}(h]h ](jstructeh"]h$]h&]j$jj%jaj&jaj'j(j)uh1jhhhjzhNhNubj+)}(hX#**Definition**:: struct zynqmp_dp_test { enum test_pattern pattern; bool enhanced, downspread, active; u8 custom[10]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 bw_code; u8 link_cnt; }; **Members** ``pattern`` The test pattern ``enhanced`` Use enhanced framing ``downspread`` Use SSC ``active`` Whether test mode is active ``custom`` Custom pattern for ``TEST_80BIT_CUSTOM`` ``train_set`` Voltage/preemphasis settings ``bw_code`` Bandwidth code for the link ``link_cnt`` Number of lanesh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjaubh:}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMBhjaubj)}(hstruct zynqmp_dp_test { enum test_pattern pattern; bool enhanced, downspread, active; u8 custom[10]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 bw_code; u8 link_cnt; };h]hstruct zynqmp_dp_test { enum test_pattern pattern; bool enhanced, downspread, active; u8 custom[10]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 bw_code; u8 link_cnt; };}hjasbah}(h]h ]h"]h$]h&]hhuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMDhjaubh)}(h **Members**h]j5)}(hjah]hMembers}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjaubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMMhjaubj )}(hhh](j)}(h``pattern`` The test pattern h](j)}(h ``pattern``h]jV)}(hjah]hpattern}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM@hjaubj()}(hhh]h)}(hThe test patternh]hThe test pattern}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhM@hjbubah}(h]h ]h"]h$]h&]uh1j'hjaubeh}(h]h ]h"]h$]h&]uh1jhjbhM@hjaubj)}(h"``enhanced`` Use enhanced framing h](j)}(h ``enhanced``h]jV)}(hj2bh]henhanced}(hj4bhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj0bubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMAhj,bubj()}(hhh]h)}(hUse enhanced framingh]hUse enhanced framing}(hjKbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGbhMAhjHbubah}(h]h ]h"]h$]h&]uh1j'hj,bubeh}(h]h ]h"]h$]h&]uh1jhjGbhMAhjaubj)}(h``downspread`` Use SSC h](j)}(h``downspread``h]jV)}(hjkbh]h downspread}(hjmbhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjibubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMBhjebubj()}(hhh]h)}(hUse SSCh]hUse SSC}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMBhjbubah}(h]h ]h"]h$]h&]uh1j'hjebubeh}(h]h ]h"]h$]h&]uh1jhjbhMBhjaubj)}(h'``active`` Whether test mode is active h](j)}(h ``active``h]jV)}(hjbh]hactive}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjbubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMChjbubj()}(hhh]h)}(hWhether test mode is activeh]hWhether test mode is active}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMChjbubah}(h]h ]h"]h$]h&]uh1j'hjbubeh}(h]h ]h"]h$]h&]uh1jhjbhMChjaubj)}(h4``custom`` Custom pattern for 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``bw_code``h]jV)}(hj]ch]hbw_code}(hj_chhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj[cubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMFhjWcubj()}(hhh]h)}(hBandwidth code for the linkh]hBandwidth code for the link}(hjvchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrchMFhjscubah}(h]h ]h"]h$]h&]uh1j'hjWcubeh}(h]h ]h"]h$]h&]uh1jhjrchMFhjaubj)}(h``link_cnt`` Number of lanesh](j)}(h ``link_cnt``h]jV)}(hjch]hlink_cnt}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMFhjcubj()}(hhh]h)}(hNumber of lanesh]hNumber of lanes}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMGhjcubah}(h]h ]h"]h$]h&]uh1j'hjcubeh}(h]h ]h"]h$]h&]uh1jhjchMFhjaubeh}(h]h ]h"]h$]h&]uh1j hjaubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#zynqmp_dp_train_set_priv (C struct)c.zynqmp_dp_train_set_privhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hzynqmp_dp_train_set_privh]j)}(hstruct zynqmp_dp_train_set_privh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjchhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMMubj)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjchhhjchMMubj)}(hzynqmp_dp_train_set_privh]j)}(hjch]hzynqmp_dp_train_set_priv}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj dubah}(h]h ](jjeh"]h$]h&]hhuh1jhjchhhjchMMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjchhhjchMMubah}(h]jcah ](jjeh"]h$]h&]jj)jhuh1jhjchMMhjchhubj)}(hhh]h)}(h(Private data for train_set debugfs filesh]h(Private data for train_set debugfs files}(hj2dhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMRhj/dhhubah}(h]h ]h"]h$]h&]uh1jhjchhhjchMMubeh}(h]h ](jstructeh"]h$]h&]j$jj%jJdj&jJdj'j(j)uh1jhhhjzhNhNubj+)}(h**Definition**:: struct zynqmp_dp_train_set_priv { struct zynqmp_dp *dp; int lane; }; **Members** ``dp`` DisplayPort IP core structure ``lane`` The lane for this fileh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjVdhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjRdubh:}(hjRdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMVhjNdubj)}(hLstruct zynqmp_dp_train_set_priv { struct zynqmp_dp *dp; int lane; };h]hLstruct zynqmp_dp_train_set_priv { struct zynqmp_dp *dp; int lane; };}hjodsbah}(h]h ]h"]h$]h&]hhuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMXhjNdubh)}(h **Members**h]j5)}(hjdh]hMembers}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj~dubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM]hjNdubj )}(hhh](j)}(h%``dp`` DisplayPort IP core structure h](j)}(h``dp``h]jV)}(hjdh]hdp}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjdubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMThjdubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMThjdubah}(h]h ]h"]h$]h&]uh1j'hjdubeh}(h]h ]h"]h$]h&]uh1jhjdhMThjdubj)}(h``lane`` The lane for this fileh](j)}(h``lane``h]jV)}(hjdh]hlane}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjdubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMThjdubj()}(hhh]h)}(hThe lane for this fileh]hThe lane for this file}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMUhjdubah}(h]h ]h"]h$]h&]uh1j'hjdubeh}(h]h ]h"]h$]h&]uh1jhjdhMThjdubeh}(h]h ]h"]h$]h&]uh1j hjNdubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp (C struct) c.zynqmp_dphNtauh1jhjzhhhNhNubj)}(hhh](j)}(h zynqmp_dph]j)}(hstruct zynqmp_dph](j)}(hjh]hstruct}(hj2ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ehhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM[ubj)}(h h]h }(hj@ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ehhhj?ehM[ubj)}(h zynqmp_dph]j)}(hj,eh]h zynqmp_dp}(hjRehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNeubah}(h]h ](jjeh"]h$]h&]hhuh1jhj.ehhhj?ehM[ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj*ehhhj?ehM[ubah}(h]j%eah ](jjeh"]h$]h&]jj)jhuh1jhj?ehM[hj'ehhubj)}(hhh]h)}(hXilinx DisplayPort coreh]hXilinx DisplayPort core}(hjtehhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM\hjqehhubah}(h]h ]h"]h$]h&]uh1jhj'ehhhj?ehM[ubeh}(h]h ](jstructeh"]h$]h&]j$jj%jej&jej'j(j)uh1jhhhjzhNhNubj+)}(hX**Definition**:: struct zynqmp_dp { struct drm_dp_aux aux; struct drm_bridge bridge; struct work_struct hpd_work; struct work_struct hpd_irq_work; struct completion aux_done; struct mutex lock; struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *iomem; struct reset_control *reset; struct phy *phy[ZYNQMP_DP_MAX_LANES]; enum drm_connector_status status; int irq; bool enabled; bool ignore_aux_errors; bool ignore_hpd; struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES]; struct zynqmp_dp_mode mode; struct zynqmp_dp_link_config link_config; struct zynqmp_dp_test test; struct zynqmp_dp_config config; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 num_lanes; }; **Members** ``aux`` aux channel ``bridge`` DRM bridge for the DP encoder ``hpd_work`` hot plug detection worker ``hpd_irq_work`` hot plug detection IRQ worker ``aux_done`` Completed when we get an AUX reply or timeout ``lock`` Mutex protecting this struct and register access (but not AUX) ``dev`` device structure ``dpsub`` Display subsystem ``iomem`` device I/O memory for register access ``reset`` reset controller ``phy`` PHY handles for DP lanes ``status`` connection status ``irq`` irq ``enabled`` flag to indicate if the device is enabled ``ignore_aux_errors`` If set, AUX errors are suppressed ``ignore_hpd`` If set, HPD events and IRQs are ignored ``debugfs_train_set`` Debugfs private data for **train_set** ``mode`` current mode between IP core and sink device ``link_config`` common link configuration between IP core and sink device ``test`` Configuration for test mode ``config`` IP core configuration from DTS ``dpcd`` DP configuration data from currently connected sink device ``train_set`` set of training data ``num_lanes`` number of enabled phy lanesh](h)}(h**Definition**::h](j5)}(h**Definition**h]h Definition}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjeubh:}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM`hjeubj)}(hXstruct zynqmp_dp { struct drm_dp_aux aux; struct drm_bridge bridge; struct work_struct hpd_work; struct work_struct hpd_irq_work; struct completion aux_done; struct mutex lock; struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *iomem; struct reset_control *reset; struct phy *phy[ZYNQMP_DP_MAX_LANES]; enum drm_connector_status status; int irq; bool enabled; bool ignore_aux_errors; bool ignore_hpd; struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES]; struct zynqmp_dp_mode mode; struct zynqmp_dp_link_config link_config; struct zynqmp_dp_test test; struct zynqmp_dp_config config; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 num_lanes; };h]hXstruct zynqmp_dp { struct drm_dp_aux aux; struct drm_bridge bridge; struct work_struct hpd_work; struct work_struct hpd_irq_work; struct completion aux_done; struct mutex lock; struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *iomem; struct reset_control *reset; struct phy *phy[ZYNQMP_DP_MAX_LANES]; enum drm_connector_status status; int irq; bool enabled; bool ignore_aux_errors; bool ignore_hpd; struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES]; struct zynqmp_dp_mode mode; struct zynqmp_dp_link_config link_config; struct zynqmp_dp_test test; struct zynqmp_dp_config config; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 num_lanes; };}hjesbah}(h]h ]h"]h$]h&]hhuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMbhjeubh)}(h **Members**h]j5)}(hjeh]hMembers}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjeubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM}hjeubj )}(hhh](j)}(h``aux`` aux channel h](j)}(h``aux``h]jV)}(hjeh]haux}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjeubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMghjeubj()}(hhh]h)}(h aux channelh]h aux channel}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMghjeubah}(h]h ]h"]h$]h&]uh1j'hjeubeh}(h]h ]h"]h$]h&]uh1jhjehMghjeubj)}(h)``bridge`` DRM bridge for the DP encoder h](j)}(h ``bridge``h]jV)}(hjfh]hbridge}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMdhjfubj()}(hhh]h)}(hDRM bridge for the DP encoderh]hDRM bridge for the DP encoder}(hj3fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/fhMdhj0fubah}(h]h ]h"]h$]h&]uh1j'hjfubeh}(h]h ]h"]h$]h&]uh1jhj/fhMdhjeubj)}(h'``hpd_work`` hot plug detection worker h](j)}(h ``hpd_work``h]jV)}(hjSfh]hhpd_work}(hjUfhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjQfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMlhjMfubj()}(hhh]h)}(hhot plug detection workerh]hhot plug detection worker}(hjlfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhfhMlhjifubah}(h]h ]h"]h$]h&]uh1j'hjMfubeh}(h]h ]h"]h$]h&]uh1jhjhfhMlhjeubj)}(h/``hpd_irq_work`` hot plug detection IRQ worker h](j)}(h``hpd_irq_work``h]jV)}(hjfh]h hpd_irq_work}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMmhjfubj()}(hhh]h)}(hhot plug detection IRQ workerh]hhot plug detection IRQ worker}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMmhjfubah}(h]h ]h"]h$]h&]uh1j'hjfubeh}(h]h ]h"]h$]h&]uh1jhjfhMmhjeubj)}(h;``aux_done`` Completed when we get an AUX reply or timeout h](j)}(h ``aux_done``h]jV)}(hjfh]haux_done}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhhjfubj()}(hhh]h)}(h-Completed when we get an AUX reply or timeouth]h-Completed when we get an AUX reply or timeout}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMhhjfubah}(h]h ]h"]h$]h&]uh1j'hjfubeh}(h]h ]h"]h$]h&]uh1jhjfhMhhjeubj)}(hH``lock`` Mutex protecting this struct and register access (but not AUX) h](j)}(h``lock``h]jV)}(hjfh]hlock}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMbhjfubj()}(hhh]h)}(h>Mutex protecting this struct and register access (but not AUX)h]h>Mutex protecting this struct and register access (but not AUX)}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMbhjgubah}(h]h ]h"]h$]h&]uh1j'hjfubeh}(h]h ]h"]h$]h&]uh1jhjghMbhjeubj)}(h``dev`` device structure h](j)}(h``dev``h]jV)}(hj7gh]hdev}(hj9ghhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj5gubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM^hj1gubj()}(hhh]h)}(hdevice structureh]hdevice structure}(hjPghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLghM^hjMgubah}(h]h ]h"]h$]h&]uh1j'hj1gubeh}(h]h ]h"]h$]h&]uh1jhjLghM^hjeubj)}(h``dpsub`` Display subsystem h](j)}(h ``dpsub``h]jV)}(hjpgh]hdpsub}(hjrghhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjngubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM_hjjgubj()}(hhh]h)}(hDisplay subsystemh]hDisplay subsystem}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghM_hjgubah}(h]h ]h"]h$]h&]uh1j'hjjgubeh}(h]h ]h"]h$]h&]uh1jhjghM_hjeubj)}(h0``iomem`` device I/O memory for register access h](j)}(h ``iomem``h]jV)}(hjgh]hiomem}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM`hjgubj()}(hhh]h)}(h%device I/O memory for register accessh]h%device I/O memory for register access}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghM`hjgubah}(h]h ]h"]h$]h&]uh1j'hjgubeh}(h]h ]h"]h$]h&]uh1jhjghM`hjeubj)}(h``reset`` reset controller h](j)}(h ``reset``h]jV)}(hjgh]hreset}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMahjgubj()}(hhh]h)}(hreset controllerh]hreset controller}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMahjgubah}(h]h ]h"]h$]h&]uh1j'hjgubeh}(h]h ]h"]h$]h&]uh1jhjghMahjeubj)}(h!``phy`` PHY handles for DP lanes h](j)}(h``phy``h]jV)}(hjhh]hphy}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMjhjhubj()}(hhh]h)}(hPHY handles for DP lanesh]hPHY handles for DP lanes}(hj4hhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhMjhj1hubah}(h]h ]h"]h$]h&]uh1j'hjhubeh}(h]h ]h"]h$]h&]uh1jhj0hhMjhjeubj)}(h``status`` connection status h](j)}(h ``status``h]jV)}(hjThh]hstatus}(hjVhhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjRhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMohjNhubj()}(hhh]h)}(hconnection statush]hconnection status}(hjmhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihhMohjjhubah}(h]h ]h"]h$]h&]uh1j'hjNhubeh}(h]h ]h"]h$]h&]uh1jhjihhMohjeubj)}(h ``irq`` irq h](j)}(h``irq``h]jV)}(hjhh]hirq}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMchjhubj()}(hhh]h)}(hirqh]hirq}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMchjhubah}(h]h ]h"]h$]h&]uh1j'hjhubeh}(h]h ]h"]h$]h&]uh1jhjhhMchjeubj)}(h6``enabled`` flag to indicate if the device is enabled h](j)}(h ``enabled``h]jV)}(hjhh]henabled}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMphjhubj()}(hhh]h)}(h)flag to indicate if the device is enabledh]h)flag to indicate if the device is enabled}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMphjhubah}(h]h ]h"]h$]h&]uh1j'hjhubeh}(h]h ]h"]h$]h&]uh1jhjhhMphjeubj)}(h8``ignore_aux_errors`` If set, AUX errors are suppressed h](j)}(h``ignore_aux_errors``h]jV)}(hjhh]hignore_aux_errors}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMihjhubj()}(hhh]h)}(h!If set, AUX errors are suppressedh]h!If set, AUX errors are suppressed}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMihjiubah}(h]h ]h"]h$]h&]uh1j'hjhubeh}(h]h ]h"]h$]h&]uh1jhjihMihjeubj)}(h7``ignore_hpd`` If set, HPD events and IRQs are ignored h](j)}(h``ignore_hpd``h]jV)}(hj8ih]h ignore_hpd}(hj:ihhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj6iubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMnhj2iubj()}(hhh]h)}(h'If set, HPD events and IRQs are ignoredh]h'If set, HPD events and IRQs are ignored}(hjQihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMihMnhjNiubah}(h]h ]h"]h$]h&]uh1j'hj2iubeh}(h]h ]h"]h$]h&]uh1jhjMihMnhjeubj)}(h=``debugfs_train_set`` Debugfs private data for **train_set** h](j)}(h``debugfs_train_set``h]jV)}(hjqih]hdebugfs_train_set}(hjsihhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjoiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMuhjkiubj()}(hhh]h)}(h&Debugfs private data for **train_set**h](hDebugfs private data for }(hjihhhNhNubj5)}(h **train_set**h]h train_set}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjiubeh}(h]h ]h"]h$]h&]uh1hhjihMuhjiubah}(h]h ]h"]h$]h&]uh1j'hjkiubeh}(h]h ]h"]h$]h&]uh1jhjihMuhjeubj)}(h6``mode`` current mode between IP core and sink device h](j)}(h``mode``h]jV)}(hjih]hmode}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMshjiubj()}(hhh]h)}(h,current mode between IP core and sink deviceh]h,current mode between IP core and sink device}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMshjiubah}(h]h ]h"]h$]h&]uh1j'hjiubeh}(h]h ]h"]h$]h&]uh1jhjihMshjeubj)}(hJ``link_config`` common link configuration between IP core and sink device h](j)}(h``link_config``h]jV)}(hjih]h link_config}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMrhjiubj()}(hhh]h)}(h9common link configuration between IP core and sink deviceh]h9common link configuration between IP core and sink device}(hj jhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMrhjjubah}(h]h ]h"]h$]h&]uh1j'hjiubeh}(h]h ]h"]h$]h&]uh1jhjjhMrhjeubj)}(h%``test`` Configuration for test mode h](j)}(h``test``h]jV)}(hj*jh]htest}(hj,jhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj(jubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMehj$jubj()}(hhh]h)}(hConfiguration for test modeh]hConfiguration for test mode}(hjCjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?jhMehj@jubah}(h]h ]h"]h$]h&]uh1j'hj$jubeh}(h]h ]h"]h$]h&]uh1jhj?jhMehjeubj)}(h*``config`` IP core configuration from DTS h](j)}(h ``config``h]jV)}(hjcjh]hconfig}(hjejhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjajubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMfhj]jubj()}(hhh]h)}(hIP core configuration from DTSh]hIP core configuration from DTS}(hj|jhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxjhMfhjyjubah}(h]h ]h"]h$]h&]uh1j'hj]jubeh}(h]h ]h"]h$]h&]uh1jhjxjhMfhjeubj)}(hD``dpcd`` DP configuration data from currently connected sink device h](j)}(h``dpcd``h]jV)}(hjjh]hdpcd}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMqhjjubj()}(hhh]h)}(h:DP configuration data from currently connected sink deviceh]h:DP configuration data from currently connected sink device}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMqhjjubah}(h]h ]h"]h$]h&]uh1j'hjjubeh}(h]h ]h"]h$]h&]uh1jhjjhMqhjeubj)}(h#``train_set`` set of training data h](j)}(h ``train_set``h]jV)}(hjjh]h train_set}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMthjjubj()}(hhh]h)}(hset of training datah]hset of training data}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMthjjubah}(h]h ]h"]h$]h&]uh1j'hjjubeh}(h]h ]h"]h$]h&]uh1jhjjhMthjeubj)}(h)``num_lanes`` number of enabled phy lanesh](j)}(h ``num_lanes``h]jV)}(hjkh]h num_lanes}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj kubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMjhjkubj()}(hhh]h)}(hnumber of enabled phy lanesh]hnumber of enabled phy lanes}(hj'khhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMkhj$kubah}(h]h ]h"]h$]h&]uh1j'hjkubeh}(h]h ]h"]h$]h&]uh1jhj#khMjhjeubeh}(h]h ]h"]h$]h&]uh1j hjeubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubh)}(h**Description**h]j5)}(hjQkh]h Description}(hjSkhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjOkubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMnhjzhhubh)}(h**lock** covers the link configuration in this struct and the device's registers. It does not cover **aux** or **ignore_aux_errors**. It is not strictly required for any of the members which are only modified at probe/remove time (e.g. **dev**).h](j5)}(h**lock**h]hlock}(hjkkhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjgkubh^ covers the link configuration in this struct and the device’s registers. It does not cover }(hjgkhhhNhNubj5)}(h**aux**h]haux}(hj}khhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjgkubh or }(hjgkhhhNhNubj5)}(h**ignore_aux_errors**h]hignore_aux_errors}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjgkubhh. It is not strictly required for any of the members which are only modified at probe/remove time (e.g. }(hjgkhhhNhNubj5)}(h**dev**h]hdev}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjgkubh).}(hjgkhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMuhjzhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_phy_init (C function)c.zynqmp_dp_phy_inithNtauh1jhjzhhhNhNubj)}(hhh](j)}(h-int zynqmp_dp_phy_init (struct zynqmp_dp *dp)h]j)}(h,int zynqmp_dp_phy_init(struct zynqmp_dp *dp)h](jV)}(hinth]hint}(hjkhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjkhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkhhhjkhMubj)}(hzynqmp_dp_phy_inith]j)}(hzynqmp_dp_phy_inith]hzynqmp_dp_phy_init}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubah}(h]h ](jjeh"]h$]h&]hhuh1jhjkhhhjkhMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj lubj)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj lubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj.lhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+lubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj0lmodnameN classnameNjj)}j]j)}jjksbc.zynqmp_dp_phy_initasbuh1hhj lubj)}(h h]h }(hjNlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj lubj)}(hjh]h*}(hj\lhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj lubj)}(hdph]hdp}(hjilhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj lubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjlubah}(h]h ]h"]h$]h&]hhuh1jhjkhhhjkhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjkhhhjkhMubah}(h]jkah ](jjeh"]h$]h&]jj)jhuh1jhjkhMhjkhhubj)}(hhh]h)}(hInitialize the phyh]hInitialize the phy}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjlhhubah}(h]h ]h"]h$]h&]uh1jhjkhhhjkhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jlj&jlj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Initialize the phy. **Return** 0 if the phy instances are initialized correctly, or the error code returned from the callee functions.h](h)}(h**Parameters**h]j5)}(hjlh]h Parameters}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjlubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjlubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjlh]hstruct zynqmp_dp *dp}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjlubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjlubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMhjlubah}(h]h ]h"]h$]h&]uh1j'hjlubeh}(h]h ]h"]h$]h&]uh1jhjlhMhjlubah}(h]h ]h"]h$]h&]uh1j hjlubh)}(h**Description**h]j5)}(hjmh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj mubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjlubh)}(hInitialize the phy.h]hInitialize the phy.}(hj%mhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjlubh)}(h **Return**h]j5)}(hj6mh]hReturn}(hj8mhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj4mubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjlubh)}(hg0 if the phy instances are initialized correctly, or the error code returned from the callee functions.h]hg0 if the phy instances are initialized correctly, or the error code returned from the callee functions.}(hjLmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjlubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_phy_exit (C function)c.zynqmp_dp_phy_exithNtauh1jhjzhhhNhNubj)}(hhh](j)}(h.void zynqmp_dp_phy_exit (struct zynqmp_dp *dp)h]j)}(h-void zynqmp_dp_phy_exit(struct zynqmp_dp *dp)h](jV)}(hvoidh]hvoid}(hj{mhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjwmhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwmhhhjmhMubj)}(hzynqmp_dp_phy_exith]j)}(hzynqmp_dp_phy_exith]hzynqmp_dp_phy_exit}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubah}(h]h ](jjeh"]h$]h&]hhuh1jhjwmhhhjmhMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmmodnameN classnameNjj)}j]j)}jjmsbc.zynqmp_dp_phy_exitasbuh1hhjmubj)}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(hjh]h*}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(hdph]hdp}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjmubah}(h]h ]h"]h$]h&]hhuh1jhjwmhhhjmhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjsmhhhjmhMubah}(h]jnmah ](jjeh"]h$]h&]jj)jhuh1jhjmhMhjpmhhubj)}(hhh]h)}(h Exit the phyh]h Exit the phy}(hj;nhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj8nhhubah}(h]h ]h"]h$]h&]uh1jhjpmhhhjmhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jSnj&jSnj'j(j)uh1jhhhjzhNhNubj+)}(hh**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Exit the phy.h](h)}(h**Parameters**h]j5)}(hj]nh]h Parameters}(hj_nhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj[nubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjWnubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hj|nh]hstruct zynqmp_dp *dp}(hj~nhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjznubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjvnubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjnubah}(h]h ]h"]h$]h&]uh1j'hjvnubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjsnubah}(h]h ]h"]h$]h&]uh1j hjWnubh)}(h**Description**h]j5)}(hjnh]h Description}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjnubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjWnubh)}(h Exit the phy.h]h Exit the phy.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjWnubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j zynqmp_dp_phy_probe (C function)c.zynqmp_dp_phy_probehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h.int zynqmp_dp_phy_probe (struct zynqmp_dp *dp)h]j)}(h-int zynqmp_dp_phy_probe(struct zynqmp_dp *dp)h](jV)}(hinth]hint}(hjnhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjnhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnhhhj ohMubj)}(hzynqmp_dp_phy_probeh]j)}(hzynqmp_dp_phy_probeh]hzynqmp_dp_phy_probe}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ](jjeh"]h$]h&]hhuh1jhjnhhhj ohMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj9ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5oubj)}(h h]h }(hjFohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5oubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjWohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjToubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjYomodnameN classnameNjj)}j]j)}jjosbc.zynqmp_dp_phy_probeasbuh1hhj5oubj)}(h h]h }(hjwohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5oubj)}(hjh]h*}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5oubj)}(hdph]hdp}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5oubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj1oubah}(h]h ]h"]h$]h&]hhuh1jhjnhhhj ohMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjnhhhj ohMubah}(h]jnah ](jjeh"]h$]h&]jj)jhuh1jhj ohMhjnhhubj)}(hhh]h)}(hProbe the PHYsh]hProbe the PHYs}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjohhubah}(h]h ]h"]h$]h&]uh1jhjnhhhj ohMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%joj&joj'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Probe PHYs for all lanes. Less PHYs may be available than the number of lanes, which is not considered an error as long as at least one PHY is found. The caller can check dp->num_lanes to check how many PHYs were found. **Return** * 0 - Success * -ENXIO - No PHY found * -EPROBE_DEFER - Probe deferral requested * Other negative value - PHY retrieval failureh](h)}(h**Parameters**h]j5)}(hjoh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjoubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjoubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjoh]hstruct zynqmp_dp *dp}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjoubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjoubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphMhjpubah}(h]h ]h"]h$]h&]uh1j'hjoubeh}(h]h ]h"]h$]h&]uh1jhjphMhjoubah}(h]h ]h"]h$]h&]uh1j hjoubh)}(h**Description**h]j5)}(hj8ph]h Description}(hj:phhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj6pubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjoubh)}(hProbe PHYs for all lanes. Less PHYs may be available than the number of lanes, which is not considered an error as long as at least one PHY is found. The caller can check dp->num_lanes to check how many PHYs were found.h]hProbe PHYs for all lanes. Less PHYs may be available than the number of lanes, which is not considered an error as long as at least one PHY is found. The caller can check dp->num_lanes to check how many PHYs were found.}(hjNphhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjoubh)}(h **Return**h]j5)}(hj_ph]hReturn}(hjaphhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj]pubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjoubj)}(hhh](j)}(h$0 - Successh]h)}(hjzph]h$0 - Success}(hj|phhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjxpubah}(h]h ]h"]h$]h&]uh1jhjupubj)}(h)-ENXIO - No PHY foundh]h option_list)}(hhh]hoption_list_item)}(hhh](h option_group)}(hhh]hoption)}(h-ENXIOh](h option_string)}(h-Eh]h-E}hjpsbah}(h]h ]h"]h$]h&]uh1jphjpubhoption_argument)}(hNXIOh]hNXIO}(hjphhhNhNubah}(h]h ]h"]h$]h&] delimiterhuh1jphjpubeh}(h]h ]h"]h$]h&]uh1jphjpubah}(h]h ]h"]h$]h&]uh1jphjpubh description)}(h- No PHY foundh]j)}(hhh]j)}(h No PHY foundh]h)}(hjph]h No PHY found}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjpubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]j-uh1jhjphMhjpubah}(h]h ]h"]h$]h&]uh1jphjpubeh}(h]h ]h"]h$]h&]uh1jphjpubah}(h]h ]h"]h$]h&]uh1jphjphMhjpubah}(h]h ]h"]h$]h&]uh1jhjupubj)}(h5-EPROBE_DEFER - Probe deferral requestedh]jp)}(hhh]jp)}(hhh](jp)}(hhh]jp)}(h -EPROBE_DEFERh](jp)}(h-Eh]h-E}hj'qsbah}(h]h ]h"]h$]h&]uh1jphj#qubjp)}(h PROBE_DEFERh]h PROBE_DEFER}(hj5qhhhNhNubah}(h]h ]h"]h$]h&] delimiterhuh1jphj#qubeh}(h]h ]h"]h$]h&]uh1jphj qubah}(h]h ]h"]h$]h&]uh1jphjqubjp)}(h- Probe deferral requestedh]j)}(hhh]j)}(hProbe deferral requestedh]h)}(hjYqh]hProbe deferral requested}(hj[qhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjWqubah}(h]h ]h"]h$]h&]uh1jhjTqubah}(h]h ]h"]h$]h&]jjpuh1jhjhqhMhjPqubah}(h]h ]h"]h$]h&]uh1jphjqubeh}(h]h ]h"]h$]h&]uh1jphjqubah}(h]h ]h"]h$]h&]uh1jphjhqhMhjqubah}(h]h ]h"]h$]h&]uh1jhjupubj)}(h2Other negative value - PHY retrieval failureh]h)}(hjqh]h2Other negative value - PHY retrieval failure}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjqubah}(h]h ]h"]h$]h&]uh1jhjupubeh}(h]h ]h"]h$]h&]jjuh1jhjphMhjoubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j zynqmp_dp_phy_ready (C function)c.zynqmp_dp_phy_readyhNtauh1jhjzhhhNhNubj)}(hhh](j)}(h.int zynqmp_dp_phy_ready (struct zynqmp_dp *dp)h]j)}(h-int zynqmp_dp_phy_ready(struct zynqmp_dp *dp)h](jV)}(hinth]hint}(hjqhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjqhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMDubj)}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqhhhjqhMDubj)}(hzynqmp_dp_phy_readyh]j)}(hzynqmp_dp_phy_readyh]hzynqmp_dp_phy_ready}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubah}(h]h ](jjeh"]h$]h&]hhuh1jhjqhhhjqhMDubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj&rhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#rubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj(rmodnameN classnameNjj)}j]j)}jjqsbc.zynqmp_dp_phy_readyasbuh1hhjrubj)}(h h]h }(hjFrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(hjh]h*}(hjTrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(hdph]hdp}(hjarhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjrubah}(h]h ]h"]h$]h&]hhuh1jhjqhhhjqhMDubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjqhhhjqhMDubah}(h]jqah ](jjeh"]h$]h&]jj)jhuh1jhjqhMDhjqhhubj)}(hhh]h)}(hCheck if PHY is readyh]hCheck if PHY is ready}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMDhjrhhubah}(h]h ]h"]h$]h&]uh1jhjqhhhjqhMDubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jrj&jrj'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. This amount of delay was suggested by IP designer. **Return** 0 if PHY is ready, or -ENODEV if PHY is not ready.h](h)}(h**Parameters**h]j5)}(hjrh]h Parameters}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjrubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMHhjrubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjrh]hstruct zynqmp_dp *dp}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjrubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMEhjrubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMEhjrubah}(h]h ]h"]h$]h&]uh1j'hjrubeh}(h]h ]h"]h$]h&]uh1jhjrhMEhjrubah}(h]h ]h"]h$]h&]uh1j hjrubh)}(h**Description**h]j5)}(hjsh]h Description}(hj shhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjsubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMGhjrubh)}(hCheck if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. This amount of delay was suggested by IP designer.h]hCheck if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. This amount of delay was suggested by IP designer.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMFhjrubh)}(h **Return**h]j5)}(hj.sh]hReturn}(hj0shhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj,subah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMIhjrubh)}(h20 if PHY is ready, or -ENODEV if PHY is not ready.h]h20 if PHY is ready, or -ENODEV if PHY is not ready.}(hjDshhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMJhjrubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_max_rate (C function)c.zynqmp_dp_max_ratehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h;int zynqmp_dp_max_rate (int link_rate, u8 lane_num, u8 bpp)h]j)}(h:int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)h](jV)}(hinth]hint}(hjsshhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjoshhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhubj)}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoshhhjshMhubj)}(hzynqmp_dp_max_rateh]j)}(hzynqmp_dp_max_rateh]hzynqmp_dp_max_rate}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ](jjeh"]h$]h&]hhuh1jhjoshhhjshMhubj)}(h$(int link_rate, u8 lane_num, u8 bpp)h](j)}(h int link_rateh](jV)}(hinth]hint}(hjshhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjsubj)}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj)}(h link_rateh]h link_rate}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjsubj)}(h u8 lane_numh](h)}(hhh]j)}(hu8h]hu8}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjsmodnameN classnameNjj)}j]j)}jjssbc.zynqmp_dp_max_rateasbuh1hhjsubj)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj)}(hlane_numh]hlane_num}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjsubj)}(hu8 bpph](h)}(hhh]j)}(hu8h]hu8}(hj2thhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/tubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj4tmodnameN classnameNjj)}j]jtc.zynqmp_dp_max_rateasbuh1hhj+tubj)}(h h]h }(hjPthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+tubj)}(hbpph]hbpp}(hj^thhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+tubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjsubeh}(h]h ]h"]h$]h&]hhuh1jhjoshhhjshMhubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjkshhhjshMhubah}(h]jfsah ](jjeh"]h$]h&]jj)jhuh1jhjshMhhjhshhubj)}(hhh]h)}(h.Calculate and return available max pixel clockh]h.Calculate and return available max pixel clock}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhhjthhubah}(h]h ]h"]h$]h&]uh1jhjhshhhjshMhubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jtj&jtj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``int link_rate`` link rate (Kilo-bytes / sec) ``u8 lane_num`` number of lanes ``u8 bpp`` bits per pixel **Return** max pixel clock (KHz) supported by current link config.h](h)}(h**Parameters**h]j5)}(hjth]h Parameters}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjtubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMlhjtubj )}(hhh](j)}(h/``int link_rate`` link rate (Kilo-bytes / sec) h](j)}(h``int link_rate``h]jV)}(hjth]h int link_rate}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjtubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMihjtubj()}(hhh]h)}(hlink rate (Kilo-bytes / sec)h]hlink rate (Kilo-bytes / sec)}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMihjtubah}(h]h ]h"]h$]h&]uh1j'hjtubeh}(h]h ]h"]h$]h&]uh1jhjthMihjtubj)}(h ``u8 lane_num`` number of lanes h](j)}(h``u8 lane_num``h]jV)}(hjuh]h u8 lane_num}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjuubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMjhjtubj()}(hhh]h)}(hnumber of lanesh]hnumber of lanes}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMjhjuubah}(h]h ]h"]h$]h&]uh1j'hjtubeh}(h]h ]h"]h$]h&]uh1jhjuhMjhjtubj)}(h``u8 bpp`` bits per pixel h](j)}(h ``u8 bpp``h]jV)}(hj;uh]hu8 bpp}(hj=uhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj9uubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMkhj5uubj()}(hhh]h)}(hbits per pixelh]hbits per pixel}(hjTuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPuhMkhjQuubah}(h]h ]h"]h$]h&]uh1j'hj5uubeh}(h]h ]h"]h$]h&]uh1jhjPuhMkhjtubeh}(h]h ]h"]h$]h&]uh1j hjtubh)}(h **Return**h]j5)}(hjvuh]hReturn}(hjxuhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjtuubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMmhjtubh)}(h7max pixel clock (KHz) supported by current link config.h]h7max pixel clock (KHz) supported by current link config.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMmhjtubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_dp_mode_configure (C function)c.zynqmp_dp_mode_configurehNtauh1jhjzhhhNhNubj)}(hhh](j)}(hNint zynqmp_dp_mode_configure (struct zynqmp_dp *dp, int pclock, u8 current_bw)h]j)}(hMint zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, u8 current_bw)h](jV)}(hinth]hint}(hjuhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjuhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMuubj)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuhhhjuhMuubj)}(hzynqmp_dp_mode_configureh]j)}(hzynqmp_dp_mode_configureh]hzynqmp_dp_mode_configure}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubah}(h]h ](jjeh"]h$]h&]hhuh1jhjuhhhjuhMuubj)}(h1(struct zynqmp_dp *dp, int pclock, u8 current_bw)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjvmodnameN classnameNjj)}j]j)}jjusbc.zynqmp_dp_mode_configureasbuh1hhjuubj)}(h h]h }(hj6vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubj)}(hjh]h*}(hjDvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubj)}(hdph]hdp}(hjQvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjuubj)}(h int pclockh](jV)}(hinth]hint}(hjjvhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjfvubj)}(h h]h }(hjxvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfvubj)}(hpclockh]hpclock}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfvubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjuubj)}(h u8 current_bwh](h)}(hhh]j)}(hu8h]hu8}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjvmodnameN classnameNjj)}j]j2vc.zynqmp_dp_mode_configureasbuh1hhjvubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(h current_bwh]h current_bw}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjuubeh}(h]h ]h"]h$]h&]hhuh1jhjuhhhjuhMuubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjuhhhjuhMuubah}(h]juah ](jjeh"]h$]h&]jj)jhuh1jhjuhMuhjuhhubj)}(hhh]h)}(hConfigure the link valuesh]hConfigure the link values}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMuhjvhhubah}(h]h ]h"]h$]h&]uh1jhjuhhhjuhMuubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jwj&jwj'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``int pclock`` pixel clock for requested display mode ``u8 current_bw`` current link rate **Description** Find the link configuration values, rate and lane count for requested pixel clock **pclock**. The **pclock** is stored in the mode to be used in other functions later. The returned rate is downshifted from the current rate **current_bw**. **Return** Current link rate code, or -EINVAL.h](h)}(h**Parameters**h]j5)}(hjwh]h Parameters}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjwubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMyhjwubj )}(hhh](j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hj9wh]hstruct zynqmp_dp *dp}(hj;whhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj7wubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMvhj3wubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjRwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNwhMvhjOwubah}(h]h ]h"]h$]h&]uh1j'hj3wubeh}(h]h ]h"]h$]h&]uh1jhjNwhMvhj0wubj)}(h6``int pclock`` pixel clock for requested display mode h](j)}(h``int pclock``h]jV)}(hjrwh]h int pclock}(hjtwhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjpwubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMwhjlwubj()}(hhh]h)}(h&pixel clock for requested display modeh]h&pixel clock for requested display mode}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMwhjwubah}(h]h ]h"]h$]h&]uh1j'hjlwubeh}(h]h ]h"]h$]h&]uh1jhjwhMwhj0wubj)}(h$``u8 current_bw`` current link rate h](j)}(h``u8 current_bw``h]jV)}(hjwh]h u8 current_bw}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjwubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMxhjwubj()}(hhh]h)}(hcurrent link rateh]hcurrent link rate}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMxhjwubah}(h]h ]h"]h$]h&]uh1j'hjwubeh}(h]h ]h"]h$]h&]uh1jhjwhMxhj0wubeh}(h]h ]h"]h$]h&]uh1j hjwubh)}(h**Description**h]j5)}(hjwh]h Description}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjwubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMzhjwubh)}(hFind the link configuration values, rate and lane count for requested pixel clock **pclock**. The **pclock** is stored in the mode to be used in other functions later. The returned rate is downshifted from the current rate **current_bw**.h](hRFind the link configuration values, rate and lane count for requested pixel clock }(hjwhhhNhNubj5)}(h **pclock**h]hpclock}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjwubh. The }(hjwhhhNhNubj5)}(h **pclock**h]hpclock}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjwubhs is stored in the mode to be used in other functions later. The returned rate is downshifted from the current rate }(hjwhhhNhNubj5)}(h**current_bw**h]h current_bw}(hj(xhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjwubh.}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMyhjwubh)}(h **Return**h]j5)}(hjCxh]hReturn}(hjExhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjAxubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM~hjwubh)}(h#Current link rate code, or -EINVAL.h]h#Current link rate code, or -EINVAL.}(hjYxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjwubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#zynqmp_dp_adjust_train (C function)c.zynqmp_dp_adjust_trainhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hWvoid zynqmp_dp_adjust_train (struct zynqmp_dp *dp, u8 link_status[DP_LINK_STATUS_SIZE])h]j)}(hVvoid zynqmp_dp_adjust_train(struct zynqmp_dp *dp, u8 link_status[DP_LINK_STATUS_SIZE])h](jV)}(hvoidh]hvoid}(hjxhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjxhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxhhhjxhMubj)}(hzynqmp_dp_adjust_trainh]j)}(hzynqmp_dp_adjust_trainh]hzynqmp_dp_adjust_train}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubah}(h]h ](jjeh"]h$]h&]hhuh1jhjxhhhjxhMubj)}(h;(struct zynqmp_dp *dp, u8 link_status[DP_LINK_STATUS_SIZE])h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj)}(h h]h }(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjxmodnameN classnameNjj)}j]j)}jjxsbc.zynqmp_dp_adjust_trainasbuh1hhjxubj)}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj)}(hdph]hdp}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjxubj)}(h#u8 link_status[DP_LINK_STATUS_SIZE]h](h)}(hhh]j)}(hu8h]hu8}(hj:yhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7yubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjlink status from sink which contains requested training valuesh]h>link status from sink which contains requested training values}(hj`zhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]zubah}(h]h ]h"]h$]h&]uh1j'hjAzubeh}(h]h ]h"]h$]h&]uh1jhj\zhMhjzubeh}(h]h ]h"]h$]h&]uh1j hjyubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_dp_update_vs_emph (C function)c.zynqmp_dp_update_vs_emphhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hBint zynqmp_dp_update_vs_emph (struct zynqmp_dp *dp, u8 *train_set)h]j)}(hAint zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set)h](jV)}(hinth]hint}(hjzhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjzhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzhhhjzhMubj)}(hzynqmp_dp_update_vs_emphh]j)}(hzynqmp_dp_update_vs_emphh]hzynqmp_dp_update_vs_emph}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ](jjeh"]h$]h&]hhuh1jhjzhhhjzhMubj)}(h%(struct zynqmp_dp *dp, u8 *train_set)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjzmodnameN classnameNjj)}j]j)}jjzsbc.zynqmp_dp_update_vs_emphasbuh1hhjzubj)}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(hjh]h*}(hj*{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(hdph]hdp}(hj7{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjzubj)}(h u8 *train_seth](h)}(hhh]j)}(hu8h]hu8}(hjS{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjU{modnameN classnameNjj)}j]j{c.zynqmp_dp_update_vs_emphasbuh1hhjL{ubj)}(h h]h }(hjq{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL{ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL{ubj)}(h train_seth]h train_set}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL{ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjzubeh}(h]h ]h"]h$]h&]hhuh1jhjzhhhjzhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjzhhhjzhMubah}(h]jzah ](jjeh"]h$]h&]jj)jhuh1jhjzhMhjzhhubj)}(hhh]h)}(hUpdate the training valuesh]hUpdate the training values}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj{hhubah}(h]h ]h"]h$]h&]uh1jhjzhhhjzhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j{j&j{j'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``u8 *train_set`` A set of training values **Description** Update the training values based on the request from sink. The mapped values are predefined, and values(vs, pe, pc) are from the device manual. **Return** 0 if vs and emph are updated successfully, or the error code returned by drm_dp_dpcd_write().h](h)}(h**Parameters**h]j5)}(hj{h]h Parameters}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj{ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj{ubj )}(hhh](j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hj{h]hstruct zynqmp_dp *dp}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj{ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj{ubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj |hMhj |ubah}(h]h ]h"]h$]h&]uh1j'hj{ubeh}(h]h ]h"]h$]h&]uh1jhj |hMhj{ubj)}(h+``u8 *train_set`` A set of training values h](j)}(h``u8 *train_set``h]jV)}(hj0|h]h u8 *train_set}(hj2|hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj.|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj*|ubj()}(hhh]h)}(hA set of training valuesh]hA set of training values}(hjI|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE|hMhjF|ubah}(h]h ]h"]h$]h&]uh1j'hj*|ubeh}(h]h ]h"]h$]h&]uh1jhjE|hMhj{ubeh}(h]h ]h"]h$]h&]uh1j hj{ubh)}(h**Description**h]j5)}(hjk|h]h Description}(hjm|hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hji|ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj{ubh)}(hUpdate the training values based on the request from sink. The mapped values are predefined, and values(vs, pe, pc) are from the device manual.h]hUpdate the training values based on the request from sink. The mapped values are predefined, and values(vs, pe, pc) are from the device manual.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj{ubh)}(h **Return**h]j5)}(hj|h]hReturn}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj|ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj{ubh)}(h]0 if vs and emph are updated successfully, or the error code returned by drm_dp_dpcd_write().h]h]0 if vs and emph are updated successfully, or the error code returned by drm_dp_dpcd_write().}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$zynqmp_dp_link_train_cr (C function)c.zynqmp_dp_link_train_crhNtauh1jhjzhhhNhNubj)}(hhh](j)}(h2int zynqmp_dp_link_train_cr (struct zynqmp_dp *dp)h]j)}(h1int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)h](jV)}(hinth]hint}(hj|hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj|hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|hhhj|hMubj)}(hzynqmp_dp_link_train_crh]j)}(hzynqmp_dp_link_train_crh]hzynqmp_dp_link_train_cr}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj|hhhj|hMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubj)}(h h]h }(hj!}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj2}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/}ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj4}modnameN classnameNjj)}j]j)}jj|sbc.zynqmp_dp_link_train_crasbuh1hhj}ubj)}(h h]h }(hjR}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubj)}(hjh]h*}(hj`}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubj)}(hdph]hdp}(hjm}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj }ubah}(h]h ]h"]h$]h&]hhuh1jhj|hhhj|hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj|hhhj|hMubah}(h]j|ah ](jjeh"]h$]h&]jj)jhuh1jhj|hMhj|hhubj)}(hhh]h)}(hTrain clock recoveryh]hTrain clock recovery}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj}hhubah}(h]h ]h"]h$]h&]uh1jhj|hhhj|hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j}j&j}j'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Return** 0 if clock recovery train is done successfully, or corresponding error code.h](h)}(h**Parameters**h]j5)}(hj}h]h Parameters}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj}ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj}ubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hj}h]hstruct zynqmp_dp *dp}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj}ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj}ubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj}ubah}(h]h ]h"]h$]h&]uh1j'hj}ubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj}ubah}(h]h ]h"]h$]h&]uh1j hj}ubh)}(h **Return**h]j5)}(hj~h]hReturn}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj~ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj}ubh)}(hL0 if clock recovery train is done successfully, or corresponding error code.h]hL0 if clock recovery train is done successfully, or corresponding error code.}(hj)~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj}ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$zynqmp_dp_link_train_ce (C function)c.zynqmp_dp_link_train_cehNtauh1jhjzhhhNhNubj)}(hhh](j)}(h2int zynqmp_dp_link_train_ce (struct zynqmp_dp *dp)h]j)}(h1int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)h](jV)}(hinth]hint}(hjX~hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjT~hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM3ubj)}(h h]h }(hjg~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjT~hhhjf~hM3ubj)}(hzynqmp_dp_link_train_ceh]j)}(hzynqmp_dp_link_train_ceh]hzynqmp_dp_link_train_ce}(hjy~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhju~ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjT~hhhjf~hM3ubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj~modnameN classnameNjj)}j]j)}jj{~sbc.zynqmp_dp_link_train_ceasbuh1hhj~ubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(hjh]h*}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(hdph]hdp}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj~ubah}(h]h ]h"]h$]h&]hhuh1jhjT~hhhjf~hM3ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjP~hhhjf~hM3ubah}(h]jK~ah ](jjeh"]h$]h&]jj)jhuh1jhjf~hM3hjM~hhubj)}(hhh]h)}(hTrain channel equalizationh]hTrain channel equalization}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM3hjhhubah}(h]h ]h"]h$]h&]uh1jhjM~hhhjf~hM3ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j0j&j0j'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Return** 0 if channel equalization train is done successfully, or corresponding error code.h](h)}(h**Parameters**h]j5)}(hj:h]h Parameters}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj8ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM7hj4ubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjYh]hstruct zynqmp_dp *dp}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjWubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM4hjSubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhM4hjoubah}(h]h ]h"]h$]h&]uh1j'hjSubeh}(h]h ]h"]h$]h&]uh1jhjnhM4hjPubah}(h]h ]h"]h$]h&]uh1j hj4ubh)}(h **Return**h]j5)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM6hj4ubh)}(hR0 if channel equalization train is done successfully, or corresponding error code.h]hR0 if channel equalization train is done successfully, or corresponding error code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM6hj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_setup (C function)c.zynqmp_dp_setuphNtauh1jhjzhhhNhNubj)}(hhh](j)}(hcint zynqmp_dp_setup (struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, bool enhanced, bool downspread)h]j)}(hbint zynqmp_dp_setup(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, bool enhanced, bool downspread)h](jV)}(hinth]hint}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMeubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMeubj)}(hzynqmp_dp_setuph]j)}(hzynqmp_dp_setuph]hzynqmp_dp_setup}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMeubj)}(hO(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, bool enhanced, bool downspread)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj6modnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_setupasbuh1hhjubj)}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h u8 bw_codeh](h)}(hhh]j)}(hu8h]hu8}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jPc.zynqmp_dp_setupasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hbw_codeh]hbw_code}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h u8 lane_cnth](h)}(hhh]j)}(hu8h]hu8}(hjӀhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjЀubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjՀmodnameN classnameNjj)}j]jPc.zynqmp_dp_setupasbuh1hhj̀ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̀ubj)}(hlane_cnth]hlane_cnt}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̀ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h bool enhancedh](jV)}(hj+h]hbool}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(henhancedh]henhanced}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hbool downspreadh](jV)}(hj+h]hbool}(hjLhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjHubj)}(h h]h }(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubj)}(h downspreadh]h downspread}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMeubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhMeubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMehjhhubj)}(hhh]h)}(hSet up major link parametersh]hSet up major link parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMehjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMeubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(hXE**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``u8 bw_code`` The link bandwidth as a multiple of 270 MHz ``u8 lane_cnt`` The number of lanes to use ``bool enhanced`` Use enhanced framing ``bool downspread`` Enable spread-spectrum clocking **Return** 0 on success, or -errno on failureh](h)}(h**Parameters**h]j5)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMihjubj )}(hhh](j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjҁh]hstruct zynqmp_dp *dp}(hjԁhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjЁubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMfhj́ubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMfhjubah}(h]h ]h"]h$]h&]uh1j'hj́ubeh}(h]h ]h"]h$]h&]uh1jhjhMfhjɁubj)}(h;``u8 bw_code`` The link bandwidth as a multiple of 270 MHz h](j)}(h``u8 bw_code``h]jV)}(hj h]h u8 bw_code}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMghjubj()}(hhh]h)}(h+The link bandwidth as a multiple of 270 MHzh]h+The link bandwidth as a multiple of 270 MHz}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMghj!ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hMghjɁubj)}(h+``u8 lane_cnt`` The number of lanes to use h](j)}(h``u8 lane_cnt``h]jV)}(hjDh]h u8 lane_cnt}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjBubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhhj>ubj()}(hhh]h)}(hThe number of lanes to useh]hThe number of lanes to use}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMhhjZubah}(h]h ]h"]h$]h&]uh1j'hj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhMhhjɁubj)}(h'``bool enhanced`` Use enhanced framing h](j)}(h``bool enhanced``h]jV)}(hj}h]h bool enhanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj{ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMihjwubj()}(hhh]h)}(hUse enhanced framingh]hUse enhanced framing}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMihjubah}(h]h ]h"]h$]h&]uh1j'hjwubeh}(h]h ]h"]h$]h&]uh1jhjhMihjɁubj)}(h4``bool downspread`` Enable spread-spectrum clocking h](j)}(h``bool downspread``h]jV)}(hjh]hbool downspread}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMjhjubj()}(hhh]h)}(hEnable spread-spectrum clockingh]hEnable spread-spectrum clocking}(hjςhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj˂hMjhĵubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj˂hMjhjɁubeh}(h]h ]h"]h$]h&]uh1j hjubh)}(h **Return**h]j5)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMlhjubh)}(h"0 on success, or -errno on failureh]h"0 on success, or -errno on failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMlhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_train (C function)c.zynqmp_dp_trainhNtauh1jhjzhhhNhNubj)}(hhh](j)}(h*int zynqmp_dp_train (struct zynqmp_dp *dp)h]j)}(h)int zynqmp_dp_train(struct zynqmp_dp *dp)h](jV)}(hinth]hint}(hj6hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj2hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhjDhMubj)}(hzynqmp_dp_trainh]j)}(hzynqmp_dp_trainh]hzynqmp_dp_train}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ](jjeh"]h$]h&]hhuh1jhj2hhhjDhMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjYsbc.zynqmp_dp_trainasbuh1hhjoubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hdph]hdp}(hj̃hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjkubah}(h]h ]h"]h$]h&]hhuh1jhj2hhhjDhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj.hhhjDhMubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1jhjDhMhj+hhubj)}(hhh]h)}(hTrain the linkh]hTrain the link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj+hhhjDhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Return** 0 if all trains are done successfully, or corresponding error code.h](h)}(h**Parameters**h]j5)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hj7h]hstruct zynqmp_dp *dp}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj5ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj1ubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhMhjMubah}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhMhj.ubah}(h]h ]h"]h$]h&]uh1j hjubh)}(h **Return**h]j5)}(hjrh]hReturn}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjpubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hC0 if all trains are done successfully, or corresponding error code.h]hC0 if all trains are done successfully, or corresponding error code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!zynqmp_dp_train_loop (C function)c.zynqmp_dp_train_loophNtauh1jhjzhhhNhNubj)}(hhh](j)}(h0void zynqmp_dp_train_loop (struct zynqmp_dp *dp)h]j)}(h/void zynqmp_dp_train_loop(struct zynqmp_dp *dp)h](jV)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjƄhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjńhMubj)}(hzynqmp_dp_train_looph]j)}(hzynqmp_dp_train_looph]hzynqmp_dp_train_loop}(hj؄hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjԄubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjńhMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjڄsbc.zynqmp_dp_train_loopasbuh1hhjubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjńhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjńhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjńhMhjhhubj)}(hhh]h)}(h'Downshift the link rate during trainingh]h'Downshift the link rate during training}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjthhubah}(h]h ]h"]h$]h&]uh1jhjhhhjńhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Train the link by downshifting the link rate if training is not successful.h](h)}(h**Parameters**h]j5)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjхhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjͅhMhj΅ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjͅhMhjubah}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j5)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hKTrain the link by downshifting the link rate if training is not successful.h]hKTrain the link by downshifting the link rate if training is not successful.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_dp_aux_cmd_submit (C function)c.zynqmp_dp_aux_cmd_submithNtauh1jhjzhhhNhNubj)}(hhh](j)}(hdint zynqmp_dp_aux_cmd_submit (struct zynqmp_dp *dp, u32 cmd, u16 addr, u8 *buf, u8 bytes, u8 *reply)h]j)}(hcint zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr, u8 *buf, u8 bytes, u8 *reply)h](jV)}(hinth]hint}(hj8hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj4hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhjFhMubj)}(hzynqmp_dp_aux_cmd_submith]j)}(hzynqmp_dp_aux_cmd_submith]hzynqmp_dp_aux_cmd_submit}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubah}(h]h ](jjeh"]h$]h&]hhuh1jhj4hhhjFhMubj)}(hG(struct zynqmp_dp *dp, u32 cmd, u16 addr, u8 *buf, u8 bytes, u8 *reply)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jj[sbc.zynqmp_dp_aux_cmd_submitasbuh1hhjqubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(hdph]hdp}(hjΆhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjmubj)}(hu32 cmdh](h)}(hhh]j)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hcmdh]hcmd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjmubj)}(hu16 addrh](h)}(hhh]j)}(hu16h]hu16}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj4modnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhj+ubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubj)}(haddrh]haddr}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjmubj)}(hu8 *bufh](h)}(hhh]j)}(hu8h]hu8}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj|modnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhjsubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj)}(hbufh]hbuf}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjmubj)}(hu8 bytesh](h)}(hhh]j)}(hu8h]hu8}(hjχhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̇ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjчmodnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhjȇubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȇubj)}(hbytesh]hbytes}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȇubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjmubj)}(h u8 *replyh](h)}(hhh]j)}(hu8h]hu8}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhjubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hreplyh]hreply}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjmubeh}(h]h ]h"]h$]h&]hhuh1jhj4hhhjFhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj0hhhjFhMubah}(h]j+ah ](jjeh"]h$]h&]jj)jhuh1jhjFhMhj-hhubj)}(hhh]h)}(hSubmit aux commandh]hSubmit aux command}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjwhhubah}(h]h ]h"]h$]h&]uh1jhj-hhhjFhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``u32 cmd`` aux command ``u16 addr`` aux address ``u8 *buf`` buffer for command data ``u8 bytes`` number of bytes for **buf** ``u8 *reply`` reply code to be returned **Description** Submit an aux command. All aux related commands, native or i2c aux read/write, are submitted through this function. The function is mapped to the transfer function of struct drm_dp_aux. This function involves in multiple register reads/writes, thus synchronization is needed, and it is done by drm_dp_helper using **hw_mutex**. The calling thread goes into sleep if there's no immediate reply to the command submission. The reply code is returned at **reply** if **reply** != NULL. **Return** 0 if the command is submitted properly, or corresponding error code: -EBUSY when there is any request already being processed -ETIMEDOUT when receiving reply is timed out -EIO when received bytes are less than requestedh](h)}(h**Parameters**h]j5)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj )}(hhh](j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjԈhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjЈhMhjшubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjЈhMhjubj)}(h``u32 cmd`` aux command h](j)}(h ``u32 cmd``h]jV)}(hjh]hu32 cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(h aux commandh]h aux command}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(h``u16 addr`` aux address h](j)}(h ``u16 addr``h]jV)}(hj-h]hu16 addr}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj+ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj'ubj()}(hhh]h)}(h aux addressh]h aux address}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMhjCubah}(h]h ]h"]h$]h&]uh1j'hj'ubeh}(h]h ]h"]h$]h&]uh1jhjBhMhjubj)}(h$``u8 *buf`` buffer for command data h](j)}(h ``u8 *buf``h]jV)}(hjfh]hu8 *buf}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjdubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj`ubj()}(hhh]h)}(hbuffer for command datah]hbuffer for command data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hMhj|ubah}(h]h ]h"]h$]h&]uh1j'hj`ubeh}(h]h ]h"]h$]h&]uh1jhj{hMhjubj)}(h)``u8 bytes`` number of bytes for **buf** h](j)}(h ``u8 bytes``h]jV)}(hjh]hu8 bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hnumber of bytes for **buf**h](hnumber of bytes for }(hjhhhNhNubj5)}(h**buf**h]hbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h(``u8 *reply`` reply code to be returned h](j)}(h ``u8 *reply``h]jV)}(hjh]h u8 *reply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hreply code to be returnedh]hreply code to be returned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j5)}(hj!h]h Description}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hXSubmit an aux command. All aux related commands, native or i2c aux read/write, are submitted through this function. The function is mapped to the transfer function of struct drm_dp_aux. This function involves in multiple register reads/writes, thus synchronization is needed, and it is done by drm_dp_helper using **hw_mutex**. The calling thread goes into sleep if there's no immediate reply to the command submission. The reply code is returned at **reply** if **reply** != NULL.h](hX:Submit an aux command. All aux related commands, native or i2c aux read/write, are submitted through this function. The function is mapped to the transfer function of struct drm_dp_aux. This function involves in multiple register reads/writes, thus synchronization is needed, and it is done by drm_dp_helper using }(hj7hhhNhNubj5)}(h **hw_mutex**h]hhw_mutex}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj7ubh~. The calling thread goes into sleep if there’s no immediate reply to the command submission. The reply code is returned at }(hj7hhhNhNubj5)}(h **reply**h]hreply}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj7ubh if }(hj7hhhNhNubj5)}(h **reply**h]hreply}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj7ubh != NULL.}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(h **Return**h]j5)}(hj~h]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj|ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(h0 if the command is submitted properly, or corresponding error code: -EBUSY when there is any request already being processed -ETIMEDOUT when receiving reply is timed out -EIO when received bytes are less than requestedh]h0 if the command is submitted properly, or corresponding error code: -EBUSY when there is any request already being processed -ETIMEDOUT when receiving reply is timed out -EIO when received bytes are less than requested}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_aux_init (C function)c.zynqmp_dp_aux_inithNtauh1jhjzhhhNhNubj)}(hhh](j)}(h-int zynqmp_dp_aux_init (struct zynqmp_dp *dp)h]j)}(h,int zynqmp_dp_aux_init(struct zynqmp_dp *dp)h](jV)}(hinth]hint}(hjÊhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMnubj)}(h h]h }(hjҊhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjъhMnubj)}(hzynqmp_dp_aux_inith]j)}(hzynqmp_dp_aux_inith]hzynqmp_dp_aux_init}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjъhMnubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_aux_initasbuh1hhjubj)}(h h]h }(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjъhMnubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjъhMnubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjъhMnhjhhubj)}(hhh]h)}(h"Initialize and register the DP AUXh]h"Initialize and register the DP AUX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMnhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjъhMnubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Program the AUX clock divider and filter and register the DP AUX adapter. **Return** 0 on success, error value otherwiseh](h)}(h**Parameters**h]j5)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMrhjubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjċh]hstruct zynqmp_dp *dp}(hjƋhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj‹ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMohjubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj݋hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjًhMohjڋubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjًhMohjubah}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j5)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMqhjubh)}(hIProgram the AUX clock divider and filter and register the DP AUX adapter.h]hIProgram the AUX clock divider and filter and register the DP AUX adapter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMphjubh)}(h **Return**h]j5)}(hj&h]hReturn}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj$ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMrhjubh)}(h#0 on success, error value otherwiseh]h#0 on success, error value otherwise}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMshjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"zynqmp_dp_aux_cleanup (C function)c.zynqmp_dp_aux_cleanuphNtauh1jhjzhhhNhNubj)}(hhh](j)}(h1void zynqmp_dp_aux_cleanup (struct zynqmp_dp *dp)h]j)}(h0void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp)h](jV)}(hvoidh]hvoid}(hjkhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjghhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjghhhjyhMubj)}(hzynqmp_dp_aux_cleanuph]j)}(hzynqmp_dp_aux_cleanuph]hzynqmp_dp_aux_cleanup}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjghhhjyhMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjƌhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjÌubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjȌmodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_aux_cleanupasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjghhhjyhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjchhhjyhMubah}(h]j^ah ](jjeh"]h$]h&]jj)jhuh1jhjyhMhj`hhubj)}(hhh]h)}(hCleanup the DP AUXh]hCleanup the DP AUX}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj(hhubah}(h]h ]h"]h$]h&]uh1jhj`hhhjyhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jCj&jCj'j(j)uh1jhhhjzhNhNubj+)}(hy**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Unregister the DP AUX adapter.h](h)}(h**Parameters**h]j5)}(hjMh]h Parameters}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjKubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjGubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjlh]hstruct zynqmp_dp *dp}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjfubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjfubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubah}(h]h ]h"]h$]h&]uh1j hjGubh)}(h**Description**h]j5)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjGubh)}(hUnregister the DP AUX adapter.h]hUnregister the DP AUX adapter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjGubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"zynqmp_dp_update_misc (C function)c.zynqmp_dp_update_mischNtauh1jhjzhhhNhNubj)}(hhh](j)}(h1void zynqmp_dp_update_misc (struct zynqmp_dp *dp)h]j)}(h0void zynqmp_dp_update_misc(struct zynqmp_dp *dp)h](jV)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hzynqmp_dp_update_misch]j)}(hzynqmp_dp_update_misch]hzynqmp_dp_update_misc}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjImodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_update_miscasbuh1hhj%ubj)}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj!ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhMubah}(h]jߍah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hWrite the misc registersh]hWrite the misc registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jĎj&jĎj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** The misc register values are stored in the structure, and this function applies the values into the registers.h](h)}(h**Parameters**h]j5)}(hjΎh]h Parameters}(hjЎhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj̎ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjȎubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjȎubh)}(h**Description**h]j5)}(hj(h]h Description}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj&ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjȎubh)}(hnThe misc register values are stored in the structure, and this function applies the values into the registers.h]hnThe misc register values are stored in the structure, and this function applies the values into the registers.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjȎubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!zynqmp_dp_set_format (C function)c.zynqmp_dp_set_formathNtauh1jhjzhhhNhNubj)}(hhh](j)}(hint zynqmp_dp_set_format (struct zynqmp_dp *dp, const struct drm_display_info *info, enum zynqmp_dpsub_format format, unsigned int bpc)h]j)}(hint zynqmp_dp_set_format(struct zynqmp_dp *dp, const struct drm_display_info *info, enum zynqmp_dpsub_format format, unsigned int bpc)h](jV)}(hinth]hint}(hjmhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjihhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjihhhj{hMubj)}(hzynqmp_dp_set_formath]j)}(hzynqmp_dp_set_formath]hzynqmp_dp_set_format}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjihhhj{hMubj)}(hn(struct zynqmp_dp *dp, const struct drm_display_info *info, enum zynqmp_dpsub_format format, unsigned int bpc)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjȏhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjŏubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjʏmodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_set_formatasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h#const struct drm_display_info *infoh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hstruct}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdrm_display_infoh]hdrm_display_info}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjWmodnameN classnameNjj)}j]jc.zynqmp_dp_set_formatasbuh1hhjubj)}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum zynqmp_dpsub_format formath](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hzynqmp_dpsub_formath]hzynqmp_dpsub_format}(hjŐhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjǐmodnameN classnameNjj)}j]jc.zynqmp_dp_set_formatasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hformath]hformat}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int bpch](jV)}(hunsignedh]hunsigned}(hj hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjV)}(hinth]hint}(hj&hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hbpch]hbpc}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjihhhj{hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjehhhj{hMubah}(h]j`ah ](jjeh"]h$]h&]jj)jhuh1jhj{hMhjbhhubj)}(hhh]h)}(hSet the input formath]hSet the input format}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjihhubah}(h]h ]h"]h$]h&]uh1jhjbhhhj{hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(hX[**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``const struct drm_display_info *info`` Display info ``enum zynqmp_dpsub_format format`` input format ``unsigned int bpc`` bits per component **Description** Update misc register values based on input **format** and **bpc**. **Return** 0 on success, or -EINVAL.h](h)}(h**Parameters**h]j5)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj )}(hhh](j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjƑhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj‘hMhjÑubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj‘hMhjubj)}(h5``const struct drm_display_info *info`` Display info h](j)}(h'``const struct drm_display_info *info``h]jV)}(hjh]h#const struct drm_display_info *info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(h Display infoh]h Display info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h1``enum zynqmp_dpsub_format format`` input format h](j)}(h#``enum zynqmp_dpsub_format format``h]jV)}(hjh]henum zynqmp_dpsub_format format}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(h input formath]h input format}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMhj5ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj4hMhjubj)}(h(``unsigned int bpc`` bits per component h](j)}(h``unsigned int bpc``h]jV)}(hjXh]hunsigned int bpc}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjVubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjRubj()}(hhh]h)}(hbits per componenth]hbits per component}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhMhjnubah}(h]h ]h"]h$]h&]uh1j'hjRubeh}(h]h ]h"]h$]h&]uh1jhjmhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j5)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hBUpdate misc register values based on input **format** and **bpc**.h](h+Update misc register values based on input }(hjhhhNhNubj5)}(h **format**h]hformat}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubh and }(hjhhhNhNubj5)}(h**bpc**h]hbpc}(hjÒhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(h **Return**h]j5)}(hjޒh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjܒubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(h0 on success, or -EINVAL.h]h0 on success, or -EINVAL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j5zynqmp_dp_encoder_mode_set_transfer_unit (C function)*c.zynqmp_dp_encoder_mode_set_transfer_unithNtauh1jhjzhhhNhNubj)}(hhh](j)}(hivoid zynqmp_dp_encoder_mode_set_transfer_unit (struct zynqmp_dp *dp, const struct drm_display_mode *mode)h]j)}(hhvoid zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp, const struct drm_display_mode *mode)h](jV)}(hvoidh]hvoid}(hj#hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj1hMubj)}(h(zynqmp_dp_encoder_mode_set_transfer_unith]j)}(h(zynqmp_dp_encoder_mode_set_transfer_unith]h(zynqmp_dp_encoder_mode_set_transfer_unit}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj1hMubj)}(h;(struct zynqmp_dp *dp, const struct drm_display_mode *mode)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj)}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjFsb*c.zynqmp_dp_encoder_mode_set_transfer_unitasbuh1hhj\ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjXubj)}(h#const struct drm_display_mode *modeh](j)}(hjh]hconst}(hjғhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΓubj)}(h h]h }(hjߓhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΓubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΓubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΓubh)}(hhh]j)}(hdrm_display_modeh]hdrm_display_mode}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j*c.zynqmp_dp_encoder_mode_set_transfer_unitasbuh1hhjΓubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΓubj)}(hjh]h*}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΓubj)}(hmodeh]hmode}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΓubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjXubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj1hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhj1hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj1hMhjhhubj)}(hhh]h)}(hSet the transfer unit valuesh]hSet the transfer unit values}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjkhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj1hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``const struct drm_display_mode *mode`` requested display mode **Description** Set the transfer unit, and calculate all transfer unit size related values. Calculation is based on DP and IP core specification.h](h)}(h**Parameters**h]j5)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj )}(hhh](j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjȔhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjĔhMhjŔubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjĔhMhjubj)}(h?``const struct drm_display_mode *mode`` requested display mode h](j)}(h'``const struct drm_display_mode *mode``h]jV)}(hjh]h#const struct drm_display_mode *mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hrequested display modeh]hrequested display mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j5)}(hj#h]h Description}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj!ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hSet the transfer unit, and calculate all transfer unit size related values. Calculation is based on DP and IP core specification.h]hSet the transfer unit, and calculate all transfer unit size related values. Calculation is based on DP and IP core specification.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.zynqmp_dp_encoder_mode_set_stream (C function)#c.zynqmp_dp_encoder_mode_set_streamhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hbvoid zynqmp_dp_encoder_mode_set_stream (struct zynqmp_dp *dp, const struct drm_display_mode *mode)h]j)}(havoid zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp, const struct drm_display_mode *mode)h](jV)}(hvoidh]hvoid}(hjhhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjdhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM3ubj)}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhhjvhM3ubj)}(h!zynqmp_dp_encoder_mode_set_streamh]j)}(h!zynqmp_dp_encoder_mode_set_streamh]h!zynqmp_dp_encoder_mode_set_stream}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjdhhhjvhM3ubj)}(h;(struct zynqmp_dp *dp, const struct drm_display_mode *mode)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjÕhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjŕmodnameN classnameNjj)}j]j)}jjsb#c.zynqmp_dp_encoder_mode_set_streamasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h#const struct drm_display_mode *modeh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hstruct}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdrm_display_modeh]hdrm_display_mode}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjRmodnameN classnameNjj)}j]jߕ#c.zynqmp_dp_encoder_mode_set_streamasbuh1hhjubj)}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hmodeh]hmode}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjdhhhjvhM3ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj`hhhjvhM3ubah}(h]j[ah ](jjeh"]h$]h&]jj)jhuh1jhjvhM3hj]hhubj)}(hhh]h)}(hConfigure the main streamh]hConfigure the main stream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM3hjhhubah}(h]h ]h"]h$]h&]uh1jhj]hhhjvhM3ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j˖j&j˖j'j(j)uh1jhhhjzhNhNubj+)}(hX **Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``const struct drm_display_mode *mode`` requested display mode **Description** Configure the main stream based on the requested mode **mode**. Calculation is based on IP core specification.h](h)}(h**Parameters**h]j5)}(hjՖh]h Parameters}(hjזhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjӖubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM7hjϖubj )}(hhh](j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM4hjubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM4hj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hM4hjubj)}(h?``const struct drm_display_mode *mode`` requested display mode h](j)}(h'``const struct drm_display_mode *mode``h]jV)}(hj-h]h#const struct drm_display_mode *mode}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj+ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM5hj'ubj()}(hhh]h)}(hrequested display modeh]hrequested display mode}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhM5hjCubah}(h]h ]h"]h$]h&]uh1j'hj'ubeh}(h]h ]h"]h$]h&]uh1jhjBhM5hjubeh}(h]h ]h"]h$]h&]uh1j hjϖubh)}(h**Description**h]j5)}(hjhh]h Description}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjfubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM7hjϖubh)}(hnConfigure the main stream based on the requested mode **mode**. Calculation is based on IP core specification.h](h6Configure the main stream based on the requested mode }(hj~hhhNhNubj5)7u}(h**mode**h]hmode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj~ubh0. Calculation is based on IP core specification.}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM6hjϖubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j0zynqmp_dp_disp_connected_live_layer (C function)%c.zynqmp_dp_disp_connected_live_layerhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hUstruct zynqmp_disp_layer * zynqmp_dp_disp_connected_live_layer (struct zynqmp_dp *dp)h]j)}(hSstruct zynqmp_disp_layer *zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj͗hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj̗hMubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjޗhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjۗubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}j#zynqmp_dp_disp_connected_live_layersb%c.zynqmp_dp_disp_connected_live_layerasbuh1hhjhhhj̗hMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj̗hMubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj̗hMubj)}(h#zynqmp_dp_disp_connected_live_layerh]j)}(hjh]h#zynqmp_dp_disp_connected_live_layer}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj̗hMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjYmodnameN classnameNjj)}j]j%c.zynqmp_dp_disp_connected_live_layerasbuh1hhj5ubj)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj1ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj̗hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhj̗hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj̗hMhjhhubj)}(hhh]h)}(h%Return the first connected live layerh]h%Return the first connected live layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj̗hMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jҘj&jҘj'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Return** The first connected live display layer or NULL if none of the live layers are connected.h](h)}(h**Parameters**h]j5)}(hjܘh]h Parameters}(hjޘhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjژubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj֘ubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1j hj֘ubh)}(h **Return**h]j5)}(hj6h]hReturn}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj4ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj֘ubh)}(hXThe first connected live display layer or NULL if none of the live layers are connected.h]hXThe first connected live display layer or NULL if none of the live layers are connected.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj֘ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'zynqmp_dp_set_test_pattern (C function)c.zynqmp_dp_set_test_patternhNtauh1jhjzhhhNhNubj)}(hhh](j)}(hbint zynqmp_dp_set_test_pattern (struct zynqmp_dp *dp, enum test_pattern pattern, u8 *const custom)h]j)}(haint zynqmp_dp_set_test_pattern(struct zynqmp_dp *dp, enum test_pattern pattern, u8 *const custom)h](jV)}(hinth]hint}(hj{hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjwhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwhhhjhMubj)}(hzynqmp_dp_set_test_patternh]j)}(hzynqmp_dp_set_test_patternh]hzynqmp_dp_set_test_pattern}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjwhhhjhMubj)}(hC(struct zynqmp_dp *dp, enum test_pattern pattern, u8 *const custom)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjřhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj֙hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjәubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjؙmodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_set_test_patternasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum test_pattern patternh](j)}(hjh]henum}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubh)}(hhh]j)}(h test_patternh]h test_pattern}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjJmodnameN classnameNjj)}j]jc.zynqmp_dp_set_test_patternasbuh1hhj&ubj)}(h h]h }(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(hpatternh]hpattern}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hu8 *const customh](h)}(hhh]j)}(hu8h]hu8}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.zynqmp_dp_set_test_patternasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hconst}(hjɚhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj֚hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hcustomh]hcustom}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjwhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjshhhjhMubah}(h]jnah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjphhubj)}(hhh]h)}(h%Configure the link for a test patternh]h%Configure the link for a test pattern}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhjphhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j&j&j&j'j(j)uh1jhhhjzhNhNubj+)}(hX **Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``enum test_pattern pattern`` The test pattern to configure ``u8 *const custom`` The custom pattern to use if **pattern** is ``TEST_80BIT_CUSTOM`` **Return** 0 on success, or negative errno on (DPCD) failureh](h)}(h**Parameters**h]j5)}(hj0h]h Parameters}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hj.ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj*ubj )}(hhh](j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjOh]hstruct zynqmp_dp *dp}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjMubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjIubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjeubah}(h]h ]h"]h$]h&]uh1j'hjIubeh}(h]h ]h"]h$]h&]uh1jhjdhMhjFubj)}(h<``enum test_pattern pattern`` The test pattern to configure h](j)}(h``enum test_pattern pattern``h]jV)}(hjh]henum test_pattern pattern}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hThe test pattern to configureh]hThe test pattern to configure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjFubj)}(hW``u8 *const custom`` The custom pattern to use if **pattern** is ``TEST_80BIT_CUSTOM`` h](j)}(h``u8 *const custom``h]jV)}(hjh]hu8 *const custom}(hjÛhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj()}(hhh]h)}(hAThe custom pattern to use if **pattern** is ``TEST_80BIT_CUSTOM``h](hThe custom pattern to use if }(hjڛhhhNhNubj5)}(h **pattern**h]hpattern}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjڛubh is }(hjڛhhhNhNubjV)}(h``TEST_80BIT_CUSTOM``h]hTEST_80BIT_CUSTOM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjڛubeh}(h]h ]h"]h$]h&]uh1hhj֛hMhjכubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj֛hMhjFubeh}(h]h ]h"]h$]h&]uh1j hj*ubh)}(h **Return**h]j5)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj*ubh)}(h10 on success, or negative errno on (DPCD) failureh]h10 on success, or negative errno on (DPCD) failure}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$zynqmp_dp_enable_vblank (C function)c.zynqmp_dp_enable_vblankhNtauh1jhjzhhhNhNubj)}(hhh](j)}(h3void zynqmp_dp_enable_vblank (struct zynqmp_dp *dp)h]j)}(h2void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)h](jV)}(hvoidh]hvoid}(hjahhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj]hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhjohMubj)}(hzynqmp_dp_enable_vblankh]j)}(hzynqmp_dp_enable_vblankh]hzynqmp_dp_enable_vblank}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]hhhjohMubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_enable_vblankasbuh1hhjubj)}(h h]h }(hjܜhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj]hhhjohMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjYhhhjohMubah}(h]jTah ](jjeh"]h$]h&]jj)jhuh1jhjohMhjVhhubj)}(hhh]h)}(h Enable vblankh]h Enable vblank}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjVhhhjohMubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j9j&j9j'j(j)uh1jhhhjzhNhNubj+)}(hr**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Enable vblank interrupth](h)}(h**Parameters**h]j5)}(hjCh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjAubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj=ubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjbh]hstruct zynqmp_dp *dp}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj\ubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMhjxubah}(h]h ]h"]h$]h&]uh1j'hj\ubeh}(h]h ]h"]h$]h&]uh1jhjwhMhjYubah}(h]h ]h"]h$]h&]uh1j hj=ubh)}(h**Description**h]j5)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj=ubh)}(hEnable vblank interrupth]hEnable vblank interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj=ubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_dp_disable_vblank (C function)c.zynqmp_dp_disable_vblankhNtauh1jhjzhhhNhNubj)}(hhh](j)}(h4void zynqmp_dp_disable_vblank (struct zynqmp_dp *dp)h]j)}(h3void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)h](jV)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjޝhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޝhhhjhM ubj)}(hzynqmp_dp_disable_vblankh]j)}(hzynqmp_dp_disable_vblankh]hzynqmp_dp_disable_vblank}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjޝhhhjhM ubj)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj?modnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_disable_vblankasbuh1hhjubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjޝhhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjڝhhhjhM ubah}(h]j՝ah ](jjeh"]h$]h&]jj)jhuh1jhjhM hjםhhubj)}(hhh]h)}(hDisable vblankh]hDisable vblank}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjםhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%jj&jj'j(j)uh1jhhhjzhNhNubj+)}(hs**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Disable vblank interrupth](h)}(h**Parameters**h]j5)}(hjĞh]h Parameters}(hjƞhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjžubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubj )}(hhh]j)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jV)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjݞubj()}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j'hjݞubeh}(h]h ]h"]h$]h&]uh1jhjhM hjڞubah}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j5)}(hjh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubh)}(hDisable vblank interrupth]hDisable vblank interrupt}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1j*hjzhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_dpsub_drm_handle_vblank (C function) c.zynqmp_dpsub_drm_handle_vblankhNtauh1jhjzhhhNhNubj)}(hhh](j)}(h@void zynqmp_dpsub_drm_handle_vblank (struct zynqmp_dpsub *dpsub)h]j)}(h?void zynqmp_dpsub_drm_handle_vblank(struct zynqmp_dpsub *dpsub)h](jV)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj_hhh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:147: ./drivers/gpu/drm/xlnx/zynqmp_kms.chM[ubj)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhhjqhM[ubj)}(hzynqmp_dpsub_drm_handle_vblankh]j)}(hzynqmp_dpsub_drm_handle_vblankh]hzynqmp_dpsub_drm_handle_vblank}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj_hhhjqhM[ubj)}(h(struct zynqmp_dpsub *dpsub)h]j)}(hstruct zynqmp_dpsub *dpsubh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dpsubh]h zynqmp_dpsub}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb c.zynqmp_dpsub_drm_handle_vblankasbuh1hhjubj)}(h h]h }(hjޟhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdpsubh]hdpsub}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj_hhhjqhM[ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj[hhhjqhM[ubah}(h]jVah ](jjeh"]h$]h&]jj)jhuh1jhjqhM[hjXhhubj)}(hhh]h)}(hHandle the vblank eventh]hHandle the vblank event}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:147: ./drivers/gpu/drm/xlnx/zynqmp_kms.chM[hj hhubah}(h]h ]h"]h$]h&]uh1jhjXhhhjqhM[ubeh}(h]h ](jfunctioneh"]h$]h&]j$jj%j;j&j;j'j(j)uh1jhhhjzhNhNubj+)}(h**Parameters** ``struct zynqmp_dpsub *dpsub`` DisplayPort subsystem **Description** This function handles the vblank interrupt, and sends an event to CRTC object. This will be called by the DP vblank interrupt handler.h](h)}(h**Parameters**h]j5)}(hjEh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjCubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:147: ./drivers/gpu/drm/xlnx/zynqmp_kms.chM_hj?ubj )}(hhh]j)}(h5``struct zynqmp_dpsub *dpsub`` DisplayPort subsystem h](j)}(h``struct zynqmp_dpsub *dpsub``h]jV)}(hjdh]hstruct zynqmp_dpsub *dpsub}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjbubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:147: ./drivers/gpu/drm/xlnx/zynqmp_kms.chM\hj^ubj()}(hhh]h)}(hDisplayPort subsystemh]hDisplayPort subsystem}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhM\hjzubah}(h]h ]h"]h$]h&]uh1j'hj^ubeh}(h]h ]h"]h$]h&]uh1jhjyhM\hj[ubah}(h]h ]h"]h$]h&]uh1j hj?ubh)}(h**Description**h]j5)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:147: ./drivers/gpu/drm/xlnx/zynqmp_kms.chM^hj?ubh)}(hThis function handles the vblank interrupt, and sends an event to CRTC object. This will be called by the DP vblank interrupt handler.h]hThis function handles the vblank interrupt, and sends an event to CRTC object. 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