sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/gpu/zynqmpmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/gpu/zynqmpmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h!SPDX-License-Identifier: GPL-2.0+h]h!SPDX-License-Identifier: GPL-2.0+}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh8/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp.rsthKubhsection)}(hhh](htitle)}(h/Xilinx ZynqMP Ultrascale+ DisplayPort Subsystemh]h/Xilinx ZynqMP Ultrascale+ DisplayPort Subsystem}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThis subsystem handles DisplayPort video and audio output on the ZynqMP. It supports in-memory framebuffers with the DisplayPort DMA controller (xilinx-dpdma), as well as "live" video and audio from the programmable logic (PL). This subsystem can perform several transformations, including color space conversion, alpha blending, and audio mixing, although not all features are currently supported.h]hXThis subsystem handles DisplayPort video and audio output on the ZynqMP. It supports in-memory framebuffers with the DisplayPort DMA controller (xilinx-dpdma), as well as “live” video and audio from the programmable logic (PL). This subsystem can perform several transformations, including color space conversion, alpha blending, and audio mixing, although not all features are currently supported.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hdebugfsh]hdebugfs}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hTo support debugging and compliance testing, several test modes can be enabled though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/ control the DisplayPort test modes:h]hTo support debugging and compliance testing, several test modes can be enabled though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/ control the DisplayPort test modes:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hXactive: Writing a 1 to this file will activate test mode, and writing a 0 will deactivate test mode. Writing a 1 or 0 when the test mode is already active/inactive will re-activate/re-deactivate test mode. When test mode is inactive, changes made to other files will have no (immediate) effect, although the settings will be saved for when test mode is activated. When test mode is active, changes made to other files will apply immediately. h](hterm)}(hactive:h]hactive:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhhubh definition)}(hhh]h)}(hXWriting a 1 to this file will activate test mode, and writing a 0 will deactivate test mode. Writing a 1 or 0 when the test mode is already active/inactive will re-activate/re-deactivate test mode. When test mode is inactive, changes made to other files will have no (immediate) effect, although the settings will be saved for when test mode is activated. When test mode is active, changes made to other files will apply immediately.h]hXWriting a 1 to this file will activate test mode, and writing a 0 will deactivate test mode. Writing a 1 or 0 when the test mode is already active/inactive will re-activate/re-deactivate test mode. When test mode is inactive, changes made to other files will have no (immediate) effect, although the settings will be saved for when test mode is activated. When test mode is active, changes made to other files will apply immediately.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubh)}(h"custom: Custom test pattern value h](j)}(hcustom:h]hcustom:}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj2ubj)}(hhh]h)}(hCustom test pattern valueh]hCustom test pattern value}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjDubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hYdownspread: Enable/disable clock downspreading (spread-spectrum clocking) by writing 1/0 h](j)}(h downspread:h]h downspread:}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK#hjaubj)}(hhh]h)}(hLEnable/disable clock downspreading (spread-spectrum clocking) by writing 1/0h]hLEnable/disable clock downspreading (spread-spectrum clocking) by writing 1/0}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjsubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1hhhhK#hhhhubh)}(h*enhanced: Enable/disable enhanced framing h](j)}(h enhanced:h]h enhanced:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK&hjubj)}(hhh]h)}(hEnable/disable enhanced framingh]hEnable/disable enhanced framing}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK&hhhhubh)}(hignore_aux_errors: Ignore AUX errors when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active) and affect all AUX transfers. h](j)}(hignore_aux_errors:h]hignore_aux_errors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK+hjubj)}(hhh]h)}(hIgnore AUX errors when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active) and affect all AUX transfers.h]hIgnore AUX errors when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active) and affect all AUX transfers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK+hhhhubh)}(hignore_hpd: Ignore hotplug events (such as cable removals or monitor link retraining requests) when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active). h](j)}(h ignore_hpd:h]h ignore_hpd:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK0hjubj)}(hhh]h)}(hIgnore hotplug events (such as cable removals or monitor link retraining requests) when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active).h]hIgnore hotplug events (such as cable removals or monitor link retraining requests) when set to 1. Writes to this file take effect immediately (regardless of whether test mode is active).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK0hhhhubh)}(hIlaneX_preemphasis: Preemphasis from 0 (lowest) to 2 (highest) for lane X h](j)}(hlaneX_preemphasis:h]hlaneX_preemphasis:}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK3hjubj)}(hhh]h)}(h5Preemphasis from 0 (lowest) to 2 (highest) for lane Xh]h5Preemphasis from 0 (lowest) to 2 (highest) for lane X}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK3hhhhubh)}(hElaneX_swing: Voltage swing from 0 (lowest) to 3 (highest) for lane X h](j)}(h laneX_swing:h]h laneX_swing:}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK6hjLubj)}(hhh]h)}(h7Voltage swing from 0 (lowest) to 3 (highest) for lane Xh]h7Voltage swing from 0 (lowest) to 3 (highest) for lane X}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hj^ubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1hhhhK6hhhhubh)}(h+lanes: Number of lanes to use (1, 2, or 4) h](j)}(hlanes:h]hlanes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK9hj{ubj)}(hhh]h)}(h#Number of lanes to use (1, 2, or 4)h]h#Number of lanes to use (1, 2, or 4)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1hhhhK9hhhhubh)}(hXApattern: Test pattern. May be one of: video Use regular video input symbol-error Symbol error measurement pattern prbs7 Output of the PRBS7 (x^7 + x^6 + 1) polynomial 80bit-custom A custom 80-bit pattern cp2520 HBR2 compliance eye pattern tps1 Link training symbol pattern TPS1 (/D10.2/) tps2 Link training symbol pattern TPS2 tps3 Link training symbol pattern TPS3 (for HBR2) h](j)}(hpattern:h]hpattern:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKThjubj)}(hhh](h)}(hTest pattern. May be one of:h]hTest pattern. May be one of:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKThhhhubh)}(horate: Rate in hertz. One of * 5400000000 (HBR2) * 2700000000 (HBR) * 1620000000 (RBR) h](j)}(hrate:h]hrate:}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK[hjfubj)}(hhh](h)}(hRate in hertz. One ofh]hRate in hertz. One of}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjxubj)}(h:* 5400000000 (HBR2) * 2700000000 (HBR) * 1620000000 (RBR) h]h bullet_list)}(hhh](h list_item)}(h5400000000 (HBR2)h]h)}(hjh]h5400000000 (HBR2)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h2700000000 (HBR)h]h)}(hjh]h2700000000 (HBR)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h1620000000 (RBR) h]h)}(h1620000000 (RBR)h]h1620000000 (RBR)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet*uh1jhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhhhKYhjxubeh}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1hhhhK[hhhhubeh}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hGYou can dump the displayport test settings with the following command::h]hFYou can dump the displayport test settings with the following command:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hhhhubh literal_block)}(hfor prop in /sys/kernel/debug/dri/1/DP-1/test/*; do printf '%-17s ' ${prop##*/} if [ ${prop##*/} = custom ]; then hexdump -C $prop | head -1 else cat $prop fi doneh]hfor prop in /sys/kernel/debug/dri/1/DP-1/test/*; do printf '%-17s ' ${prop##*/} if [ ${prop##*/} = custom ]; then hexdump -C $prop | head -1 else cat $prop fi done}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhK_hhhhubh)}(h&The output could look something like::h]h%The output could look something like:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhhubj )}(hXWactive 1 custom 00000000 00 00 00 00 00 00 00 00 00 00 |..........| downspread 0 enhanced 1 ignore_aux_errors 1 ignore_hpd 1 lane0_preemphasis 0 lane0_swing 3 lane1_preemphasis 0 lane1_swing 3 lanes 2 pattern prbs7 rate 1620000000h]hXWactive 1 custom 00000000 00 00 00 00 00 00 00 00 00 00 |..........| downspread 0 enhanced 1 ignore_aux_errors 1 ignore_hpd 1 lane0_preemphasis 0 lane0_swing 3 lane1_preemphasis 0 lane1_swing 3 lanes 2 pattern prbs7 rate 1620000000}hj&sbah}(h]h ]h"]h$]h&]hhuh1jhhhKjhhhhubh)}(hThe recommended test procedure is to connect the board to a monitor, configure test mode, activate test mode, and then disconnect the cable and connect it to your test equipment of choice. For example, one sequence of commands could be::h]hThe recommended test procedure is to connect the board to a monitor, configure test mode, activate test mode, and then disconnect the cable and connect it to your test equipment of choice. For example, one sequence of commands could be:}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhhhhubj )}(hXGecho 1 > /sys/kernel/debug/dri/1/DP-1/test/enhanced echo tps1 > /sys/kernel/debug/dri/1/DP-1/test/pattern echo 1620000000 > /sys/kernel/debug/dri/1/DP-1/test/rate echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_aux_errors echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_hpd echo 1 > /sys/kernel/debug/dri/1/DP-1/test/activeh]hXGecho 1 > /sys/kernel/debug/dri/1/DP-1/test/enhanced echo tps1 > /sys/kernel/debug/dri/1/DP-1/test/pattern echo 1620000000 > /sys/kernel/debug/dri/1/DP-1/test/rate echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_aux_errors echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_hpd echo 1 > /sys/kernel/debug/dri/1/DP-1/test/active}hjBsbah}(h]h ]h"]h$]h&]hhuh1jhhhK}hhhhubh)}(h@at which point the cable could be disconnected from the monitor.h]h@at which point the cable could be disconnected from the monitor.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]debugfsah ]h"]debugfsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Internalsh]h Internals}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhhhhhKubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlezynqmp_dpsub_layer_id (C enum)c.zynqmp_dpsub_layer_idhNtauh1jwhjfhhhNhNubhdesc)}(hhh](hdesc_signature)}(hzynqmp_dpsub_layer_idh]hdesc_signature_line)}(henum zynqmp_dpsub_layer_idh](hdesc_sig_keyword)}(henumh]henum}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hzynqmp_dpsub_layer_idh]h desc_sig_name)}(hjh]hzynqmp_dpsub_layer_id}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hh add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(hLayer identifierh]hLayer identifier}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK$hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](cenumeh"]h$]h&]domainj objtypej desctypej noindex noindexentrynocontentsentryuh1jhhhjfhNhNubh container)}(hd**Constants** ``ZYNQMP_DPSUB_LAYER_VID`` Video layer ``ZYNQMP_DPSUB_LAYER_GFX`` Graphics layerh](h)}(h **Constants**h]hstrong)}(hjh]h Constants}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK(hjubh)}(hhh](h)}(h'``ZYNQMP_DPSUB_LAYER_VID`` Video layer h](j)}(h``ZYNQMP_DPSUB_LAYER_VID``h]hliteral)}(hj?h]hZYNQMP_DPSUB_LAYER_VID}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj=ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK+hj9ubj)}(hhh]h)}(h Video layerh]h Video layer}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhK+hjWubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1hhjVhK+hj6ubh)}(h)``ZYNQMP_DPSUB_LAYER_GFX`` Graphics layerh](j)}(h``ZYNQMP_DPSUB_LAYER_GFX``h]jB)}(hjzh]hZYNQMP_DPSUB_LAYER_GFX}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjxubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK-hjtubj)}(hhh]h)}(hGraphics layerh]hGraphics layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:137: ./drivers/gpu/drm/xlnx/zynqmp_disp.hhK.hjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1hhjhK-hj6ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dpsub (C struct)c.zynqmp_dpsubhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h zynqmp_dpsubh]j)}(hstruct zynqmp_dpsubh](j)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(h zynqmp_dpsubh]j)}(hjh]h zynqmp_dpsub}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hZynqMP DisplayPort Subsystemh]hZynqMP DisplayPort Subsystem}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK/hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j structeh"]h$]h&]jj jj/jj/jjjuh1jhhhjfhNhNubj)}(hX**Definition**:: struct zynqmp_dpsub { struct device *dev; struct clk *apb_clk; struct clk *vid_clk; bool vid_clk_from_ps; struct clk *aud_clk; bool aud_clk_from_ps; unsigned int connected_ports; bool dma_enabled; struct zynqmp_dpsub_drm *drm; struct drm_bridge *bridge; struct zynqmp_disp *disp; struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; struct zynqmp_dp *dp; unsigned int dma_align; struct zynqmp_dpsub_audio *audio; }; **Members** ``dev`` The physical device ``apb_clk`` The APB clock ``vid_clk`` Video clock ``vid_clk_from_ps`` True of the video clock comes from PS, false from PL ``aud_clk`` Audio clock ``aud_clk_from_ps`` True of the audio clock comes from PS, false from PL ``connected_ports`` Bitmask of connected ports in the device tree ``dma_enabled`` True if the DMA interface is enabled, false if the DPSUB is driven by the live input ``drm`` The DRM/KMS device data ``bridge`` The DP encoder bridge ``disp`` The display controller ``layers`` Video and graphics layers ``dp`` The DisplayPort controller ``dma_align`` DMA alignment constraint (must be a power of 2) ``audio`` DP audio datah](h)}(h**Definition**::h](j!)}(h**Definition**h]h Definition}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj7ubh:}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK3hj3ubj )}(hXstruct zynqmp_dpsub { struct device *dev; struct clk *apb_clk; struct clk *vid_clk; bool vid_clk_from_ps; struct clk *aud_clk; bool aud_clk_from_ps; unsigned int connected_ports; bool dma_enabled; struct zynqmp_dpsub_drm *drm; struct drm_bridge *bridge; struct zynqmp_disp *disp; struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; struct zynqmp_dp *dp; unsigned int dma_align; struct zynqmp_dpsub_audio *audio; };h]hXstruct zynqmp_dpsub { struct device *dev; struct clk *apb_clk; struct clk *vid_clk; bool vid_clk_from_ps; struct clk *aud_clk; bool aud_clk_from_ps; unsigned int connected_ports; bool dma_enabled; struct zynqmp_dpsub_drm *drm; struct drm_bridge *bridge; struct zynqmp_disp *disp; struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; struct zynqmp_dp *dp; unsigned int dma_align; struct zynqmp_dpsub_audio *audio; };}hjTsbah}(h]h ]h"]h$]h&]hhuh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK5hj3ubh)}(h **Members**h]j!)}(hjeh]hMembers}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j hjcubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhKGhj3ubh)}(hhh](h)}(h``dev`` The physical device h](j)}(h``dev``h]jB)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK1hj~ubj)}(hhh]h)}(hThe physical deviceh]hThe physical device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK1hjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1hhjhK1hj{ubh)}(h``apb_clk`` The APB clock h](j)}(h ``apb_clk``h]jB)}(hjh]hapb_clk}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK2hjubj)}(hhh]h)}(h The APB clockh]h The APB clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK2hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhK2hj{ubh)}(h``vid_clk`` Video clock h](j)}(h ``vid_clk``h]jB)}(hjh]hvid_clk}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK3hjubj)}(hhh]h)}(h Video clockh]h Video clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK3hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hK3hj{ubh)}(hI``vid_clk_from_ps`` True of the video clock comes from PS, false from PL h](j)}(h``vid_clk_from_ps``h]jB)}(hj/h]hvid_clk_from_ps}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj-ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK4hj)ubj)}(hhh]h)}(h4True of the video clock comes from PS, false from PLh]h4True of the video clock comes from PS, false from PL}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhK4hjEubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1hhjDhK4hj{ubh)}(h``aud_clk`` Audio clock h](j)}(h ``aud_clk``h]jB)}(hjhh]haud_clk}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjfubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK5hjbubj)}(hhh]h)}(h Audio clockh]h Audio clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hK5hj~ubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1hhj}hK5hj{ubh)}(hI``aud_clk_from_ps`` True of the audio clock comes from PS, false from PL h](j)}(h``aud_clk_from_ps``h]jB)}(hjh]haud_clk_from_ps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK6hjubj)}(hhh]h)}(h4True of the audio clock comes from PS, false from PLh]h4True of the audio clock comes from PS, false from PL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhK6hj{ubh)}(hB``connected_ports`` Bitmask of connected ports in the device tree h](j)}(h``connected_ports``h]jB)}(hjh]hconnected_ports}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK7hjubj)}(hhh]h)}(h-Bitmask of connected ports in the device treeh]h-Bitmask of connected ports in the device tree}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhK7hj{ubh)}(he``dma_enabled`` True if the DMA interface is enabled, false if the DPSUB is driven by the live input h](j)}(h``dma_enabled``h]jB)}(hj h]h dma_enabled}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK9hj ubj)}(hhh]h)}(hTTrue if the DMA interface is enabled, false if the DPSUB is driven by the live inputh]hTTrue if the DMA interface is enabled, false if the DPSUB is driven by the live input}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK8hj) ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj( hK9hj{ubh)}(h ``drm`` The DRM/KMS device data h](j)}(h``drm``h]jB)}(hjM h]hdrm}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjK ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK:hjG ubj)}(hhh]h)}(hThe DRM/KMS device datah]hThe DRM/KMS device data}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb hK:hjc ubah}(h]h ]h"]h$]h&]uh1jhjG ubeh}(h]h ]h"]h$]h&]uh1hhjb hK:hj{ubh)}(h!``bridge`` The DP encoder bridge h](j)}(h ``bridge``h]jB)}(hj h]hbridge}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK;hj ubj)}(hhh]h)}(hThe DP encoder bridgeh]hThe DP encoder bridge}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK;hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hK;hj{ubh)}(h ``disp`` The display controller h](j)}(h``disp``h]jB)}(hj h]hdisp}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhKhj+ ubj)}(hhh]h)}(hThe DisplayPort controllerh]hThe DisplayPort controller}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF hK>hjG ubah}(h]h ]h"]h$]h&]uh1jhj+ ubeh}(h]h ]h"]h$]h&]uh1hhjF hK>hj{ubh)}(h>``dma_align`` DMA alignment constraint (must be a power of 2) h](j)}(h ``dma_align``h]jB)}(hjj h]h dma_align}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjh ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK?hjd ubj)}(hhh]h)}(h/DMA alignment constraint (must be a power of 2)h]h/DMA alignment constraint (must be a power of 2)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK?hj ubah}(h]h ]h"]h$]h&]uh1jhjd ubeh}(h]h ]h"]h$]h&]uh1hhj hK?hj{ubh)}(h``audio`` DP audio datah](j)}(h ``audio``h]jB)}(hj h]haudio}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK?hj ubj)}(hhh]h)}(h DP audio datah]h DP audio data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:139: ./drivers/gpu/drm/xlnx/zynqmp_dpsub.hhK@hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hK?hj{ubeh}(h]h ]h"]h$]h&]uh1hhj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dpsub_drm (C struct)c.zynqmp_dpsub_drmhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hzynqmp_dpsub_drmh]j)}(hstruct zynqmp_dpsub_drmh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hzynqmp_dpsub_drmh]j)}(hj h]hzynqmp_dpsub_drm}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj)}(hhh]h)}(h)ZynqMP DisplayPort Subsystem DRM/KMS datah]h)ZynqMP DisplayPort Subsystem DRM/KMS data}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj< hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](j structeh"]h$]h&]jj jjW jjW jjjuh1jhhhjfhNhNubj)}(hX**Definition**:: struct zynqmp_dpsub_drm { struct zynqmp_dpsub *dpsub; struct drm_device dev; struct drm_plane planes[ZYNQMP_DPSUB_NUM_LAYERS]; struct drm_crtc crtc; struct drm_encoder encoder; }; **Members** ``dpsub`` Backpointer to the DisplayPort subsystem ``dev`` The DRM/KMS device ``planes`` The DRM planes ``crtc`` The DRM CRTC ``encoder`` The dummy DRM encoderh](h)}(h**Definition**::h](j!)}(h**Definition**h]h Definition}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj_ ubh:}(hj_ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj[ ubj )}(hstruct zynqmp_dpsub_drm { struct zynqmp_dpsub *dpsub; struct drm_device dev; struct drm_plane planes[ZYNQMP_DPSUB_NUM_LAYERS]; struct drm_crtc crtc; struct drm_encoder encoder; };h]hstruct zynqmp_dpsub_drm { struct zynqmp_dpsub *dpsub; struct drm_device dev; struct drm_plane planes[ZYNQMP_DPSUB_NUM_LAYERS]; struct drm_crtc crtc; struct drm_encoder encoder; };}hj| sbah}(h]h ]h"]h$]h&]hhuh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj[ ubh)}(h **Members**h]j!)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhK'hj[ ubh)}(hhh](h)}(h3``dpsub`` Backpointer to the DisplayPort subsystem h](j)}(h ``dpsub``h]jB)}(hj h]hdpsub}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubj)}(hhh]h)}(h(Backpointer to the DisplayPort subsystemh]h(Backpointer to the DisplayPort subsystem}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hKhj ubh)}(h``dev`` The DRM/KMS device h](j)}(h``dev``h]jB)}(hj h]hdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubj)}(hhh]h)}(hThe DRM/KMS deviceh]hThe DRM/KMS device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hKhj ubh)}(h``planes`` The DRM planes h](j)}(h ``planes``h]jB)}(hj h]hplanes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubj)}(hhh]h)}(hThe DRM planesh]hThe DRM planes}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3 hKhj4 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj3 hKhj ubh)}(h``crtc`` The DRM CRTC h](j)}(h``crtc``h]jB)}(hjW h]hcrtc}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjU ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhjQ ubj)}(hhh]h)}(h The DRM CRTCh]h The DRM CRTC}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl hKhjm ubah}(h]h ]h"]h$]h&]uh1jhjQ ubeh}(h]h ]h"]h$]h&]uh1hhjl hKhj ubh)}(h!``encoder`` The dummy DRM encoderh](j)}(h ``encoder``h]jB)}(hj h]hencoder}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubj)}(hhh]h)}(hThe dummy DRM encoderh]hThe dummy DRM encoder}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:141: ./drivers/gpu/drm/xlnx/zynqmp_kms.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hKhj ubeh}(h]h ]h"]h$]h&]uh1hhj[ ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j zynqmp_dpsub_layer_mode (C enum)c.zynqmp_dpsub_layer_modehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hzynqmp_dpsub_layer_modeh]j)}(henum zynqmp_dpsub_layer_modeh](j)}(hjh]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hzynqmp_dpsub_layer_modeh]j)}(hj h]hzynqmp_dpsub_layer_mode}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj)}(hhh]h)}(h Layer modeh]h Layer mode}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKEhj) hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](j enumeh"]h$]h&]jj jjD jjD jjjuh1jhhhjfhNhNubj)}(hx**Constants** ``ZYNQMP_DPSUB_LAYER_NONLIVE`` non-live (memory) mode ``ZYNQMP_DPSUB_LAYER_LIVE`` live (stream) modeh](h)}(h **Constants**h]j!)}(hjN h]h Constants}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjL ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKIhjH ubh)}(hhh](h)}(h6``ZYNQMP_DPSUB_LAYER_NONLIVE`` non-live (memory) mode h](j)}(h``ZYNQMP_DPSUB_LAYER_NONLIVE``h]jB)}(hjm h]hZYNQMP_DPSUB_LAYER_NONLIVE}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjk ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKLhjg ubj)}(hhh]h)}(hnon-live (memory) modeh]hnon-live (memory) mode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKLhj ubah}(h]h ]h"]h$]h&]uh1jhjg ubeh}(h]h ]h"]h$]h&]uh1hhj hKLhjd ubh)}(h.``ZYNQMP_DPSUB_LAYER_LIVE`` live (stream) modeh](j)}(h``ZYNQMP_DPSUB_LAYER_LIVE``h]jB)}(hj h]hZYNQMP_DPSUB_LAYER_LIVE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKNhj ubj)}(hhh]h)}(hlive (stream) modeh]hlive (stream) mode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKOhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hKNhjd ubeh}(h]h ]h"]h$]h&]uh1hhjH ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_disp_format (C struct)c.zynqmp_disp_formathNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hzynqmp_disp_formath]j)}(hstruct zynqmp_disp_formath](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKUubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKUubj)}(hzynqmp_disp_formath]j)}(hj h]hzynqmp_disp_format}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hKUubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj hKUubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKUhj hhubj)}(hhh]h)}(h$Display subsystem format informationh]h$Display subsystem format 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formats}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohKThjpubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1hhjohKThjubh)}(h+``sf`` Scaling factors for color componentsh](j)}(h``sf``h]jB)}(hjh]hsf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKThjubj)}(hhh]h)}(h$Scaling factors for color componentsh]h$Scaling factors for color components}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKUhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKThjubeh}(h]h ]h"]h$]h&]uh1hhj^ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j zynqmp_disp_layer_dma (C struct)c.zynqmp_disp_layer_dmahNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hzynqmp_disp_layer_dmah]j)}(hstruct zynqmp_disp_layer_dmah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h 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chunk for dma_interleaved_template}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKchj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj#hKbhjubeh}(h]h ]h"]h$]h&]uh1hhjKubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j!zynqmp_disp_layer_info (C struct)c.zynqmp_disp_layer_infohNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hzynqmp_disp_layer_infoh]j)}(hstruct zynqmp_disp_layer_infoh](j)}(hjh]hstruct}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKiubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhhjuhKiubj)}(hzynqmp_disp_layer_infoh]j)}(hjbh]hzynqmp_disp_layer_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjdhhhjuhKiubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj`hhhjuhKiubah}(h]j[ah ](jjeh"]h$]h&]jj)jhuh1jhjuhKihj]hhubj)}(hhh]h)}(hStatic layer informationh]hStatic layer information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKkhjhhubah}(h]h ]h"]h$]h&]uh1jhj]hhhjuhKiubeh}(h]h ](j structeh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(hXE**Definition**:: struct zynqmp_disp_layer_info { const struct zynqmp_disp_format *formats; unsigned int num_formats; unsigned int num_channels; }; **Members** ``formats`` Array of supported formats ``num_formats`` Number of formats in **formats** array ``num_channels`` Number of DMA channelsh](h)}(h**Definition**::h](j!)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKohjubj )}(hstruct zynqmp_disp_layer_info { const struct zynqmp_disp_format *formats; unsigned int num_formats; unsigned int num_channels; };h]hstruct zynqmp_disp_layer_info { const struct zynqmp_disp_format *formats; unsigned int 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struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; const struct zynqmp_disp_format *disp_fmt; const struct drm_format_info *drm_fmt; enum zynqmp_dpsub_layer_mode mode; }; **Members** ``id`` Layer ID ``disp`` Back pointer to struct zynqmp_disp ``info`` Static layer information ``dmas`` DMA channels ``disp_fmt`` Current format information ``drm_fmt`` Current DRM format information ``mode`` Current operation modeh](h)}(h**Definition**::h](j!)}(h**Definition**h]h Definition}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjWubh:}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK{hjSubj )}(hXUstruct zynqmp_disp_layer { enum zynqmp_dpsub_layer_id id; struct zynqmp_disp *disp; const struct zynqmp_disp_layer_info *info; struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; const struct zynqmp_disp_format *disp_fmt; const struct drm_format_info *drm_fmt; enum zynqmp_dpsub_layer_mode mode; };h]hXUstruct zynqmp_disp_layer { enum zynqmp_dpsub_layer_id id; struct zynqmp_disp *disp; const struct zynqmp_disp_layer_info *info; struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; const struct zynqmp_disp_format *disp_fmt; const struct drm_format_info *drm_fmt; enum zynqmp_dpsub_layer_mode mode; };}hjtsbah}(h]h ]h"]h$]h&]hhuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK}hjSubh)}(h **Members**h]j!)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjSubh)}(hhh](h)}(h``id`` Layer ID h](j)}(h``id``h]jB)}(hjh]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKyhjubj)}(hhh]h)}(hLayer IDh]hLayer ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKyhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKyhjubh)}(h,``disp`` Back pointer to struct zynqmp_disp h](j)}(h``disp``h]jB)}(hjh]hdisp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKzhjubj)}(hhh]h)}(h"Back pointer to struct zynqmp_disph]h"Back pointer to struct zynqmp_disp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKzhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKzhjubh)}(h"``info`` Static layer information h](j)}(h``info``h]jB)}(hjh]hinfo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK{hjubj)}(hhh]h)}(hStatic layer informationh]hStatic layer information}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hK{hj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj+hK{hjubh)}(h``dmas`` DMA channels h](j)}(h``dmas``h]jB)}(hjOh]hdmas}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjMubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK|hjIubj)}(hhh]h)}(h DMA channelsh]h DMA channels}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhK|hjeubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1hhjdhK|hjubh)}(h(``disp_fmt`` Current format information h](j)}(h ``disp_fmt``h]jB)}(hjh]hdisp_fmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK}hjubj)}(hhh]h)}(hCurrent format informationh]hCurrent format information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhK}hjubh)}(h+``drm_fmt`` Current DRM format information h](j)}(h ``drm_fmt``h]jB)}(hjh]hdrm_fmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK~hjubj)}(hhh]h)}(hCurrent DRM format informationh]hCurrent DRM format information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhK~hjubh)}(h``mode`` Current operation modeh](j)}(h``mode``h]jB)}(hjh]hmode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chK~hjubj)}(hhh]h)}(hCurrent operation modeh]hCurrent operation mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhK~hjubeh}(h]h ]h"]h$]h&]uh1hhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_disp (C struct) c.zynqmp_disphNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h zynqmp_disph]j)}(hstruct zynqmp_disph](j)}(hjh]hstruct}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhjahKubj)}(h zynqmp_disph]j)}(hjNh]h zynqmp_disp}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubah}(h]h ](jjeh"]h$]h&]hhuh1jhjPhhhjahKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjLhhhjahKubah}(h]jGah ](jjeh"]h$]h&]jj)jhuh1jhjahKhjIhhubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhjIhhhjahKubeh}(h]h ](j structeh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(hX**Definition**:: struct zynqmp_disp { struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *blend; void __iomem *avbuf; struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS]; }; **Members** ``dev`` Device structure ``dpsub`` Display subsystem ``blend`` Register I/O base address for the blender ``avbuf`` Register I/O base address for the audio/video buffer manager ``layers`` Layers (planes)h](h)}(h**Definition**::h](j!)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubj )}(hstruct zynqmp_disp { struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *blend; void __iomem *avbuf; struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS]; };h]hstruct zynqmp_disp { struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *blend; void __iomem *avbuf; struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS]; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubh)}(h **Members**h]j!)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubh)}(hhh](h)}(h``dev`` Device structure h](j)}(h``dev``h]jB)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubj)}(hhh]h)}(hDevice structureh]hDevice structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``dpsub`` Display subsystem h](j)}(h ``dpsub``h]jB)}(hj<h]hdpsub}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj:ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhj6ubj)}(hhh]h)}(hDisplay subsystemh]hDisplay subsystem}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhKhjRubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1hhjQhKhjubh)}(h4``blend`` Register I/O base address for the blender h](j)}(h ``blend``h]jB)}(hjuh]hblend}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjoubj)}(hhh]h)}(h)Register I/O base address for the blenderh]h)Register I/O base address for the blender}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(hG``avbuf`` Register I/O base address for the audio/video buffer manager h](j)}(h ``avbuf``h]jB)}(hjh]havbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chKhjubj)}(hhh]h)}(hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hlayerh]hlayer}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj{ubj)}(h$const struct zynqmp_disp_format *fmth](j)}(hconsth]hconst}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubh)}(hhh]j)}(hzynqmp_disp_formath]hzynqmp_disp_format}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]jc.zynqmp_disp_avbuf_set_formatasbuh1hhjnubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(hfmth]hfmt}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj{ubeh}(h]h ]h"]h$]h&]hhuh1jyhj=hhhjRhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj9hhhjRhMubah}(h]j4ah ](jjeh"]h$]h&]jj)jhuh1jhjRhMhj6hhubj)}(hhh]h)}(h Set the input format for a layerh]h Set the input format for a layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj6hhhjRhMubeh}(h]h ](j functioneh"]h$]h&]jj jj'jj'jjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer ``const struct zynqmp_disp_format *fmt`` The format information **Description** Set the video buffer manager format for **layer** to **fmt**.h](h)}(h**Parameters**h]j!)}(hj1h]h Parameters}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj/ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj+ubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hjPh]hstruct zynqmp_disp *disp}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjJubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMhjfubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1hhjehMhjGubh)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hjh]hstruct zynqmp_disp_layer *layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubj)}(hhh]h)}(h The layerh]h The layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjGubh)}(h@``const struct zynqmp_disp_format *fmt`` The format information h](j)}(h(``const struct zynqmp_disp_format *fmt``h]jB)}(hjh]h$const struct zynqmp_disp_format *fmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubj)}(hhh]h)}(hThe format informationh]hThe format information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjGubeh}(h]h ]h"]h$]h&]uh1hhj+ubh)}(h**Description**h]j!)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj+ubh)}(h=Set the video buffer manager format for **layer** to **fmt**.h](h(Set the video buffer manager format for }(hjhhhNhNubj!)}(h **layer**h]hlayer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh to }(hjhhhNhNubj!)}(h**fmt**h]hfmt}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j1zynqmp_disp_avbuf_set_clocks_sources (C function)&c.zynqmp_disp_avbuf_set_clocks_sourceshNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hvoid zynqmp_disp_avbuf_set_clocks_sources (struct zynqmp_disp *disp, bool video_from_ps, bool audio_from_ps, bool timings_internal)h]j)}(hvoid zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp *disp, bool video_from_ps, bool audio_from_ps, bool timings_internal)h](jB)}(hvoidh]hvoid}(hjfhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjbhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhjthMubj)}(h$zynqmp_disp_avbuf_set_clocks_sourcesh]j)}(h$zynqmp_disp_avbuf_set_clocks_sourcesh]h$zynqmp_disp_avbuf_set_clocks_sources}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjbhhhjthMubjz)}(hY(struct zynqmp_disp *disp, bool video_from_ps, bool audio_from_ps, bool timings_internal)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb&c.zynqmp_disp_avbuf_set_clocks_sourcesasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdisph]hdisp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hbool video_from_psh](jB)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h video_from_psh]h video_from_ps}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hbool audio_from_psh](jB)}(hjh]hbool}(hjJhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjFubj)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubj)}(h audio_from_psh]h audio_from_ps}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hbool timings_internalh](jB)}(hjh]hbool}(hj~hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjzubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(htimings_internalh]htimings_internal}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jyhjbhhhjthMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj^hhhjthMubah}(h]jYah ](jjeh"]h$]h&]jj)jhuh1jhjthMhj[hhubj)}(hhh]h)}(hSet the clocks sourcesh]hSet the clocks sources}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj[hhhjthMubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_disp *disp`` Display controller ``bool video_from_ps`` True if the video clock originates from the PS ``bool audio_from_ps`` True if the audio clock originates from the PS ``bool timings_internal`` True if video timings are generated internally **Description** Set the source for the video and audio clocks, as well as for the video timings. Clocks can originate from the PS or PL, and timings can be generated internally or externally.h](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hjh]hstruct zynqmp_disp *disp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hF``bool video_from_ps`` True if the video clock originates from the PS h](j)}(h``bool video_from_ps``h]jB)}(hj=h]hbool video_from_ps}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj;ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj7ubj)}(hhh]h)}(h.True if the video clock originates from the PSh]h.True if the video clock originates from the PS}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhMhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1hhjRhMhjubh)}(hF``bool audio_from_ps`` True if the audio clock originates from the PS h](j)}(h``bool audio_from_ps``h]jB)}(hjvh]hbool audio_from_ps}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjpubj)}(hhh]h)}(h.True if the audio clock originates from the PSh]h.True if the audio clock originates from the PS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hI``bool timings_internal`` True if video timings are generated internally h](j)}(h``bool timings_internal``h]jB)}(hjh]hbool timings_internal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubj)}(hhh]h)}(h.True if video timings are generated internallyh]h.True if video timings are generated internally}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubh)}(hSet the source for the video and audio clocks, as well as for the video timings. Clocks can originate from the PS or PL, and timings can be generated internally or externally.h]hSet the source for the video and audio clocks, as well as for the video timings. Clocks can originate from the PS or PL, and timings can be generated internally or externally.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j.zynqmp_disp_avbuf_enable_channels (C function)#c.zynqmp_disp_avbuf_enable_channelshNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hAvoid zynqmp_disp_avbuf_enable_channels (struct zynqmp_disp *disp)h]j)}(h@void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp *disp)h](jB)}(hvoidh]hvoid}(hj/hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj+hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhj=hMubj)}(h!zynqmp_disp_avbuf_enable_channelsh]j)}(h!zynqmp_disp_avbuf_enable_channelsh]h!zynqmp_disp_avbuf_enable_channels}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ](jjeh"]h$]h&]hhuh1jhj+hhhj=hMubjz)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjRsb#c.zynqmp_disp_avbuf_enable_channelsasbuh1hhjhubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(hdisph]hdisp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjdubah}(h]h ]h"]h$]h&]hhuh1jyhj+hhhj=hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj'hhhj=hMubah}(h]j"ah ](jjeh"]h$]h&]jj)jhuh1jhj=hMhj$hhubj)}(hhh]h)}(hEnable buffer channelsh]hEnable buffer channels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj$hhhj=hMubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Enable all (video and audio) buffer channels.h](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj ubh)}(hhh]h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj0h]hstruct zynqmp_disp *disp}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj.ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj*ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1hhjEhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(h**Description**h]j!)}(hjkh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjiubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj ubh)}(h-Enable all (video and audio) buffer channels.h]h-Enable all (video and audio) buffer channels.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j/zynqmp_disp_avbuf_disable_channels (C function)$c.zynqmp_disp_avbuf_disable_channelshNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hBvoid zynqmp_disp_avbuf_disable_channels (struct zynqmp_disp *disp)h]j)}(hAvoid zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp)h](jB)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM 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]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjmhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Disable all (video and audio) buffer channels.h](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubh)}(hhh]h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hjh]hstruct zynqmp_disp *disp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubh)}(h.Disable all (video and audio) buffer channels.h]h.Disable all (video and audio) buffer channels.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_avbuf_enable_audio (C function) c.zynqmp_disp_avbuf_enable_audiohNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h>void zynqmp_disp_avbuf_enable_audio (struct zynqmp_disp *disp)h]j)}(h=void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp)h](jB)}(hvoidh]hvoid}(hj1 hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj- hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj@ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj- hhhj? hMubj)}(hzynqmp_disp_avbuf_enable_audioh]j)}(hzynqmp_disp_avbuf_enable_audioh]hzynqmp_disp_avbuf_enable_audio}(hjR hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjN ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj- hhhj? hMubjz)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjn hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubj)}(h h]h }(hj{ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNjj)}j]j)}jjT sb c.zynqmp_disp_avbuf_enable_audioasbuh1hhjj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubj)}(hdisph]hdisp}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjf ubah}(h]h ]h"]h$]h&]hhuh1jyhj- hhhj? hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj) hhhj? hMubah}(h]j$ ah ](jjeh"]h$]h&]jj)jhuh1jhj? hMhj& hhubj)}(hhh]h)}(h Enable audioh]h Enable audio}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj& hhhj? hMubeh}(h]h ](j functioneh"]h$]h&]jj jj !jj !jjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Enable all audio buffers with a non-live (memory) source.h](h)}(h**Parameters**h]j!)}(hj!h]h Parameters}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj!ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj !ubh)}(hhh]h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj2!h]hstruct zynqmp_disp *disp}(hj4!hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj0!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj,!ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjK!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjG!hMhjH!ubah}(h]h ]h"]h$]h&]uh1jhj,!ubeh}(h]h ]h"]h$]h&]uh1hhjG!hMhj)!ubah}(h]h ]h"]h$]h&]uh1hhj !ubh)}(h**Description**h]j!)}(hjm!h]h Description}(hjo!hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjk!ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj !ubh)}(h9Enable all audio buffers with a non-live (memory) source.h]h9Enable all audio buffers with a non-live (memory) source.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj !ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j,zynqmp_disp_avbuf_disable_audio (C function)!c.zynqmp_disp_avbuf_disable_audiohNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h?void zynqmp_disp_avbuf_disable_audio (struct zynqmp_disp *disp)h]j)}(h>void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp)h](jB)}(hvoidh]hvoid}(hj!hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj!hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM)ubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!hhhj!hM)ubj)}(hzynqmp_disp_avbuf_disable_audioh]j)}(hzynqmp_disp_avbuf_disable_audioh]hzynqmp_disp_avbuf_disable_audio}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj!hhhj!hM)ubjz)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj "hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj "ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj"modnameN classnameNjj)}j]j)}jj!sb!c.zynqmp_disp_avbuf_disable_audioasbuh1hhj!ubj)}(h h]h }(hj-"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(hjh]h*}(hj;"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(hdisph]hdisp}(hjH"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj!ubah}(h]h ]h"]h$]h&]hhuh1jyhj!hhhj!hM)ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj!hhhj!hM)ubah}(h]j!ah ](jjeh"]h$]h&]jj)jhuh1jhj!hM)hj!hhubj)}(hhh]h)}(h Disable audioh]h Disable audio}(hjr"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM$hjo"hhubah}(h]h ]h"]h$]h&]uh1jhj!hhhj!hM)ubeh}(h]h ](j functioneh"]h$]h&]jj jj"jj"jjjuh1jhhhjfhNhNubj)}(hn**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Disable all audio buffers.h](h)}(h**Parameters**h]j!)}(hj"h]h Parameters}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj"ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM(hj"ubh)}(hhh]h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj"h]hstruct zynqmp_disp *disp}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj"ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM%hj"ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM%hj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1hhj"hM%hj"ubah}(h]h ]h"]h$]h&]uh1hhj"ubh)}(h**Description**h]j!)}(hj"h]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj"ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM'hj"ubh)}(hDisable all audio buffers.h]hDisable all audio buffers.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM'hj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_avbuf_enable_video (C function) c.zynqmp_disp_avbuf_enable_videohNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h_void zynqmp_disp_avbuf_enable_video (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h^void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jB)}(hvoidh]hvoid}(hj3#hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj/#hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM;ubj)}(h h]h }(hjB#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/#hhhjA#hM;ubj)}(hzynqmp_disp_avbuf_enable_videoh]j)}(hzynqmp_disp_avbuf_enable_videoh]hzynqmp_disp_avbuf_enable_video}(hjT#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP#ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj/#hhhjA#hM;ubjz)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hjp#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl#ubj)}(h h]h }(hj}#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl#ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj#modnameN classnameNjj)}j]j)}jjV#sb c.zynqmp_disp_avbuf_enable_videoasbuh1hhjl#ubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl#ubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl#ubj)}(hdisph]hdisp}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjh#ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj$modnameN classnameNjj)}j]j# c.zynqmp_disp_avbuf_enable_videoasbuh1hhj#ubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hjh]h*}(hj,$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hlayerh]hlayer}(hj9$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjh#ubeh}(h]h ]h"]h$]h&]hhuh1jyhj/#hhhjA#hM;ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj+#hhhjA#hM;ubah}(h]j&#ah ](jjeh"]h$]h&]jj)jhuh1jhjA#hM;hj(#hhubj)}(hhh]h)}(hEnable a video layerh]hEnable a video layer}(hjc$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM5hj`$hhubah}(h]h ]h"]h$]h&]uh1jhj(#hhhjA#hM;ubeh}(h]h ](j functioneh"]h$]h&]jj jj{$jj{$jjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer **Description** Enable the video/graphics buffer for **layer**.h](h)}(h**Parameters**h]j!)}(hj$h]h Parameters}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj$ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM9hj$ubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj$h]hstruct zynqmp_disp *disp}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM6hj$ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM6hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1hhj$hM6hj$ubh)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hj$h]hstruct zynqmp_disp_layer *layer}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM7hj$ubj)}(hhh]h)}(h The layerh]h The layer}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM7hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1hhj$hM7hj$ubeh}(h]h ]h"]h$]h&]uh1hhj$ubh)}(h**Description**h]j!)}(hj%h]h Description}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj%ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM9hj$ubh)}(h/Enable the video/graphics buffer for **layer**.h](h%Enable the video/graphics buffer for }(hj.%hhhNhNubj!)}(h **layer**h]hlayer}(hj6%hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj.%ubh.}(hj.%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM9hj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j,zynqmp_disp_avbuf_disable_video (C function)!c.zynqmp_disp_avbuf_disable_videohNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h`void zynqmp_disp_avbuf_disable_video (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h_void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jB)}(hvoidh]hvoid}(hjo%hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjk%hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMYubj)}(h h]h }(hj~%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjk%hhhj}%hMYubj)}(hzynqmp_disp_avbuf_disable_videoh]j)}(hzynqmp_disp_avbuf_disable_videoh]hzynqmp_disp_avbuf_disable_video}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjk%hhhj}%hMYubjz)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj%modnameN classnameNjj)}j]j)}jj%sb!c.zynqmp_disp_avbuf_disable_videoasbuh1hhj%ubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(hdisph]hdisp}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(h h]h }(hj+&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj<&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9&ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj>&modnameN classnameNjj)}j]j%!c.zynqmp_disp_avbuf_disable_videoasbuh1hhj&ubj)}(h h]h }(hjZ&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(hjh]h*}(hjh&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(hlayerh]hlayer}(hju&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%ubeh}(h]h ]h"]h$]h&]hhuh1jyhjk%hhhj}%hMYubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjg%hhhj}%hMYubah}(h]jb%ah ](jjeh"]h$]h&]jj)jhuh1jhj}%hMYhjd%hhubj)}(hhh]h)}(hDisable a video layerh]hDisable a video layer}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMShj&hhubah}(h]h ]h"]h$]h&]uh1jhjd%hhhj}%hMYubeh}(h]h ](j functioneh"]h$]h&]jj jj&jj&jjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer **Description** Disable the video/graphics buffer for **layer**.h](h)}(h**Parameters**h]j!)}(hj&h]h Parameters}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj&ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMWhj&ubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj&h]hstruct zynqmp_disp *disp}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj&ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMThj&ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hMThj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1hhj&hMThj&ubh)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hj'h]hstruct zynqmp_disp_layer *layer}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMUhj'ubj)}(hhh]h)}(h The layerh]h The layer}(hj2'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.'hMUhj/'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1hhj.'hMUhj&ubeh}(h]h ]h"]h$]h&]uh1hhj&ubh)}(h**Description**h]j!)}(hjT'h]h Description}(hjV'hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjR'ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMWhj&ubh)}(h0Disable the video/graphics buffer for **layer**.h](h&Disable the video/graphics buffer for }(hjj'hhhNhNubj!)}(h **layer**h]hlayer}(hjr'hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjj'ubh.}(hjj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMWhj&ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_disp_avbuf_enable (C function)c.zynqmp_disp_avbuf_enablehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h8void zynqmp_disp_avbuf_enable (struct zynqmp_disp *disp)h]j)}(h7void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp)h](jB)}(hvoidh]hvoid}(hj'hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj'hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMoubj)}(h h]h }(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'hhhj'hMoubj)}(hzynqmp_disp_avbuf_enableh]j)}(hzynqmp_disp_avbuf_enableh]hzynqmp_disp_avbuf_enable}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj'hhhj'hMoubjz)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj)}(h h]h }(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj(modnameN classnameNjj)}j]j)}jj'sbc.zynqmp_disp_avbuf_enableasbuh1hhj'ubj)}(h h]h }(hj&(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj)}(hjh]h*}(hj4(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj)}(hdisph]hdisp}(hjA(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj'ubah}(h]h ]h"]h$]h&]hhuh1jyhj'hhhj'hMoubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj'hhhj'hMoubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1jhj'hMohj'hhubj)}(hhh]h)}(hEnable the video pipeh]hEnable the video pipe}(hjk(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMjhjh(hhubah}(h]h ]h"]h$]h&]uh1jhj'hhhj'hMoubeh}(h]h ](j functioneh"]h$]h&]jj jj(jj(jjjuh1jhhhjfhNhNubj)}(hs**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** De-assert the video pipe reset.h](h)}(h**Parameters**h]j!)}(hj(h]h Parameters}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj(ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMnhj(ubh)}(hhh]h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj(h]hstruct zynqmp_disp *disp}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj(ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMkhj(ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hMkhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1hhj(hMkhj(ubah}(h]h ]h"]h$]h&]uh1hhj(ubh)}(h**Description**h]j!)}(hj(h]h Description}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj(ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMmhj(ubh)}(hDe-assert the video pipe reset.h]hDe-assert the video pipe reset.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMmhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j&zynqmp_disp_avbuf_disable (C function)c.zynqmp_disp_avbuf_disablehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h9void zynqmp_disp_avbuf_disable (struct zynqmp_disp *disp)h]j)}(h8void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp)h](jB)}(hvoidh]hvoid}(hj,)hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj()hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMzubj)}(h h]h }(hj;)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj()hhhj:)hMzubj)}(hzynqmp_disp_avbuf_disableh]j)}(hzynqmp_disp_avbuf_disableh]hzynqmp_disp_avbuf_disable}(hjM)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI)ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj()hhhj:)hMzubjz)}(h(struct zynqmp_disp *disp)h]j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hji)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje)ubj)}(h h]h }(hjv)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje)ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj)modnameN classnameNjj)}j]j)}jjO)sbc.zynqmp_disp_avbuf_disableasbuh1hhje)ubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje)ubj)}(hjh]h*}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje)ubj)}(hdisph]hdisp}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje)ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhja)ubah}(h]h ]h"]h$]h&]hhuh1jyhj()hhhj:)hMzubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj$)hhhj:)hMzubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1jhj:)hMzhj!)hhubj)}(hhh]h)}(hDisable the video pipeh]hDisable the video pipe}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMuhj)hhubah}(h]h ]h"]h$]h&]uh1jhj!)hhhj:)hMzubeh}(h]h ](j functioneh"]h$]h&]jj jj*jj*jjjuh1jhhhjfhNhNubj)}(hp**Parameters** ``struct zynqmp_disp *disp`` Display controller **Description** Assert the video pipe reset.h](h)}(h**Parameters**h]j!)}(hj*h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj *ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMyhj*ubh)}(hhh]h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj-*h]hstruct zynqmp_disp *disp}(hj/*hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj+*ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMvhj'*ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hjF*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB*hMvhjC*ubah}(h]h ]h"]h$]h&]uh1jhj'*ubeh}(h]h ]h"]h$]h&]uh1hhjB*hMvhj$*ubah}(h]h ]h"]h$]h&]uh1hhj*ubh)}(h**Description**h]j!)}(hjh*h]h Description}(hjj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjf*ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMxhj*ubh)}(hAssert the video pipe reset.h]hAssert the video pipe reset.}(hj~*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMxhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j0zynqmp_disp_blend_set_output_format (C function)%c.zynqmp_disp_blend_set_output_formathNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hdvoid zynqmp_disp_blend_set_output_format (struct zynqmp_disp *disp, enum zynqmp_dpsub_format format)h]j)}(hcvoid zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp, enum zynqmp_dpsub_format format)h](jB)}(hvoidh]hvoid}(hj*hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj*hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*hhhj*hMubj)}(h#zynqmp_disp_blend_set_output_formath]j)}(h#zynqmp_disp_blend_set_output_formath]h#zynqmp_disp_blend_set_output_format}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj*hhhj*hMubjz)}(h;(struct zynqmp_disp *disp, enum zynqmp_dpsub_format format)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj +modnameN classnameNjj)}j]j)}jj*sb%c.zynqmp_disp_blend_set_output_formatasbuh1hhj*ubj)}(h h]h }(hj(+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj)}(hjh]h*}(hj6+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj)}(hdisph]hdisp}(hjC+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubj)}(henum zynqmp_dpsub_format formath](j)}(hjh]henum}(hj\+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX+ubj)}(h h]h }(hji+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX+ubh)}(hhh]j)}(hzynqmp_dpsub_formath]hzynqmp_dpsub_format}(hjz+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw+ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj|+modnameN classnameNjj)}j]j$+%c.zynqmp_disp_blend_set_output_formatasbuh1hhjX+ubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX+ubj)}(hformath]hformat}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubeh}(h]h ]h"]h$]h&]hhuh1jyhj*hhhj*hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj*hhhj*hMubah}(h]j*ah ](jjeh"]h$]h&]jj)jhuh1jhj*hMhj*hhubj)}(hhh]h)}(h$Set the output format of the blenderh]h$Set the output format of the blender}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj+hhubah}(h]h ]h"]h$]h&]uh1jhj*hhhj*hMubeh}(h]h ](j functioneh"]h$]h&]jj jj+jj+jjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_disp *disp`` Display controller ``enum zynqmp_dpsub_format format`` Output format **Description** Set the output format of the blender to **format**.h](h)}(h**Parameters**h]j!)}(hj+h]h Parameters}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj+ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj+ubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj,h]hstruct zynqmp_disp *disp}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj,ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj ,ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj*,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&,hMhj',ubah}(h]h ]h"]h$]h&]uh1jhj ,ubeh}(h]h ]h"]h$]h&]uh1hhj&,hMhj,ubh)}(h2``enum zynqmp_dpsub_format format`` Output format h](j)}(h#``enum zynqmp_dpsub_format format``h]jB)}(hjJ,h]henum zynqmp_dpsub_format format}(hjL,hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjH,ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjD,ubj)}(hhh]h)}(h Output formath]h Output format}(hjc,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_,hMhj`,ubah}(h]h ]h"]h$]h&]uh1jhjD,ubeh}(h]h ]h"]h$]h&]uh1hhj_,hMhj,ubeh}(h]h ]h"]h$]h&]uh1hhj+ubh)}(h**Description**h]j!)}(hj,h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj,ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj+ubh)}(h3Set the output format of the blender to **format**.h](h(Set the output format of the blender to }(hj,hhhNhNubj!)}(h **format**h]hformat}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj,ubh.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_blend_set_bg_color (C function) c.zynqmp_disp_blend_set_bg_colorhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hXvoid zynqmp_disp_blend_set_bg_color (struct zynqmp_disp *disp, u32 rcr, u32 gy, u32 bcb)h]j)}(hWvoid zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp, u32 rcr, u32 gy, u32 bcb)h](jB)}(hvoidh]hvoid}(hj,hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj,hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,hhhj,hMubj)}(hzynqmp_disp_blend_set_bg_colorh]j)}(hzynqmp_disp_blend_set_bg_colorh]hzynqmp_disp_blend_set_bg_color}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj,hhhj,hMubjz)}(h4(struct zynqmp_disp *disp, u32 rcr, u32 gy, u32 bcb)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(h h]h }(hj&-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj7-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4-ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj9-modnameN classnameNjj)}j]j)}jj,sb c.zynqmp_disp_blend_set_bg_colorasbuh1hhj-ubj)}(h h]h }(hjW-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hjh]h*}(hje-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hdisph]hdisp}(hjr-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj-ubj)}(hu32 rcrh](h)}(hhh]j)}(hu32h]hu32}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj-modnameN classnameNjj)}j]jS- c.zynqmp_disp_blend_set_bg_colorasbuh1hhj-ubj)}(h h]h }(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hrcrh]hrcr}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj-ubj)}(hu32 gyh](h)}(hhh]j)}(hu32h]hu32}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj-modnameN classnameNjj)}j]jS- c.zynqmp_disp_blend_set_bg_colorasbuh1hhj-ubj)}(h h]h }(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hgyh]hgy}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj-ubj)}(hu32 bcbh](h)}(hhh]j)}(hu32h]hu32}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj .modnameN classnameNjj)}j]jS- c.zynqmp_disp_blend_set_bg_colorasbuh1hhj.ubj)}(h h]h }(hj<.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubj)}(hbcbh]hbcb}(hjJ.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj-ubeh}(h]h ]h"]h$]h&]hhuh1jyhj,hhhj,hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj,hhhj,hMubah}(h]j,ah ](jjeh"]h$]h&]jj)jhuh1jhj,hMhj,hhubj)}(hhh]h)}(hSet the background colorh]hSet the background color}(hjt.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjq.hhubah}(h]h ]h"]h$]h&]uh1jhj,hhhj,hMubeh}(h]h ](j functioneh"]h$]h&]jj jj.jj.jjjuh1jhhhjfhNhNubj)}(hXo**Parameters** ``struct zynqmp_disp *disp`` Display controller ``u32 rcr`` Red/Cr color component ``u32 gy`` Green/Y color component ``u32 bcb`` Blue/Cb color component **Description** Set the background color to (**rcr**, **gy**, **bcb**), corresponding to the R, G and B or Cr, Y and Cb components respectively depending on the selected output format.h](h)}(h**Parameters**h]j!)}(hj.h]h Parameters}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj.ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj.ubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj.h]hstruct zynqmp_disp *disp}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj.ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj.ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1hhj.hMhj.ubh)}(h#``u32 rcr`` Red/Cr color component h](j)}(h ``u32 rcr``h]jB)}(hj.h]hu32 rcr}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj.ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj.ubj)}(hhh]h)}(hRed/Cr color componenth]hRed/Cr color component}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1hhj/hMhj.ubh)}(h#``u32 gy`` Green/Y color component h](j)}(h ``u32 gy``h]jB)}(hj'/h]hu32 gy}(hj)/hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj%/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj!/ubj)}(hhh]h)}(hGreen/Y color componenth]hGreen/Y color component}(hj@/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;3ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj@3modnameN classnameNjj)}j]j2!c.zynqmp_disp_blend_layer_set_cscasbuh1hhj3ubj)}(h h]h }(hj\3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hjh]h*}(hjj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hlayerh]hlayer}(hjw3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubj)}(hconst u16 *coeffsh](j)}(hjth]hconst}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubh)}(hhh]j)}(hu16h]hu16}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj3modnameN classnameNjj)}j]j2!c.zynqmp_disp_blend_layer_set_cscasbuh1hhj3ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hjh]h*}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hcoeffsh]hcoeffs}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubj)}(hconst u32 *offsetsh](j)}(hjth]hconst}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(h h]h }(hj 4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubh)}(hhh]j)}(hu32h]hu32}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj 4modnameN classnameNjj)}j]j2!c.zynqmp_disp_blend_layer_set_cscasbuh1hhj3ubj)}(h h]h }(hj<4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hjh]h*}(hjJ4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hoffsetsh]hoffsets}(hjW4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubeh}(h]h ]h"]h$]h&]hhuh1jyhjm2hhhj2hM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhji2hhhj2hM ubah}(h]jd2ah ](jjeh"]h$]h&]jj)jhuh1jhj2hM hjf2hhubj)}(hhh]h)}(h)Configure colorspace conversion for layerh]h)Configure colorspace conversion for layer}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj~4hhubah}(h]h ]h"]h$]h&]uh1jhjf2hhhj2hM ubeh}(h]h ](j functioneh"]h$]h&]jj jj4jj4jjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layer ``const u16 *coeffs`` Colorspace conversion matrix ``const u32 *offsets`` Colorspace conversion offsets **Description** Configure the input colorspace conversion matrix and offsets for the **layer**. Columns of the matrix are automatically swapped based on the input format to handle RGB and YCrCb components permutations.h](h)}(h**Parameters**h]j!)}(hj4h]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj4ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj4ubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hj4h]hstruct zynqmp_disp *disp}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj4ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj4ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1hhj4hMhj4ubh)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hj4h]hstruct zynqmp_disp_layer *layer}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj4ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj4ubj)}(hhh]h)}(h The layerh]h The layer}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1hhj5hMhj4ubh)}(h3``const u16 *coeffs`` Colorspace conversion matrix h](j)}(h``const u16 *coeffs``h]jB)}(hj45h]hconst u16 *coeffs}(hj65hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj25ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj.5ubj)}(hhh]h)}(hColorspace conversion matrixh]hColorspace conversion matrix}(hjM5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI5hMhjJ5ubah}(h]h ]h"]h$]h&]uh1jhj.5ubeh}(h]h ]h"]h$]h&]uh1hhjI5hMhj4ubh)}(h5``const u32 *offsets`` Colorspace conversion offsets h](j)}(h``const u32 *offsets``h]jB)}(hjm5h]hconst u32 *offsets}(hjo5hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjk5ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjg5ubj)}(hhh]h)}(hColorspace conversion offsetsh]hColorspace conversion offsets}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhjg5ubeh}(h]h ]h"]h$]h&]uh1hhj5hMhj4ubeh}(h]h ]h"]h$]h&]uh1hhj4ubh)}(h**Description**h]j!)}(hj5h]h Description}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj5ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj4ubh)}(hConfigure the input colorspace conversion matrix and offsets for the **layer**. Columns of the matrix are automatically swapped based on the input format to handle RGB and YCrCb components permutations.h](hEConfigure the input colorspace conversion matrix and offsets for the }(hj5hhhNhNubj!)}(h **layer**h]hlayer}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj5ubh|. Columns of the matrix are automatically swapped based on the input format to handle RGB and YCrCb components permutations.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_blend_layer_enable (C function) c.zynqmp_disp_blend_layer_enablehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h_void zynqmp_disp_blend_layer_enable (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h^void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jB)}(hvoidh]hvoid}(hj5hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj5hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM7ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5hhhj 6hM7ubj)}(hzynqmp_disp_blend_layer_enableh]j)}(hzynqmp_disp_blend_layer_enableh]hzynqmp_disp_blend_layer_enable}(hj 6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj5hhhj 6hM7ubjz)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj<6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj86ubj)}(h h]h }(hjI6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj86ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hjZ6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjW6ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj\6modnameN classnameNjj)}j]j)}jj"6sb c.zynqmp_disp_blend_layer_enableasbuh1hhj86ubj)}(h h]h }(hjz6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj86ubj)}(hjh]h*}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj86ubj)}(hdisph]hdisp}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj86ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj46ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj6modnameN classnameNjj)}j]jv6 c.zynqmp_disp_blend_layer_enableasbuh1hhj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(hjh]h*}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(hlayerh]hlayer}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj46ubeh}(h]h ]h"]h$]h&]hhuh1jyhj5hhhj 6hM7ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj5hhhj 6hM7ubah}(h]j5ah ](jjeh"]h$]h&]jj)jhuh1jhj 6hM7hj5hhubj)}(hhh]h)}(hEnable a layerh]hEnable a layer}(hj/7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM3hj,7hhubah}(h]h ]h"]h$]h&]uh1jhj5hhhj 6hM7ubeh}(h]h ](j functioneh"]h$]h&]jj jjG7jjG7jjjuh1jhhhjfhNhNubj)}(hr**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layerh](h)}(h**Parameters**h]j!)}(hjQ7h]h Parameters}(hjS7hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjO7ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM7hjK7ubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hjp7h]hstruct zynqmp_disp *disp}(hjr7hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjn7ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM4hjj7ubj)}(hhh]h)}(hDisplay controllerh]hDisplay controller}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hM4hj7ubah}(h]h ]h"]h$]h&]uh1jhjj7ubeh}(h]h ]h"]h$]h&]uh1hhj7hM4hjg7ubh)}(h-``struct zynqmp_disp_layer *layer`` The layerh](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hj7h]hstruct zynqmp_disp_layer *layer}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj7ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM6hj7ubj)}(hhh]h)}(h The layerh]h The layer}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM5hj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1hhj7hM6hjg7ubeh}(h]h ]h"]h$]h&]uh1hhjK7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j,zynqmp_disp_blend_layer_disable (C function)!c.zynqmp_disp_blend_layer_disablehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h`void zynqmp_disp_blend_layer_disable (struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h]j)}(h_void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](jB)}(hvoidh]hvoid}(hj8hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj7hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMWubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7hhhj8hMWubj)}(hzynqmp_disp_blend_layer_disableh]j)}(hzynqmp_disp_blend_layer_disableh]hzynqmp_disp_blend_layer_disable}(hj$8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 8ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj7hhhj8hMWubjz)}(h;(struct zynqmp_disp *disp, struct zynqmp_disp_layer *layer)h](j)}(hstruct zynqmp_disp *disph](j)}(hjh]hstruct}(hj@8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<8ubj)}(h h]h }(hjM8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<8ubh)}(hhh]j)}(h zynqmp_disph]h zynqmp_disp}(hj^8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[8ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj`8modnameN classnameNjj)}j]j)}jj&8sb!c.zynqmp_disp_blend_layer_disableasbuh1hhj<8ubj)}(h h]h }(hj~8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<8ubj)}(hjh]h*}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<8ubj)}(hdisph]hdisp}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<8ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj88ubj)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj8modnameN classnameNjj)}j]jz8!c.zynqmp_disp_blend_layer_disableasbuh1hhj8ubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(hjh]h*}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(hlayerh]hlayer}(hj 9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj88ubeh}(h]h ]h"]h$]h&]hhuh1jyhj7hhhj8hMWubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj7hhhj8hMWubah}(h]j7ah ](jjeh"]h$]h&]jj)jhuh1jhj8hMWhj7hhubj)}(hhh]h)}(hDisable a layerh]hDisable a layer}(hj39hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMShj09hhubah}(h]h ]h"]h$]h&]uh1jhj7hhhj8hMWubeh}(h]h ](j functioneh"]h$]h&]jj jjK9jjK9jjjuh1jhhhjfhNhNubj)}(hr**Parameters** ``struct zynqmp_disp *disp`` Display controller ``struct zynqmp_disp_layer *layer`` The layerh](h)}(h**Parameters**h]j!)}(hjU9h]h Parameters}(hjW9hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjS9ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMWhjO9ubh)}(hhh](h)}(h0``struct zynqmp_disp *disp`` Display controller h](j)}(h``struct zynqmp_disp *disp``h]jB)}(hjt9h]hstruct zynqmp_disp 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]h"]h$]h&]entries](j*zynqmp_disp_layer_find_format (C function)c.zynqmp_disp_layer_find_formathNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hnconst struct zynqmp_disp_format * zynqmp_disp_layer_find_format (struct zynqmp_disp_layer *layer, u32 drm_fmt)h]j)}(hlconst struct zynqmp_disp_format *zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, u32 drm_fmt)h](j)}(hjth]hconst}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMqubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj:hMqubj)}(hjh]hstruct}(hj#:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj:hMqubj)}(h h]h }(hj0:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj:hMqubh)}(hhh]j)}(hzynqmp_disp_formath]hzynqmp_disp_format}(hjA:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>:ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjC:modnameN classnameNjj)}j]j)}jzynqmp_disp_layer_find_formatsbc.zynqmp_disp_layer_find_formatasbuh1hhj:hhhj:hMqubj)}(h h]h }(hjb:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj:hMqubj)}(hjh]h*}(hjp:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhj:hMqubj)}(hzynqmp_disp_layer_find_formath]j)}(hj_:h]hzynqmp_disp_layer_find_format}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}:ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj:hhhj:hMqubjz)}(h.(struct zynqmp_disp_layer *layer, u32 drm_fmt)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj:modnameN classnameNjj)}j]j]:c.zynqmp_disp_layer_find_formatasbuh1hhj:ubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hjh]h*}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hlayerh]hlayer}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj:ubj)}(h u32 drm_fmth](h)}(hhh]j)}(hu32h]hu32}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ;ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj;modnameN classnameNjj)}j]j]:c.zynqmp_disp_layer_find_formatasbuh1hhj;ubj)}(h h]h }(hj-;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj)}(hdrm_fmth]hdrm_fmt}(hj;;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj:ubeh}(h]h ]h"]h$]h&]hhuh1jyhj:hhhj:hMqubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj9hhhj:hMqubah}(h]j9ah ](jjeh"]h$]h&]jj)jhuh1jhj:hMqhj9hhubj)}(hhh]h)}(h(Find format information for a DRM formath]h(Find format information for a DRM format}(hje;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMghjb;hhubah}(h]h ]h"]h$]h&]uh1jhj9hhhj:hMqubeh}(h]h ](j functioneh"]h$]h&]jj jj};jj};jjjuh1jhhhjfhNhNubj)}(hXb**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``u32 drm_fmt`` DRM format to search **Description** Search display subsystem format information corresponding to the given DRM format **drm_fmt** for the **layer**, and return a pointer to the format descriptor. **Return** A pointer to the format descriptor if found, NULL otherwiseh](h)}(h**Parameters**h]j!)}(hj;h]h Parameters}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj;ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMkhj;ubh)}(hhh](h)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hj;h]hstruct zynqmp_disp_layer *layer}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj;ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhhj;ubj)}(hhh]h)}(h The layerh]h The layer}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1hhj;hMhhj;ubh)}(h%``u32 drm_fmt`` DRM format to search h](j)}(h``u32 drm_fmt``h]jB)}(hj;h]h u32 drm_fmt}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj;ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMihj;ubj)}(hhh]h)}(hDRM format to searchh]hDRM format to search}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMihj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1hhj;hMihj;ubeh}(h]h ]h"]h$]h&]uh1hhj;ubh)}(h**Description**h]j!)}(hj<h]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj<ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMkhj;ubh)}(hSearch display subsystem format information corresponding to the given DRM format **drm_fmt** for the **layer**, and return a pointer to the format descriptor.h](hRSearch display subsystem format information corresponding to the given DRM format }(hj0<hhhNhNubj!)}(h **drm_fmt**h]hdrm_fmt}(hj8<hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj0<ubh for the }(hj0<hhhNhNubj!)}(h **layer**h]hlayer}(hjJ<hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj0<ubh0, and return a pointer to the format descriptor.}(hj0<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMkhj;ubh)}(h **Return**h]j!)}(hje<h]hReturn}(hjg<hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjc<ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMohj;ubh)}(h;A pointer to the format descriptor if found, NULL otherwiseh]h;A pointer to the format descriptor if found, NULL otherwise}(hj{<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMohj;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j/zynqmp_disp_layer_find_live_format (C function)$c.zynqmp_disp_layer_find_live_formathNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h|const struct zynqmp_disp_format * zynqmp_disp_layer_find_live_format (struct zynqmp_disp_layer *layer, u32 media_bus_format)h]j)}(hzconst struct zynqmp_disp_format *zynqmp_disp_layer_find_live_format(struct zynqmp_disp_layer *layer, u32 media_bus_format)h](j)}(hjth]hconst}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubj)}(hjh]hstruct}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubj)}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubh)}(hhh]j)}(hzynqmp_disp_formath]hzynqmp_disp_format}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj<modnameN classnameNjj)}j]j)}j"zynqmp_disp_layer_find_live_formatsb$c.zynqmp_disp_layer_find_live_formatasbuh1hhj<hhhj<hMubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubj)}(hjh]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hMubj)}(h"zynqmp_disp_layer_find_live_formath]j)}(hj=h]h"zynqmp_disp_layer_find_live_format}(hj$=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj =ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj<hhhj<hMubjz)}(h7(struct zynqmp_disp_layer *layer, u32 media_bus_format)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj?=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;=ubj)}(h h]h }(hjL=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;=ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj]=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZ=ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj_=modnameN classnameNjj)}j]j=$c.zynqmp_disp_layer_find_live_formatasbuh1hhj;=ubj)}(h h]h }(hj{=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;=ubj)}(hjh]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;=ubj)}(hlayerh]hlayer}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;=ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj7=ubj)}(hu32 media_bus_formath](h)}(hhh]j)}(hu32h]hu32}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj=modnameN classnameNjj)}j]j=$c.zynqmp_disp_layer_find_live_formatasbuh1hhj=ubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubj)}(hmedia_bus_formath]hmedia_bus_format}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj7=ubeh}(h]h ]h"]h$]h&]hhuh1jyhj<hhhj<hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj<hhhj<hMubah}(h]j<ah ](jjeh"]h$]h&]jj)jhuh1jhj<hMhj<hhubj)}(hhh]h)}(h2Find format information for given media bus formath]h2Find format information for given media bus format}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj>hhubah}(h]h ]h"]h$]h&]uh1jhj<hhhj<hMubeh}(h]h ](j functioneh"]h$]h&]jj jj >jj >jjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``u32 media_bus_format`` Media bus format to search **Description** Search display subsystem format information corresponding to the given media bus format **media_bus_format** for the **layer**, and return a pointer to the format descriptor. **Return** A pointer to the format descriptor if found, NULL otherwiseh](h)}(h**Parameters**h]j!)}(hj*>h]h Parameters}(hj,>hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj(>ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj$>ubh)}(hhh](h)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hjI>h]hstruct zynqmp_disp_layer *layer}(hjK>hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjG>ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjC>ubj)}(hhh]h)}(h The layerh]h The layer}(hjb>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^>hMhj_>ubah}(h]h ]h"]h$]h&]uh1jhjC>ubeh}(h]h ]h"]h$]h&]uh1hhj^>hMhj@>ubh)}(h4``u32 media_bus_format`` Media bus format to search h](j)}(h``u32 media_bus_format``h]jB)}(hj>h]hu32 media_bus_format}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj>ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj|>ubj)}(hhh]h)}(hMedia bus format to searchh]hMedia bus format to search}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj>ubah}(h]h ]h"]h$]h&]uh1jhj|>ubeh}(h]h ]h"]h$]h&]uh1hhj>hMhj@>ubeh}(h]h ]h"]h$]h&]uh1hhj$>ubh)}(h**Description**h]j!)}(hj>h]h Description}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj>ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj$>ubh)}(hSearch display subsystem format information corresponding to the given media bus format **media_bus_format** for the **layer**, and return a pointer to the format descriptor.h](hXSearch display subsystem format information corresponding to the given media bus format }(hj>hhhNhNubj!)}(h**media_bus_format**h]hmedia_bus_format}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj>ubh for the }(hj>hhhNhNubj!)}(h **layer**h]hlayer}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj>ubh0, and return a pointer to the format descriptor.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj$>ubh)}(h **Return**h]j!)}(hj?h]hReturn}(hj ?hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj?ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj$>ubh)}(h;A pointer to the format descriptor if found, NULL otherwiseh]h;A pointer to the format descriptor if found, NULL otherwise}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj$>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j*zynqmp_disp_layer_drm_formats (C function)c.zynqmp_disp_layer_drm_formatshNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h`u32 * zynqmp_disp_layer_drm_formats (struct zynqmp_disp_layer *layer, unsigned int *num_formats)h]j)}(h^u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, unsigned int *num_formats)h](h)}(hhh]j)}(hu32h]hu32}(hjP?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjM?ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjR?modnameN classnameNjj)}j]j)}jzynqmp_disp_layer_drm_formatssbc.zynqmp_disp_layer_drm_formatsasbuh1hhjI?hhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hjr?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI?hhhjq?hMubj)}(hjh]h*}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI?hhhjq?hMubj)}(hzynqmp_disp_layer_drm_formatsh]j)}(hjn?h]hzynqmp_disp_layer_drm_formats}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjI?hhhjq?hMubjz)}(h<(struct zynqmp_disp_layer *layer, unsigned int *num_formats)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj)}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj?modnameN classnameNjj)}j]jl?c.zynqmp_disp_layer_drm_formatsasbuh1hhj?ubj)}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj)}(hjh]h*}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj)}(hlayerh]hlayer}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubj)}(hunsigned int *num_formatsh](jB)}(hunsignedh]hunsigned}(hj@hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj@ubj)}(h h]h }(hj*@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubjB)}(hinth]hint}(hj8@hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj@ubj)}(h h]h }(hjF@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubj)}(hjh]h*}(hjT@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubj)}(h num_formatsh]h num_formats}(hja@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubeh}(h]h ]h"]h$]h&]hhuh1jyhjI?hhhjq?hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjE?hhhjq?hMubah}(h]j@?ah ](jjeh"]h$]h&]jj)jhuh1jhjq?hMhjB?hhubj)}(hhh]h)}(h-Return the DRM formats supported by the layerh]h-Return the DRM formats supported by the layer}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@hhubah}(h]h ]h"]h$]h&]uh1jhjB?hhhjq?hMubeh}(h]h ](j functioneh"]h$]h&]jj jj@jj@jjjuh1jhhhjfhNhNubj)}(hX0**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``unsigned int *num_formats`` Pointer to the returned number of formats **NOTE** This function doesn't make sense for live video layers and will always return an empty list in such cases. zynqmp_disp_live_layer_formats() should be used to query a list of media bus formats supported by the live video input layer. **Return** A newly allocated u32 array that stores all the DRM formats supported by the layer. The number of formats in the array is returned through the num_formats argument.h](h)}(h**Parameters**h]j!)}(hj@h]h Parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj@ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubh)}(hhh](h)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hj@h]hstruct zynqmp_disp_layer *layer}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj@ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubj)}(hhh]h)}(h The layerh]h The layer}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubh)}(hH``unsigned int *num_formats`` Pointer to the returned number of formats h](j)}(h``unsigned int *num_formats``h]jB)}(hjAh]hunsigned int *num_formats}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjAubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubj)}(hhh]h)}(h)Pointer to the returned number of formatsh]h)Pointer to the returned number of formats}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhMhjAubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1hhjAhMhj@ubeh}(h]h ]h"]h$]h&]uh1hhj@ubh)}(h**NOTE**h]j!)}(hj@Ah]hNOTE}(hjBAhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj>Aubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubh)}(hThis function doesn't make sense for live video layers and will always return an empty list in such cases. zynqmp_disp_live_layer_formats() should be used to query a list of media bus formats supported by the live video input layer.h]hThis function doesn’t make sense for live video layers and will always return an empty list in such cases. zynqmp_disp_live_layer_formats() should be used to query a list of media bus formats supported by the live video input layer.}(hjVAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubh)}(h **Return**h]j!)}(hjgAh]hReturn}(hjiAhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjeAubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubh)}(hA newly allocated u32 array that stores all the DRM formats supported by the layer. The number of formats in the array is returned through the num_formats argument.h]hA newly allocated u32 array that stores all the DRM formats supported by the layer. The number of formats in the array is returned through the num_formats argument.}(hj}AhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j+zynqmp_disp_live_layer_formats (C function) c.zynqmp_disp_live_layer_formatshNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hau32 * zynqmp_disp_live_layer_formats (struct zynqmp_disp_layer *layer, unsigned int *num_formats)h]j)}(h_u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer, unsigned int *num_formats)h](h)}(hhh]j)}(hu32h]hu32}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjAmodnameN classnameNjj)}j]j)}jzynqmp_disp_live_layer_formatssb c.zynqmp_disp_live_layer_formatsasbuh1hhjAhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhjAhMubj)}(hjh]h*}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhjAhMubj)}(hzynqmp_disp_live_layer_formatsh]j)}(hjAh]hzynqmp_disp_live_layer_formats}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ](jjeh"]h$]h&]hhuh1jhjAhhhjAhMubjz)}(h<(struct zynqmp_disp_layer *layer, unsigned int *num_formats)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hj BhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj)BhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&Bubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj+BmodnameN classnameNjj)}j]jA c.zynqmp_disp_live_layer_formatsasbuh1hhjBubj)}(h h]h }(hjGBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(hjh]h*}(hjUBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(hlayerh]hlayer}(hjbBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjBubj)}(hunsigned int *num_formatsh](jB)}(hunsignedh]hunsigned}(hj{BhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjwBubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwBubjB)}(hinth]hint}(hjBhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjwBubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwBubj)}(hjh]h*}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwBubj)}(h num_formatsh]h num_formats}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwBubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjBubeh}(h]h ]h"]h$]h&]hhuh1jyhjAhhhjAhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjAhhhjAhMubah}(h]jAah ](jjeh"]h$]h&]jj)jhuh1jhjAhMhjAhhubj)}(hhh]h)}(h>Return the media bus formats supported by the live video layerh]h>Return the media bus formats supported by the live video layer}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjBhhubah}(h]h ]h"]h$]h&]uh1jhjAhhhjAhMubeh}(h]h ](j functioneh"]h$]h&]jj jjCjjCjjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``unsigned int *num_formats`` Pointer to the returned number of formats **NOTE** This function should be used only for live video input layers. **Return** A newly allocated u32 array of media bus formats supported by the layer. The number of formats in the array is returned through the **num_formats** argument.h](h)}(h**Parameters**h]j!)}(hj Ch]h Parameters}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j hj Cubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubh)}(hhh](h)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hj+Ch]hstruct zynqmp_disp_layer *layer}(hj-ChhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj)Cubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj%Cubj)}(hhh]h)}(h The layerh]h The layer}(hjDChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ChMhjACubah}(h]h ]h"]h$]h&]uh1jhj%Cubeh}(h]h ]h"]h$]h&]uh1hhj@ChMhj"Cubh)}(hH``unsigned int *num_formats`` Pointer to the returned number of formats h](j)}(h``unsigned int *num_formats``h]jB)}(hjdCh]hunsigned int *num_formats}(hjfChhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjbCubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhj^Cubj)}(hhh]h)}(h)Pointer to the returned number of formatsh]h)Pointer to the returned number of formats}(hj}ChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyChMhjzCubah}(h]h ]h"]h$]h&]uh1jhj^Cubeh}(h]h ]h"]h$]h&]uh1hhjyChMhj"Cubeh}(h]h ]h"]h$]h&]uh1hhjCubh)}(h**NOTE**h]j!)}(hjCh]hNOTE}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j hjCubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubh)}(h>This function should be used only for live video input layers.h]h>This function should be used only for live video input layers.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubh)}(h **Return**h]j!)}(hjCh]hReturn}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j hjCubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubh)}(hA newly allocated u32 array of media bus formats supported by the layer. The number of formats in the array is returned through the **num_formats** argument.h](hA newly allocated u32 array of media bus formats supported by the layer. The number of formats in the array is returned through the }(hjChhhNhNubj!)}(h**num_formats**h]h num_formats}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j hjCubh argument.}(hjChhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjCubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_disp_layer_enable (C function)c.zynqmp_disp_layer_enablehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h?void zynqmp_disp_layer_enable (struct zynqmp_disp_layer *layer)h]j)}(h>void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer)h](jB)}(hvoidh]hvoid}(hjDhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjDhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj,DhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDhhhj+DhMubj)}(hzynqmp_disp_layer_enableh]j)}(hzynqmp_disp_layer_enableh]hzynqmp_disp_layer_enable}(hj>DhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:Dubah}(h]h ](jjeh"]h$]h&]hhuh1jhjDhhhj+DhMubjz)}(h!(struct zynqmp_disp_layer *layer)h]j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjZDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVDubj)}(h h]h }(hjgDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVDubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjxDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuDubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjzDmodnameN classnameNjj)}j]j)}jj@Dsbc.zynqmp_disp_layer_enableasbuh1hhjVDubj)}(h h]h }(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVDubj)}(hjh]h*}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVDubj)}(hlayerh]hlayer}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVDubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjRDubah}(h]h ]h"]h$]h&]hhuh1jyhjDhhhj+DhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjDhhhj+DhMubah}(h]jDah ](jjeh"]h$]h&]jj)jhuh1jhj+DhMhjDhhubj)}(hhh]h)}(hEnable a layerh]hEnable a layer}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjDhhubah}(h]h ]h"]h$]h&]uh1jhjDhhhj+DhMubeh}(h]h ](j functioneh"]h$]h&]jj jjDjjDjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_disp_layer *layer`` The layer **Description** Enable the **layer** in the audio/video buffer manager and the blender. DMA channels are started separately by zynqmp_disp_layer_update().h](h)}(h**Parameters**h]j!)}(hjDh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjDubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjDubh)}(hhh]h)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hjEh]hstruct zynqmp_disp_layer *layer}(hj EhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjEubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjEubj)}(hhh]h)}(h The layerh]h The layer}(hj7EhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3EhMhj4Eubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1hhj3EhMhjEubah}(h]h ]h"]h$]h&]uh1hhjDubh)}(h**Description**h]j!)}(hjYEh]h Description}(hj[EhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjWEubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjDubh)}(hEnable the **layer** in the audio/video buffer manager and the blender. DMA channels are started separately by zynqmp_disp_layer_update().h](h Enable the }(hjoEhhhNhNubj!)}(h **layer**h]hlayer}(hjwEhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjoEubhv in the audio/video buffer manager and the blender. DMA channels are started separately by zynqmp_disp_layer_update().}(hjoEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjDubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j&zynqmp_disp_layer_disable (C function)c.zynqmp_disp_layer_disablehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h@void zynqmp_disp_layer_disable (struct zynqmp_disp_layer *layer)h]j)}(h?void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer)h](jB)}(hvoidh]hvoid}(hjEhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjEhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEhhhjEhMubj)}(hzynqmp_disp_layer_disableh]j)}(hzynqmp_disp_layer_disableh]hzynqmp_disp_layer_disable}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ](jjeh"]h$]h&]hhuh1jhjEhhhjEhMubjz)}(h!(struct zynqmp_disp_layer *layer)h]j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj FhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj FmodnameN classnameNjj)}j]j)}jjEsbc.zynqmp_disp_layer_disableasbuh1hhjEubj)}(h h]h }(hj+FhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(hjh]h*}(hj9FhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(hlayerh]hlayer}(hjFFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjEubah}(h]h ]h"]h$]h&]hhuh1jyhjEhhhjEhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjEhhhjEhMubah}(h]jEah ](jjeh"]h$]h&]jj)jhuh1jhjEhMhjEhhubj)}(hhh]h)}(hDisable the layerh]hDisable the layer}(hjpFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjmFhhubah}(h]h ]h"]h$]h&]uh1jhjEhhhjEhMubeh}(h]h ](j functioneh"]h$]h&]jj jjFjjFjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_disp_layer *layer`` The layer **Description** Disable the layer by stopping its DMA channels and disabling it in the audio/video buffer manager and the blender.h](h)}(h**Parameters**h]j!)}(hjFh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjFubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjFubh)}(hhh]h)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hjFh]hstruct zynqmp_disp_layer *layer}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjFubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjFubj)}(hhh]h)}(h The layerh]h The layer}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhMhjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1hhjFhMhjFubah}(h]h ]h"]h$]h&]uh1hhjFubh)}(h**Description**h]j!)}(hjFh]h Description}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjFubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjFubh)}(hrDisable the layer by stopping its DMA channels and disabling it in the audio/video buffer manager and the blender.h]hrDisable the layer by stopping its DMA channels and disabling it in the audio/video buffer manager and the blender.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjFubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j)zynqmp_disp_layer_set_format (C function)c.zynqmp_disp_layer_set_formathNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hgvoid zynqmp_disp_layer_set_format (struct zynqmp_disp_layer *layer, const struct drm_format_info *info)h]j)}(hfvoid zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, const struct drm_format_info *info)h](jB)}(hvoidh]hvoid}(hj1GhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj-Ghhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMubj)}(h h]h }(hj@GhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-Ghhhj?GhMubj)}(hzynqmp_disp_layer_set_formath]j)}(hzynqmp_disp_layer_set_formath]hzynqmp_disp_layer_set_format}(hjRGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNGubah}(h]h ](jjeh"]h$]h&]hhuh1jhj-Ghhhj?GhMubjz)}(hE(struct zynqmp_disp_layer *layer, const struct drm_format_info *info)h](j)}(hstruct zynqmp_disp_layer *layerh](j)}(hjh]hstruct}(hjnGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjGubj)}(h h]h }(hj{GhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjGubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjGmodnameN classnameNjj)}j]j)}jjTGsbc.zynqmp_disp_layer_set_formatasbuh1hhjjGubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjGubj)}(hjh]h*}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjGubj)}(hlayerh]hlayer}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjGubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjfGubj)}(h"const struct drm_format_info *infoh](j)}(hjth]hconst}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(hjh]hstruct}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(h h]h }(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubh)}(hhh]j)}(hdrm_format_infoh]hdrm_format_info}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjHmodnameN classnameNjj)}j]jGc.zynqmp_disp_layer_set_formatasbuh1hhjGubj)}(h h]h }(hj7HhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(hjh]h*}(hjEHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(hinfoh]hinfo}(hjRHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjfGubeh}(h]h ]h"]h$]h&]hhuh1jyhj-Ghhhj?GhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj)Ghhhj?GhMubah}(h]j$Gah ](jjeh"]h$]h&]jj)jhuh1jhj?GhMhj&Ghhubj)}(hhh]h)}(hSet the layer formath]hSet the layer format}(hj|HhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjyHhhubah}(h]h ]h"]h$]h&]uh1jhj&Ghhhj?GhMubeh}(h]h ](j functioneh"]h$]h&]jj jjHjjHjjjuh1jhhhjfhNhNubj)}(hX3**Parameters** ``struct zynqmp_disp_layer *layer`` The layer ``const struct drm_format_info *info`` The format info **NOTE** Use zynqmp_disp_layer_set_live_format() to set media bus format for live video layers. **Description** Set the format for **layer** to **info**. The layer must be disabled.h](h)}(h**Parameters**h]j!)}(hjHh]h Parameters}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjHubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hjHubh)}(hhh](h)}(h.``struct zynqmp_disp_layer *layer`` The layer h](j)}(h#``struct zynqmp_disp_layer *layer``h]jB)}(hjHh]hstruct zynqmp_disp_layer *layer}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjHubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjHubj)}(hhh]h)}(h The layerh]h The layer}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMhjHubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1hhjHhMhjHubh)}(h7``const struct drm_format_info *info`` The format info h](j)}(h&``const struct drm_format_info *info``h]jB)}(hjHh]h"const struct drm_format_info *info}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjHubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chMhjHubj)}(hhh]h)}(hThe format infoh]hThe format info}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj IhMhj Iubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1hhj IhMhjHubeh}(h]h ]h"]h$]h&]uh1hhjHubh)}(h**NOTE**h]j!)}(hj1Ih]hNOTE}(hj3IhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj/Iubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hjHubh)}(hVUse zynqmp_disp_layer_set_live_format() to set media bus format for live video layers.h]hVUse zynqmp_disp_layer_set_live_format() to set media bus format for live video layers.}(hjGIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hjHubh)}(h**Description**h]j!)}(hjXIh]h Description}(hjZIhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjVIubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hjHubh)}(hESet the format for **layer** to **info**. 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The layer must be disabled.}(hjnIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM hjHubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j.zynqmp_disp_layer_set_live_format (C function)#c.zynqmp_disp_layer_set_live_formathNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h^void zynqmp_disp_layer_set_live_format (struct zynqmp_disp_layer *layer, u32 media_bus_format)h]j)}(h]void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer, u32 media_bus_format)h](jB)}(hvoidh]hvoid}(hjIhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjIhhh^/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:143: ./drivers/gpu/drm/xlnx/zynqmp_disp.chM;ubj)}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhhjIhM;ubj)}(h!zynqmp_disp_layer_set_live_formath]j)}(h!zynqmp_disp_layer_set_live_formath]h!zynqmp_disp_layer_set_live_format}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubah}(h]h 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]jah"]h$]h&]uh1jhj{]hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM ubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{]hhhj]hM ubj)}(hzynqmp_dp_configh]j)}(hjy]h]hzynqmp_dp_config}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj{]hhhj]hM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjw]hhhj]hM ubah}(h]jr]ah ](jjeh"]h$]h&]jj)jhuh1jhj]hM hjt]hhubj)}(hhh]h)}(h%Configuration of DisplayPort from DTSh]h%Configuration of DisplayPort from DTS}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]hhubah}(h]h ]h"]h$]h&]uh1jhjt]hhhj]hM ubeh}(h]h ](j structeh"]h$]h&]jj jj]jj]jjjuh1jhhhjfhNhNubj)}(h**Definition**:: struct zynqmp_dp_config { u8 misc0; u8 misc1; u8 bpp; }; **Members** ``misc0`` misc0 configuration (per DP v1.2 spec) ``misc1`` misc1 configuration (per DP v1.2 spec) ``bpp`` bits per pixelh](h)}(h**Definition**::h](j!)}(h**Definition**h]h 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jjT_jjT_jjjuh1jhhhjfhNhNubj)}(hX**Constants** ``TEST_VIDEO`` Use regular video input ``TEST_TPS1`` Link training symbol pattern TPS1 (/D10.2/) ``TEST_TPS2`` Link training symbol pattern TPS2 ``TEST_TPS3`` Link training symbol pattern TPS3 (for HBR2) ``TEST_SYMBOL_ERROR`` Symbol error measurement pattern ``TEST_PRBS7`` Output of the PRBS7 (x^7 + x^6 + 1) polynomial ``TEST_80BIT_CUSTOM`` A custom 80-bit pattern ``TEST_CP2520`` HBR2 compliance eye patternh](h)}(h **Constants**h]j!)}(hj^_h]h Constants}(hj`_hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj\_ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM!hjX_ubh)}(hhh](h)}(h'``TEST_VIDEO`` Use regular video input h](j)}(h``TEST_VIDEO``h]jB)}(hj}_h]h TEST_VIDEO}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj{_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM$hjw_ubj)}(hhh]h)}(hUse regular video inputh]hUse regular video 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]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1hhj`hM*hjt_ubh)}(h;``TEST_TPS3`` Link training symbol pattern TPS3 (for HBR2) h](j)}(h ``TEST_TPS3``h]jB)}(hj(`h]h TEST_TPS3}(hj*`hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj&`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM-hj"`ubj)}(hhh]h)}(h,Link training symbol pattern TPS3 (for HBR2)h]h,Link training symbol pattern TPS3 (for HBR2)}(hjA`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=`hM-hj>`ubah}(h]h ]h"]h$]h&]uh1jhj"`ubeh}(h]h ]h"]h$]h&]uh1hhj=`hM-hjt_ubh)}(h7``TEST_SYMBOL_ERROR`` Symbol error measurement pattern h](j)}(h``TEST_SYMBOL_ERROR``h]jB)}(hja`h]hTEST_SYMBOL_ERROR}(hjc`hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj_`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM0hj[`ubj)}(hhh]h)}(h Symbol error measurement patternh]h Symbol error measurement pattern}(hjz`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv`hM0hjw`ubah}(h]h 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]jah"]h$]h&]uh1jhjbahhhjsahM?ubj)}(hzynqmp_dp_testh]j)}(hj`ah]hzynqmp_dp_test}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubah}(h]h ](jjeh"]h$]h&]hhuh1jhjbahhhjsahM?ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj^ahhhjsahM?ubah}(h]jYaah ](jjeh"]h$]h&]jj)jhuh1jhjsahM?hj[ahhubj)}(hhh]h)}(hConfiguration for test modeh]hConfiguration for test mode}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM>hjahhubah}(h]h ]h"]h$]h&]uh1jhj[ahhhjsahM?ubeh}(h]h ](j structeh"]h$]h&]jj jjajjajjjuh1jhhhjfhNhNubj)}(hX#**Definition**:: struct zynqmp_dp_test { enum test_pattern pattern; bool enhanced, downspread, active; u8 custom[10]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 bw_code; u8 link_cnt; }; **Members** ``pattern`` The test pattern ``enhanced`` Use enhanced framing ``downspread`` Use SSC ``active`` Whether test mode is active ``custom`` Custom pattern for ``TEST_80BIT_CUSTOM`` ``train_set`` Voltage/preemphasis settings ``bw_code`` Bandwidth code for the link ``link_cnt`` Number of lanesh](h)}(h**Definition**::h](j!)}(h**Definition**h]h Definition}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j hjaubh:}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMBhjaubj )}(hstruct zynqmp_dp_test { enum test_pattern pattern; bool enhanced, downspread, active; u8 custom[10]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 bw_code; u8 link_cnt; };h]hstruct zynqmp_dp_test { enum test_pattern pattern; bool enhanced, downspread, active; u8 custom[10]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 bw_code; u8 link_cnt; };}hjasbah}(h]h ]h"]h$]h&]hhuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMDhjaubh)}(h **Members**h]j!)}(hjah]hMembers}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j hjaubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMMhjaubh)}(hhh](h)}(h``pattern`` The test pattern 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./drivers/gpu/drm/xlnx/zynqmp_dp.chMBhjbubj)}(hhh]h)}(hUse SSCh]hUse SSC}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMBhjbubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1hhjbhMBhj bubh)}(h'``active`` Whether test mode is active h](j)}(h ``active``h]jB)}(hjbh]hactive}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjbubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMChjbubj)}(hhh]h)}(hWhether test mode is activeh]hWhether test mode is active}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMChjbubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1hhjbhMChj bubh)}(h4``custom`` Custom pattern for ``TEST_80BIT_CUSTOM`` h](j)}(h ``custom``h]jB)}(hjbh]hcustom}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjbubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMDhjbubj)}(hhh]h)}(h(Custom pattern for ``TEST_80BIT_CUSTOM``h](hCustom pattern for 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]h"]h$]h&]uh1hhjchMFhjcubah}(h]h ]h"]h$]h&]uh1jhjscubeh}(h]h ]h"]h$]h&]uh1hhjchMFhj bubh)}(h``link_cnt`` Number of lanesh](j)}(h ``link_cnt``h]jB)}(hjch]hlink_cnt}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMFhjcubj)}(hhh]h)}(hNumber of lanesh]hNumber of lanes}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMGhjcubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1hhjchMFhj bubeh}(h]h ]h"]h$]h&]uh1hhjaubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j#zynqmp_dp_train_set_priv (C struct)c.zynqmp_dp_train_set_privhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hzynqmp_dp_train_set_privh]j)}(hstruct zynqmp_dp_train_set_privh](j)}(hjh]hstruct}(hj dhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMMubj)}(h h]h }(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhhjdhMMubj)}(hzynqmp_dp_train_set_privh]j)}(hjdh]hzynqmp_dp_train_set_priv}(hj,dhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(dubah}(h]h ](jjeh"]h$]h&]hhuh1jhjdhhhjdhMMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjdhhhjdhMMubah}(h]jcah ](jjeh"]h$]h&]jj)jhuh1jhjdhMMhjdhhubj)}(hhh]h)}(h(Private data for train_set debugfs filesh]h(Private data for train_set debugfs files}(hjNdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMRhjKdhhubah}(h]h ]h"]h$]h&]uh1jhjdhhhjdhMMubeh}(h]h ](j structeh"]h$]h&]jj jjfdjjfdjjjuh1jhhhjfhNhNubj)}(h**Definition**:: struct zynqmp_dp_train_set_priv { struct zynqmp_dp *dp; int lane; }; **Members** ``dp`` DisplayPort IP core structure ``lane`` The lane for this fileh](h)}(h**Definition**::h](j!)}(h**Definition**h]h Definition}(hjrdhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjndubh:}(hjndhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMVhjjdubj )}(hLstruct zynqmp_dp_train_set_priv { struct zynqmp_dp *dp; int lane; };h]hLstruct zynqmp_dp_train_set_priv { struct zynqmp_dp *dp; int lane; };}hjdsbah}(h]h ]h"]h$]h&]hhuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMXhjjdubh)}(h **Members**h]j!)}(hjdh]hMembers}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjdubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM]hjjdubh)}(hhh](h)}(h%``dp`` DisplayPort IP core structure h](j)}(h``dp``h]jB)}(hjdh]hdp}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjdubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMThjdubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMThjdubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1hhjdhMThjdubh)}(h``lane`` The lane for this fileh](j)}(h``lane``h]jB)}(hjdh]hlane}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjdubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMThjdubj)}(hhh]h)}(hThe lane for this fileh]hThe lane for this file}(hj ehhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMUhj eubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1hhj ehMThjdubeh}(h]h ]h"]h$]h&]uh1hhjjdubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp (C struct) c.zynqmp_dphNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h zynqmp_dph]j)}(hstruct zynqmp_dph](j)}(hjh]hstruct}(hjNehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJehhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM[ubj)}(h h]h }(hj\ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJehhhj[ehM[ubj)}(h zynqmp_dph]j)}(hjHeh]h zynqmp_dp}(hjnehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjeubah}(h]h ](jjeh"]h$]h&]hhuh1jhjJehhhj[ehM[ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjFehhhj[ehM[ubah}(h]jAeah ](jjeh"]h$]h&]jj)jhuh1jhj[ehM[hjCehhubj)}(hhh]h)}(hXilinx DisplayPort coreh]hXilinx DisplayPort core}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM\hjehhubah}(h]h ]h"]h$]h&]uh1jhjCehhhj[ehM[ubeh}(h]h ](j structeh"]h$]h&]jj jjejjejjjuh1jhhhjfhNhNubj)}(hX#**Definition**:: struct zynqmp_dp { struct drm_dp_aux aux; struct drm_bridge bridge; struct work_struct hpd_work; struct work_struct hpd_irq_work; struct completion aux_done; struct mutex lock; struct drm_bridge *next_bridge; struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *iomem; struct reset_control *reset; struct phy *phy[ZYNQMP_DP_MAX_LANES]; enum drm_connector_status status; int irq; bool enabled; bool ignore_aux_errors; bool ignore_hpd; struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES]; struct zynqmp_dp_mode mode; struct zynqmp_dp_link_config link_config; struct zynqmp_dp_test test; struct zynqmp_dp_config config; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 num_lanes; }; **Members** ``aux`` aux channel ``bridge`` DRM bridge for the DP encoder ``hpd_work`` hot plug detection worker ``hpd_irq_work`` hot plug detection IRQ worker ``aux_done`` Completed when we get an AUX reply or timeout ``lock`` Mutex protecting this struct and register access (but not AUX) ``next_bridge`` The downstream bridge ``dev`` device structure ``dpsub`` Display subsystem ``iomem`` device I/O memory for register access ``reset`` reset controller ``phy`` PHY handles for DP lanes ``status`` connection status ``irq`` irq ``enabled`` flag to indicate if the device is enabled ``ignore_aux_errors`` If set, AUX errors are suppressed ``ignore_hpd`` If set, HPD events and IRQs are ignored ``debugfs_train_set`` Debugfs private data for **train_set** ``mode`` current mode between IP core and sink device ``link_config`` common link configuration between IP core and sink device ``test`` Configuration for test mode ``config`` IP core configuration from DTS ``dpcd`` DP configuration data from currently connected sink device ``train_set`` set of training data ``num_lanes`` number of enabled phy lanesh](h)}(h**Definition**::h](j!)}(h**Definition**h]h Definition}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j hjeubh:}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM`hjeubj )}(hX;struct zynqmp_dp { struct drm_dp_aux aux; struct drm_bridge bridge; struct work_struct hpd_work; struct work_struct hpd_irq_work; struct completion aux_done; struct mutex lock; struct drm_bridge *next_bridge; struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *iomem; struct reset_control *reset; struct phy *phy[ZYNQMP_DP_MAX_LANES]; enum drm_connector_status status; int irq; bool enabled; bool ignore_aux_errors; bool ignore_hpd; struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES]; struct zynqmp_dp_mode mode; struct zynqmp_dp_link_config link_config; struct zynqmp_dp_test test; struct zynqmp_dp_config config; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 num_lanes; };h]hX;struct zynqmp_dp { struct drm_dp_aux aux; struct drm_bridge bridge; struct work_struct hpd_work; struct work_struct hpd_irq_work; struct completion aux_done; struct mutex lock; struct drm_bridge *next_bridge; struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *iomem; struct reset_control *reset; struct phy *phy[ZYNQMP_DP_MAX_LANES]; enum drm_connector_status status; int irq; bool enabled; bool ignore_aux_errors; bool ignore_hpd; struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES]; struct zynqmp_dp_mode mode; struct zynqmp_dp_link_config link_config; struct zynqmp_dp_test test; struct zynqmp_dp_config config; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 train_set[ZYNQMP_DP_MAX_LANES]; u8 num_lanes; };}hjesbah}(h]h ]h"]h$]h&]hhuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMbhjeubh)}(h **Members**h]j!)}(hjeh]hMembers}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j hjeubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM~hjeubh)}(hhh](h)}(h``aux`` aux channel h](j)}(h``aux``h]jB)}(hjeh]haux}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjeubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhhjeubj)}(hhh]h)}(h aux channelh]h aux channel}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMhhjfubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1hhjfhMhhjeubh)}(h)``bridge`` DRM bridge for the DP encoder h](j)}(h ``bridge``h]jB)}(hj6fh]hbridge}(hj8fhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj4fubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMdhj0fubj)}(hhh]h)}(hDRM bridge for the DP encoderh]hDRM bridge for the DP encoder}(hjOfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKfhMdhjLfubah}(h]h ]h"]h$]h&]uh1jhj0fubeh}(h]h ]h"]h$]h&]uh1hhjKfhMdhjeubh)}(h'``hpd_work`` hot plug detection worker h](j)}(h ``hpd_work``h]jB)}(hjofh]hhpd_work}(hjqfhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjmfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMmhjifubj)}(hhh]h)}(hhot plug detection workerh]hhot plug detection worker}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMmhjfubah}(h]h ]h"]h$]h&]uh1jhjifubeh}(h]h ]h"]h$]h&]uh1hhjfhMmhjeubh)}(h/``hpd_irq_work`` hot plug detection IRQ worker h](j)}(h``hpd_irq_work``h]jB)}(hjfh]h hpd_irq_work}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMnhjfubj)}(hhh]h)}(hhot plug detection IRQ workerh]hhot plug detection IRQ worker}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMnhjfubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1hhjfhMnhjeubh)}(h;``aux_done`` Completed when we get an AUX reply or timeout h](j)}(h ``aux_done``h]jB)}(hjfh]haux_done}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMihjfubj)}(hhh]h)}(h-Completed when we get an AUX reply or timeouth]h-Completed when we get an AUX reply or timeout}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMihjfubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1hhjfhMihjeubh)}(hH``lock`` Mutex protecting this struct and register access (but not AUX) h](j)}(h``lock``h]jB)}(hjgh]hlock}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMbhjgubj)}(hhh]h)}(h>Mutex protecting this struct and register access (but not AUX)h]h>Mutex protecting this struct and register access (but not AUX)}(hj3ghhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/ghMbhj0gubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1hhj/ghMbhjeubh)}(h&``next_bridge`` The downstream bridge h](j)}(h``next_bridge``h]jB)}(hjSgh]h next_bridge}(hjUghhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjQgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMehjMgubj)}(hhh]h)}(hThe downstream bridgeh]hThe downstream bridge}(hjlghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhghMehjigubah}(h]h ]h"]h$]h&]uh1jhjMgubeh}(h]h ]h"]h$]h&]uh1hhjhghMehjeubh)}(h``dev`` device structure h](j)}(h``dev``h]jB)}(hjgh]hdev}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM^hjgubj)}(hhh]h)}(hdevice structureh]hdevice structure}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghM^hjgubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1hhjghM^hjeubh)}(h``dpsub`` Display subsystem h](j)}(h ``dpsub``h]jB)}(hjgh]hdpsub}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM_hjgubj)}(hhh]h)}(hDisplay subsystemh]hDisplay subsystem}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghM_hjgubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1hhjghM_hjeubh)}(h0``iomem`` device I/O memory for register access h](j)}(h ``iomem``h]jB)}(hjgh]hiomem}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM`hjgubj)}(hhh]h)}(h%device I/O memory for register accessh]h%device I/O memory for register access}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhM`hjhubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1hhjhhM`hjeubh)}(h``reset`` reset controller h](j)}(h ``reset``h]jB)}(hj7hh]hreset}(hj9hhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj5hubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMahj1hubj)}(hhh]h)}(hreset controllerh]hreset controller}(hjPhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhMahjMhubah}(h]h ]h"]h$]h&]uh1jhj1hubeh}(h]h ]h"]h$]h&]uh1hhjLhhMahjeubh)}(h!``phy`` PHY handles for DP lanes h](j)}(h``phy``h]jB)}(hjphh]hphy}(hjrhhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjnhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMkhjjhubj)}(hhh]h)}(hPHY handles for DP lanesh]hPHY handles for DP lanes}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMkhjhubah}(h]h ]h"]h$]h&]uh1jhjjhubeh}(h]h ]h"]h$]h&]uh1hhjhhMkhjeubh)}(h``status`` connection status h](j)}(h ``status``h]jB)}(hjhh]hstatus}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMphjhubj)}(hhh]h)}(hconnection statush]hconnection status}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMphjhubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1hhjhhMphjeubh)}(h ``irq`` irq h](j)}(h``irq``h]jB)}(hjhh]hirq}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMchjhubj)}(hhh]h)}(hirqh]hirq}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMchjhubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1hhjhhMchjeubh)}(h6``enabled`` flag to indicate if the device is enabled h](j)}(h ``enabled``h]jB)}(hjih]henabled}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMqhjiubj)}(hhh]h)}(h)flag to indicate if the device is enabledh]h)flag to indicate if the device is enabled}(hj4ihhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ihMqhj1iubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1hhj0ihMqhjeubh)}(h8``ignore_aux_errors`` If set, AUX errors are suppressed h](j)}(h``ignore_aux_errors``h]jB)}(hjTih]hignore_aux_errors}(hjVihhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjRiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMjhjNiubj)}(hhh]h)}(h!If set, AUX errors are suppressedh]h!If set, AUX errors are suppressed}(hjmihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjiihMjhjjiubah}(h]h ]h"]h$]h&]uh1jhjNiubeh}(h]h ]h"]h$]h&]uh1hhjiihMjhjeubh)}(h7``ignore_hpd`` If set, HPD events and IRQs are ignored h](j)}(h``ignore_hpd``h]jB)}(hjih]h ignore_hpd}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMohjiubj)}(hhh]h)}(h'If set, HPD events and IRQs are ignoredh]h'If set, HPD events and IRQs are ignored}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMohjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1hhjihMohjeubh)}(h=``debugfs_train_set`` Debugfs private data for **train_set** h](j)}(h``debugfs_train_set``h]jB)}(hjih]hdebugfs_train_set}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMvhjiubj)}(hhh]h)}(h&Debugfs private data for **train_set**h](hDebugfs private data for }(hjihhhNhNubj!)}(h **train_set**h]h train_set}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1j hjiubeh}(h]h ]h"]h$]h&]uh1hhjihMvhjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1hhjihMvhjeubh)}(h6``mode`` current mode between IP core and sink device h](j)}(h``mode``h]jB)}(hj jh]hmode}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj jubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMthjjubj)}(hhh]h)}(h,current mode between IP core and sink deviceh]h,current mode between IP core and sink device}(hj&jhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"jhMthj#jubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1hhj"jhMthjeubh)}(hJ``link_config`` common link configuration between IP core and sink device h](j)}(h``link_config``h]jB)}(hjFjh]h link_config}(hjHjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjDjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMshj@jubj)}(hhh]h)}(h9common link configuration between IP core and sink deviceh]h9common link configuration between IP core and sink device}(hj_jhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[jhMshj\jubah}(h]h ]h"]h$]h&]uh1jhj@jubeh}(h]h ]h"]h$]h&]uh1hhj[jhMshjeubh)}(h%``test`` Configuration for test mode h](j)}(h``test``h]jB)}(hjjh]htest}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj}jubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMfhjyjubj)}(hhh]h)}(hConfiguration for test modeh]hConfiguration for test mode}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMfhjjubah}(h]h ]h"]h$]h&]uh1jhjyjubeh}(h]h ]h"]h$]h&]uh1hhjjhMfhjeubh)}(h*``config`` IP core configuration from DTS h](j)}(h ``config``h]jB)}(hjjh]hconfig}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMghjjubj)}(hhh]h)}(hIP core configuration from DTSh]hIP core configuration from DTS}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMghjjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1hhjjhMghjeubh)}(hD``dpcd`` DP configuration data from currently connected sink device h](j)}(h``dpcd``h]jB)}(hjjh]hdpcd}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMrhjjubj)}(hhh]h)}(h:DP configuration data from currently connected sink deviceh]h:DP configuration data from currently connected sink device}(hj khhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhMrhjkubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1hhjkhMrhjeubh)}(h#``train_set`` set of training data h](j)}(h ``train_set``h]jB)}(hj*kh]h train_set}(hj,khhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj(kubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMuhj$kubj)}(hhh]h)}(hset of training datah]hset of training data}(hjCkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?khMuhj@kubah}(h]h ]h"]h$]h&]uh1jhj$kubeh}(h]h ]h"]h$]h&]uh1hhj?khMuhjeubh)}(h)``num_lanes`` number of enabled phy lanesh](j)}(h ``num_lanes``h]jB)}(hjckh]h num_lanes}(hjekhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjakubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMkhj]kubj)}(hhh]h)}(hnumber of enabled phy lanesh]hnumber of enabled phy lanes}(hj|khhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMlhjykubah}(h]h ]h"]h$]h&]uh1jhj]kubeh}(h]h ]h"]h$]h&]uh1hhjxkhMkhjeubeh}(h]h ]h"]h$]h&]uh1hhjeubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubh)}(h**Description**h]j!)}(hjkh]h Description}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjkubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMohjfhhubh)}(h**lock** covers the link configuration in this struct and the device's registers. It does not cover **aux** or **ignore_aux_errors**. It is not strictly required for any of the members which are only modified at probe/remove time (e.g. **dev**).h](j!)}(h**lock**h]hlock}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjkubh^ covers the link configuration in this struct and the device’s registers. It does not cover }(hjkhhhNhNubj!)}(h**aux**h]haux}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjkubh or }(hjkhhhNhNubj!)}(h**ignore_aux_errors**h]hignore_aux_errors}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjkubhh. It is not strictly required for any of the members which are only modified at probe/remove time (e.g. }(hjkhhhNhNubj!)}(h**dev**h]hdev}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjkubh).}(hjkhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMwhjfhhubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_phy_init (C function)c.zynqmp_dp_phy_inithNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h-int zynqmp_dp_phy_init (struct zynqmp_dp *dp)h]j)}(h,int zynqmp_dp_phy_init(struct zynqmp_dp *dp)h](jB)}(hinth]hint}(hj(lhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj$lhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj7lhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$lhhhj6lhMubj)}(hzynqmp_dp_phy_inith]j)}(hzynqmp_dp_phy_inith]hzynqmp_dp_phy_init}(hjIlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjElubah}(h]h ](jjeh"]h$]h&]hhuh1jhj$lhhhj6lhMubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjelhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjalubj)}(h h]h }(hjrlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjalubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjlmodnameN classnameNjj)}j]j)}jjKlsbc.zynqmp_dp_phy_initasbuh1hhjalubj)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjalubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjalubj)}(hdph]hdp}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjalubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj]lubah}(h]h ]h"]h$]h&]hhuh1jyhj$lhhhj6lhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj lhhhj6lhMubah}(h]jlah ](jjeh"]h$]h&]jj)jhuh1jhj6lhMhjlhhubj)}(hhh]h)}(hInitialize the phyh]hInitialize the phy}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjlhhubah}(h]h ]h"]h$]h&]uh1jhjlhhhj6lhMubeh}(h]h ](j functioneh"]h$]h&]jj jjmjjmjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Initialize the phy. **Return** 0 if the phy instances are initialized correctly, or the error code returned from the callee functions.h](h)}(h**Parameters**h]j!)}(hj mh]h Parameters}(hj mhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjmubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjmubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hj)mh]hstruct zynqmp_dp *dp}(hj+mhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj'mubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj#mubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjBmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>mhMhj?mubah}(h]h ]h"]h$]h&]uh1jhj#mubeh}(h]h ]h"]h$]h&]uh1hhj>mhMhj mubah}(h]h ]h"]h$]h&]uh1hhjmubh)}(h**Description**h]j!)}(hjdmh]h Description}(hjfmhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjbmubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjmubh)}(hInitialize the phy.h]hInitialize the phy.}(hjzmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjmubh)}(h **Return**h]j!)}(hjmh]hReturn}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjmubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjmubh)}(hg0 if the phy instances are initialized correctly, or the error code returned from the callee functions.h]hg0 if the phy instances are initialized correctly, or the error code returned from the callee functions.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjmubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_phy_exit (C function)c.zynqmp_dp_phy_exithNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h.void zynqmp_dp_phy_exit (struct zynqmp_dp *dp)h]j)}(h-void zynqmp_dp_phy_exit(struct zynqmp_dp *dp)h](jB)}(hvoidh]hvoid}(hjmhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjmhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhhjmhMubj)}(hzynqmp_dp_phy_exith]j)}(hzynqmp_dp_phy_exith]hzynqmp_dp_phy_exit}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubah}(h]h ](jjeh"]h$]h&]hhuh1jhjmhhhjmhMubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj nhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj nubj)}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj nubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj+nhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(nubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj-nmodnameN classnameNjj)}j]j)}jjmsbc.zynqmp_dp_phy_exitasbuh1hhj nubj)}(h h]h }(hjKnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj nubj)}(hjh]h*}(hjYnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj nubj)}(hdph]hdp}(hjfnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj nubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjnubah}(h]h ]h"]h$]h&]hhuh1jyhjmhhhjmhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjmhhhjmhMubah}(h]jmah ](jjeh"]h$]h&]jj)jhuh1jhjmhMhjmhhubj)}(hhh]h)}(h Exit the phyh]h Exit the phy}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjnhhubah}(h]h ]h"]h$]h&]uh1jhjmhhhjmhMubeh}(h]h ](j functioneh"]h$]h&]jj jjnjjnjjjuh1jhhhjfhNhNubj)}(hh**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Exit the phy.h](h)}(h**Parameters**h]j!)}(hjnh]h Parameters}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjnubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjnubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjnh]hstruct zynqmp_dp *dp}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjnubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjnubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjnubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1hhjnhMhjnubah}(h]h ]h"]h$]h&]uh1hhjnubh)}(h**Description**h]j!)}(hj oh]h Description}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j hj oubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjnubh)}(h Exit the phy.h]h Exit the phy.}(hj"ohhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjnubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j zynqmp_dp_phy_probe (C function)c.zynqmp_dp_phy_probehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h.int zynqmp_dp_phy_probe (struct zynqmp_dp *dp)h]j)}(h-int zynqmp_dp_phy_probe(struct zynqmp_dp *dp)h](jB)}(hinth]hint}(hjQohhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjMohhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM ubj)}(h h]h }(hj`ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMohhhj_ohM ubj)}(hzynqmp_dp_phy_probeh]j)}(hzynqmp_dp_phy_probeh]hzynqmp_dp_phy_probe}(hjrohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnoubah}(h]h ](jjeh"]h$]h&]hhuh1jhjMohhhj_ohM ubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjomodnameN classnameNjj)}j]j)}jjtosbc.zynqmp_dp_phy_probeasbuh1hhjoubj)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hjh]h*}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hdph]hdp}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjoubah}(h]h ]h"]h$]h&]hhuh1jyhjMohhhj_ohM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjIohhhj_ohM ubah}(h]jDoah ](jjeh"]h$]h&]jj)jhuh1jhj_ohM hjFohhubj)}(hhh]h)}(hProbe the PHYsh]hProbe the PHYs}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjphhubah}(h]h ]h"]h$]h&]uh1jhjFohhhj_ohM ubeh}(h]h ](j functioneh"]h$]h&]jj jj)pjj)pjjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Probe PHYs for all lanes. Less PHYs may be available than the number of lanes, which is not considered an error as long as at least one PHY is found. The caller can check dp->num_lanes to check how many PHYs were found. **Return** * 0 - Success * -ENXIO - No PHY found * -EPROBE_DEFER - Probe deferral requested * Other negative value - PHY retrieval failureh](h)}(h**Parameters**h]j!)}(hj3ph]h Parameters}(hj5phhhNhNubah}(h]h ]h"]h$]h&]uh1j hj1pubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj-pubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjRph]hstruct zynqmp_dp *dp}(hjTphhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjPpubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjLpubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjkphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgphMhjhpubah}(h]h ]h"]h$]h&]uh1jhjLpubeh}(h]h ]h"]h$]h&]uh1hhjgphMhjIpubah}(h]h ]h"]h$]h&]uh1hhj-pubh)}(h**Description**h]j!)}(hjph]h Description}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j hjpubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj-pubh)}(hProbe PHYs for all lanes. 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If PHY is not ready, wait 1ms to check for 100 times. This amount of delay was suggested by IP designer. **Return** 0 if PHY is ready, or -ENODEV if PHY is not ready.h](h)}(h**Parameters**h]j!)}(hjsh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j hjsubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMJhjrubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hj!sh]hstruct zynqmp_dp *dp}(hj#shhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjsubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMGhjsubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj:shhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6shMGhj7subah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1hhj6shMGhjsubah}(h]h ]h"]h$]h&]uh1hhjrubh)}(h**Description**h]j!)}(hj\sh]h Description}(hj^shhhNhNubah}(h]h ]h"]h$]h&]uh1j hjZsubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMIhjrubh)}(hCheck if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. This amount of delay was suggested by IP designer.h]hCheck if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. This amount of delay was suggested by IP designer.}(hjrshhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMIhjrubh)}(h **Return**h]j!)}(hjsh]hReturn}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j hjsubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMLhjrubh)}(h20 if PHY is ready, or -ENODEV if PHY is not ready.h]h20 if PHY is ready, or -ENODEV if PHY is not ready.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMLhjrubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_max_rate (C function)c.zynqmp_dp_max_ratehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h;int zynqmp_dp_max_rate (int link_rate, u8 lane_num, u8 bpp)h]j)}(h:int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)h](jB)}(hinth]hint}(hjshhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjshhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMqubj)}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjshhhjshMqubj)}(hzynqmp_dp_max_rateh]j)}(hzynqmp_dp_max_rateh]hzynqmp_dp_max_rate}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ](jjeh"]h$]h&]hhuh1jhjshhhjshMqubjz)}(h$(int link_rate, u8 lane_num, u8 bpp)h](j)}(h int link_rateh](jB)}(hinth]hint}(hjthhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjtubj)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubj)}(h link_rateh]h link_rate}(hj!thhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjsubj)}(h u8 lane_numh](h)}(hhh]j)}(hu8h]hu8}(hj=thhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:tubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj?tmodnameN classnameNjj)}j]j)}jjssbc.zynqmp_dp_max_rateasbuh1hhj6tubj)}(h h]h }(hj]thhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6tubj)}(hlane_numh]hlane_num}(hjkthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6tubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjsubj)}(hu8 bpph](h)}(hhh]j)}(hu8h]hu8}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjtmodnameN classnameNjj)}j]jYtc.zynqmp_dp_max_rateasbuh1hhjtubj)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubj)}(hbpph]hbpp}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjsubeh}(h]h ]h"]h$]h&]hhuh1jyhjshhhjshMqubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjshhhjshMqubah}(h]jsah ](jjeh"]h$]h&]jj)jhuh1jhjshMqhjshhubj)}(hhh]h)}(h.Calculate and return available max pixel clockh]h.Calculate and return available max pixel clock}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMjhjthhubah}(h]h ]h"]h$]h&]uh1jhjshhhjshMqubeh}(h]h ](j functioneh"]h$]h&]jj jjtjjtjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``int link_rate`` link rate (Kilo-bytes / sec) ``u8 lane_num`` number of lanes ``u8 bpp`` bits per pixel **Return** max pixel clock (KHz) supported by current link config.h](h)}(h**Parameters**h]j!)}(hjth]h Parameters}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjtubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMnhjtubh)}(hhh](h)}(h/``int link_rate`` link rate (Kilo-bytes / sec) h](j)}(h``int link_rate``h]jB)}(hjuh]h int link_rate}(hj uhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjuubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMkhjuubj)}(hhh]h)}(hlink rate (Kilo-bytes / sec)h]hlink rate (Kilo-bytes / sec)}(hj7uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3uhMkhj4uubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1hhj3uhMkhjuubh)}(h ``u8 lane_num`` number of lanes h](j)}(h``u8 lane_num``h]jB)}(hjWuh]h u8 lane_num}(hjYuhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjUuubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMlhjQuubj)}(hhh]h)}(hnumber of lanesh]hnumber of lanes}(hjpuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjluhMlhjmuubah}(h]h ]h"]h$]h&]uh1jhjQuubeh}(h]h ]h"]h$]h&]uh1hhjluhMlhjuubh)}(h``u8 bpp`` bits per pixel h](j)}(h ``u8 bpp``h]jB)}(hjuh]hu8 bpp}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjuubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMmhjuubj)}(hhh]h)}(hbits per pixelh]hbits per pixel}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMmhjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1hhjuhMmhjuubeh}(h]h ]h"]h$]h&]uh1hhjtubh)}(h **Return**h]j!)}(hjuh]hReturn}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjuubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMohjtubh)}(h7max pixel clock (KHz) supported by current link config.h]h7max pixel clock (KHz) supported by current link config.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMohjtubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_dp_mode_configure (C function)c.zynqmp_dp_mode_configurehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hNint zynqmp_dp_mode_configure (struct zynqmp_dp *dp, int pclock, u8 current_bw)h]j)}(hMint zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, u8 current_bw)h](jB)}(hinth]hint}(hjvhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj vhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj vhhhjvhMubj)}(hzynqmp_dp_mode_configureh]j)}(hzynqmp_dp_mode_configureh]hzynqmp_dp_mode_configure}(hj1vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-vubah}(h]h ](jjeh"]h$]h&]hhuh1jhj vhhhjvhMubjz)}(h1(struct zynqmp_dp *dp, int pclock, u8 current_bw)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjMvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIvubj)}(h h]h }(hjZvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIvubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjkvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhvubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmvmodnameN classnameNjj)}j]j)}jj3vsbc.zynqmp_dp_mode_configureasbuh1hhjIvubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIvubj)}(hjh]h*}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIvubj)}(hdph]hdp}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIvubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjEvubj)}(h int pclockh](jB)}(hinth]hint}(hjvhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjvubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(hpclockh]hpclock}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjEvubj)}(h u8 current_bwh](h)}(hhh]j)}(hu8h]hu8}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjvmodnameN classnameNjj)}j]jvc.zynqmp_dp_mode_configureasbuh1hhjvubj)}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(h current_bwh]h current_bw}(hj#whhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjEvubeh}(h]h ]h"]h$]h&]hhuh1jyhj vhhhjvhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjvhhhjvhMubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1jhjvhMhjvhhubj)}(hhh]h)}(hConfigure the link valuesh]hConfigure the link values}(hjMwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMwhjJwhhubah}(h]h ]h"]h$]h&]uh1jhjvhhhjvhMubeh}(h]h ](j functioneh"]h$]h&]jj jjewjjewjjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``int pclock`` pixel clock for requested display mode ``u8 current_bw`` current link rate **Description** Find the link configuration values, rate and lane count for requested pixel clock **pclock**. The **pclock** is stored in the mode to be used in other functions later. The returned rate is downshifted from the current rate **current_bw**. **Return** Current link rate code, or -EINVAL.h](h)}(h**Parameters**h]j!)}(hjowh]h Parameters}(hjqwhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjmwubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM{hjiwubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjwh]hstruct zynqmp_dp *dp}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjwubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMxhjwubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMxhjwubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1hhjwhMxhjwubh)}(h6``int pclock`` pixel clock for requested display mode h](j)}(h``int pclock``h]jB)}(hjwh]h int pclock}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjwubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMyhjwubj)}(hhh]h)}(h&pixel clock for requested display modeh]h&pixel clock for requested display mode}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMyhjwubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1hhjwhMyhjwubh)}(h$``u8 current_bw`` current link rate h](j)}(h``u8 current_bw``h]jB)}(hjxh]h u8 current_bw}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjwubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMzhjwubj)}(hhh]h)}(hcurrent link rateh]hcurrent link rate}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMzhjxubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1hhjxhMzhjwubeh}(h]h ]h"]h$]h&]uh1hhjiwubh)}(h**Description**h]j!)}(hj;xh]h Description}(hj=xhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj9xubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM|hjiwubh)}(hFind the link configuration values, rate and lane count for requested pixel clock **pclock**. The **pclock** is stored in the mode to be used in other functions later. The returned rate is downshifted from the current rate **current_bw**.h](hRFind the link configuration values, rate and lane count for requested pixel clock }(hjQxhhhNhNubj!)}(h **pclock**h]hpclock}(hjYxhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjQxubh. The }(hjQxhhhNhNubj!)}(h **pclock**h]hpclock}(hjkxhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjQxubhs is stored in the mode to be used in other functions later. The returned rate is downshifted from the current rate }(hjQxhhhNhNubj!)}(h**current_bw**h]h current_bw}(hj}xhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjQxubh.}(hjQxhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM|hjiwubh)}(h **Return**h]j!)}(hjxh]hReturn}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjxubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjiwubh)}(h#Current link rate code, or -EINVAL.h]h#Current link rate code, or -EINVAL.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjiwubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j#zynqmp_dp_adjust_train (C function)c.zynqmp_dp_adjust_trainhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hWvoid zynqmp_dp_adjust_train (struct zynqmp_dp *dp, u8 link_status[DP_LINK_STATUS_SIZE])h]j)}(hVvoid zynqmp_dp_adjust_train(struct zynqmp_dp *dp, u8 link_status[DP_LINK_STATUS_SIZE])h](jB)}(hvoidh]hvoid}(hjxhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjxhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxhhhjxhMubj)}(hzynqmp_dp_adjust_trainh]j)}(hzynqmp_dp_adjust_trainh]hzynqmp_dp_adjust_train}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubah}(h]h ](jjeh"]h$]h&]hhuh1jhjxhhhjxhMubjz)}(h;(struct zynqmp_dp *dp, u8 link_status[DP_LINK_STATUS_SIZE])h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubj)}(h h]h }(hj'yhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj8yhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5yubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj:ymodnameN classnameNjj)}j]j)}jjysbc.zynqmp_dp_adjust_trainasbuh1hhjyubj)}(h h]h }(hjXyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubj)}(hjh]h*}(hjfyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubj)}(hdph]hdp}(hjsyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjyubj)}(h#u8 link_status[DP_LINK_STATUS_SIZE]h](h)}(hhh]j)}(hu8h]hu8}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjymodnameN classnameNjj)}j]jTyc.zynqmp_dp_adjust_trainasbuh1hhjyubj)}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubj)}(h link_statush]h link_status}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubj)}(h[h]h[}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubh)}(hhh]j)}(hDP_LINK_STATUS_SIZEh]hDP_LINK_STATUS_SIZE}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjymodnameN classnameNjj)}j]jTyc.zynqmp_dp_adjust_trainasbuh1hhjyubj)}(h]h]h]}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjyubeh}(h]h ]h"]h$]h&]hhuh1jyhjxhhhjxhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjxhhhjxhMubah}(h]jxah ](jjeh"]h$]h&]jj)jhuh1jhjxhMhjxhhubj)}(hhh]h)}(hAdjust train valuesh]hAdjust train values}(hj"zhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjzhhubah}(h]h ]h"]h$]h&]uh1jhjxhhhjxhMubeh}(h]h ](j functioneh"]h$]h&]jj jj:zjj:zjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``u8 link_status[DP_LINK_STATUS_SIZE]`` link status from sink which contains requested training valuesh](h)}(h**Parameters**h]j!)}(hjDzh]h Parameters}(hjFzhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjBzubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj>zubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjczh]hstruct zynqmp_dp *dp}(hjezhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjazubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj]zubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj|zhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxzhMhjyzubah}(h]h ]h"]h$]h&]uh1jhj]zubeh}(h]h ]h"]h$]h&]uh1hhjxzhMhjZzubh)}(hf``u8 link_status[DP_LINK_STATUS_SIZE]`` link status from sink which contains requested training valuesh](j)}(h'``u8 link_status[DP_LINK_STATUS_SIZE]``h]jB)}(hjzh]h#u8 link_status[DP_LINK_STATUS_SIZE]}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjzubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjzubj)}(hhh]h)}(h>link status from sink which contains requested training valuesh]h>link status from sink which contains requested training values}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjzubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1hhjzhMhjZzubeh}(h]h ]h"]h$]h&]uh1hhj>zubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_dp_update_vs_emph (C function)c.zynqmp_dp_update_vs_emphhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hBint zynqmp_dp_update_vs_emph (struct zynqmp_dp *dp, u8 *train_set)h]j)}(hAint zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set)h](jB)}(hinth]hint}(hjzhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjzhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzhhhj{hMubj)}(hzynqmp_dp_update_vs_emphh]j)}(hzynqmp_dp_update_vs_emphh]hzynqmp_dp_update_vs_emph}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjzhhhj{hMubjz)}(h%(struct zynqmp_dp *dp, u8 *train_set)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj3{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/{ubj)}(h h]h }(hj@{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/{ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjQ{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjN{ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjS{modnameN classnameNjj)}j]j)}jj{sbc.zynqmp_dp_update_vs_emphasbuh1hhj/{ubj)}(h h]h }(hjq{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/{ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/{ubj)}(hdph]hdp}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/{ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj+{ubj)}(h u8 *train_seth](h)}(hhh]j)}(hu8h]hu8}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj{modnameN classnameNjj)}j]jm{c.zynqmp_dp_update_vs_emphasbuh1hhj{ubj)}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj)}(h train_seth]h train_set}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj+{ubeh}(h]h ]h"]h$]h&]hhuh1jyhjzhhhj{hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjzhhhj{hMubah}(h]jzah ](jjeh"]h$]h&]jj)jhuh1jhj{hMhjzhhubj)}(hhh]h)}(hUpdate the training valuesh]hUpdate the training values}(hj |hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj|hhubah}(h]h ]h"]h$]h&]uh1jhjzhhhj{hMubeh}(h]h ](j functioneh"]h$]h&]jj jj#|jj#|jjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``u8 *train_set`` A set of training values **Description** Update the training values based on the request from sink. The mapped values are predefined, and values(vs, pe, pc) are from the device manual. **Return** 0 if vs and emph are updated successfully, or the error code returned by drm_dp_dpcd_write().h](h)}(h**Parameters**h]j!)}(hj-|h]h Parameters}(hj/|hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj+|ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj'|ubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjL|h]hstruct zynqmp_dp *dp}(hjN|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjJ|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjF|ubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hje|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhja|hMhjb|ubah}(h]h ]h"]h$]h&]uh1jhjF|ubeh}(h]h ]h"]h$]h&]uh1hhja|hMhjC|ubh)}(h+``u8 *train_set`` A set of training values h](j)}(h``u8 *train_set``h]jB)}(hj|h]h u8 *train_set}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj|ubj)}(hhh]h)}(hA set of training valuesh]hA set of training values}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMhj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1hhj|hMhjC|ubeh}(h]h ]h"]h$]h&]uh1hhj'|ubh)}(h**Description**h]j!)}(hj|h]h Description}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj|ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj'|ubh)}(hUpdate the training values based on the request from sink. The mapped values are predefined, and values(vs, pe, pc) are from the device manual.h]hUpdate the training values based on the request from sink. The mapped values are predefined, and values(vs, pe, pc) are from the device manual.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj'|ubh)}(h **Return**h]j!)}(hj|h]hReturn}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj|ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj'|ubh)}(h]0 if vs and emph are updated successfully, or the error code returned by drm_dp_dpcd_write().h]h]0 if vs and emph are updated successfully, or the error code returned by drm_dp_dpcd_write().}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj'|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j$zynqmp_dp_link_train_cr (C function)c.zynqmp_dp_link_train_crhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h2int zynqmp_dp_link_train_cr (struct zynqmp_dp *dp)h]j)}(h1int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)h](jB)}(hinth]hint}(hj,}hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj(}hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj;}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(}hhhj:}hMubj)}(hzynqmp_dp_link_train_crh]j)}(hzynqmp_dp_link_train_crh]hzynqmp_dp_link_train_cr}(hjM}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI}ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj(}hhhj:}hMubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hji}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje}ubj)}(h h]h }(hjv}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje}ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj}modnameN classnameNjj)}j]j)}jjO}sbc.zynqmp_dp_link_train_crasbuh1hhje}ubj)}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje}ubj)}(hjh]h*}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje}ubj)}(hdph]hdp}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhje}ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhja}ubah}(h]h ]h"]h$]h&]hhuh1jyhj(}hhhj:}hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj$}hhhj:}hMubah}(h]j}ah ](jjeh"]h$]h&]jj)jhuh1jhj:}hMhj!}hhubj)}(hhh]h)}(hTrain clock recoveryh]hTrain clock recovery}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj}hhubah}(h]h ]h"]h$]h&]uh1jhj!}hhhj:}hMubeh}(h]h ](j functioneh"]h$]h&]jj jj~jj~jjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Return** 0 if clock recovery train is done successfully, or corresponding error code.h](h)}(h**Parameters**h]j!)}(hj~h]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ~ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj~ubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hj-~h]hstruct zynqmp_dp *dp}(hj/~hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj+~ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj'~ubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjF~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB~hMhjC~ubah}(h]h ]h"]h$]h&]uh1jhj'~ubeh}(h]h ]h"]h$]h&]uh1hhjB~hMhj$~ubah}(h]h ]h"]h$]h&]uh1hhj~ubh)}(h **Return**h]j!)}(hjh~h]hReturn}(hjj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjf~ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj~ubh)}(hL0 if clock recovery train is done successfully, or corresponding error code.h]hL0 if clock recovery train is done successfully, or corresponding error code.}(hj~~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj~ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j$zynqmp_dp_link_train_ce (C function)c.zynqmp_dp_link_train_cehNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h2int zynqmp_dp_link_train_ce (struct zynqmp_dp *dp)h]j)}(h1int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)h](jB)}(hinth]hint}(hj~hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj~hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM;ubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhhj~hM;ubj)}(hzynqmp_dp_link_train_ceh]j)}(hzynqmp_dp_link_train_ceh]hzynqmp_dp_link_train_ce}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj~hhhj~hM;ubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNjj)}j]j)}jj~sbc.zynqmp_dp_link_train_ceasbuh1hhj~ubj)}(h h]h }(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(hjh]h*}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(hdph]hdp}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj~ubah}(h]h ]h"]h$]h&]hhuh1jyhj~hhhj~hM;ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj~hhhj~hM;ubah}(h]j~ah ](jjeh"]h$]h&]jj)jhuh1jhj~hM;hj~hhubj)}(hhh]h)}(hTrain channel equalizationh]hTrain channel equalization}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM5hjjhhubah}(h]h ]h"]h$]h&]uh1jhj~hhhj~hM;ubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Return** 0 if channel equalization train is done successfully, or corresponding error code.h](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM9hjubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM6hjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM6hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM6hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h **Return**h]j!)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM8hjubh)}(hR0 if channel equalization train is done successfully, or corresponding error code.h]hR0 if channel equalization train is done successfully, or corresponding error code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM8hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_setup (C function)c.zynqmp_dp_setuphNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hcint zynqmp_dp_setup (struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, bool enhanced, bool downspread)h]j)}(hbint zynqmp_dp_setup(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, bool enhanced, bool downspread)h](jB)}(hinth]hint}(hj.hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj*hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMpubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*hhhj<hMpubj)}(hzynqmp_dp_setuph]j)}(hzynqmp_dp_setuph]hzynqmp_dp_setup}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubah}(h]h ](jjeh"]h$]h&]hhuh1jhj*hhhj<hMpubjz)}(hO(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, bool enhanced, bool downspread)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubj)}(h h]h }(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjQsbc.zynqmp_dp_setupasbuh1hhjgubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubj)}(hdph]hdp}(hjĀhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjcubj)}(h u8 bw_codeh](h)}(hhh]j)}(hu8h]hu8}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj݀ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]jc.zynqmp_dp_setupasbuh1hhjـubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjـubj)}(hbw_codeh]hbw_code}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjـubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjcubj)}(h u8 lane_cnth](h)}(hhh]j)}(hu8h]hu8}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj*modnameN classnameNjj)}j]jc.zynqmp_dp_setupasbuh1hhj!ubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(hlane_cnth]hlane_cnt}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjcubj)}(h bool enhancedh](jB)}(hjh]hbool}(hjmhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjiubj)}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubj)}(henhancedh]henhanced}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjcubj)}(hbool downspreadh](jB)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h downspreadh]h downspread}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjcubeh}(h]h ]h"]h$]h&]hhuh1jyhj*hhhj<hMpubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj&hhhj<hMpubah}(h]j!ah ](jjeh"]h$]h&]jj)jhuh1jhj<hMphj#hhubj)}(hhh]h)}(hSet up major link parametersh]hSet up major link parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMghjhhubah}(h]h ]h"]h$]h&]uh1jhj#hhhj<hMpubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(hXE**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``u8 bw_code`` The link bandwidth as a multiple of 270 MHz ``u8 lane_cnt`` The number of lanes to use ``bool enhanced`` Use enhanced framing ``bool downspread`` Enable spread-spectrum clocking **Return** 0 on success, or -errno on failureh](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMkhjubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hj'h]hstruct zynqmp_dp *dp}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj%ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhhj!ubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhhj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhj<hMhhjubh)}(h;``u8 bw_code`` The link bandwidth as a multiple of 270 MHz h](j)}(h``u8 bw_code``h]jB)}(hj`h]h u8 bw_code}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMihjZubj)}(hhh]h)}(h+The link bandwidth as a multiple of 270 MHzh]h+The link bandwidth as a multiple of 270 MHz}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMihjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1hhjuhMihjubh)}(h+``u8 lane_cnt`` The number of lanes to use h](j)}(h``u8 lane_cnt``h]jB)}(hjh]h u8 lane_cnt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMjhjubj)}(hhh]h)}(hThe number of lanes to useh]hThe number of lanes to use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMjhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMjhjubh)}(h'``bool enhanced`` Use enhanced framing h](j)}(h``bool enhanced``h]jB)}(hj҂h]h bool enhanced}(hjԂhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjЂubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMkhĵubj)}(hhh]h)}(hUse enhanced framingh]hUse enhanced framing}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMkhjubah}(h]h ]h"]h$]h&]uh1jhĵubeh}(h]h ]h"]h$]h&]uh1hhjhMkhjubh)}(h4``bool downspread`` Enable spread-spectrum clocking h](j)}(h``bool downspread``h]jB)}(hj h]hbool downspread}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMlhjubj)}(hhh]h)}(hEnable spread-spectrum clockingh]hEnable spread-spectrum clocking}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMlhj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hMlhjubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(h **Return**h]j!)}(hjFh]hReturn}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjDubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMnhjubh)}(h"0 on success, or -errno on failureh]h"0 on success, or -errno on failure}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_train (C function)c.zynqmp_dp_trainhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h*int zynqmp_dp_train (struct zynqmp_dp *dp)h]j)}(h)int zynqmp_dp_train(struct zynqmp_dp *dp)h](jB)}(hinth]hint}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hzynqmp_dp_trainh]j)}(hzynqmp_dp_trainh]hzynqmp_dp_train}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjȃhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjăubj)}(h h]h }(hjՃhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjăubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_trainasbuh1hhjăubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjăubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjăubj)}(hdph]hdp}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjăubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jyhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhMubah}(h]j~ah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hTrain the linkh]hTrain the link}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjHhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j functioneh"]h$]h&]jj jjcjjcjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Return** 0 if all trains are done successfully, or corresponding error code.h](h)}(h**Parameters**h]j!)}(hjmh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j hjkubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjgubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1hhjgubh)}(h **Return**h]j!)}(hjDŽh]hReturn}(hjɄhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjńubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjgubh)}(hC0 if all trains are done successfully, or corresponding error code.h]hC0 if all trains are done successfully, or corresponding error code.}(hj݄hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j!zynqmp_dp_train_loop (C function)c.zynqmp_dp_train_loophNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h0void zynqmp_dp_train_loop (struct zynqmp_dp *dp)h]j)}(h/void zynqmp_dp_train_loop(struct zynqmp_dp *dp)h](jB)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hzynqmp_dp_train_looph]j)}(hzynqmp_dp_train_looph]hzynqmp_dp_train_loop}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(h h]h }(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjimodnameN classnameNjj)}j]j)}jj/sbc.zynqmp_dp_train_loopasbuh1hhjEubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjAubah}(h]h ]h"]h$]h&]hhuh1jyhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h'Downshift the link rate during trainingh]h'Downshift the link rate during training}(hj̅hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjɅhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Train the link by downshifting the link rate if training is not successful.h](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hj h]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj"hMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hjHh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjFubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hKTrain the link by downshifting the link rate if training is not successful.h]hKTrain the link by downshifting the link rate if training is not successful.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_dp_aux_cmd_submit (C function)c.zynqmp_dp_aux_cmd_submithNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hdint zynqmp_dp_aux_cmd_submit (struct zynqmp_dp *dp, u32 cmd, u16 addr, u8 *buf, u8 bytes, u8 *reply)h]j)}(hcint zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr, u8 *buf, u8 bytes, u8 *reply)h](jB)}(hinth]hint}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hzynqmp_dp_aux_cmd_submith]j)}(hzynqmp_dp_aux_cmd_submith]hzynqmp_dp_aux_cmd_submit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubjz)}(hG(struct zynqmp_dp *dp, u32 cmd, u16 addr, u8 *buf, u8 bytes, u8 *reply)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjʆhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƆubj)}(h h]h }(hj׆hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƆubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_aux_cmd_submitasbuh1hhjƆubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƆubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƆubj)}(hdph]hdp}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƆubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj†ubj)}(hu32 cmdh](h)}(hhh]j)}(hu32h]hu32}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjAmodnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhj8ubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(hcmdh]hcmd}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj†ubj)}(hu16 addrh](h)}(hhh]j)}(hu16h]hu16}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(haddrh]haddr}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj†ubj)}(hu8 *bufh](h)}(hhh]j)}(hu8h]hu8}(hjχhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̇ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjчmodnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhjȇubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȇubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȇubj)}(hbufh]hbuf}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȇubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj†ubj)}(hu8 bytesh](h)}(hhh]j)}(hu8h]hu8}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj&modnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhjubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hbytesh]hbytes}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj†ubj)}(h u8 *replyh](h)}(hhh]j)}(hu8h]hu8}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjnmodnameN classnameNjj)}j]jc.zynqmp_dp_aux_cmd_submitasbuh1hhjeubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj)}(hreplyh]hreply}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj†ubeh}(h]h ]h"]h$]h&]hhuh1jyhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hSubmit aux commandh]hSubmit aux command}(hjψhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj̈hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``u32 cmd`` aux command ``u16 addr`` aux address ``u8 *buf`` buffer for command data ``u8 bytes`` number of bytes for **buf** ``u8 *reply`` reply code to be returned **Description** Submit an aux command. All aux related commands, native or i2c aux read/write, are submitted through this function. The function is mapped to the transfer function of struct drm_dp_aux. This function involves in multiple register reads/writes, thus synchronization is needed, and it is done by drm_dp_helper using **hw_mutex**. The calling thread goes into sleep if there's no immediate reply to the command submission. The reply code is returned at **reply** if **reply** != NULL. **Return** 0 if the command is submitted properly, or corresponding error code: -EBUSY when there is any request already being processed -ETIMEDOUT when receiving reply is timed out -EIO when received bytes are less than requestedh](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj ubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMhj&ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj%hMhjubh)}(h``u32 cmd`` aux command h](j)}(h ``u32 cmd``h]jB)}(hjIh]hu32 cmd}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjGubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjCubj)}(hhh]h)}(h aux commandh]h aux command}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hMhj_ubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1hhj^hMhjubh)}(h``u16 addr`` aux address h](j)}(h ``u16 addr``h]jB)}(hjh]hu16 addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj|ubj)}(hhh]h)}(h aux addressh]h aux address}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h$``u8 *buf`` buffer for command data h](j)}(h ``u8 *buf``h]jB)}(hjh]hu8 *buf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hbuffer for command datah]hbuffer for command data}(hjԉhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjЉhMhjщubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjЉhMhjubh)}(h)``u8 bytes`` number of bytes for **buf** h](j)}(h ``u8 bytes``h]jB)}(hjh]hu8 bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hnumber of bytes for **buf**h](hnumber of bytes for }(hj hhhNhNubj!)}(h**buf**h]hbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hMhjubh)}(h(``u8 *reply`` reply code to be returned h](j)}(h ``u8 *reply``h]jB)}(hj;h]h u8 *reply}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj9ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj5ubj)}(hhh]h)}(hreply code to be returnedh]hreply code to be returned}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1hhjPhMhjubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hjvh]h Description}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjtubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hXSubmit an aux command. All aux related commands, native or i2c aux read/write, are submitted through this function. The function is mapped to the transfer function of struct drm_dp_aux. This function involves in multiple register reads/writes, thus synchronization is needed, and it is done by drm_dp_helper using **hw_mutex**. The calling thread goes into sleep if there's no immediate reply to the command submission. The reply code is returned at **reply** if **reply** != NULL.h](hX:Submit an aux command. All aux related commands, native or i2c aux read/write, are submitted through this function. The function is mapped to the transfer function of struct drm_dp_aux. This function involves in multiple register reads/writes, thus synchronization is needed, and it is done by drm_dp_helper using }(hjhhhNhNubj!)}(h **hw_mutex**h]hhw_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh~. The calling thread goes into sleep if there’s no immediate reply to the command submission. The reply code is returned at }(hjhhhNhNubj!)}(h **reply**h]hreply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh if }(hjhhhNhNubj!)}(h **reply**h]hreply}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh != NULL.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(h **Return**h]j!)}(hjӊh]hReturn}(hjՊhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjъubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubh)}(h0 if the command is submitted properly, or corresponding error code: -EBUSY when there is any request already being processed -ETIMEDOUT when receiving reply is timed out -EIO when received bytes are less than requestedh]h0 if the command is submitted properly, or corresponding error code: -EBUSY when there is any request already being processed -ETIMEDOUT when receiving reply is timed out -EIO when received bytes are less than requested}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](jzynqmp_dp_aux_init (C function)c.zynqmp_dp_aux_inithNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h-int zynqmp_dp_aux_init (struct zynqmp_dp *dp)h]j)}(h,int zynqmp_dp_aux_init(struct zynqmp_dp *dp)h](jB)}(hinth]hint}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMwubj)}(h h]h }(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj&hMwubj)}(hzynqmp_dp_aux_inith]j)}(hzynqmp_dp_aux_inith]hzynqmp_dp_aux_init}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj&hMwubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjumodnameN classnameNjj)}j]j)}jj;sbc.zynqmp_dp_aux_initasbuh1hhjQubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjMubah}(h]h ]h"]h$]h&]hhuh1jyhjhhhj&hMwubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhj&hMwubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj&hMwhj hhubj)}(hhh]h)}(h"Initialize and register the DP AUXh]h"Initialize and register the DP AUX}(hj؋hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMphjՋhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj&hMwubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Program the AUX clock divider and filter and register the DP AUX adapter. **Return** 0 on success, error value otherwiseh](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMthjubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMqhjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMqhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj.hMqhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hjTh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjRubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMshjubh)}(hIProgram the AUX clock divider and filter and register the DP AUX adapter.h]hIProgram the AUX clock divider and filter and register the DP AUX adapter.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMshjubh)}(h **Return**h]j!)}(hj{h]hReturn}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjyubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMuhjubh)}(h#0 on success, error value otherwiseh]h#0 on success, error value otherwise}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMuhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j"zynqmp_dp_aux_cleanup (C function)c.zynqmp_dp_aux_cleanuphNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h1void zynqmp_dp_aux_cleanup (struct zynqmp_dp *dp)h]j)}(h0void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp)h](jB)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjόhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjΌhMubj)}(hzynqmp_dp_aux_cleanuph]j)}(hzynqmp_dp_aux_cleanuph]hzynqmp_dp_aux_cleanup}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj݌ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjΌhMubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_aux_cleanupasbuh1hhjubj)}(h h]h }(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jyhjhhhjΌhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjΌhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjΌhMhjhhubj)}(hhh]h)}(hCleanup the DP AUXh]hCleanup the DP AUX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj}hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjΌhMubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(hy**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Unregister the DP AUX adapter.h](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjÍhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjڍhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj֍hMhj׍ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj֍hMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hUnregister the DP AUX adapter.h]hUnregister the DP AUX adapter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j"zynqmp_dp_update_misc (C function)c.zynqmp_dp_update_mischNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h1void zynqmp_dp_update_misc (struct zynqmp_dp *dp)h]j)}(h0void zynqmp_dp_update_misc(struct zynqmp_dp *dp)h](jB)}(hvoidh]hvoid}(hjAhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj=hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhhjOhMubj)}(hzynqmp_dp_update_misch]j)}(hzynqmp_dp_update_misch]hzynqmp_dp_update_misc}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj=hhhjOhMubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjdsbc.zynqmp_dp_update_miscasbuh1hhjzubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(hjh]h*}(hjʎhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(hdph]hdp}(hj׎hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjvubah}(h]h ]h"]h$]h&]hhuh1jyhj=hhhjOhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj9hhhjOhMubah}(h]j4ah ](jjeh"]h$]h&]jj)jhuh1jhjOhMhj6hhubj)}(hhh]h)}(hWrite the misc registersh]hWrite the misc registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj6hhhjOhMubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** The misc register values are stored in the structure, and this function applies the values into the registers.h](h)}(h**Parameters**h]j!)}(hj#h]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj!ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjBh]hstruct zynqmp_dp *dp}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj@ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj<ubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhMhjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1hhjWhMhj9ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hj}h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj{ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hnThe misc register values are stored in the structure, and this function applies the values into the registers.h]hnThe misc register values are stored in the structure, and this function applies the values into the registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j!zynqmp_dp_set_format (C function)c.zynqmp_dp_set_formathNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hint zynqmp_dp_set_format (struct zynqmp_dp *dp, const struct drm_display_info *info, enum zynqmp_dpsub_format format, unsigned int bpc)h]j)}(hint zynqmp_dp_set_format(struct zynqmp_dp *dp, const struct drm_display_info *info, enum zynqmp_dpsub_format format, unsigned int bpc)h](jB)}(hinth]hint}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjяhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjЏhMubj)}(hzynqmp_dp_set_formath]j)}(hzynqmp_dp_set_formath]hzynqmp_dp_set_format}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjߏubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjЏhMubjz)}(hn(struct zynqmp_dp *dp, const struct drm_display_info *info, enum zynqmp_dpsub_format format, unsigned int bpc)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_set_formatasbuh1hhjubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h#const struct drm_display_info *infoh](j)}(hjth]hconst}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubh)}(hhh]j)}(hdrm_display_infoh]hdrm_display_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j9c.zynqmp_dp_set_formatasbuh1hhjmubj)}(h h]h }(hjȐhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(hjh]h*}(hj֐hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum zynqmp_dpsub_format formath](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hzynqmp_dpsub_formath]hzynqmp_dpsub_format}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j9c.zynqmp_dp_set_formatasbuh1hhjubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hformath]hformat}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int bpch](jB)}(hunsignedh]hunsigned}(hj_hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj[ubj)}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubjB)}(hinth]hint}(hj{hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj[ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubj)}(hbpch]hbpc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jyhjhhhjЏhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjЏhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjЏhMhjhhubj)}(hhh]h)}(hSet the input formath]hSet the input format}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjЏhMubeh}(h]h ](j functioneh"]h$]h&]jj jjّjjّjjjuh1jhhhjfhNhNubj)}(hX[**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``const struct drm_display_info *info`` Display info ``enum zynqmp_dpsub_format format`` input format ``unsigned int bpc`` bits per component **Description** Update misc register values based on input **format** and **bpc**. **Return** 0 on success, or -EINVAL.h](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjݑubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h5``const struct drm_display_info *info`` Display info h](j)}(h'``const struct drm_display_info *info``h]jB)}(hj;h]h#const struct drm_display_info *info}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj9ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj5ubj)}(hhh]h)}(h Display infoh]h Display info}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1hhjPhMhjubh)}(h1``enum zynqmp_dpsub_format format`` input format h](j)}(h#``enum zynqmp_dpsub_format format``h]jB)}(hjth]henum zynqmp_dpsub_format format}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjrubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjnubj)}(hhh]h)}(h input formath]h input format}(hjhhhNhNubah}(h]h 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hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjݑubh)}(h **Return**h]j!)}(hj3h]hReturn}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj1ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjݑubh)}(h0 on success, or -EINVAL.h]h0 on success, or -EINVAL.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjݑubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j5zynqmp_dp_encoder_mode_set_transfer_unit (C function)*c.zynqmp_dp_encoder_mode_set_transfer_unithNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hivoid zynqmp_dp_encoder_mode_set_transfer_unit (struct zynqmp_dp *dp, const struct drm_display_mode *mode)h]j)}(hhvoid zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp, const struct drm_display_mode *mode)h](jB)}(hvoidh]hvoid}(hjxhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjthhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjthhhjhMubj)}(h(zynqmp_dp_encoder_mode_set_transfer_unith]j)}(h(zynqmp_dp_encoder_mode_set_transfer_unith]h(zynqmp_dp_encoder_mode_set_transfer_unit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjthhhjhMubjz)}(h;(struct zynqmp_dp *dp, const struct drm_display_mode *mode)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj“hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjӓhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjГubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjՓmodnameN classnameNjj)}j]j)}jjsb*c.zynqmp_dp_encoder_mode_set_transfer_unitasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h#const struct drm_display_mode *modeh](j)}(hjth]hconst}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hjh]hstruct}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubh)}(hhh]j)}(hdrm_display_modeh]hdrm_display_mode}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjbmodnameN classnameNjj)}j]j*c.zynqmp_dp_encoder_mode_set_transfer_unitasbuh1hhj#ubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hmodeh]hmode}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jyhjthhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjphhhjhMubah}(h]jkah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjmhhubj)}(hhh]h)}(hSet the transfer unit valuesh]hSet the transfer unit values}(hjÔhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjmhhhjhMubeh}(h]h ](j functioneh"]h$]h&]jj jj۔jj۔jjjuh1jhhhjfhNhNubj)}(hX**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``const struct drm_display_mode *mode`` requested display mode **Description** Set the transfer unit, and calculate all transfer unit size related values. Calculation is based on DP and IP core specification.h](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjߔubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h?``const struct drm_display_mode *mode`` requested display mode h](j)}(h'``const struct drm_display_mode *mode``h]jB)}(hj=h]h#const struct drm_display_mode *mode}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj;ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj7ubj)}(hhh]h)}(hrequested display modeh]hrequested display mode}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhMhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1hhjRhMhjubeh}(h]h ]h"]h$]h&]uh1hhjߔubh)}(h**Description**h]j!)}(hjxh]h Description}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjvubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjߔubh)}(hSet the transfer unit, and calculate all transfer unit size related values. Calculation is based on DP and IP core specification.h]hSet the transfer unit, and calculate all transfer unit size related values. Calculation is based on DP and IP core specification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjߔubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j.zynqmp_dp_encoder_mode_set_stream (C function)#c.zynqmp_dp_encoder_mode_set_streamhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hbvoid zynqmp_dp_encoder_mode_set_stream (struct zynqmp_dp *dp, const struct drm_display_mode *mode)h]j)}(havoid zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp, const struct drm_display_mode *mode)h](jB)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM<ubj)}(h h]h }(hj̕hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj˕hM<ubj)}(h!zynqmp_dp_encoder_mode_set_streamh]j)}(h!zynqmp_dp_encoder_mode_set_streamh]h!zynqmp_dp_encoder_mode_set_stream}(hjޕhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjڕubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj˕hM<ubjz)}(h;(struct zynqmp_dp *dp, const struct drm_display_mode *mode)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb#c.zynqmp_dp_encoder_mode_set_streamasbuh1hhjubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h#const struct drm_display_mode *modeh](j)}(hjth]hconst}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubh)}(hhh]j)}(hdrm_display_modeh]hdrm_display_mode}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j4#c.zynqmp_dp_encoder_mode_set_streamasbuh1hhjhubj)}(h h]h }(hjÖhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(hjh]h*}(hjіhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(hmodeh]hmode}(hjޖhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jyhjhhhj˕hM<ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhj˕hM<ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj˕hM<hjhhubj)}(hhh]h)}(hConfigure the main streamh]hConfigure the main stream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM5hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj˕hM<ubeh}(h]h ](j functioneh"]h$]h&]jj jj jj jjjuh1jhhhjfhNhNubj)}(hX **Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``const struct drm_display_mode *mode`` requested display mode **Description** Configure the main stream based on the requested mode **mode**. Calculation is based on IP core specification.h](h)}(h**Parameters**h]j!)}(hj*h]h Parameters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj(ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM9hj$ubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjIh]hstruct zynqmp_dp *dp}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjGubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM6hjCubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hM6hj_ubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1hhj^hM6hj@ubh)}(h?``const struct drm_display_mode *mode`` requested display mode h](j)}(h'``const struct drm_display_mode *mode``h]jB)}(hjh]h#const struct drm_display_mode *mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM7hj|ubj)}(hhh]h)}(hrequested display modeh]hrequested display mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM7hjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1hhjhM7hj@ubeh}(h]h ]h"]h$]h&]uh1hhj$ubh)}(h**Description**h]j!)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM9hj$ubh)}(hnConfigure the main stream based on the requested mode **mode**. Calculation is based on IP core specification.h](h6Configure the main stream based on the requested mode }(hjӗhhhNhNubj!)}(h**mode**h]hmode}(hjۗhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjӗubh0. Calculation is based on IP core specification.}(hjӗhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM9hj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j0zynqmp_dp_disp_connected_live_layer (C function)%c.zynqmp_dp_disp_connected_live_layerhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hUstruct zynqmp_disp_layer * zynqmp_dp_disp_connected_live_layer (struct zynqmp_dp *dp)h]j)}(hSstruct zynqmp_disp_layer *zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp)h](j)}(hjh]hstruct}(hjhhhNhNubah}(hq]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj!hMubh)}(hhh]j)}(hzynqmp_disp_layerh]hzynqmp_disp_layer}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj5modnameN classnameNjj)}j]j)}j#zynqmp_dp_disp_connected_live_layersb%c.zynqmp_dp_disp_connected_live_layerasbuh1hhjhhhj!hMubj)}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj!hMubj)}(hjh]h*}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj!hMubj)}(h#zynqmp_dp_disp_connected_live_layerh]j)}(hjQh]h#zynqmp_dp_disp_connected_live_layer}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj!hMubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]jO%c.zynqmp_dp_disp_connected_live_layerasbuh1hhjubj)}(h h]h }(hjʘhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjؘhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jyhjhhhj!hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj!hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj!hMhj hhubj)}(hhh]h)}(h%Return the first connected live layerh]h%Return the first connected live layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj!hMubeh}(h]h ](j functioneh"]h$]h&]jj jj'jj'jjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Return** The first connected live display layer or NULL if none of the live layers are connected.h](h)}(h**Parameters**h]j!)}(hj1h]h Parameters}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj/ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj+ubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjPh]hstruct zynqmp_dp *dp}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjNubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjJubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMhjfubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1hhjehMhjGubah}(h]h ]h"]h$]h&]uh1hhj+ubh)}(h **Return**h]j!)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj+ubh)}(hXThe first connected live display layer or NULL if none of the live layers are connected.h]hXThe first connected live display layer or NULL if none of the live layers are connected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j'zynqmp_dp_set_test_pattern (C function)c.zynqmp_dp_set_test_patternhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(hbint zynqmp_dp_set_test_pattern (struct zynqmp_dp *dp, enum test_pattern pattern, u8 *const custom)h]j)}(haint zynqmp_dp_set_test_pattern(struct zynqmp_dp *dp, enum test_pattern pattern, u8 *const custom)h](jB)}(hinth]hint}(hjЙhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj̙hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMubj)}(h h]h }(hjߙhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̙hhhjޙhMubj)}(hzynqmp_dp_set_test_patternh]j)}(hzynqmp_dp_set_test_patternh]hzynqmp_dp_set_test_pattern}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj̙hhhjޙhMubjz)}(hC(struct zynqmp_dp *dp, enum test_pattern pattern, u8 *const custom)h](j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj-modnameN classnameNjj)}j]j)}jjsbc.zynqmp_dp_set_test_patternasbuh1hhj ubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hjh]h*}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hdph]hdp}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum test_pattern patternh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubh)}(hhh]j)}(h test_patternh]h test_pattern}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]jGc.zynqmp_dp_set_test_patternasbuh1hhj{ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj)}(hpatternh]hpattern}(hjɚhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hu8 *const customh](h)}(hhh]j)}(hu8h]hu8}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]jGc.zynqmp_dp_set_test_patternasbuh1hhjޚubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޚubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޚubj)}(hjth]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޚubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޚubj)}(hcustomh]hcustom}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޚubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jyhj̙hhhjޙhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjșhhhjޙhMubah}(h]jÙah ](jjeh"]h$]h&]jj)jhuh1jhjޙhMhjřhhubj)}(hhh]h)}(h%Configure the link for a test patternh]h%Configure the link for a test pattern}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhj`hhubah}(h]h ]h"]h$]h&]uh1jhjřhhhjޙhMubeh}(h]h ](j functioneh"]h$]h&]jj jj{jj{jjjuh1jhhhjfhNhNubj)}(hX **Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure ``enum test_pattern pattern`` The test pattern to configure ``u8 *const custom`` The custom pattern to use if **pattern** is ``TEST_80BIT_CUSTOM`` **Return** 0 on success, or negative errno on (DPCD) failureh](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(hhh](h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h<``enum test_pattern pattern`` The test pattern to configure h](j)}(h``enum test_pattern pattern``h]jB)}(hjݛh]henum test_pattern pattern}(hjߛhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjۛubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjכubj)}(hhh]h)}(hThe test pattern to configureh]hThe test pattern to configure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjכubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hW``u8 *const custom`` The custom pattern to use if **pattern** is ``TEST_80BIT_CUSTOM`` h](j)}(h``u8 *const custom``h]jB)}(hjh]hu8 *const custom}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubj)}(hhh]h)}(hAThe custom pattern to use if **pattern** is ``TEST_80BIT_CUSTOM``h](hThe custom pattern to use if }(hj/hhhNhNubj!)}(h **pattern**h]hpattern}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj/ubh is }(hj/hhhNhNubjB)}(h``TEST_80BIT_CUSTOM``h]hTEST_80BIT_CUSTOM}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj/ubeh}(h]h ]h"]h$]h&]uh1hhj+hMhj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj+hMhjubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(h **Return**h]j!)}(hjqh]hReturn}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j hjoubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubh)}(h10 on success, or negative errno on (DPCD) failureh]h10 on success, or negative errno on (DPCD) failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j$zynqmp_dp_enable_vblank (C function)c.zynqmp_dp_enable_vblankhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h3void zynqmp_dp_enable_vblank (struct zynqmp_dp *dp)h]j)}(h2void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)h](jB)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM ubj)}(h h]h }(hjŜhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjĜhM ubj)}(hzynqmp_dp_enable_vblankh]j)}(hzynqmp_dp_enable_vblankh]hzynqmp_dp_enable_vblank}(hjלhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjӜubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjĜhM ubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjٜsbc.zynqmp_dp_enable_vblankasbuh1hhjubj)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdph]hdp}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jyhjhhhjĜhM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjĜhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjĜhM hjhhubj)}(hhh]h)}(h Enable vblankh]h Enable vblank}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjshhubah}(h]h ]h"]h$]h&]uh1jhjhhhjĜhM ubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(hr**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Enable vblank interrupth](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hjh]hstruct zynqmp_dp *dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjНhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj̝hM hj͝ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj̝hM hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubh)}(hEnable vblank interrupth]hEnable vblank interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubjx)}(hhh]h}(h]h ]h"]h$]h&]entries](j%zynqmp_dp_disable_vblank (C function)c.zynqmp_dp_disable_vblankhNtauh1jwhjfhhhNhNubj)}(hhh](j)}(h4void zynqmp_dp_disable_vblank (struct zynqmp_dp *dp)h]j)}(h3void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)h](jB)}(hvoidh]hvoid}(hj7hhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhj3hhh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM& ubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3hhhjEhM& ubj)}(hzynqmp_dp_disable_vblankh]j)}(hzynqmp_dp_disable_vblankh]hzynqmp_dp_disable_vblank}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ](jjeh"]h$]h&]hhuh1jhj3hhhjEhM& ubjz)}(h(struct zynqmp_dp *dp)h]j)}(hstruct zynqmp_dp *dph](j)}(hjh]hstruct}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubh)}(hhh]j)}(h zynqmp_dph]h zynqmp_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jjZsbc.zynqmp_dp_disable_vblankasbuh1hhjpubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubj)}(hdph]hdp}(hj͞hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjlubah}(h]h ]h"]h$]h&]hhuh1jyhj3hhhjEhM& ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj/hhhjEhM& ubah}(h]j*ah ](jjeh"]h$]h&]jj)jhuh1jhjEhM& hj,hhubj)}(hhh]h)}(hDisable vblankh]hDisable vblank}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM! hjhhubah}(h]h ]h"]h$]h&]uh1jhj,hhhjEhM& ubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(hs**Parameters** ``struct zynqmp_dp *dp`` DisplayPort IP core structure **Description** Disable vblank interrupth](h)}(h**Parameters**h]j!)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM% hjubh)}(hhh]h)}(h7``struct zynqmp_dp *dp`` DisplayPort IP core structure h](j)}(h``struct zynqmp_dp *dp``h]jB)}(hj8h]hstruct zynqmp_dp *dp}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj6ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM" hj2ubj)}(hhh]h)}(hDisplayPort IP core structureh]hDisplayPort IP core structure}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhM" hjNubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhjMhM" hj/ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]j!)}(hjsh]h Description}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjqubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:145: ./drivers/gpu/drm/xlnx/zynqmp_dp.chM$ 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*dpsubh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h zynqmp_dpsubh]h zynqmp_dpsub}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNjj)}j]j)}jj۟sb c.zynqmp_dpsub_drm_handle_vblankasbuh1hhjubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdpsubh]hdpsub}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jyhjhhhjƟhM`ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjƟhM`ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjƟhM`hjhhubj)}(hhh]h)}(hHandle the vblank eventh]hHandle the vblank event}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/zynqmp:147: ./drivers/gpu/drm/xlnx/zynqmp_kms.chMZhjuhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjƟhM`ubeh}(h]h ](j functioneh"]h$]h&]jj jjjjjjjuh1jhhhjfhNhNubj)}(h**Parameters** ``struct zynqmp_dpsub *dpsub`` DisplayPort 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