sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget /translations/zh_CN/gpu/xe/xe_wamodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/zh_TW/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/it_IT/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/ja_JP/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/ko_KR/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/pt_BR/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/sp_SP/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)h]h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh:/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa.rsthKubhsection)}(hhh](htitle)}(hHardware workaroundsh]hHardware workarounds}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:h]hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKhhhhubh bullet_list)}(hhh](h list_item)}(hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers. See drivers/gpu/drm/xe/xe_lrc.c for default context handling. h]h)}(hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers. See drivers/gpu/drm/xe/xe_lrc.c for default context handling.h]hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a “primed golden context”, i.e. a context image that already contains the changes needed to all the registers. See drivers/gpu/drm/xe/xe_lrc.c for default context handling.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK$hhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved is written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See drivers/gpu/drm/xe/xe_guc_ads.c for reference. h]h)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved is written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See drivers/gpu/drm/xe/xe_guc_ads.c for reference.h]hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It’s also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved is written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See drivers/gpu/drm/xe/xe_guc_ads.c for reference.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK,hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc. h]h)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc.h](hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume }(hj+hhhNhNubhfootnote_reference)}(h[1]_h]h1}(hj5hhhNhNubah}(h]id1ah ]h"]h$]h&]refidid2docname gpu/xe/xe_wauh1j3hj+resolvedKubh, etc.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK8hj'ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hXeRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers). h]h)}(hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).h]hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK;hjZubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hXWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled via these hardware mechanisms: #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. When a context is being restored, this is executed after the ring context, in the middle (or beginning) of the engine context image. #. BB_PER_CTX_PTR (also known as **post context restore bb**): A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. Below is the timeline for a context restore sequence: .. code:: INDIRECT_CTX_OFFSET |----------->| .------------.------------.-------------.------------.--------------.-----------. |Ring | Engine | Mid-context | Engine | Post-context | Ring | |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | `------------'------------'-------------'------------'--------------'-----------' h](h)}(hXVWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled via these hardware mechanisms:h]hXVWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled via these hardware mechanisms:}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKAhjsubhenumerated_list)}(hhh](h)}(hXcINDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. When a context is being restored, this is executed after the ring context, in the middle (or beginning) of the engine context image. h]h)}(hXbINDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. When a context is being restored, this is executed after the ring context, in the middle (or beginning) of the engine context image.h](hINDIRECT_CTX (also known as }(hjhhhNhNubhstrong)}(h**mid context restore bb**h]hmid context restore bb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX,): A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. When a context is being restored, this is executed after the ring context, in the middle (or beginning) of the engine context image.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKGhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hBB_PER_CTX_PTR (also known as **post context restore bb**): A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. h]h)}(hBB_PER_CTX_PTR (also known as **post context restore bb**): A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence.h](hBB_PER_CTX_PTR (also known as }(hjhhhNhNubj)}(h**post context restore bb**h]hpost context restore bb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh): A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjsubh)}(h5Below is the timeline for a context restore sequence:h]h5Below is the timeline for a context restore sequence:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKRhjsubh literal_block)}(hX INDIRECT_CTX_OFFSET |----------->| .------------.------------.-------------.------------.--------------.-----------. |Ring | Engine | Mid-context | Engine | Post-context | Ring | |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | `------------'------------'-------------'------------'--------------'-----------'h]hX INDIRECT_CTX_OFFSET |----------->| .------------.------------.-------------.------------.--------------.-----------. |Ring | Engine | Mid-context | Engine | Post-context | Ring | |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | `------------'------------'-------------'------------'--------------'-----------'}hjsbah}(h]h ]h"]h$]h&]forcehighlight_args}hhƌlanguagenoneuh1jhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKThjsubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hXEOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. There's a central place to control which workarounds are enabled: drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. These files only record which workarounds are enabled: during early device initialization those rules are evaluated and recorded by the driver. Then later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to implement them. h]h)}(hXDOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. There's a central place to control which workarounds are enabled: drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. These files only record which workarounds are enabled: during early device initialization those rules are evaluated and recorded by the driver. Then later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to implement them.h](hXOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. There’s a central place to control which workarounds are enabled: drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. These files only record which workarounds are enabled: during early device initialization those rules are evaluated and recorded by the driver. Then later the driver checks with }(hjhhhNhNubhliteral)}(h``XE_GT_WA()``h]h XE_GT_WA()}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh and }(hjhhhNhNubj&)}(h``XE_DEVICE_WA()``h]hXE_DEVICE_WA()}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh to implement them.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK]hjubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]bullet-uh1hhjhK$hhhhubhfootnote)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver. h](hlabel)}(h1h]h1}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjbubh)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver.h]hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it’s the approach taken in the driver.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKghjbubeh}(h]jEah ]h"]1ah$]h&]j?ajFjGuh1j`hjhKghhhhjHKubhnote)}(hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.h]h)}(hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.h]hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKlhjubah}(h]h ]h"]h$]h&]uh1jhhhhhNhNubj)}(hX{When a workaround applies to every single known IP version in a range, the preferred handling is to use a single range-based RTP entry rather than individual entries for each version, even if some of the intermediate version numbers are currently unused. If a new intermediate IP version appears in the future and is enabled in the driver, any existing range-based entries that contain the new version number will need to be analyzed to determine whether their workarounds should apply to the new version, or whether any existing range based entries needs to be split into two entries that do not include the new intermediate version.h]h)}(hX{When a workaround applies to every single known IP version in a range, the preferred handling is to use a single range-based RTP entry rather than individual entries for each version, even if some of the intermediate version numbers are currently unused. If a new intermediate IP version appears in the future and is enabled in the driver, any existing range-based entries that contain the new version number will need to be analyzed to determine whether their workarounds should apply to the new version, or whether any existing range based entries needs to be split into two entries that do not include the new intermediate version.h]hX{When a workaround applies to every single known IP version in a range, the preferred handling is to use a single range-based RTP entry rather than individual entries for each version, even if some of the intermediate version numbers are currently unused. If a new intermediate IP version appears in the future and is enabled in the driver, any existing range-based entries that contain the new version number will need to be analyzed to determine whether their workarounds should apply to the new version, or whether any existing range based entries needs to be split into two entries that do not include the new intermediate version.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKrhjubah}(h]h ]h"]h$]h&]uh1jhhhhhNhNubh)}(hhh](h)}(h Internal APIh]h Internal API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK ubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single%xe_wa_process_device_oob (C function)c.xe_wa_process_device_oobhNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(h4void xe_wa_process_device_oob (struct xe_device *xe)h]hdesc_signature_line)}(h3void xe_wa_process_device_oob(struct xe_device *xe)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h 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ubh)}(hhh]j)}(hxe_gth]hxe_gt}(hj hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjxreftypejz reftargetj modnameN classnameNj~j)}j]j)}jzj sbc.xe_wa_gt_initasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hgth]hgt}(hj% hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1j;hj ubah}(h]h ]h"]h$]h&]hhuh1j5hj hhhj hMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hMhj hhubj)}(hhh]h)}(h)initialize gt with workaround bookkeepingh]h)initialize gt with workaround bookkeeping}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1hhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhjL hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jxfunctioneh"]h$]h&]jjxjjg jjg jjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct xe_gt *gt`` GT instance to initialize **Description** Returns 0 for success, negative error code otherwise.h](h)}(h**Parameters**h]j)}(hjq h]h Parameters}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo ubah}(h]h ]h"]h$]h&]uh1hhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhjk ubj )}(hhh]j%)}(h/``struct xe_gt *gt`` GT instance to initialize h](j+)}(h``struct xe_gt *gt``h]j&)}(hj h]hstruct xe_gt *gt}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubah}(h]h ]h"]h$]h&]uh1j*hW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhj ubjE)}(hhh]h)}(hGT instance to initializeh]hGT instance to initialize}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jDhj ubeh}(h]h ]h"]h$]h&]uh1j$hj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjk ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhjk ubh)}(h5Returns 0 for success, negative error code otherwise.h]h5Returns 0 for success, negative error code otherwise.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhjk ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jxe_wa_gt_dump (C function)c.xe_wa_gt_dumphNtauh1jhjhhhNhNubj)}(hhh](j)}(h;int xe_wa_gt_dump (struct xe_gt *gt, struct drm_printer *p)h]j)}(h:int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhjhMubj)}(h xe_wa_gt_dumph]j)}(h xe_wa_gt_dumph]h xe_wa_gt_dump}(hj1hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1jhj-ubah}(h]h ](j0j1eh"]h$]h&]hhuh1jhj hhhjhMubj6)}(h)(struct xe_gt *gt, struct drm_printer *p)h](j<)}(hstruct xe_gt *gth](jB)}(hjEh]hstruct}(hjMhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjIubj)}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubh)}(hhh]j)}(hxe_gth]hxe_gt}(hjkhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&] refdomainjxreftypejz reftargetjmmodnameN classnameNj~j)}j]j)}jzj3sbc.xe_wa_gt_dumpasbuh1hhjIubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(hgth]hgt}(hjhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]noemphhhuh1j;hjEubj<)}(hstruct drm_printer *ph](jB)}(hjEh]hstruct}(hjhhhNhNubah}(h]h ]jNah"]h$]h&]uh1jAhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h drm_printerh]h drm_printer}(hjhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjxreftypejz reftargetjmodnameN classnameNj~j)}j]jc.xe_wa_gt_dumpasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hp}(hjhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1j;hjEubeh}(h]h ]h"]h$]h&]hhuh1j5hj hhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h'Dump GT workarounds into a drm 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