sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget /translations/zh_CN/gpu/xe/xe_wamodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/zh_TW/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/it_IT/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/ja_JP/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/ko_KR/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/sp_SP/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)h]h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh:/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa.rsthKubhsection)}(hhh](htitle)}(hHardware workaroundsh]hHardware workarounds}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:h]hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKhhhhubh bullet_list)}(hhh](h list_item)}(hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers. See drivers/gpu/drm/xe/xe_lrc.c for default context handling. h]h)}(hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers. See drivers/gpu/drm/xe/xe_lrc.c for default context handling.h]hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a “primed golden context”, i.e. a context image that already contains the changes needed to all the registers. See drivers/gpu/drm/xe/xe_lrc.c for default context handling.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK#hhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved is written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See drivers/gpu/drm/xe/xe_guc_ads.c for reference. h]h)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved is written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See drivers/gpu/drm/xe/xe_guc_ads.c for reference.h]hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It’s also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved is written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See drivers/gpu/drm/xe/xe_guc_ads.c for reference.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK+hhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc. h]h)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc.h](hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume }(hjhhhNhNubhfootnote_reference)}(h[1]_h]h1}(hj!hhhNhNubah}(h]id1ah ]h"]h$]h&]refidid2docname gpu/xe/xe_wauh1jhjresolvedKubh, etc.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK7hjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hXeRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers). h]h)}(hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).h]hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK:hjFubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hXWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled via these hardware mechanisms: #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. When a context is being restored, this is executed after the ring context, in the middle (or beginning) of the engine context image. #. BB_PER_CTX_PTR (also known as **post context restore bb**): A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. Below is the timeline for a context restore sequence: .. code:: INDIRECT_CTX_OFFSET |----------->| .------------.------------.-------------.------------.--------------.-----------. |Ring | Engine | Mid-context | Engine | Post-context | Ring | |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | `------------'------------'-------------'------------'--------------'-----------' h](h)}(hXVWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled via these hardware mechanisms:h]hXVWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled via these hardware mechanisms:}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK@hj_ubhenumerated_list)}(hhh](h)}(hXcINDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. When a context is being restored, this is executed after the ring context, in the middle (or beginning) of the engine context image. h]h)}(hXbINDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. When a context is being restored, this is executed after the ring context, in the middle (or beginning) of the engine context image.h](hINDIRECT_CTX (also known as }(hj{hhhNhNubhstrong)}(h**mid context restore bb**h]hmid context restore bb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubhX,): A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. When a context is being restored, this is executed after the ring context, in the middle (or beginning) of the engine context image.}(hj{hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKFhjwubah}(h]h ]h"]h$]h&]uh1hhjtubh)}(hBB_PER_CTX_PTR (also known as **post context restore bb**): A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. h]h)}(hBB_PER_CTX_PTR (also known as **post context restore bb**): A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence.h](hBB_PER_CTX_PTR (also known as }(hjhhhNhNubj)}(h**post context restore bb**h]hpost context restore bb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh): A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKLhjubah}(h]h ]h"]h$]h&]uh1hhjtubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jrhj_ubh)}(h5Below is the timeline for a context restore sequence:h]h5Below is the timeline for a context restore sequence:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKQhj_ubh literal_block)}(hX INDIRECT_CTX_OFFSET |----------->| .------------.------------.-------------.------------.--------------.-----------. |Ring | Engine | Mid-context | Engine | Post-context | Ring | |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | `------------'------------'-------------'------------'--------------'-----------'h]hX INDIRECT_CTX_OFFSET |----------->| .------------.------------.-------------.------------.--------------.-----------. |Ring | Engine | Mid-context | Engine | Post-context | Ring | |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | `------------'------------'-------------'------------'--------------'-----------'}hjsbah}(h]h ]h"]h$]h&]forcehighlight_args}hhlanguagenoneuh1jhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKShj_ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hXEOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. There's a central place to control which workarounds are enabled: drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. These files only record which workarounds are enabled: during early device initialization those rules are evaluated and recorded by the driver. Then later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to implement them. h]h)}(hXDOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. There's a central place to control which workarounds are enabled: drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. These files only record which workarounds are enabled: during early device initialization those rules are evaluated and recorded by the driver. Then later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to implement them.h](hXOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. There’s a central place to control which workarounds are enabled: drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. These files only record which workarounds are enabled: during early device initialization those rules are evaluated and recorded by the driver. Then later the driver checks with }(hj hhhNhNubhliteral)}(h``XE_GT_WA()``h]h XE_GT_WA()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh and }(hj hhhNhNubj)}(h``XE_DEVICE_WA()``h]hXE_DEVICE_WA()}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh to implement them.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK\hjubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK#hhhhubhfootnote)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver. h](hlabel)}(h1h]h1}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjNubh)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver.h]hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it’s the approach taken in the driver.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKfhjNubeh}(h]j1ah ]h"]1ah$]h&]j+aj2j3uh1jLhjphKfhhhhj4Kubhnote)}(hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.h]h)}(hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.h]hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKkhjzubah}(h]h ]h"]h$]h&]uh1jxhhhhhNhNubh)}(hhh](h)}(h Internal APIh]h Internal API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK ubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single%xe_wa_process_device_oob (C function)c.xe_wa_process_device_oobhNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(h4void xe_wa_process_device_oob (struct xe_device *xe)h]hdesc_signature_line)}(h3void xe_wa_process_device_oob(struct xe_device *xe)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjhhhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhMubh desc_name)}(hxe_wa_process_device_oobh]h desc_sig_name)}(hxe_wa_process_device_oobh]hxe_wa_process_device_oob}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjhhhjhMubhdesc_parameterlist)}(h(struct xe_device *xe)h]hdesc_parameter)}(hstruct xe_device *xeh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h xe_deviceh]h xe_device}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetj8modnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]jR ASTIdentifier)}jMjsbc.xe_wa_process_device_oobasbuh1hhjubj)}(h h]h }(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubhdesc_sig_punctuation)}(h*h]h*}(hjohhhNhNubah}(h]h ]pah"]h$]h&]uh1jmhjubj)}(hxeh]hxe}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hh add_permalinkuh1jsphinx_line_type declaratorhjhhhjhMubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhMhjhhubh desc_content)}(hhh]h)}(hprocess OOB workaround tableh]hprocess OOB workaround table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jKfunctioneh"]h$]h&]domainjKobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhjhNhNubh container)}(h**Parameters** ``struct xe_device *xe`` device instance to process workarounds for **Description** process OOB workaround table for this device, marking in **xe** the workarounds that are active.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhjubhdefinition_list)}(hhh]hdefinition_list_item)}(hD``struct xe_device *xe`` device instance to process workarounds for h](hterm)}(h``struct xe_device *xe``h]j)}(hjh]hstruct xe_device *xe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhjubh definition)}(hhh]h)}(h*device instance to process workarounds forh]h*device instance to process workarounds for}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj>h]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1hhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMhjubh)}(h`process OOB workaround table for this device, marking in **xe** the workarounds that are active.h](h9process OOB workaround table for this device, marking in }(hjThhhNhNubj)}(h**xe**h]hxe}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubh! the workarounds that are active.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: 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