sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget /translations/zh_CN/gpu/xe/xe_wamodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/zh_TW/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/it_IT/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/ja_JP/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/ko_KR/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/sp_SP/gpu/xe/xe_wamodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)h]h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh:/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa.rsthKubhsection)}(hhh](htitle)}(hHardware workaroundsh]hHardware workarounds}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:h]hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKhhhhubh bullet_list)}(hhh](h list_item)}(hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers. h]h)}(hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers.h]hXLRC workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a “primed golden context”, i.e. a context image that already contains the changes needed to all the registers.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK"hhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference. h]h)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.h](hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It’s also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See }(hhhhhNhNubhliteral)}(h#``drivers/gpu/drm/xe/xe_guc_ads.c``h]hdrivers/gpu/drm/xe/xe_guc_ads.c}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhubh for reference.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK)hhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc. h]h)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc.h](hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume }(hj+hhhNhNubhfootnote_reference)}(h[1]_h]h1}(hj5hhhNhNubah}(h]id1ah ]h"]h$]h&]refidid2docname gpu/xe/xe_wauh1j3hj+resolvedKubh, etc.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK5hj'ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hXeRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers). h]h)}(hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).h]hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK8hjZubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hX`Workaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms: #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms. #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver. h](h)}(hXRWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms:h]hXRWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms:}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chK>hjsubhenumerated_list)}(hhh](h)}(hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms. h]h)}(hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms.h]hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKDhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver. h]h)}(hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver.h]hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKIhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjsubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example. h]h)}(hOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example.h]hOther/OOB: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKNhjubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK"hhhhubhfootnote)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver. h](hlabel)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver.h]hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it’s the approach taken in the driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKRhjubeh}(h]jEah ]h"]1ah$]h&]j?ajFjGuh1jhjhKRhhhhjHKubhnote)}(hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.h]h)}(hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.h]hXHardware workarounds in xe work the same way as in i915, with the difference of how they are maintained in the code. In xe it uses the xe_rtp infrastructure so the workarounds can be kept in tables, following a more declarative approach rather than procedural.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhV/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:7: ./drivers/gpu/drm/xe/xe_wa.chKWhjubah}(h]h ]h"]h$]h&]uh1jhhhhhNhNubh)}(hhh](h)}(h Internal APIh]h Internal API}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhK ubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlexe_wa_process_oob (C function)c.xe_wa_process_oobhNtauh1jGhj6hhhNhNubhdesc)}(hhh](hdesc_signature)}(h)void xe_wa_process_oob (struct xe_gt *gt)h]hdesc_signature_line)}(h(void xe_wa_process_oob(struct xe_gt *gt)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjkhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jihjehhhW/var/lib/git/docbuild/linux/Documentation/gpu/xe/xe_wa:13: ./drivers/gpu/drm/xe/xe_wa.chMPubhdesc_sig_space)}(h h]h }(hj}hhhNhNubah}(h]h ]wah"]h$]h&]uh1j{hjehhhjzhMPubh desc_name)}(hxe_wa_process_oobh]h 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