sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/gpu/tegramodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/gpu/tegramodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/gpu/tegramodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/gpu/tegramodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/gpu/tegramodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/pt_BR/gpu/tegramodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/gpu/tegramodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h-drm/tegra NVIDIA Tegra GPU and display driverh]h-drm/tegra NVIDIA Tegra GPU and display driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh7/var/lib/git/docbuild/linux/Documentation/gpu/tegra.rsthKubh paragraph)}(hX+NVIDIA Tegra SoCs support a set of display, graphics and video functions via the host1x controller. host1x supplies command streams, gathered from a push buffer provided directly by the CPU, to its clients via channels. Software, or blocks amongst themselves, can use syncpoints for synchronization.h]hX+NVIDIA Tegra SoCs support a set of display, graphics and video functions via the host1x controller. host1x supplies command streams, gathered from a push buffer provided directly by the CPU, to its clients via channels. Software, or blocks amongst themselves, can use syncpoints for synchronization.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXUp until, but not including, Tegra124 (aka Tegra K1) the drm/tegra driver supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting with Tegra124 the GPU is based on the NVIDIA desktop GPU architecture and supported by the drm/nouveau driver.h]hXUp until, but not including, Tegra124 (aka Tegra K1) the drm/tegra driver supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting with Tegra124 the GPU is based on the NVIDIA desktop GPU architecture and supported by the drm/nouveau driver.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(h]The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It has three parts:h]h]The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It has three parts:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hXD- A host1x driver that provides infrastructure and access to the host1x services. - A KMS driver that supports the display controllers as well as a number of outputs, such as RGB, HDMI, DSI, and DisplayPort. - A set of custom userspace IOCTLs that can be used to submit jobs to the GPU and video engines via host1x. h]h bullet_list)}(hhh](h list_item)}(hPA host1x driver that provides infrastructure and access to the host1x services. h]h)}(hOA host1x driver that provides infrastructure and access to the host1x services.h]hOA host1x driver that provides infrastructure and access to the host1x services.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhhubj)}(h|A KMS driver that supports the display controllers as well as a number of outputs, such as RGB, HDMI, DSI, and DisplayPort. h]h)}(h{A KMS driver that supports the display controllers as well as a number of outputs, such as RGB, HDMI, DSI, and DisplayPort.h]h{A KMS driver that supports the display controllers as well as a number of outputs, such as RGB, HDMI, DSI, and DisplayPort.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhhubj)}(hjA set of custom userspace IOCTLs that can be used to submit jobs to the GPU and video engines via host1x. h]h)}(hiA set of custom userspace IOCTLs that can be used to submit jobs to the GPU and video engines via host1x.h]hiA set of custom userspace IOCTLs that can be used to submit jobs to the GPU and video engines via host1x.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj4ubah}(h]h ]h"]h$]h&]uh1jhhubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hDriver Infrastructureh]hDriver Infrastructure}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhKubh)}(hXDThe various host1x clients need to be bound together into a logical device in order to expose their functionality to users. The infrastructure that supports this is implemented in the host1x driver. When a driver is registered with the infrastructure it provides a list of compatible strings specifying the devices that it needs. The infrastructure creates a logical device and scan the device tree for matching device nodes, adding the required clients to a list. Drivers for individual clients register with the infrastructure as well and are added to the logical host1x device.h]hXDThe various host1x clients need to be bound together into a logical device in order to expose their functionality to users. The infrastructure that supports this is implemented in the host1x driver. When a driver is registered with the infrastructure it provides a list of compatible strings specifying the devices that it needs. The infrastructure creates a logical device and scan the device tree for matching device nodes, adding the required clients to a list. Drivers for individual clients register with the infrastructure as well and are added to the logical host1x device.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjZhhubh)}(hOnce all clients are available, the infrastructure will initialize the logical device using a driver-provided function which will set up the bits specific to the subsystem and in turn initialize each of its clients.h]hOnce all clients are available, the infrastructure will initialize the logical device using a driver-provided function which will set up the bits specific to the subsystem and in turn initialize each of its clients.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjZhhubh)}(hSimilarly, when one of the clients is unregistered, the infrastructure will destroy the logical device by calling back into the driver, which ensures that the subsystem specific bits are torn down and the clients destroyed in turn.h]hSimilarly, when one of the clients is unregistered, the infrastructure will destroy the logical device by calling back into the driver, which ensures that the subsystem specific bits are torn down and the clients destroyed in turn.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjZhhubh)}(hhh](h)}(hHost1x Infrastructure Referenceh]hHost1x Infrastructure Reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK0ubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlehost1x_bo_cache (C struct)c.host1x_bo_cachehNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(hhost1x_bo_cacheh]hdesc_signature_line)}(hstruct host1x_bo_cacheh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hhost1x_bo_cacheh]h desc_sig_name)}(hjh]hhost1x_bo_cache}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]j j  add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(hhost1x buffer object cacheh]hhost1x buffer object cache}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK%hj!hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](cstructeh"]h$]h&]domainj<objtypej=desctypej=noindex noindexentrynocontentsentryuh1jhhhjhNhNubh container)}(h**Definition**:: struct host1x_bo_cache { struct list_head mappings; struct mutex lock; }; **Members** ``mappings`` list of mappings ``lock`` synchronizes accesses to the list of mappingsh](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjMubh:}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK)hjIubh literal_block)}(hQstruct host1x_bo_cache { struct list_head mappings; struct mutex lock; };h]hQstruct host1x_bo_cache { struct list_head mappings; struct mutex lock; };}hjnsbah}(h]h ]h"]h$]h&]j j uh1jlhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK+hjIubh)}(h **Members**h]jR)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj}ubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK0hjIubhdefinition_list)}(hhh](hdefinition_list_item)}(h``mappings`` list of mappings h](hterm)}(h ``mappings``h]hliteral)}(hjh]hmappings}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK'hjubh definition)}(hhh]h)}(hlist of mappingsh]hlist of mappings}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK'hjubj)}(h6``lock`` synchronizes accesses to the list of mappingsh](j)}(h``lock``h]j)}(hjh]hlock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK'hjubj)}(hhh]h)}(h-synchronizes accesses to the list of mappingsh]h-synchronizes accesses to the list of mappings}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK'hjubeh}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubh)}(h**Description**h]jR)}(hj$h]h Description}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj"ubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK+hjhhubh)}(hXNote that entries are not periodically evicted from this cache and instead need to be explicitly released. This is used primarily for DRM/KMS where the cache's reference is released when the last reference to a buffer object represented by a mapping in this cache is dropped.h]hXNote that entries are not periodically evicted from this cache and instead need to be explicitly released. This is used primarily for DRM/KMS where the cache’s reference is released when the last reference to a buffer object represented by a mapping in this cache is dropped.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK(hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_client_ops (C struct)c.host1x_client_opshNtauh1jhjhhhNhNubj)}(hhh](j)}(hhost1x_client_opsh]j)}(hstruct host1x_client_opsh](j)}(hjh]hstruct}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK0ubj)}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhjohK0ubj)}(hhost1x_client_opsh]j)}(hj\h]hhost1x_client_ops}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj^hhhjohK0ubeh}(h]h ]h"]h$]h&]j j juh1jjjhjZhhhjohK0ubah}(h]jUah ](jjeh"]h$]h&]jj)jhuh1jhjohK0hjWhhubj )}(hhh]h)}(hhost1x client operationsh]hhost1x client operations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK@hjhhubah}(h]h ]h"]h$]h&]uh1jhjWhhhjohK0ubeh}(h]h ](j<structeh"]h$]h&]jAj<jBjjCjjDjEjFuh1jhhhjhNhNubjH)}(hX**Definition**:: struct host1x_client_ops { int (*early_init)(struct host1x_client *client); int (*init)(struct host1x_client *client); int (*exit)(struct host1x_client *client); int (*late_exit)(struct host1x_client *client); int (*suspend)(struct host1x_client *client); int (*resume)(struct host1x_client *client); }; **Members** ``early_init`` host1x client early initialization code ``init`` host1x client initialization code ``exit`` host1x client tear down code ``late_exit`` host1x client late tear down code ``suspend`` host1x client suspend code ``resume`` host1x client resume codeh](h)}(h**Definition**::h](jR)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKDhjubjm)}(hXGstruct host1x_client_ops { int (*early_init)(struct host1x_client *client); int (*init)(struct host1x_client *client); int (*exit)(struct host1x_client *client); int (*late_exit)(struct host1x_client *client); int (*suspend)(struct host1x_client *client); int (*resume)(struct host1x_client *client); };h]hXGstruct host1x_client_ops { int (*early_init)(struct host1x_client *client); int (*init)(struct host1x_client *client); int (*exit)(struct host1x_client *client); int (*late_exit)(struct host1x_client *client); int (*suspend)(struct host1x_client *client); int (*resume)(struct host1x_client *client); };}hjsbah}(h]h ]h"]h$]h&]j j uh1jlhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKFhjubh)}(h **Members**h]jR)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKOhjubj)}(hhh](j)}(h7``early_init`` host1x client early initialization code h](j)}(h``early_init``h]j)}(hjh]h early_init}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKBhj ubj)}(hhh]h)}(h'host1x client early initialization codeh]h'host1x client early initialization code}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKBhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj&hKBhjubj)}(h+``init`` host1x client initialization code h](j)}(h``init``h]j)}(hjJh]hinit}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKChjDubj)}(hhh]h)}(h!host1x client initialization codeh]h!host1x client initialization code}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKChj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhj_hKChjubj)}(h&``exit`` host1x client tear down code h](j)}(h``exit``h]j)}(hjh]hexit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKDhj}ubj)}(hhh]h)}(hhost1x client tear down codeh]hhost1x client tear down code}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKDhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhjhKDhjubj)}(h0``late_exit`` host1x client late tear down code h](j)}(h ``late_exit``h]j)}(hjh]h late_exit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKEhjubj)}(hhh]h)}(h!host1x client late tear down codeh]h!host1x client late tear down code}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKEhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKEhjubj)}(h'``suspend`` host1x client suspend code h](j)}(h ``suspend``h]j)}(hjh]hsuspend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKFhjubj)}(hhh]h)}(hhost1x client suspend codeh]hhost1x client suspend code}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKFhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hKFhjubj)}(h$``resume`` host1x client resume codeh](j)}(h ``resume``h]j)}(hj.h]hresume}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKFhj(ubj)}(hhh]h)}(hhost1x client resume codeh]hhost1x client resume code}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKGhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjChKFhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_client (C struct)c.host1x_clienthNtauh1jhjhhhNhNubj)}(hhh](j)}(h host1x_clienth]j)}(hstruct host1x_clienth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKMubj)}(h host1x_clienth]j)}(hjh]h host1x_client}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]j j uh1jhjhhhjhKMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjhhhjhKMubah}(h]j{ah ](jjeh"]h$]h&]jj)jhuh1jhjhKMhj}hhubj )}(hhh]h)}(hhost1x client structureh]hhost1x client structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKRhjhhubah}(h]h ]h"]h$]h&]uh1jhj}hhhjhKMubeh}(h]h ](j<structeh"]h$]h&]jAj<jBjjCjjDjEjFuh1jhhhjhNhNubjH)}(hX**Definition**:: struct host1x_client { struct list_head list; struct device *host; struct device *dev; struct iommu_group *group; const struct host1x_client_ops *ops; enum host1x_class class; struct host1x_channel *channel; struct host1x_syncpt **syncpts; unsigned int num_syncpts; struct host1x_client *parent; unsigned int usecount; struct mutex lock; struct host1x_bo_cache cache; }; **Members** ``list`` list node for the host1x client ``host`` pointer to struct device representing the host1x controller ``dev`` pointer to struct device backing this host1x client ``group`` IOMMU group that this client is a member of ``ops`` host1x client operations ``class`` host1x class represented by this client ``channel`` host1x channel associated with this client ``syncpts`` array of syncpoints requested for this client ``num_syncpts`` number of syncpoints requested for this client ``parent`` pointer to parent structure ``usecount`` reference count for this structure ``lock`` mutex for mutually exclusive concurrency ``cache`` host1x buffer object cacheh](h)}(h**Definition**::h](jR)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKVhjubjm)}(hXstruct host1x_client { struct list_head list; struct device *host; struct device *dev; struct iommu_group *group; const struct host1x_client_ops *ops; enum host1x_class class; struct host1x_channel *channel; struct host1x_syncpt **syncpts; unsigned int num_syncpts; struct host1x_client *parent; unsigned int usecount; struct mutex lock; struct host1x_bo_cache cache; };h]hXstruct host1x_client { struct list_head list; struct device *host; struct device *dev; struct iommu_group *group; const struct host1x_client_ops *ops; enum host1x_class class; struct host1x_channel *channel; struct host1x_syncpt **syncpts; unsigned int num_syncpts; struct host1x_client *parent; unsigned int usecount; struct mutex lock; struct host1x_bo_cache cache; };}hjsbah}(h]h ]h"]h$]h&]j j uh1jlhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKXhjubh)}(h **Members**h]jR)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKhhjubj)}(hhh](j)}(h)``list`` list node for the host1x client h](j)}(h``list``h]j)}(hj7h]hlist}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKThj1ubj)}(hhh]h)}(hlist node for the host1x clienth]hlist node for the host1x client}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhKThjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhKThj.ubj)}(hE``host`` pointer to struct device representing the host1x controller h](j)}(h``host``h]j)}(hjph]hhost}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKUhjjubj)}(hhh]h)}(h;pointer to struct device representing the host1x controllerh]h;pointer to struct device representing the host1x controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKUhjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjhKUhj.ubj)}(h<``dev`` pointer to struct device backing this host1x client h](j)}(h``dev``h]j)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKVhjubj)}(hhh]h)}(h3pointer to struct device backing this host1x clienth]h3pointer to struct device backing this host1x client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKVhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKVhj.ubj)}(h6``group`` IOMMU group that this client is a member of h](j)}(h ``group``h]j)}(hjh]hgroup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKWhjubj)}(hhh]h)}(h+IOMMU group that this client is a member ofh]h+IOMMU group that this client is a member of}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKWhj.ubj)}(h!``ops`` host1x client operations h](j)}(h``ops``h]j)}(hjh]hops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKXhjubj)}(hhh]h)}(hhost1x client operationsh]hhost1x client operations}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hKXhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj0hKXhj.ubj)}(h2``class`` host1x class represented by this client h](j)}(h ``class``h]j)}(hjTh]hclass}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKYhjNubj)}(hhh]h)}(h'host1x class represented by this clienth]h'host1x class represented by this client}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKYhjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjihKYhj.ubj)}(h7``channel`` host1x channel associated with this client h](j)}(h ``channel``h]j)}(hjh]hchannel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKZhjubj)}(hhh]h)}(h*host1x channel associated with this clienth]h*host1x channel associated with this client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKZhj.ubj)}(h:``syncpts`` array of syncpoints requested for this client h](j)}(h ``syncpts``h]j)}(hjh]hsyncpts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK[hjubj)}(hhh]h)}(h-array of syncpoints requested for this clienth]h-array of syncpoints requested for this client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK[hj.ubj)}(h?``num_syncpts`` number of syncpoints requested for this client h](j)}(h``num_syncpts``h]j)}(hjh]h num_syncpts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK\hjubj)}(hhh]h)}(h.number of syncpoints requested for this clienth]h.number of syncpoints requested for this client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK\hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK\hj.ubj)}(h'``parent`` pointer to parent structure h](j)}(h ``parent``h]j)}(hj8h]hparent}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK]hj2ubj)}(hhh]h)}(hpointer to parent structureh]hpointer to parent structure}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhK]hjNubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhjMhK]hj.ubj)}(h0``usecount`` reference count for this structure h](j)}(h ``usecount``h]j)}(hjqh]husecount}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK^hjkubj)}(hhh]h)}(h"reference count for this structureh]h"reference count for this structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK^hjubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jhjhK^hj.ubj)}(h2``lock`` mutex for mutually exclusive concurrency h](j)}(h``lock``h]j)}(hjh]hlock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK_hjubj)}(hhh]h)}(h(mutex for mutually exclusive concurrencyh]h(mutex for mutually exclusive concurrency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK_hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK_hj.ubj)}(h$``cache`` host1x buffer object cacheh](j)}(h ``cache``h]j)}(hjh]hcache}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK_hjubj)}(hhh]h)}(hhost1x buffer object cacheh]hhost1x buffer object cache}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhK`hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK_hj.ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_bo_ops (C struct)c.host1x_bo_opshNtauh1jhjhhhNhNubj)}(hhh](j)}(h host1x_bo_opsh]j)}(hstruct host1x_bo_opsh](j)}(hjh]hstruct}(hj= hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9 hhhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKfubj)}(h h]h }(hjK hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9 hhhjJ hKfubj)}(h host1x_bo_opsh]j)}(hj7 h]h host1x_bo_ops}(hj] hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjY ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj9 hhhjJ hKfubeh}(h]h ]h"]h$]h&]j j juh1jjjhj5 hhhjJ hKfubah}(h]j0 ah ](jjeh"]h$]h&]jj)jhuh1jhjJ hKfhj2 hhubj )}(hhh]h)}(h.operations implemented by a host1x_bo providerh]h.operations implemented by a host1x_bo provider}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKhj| hhubah}(h]h ]h"]h$]h&]uh1jhj2 hhhjJ hKfubeh}(h]h ](j<structeh"]h$]h&]jAj<jBj jCj jDjEjFuh1jhhhjhNhNubjH)}(hXH**Definition**:: struct host1x_bo_ops { struct host1x_bo *(*get)(struct host1x_bo *bo); void (*put)(struct host1x_bo *bo); struct host1x_bo_mapping *(*pin)(struct device *dev, struct host1x_bo *bo, enum dma_data_direction dir); void (*unpin)(struct host1x_bo_mapping *map); void *(*mmap)(struct host1x_bo *bo); void (*munmap)(struct host1x_bo *bo, void *addr); }; **Members** ``pin`` create a DMA mapping. Implementation must not touch the bo's refcount. ``unpin`` destroy a DMA mapping. Implementation must not touch the bo's refcount.h](h)}(h**Definition**::h](jR)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKhj ubjm)}(hXrstruct host1x_bo_ops { struct host1x_bo *(*get)(struct host1x_bo *bo); void (*put)(struct host1x_bo *bo); struct host1x_bo_mapping *(*pin)(struct device *dev, struct host1x_bo *bo, enum dma_data_direction dir); void (*unpin)(struct host1x_bo_mapping *map); void *(*mmap)(struct host1x_bo *bo); void (*munmap)(struct host1x_bo *bo, void *addr); };h]hXrstruct host1x_bo_ops { struct host1x_bo *(*get)(struct host1x_bo *bo); void (*put)(struct host1x_bo *bo); struct host1x_bo_mapping *(*pin)(struct device *dev, struct host1x_bo *bo, enum dma_data_direction dir); void (*unpin)(struct host1x_bo_mapping *map); void *(*mmap)(struct host1x_bo *bo); void (*munmap)(struct host1x_bo *bo, void *addr); };}hj sbah}(h]h ]h"]h$]h&]j j uh1jlhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKhj ubh)}(h **Members**h]jR)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj ubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKhj ubj)}(hhh](j)}(hO``pin`` create a DMA mapping. Implementation must not touch the bo's refcount. h](j)}(h``pin``h]j)}(hj h]hpin}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKhj ubj)}(hhh]h)}(hFcreate a DMA mapping. Implementation must not touch the bo's refcount.h]hHcreate a DMA mapping. Implementation must not touch the bo’s refcount.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(hQ``unpin`` destroy a DMA mapping. Implementation must not touch the bo's refcount.h](j)}(h ``unpin``h]j)}(hj% h]hunpin}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj# ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKhj ubj)}(hhh]h)}(hGdestroy a DMA mapping. Implementation must not touch the bo's refcount.h]hIdestroy a DMA mapping. Implementation must not touch the bo’s refcount.}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKhj; ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj: hKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_driver (C struct)c.host1x_driverhNtauh1jhjhhhNhNubj)}(hhh](j)}(h host1x_driverh]j)}(hstruct host1x_driverh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ hhhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ hhhj hKubj)}(h host1x_driverh]j)}(hjy h]h host1x_driver}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj{ hhhj hKubeh}(h]h ]h"]h$]h&]j j juh1jjjhjw hhhj hKubah}(h]jr ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhjt hhubj )}(hhh]h)}(hhost1x logical device driverh]hhost1x logical device driver}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhMwhj hhubah}(h]h ]h"]h$]h&]uh1jhjt hhhj hKubeh}(h]h ](j<structeh"]h$]h&]jAj<jBj jCj jDjEjFuh1jhhhjhNhNubjH)}(hX**Definition**:: struct host1x_driver { struct device_driver driver; const struct of_device_id *subdevs; struct list_head list; int (*probe)(struct host1x_device *device); void (*remove)(struct host1x_device *device); void (*shutdown)(struct host1x_device *device); }; **Members** ``driver`` core driver ``subdevs`` table of OF device IDs matching subdevices for this driver ``list`` list node for the driver ``probe`` called when the host1x logical device is probed ``remove`` called when the host1x logical device is removed ``shutdown`` called when the host1x logical device is shut downh](h)}(h**Definition**::h](jR)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhM{hj ubjm)}(hXstruct host1x_driver { struct device_driver driver; const struct of_device_id *subdevs; struct list_head list; int (*probe)(struct host1x_device *device); void (*remove)(struct host1x_device *device); void (*shutdown)(struct host1x_device *device); };h]hXstruct host1x_driver { struct device_driver driver; const struct of_device_id *subdevs; struct list_head list; int (*probe)(struct host1x_device *device); void (*remove)(struct host1x_device *device); void (*shutdown)(struct host1x_device *device); };}hj sbah}(h]h ]h"]h$]h&]j j uh1jlhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhM}hj ubh)}(h **Members**h]jR)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj ubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhMhj ubj)}(hhh](j)}(h``driver`` core driver h](j)}(h ``driver``h]j)}(hj. h]hdriver}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj, ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhMyhj( ubj)}(hhh]h)}(h core driverh]h core driver}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC hMyhjD ubah}(h]h ]h"]h$]h&]uh1jhj( ubeh}(h]h ]h"]h$]h&]uh1jhjC hMyhj% ubj)}(hG``subdevs`` table of OF device IDs matching subdevices for this driver h](j)}(h ``subdevs``h]j)}(hjg h]hsubdevs}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhMzhja ubj)}(hhh]h)}(h:table of OF device IDs matching subdevices for this driverh]h:table of OF device IDs matching subdevices for this driver}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj| hMzhj} ubah}(h]h ]h"]h$]h&]uh1jhja ubeh}(h]h ]h"]h$]h&]uh1jhj| hMzhj% ubj)}(h"``list`` list node for the driver h](j)}(h``list``h]j)}(hj h]hlist}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhM{hj ubj)}(hhh]h)}(hlist node for the driverh]hlist node for the driver}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM{hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hM{hj% ubj)}(h:``probe`` called when the host1x logical device is probed h](j)}(h ``probe``h]j)}(hj h]hprobe}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhM|hj ubj)}(hhh]h)}(h/called when the host1x logical device is probedh]h/called when the host1x logical device is probed}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM|hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hM|hj% ubj)}(h<``remove`` called when the host1x logical device is removed h](j)}(h ``remove``h]j)}(hj h]hremove}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhM}hj ubj)}(hhh]h)}(h0called when the host1x logical device is removedh]h0called when the host1x logical device is removed}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj' hM}hj( ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj' hM}hj% ubj)}(h?``shutdown`` called when the host1x logical device is shut downh](j)}(h ``shutdown``h]j)}(hjK h]hshutdown}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI ubah}(h]h ]h"]h$]h&]uh1jhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhM}hjE ubj)}(hhh]h)}(h2called when the host1x logical device is shut downh]h2called when the host1x logical device is shut down}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1hhP/var/lib/git/docbuild/linux/Documentation/gpu/tegra:50: ./include/linux/host1x.hhM~hja ubah}(h]h ]h"]h$]h&]uh1jhjE ubeh}(h]h ]h"]h$]h&]uh1jhj` hM}hj% ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_device_init (C function)c.host1x_device_inithNtauh1jhjhhhNhNubj)}(hhh](j)}(h5int host1x_device_init (struct host1x_device *device)h]j)}(h4int host1x_device_init(struct host1x_device *device)h](hdesc_sig_keyword_type)}(hinth]hint}(hj hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j hj hhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hhost1x_device_inith]j)}(hhost1x_device_inith]hhost1x_device_init}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj hhhj hKubhdesc_parameterlist)}(h(struct host1x_device *device)h]hdesc_parameter)}(hstruct host1x_device *deviceh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h host1x_deviceh]h host1x_device}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj<reftype identifier reftargetj modnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j" ASTIdentifier)}j j sbc.host1x_device_initasbuh1hhj ubj)}(h h]h }(hj/ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubhdesc_sig_punctuation)}(h*h]h*}(hj? hhhNhNubah}(h]h ]pah"]h$]h&]uh1j= hj ubj)}(hdeviceh]hdevice}(hjN hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj ubah}(h]h ]h"]h$]h&]j j uh1j hj hhhj hKubeh}(h]h ]h"]h$]h&]j j juh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj )}(hhh]h)}(h"initialize a host1x logical deviceh]h"initialize a host1x logical device}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhju hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj jCj jDjEjFuh1jhhhjhNhNubjH)}(hX**Parameters** ``struct host1x_device *device`` host1x logical device **Description** The driver for the host1x logical device can call this during execution of its :c:type:`host1x_driver.probe ` implementation to initialize each of its clients. The client drivers access the subsystem specific driver data using the :c:type:`host1x_client.parent ` field and driver data associated with it (usually by calling dev_get_drvdata()).h](h)}(h**Parameters**h]jR)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj ubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhj ubj)}(hhh]j)}(h7``struct host1x_device *device`` host1x logical device h](j)}(h ``struct host1x_device *device``h]j)}(hj h]hstruct host1x_device *device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhj ubj)}(hhh]h)}(hhost1x logical deviceh]hhost1x logical device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]jR)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj ubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhj ubh)}(hXuThe driver for the host1x logical device can call this during execution of its :c:type:`host1x_driver.probe ` implementation to initialize each of its clients. The client drivers access the subsystem specific driver data using the :c:type:`host1x_client.parent ` field and driver data associated with it (usually by calling dev_get_drvdata()).h](hOThe driver for the host1x logical device can call this during execution of its }(hj hhhNhNubh)}(h-:c:type:`host1x_driver.probe `h]j)}(hjh]hhost1x_driver.probe}(hjhhhNhNubah}(h]h ](xrefj<c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc gpu/tegra refdomainj<reftypetype refexplicitrefwarnj! j$ )}j' ]sb reftarget host1x_driveruh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhj ubhz implementation to initialize each of its clients. The client drivers access the subsystem specific driver data using the }(hj hhhNhNubh)}(h.:c:type:`host1x_client.parent `h]j)}(hj>h]hhost1x_client.parent}(hj@hhhNhNubah}(h]h ](j j<c-typeeh"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]refdocj, refdomainj<reftypetype refexplicitrefwarnj! j2j5 host1x_clientuh1hhj7hKhj ubhQ field and driver data associated with it (usually by calling dev_get_drvdata()).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj7hKhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_device_exit (C function)c.host1x_device_exithNtauh1jhjhhhNhNubj)}(hhh](j)}(h5int host1x_device_exit (struct host1x_device *device)h]j)}(h4int host1x_device_exit(struct host1x_device *device)h](j )}(hinth]hint}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hhost1x_device_exith]j)}(hhost1x_device_exith]hhost1x_device_exit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]j j uh1jhjhhhjhKubj )}(h(struct host1x_device *device)h]j )}(hstruct host1x_device *deviceh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h host1x_deviceh]h host1x_device}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]j* )}j jsbc.host1x_device_exitasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj> )}(hjA h]h*}(hjhhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubah}(h]h ]h"]h$]h&]j j uh1j hjhhhjhKubeh}(h]h ]h"]h$]h&]j j juh1jjjhj}hhhjhKubah}(h]jxah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjzhhubj )}(hhh]h)}(h"uninitialize host1x logical deviceh]h"uninitialize host1x logical device}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhjBhhubah}(h]h ]h"]h$]h&]uh1jhjzhhhjhKubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj]jCj]jDjEjFuh1jhhhjhNhNubjH)}(hXH**Parameters** ``struct host1x_device *device`` host1x logical device **Description** When the driver for a host1x logical device is unloaded, it can call this function to tear down each of its clients. Typically this is done after a subsystem-specific data structure is removed and the functionality can no longer be used.h](h)}(h**Parameters**h]jR)}(hjgh]h Parameters}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjeubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhjaubj)}(hhh]j)}(h7``struct host1x_device *device`` host1x logical device h](j)}(h ``struct host1x_device *device``h]j)}(hjh]hstruct host1x_device *device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhjubj)}(hhh]h)}(hhost1x logical deviceh]hhost1x logical device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj}ubah}(h]h ]h"]h$]h&]uh1jhjaubh)}(h**Description**h]jR)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhjaubh)}(hWhen the driver for a host1x logical device is unloaded, it can call this function to tear down each of its clients. Typically this is done after a subsystem-specific data structure is removed and the functionality can no longer be used.h]hWhen the driver for a host1x logical device is unloaded, it can call this function to tear down each of its clients. Typically this is done after a subsystem-specific data structure is removed and the functionality can no longer be used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chKhjaubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(host1x_driver_register_full (C function)c.host1x_driver_register_fullhNtauh1jhjhhhNhNubj)}(hhh](j)}(hTint host1x_driver_register_full (struct host1x_driver *driver, struct module *owner)h]j)}(hSint host1x_driver_register_full(struct host1x_driver *driver, struct module *owner)h](j )}(hinth]hint}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hhost1x_driver_register_fullh]j)}(hhost1x_driver_register_fullh]hhost1x_driver_register_full}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ](jjeh"]h$]h&]j j uh1jhjhhhjhMubj )}(h4(struct host1x_driver *driver, struct module *owner)h](j )}(hstruct host1x_driver *driverh](j)}(hjh]hstruct}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubh)}(hhh]j)}(h host1x_driverh]h host1x_driver}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjcmodnameN classnameNj! j$ )}j' ]j* )}j j)sbc.host1x_driver_register_fullasbuh1hhj?ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj> )}(hjA h]h*}(hjhhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj?ubj)}(hdriverh]hdriver}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj;ubj )}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]j}c.host1x_driver_register_fullasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj> )}(hjA h]h*}(hjhhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hownerh]howner}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj;ubeh}(h]h ]h"]h$]h&]j j uh1j hjhhhjhMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj )}(hhh]h)}(hregister a host1x driverh]hregister a host1x driver}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj3hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjNjCjNjDjEjFuh1jhhhjhNhNubjH)}(hX**Parameters** ``struct host1x_driver *driver`` host1x driver ``struct module *owner`` owner module **Description** Drivers for host1x logical devices call this function to register a driver with the infrastructure. Note that since these drive logical devices, the registration of the driver actually triggers tho logical device creation. A logical device will be created for each host1x instance.h](h)}(h**Parameters**h]jR)}(hjXh]h Parameters}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjVubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjRubj)}(hhh](j)}(h/``struct host1x_driver *driver`` host1x driver h](j)}(h ``struct host1x_driver *driver``h]j)}(hjwh]hstruct host1x_driver *driver}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjqubj)}(hhh]h)}(h host1x driverh]h host1x driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhjhMhjnubj)}(h&``struct module *owner`` owner module h](j)}(h``struct module *owner``h]j)}(hjh]hstruct module *owner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh]h)}(h owner moduleh]h owner module}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjnubeh}(h]h ]h"]h$]h&]uh1jhjRubh)}(h**Description**h]jR)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjRubh)}(hXDrivers for host1x logical devices call this function to register a driver with the infrastructure. Note that since these drive logical devices, the registration of the driver actually triggers tho logical device creation. A logical device will be created for each host1x instance.h]hXDrivers for host1x logical devices call this function to register a driver with the infrastructure. Note that since these drive logical devices, the registration of the driver actually triggers tho logical device creation. A logical device will be created for each host1x instance.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjRubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%host1x_driver_unregister (C function)c.host1x_driver_unregisterhNtauh1jhjhhhNhNubj)}(hhh](j)}(hhMubj)}(hhost1x_driver_unregisterh]j)}(hhost1x_driver_unregisterh]hhost1x_driver_unregister}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubah}(h]h ](jjeh"]h$]h&]j j uh1jhj,hhhj>hMubj )}(h(struct host1x_driver *driver)h]j )}(hstruct host1x_driver *driverh](j)}(hjh]hstruct}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubj)}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubh)}(hhh]j)}(h host1x_driverh]h host1x_driver}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]j* )}j jSsbc.host1x_driver_unregisterasbuh1hhjiubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubj> )}(hjA h]h*}(hjhhhNhNubahN}(h]h ]jJ ah"]h$]h&]uh1j= hjiubj)}(hdriverh]hdriver}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjeubah}(h]h ]h"]h$]h&]j j uh1j hj,hhhj>hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhj(hhhj>hMubah}(h]j#ah ](jjeh"]h$]h&]jj)jhuh1jhj>hMhj%hhubj )}(hhh]h)}(hunregister a host1x driverh]hunregister a host1x driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj%hhhj>hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjjCjjDjEjFuh1jhhhjhNhNubjH)}(h**Parameters** ``struct host1x_driver *driver`` host1x driver **Description** Unbinds the driver from each of the host1x logical devices that it is bound to, effectively removing the subsystem devices that they represent.h](h)}(h**Parameters**h]jR)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj ubj)}(hhh]j)}(h/``struct host1x_driver *driver`` host1x driver h](j)}(h ``struct host1x_driver *driver``h]j)}(hj1h]hstruct host1x_driver *driver}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj+ubj)}(hhh]h)}(h host1x driverh]h host1x driver}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhMhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjFhMhj(ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]jR)}(hjlh]h Description}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj ubh)}(hUnbinds the driver from each of the host1x logical devices that it is bound to, effectively removing the subsystem devices that they represent.h]hUnbinds the driver from each of the host1x logical devices that it is bound to, effectively removing the subsystem devices that they represent.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!__host1x_client_init (C function)c.__host1x_client_inithNtauh1jhjhhhNhNubj)}(hhh](j)}(hTvoid __host1x_client_init (struct host1x_client *client, struct lock_class_key *key)h]j)}(hSvoid __host1x_client_init(struct host1x_client *client, struct lock_class_key *key)h](j )}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(h__host1x_client_inith]j)}(h__host1x_client_inith]h__host1x_client_init}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]j j uh1jhjhhhjhMubj )}(h:(struct host1x_client *client, struct lock_class_key *key)h](j )}(hstruct host1x_client *clienth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h host1x_clienth]h host1x_client}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]j* )}j jsbc.__host1x_client_initasbuh1hhjubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj> )}(hjA h]h*}(hj:hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hclienth]hclient}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubj )}(hstruct lock_class_key *keyh](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj)}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubh)}(hhh]j)}(hlock_class_keyh]hlock_class_key}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]j(c.__host1x_client_initasbuh1hhj\ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj> )}(hjA h]h*}(hjhhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj\ubj)}(hkeyh]hkey}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubeh}(h]h ]h"]h$]h&]j j uh1j hjhhhjhMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj )}(hhh]h)}(hinitialize a host1x clienth]hinitialize a host1x client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjjCjjDjEjFuh1jhhhjhNhNubjH)}(h**Parameters** ``struct host1x_client *client`` host1x client ``struct lock_class_key *key`` lock class key for the client-specific mutexh](h)}(h**Parameters**h]jR)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh](j)}(h/``struct host1x_client *client`` host1x client h](j)}(h ``struct host1x_client *client``h]j)}(hj"h]hstruct host1x_client *client}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh]h)}(h host1x clienth]h host1x client}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj7hMhjubj)}(hK``struct lock_class_key *key`` lock class key for the client-specific mutexh](j)}(h``struct lock_class_key *key``h]j)}(hj[h]hstruct lock_class_key *key}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjUubj)}(hhh]h)}(h,lock class key for the client-specific mutexh]h,lock class key for the client-specific mutex}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjphMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_client_exit (C function)c.host1x_client_exithNtauh1jhjhhhNhNubj)}(hhh](j)}(h6void host1x_client_exit (struct host1x_client *client)h]j)}(h5void host1x_client_exit(struct host1x_client *client)h](j )}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hhost1x_client_exith]j)}(hhost1x_client_exith]hhost1x_client_exit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]j j uh1jhjhhhjhMubj )}(h(struct host1x_client *client)h]j )}(hstruct host1x_client *clienth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h host1x_clienth]h host1x_client}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]j* )}j jsbc.host1x_client_exitasbuh1hhjubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj> )}(hjA h]h*}(hj>hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hclienth]hclient}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubah}(h]h ]h"]h$]h&]j j uh1j hjhhhjhMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj )}(hhh]h)}(huninitialize a host1x clienth]huninitialize a host1x client}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjrhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjjCjjDjEjFuh1jhhhjhNhNubjH)}(h@**Parameters** ``struct host1x_client *client`` host1x clienth](h)}(h**Parameters**h]jR)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh]j)}(h.``struct host1x_client *client`` host1x clienth](j)}(h ``struct host1x_client *client``h]j)}(hjh]hstruct host1x_client *client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh]h)}(h host1x clienth]h host1x client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%__host1x_client_register (C function)c.__host1x_client_registerhNtauh1jhjhhhNhNubj)}(hhh](j)}(h;int __host1x_client_register (struct host1x_client *client)h]j)}(h:int __host1x_client_register(struct host1x_client *client)h](j )}(hinth]hint}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj hhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhjhMubj)}(h__host1x_client_registerh]j)}(h__host1x_client_registerh]h__host1x_client_register}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj hhhjhMubj )}(h(struct host1x_client *client)h]j )}(hstruct host1x_client *clienth](j)}(hjh]hstruct}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubh)}(hhh]j)}(h host1x_clienth]h host1x_client}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmmodnameN classnameNj! j$ )}j' ]j* )}j j3sbc.__host1x_client_registerasbuh1hhjIubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj> )}(hjA h]h*}(hjhhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjIubj)}(hclienth]hclient}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjEubah}(h]h ]h"]h$]h&]j j uh1j hj hhhjhMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj )}(hhh]h)}(hregister a host1x clienth]hregister a host1x client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjjCjjDjEjFuh1jhhhjhNhNubjH)}(hX**Parameters** ``struct host1x_client *client`` host1x client **Description** Registers a host1x client with each host1x controller instance. Note that each client will only match their parent host1x controller and will only be associated with that instance. Once all clients have been registered with their parent host1x controller, the infrastructure will set up the logical device and call host1x_device_init(), which will in turn call each client's :c:type:`host1x_client_ops.init ` implementation.h](h)}(h**Parameters**h]jR)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh]j)}(h/``struct host1x_client *client`` host1x client h](j)}(h ``struct host1x_client *client``h]j)}(hjh]hstruct host1x_client *client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj ubj)}(hhh]h)}(h host1x clienth]h host1x client}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hMhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj&hMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jR)}(hjLh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjJubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubh)}(hXRegisters a host1x client with each host1x controller instance. Note that each client will only match their parent host1x controller and will only be associated with that instance. Once all clients have been registered with their parent host1x controller, the infrastructure will set up the logical device and call host1x_device_init(), which will in turn call each client's :c:type:`host1x_client_ops.init ` implementation.h](hXyRegisters a host1x client with each host1x controller instance. Note that each client will only match their parent host1x controller and will only be associated with that instance. Once all clients have been registered with their parent host1x controller, the infrastructure will set up the logical device and call host1x_device_init(), which will in turn call each client’s }(hjbhhhNhNubh)}(h4:c:type:`host1x_client_ops.init `h]j)}(hjlh]hhost1x_client_ops.init}(hjnhhhNhNubah}(h]h ](j j<c-typeeh"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]refdocj, refdomainj<reftypetype refexplicitrefwarnj! j2j5host1x_client_opsuh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjbubh implementation.}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%host1x_client_unregister (C function)c.host1x_client_unregisterhNtauh1jhjhhhNhNubj)}(hhh](j)}(h )}(hjA h]h*}(hj=hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hclienth]hclient}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubah}(h]h ]h"]h$]h&]j j uh1j hjhhhjhM ubeh}(h]h ]h"]h$]h&]j j juh1jjjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM hjhhubj )}(hhh]h)}(hunregister a host1x clienth]hunregister a host1x client}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chM hjqhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjjCjjDjEjFuh1jhhhjhNhNubjH)}(h**Parameters** ``struct host1x_client *client`` host1x client **Description** Removes a host1x client from its host1x controller instance. If a logical device has already been initialized, it will be torn down.h](h)}(h**Parameters**h]jR)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh]j)}(h/``struct host1x_client *client`` host1x client h](j)}(h ``struct host1x_client *client``h]j)}(hjh]hstruct host1x_client *client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh]h)}(h host1x clienth]h host1x client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jR)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubh)}(hRemoves a host1x client from its host1x controller instance. If a logical device has already been initialized, it will be torn down.h]hRemoves a host1x client from its host1x controller instance. If a logical device has already been initialized, it will be torn down.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_bo_pin (C function)c.host1x_bo_pinhNtauh1jhjhhhNhNubj)}(hhh](j)}(hstruct host1x_bo_mapping * host1x_bo_pin (struct device *dev, struct host1x_bo *bo, enum dma_data_direction dir, struct host1x_bo_cache *cache)h]j)}(hstruct host1x_bo_mapping *host1x_bo_pin(struct device *dev, struct host1x_bo *bo, enum dma_data_direction dir, struct host1x_bo_cache *cache)h](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chM{ubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhjBhM{ubh)}(hhh]j)}(hhost1x_bo_mappingh]hhost1x_bo_mapping}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjVmodnameN classnameNj! j$ )}j' ]j* )}j host1x_bo_pinsbc.host1x_bo_pinasbuh1hhj1hhhjBhM{ubj)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhjBhM{ubj> )}(hjA h]h*}(hjhhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj1hhhjBhM{ubj)}(h host1x_bo_pinh]j)}(hjrh]h host1x_bo_pin}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]j j uh1jhj1hhhjBhM{ubj )}(hf(struct device *dev, struct host1x_bo *bo, enum dma_data_direction dir, struct host1x_bo_cache *cache)h](j )}(hstruct device *devh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]jpc.host1x_bo_pinasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj> )}(hjA h]h*}(hjhhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hdevh]hdev}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubj )}(hstruct host1x_bo *boh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h host1x_boh]h host1x_bo}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj?modnameN classnameNj! j$ )}j' ]jpc.host1x_bo_pinasbuh1hhjubj)}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj> )}(hjA h]h*}(hjihhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hboh]hbo}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubj )}(henum dma_data_direction dirh](j)}(henumh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdma_data_directionh]hdma_data_direction}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]jpc.host1x_bo_pinasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdirh]hdir}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubj )}(hstruct host1x_bo_cache *cacheh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hhost1x_bo_cacheh]hhost1x_bo_cache}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]jpc.host1x_bo_pinasbuh1hhjubj)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj> )}(hjA h]h*}(hj=hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hcacheh]hcache}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjubeh}(h]h ]h"]h$]h&]j j uh1j hj1hhhjBhM{ubeh}(h]h ]h"]h$]h&]j j juh1jjjhj-hhhjBhM{ubah}(h]j(ah ](jjeh"]h$]h&]jj)jhuh1jhjBhM{hj*hhubj )}(hhh]h)}(h*Create a DMA mapping for the buffer objecth]h*Create a DMA mapping for the buffer object}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chM{hjqhhubah}(h]h ]h"]h$]h&]uh1jhj*hhhjBhM{ubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjjCjjDjEjFuh1jhhhjhNhNubjH)}(hXr**Parameters** ``struct device *dev`` Device onto which DMA map to ``struct host1x_bo *bo`` Buffer object to map ``enum dma_data_direction dir`` DMA direction ``struct host1x_bo_cache *cache`` Cache in which to store mapping, or NULL **Description** Creates a DMA mapping pointing to **bo** for **dev**. The refcount of **bo** is incremented until host1x_bo_unpin is called. If **cache** is specified, the mapping is also stored in the cache and not released until **bo** is freed (refcount drops to zero). This improves performance when a buffer is pinned and unpinned frequently as in the case of display use.h](h)}(h**Parameters**h]jR)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubj)}(hhh](j)}(h4``struct device *dev`` Device onto which DMA map to h](j)}(h``struct device *dev``h]j)}(hjh]hstruct device *dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chM|hjubj)}(hhh]h)}(hDevice onto which DMA map toh]hDevice onto which DMA map to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM|hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM|hjubj)}(h.``struct host1x_bo *bo`` Buffer object to map h](j)}(h``struct host1x_bo *bo``h]j)}(hjh]hstruct host1x_bo *bo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chM}hjubj)}(hhh]h)}(hBuffer object to maph]hBuffer object to map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM}hjubj)}(h.``enum dma_data_direction dir`` DMA direction h](j)}(h``enum dma_data_direction dir``h]j)}(hj'h]henum dma_data_direction dir}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chM~hj!ubj)}(hhh]h)}(h DMA directionh]h DMA direction}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM~hj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj<hM~hjubj)}(hK``struct host1x_bo_cache *cache`` Cache in which to store mapping, or NULL h](j)}(h!``struct host1x_bo_cache *cache``h]j)}(hj`h]hstruct host1x_bo_cache *cache}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjZubj)}(hhh]h)}(h(Cache in which to store mapping, or NULLh]h(Cache in which to store mapping, or NULL}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjuhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jR)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubh)}(h|Creates a DMA mapping pointing to **bo** for **dev**. The refcount of **bo** is incremented until host1x_bo_unpin is called.h](h"Creates a DMA mapping pointing to }(hjhhhNhNubjR)}(h**bo**h]hbo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubh for }(hjhhhNhNubjR)}(h**dev**h]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubh. The refcount of }(hjhhhNhNubjR)}(h**bo**h]hbo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubh0 is incremented until host1x_bo_unpin is called.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubh)}(hIf **cache** is specified, the mapping is also stored in the cache and not released until **bo** is freed (refcount drops to zero). This improves performance when a buffer is pinned and unpinned frequently as in the case of display use.h](hIf }(hjhhhNhNubjR)}(h **cache**h]hcache}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubhN is specified, the mapping is also stored in the cache and not released until }(hjhhhNhNubjR)}(h**bo**h]hbo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubh is freed (refcount drops to zero). This improves performance when a buffer is pinned and unpinned frequently as in the case of display use.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_bo_unpin (C function)c.host1x_bo_unpinhNtauh1jhjhhhNhNubj)}(hhh](j)}(h8void host1x_bo_unpin (struct host1x_bo_mapping *mapping)h]j)}(h7void host1x_bo_unpin(struct host1x_bo_mapping *mapping)h](j )}(hvoidh]hvoid}(hjIhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjEhhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMubj)}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEhhhjWhMubj)}(hhost1x_bo_unpinh]j)}(hhost1x_bo_unpinh]hhost1x_bo_unpin}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubah}(h]h ](jjeh"]h$]h&]j j uh1jhjEhhhjWhMubj )}(h#(struct host1x_bo_mapping *mapping)h]j )}(h!struct host1x_bo_mapping *mappingh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hhost1x_bo_mappingh]hhost1x_bo_mapping}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjmodnameN classnameNj! j$ )}j' ]j* )}j jlsbc.host1x_bo_unpinasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj> )}(hjA h]h*}(hjhhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjubj)}(hmappingh]hmapping}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj~ubah}(h]h ]h"]h$]h&]j j uh1j hjEhhhjWhMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjAhhhjWhMubah}(h]j<ah ](jjeh"]h$]h&]jj)jhuh1jhjWhMhj>hhubj )}(hhh]h)}(h5Release an established DMA mapping of a buffer objecth]h5Release an established DMA mapping of a buffer object}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj>hhhjWhMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj!jCj!jDjEjFuh1jhhhjhNhNubjH)}(h**Parameters** ``struct host1x_bo_mapping *mapping`` Mapping to release **Description** Unmaps the given **mapping**, unless it is cached. Decreases the refcount on the underlying buffer object.h](h)}(h**Parameters**h]jR)}(hj+h]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj)ubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj%ubj)}(hhh]j)}(h9``struct host1x_bo_mapping *mapping`` Mapping to release h](j)}(h%``struct host1x_bo_mapping *mapping``h]j)}(hjJh]h!struct host1x_bo_mapping *mapping}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhjDubj)}(hhh]h)}(hMapping to releaseh]hMapping to release}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hMhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhj_hMhjAubah}(h]h ]h"]h$]h&]uh1jhj%ubh)}(h**Description**h]jR)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj%ubh)}(hjUnmaps the given **mapping**, unless it is cached. Decreases the refcount on the underlying buffer object.h](hUnmaps the given }(hjhhhNhNubjR)}(h **mapping**h]hmapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjubhN, unless it is cached. Decreases the refcount on the underlying buffer object.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,host1x_bo_clear_cached_mappings (C function)!c.host1x_bo_clear_cached_mappingshNtauh1jhjhhhNhNubj)}(hhh](j)}(h;void host1x_bo_clear_cached_mappings (struct host1x_bo *bo)h]j)}(h:void host1x_bo_clear_cached_mappings(struct host1x_bo *bo)h](j )}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hhost1x_bo_clear_cached_mappingsh]j)}(hhost1x_bo_clear_cached_mappingsh]hhost1x_bo_clear_cached_mappings}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]j j uh1jhjhhhjhMubj )}(h(struct host1x_bo *bo)h]j )}(hstruct host1x_bo *boh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj& hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h host1x_boh]h host1x_bo}(hj7 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4 ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj9 modnameN classnameNj! j$ )}j' ]j* )}j jsb!c.host1x_bo_clear_cached_mappingsasbuh1hhj ubj)}(h h]h }(hjW hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj> )}(hjA h]h*}(hje hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj ubj)}(hboh]hbo}(hjr hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj ubah}(h]h ]h"]h$]h&]j j uh1j hjhhhjhMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj )}(hhh]h)}(h+Remove all cached mappings pointing at a boh]h+Remove all cached mappings pointing at a bo}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj jCj jDjEjFuh1jhhhjhNhNubjH)}(hX**Parameters** ``struct host1x_bo *bo`` Buffer object to release mappings of **Description** Drops references to any mappings pointing to **bo** left in any caches. This must be called by any host1x_bo implementers that may be pinned with caching enabled before freeing the bo.h](h)}(h**Parameters**h]jR)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj ubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj ubj)}(hhh]j)}(h>``struct host1x_bo *bo`` Buffer object to release mappings of h](j)}(h``struct host1x_bo *bo``h]j)}(hj h]hstruct host1x_bo *bo}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj ubj)}(hhh]h)}(h$Buffer object to release mappings ofh]h$Buffer object to release mappings of}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]jR)}(hj!h]h Description}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj!ubah}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj ubh)}(hDrops references to any mappings pointing to **bo** left in any caches. This must be called by any host1x_bo implementers that may be pinned with caching enabled before freeing the bo.h](h-Drops references to any mappings pointing to }(hj.!hhhNhNubjR)}(h**bo**h]hbo}(hj6!hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj.!ubh left in any caches. This must be called by any host1x_bo implementers that may be pinned with caching enabled before freeing the bo.}(hj.!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhR/var/lib/git/docbuild/linux/Documentation/gpu/tegra:52: ./drivers/gpu/host1x/bus.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhjhhhNhNubeh}(h]host1x-infrastructure-referenceah ]h"]host1x infrastructure referenceah$]h&]uh1hhjZhhhhhK0ubh)}(hhh](h)}(hHost1x Syncpoint Referenceh]hHost1x Syncpoint Reference}(hja!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^!hhhhhK8ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j host1x_syncpt_alloc (C function)c.host1x_syncpt_allochNtauh1jhj^!hhhNhNubj)}(hhh](j)}(hgstruct host1x_syncpt * host1x_syncpt_alloc (struct host1x *host, unsigned long flags, const char *name)h]j)}(hestruct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host, unsigned long flags, const char *name)h](j)}(hjh]hstruct}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK0ubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!hhhj!hK0ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj!modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_allocsbc.host1x_syncpt_allocasbuh1hhj!hhhj!hK0ubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!hhhj!hK0ubj> )}(hjA h]h*}(hj!hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj!hhhj!hK0ubj)}(hhost1x_syncpt_alloch]j)}(hj!h]hhost1x_syncpt_alloc}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj!hhhj!hK0ubj )}(h<(struct host1x *host, unsigned long flags, const char *name)h](j )}(hstruct host1x *hosth](j)}(hjh]hstruct}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubh)}(hhh]j)}(hhost1xh]hhost1x}(hj "hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj""modnameN classnameNj! j$ )}j' ]j!c.host1x_syncpt_allocasbuh1hhj!ubj)}(h h]h }(hj>"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj> )}(hjA h]h*}(hjL"hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj!ubj)}(hhosth]hhost}(hjY"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj!ubj )}(hunsigned long flagsh](j )}(hunsignedh]hunsigned}(hjr"hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjn"ubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn"ubj )}(hlongh]hlong}(hj"hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjn"ubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn"ubj)}(hflagsh]hflags}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn"ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj!ubj )}(hconst char *nameh](j)}(hconsth]hconst}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj )}(hcharh]hchar}(hj"hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj"ubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj> )}(hjA h]h*}(hj"hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj"ubj)}(hnameh]hname}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj!ubeh}(h]h ]h"]h$]h&]j j uh1j hj!hhhj!hK0ubeh}(h]h ]h"]h$]h&]j j juh1jjjhj!hhhj!hK0ubah}(h]j{!ah ](jjeh"]h$]h&]jj)jhuh1jhj!hK0hj}!hhubj )}(hhh]h)}(hallocate a syncpointh]hallocate a syncpoint}(hj2#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK0hj/#hhubah}(h]h ]h"]h$]h&]uh1jhj}!hhhj!hK0ubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjJ#jCjJ#jDjEjFuh1jhhhj^!hNhNubjH)}(hX**Parameters** ``struct host1x *host`` host1x device data ``unsigned long flags`` bitfield of HOST1X_SYNCPT_* flags ``const char *name`` name for the syncpoint for use in debug prints **Description** Allocates a hardware syncpoint for the caller's use. The caller then has the sole authority to mutate the syncpoint's value until it is freed again. If no free syncpoints are available, or a NULL name was specified, returns NULL.h](h)}(h**Parameters**h]jR)}(hjT#h]h Parameters}(hjV#hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjR#ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK4hjN#ubj)}(hhh](j)}(h+``struct host1x *host`` host1x device data h](j)}(h``struct host1x *host``h]j)}(hjs#h]hstruct host1x *host}(hju#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq#ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK1hjm#ubj)}(hhh]h)}(hhost1x device datah]hhost1x device data}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hK1hj#ubah}(h]h ]h"]h$]h&]uh1jhjm#ubeh}(h]h ]h"]h$]h&]uh1jhj#hK1hjj#ubj)}(h:``unsigned long flags`` bitfield of HOST1X_SYNCPT_* flags h](j)}(h``unsigned long flags``h]j)}(hj#h]hunsigned long flags}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK2hj#ubj)}(hhh]h)}(h!bitfield of HOST1X_SYNCPT_* flagsh]h!bitfield of HOST1X_SYNCPT_* flags}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hK2hj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hK2hjj#ubj)}(hD``const char *name`` name for the syncpoint for use in debug prints h](j)}(h``const char *name``h]j)}(hj#h]hconst char *name}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK3hj#ubj)}(hhh]h)}(h.name for the syncpoint for use in debug printsh]h.name for the syncpoint for use in debug prints}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hK3hj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hK3hjj#ubeh}(h]h ]h"]h$]h&]uh1jhjN#ubh)}(h**Description**h]jR)}(hj $h]h Description}(hj"$hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj$ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK5hjN#ubh)}(hAllocates a hardware syncpoint for the caller's use. The caller then has the sole authority to mutate the syncpoint's value until it is freed again.h]hAllocates a hardware syncpoint for the caller’s use. The caller then has the sole authority to mutate the syncpoint’s value until it is freed again.}(hj6$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK4hjN#ubh)}(hPIf no free syncpoints are available, or a NULL name was specified, returns NULL.h]hPIf no free syncpoints are available, or a NULL name was specified, returns NULL.}(hjE$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK7hjN#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_syncpt_id (C function)c.host1x_syncpt_idhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h/u32 host1x_syncpt_id (struct host1x_syncpt *sp)h]j)}(h.u32 host1x_syncpt_id(struct host1x_syncpt *sp)h](h)}(hhh]j)}(hu32h]hu32}(hjw$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjt$ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjy$modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_idsbc.host1x_syncpt_idasbuh1hhjp$hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKnubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp$hhhj$hKnubj)}(hhost1x_syncpt_idh]j)}(hj$h]hhost1x_syncpt_id}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ](jjeh"]h$]h&]j j uh1jhjp$hhhj$hKnubj )}(h(struct host1x_syncpt *sp)h]j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj$modnameN classnameNj! j$ )}j' ]j$c.host1x_syncpt_idasbuh1hhj$ubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj> )}(hjA h]h*}(hj%hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj$ubj)}(hsph]hsp}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj$ubah}(h]h ]h"]h$]h&]j j uh1j hjp$hhhj$hKnubeh}(h]h ]h"]h$]h&]j j juh1jjjhjl$hhhj$hKnubah}(h]jg$ah ](jjeh"]h$]h&]jj)jhuh1jhj$hKnhji$hhubj )}(hhh]h)}(hretrieve syncpoint IDh]hretrieve syncpoint ID}(hjG%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKnhjD%hhubah}(h]h ]h"]h$]h&]uh1jhji$hhhj$hKnubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj_%jCj_%jDjEjFuh1jhhhj^!hNhNubjH)}(hX**Parameters** ``struct host1x_syncpt *sp`` host1x syncpoint **Description** Given a pointer to a struct host1x_syncpt, retrieves its ID. This ID is often used as a value to program into registers that control how hardware blocks interact with syncpoints.h](h)}(h**Parameters**h]jR)}(hji%h]h Parameters}(hjk%hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjg%ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKrhjc%ubj)}(hhh]j)}(h.``struct host1x_syncpt *sp`` host1x syncpoint h](j)}(h``struct host1x_syncpt *sp``h]j)}(hj%h]hstruct host1x_syncpt *sp}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKohj%ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hKohj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hKohj%ubah}(h]h ]h"]h$]h&]uh1jhjc%ubh)}(h**Description**h]jR)}(hj%h]h Description}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj%ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKqhjc%ubh)}(hGiven a pointer to a struct host1x_syncpt, retrieves its ID. This ID is often used as a value to program into registers that control how hardware blocks interact with syncpoints.h]hGiven a pointer to a struct host1x_syncpt, retrieves its ID. This ID is often used as a value to program into registers that control how hardware blocks interact with syncpoints.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKphjc%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#host1x_syncpt_incr_max (C function)c.host1x_syncpt_incr_maxhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h@u32 host1x_syncpt_incr_max (struct host1x_syncpt *sp, u32 incrs)h]j)}(h?u32 host1x_syncpt_incr_max(struct host1x_syncpt *sp, u32 incrs)h](h)}(hhh]j)}(hu32h]hu32}(hj &hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj &modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_incr_maxsbc.host1x_syncpt_incr_maxasbuh1hhj&hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK|ubj)}(h h]h }(hj-&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&hhhj,&hK|ubj)}(hhost1x_syncpt_incr_maxh]j)}(hj)&h]hhost1x_syncpt_incr_max}(hj?&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;&ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj&hhhj,&hK|ubj )}(h%(struct host1x_syncpt *sp, u32 incrs)h](j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hjZ&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjV&ubj)}(h h]h }(hjg&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjV&ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hjx&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhju&ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjz&modnameN classnameNj! j$ )}j' ]j'&c.host1x_syncpt_incr_maxasbuh1hhjV&ubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjV&ubj> )}(hjA h]h*}(hj&hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjV&ubj)}(hsph]hsp}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjV&ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjR&ubj )}(h u32 incrsh](h)}(hhh]j)}(hu32h]hu32}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj&modnameN classnameNj! j$ )}j' ]j'&c.host1x_syncpt_incr_maxasbuh1hhj&ubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(hincrsh]hincrs}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjR&ubeh}(h]h ]h"]h$]h&]j j uh1j hj&hhhj,&hK|ubeh}(h]h ]h"]h$]h&]j j juh1jjjhj&hhhj,&hK|ubah}(h]j%ah ](jjeh"]h$]h&]jj)jhuh1jhj,&hK|hj%hhubj )}(hhh]h)}(h!update the value sent to hardwareh]h!update the value sent to hardware}(hj#'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK|hj 'hhubah}(h]h ]h"]h$]h&]uh1jhj%hhhj,&hK|ubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj;'jCj;'jDjEjFuh1jhhhj^!hNhNubjH)}(he**Parameters** ``struct host1x_syncpt *sp`` host1x syncpoint ``u32 incrs`` number of incrementsh](h)}(h**Parameters**h]jR)}(hjE'h]h Parameters}(hjG'hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjC'ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj?'ubj)}(hhh](j)}(h.``struct host1x_syncpt *sp`` host1x syncpoint h](j)}(h``struct host1x_syncpt *sp``h]j)}(hjd'h]hstruct host1x_syncpt *sp}(hjf'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb'ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK}hj^'ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hj}'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjy'hK}hjz'ubah}(h]h ]h"]h$]h&]uh1jhj^'ubeh}(h]h ]h"]h$]h&]uh1jhjy'hK}hj['ubj)}(h"``u32 incrs`` number of incrementsh](j)}(h ``u32 incrs``h]j)}(hj'h]h u32 incrs}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj'ubj)}(hhh]h)}(hnumber of incrementsh]hnumber of increments}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chK~hj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hKhj['ubeh}(h]h ]h"]h$]h&]uh1jhj?'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_syncpt_incr (C function)c.host1x_syncpt_incrhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h1int host1x_syncpt_incr (struct host1x_syncpt *sp)h]j)}(h0int host1x_syncpt_incr(struct host1x_syncpt *sp)h](j )}(hinth]hint}(hj'hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj'hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKubj)}(h h]h }(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'hhhj(hKubj)}(hhost1x_syncpt_incrh]j)}(hhost1x_syncpt_incrh]hhost1x_syncpt_incr}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj'hhhj(hKubj )}(h(struct host1x_syncpt *sp)h]j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hj4(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0(ubj)}(h h]h }(hjA(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0(ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hjR(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO(ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjT(modnameN classnameNj! j$ )}j' ]j* )}j j(sbc.host1x_syncpt_incrasbuh1hhj0(ubj)}(h h]h }(hjr(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0(ubj> )}(hjA h]h*}(hj(hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj0(ubj)}(hsph]hsp}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0(ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj,(ubah}(h]h ]h"]h$]h&]j j uh1j hj'hhhj(hKubeh}(h]h ]h"]h$]h&]j j juh1jjjhj'hhhj(hKubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1jhj(hKhj'hhubj )}(hhh]h)}(h2increment syncpoint value from CPU, updating cacheh]h2increment syncpoint value from CPU, updating cache}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.c hKhj(hhubah}(h]h ]h"]h$]h&]uh1jhj'hhhj(hKubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj(jCj(jDjEjFuh1jhhhj^!hNhNubjH)}(h?**Parameters** ``struct host1x_syncpt *sp`` host1x syncpointh](h)}(h**Parameters**h]jR)}(hj(h]h Parameters}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj(ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj(ubj)}(hhh]j)}(h-``struct host1x_syncpt *sp`` host1x syncpointh](j)}(h``struct host1x_syncpt *sp``h]j)}(hj(h]hstruct host1x_syncpt *sp}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj(ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj)ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhj )hKhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_syncpt_wait (C function)c.host1x_syncpt_waithNtauh1jhj^!hhhNhNubj)}(hhh](j)}(hWint host1x_syncpt_wait (struct host1x_syncpt *sp, u32 thresh, long timeout, u32 *value)h]j)}(hVint host1x_syncpt_wait(struct host1x_syncpt *sp, u32 thresh, long timeout, u32 *value)h](j )}(hinth]hint}(hjR)hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjN)hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKubj)}(h h]h }(hja)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjN)hhhj`)hKubj)}(hhost1x_syncpt_waith]j)}(hhost1x_syncpt_waith]hhost1x_syncpt_wait}(hjs)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjo)ubah}(h]h ](jjeh"]h$]h&]j j uh1jhjN)hhhj`)hKubj )}(h@(struct host1x_syncpt *sp, u32 thresh, long timeout, u32 *value)h](j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj)modnameN classnameNj! j$ )}j' ]j* )}j ju)sbc.host1x_syncpt_waitasbuh1hhj)ubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj> )}(hjA h]h*}(hj)hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj)ubj)}(hsph]hsp}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj)ubj )}(h u32 threshh](h)}(hhh]j)}(hu32h]hu32}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj*modnameN classnameNj! j$ )}j' ]j)c.host1x_syncpt_waitasbuh1hhj)ubj)}(h h]h }(hj"*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj)}(hthreshh]hthresh}(hj0*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj)ubj )}(h long timeouth](j )}(hlongh]hlong}(hjI*hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjE*ubj)}(h h]h }(hjW*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjE*ubj)}(htimeouth]htimeout}(hje*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjE*ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj)ubj )}(h u32 *valueh](h)}(hhh]j)}(hu32h]hu32}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~*ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj*modnameN classnameNj! j$ )}j' ]j)c.host1x_syncpt_waitasbuh1hhjz*ubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz*ubj> )}(hjA h]h*}(hj*hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjz*ubj)}(hvalueh]hvalue}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz*ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj)ubeh}(h]h ]h"]h$]h&]j j uh1j hjN)hhhj`)hKubeh}(h]h ]h"]h$]h&]j j juh1jjjhjJ)hhhj`)hKubah}(h]jE)ah ](jjeh"]h$]h&]jj)jhuh1jhj`)hKhjG)hhubj )}(hhh]h)}(h+wait for a syncpoint to reach a given valueh]h+wait for a syncpoint to reach a given value}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj*hhubah}(h]h ]h"]h$]h&]uh1jhjG)hhhj`)hKubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj*jCj*jDjEjFuh1jhhhj^!hNhNubjH)}(h**Parameters** ``struct host1x_syncpt *sp`` host1x syncpoint ``u32 thresh`` threshold ``long timeout`` maximum time to wait for the syncpoint to reach the given value ``u32 *value`` return location for the syncpoint valueh](h)}(h**Parameters**h]jR)}(hj+h]h Parameters}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj+ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj+ubj)}(hhh](j)}(h.``struct host1x_syncpt *sp`` host1x syncpoint h](j)}(h``struct host1x_syncpt *sp``h]j)}(hj%+h]hstruct host1x_syncpt *sp}(hj'+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#+ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj+ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hj>+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:+hKhj;+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj:+hKhj+ubj)}(h``u32 thresh`` threshold h](j)}(h``u32 thresh``h]j)}(hj^+h]h u32 thresh}(hj`+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\+ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhjX+ubj)}(hhh]h)}(h thresholdh]h threshold}(hjw+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs+hKhjt+ubah}(h]h ]h"]h$]h&]uh1jhjX+ubeh}(h]h ]h"]h$]h&]uh1jhjs+hKhj+ubj)}(hQ``long timeout`` maximum time to wait for the syncpoint to reach the given value h](j)}(h``long timeout``h]j)}(hj+h]h long timeout}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj+ubj)}(hhh]h)}(h?maximum time to wait for the syncpoint to reach the given valueh]h?maximum time to wait for the syncpoint to reach the given value}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hKhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hKhj+ubj)}(h6``u32 *value`` return location for the syncpoint valueh](j)}(h``u32 *value``h]j)}(hj+h]h u32 *value}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj+ubj)}(hhh]h)}(h'return location for the syncpoint valueh]h'return location for the syncpoint value}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chKhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hKhj+ubeh}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"host1x_syncpt_request (C function)c.host1x_syncpt_requesthNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h`struct host1x_syncpt * host1x_syncpt_request (struct host1x_client *client, unsigned long flags)h]j)}(h^struct host1x_syncpt *host1x_syncpt_request(struct host1x_client *client, unsigned long flags)h](j)}(hjh]hstruct}(hj*,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&,hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMLubj)}(h h]h }(hj8,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&,hhhj7,hMLubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hjI,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjF,ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjK,modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_requestsbc.host1x_syncpt_requestasbuh1hhj&,hhhj7,hMLubj)}(h h]h }(hjj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&,hhhj7,hMLubj> )}(hjA h]h*}(hjx,hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj&,hhhj7,hMLubj)}(hhost1x_syncpt_requesth]j)}(hjg,h]hhost1x_syncpt_request}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj&,hhhj7,hMLubj )}(h3(struct host1x_client *client, unsigned long flags)h](j )}(hstruct host1x_client *clienth](j)}(hjh]hstruct}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubh)}(hhh]j)}(h host1x_clienth]h host1x_client}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj,modnameN classnameNj! j$ )}j' ]je,c.host1x_syncpt_requestasbuh1hhj,ubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj> )}(hjA h]h*}(hj,hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj,ubj)}(hclienth]hclient}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj,ubj )}(hunsigned long flagsh](j )}(hunsignedh]hunsigned}(hj-hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj-ubj)}(h h]h }(hj"-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj )}(hlongh]hlong}(hj0-hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj-ubj)}(h h]h }(hj>-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hflagsh]hflags}(hjL-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj,ubeh}(h]h ]h"]h$]h&]j j uh1j hj&,hhhj7,hMLubeh}(h]h ]h"]h$]h&]j j juh1jjjhj",hhhj7,hMLubah}(h]j,ah ](jjeh"]h$]h&]jj)jhuh1jhj7,hMLhj,hhubj )}(hhh]h)}(hrequest a syncpointh]hrequest a syncpoint}(hjv-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMLhjs-hhubah}(h]h ]h"]h$]h&]uh1jhj,hhhj7,hMLubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj-jCj-jDjEjFuh1jhhhj^!hNhNubjH)}(hX**Parameters** ``struct host1x_client *client`` client requesting the syncpoint ``unsigned long flags`` flags **Description** host1x client drivers can use this function to allocate a syncpoint for subsequent use. A syncpoint returned by this function will be reserved for use by the client exclusively. When no longer using a syncpoint, a host1x client driver needs to release it using host1x_syncpt_put().h](h)}(h**Parameters**h]jR)}(hj-h]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj-ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMPhj-ubj)}(hhh](j)}(hA``struct host1x_client *client`` client requesting the syncpoint h](j)}(h ``struct host1x_client *client``h]j)}(hj-h]hstruct host1x_client *client}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMMhj-ubj)}(hhh]h)}(hclient requesting the syncpointh]hclient requesting the syncpoint}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMMhj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hMMhj-ubj)}(h``unsigned long flags`` flags h](j)}(h``unsigned long flags``h]j)}(hj-h]hunsigned long flags}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMNhj-ubj)}(hhh]h)}(hflagsh]hflags}(hj .hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMNhj.ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj.hMNhj-ubeh}(h]h ]h"]h$]h&]uh1jhj-ubh)}(h**Description**h]jR)}(hj+.h]h Description}(hj-.hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj).ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMPhj-ubh)}(hXhost1x client drivers can use this function to allocate a syncpoint for subsequent use. A syncpoint returned by this function will be reserved for use by the client exclusively. When no longer using a syncpoint, a host1x client driver needs to release it using host1x_syncpt_put().h]hXhost1x client drivers can use this function to allocate a syncpoint for subsequent use. A syncpoint returned by this function will be reserved for use by the client exclusively. When no longer using a syncpoint, a host1x client driver needs to release it using host1x_syncpt_put().}(hjA.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMOhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_syncpt_put (C function)c.host1x_syncpt_puthNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h1void host1x_syncpt_put (struct host1x_syncpt *sp)h]j)}(h0void host1x_syncpt_put(struct host1x_syncpt *sp)h](j )}(hvoidh]hvoid}(hjp.hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjl.hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMpubj)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl.hhhj~.hMpubj)}(hhost1x_syncpt_puth]j)}(hhost1x_syncpt_puth]hhost1x_syncpt_put}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ](jjeh"]h$]h&]j j uh1jhjl.hhhj~.hMpubj )}(h(struct host1x_syncpt *sp)h]j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubj)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj.modnameN classnameNj! j$ )}j' ]j* )}j j.sbc.host1x_syncpt_putasbuh1hhj.ubj)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubj> )}(hjA h]h*}(hj.hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj.ubj)}(hsph]hsp}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj.ubah}(h]h ]h"]h$]h&]j j uh1j hjl.hhhj~.hMpubeh}(h]h ]h"]h$]h&]j j juh1jjjhjh.hhhj~.hMpubah}(h]jc.ah ](jjeh"]h$]h&]jj)jhuh1jhj~.hMphje.hhubj )}(hhh]h)}(hfree a requested syncpointh]hfree a requested syncpoint}(hj0/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMphj-/hhubah}(h]h ]h"]h$]h&]uh1jhje.hhhj~.hMpubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjH/jCjH/jDjEjFuh1jhhhj^!hNhNubjH)}(h**Parameters** ``struct host1x_syncpt *sp`` host1x syncpoint **Description** Release a syncpoint previously allocated using host1x_syncpt_request(). A host1x client driver should call this when the syncpoint is no longer in use.h](h)}(h**Parameters**h]jR)}(hjR/h]h Parameters}(hjT/hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjP/ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMthjL/ubj)}(hhh]j)}(h.``struct host1x_syncpt *sp`` host1x syncpoint h](j)}(h``struct host1x_syncpt *sp``h]j)}(hjq/h]hstruct host1x_syncpt *sp}(hjs/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo/ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMqhjk/ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMqhj/ubah}(h]h ]h"]h$]h&]uh1jhjk/ubeh}(h]h ]h"]h$]h&]uh1jhj/hMqhjh/ubah}(h]h ]h"]h$]h&]uh1jhjL/ubh)}(h**Description**h]jR)}(hj/h]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj/ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMshjL/ubh)}(hRelease a syncpoint previously allocated using host1x_syncpt_request(). A host1x client driver should call this when the syncpoint is no longer in use.h]hRelease a syncpoint previously allocated using host1x_syncpt_request(). A host1x client driver should call this when the syncpoint is no longer in use.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMrhjL/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#host1x_syncpt_read_max (C function)c.host1x_syncpt_read_maxhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h5u32 host1x_syncpt_read_max (struct host1x_syncpt *sp)h]j)}(h4u32 host1x_syncpt_read_max(struct host1x_syncpt *sp)h](h)}(hhh]j)}(hu32h]hu32}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj/modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_read_maxsbc.host1x_syncpt_read_maxasbuh1hhj/hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/hhhj0hMubj)}(hhost1x_syncpt_read_maxh]j)}(hj0h]hhost1x_syncpt_read_max}(hj(0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$0ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj/hhhj0hMubj )}(h(struct host1x_syncpt *sp)h]j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hjC0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?0ubj)}(h h]h }(hjP0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?0ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hja0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^0ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjc0modnameN classnameNj! j$ )}j' ]j0c.host1x_syncpt_read_maxasbuh1hhj?0ubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?0ubj> )}(hjA h]h*}(hj0hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj?0ubj)}(hsph]hsp}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?0ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj;0ubah}(h]h ]h"]h$]h&]j j uh1j hj/hhhj0hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhj/hhhj0hMubah}(h]j/ah ](jjeh"]h$]h&]jj)jhuh1jhj0hMhj/hhubj )}(hhh]h)}(hread maximum syncpoint valueh]hread maximum syncpoint value}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj0hhubah}(h]h ]h"]h$]h&]uh1jhj/hhhj0hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj0jCj0jDjEjFuh1jhhhj^!hNhNubjH)}(h**Parameters** ``struct host1x_syncpt *sp`` host1x syncpoint **Description** The maximum syncpoint value indicates how many operations there are in queue, either in channel or in a software thread.h](h)}(h**Parameters**h]jR)}(hj0h]h Parameters}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj0ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj0ubj)}(hhh]j)}(h.``struct host1x_syncpt *sp`` host1x syncpoint h](j)}(h``struct host1x_syncpt *sp``h]j)}(hj1h]hstruct host1x_syncpt *sp}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj0ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj1ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhj1hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj0ubh)}(h**Description**h]jR)}(hj@1h]h Description}(hjB1hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj>1ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj0ubh)}(hxThe maximum syncpoint value indicates how many operations there are in queue, either in channel or in a software thread.h]hxThe maximum syncpoint value indicates how many operations there are in queue, either in channel or in a software thread.}(hjV1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#host1x_syncpt_read_min (C function)c.host1x_syncpt_read_minhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h5u32 host1x_syncpt_read_min (struct host1x_syncpt *sp)h]j)}(h4u32 host1x_syncpt_read_min(struct host1x_syncpt *sp)h](h)}(hhh]j)}(hu32h]hu32}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj1modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_read_minsbc.host1x_syncpt_read_minasbuh1hhj1hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhj1hMubj)}(hhost1x_syncpt_read_minh]j)}(hj1h]hhost1x_syncpt_read_min}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj1hhhj1hMubj )}(h(struct host1x_syncpt *sp)h]j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj1modnameN classnameNj! j$ )}j' ]j1c.host1x_syncpt_read_minasbuh1hhj1ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj> )}(hjA h]h*}(hj!2hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj1ubj)}(hsph]hsp}(hj.2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj1ubah}(h]h ]h"]h$]h&]j j uh1j hj1hhhj1hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhj}1hhhj1hMubah}(h]jx1ah ](jjeh"]h$]h&]jj)jhuh1jhj1hMhjz1hhubj )}(hhh]h)}(hread minimum syncpoint valueh]hread minimum syncpoint value}(hjX2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjU2hhubah}(h]h ]h"]h$]h&]uh1jhjz1hhhj1hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjp2jCjp2jDjEjFuh1jhhhj^!hNhNubjH)}(h**Parameters** ``struct host1x_syncpt *sp`` host1x syncpoint **Description** The minimum syncpoint value is a shadow of the current sync point value in hardware.h](h)}(h**Parameters**h]jR)}(hjz2h]h Parameters}(hj|2hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjx2ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjt2ubj)}(hhh]j)}(h.``struct host1x_syncpt *sp`` host1x syncpoint h](j)}(h``struct host1x_syncpt *sp``h]j)}(hj2h]hstruct host1x_syncpt *sp}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj2ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hMhj2ubah}(h]h ]h"]h$]h&]uh1jhjt2ubh)}(h**Description**h]jR)}(hj2h]h Description}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj2ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjt2ubh)}(hTThe minimum syncpoint value is a shadow of the current sync point value in hardware.h]hTThe minimum syncpoint value is a shadow of the current sync point value in hardware.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjt2ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_syncpt_read (C function)c.host1x_syncpt_readhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h1u32 host1x_syncpt_read (struct host1x_syncpt *sp)h]j)}(h0u32 host1x_syncpt_read(struct host1x_syncpt *sp)h](h)}(hhh]j)}(hu32h]hu32}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj3modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_readsbc.host1x_syncpt_readasbuh1hhj3hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hj>3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3hhhj=3hMubj)}(hhost1x_syncpt_readh]j)}(hj:3h]hhost1x_syncpt_read}(hjP3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL3ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj3hhhj=3hMubj )}(h(struct host1x_syncpt *sp)h]j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hjk3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjg3ubj)}(h h]h }(hjx3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjg3ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj3modnameN classnameNj! j$ )}j' ]j83c.host1x_syncpt_readasbuh1hhjg3ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjg3ubj> )}(hjA h]h*}(hj3hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjg3ubj)}(hsph]hsp}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjg3ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hjc3ubah}(h]h ]h"]h$]h&]j j uh1j hj3hhhj=3hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhj3hhhj=3hMubah}(h]j 3ah ](jjeh"]h$]h&]jj)jhuh1jhj=3hMhj3hhubj )}(hhh]h)}(h read the current syncpoint valueh]h read the current syncpoint value}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj3hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj=3hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj4jCj4jDjEjFuh1jhhhj^!hNhNubjH)}(h?**Parameters** ``struct host1x_syncpt *sp`` host1x syncpointh](h)}(h**Parameters**h]jR)}(hj4h]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj 4ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj4ubj)}(hhh]j)}(h-``struct host1x_syncpt *sp`` host1x syncpointh](j)}(h``struct host1x_syncpt *sp``h]j)}(hj-4h]hstruct host1x_syncpt *sp}(hj/4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+4ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj'4ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hjF4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjC4ubah}(h]h ]h"]h$]h&]uh1jhj'4ubeh}(h]h ]h"]h$]h&]uh1jhjB4hMhj$4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$host1x_syncpt_get_by_id (C function)c.host1x_syncpt_get_by_idhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(hUstruct host1x_syncpt * host1x_syncpt_get_by_id (struct host1x *host, unsigned int id)h]j)}(hSstruct host1x_syncpt *host1x_syncpt_get_by_id(struct host1x *host, unsigned int id)h](j)}(hjh]hstruct}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhj4hMubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj4modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_get_by_idsbc.host1x_syncpt_get_by_idasbuh1hhj4hhhj4hMubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhj4hMubj> )}(hjA h]h*}(hj4hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj4hhhj4hMubj)}(hhost1x_syncpt_get_by_idh]j)}(hj4h]hhost1x_syncpt_get_by_id}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj4hhhj4hMubj )}(h&(struct host1x *host, unsigned int id)h](j )}(hstruct host1x *hosth](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubh)}(hhh]j)}(hhost1xh]hhost1x}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj!5modnameN classnameNj! j$ )}j' ]j4c.host1x_syncpt_get_by_idasbuh1hhj4ubj)}(h h]h }(hj=5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj> )}(hjA h]h*}(hjK5hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj4ubj)}(hhosth]hhost}(hjX5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj4ubj )}(hunsigned int idh](j )}(hunsignedh]hunsigned}(hjq5hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjm5ubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm5ubj )}(hinth]hint}(hj5hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjm5ubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm5ubj)}(hidh]hid}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm5ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj4ubeh}(h]h ]h"]h$]h&]j j uh1j hj4hhhj4hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhj4hhhj4hMubah}(h]jz4ah ](jjeh"]h$]h&]jj)jhuh1jhj4hMhj|4hhubj )}(hhh]h)}(hobtain a syncpoint by IDh]hobtain a syncpoint by ID}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj5hhubah}(h]h ]h"]h$]h&]uh1jhj|4hhhj4hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj5jCj5jDjEjFuh1jhhhj^!hNhNubjH)}(h_**Parameters** ``struct host1x *host`` host1x controller ``unsigned int id`` syncpoint IDh](h)}(h**Parameters**h]jR)}(hj5h]h Parameters}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj5ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj5ubj)}(hhh](j)}(h*``struct host1x *host`` host1x controller h](j)}(h``struct host1x *host``h]j)}(hj6h]hstruct host1x *host}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj6ubj)}(hhh]h)}(hhost1x controllerh]hhost1x controller}(hj-6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)6hMhj*6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj)6hMhj 6ubj)}(h ``unsigned int id`` syncpoint IDh](j)}(h``unsigned int id``h]j)}(hjM6h]hunsigned int id}(hjO6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK6ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjG6ubj)}(hhh]h)}(h syncpoint IDh]h syncpoint ID}(hjf6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjc6ubah}(h]h ]h"]h$]h&]uh1jhjG6ubeh}(h]h ]h"]h$]h&]uh1jhjb6hMhj 6ubeh}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*host1x_syncpt_get_by_id_noref (C function)c.host1x_syncpt_get_by_id_norefhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h[struct host1x_syncpt * host1x_syncpt_get_by_id_noref (struct host1x *host, unsigned int id)h]j)}(hYstruct host1x_syncpt *host1x_syncpt_get_by_id_noref(struct host1x *host, unsigned int id)h](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhj6hMubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj6modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_get_by_id_norefsbc.host1x_syncpt_get_by_id_norefasbuh1hhj6hhhj6hMubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhj6hMubj> )}(hjA h]h*}(hj6hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj6hhhj6hMubj)}(hhost1x_syncpt_get_by_id_norefh]j)}(hj6h]hhost1x_syncpt_get_by_id_noref}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj6hhhj6hMubj )}(h&(struct host1x *host, unsigned int id)h](j )}(hstruct host1x *hosth](j)}(hjh]hstruct}(hj!7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj)}(h h]h }(hj.7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubh)}(hhh]j)}(hhost1xh]hhost1x}(hj?7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<7ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetjA7modnameN classnameNj! j$ )}j' ]j6c.host1x_syncpt_get_by_id_norefasbuh1hhj7ubj)}(h h]h }(hj]7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj> )}(hjA h]h*}(hjk7hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj7ubj)}(hhosth]hhost}(hjx7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj7ubj )}(hunsigned int idh](j )}(hunsignedh]hunsigned}(hj7hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj7ubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj )}(hinth]hint}(hj7hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj7ubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj)}(hidh]hid}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj7ubeh}(h]h ]h"]h$]h&]j j uh1j hj6hhhj6hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhj6hhhj6hMubah}(h]j6ah ](jjeh"]h$]h&]jj)jhuh1jhj6hMhj6hhubj )}(hhh]h)}(h9obtain a syncpoint by ID but don't increase the refcount.h]h;obtain a syncpoint by ID but don’t increase the refcount.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj7hhubah}(h]h ]h"]h$]h&]uh1jhj6hhhj6hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj 8jCj 8jDjEjFuh1jhhhj^!hNhNubjH)}(h_**Parameters** ``struct host1x *host`` host1x controller ``unsigned int id`` syncpoint IDh](h)}(h**Parameters**h]jR)}(hj8h]h Parameters}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj8ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj8ubj)}(hhh](j)}(h*``struct host1x *host`` host1x controller h](j)}(h``struct host1x *host``h]j)}(hj48h]hstruct host1x *host}(hj68hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj28ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj.8ubj)}(hhh]h)}(hhost1x controllerh]hhost1x controller}(hjM8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI8hMhjJ8ubah}(h]h ]h"]h$]h&]uh1jhj.8ubeh}(h]h ]h"]h$]h&]uh1jhjI8hMhj+8ubj)}(h ``unsigned int id`` syncpoint IDh](j)}(h``unsigned int id``h]j)}(hjm8h]hunsigned int id}(hjo8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk8ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjg8ubj)}(hhh]h)}(h syncpoint IDh]h syncpoint ID}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj8ubah}(h]h ]h"]h$]h&]uh1jhjg8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhj+8ubeh}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jhost1x_syncpt_get (C function)c.host1x_syncpt_gethNtauh1jhj^!hhhNhNubj)}(hhh](j)}(hCstruct host1x_syncpt * host1x_syncpt_get (struct host1x_syncpt *sp)h]j)}(hAstruct host1x_syncpt *host1x_syncpt_get(struct host1x_syncpt *sp)h](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8hhhj8hMubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj8modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_getsbc.host1x_syncpt_getasbuh1hhj8hhhj8hMubj)}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8hhhj8hMubj> )}(hjA h]h*}(hj9hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj8hhhj8hMubj)}(hhost1x_syncpt_geth]j)}(hj9h]hhost1x_syncpt_get}(hj&9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"9ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj8hhhj8hMubj )}(h(struct host1x_syncpt *sp)h]j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hjA9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=9ubj)}(h h]h }(hjN9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=9ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj_9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\9ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetja9modnameN classnameNj! j$ )}j' ]j9c.host1x_syncpt_getasbuh1hhj=9ubj)}(h h]h }(hj}9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=9ubj> )}(hjA h]h*}(hj9hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj=9ubj)}(hsph]hsp}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=9ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj99ubah}(h]h ]h"]h$]h&]j j uh1j hj8hhhj8hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhj8hhhj8hMubah}(h]j8ah ](jjeh"]h$]h&]jj)jhuh1jhj8hMhj8hhubj )}(hhh]h)}(hincrement syncpoint refcounth]hincrement syncpoint refcount}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj9hhubah}(h]h ]h"]h$]h&]uh1jhj8hhhj8hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj9jCj9jDjEjFuh1jhhhj^!hNhNubjH)}(h8**Parameters** ``struct host1x_syncpt *sp`` syncpointh](h)}(h**Parameters**h]jR)}(hj9h]h Parameters}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj9ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj9ubj)}(hhh]j)}(h&``struct host1x_syncpt *sp`` syncpointh](j)}(h``struct host1x_syncpt *sp``h]j)}(hj:h]hstruct host1x_syncpt *sp}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj9ubj)}(hhh]h)}(h syncpointh]h syncpoint}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj:ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#host1x_syncpt_get_base (C function)c.host1x_syncpt_get_basehNtauh1jhj^!hhhNhNubj)}(hhh](j)}(hMstruct host1x_syncpt_base * host1x_syncpt_get_base (struct host1x_syncpt *sp)h]j)}(hKstruct host1x_syncpt_base *host1x_syncpt_get_base(struct host1x_syncpt *sp)h](j)}(hjh]hstruct}(hj]:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjY:hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hjk:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjY:hhhjj:hMubh)}(hhh]j)}(hhost1x_syncpt_baseh]hhost1x_syncpt_base}(hj|:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy:ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj~:modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_get_basesbc.host1x_syncpt_get_baseasbuh1hhjY:hhhjj:hMubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjY:hhhjj:hMubj> )}(hjA h]h*}(hj:hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjY:hhhjj:hMubj)}(hhost1x_syncpt_get_baseh]j)}(hj:h]hhost1x_syncpt_get_base}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](jjeh"]h$]h&]j j uh1jhjY:hhhjj:hMubj )}(h(struct host1x_syncpt *sp)h]j )}(hstruct host1x_syncpt *sph](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubh)}(hhh]j)}(h host1x_syncpth]h host1x_syncpt}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj:modnameN classnameNj! j$ )}j' ]j:c.host1x_syncpt_get_baseasbuh1hhj:ubj)}(h h]h }(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj> )}(hjA h]h*}(hj!;hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj:ubj)}(hsph]hsp}(hj.;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj:ubah}(h]h ]h"]h$]h&]j j uh1j hjY:hhhjj:hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjU:hhhjj:hMubah}(h]jP:ah ](jjeh"]h$]h&]jj)jhuh1jhjj:hMhjR:hhubj )}(hhh]h)}(h0obtain the wait base associated with a syncpointh]h0obtain the wait base associated with a syncpoint}(hjX;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjU;hhubah}(h]h ]h"]h$]h&]uh1jhjR:hhhjj:hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBjp;jCjp;jDjEjFuh1jhhhj^!hNhNubjH)}(h?**Parameters** ``struct host1x_syncpt *sp`` host1x syncpointh](h)}(h**Parameters**h]jR)}(hjz;h]h Parameters}(hj|;hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjx;ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjt;ubj)}(hhh]j)}(h-``struct host1x_syncpt *sp`` host1x syncpointh](j)}(h``struct host1x_syncpt *sp``h]j)}(hj;h]hstruct host1x_syncpt *sp}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj;ubj)}(hhh]h)}(hhost1x syncpointh]hhost1x syncpoint}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhjt;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"host1x_syncpt_base_id (C function)c.host1x_syncpt_base_idhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h;u32 host1x_syncpt_base_id (struct host1x_syncpt_base *base)h]j)}(h:u32 host1x_syncpt_base_id(struct host1x_syncpt_base *base)h](h)}(hhh]j)}(hu32h]hu32}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj;modnameN classnameNj! j$ )}j' ]j* )}j host1x_syncpt_base_idsbc.host1x_syncpt_base_idasbuh1hhj;hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhj<hMubj)}(hhost1x_syncpt_base_idh]j)}(hj<h]hhost1x_syncpt_base_id}(hj*<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&<ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj;hhhj<hMubj )}(h!(struct host1x_syncpt_base *base)h]j )}(hstruct host1x_syncpt_base *baseh](j)}(hjh]hstruct}(hjE<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA<ubj)}(h h]h }(hjR<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA<ubh)}(hhh]j)}(hhost1x_syncpt_baseh]hhost1x_syncpt_base}(hjc<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`<ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetje<modnameN classnameNj! j$ )}j' ]j<c.host1x_syncpt_base_idasbuh1hhjA<ubj)}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA<ubj> )}(hjA h]h*}(hj<hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hjA<ubj)}(hbaseh]hbase}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA<ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj=<ubah}(h]h ]h"]h$]h&]j j uh1j hj;hhhj<hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhj;hhhj<hMubah}(h]j;ah ](jjeh"]h$]h&]jj)jhuh1jhj<hMhj;hhubj )}(hhh]h)}(h(retrieve the ID of a syncpoint wait baseh]h(retrieve the ID of a syncpoint wait base}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj<hhubah}(h]h ]h"]h$]h&]uh1jhj;hhhj<hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj<jCj<jDjEjFuh1jhhhj^!hNhNubjH)}(hP**Parameters** ``struct host1x_syncpt_base *base`` host1x syncpoint wait baseh](h)}(h**Parameters**h]jR)}(hj<h]h Parameters}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj<ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj<ubj)}(hhh]j)}(h>``struct host1x_syncpt_base *base`` host1x syncpoint wait baseh](j)}(h#``struct host1x_syncpt_base *base``h]j)}(hj=h]hstruct host1x_syncpt_base *base}(hj =hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj=ubj)}(hhh]h)}(hhost1x syncpoint wait baseh]hhost1x syncpoint wait base}(hj =hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j5host1x_syncpt_release_vblank_reservation (C function)*c.host1x_syncpt_release_vblank_reservationhNtauh1jhj^!hhhNhNubj)}(hhh](j)}(h[void host1x_syncpt_release_vblank_reservation (struct host1x_client *client, u32 syncpt_id)h]j)}(hZvoid host1x_syncpt_release_vblank_reservation(struct host1x_client *client, u32 syncpt_id)h](j )}(hvoidh]hvoid}(hja=hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj]=hhhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMubj)}(h h]h }(hjp=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]=hhhjo=hMubj)}(h(host1x_syncpt_release_vblank_reservationh]j)}(h(host1x_syncpt_release_vblank_reservationh]h(host1x_syncpt_release_vblank_reservation}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~=ubah}(h]h ](jjeh"]h$]h&]j j uh1jhj]=hhhjo=hMubj )}(h-(struct host1x_client *client, u32 syncpt_id)h](j )}(hstruct host1x_client *clienth](j)}(hjh]hstruct}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubh)}(hhh]j)}(h host1x_clienth]h host1x_client}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj=modnameN classnameNj! j$ )}j' ]j* )}j j=sb*c.host1x_syncpt_release_vblank_reservationasbuh1hhj=ubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubj> )}(hjA h]h*}(hj=hhhNhNubah}(h]h ]jJ ah"]h$]h&]uh1j= hj=ubj)}(hclienth]hclient}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj=ubj )}(h u32 syncpt_idh](h)}(hhh]j)}(hu32h]hu32}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&] refdomainj<reftypej reftargetj>modnameN classnameNj! j$ )}j' ]j=*c.host1x_syncpt_release_vblank_reservationasbuh1hhj >ubj)}(h h]h }(hj1>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj >ubj)}(h syncpt_idh]h syncpt_id}(hj?>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj >ubeh}(h]h ]h"]h$]h&]noemphj j uh1j hj=ubeh}(h]h ]h"]h$]h&]j j uh1j hj]=hhhjo=hMubeh}(h]h ]h"]h$]h&]j j juh1jjjhjY=hhhjo=hMubah}(h]jT=ah ](jjeh"]h$]h&]jj)jhuh1jhjo=hMhjV=hhubj )}(hhh]h)}(h.Make VBLANK syncpoint available for allocationh]h.Make VBLANK syncpoint available for allocation}(hji>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chMhjf>hhubah}(h]h ]h"]h$]h&]uh1jhjV=hhhjo=hMubeh}(h]h ](j<functioneh"]h$]h&]jAj<jBj>jCj>jDjEjFuh1jhhhj^!hNhNubjH)}(hX**Parameters** ``struct host1x_client *client`` host1x bus client ``u32 syncpt_id`` syncpoint ID to make available **Description** Makes VBLANK syncpoint available for allocatation if it was reserved at initialization time. This should be called by the display driver after it has ensured that any VBLANK increment programming configured by the boot chain has been disabled.h](h)}(h**Parameters**h]jR)}(hj>h]h Parameters}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj>ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chM hj>ubj)}(hhh](j)}(h3``struct host1x_client *client`` host1x bus client h](j)}(h ``struct host1x_client *client``h]j)}(hj>h]hstruct host1x_client *client}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chM hj>ubj)}(hhh]h)}(hhost1x bus clienth]hhost1x bus client}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hM hj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hM hj>ubj)}(h1``u32 syncpt_id`` syncpoint ID to make available h](j)}(h``u32 syncpt_id``h]j)}(hj>h]h u32 syncpt_id}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chM hj>ubj)}(hhh]h)}(hsyncpoint ID to make availableh]hsyncpoint ID to make available}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hM hj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hM hj>ubeh}(h]h ]h"]h$]h&]uh1jhj>ubh)}(h**Description**h]jR)}(hj?h]h Description}(hj ?hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj?ubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chM hj>ubh)}(hMakes VBLANK syncpoint available for allocatation if it was reserved at initialization time. This should be called by the display driver after it has ensured that any VBLANK increment programming configured by the boot chain has been disabled.h]hMakes VBLANK syncpoint available for allocatation if it was reserved at initialization time. This should be called by the display driver after it has ensured that any VBLANK increment programming configured by the boot chain has been disabled.}(hj4?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhU/var/lib/git/docbuild/linux/Documentation/gpu/tegra:58: ./drivers/gpu/host1x/syncpt.chM hj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jGhj^!hhhNhNubeh}(h]host1x-syncpoint-referenceah ]h"]host1x syncpoint referenceah$]h&]uh1hhjZhhhhhK8ubeh}(h]driver-infrastructureah ]h"]driver infrastructureah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h KMS driverh]h KMS driver}(hj]?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ?hhhhhK>ubh)}(hThe display hardware has remained mostly backwards compatible over the various Tegra SoC generations, up until Tegra186 which introduces several changes that make it difficult to support with a parameterized driver.Ch]hThe display hardware has remained mostly backwards compatible over the various Tegra SoC generations, up until Tegra186 which introduces several changes that make it difficult to support with a parameterized driver.}(hjk?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjZ?hhubh)}(hhh](h)}(hDisplay Controllersh]hDisplay Controllers}(hj|?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjy?hhhhhKEubh)}(hXTegra SoCs have two display controllers, each of which can be associated with zero or more outputs. Outputs can also share a single display controller, but only if they run with compatible display timings. Two display controllers can also share a single framebuffer, allowing cloned configurations even if modes on two outputs don't match. A display controller is modelled as a CRTC in KMS terms.h]hXTegra SoCs have two display controllers, each of which can be associated with zero or more outputs. Outputs can also share a single display controller, but only if they run with compatible display timings. Two display controllers can also share a single framebuffer, allowing cloned configurations even if modes on two outputs don’t match. A display controller is modelled as a CRTC in KMS terms.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjy?hhubh)}(hOn Tegra186, the number of display controllers has been increased to three. A display controller can no longer drive all of the outputs. While two of these controllers can drive both DSI outputs and both SOR outputs, the third cannot drive any DSI.h]hOn Tegra186, the number of display controllers has been increased to three. A display controller can no longer drive all of the outputs. While two of these controllers can drive both DSI outputs and both SOR outputs, the third cannot drive any DSI.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjy?hhubh)}(hhh](h)}(hWindowsh]hWindows}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhKTubh)}(hXA display controller controls a set of windows that can be used to composite multiple buffers onto the screen. While it is possible to assign arbitrary Z ordering to individual windows (by programming the corresponding blending registers), this is currently not supported by the driver. Instead, it will assume a fixed Z ordering of the windows (window A is the root window, that is, the lowest, while windows B and C are overlaid on top of window A). The overlay windows support multiple pixel formats and can automatically convert from YUV to RGB at scanout time. This makes them useful for displaying video content. In KMS, each window is modelled as a plane. Each display controller has a hardware cursor that is exposed as a cursor plane.h]hXA display controller controls a set of windows that can be used to composite multiple buffers onto the screen. While it is possible to assign arbitrary Z ordering to individual windows (by programming the corresponding blending registers), this is currently not supported by the driver. Instead, it will assume a fixed Z ordering of the windows (window A is the root window, that is, the lowest, while windows B and C are overlaid on top of window A). The overlay windows support multiple pixel formats and can automatically convert from YUV to RGB at scanout time. This makes them useful for displaying video content. In KMS, each window is modelled as a plane. Each display controller has a hardware cursor that is exposed as a cursor plane.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhj?hhubeh}(h]windowsah ]h"]windowsah$]h&]uh1hhjy?hhhhhKTubeh}(h]display-controllersah ]h"]display controllersah$]h&]uh1hhjZ?hhhhhKEubh)}(hhh](h)}(hOutputsh]hOutputs}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhKbubh)}(hX6The type and number of supported outputs varies between Tegra SoC generations. All generations support at least HDMI. While earlier generations supported the very simple RGB interfaces (one per display controller), recent generations no longer do and instead provide standard interfaces such as DSI and eDP/DP.h]hX6The type and number of supported outputs varies between Tegra SoC generations. All generations support at least HDMI. While earlier generations supported the very simple RGB interfaces (one per display controller), recent generations no longer do and instead provide standard interfaces such as DSI and eDP/DP.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhj?hhubh)}(h;Outputs are modelled as a composite encoder/connector pair.h]h;Outputs are modelled as a composite encoder/connector pair.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihj?hhubh)}(hhh](h)}(hRGB/LVDSh]hRGB/LVDS}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhKlubh)}(hwThis interface is no longer available since Tegra124. It has been replaced by the more standard DSI and eDP interfaces.h]hwThis interface is no longer available since Tegra124. It has been replaced by the more standard DSI and eDP interfaces.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhj@hhubeh}(h]rgb-lvdsah ]h"]rgb/lvdsah$]h&]uh1hhj?hhhhhKlubh)}(hhh](h)}(hHDMIh]hHDMI}(hj,@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)@hhhhhKrubh)}(hHDMI is supported on all Tegra SoCs. Starting with Tegra210, HDMI is provided by the versatile SOR output, which supports eDP, DP and HDMI. The SOR is able to support HDMI 2.0, though support for this is currently not merged.h]hHDMI is supported on all Tegra SoCs. Starting with Tegra210, HDMI is provided by the versatile SOR output, which supports eDP, DP and HDMI. The SOR is able to support HDMI 2.0, though support for this is currently not merged.}(hj:@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthj)@hhubeh}(h]hdmiah ]h"]hdmiah$]h&]uh1hhj?hhhhhKrubh)}(hhh](h)}(hDSIh]hDSI}(hjS@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP@hhhhhKyubh)}(hXAlthough Tegra has supported DSI since Tegra30, the controller has changed in several ways in Tegra114. Since none of the publicly available development boards prior to Dalmore (Tegra114) have made use of DSI, only Tegra114 and later are supported by the drm/tegra driver.h]hXAlthough Tegra has supported DSI since Tegra30, the controller has changed in several ways in Tegra114. Since none of the publicly available development boards prior to Dalmore (Tegra114) have made use of DSI, only Tegra114 and later are supported by the drm/tegra driver.}(hja@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjP@hhubeh}(h]dsiah ]h"]dsiah$]h&]uh1hhj?hhhhhKyubh)}(hhh](h)}(heDP/DPh]heDP/DP}(hjz@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjw@hhhhhKubh)}(heDP was first introduced in Tegra124 where it was used to drive the display panel for notebook form factors. Tegra210 added support for full DisplayPort support, though this is currently not implemented in the drm/tegra driver.h]heDP was first introduced in Tegra124 where it was used to drive the display panel for notebook form factors. Tegra210 added support for full DisplayPort support, though this is currently not implemented in the drm/tegra driver.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjw@hhubeh}(h]edp-dpah ]h"]edp/dpah$]h&]uh1hhj?hhhhhKubeh}(h]outputsah ]h"]outputsah$]h&]uh1hhjZ?hhhhhKbubeh}(h] kms-driverah ]h"] kms driverah$]h&]uh1hhhhhhhhK>ubh)}(hhh](h)}(hUserspace Interfaceh]hUserspace Interface}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhKubh)}(hThe userspace interface provided by drm/tegra allows applications to create GEM buffers, access and control syncpoints as well as submit command streams to host1x.h]hThe userspace interface provided by drm/tegra allows applications to create GEM buffers, access and control syncpoints as well as submit command streams to host1x.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubh)}(hhh](h)}(h GEM Buffersh]h GEM Buffers}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhKubh)}(hThe ``DRM_IOCTL_TEGRA_GEM_CREATE`` IOCTL is used to create a GEM buffer object with Tegra-specific flags. This is useful for buffers that should be tiled, or that are to be scanned out upside down (useful for 3D content).h](hThe }(hj@hhhNhNubj)}(h``DRM_IOCTL_TEGRA_GEM_CREATE``h]hDRM_IOCTL_TEGRA_GEM_CREATE}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubh IOCTL is used to create a GEM buffer object with Tegra-specific flags. This is useful for buffers that should be tiled, or that are to be scanned out upside down (useful for 3D content).}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubh)}(hAfter a GEM buffer object has been created, its memory can be mapped by an application using the mmap offset returned by the ``DRM_IOCTL_TEGRA_GEM_MMAP`` IOCTL.h](h}After a GEM buffer object has been created, its memory can be mapped by an application using the mmap offset returned by the }(hj@hhhNhNubj)}(h``DRM_IOCTL_TEGRA_GEM_MMAP``h]hDRM_IOCTL_TEGRA_GEM_MMAP}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubh IOCTL.}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubeh}(h] gem-buffersah ]h"] gem buffersah$]h&]uh1hhj@hhhhhKubh)}(hhh](h)}(h Syncpointsh]h Syncpoints}(hj)AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&AhhhhhKubh)}(hThe current value of a syncpoint can be obtained by executing the ``DRM_IOCTL_TEGRA_SYNCPT_READ`` IOCTL. Incrementing the syncpoint is achieved using the ``DRM_IOCTL_TEGRA_SYNCPT_INCR`` IOCTL.h](hBThe current value of a syncpoint can be obtained by executing the }(hj7AhhhNhNubj)}(h``DRM_IOCTL_TEGRA_SYNCPT_READ``h]hDRM_IOCTL_TEGRA_SYNCPT_READ}(hj?AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7Aubh9 IOCTL. Incrementing the syncpoint is achieved using the }(hj7AhhhNhNubj)}(h``DRM_IOCTL_TEGRA_SYNCPT_INCR``h]hDRM_IOCTL_TEGRA_SYNCPT_INCR}(hjQAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7Aubh IOCTL.}(hj7AhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj&Ahhubh)}(hXUserspace can also request blocking on a syncpoint. To do so, it needs to execute the ``DRM_IOCTL_TEGRA_SYNCPT_WAIT`` IOCTL, specifying the value of the syncpoint to wait for. The kernel will release the application when the syncpoint reaches that value or after a specified timeout.h](hVUserspace can also request blocking on a syncpoint. To do so, it needs to execute the }(hjiAhhhNhNubj)}(h``DRM_IOCTL_TEGRA_SYNCPT_WAIT``h]hDRM_IOCTL_TEGRA_SYNCPT_WAIT}(hjqAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiAubh IOCTL, specifying the value of the syncpoint to wait for. The kernel will release the application when the syncpoint reaches that value or after a specified timeout.}(hjiAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj&Ahhubeh}(h] syncpointsah ]h"] syncpointsah$]h&]uh1hhj@hhhhhKubh)}(hhh](h)}(hCommand Stream Submissionh]hCommand Stream Submission}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhKubh)}(hXBefore an application can submit command streams to host1x it needs to open a channel to an engine using the ``DRM_IOCTL_TEGRA_OPEN_CHANNEL`` IOCTL. Client IDs are used to identify the target of the channel. When a channel is no longer needed, it can be closed using the ``DRM_IOCTL_TEGRA_CLOSE_CHANNEL`` IOCTL. To retrieve the syncpoint associated with a channel, an application can use the ``DRM_IOCTL_TEGRA_GET_SYNCPT``.h](hmBefore an application can submit command streams to host1x it needs to open a channel to an engine using the }(hjAhhhNhNubj)}(h ``DRM_IOCTL_TEGRA_OPEN_CHANNEL``h]hDRM_IOCTL_TEGRA_OPEN_CHANNEL}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh IOCTL. Client IDs are used to identify the target of the channel. When a channel is no longer needed, it can be closed using the }(hjAhhhNhNubj)}(h!``DRM_IOCTL_TEGRA_CLOSE_CHANNEL``h]hDRM_IOCTL_TEGRA_CLOSE_CHANNEL}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubhX IOCTL. To retrieve the syncpoint associated with a channel, an application can use the }(hjAhhhNhNubj)}(h``DRM_IOCTL_TEGRA_GET_SYNCPT``h]hDRM_IOCTL_TEGRA_GET_SYNCPT}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh.}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjAhhubh)}(hX(After opening a channel, submitting command streams is easy. The application writes commands into the memory backing a GEM buffer object and passes these to the ``DRM_IOCTL_TEGRA_SUBMIT`` IOCTL along with various other parameters, such as the syncpoints or relocations used in the job submission.h](hAfter opening a channel, submitting command streams is easy. The application writes commands into the memory backing a GEM buffer object and passes these to the }(hjAhhhNhNubj)}(h``DRM_IOCTL_TEGRA_SUBMIT``h]hDRM_IOCTL_TEGRA_SUBMIT}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubhm IOCTL along with various other parameters, such as the syncpoints or relocations used in the job submission.}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjAhhubeh}(h]command-stream-submissionah ]h"]command stream submissionah$]h&]uh1hhj@hhhhhKubeh}(h]userspace-interfaceah ]h"]userspace interfaceah$]h&]uh1hhhhhhhhKubeh}(h]-drm-tegra-nvidia-tegra-gpu-and-display-driverah ]h"]-drm/tegra nvidia tegra gpu and display driverah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjABerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehʌ _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jBjBjW?jT?j[!jX!jO?jL?j@j@j?j?j?j?j@j@j&@j#@jM@jJ@jt@jq@j@j@jBjBj#Aj AjAjAj BjBu nametypes}(jBjW?j[!jO?j@j?j?j@j&@jM@jt@j@jBj#AjAj Buh}(jBhjT?jZjX!jjjjUjZj{jj0 j5 jr jw j j jxj}jjj#j(jjjjjjjjj(j-j<jAjjjL?j^!j{!j!jg$jl$j%j&j'j'jE)jJ)j,j",jc.jh.j/j/jx1j}1j 3j3jz4j4j6j6j8j8jP:jU:j;j;jT=jY=j@jZ?j?jy?j?j?j@j?j#@j@jJ@j)@jq@jP@j@jw@jBj@j Aj@jAj&AjBjAu footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.