sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/gpu/rfc/i915_schedulermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/gpu/rfc/i915_schedulermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/gpu/rfc/i915_schedulermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/gpu/rfc/i915_schedulermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/gpu/rfc/i915_schedulermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/gpu/rfc/i915_schedulermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h)I915 GuC Submission/DRM Scheduler Sectionh]h)I915 GuC Submission/DRM Scheduler Section}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler.rsthKubh)}(hhh](h)}(h Upstream planh]h Upstream plan}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hlFor upstream the overall plan for landing GuC submission and integrating the i915 with the DRM scheduler is:h]hlFor upstream the overall plan for landing GuC submission and integrating the i915 with the DRM scheduler is:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(hXwMerge basic GuC submission * Basic submission support for all gen11+ platforms * Not enabled by default on any current platforms but can be enabled via modparam enable_guc * Lots of rework will need to be done to integrate with DRM scheduler so no need to nit pick everything in the code, it just should be functional, no major coding style / layering errors, and not regress execlists * Update IGTs / selftests as needed to work with GuC submission * Enable CI on supported platforms for a baseline * Rework / get CI heathly for GuC submission in place as neededh]hdefinition_list)}(hhh]hdefinition_list_item)}(hX;Merge basic GuC submission * Basic submission support for all gen11+ platforms * Not enabled by default on any current platforms but can be enabled via modparam enable_guc * Lots of rework will need to be done to integrate with DRM scheduler so no need to nit pick everything in the code, it just should be functional, no major coding style / layering errors, and not regress execlists * Update IGTs / selftests as needed to work with GuC submission * Enable CI on supported platforms for a baseline * Rework / get CI heathly for GuC submission in place as neededh](hterm)}(hMerge basic GuC submissionh]hMerge basic GuC submission}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubh definition)}(hhh]h)}(hhh](h)}(h1Basic submission support for all gen11+ platformsh]h)}(hjh]h1Basic submission support for all gen11+ platforms}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hZNot enabled by default on any current platforms but can be enabled via modparam enable_guch]h)}(hZNot enabled by default on any current platforms but can be enabled via modparam enable_guch]hZNot enabled by default on any current platforms but can be enabled via modparam enable_guc}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hLots of rework will need to be done to integrate with DRM scheduler so no need to nit pick everything in the code, it just should be functional, no major coding style / layering errors, and not regress execlistsh]h)}(hLots of rework will need to be done to integrate with DRM scheduler so no need to nit pick everything in the code, it just should be functional, no major coding style / layering errors, and not regress execlistsh]hLots of rework will need to be done to integrate with DRM scheduler so no need to nit pick everything in the code, it just should be functional, no major coding style / layering errors, and not regress execlists}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h=Update IGTs / selftests as needed to work with GuC submissionh]h)}(hjOh]h=Update IGTs / selftests as needed to work with GuC submission}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjMubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h/Enable CI on supported platforms for a baselineh]h)}(hjfh]h/Enable CI on supported platforms for a baseline}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h=Rework / get CI heathly for GuC submission in place as neededh]h)}(hj}h]h=Rework / get CI heathly for GuC submission in place as needed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj{ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]bullet*uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubh)}(hXTMerge new parallel submission uAPI * Bonding uAPI completely incompatible with GuC submission, plus it has severe design issues in general, which is why we want to retire it no matter what * New uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step which configures a slot with N contexts * After I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to a slot in a single execbuf IOCTL and the batches run on the GPU in paralllel * Initially only for GuC submission but execlists can be supported if neededh]h)}(hhh]h)}(hXMerge new parallel submission uAPI * Bonding uAPI completely incompatible with GuC submission, plus it has severe design issues in general, which is why we want to retire it no matter what * New uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step which configures a slot with N contexts * After I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to a slot in a single execbuf IOCTL and the batches run on the GPU in paralllel * Initially only for GuC submission but execlists can be supported if neededh](h)}(h"Merge new parallel submission uAPIh]h"Merge new parallel submission uAPI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hhh](h)}(hBonding uAPI completely incompatible with GuC submission, plus it has severe design issues in general, which is why we want to retire it no matter whath]h)}(hBonding uAPI completely incompatible with GuC submission, plus it has severe design issues in general, which is why we want to retire it no matter whath]hBonding uAPI completely incompatible with GuC submission, plus it has severe design issues in general, which is why we want to retire it no matter what}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hjNew uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step which configures a slot with N contextsh]h)}(hjNew uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step which configures a slot with N contextsh]hjNew uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step which configures a slot with N contexts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hAfter I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to a slot in a single execbuf IOCTL and the batches run on the GPU in paralllelh]h)}(hAfter I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to a slot in a single execbuf IOCTL and the batches run on the GPU in paralllelh]hAfter I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to a slot in a single execbuf IOCTL and the batches run on the GPU in paralllel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hJInitially only for GuC submission but execlists can be supported if neededh]h)}(hJInitially only for GuC submission but execlists can be supported if neededh]hJInitially only for GuC submission but execlists can be supported if needed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jjuh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubh)}(hXConvert the i915 to use the DRM scheduler * GuC submission backend fully integrated with DRM scheduler * All request queues removed from backend (e.g. all backpressure handled in DRM scheduler) * Resets / cancels hook in DRM scheduler * Watchdog hooks into DRM scheduler * Lots of complexity of the GuC backend can be pulled out once integrated with DRM scheduler (e.g. state machine gets simpler, locking gets simpler, etc...) * Execlists backend will minimum required to hook in the DRM scheduler * Legacy interface * Features like timeslicing / preemption / virtual engines would be difficult to integrate with the DRM scheduler and these features are not required for GuC submission as the GuC does these things for us * ROI low on fully integrating into DRM scheduler * Fully integrating would add lots of complexity to DRM scheduler * Port i915 priority inheritance / boosting feature in DRM scheduler * Used for i915 page flip, may be useful to other DRM drivers as well * Will be an optional feature in the DRM scheduler * Remove in-order completion assumptions from DRM scheduler * Even when using the DRM scheduler the backends will handle preemption, timeslicing, etc... so it is possible for jobs to finish out of order * Pull out i915 priority levels and use DRM priority levels * Optimize DRM scheduler as needed h]h)}(hhh]h)}(hXConvert the i915 to use the DRM scheduler * GuC submission backend fully integrated with DRM scheduler * All request queues removed from backend (e.g. all backpressure handled in DRM scheduler) * Resets / cancels hook in DRM scheduler * Watchdog hooks into DRM scheduler * Lots of complexity of the GuC backend can be pulled out once integrated with DRM scheduler (e.g. state machine gets simpler, locking gets simpler, etc...) * Execlists backend will minimum required to hook in the DRM scheduler * Legacy interface * Features like timeslicing / preemption / virtual engines would be difficult to integrate with the DRM scheduler and these features are not required for GuC submission as the GuC does these things for us * ROI low on fully integrating into DRM scheduler * Fully integrating would add lots of complexity to DRM scheduler * Port i915 priority inheritance / boosting feature in DRM scheduler * Used for i915 page flip, may be useful to other DRM drivers as well * Will be an optional feature in the DRM scheduler * Remove in-order completion assumptions from DRM scheduler * Even when using the DRM scheduler the backends will handle preemption, timeslicing, etc... so it is possible for jobs to finish out of order * Pull out i915 priority levels and use DRM priority levels * Optimize DRM scheduler as needed h](h)}(h)Convert the i915 to use the DRM schedulerh]h)Convert the i915 to use the DRM scheduler}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjVubh)}(hhh]h)}(hhh](h)}(hXGuC submission backend fully integrated with DRM scheduler * All request queues removed from backend (e.g. all backpressure handled in DRM scheduler) * Resets / cancels hook in DRM scheduler * Watchdog hooks into DRM scheduler * Lots of complexity of the GuC backend can be pulled out once integrated with DRM scheduler (e.g. state machine gets simpler, locking gets simpler, etc...)h]h)}(hhh]h)}(hXGuC submission backend fully integrated with DRM scheduler * All request queues removed from backend (e.g. all backpressure handled in DRM scheduler) * Resets / cancels hook in DRM scheduler * Watchdog hooks into DRM scheduler * Lots of complexity of the GuC backend can be pulled out once integrated with DRM scheduler (e.g. state machine gets simpler, locking gets simpler, etc...)h](h)}(h:GuC submission backend fully integrated with DRM schedulerh]h:GuC submission backend fully integrated with DRM scheduler}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjuubh)}(hhh]h)}(hhh](h)}(hXAll request queues removed from backend (e.g. all backpressure handled in DRM scheduler)h]h)}(hXAll request queues removed from backend (e.g. all backpressure handled in DRM scheduler)h]hXAll request queues removed from backend (e.g. all backpressure handled in DRM scheduler)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h&Resets / cancels hook in DRM schedulerh]h)}(hjh]h&Resets / cancels hook in DRM scheduler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h!Watchdog hooks into DRM schedulerh]h)}(hjh]h!Watchdog hooks into DRM scheduler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hLots of complexity of the GuC backend can be pulled out once integrated with DRM scheduler (e.g. state machine gets simpler, locking gets simpler, etc...)h]h)}(hLots of complexity of the GuC backend can be pulled out once integrated with DRM scheduler (e.g. state machine gets simpler, locking gets simpler, etc...)h]hLots of complexity of the GuC backend can be pulled out once integrated with DRM scheduler (e.g. state machine gets simpler, locking gets simpler, etc...)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jjuh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1hhjuubeh}(h]h ]h"]h$]h&]uh1hhhhK'hjrubah}(h]h ]h"]h$]h&]uh1hhjnubah}(h]h ]h"]h$]h&]uh1hhjkubh)}(hXExeclists backend will minimum required to hook in the DRM scheduler * Legacy interface * Features like timeslicing / preemption / virtual engines would be difficult to integrate with the DRM scheduler and these features are not required for GuC submission as the GuC does these things for us * ROI low on fully integrating into DRM scheduler * Fully integrating would add lots of complexity to DRM schedulerh]h)}(hhh]h)}(hXExeclists backend will minimum required to hook in the DRM scheduler * Legacy interface * Features like timeslicing / preemption / virtual engines would be difficult to integrate with the DRM scheduler and these features are not required for GuC submission as the GuC does these things for us * ROI low on fully integrating into DRM scheduler * Fully integrating would add lots of complexity to DRM schedulerh](h)}(hDExeclists backend will minimum required to hook in the DRM schedulerh]hDExeclists backend will minimum required to hook in the DRM scheduler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubh)}(hhh]h)}(hhh](h)}(hLegacy interfaceh]h)}(hj*h]hLegacy interface}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hj(ubah}(h]h ]h"]h$]h&]uh1hhj%ubh)}(hFeatures like timeslicing / preemption / virtual engines would be difficult to integrate with the DRM scheduler and these features are not required for GuC submission as the GuC does these things for ush]h)}(hFeatures like timeslicing / preemption / virtual engines would be difficult to integrate with the DRM scheduler and these features are not required for GuC submission as the GuC does these things for ush]hFeatures like timeslicing / preemption / virtual engines would be difficult to integrate with the DRM scheduler and these features are not required for GuC submission as the GuC does these things for us}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hj?ubah}(h]h ]h"]h$]h&]uh1hhj%ubh)}(h/ROI low on fully integrating into DRM schedulerh]h)}(hjYh]h/ROI low on fully integrating into DRM scheduler}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjWubah}(h]h ]h"]h$]h&]uh1hhj%ubh)}(h?Fully integrating would add lots of complexity to DRM schedulerh]h)}(h?Fully integrating would add lots of complexity to DRM schedulerh]h?Fully integrating would add lots of complexity to DRM scheduler}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjnubah}(h]h ]h"]h$]h&]uh1hhj%ubeh}(h]h ]h"]h$]h&]jjuh1hhhhK*hj"ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK0hj ubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhjkubh)}(hPort i915 priority inheritance / boosting feature in DRM scheduler * Used for i915 page flip, may be useful to other DRM drivers as well * Will be an optional feature in the DRM schedulerh]h)}(hhh]h)}(hPort i915 priority inheritance / boosting feature in DRM scheduler * Used for i915 page flip, may be useful to other DRM drivers as well * Will be an optional feature in the DRM schedulerh](h)}(hBPort i915 priority inheritance / boosting feature in DRM schedulerh]hBPort i915 priority inheritance / boosting feature in DRM scheduler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubh)}(hhh]h)}(hhh](h)}(hCUsed for i915 page flip, may be useful to other DRM drivers as wellh]h)}(hCUsed for i915 page flip, may be useful to other DRM drivers as wellh]hCUsed for i915 page flip, may be useful to other DRM drivers as well}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h0Will be an optional feature in the DRM schedulerh]h)}(hjh]h0Will be an optional feature in the DRM scheduler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jjuh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK4hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjkubh)}(hRemove in-order completion assumptions from DRM scheduler * Even when using the DRM scheduler the backends will handle preemption, timeslicing, etc... so it is possible for jobs to finish out of orderh]h)}(hhh]h)}(hRemove in-order completion assumptions from DRM scheduler * Even when using the DRM scheduler the backends will handle preemption, timeslicing, etc... so it is possible for jobs to finish out of orderh](h)}(h9Remove in-order completion assumptions from DRM schedulerh]h9Remove in-order completion assumptions from DRM scheduler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubh)}(hhh]h)}(hhh]h)}(hEven when using the DRM scheduler the backends will handle preemption, timeslicing, etc... so it is possible for jobs to finish out of orderh]h)}(hEven when using the DRM scheduler the backends will handle preemption, timeslicing, etc... so it is possible for jobs to finish out of orderh]hEven when using the DRM scheduler the backends will handle preemption, timeslicing, etc... so it is possible for jobs to finish out of order}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hj/ubah}(h]h ]h"]h$]h&]uh1hhj,ubah}(h]h ]h"]h$]h&]jjuh1hhhhK7hj)ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjkubh)}(h9Pull out i915 priority levels and use DRM priority levelsh]h)}(hjgh]h9Pull out i915 priority levels and use DRM priority levels}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjeubah}(h]h ]h"]h$]h&]uh1hhjkubh)}(h!Optimize DRM scheduler as needed h]h)}(h Optimize DRM scheduler as neededh]h Optimize DRM scheduler as needed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hj|ubah}(h]h ]h"]h$]h&]uh1hhjkubeh}(h]h ]h"]h$]h&]jjuh1hhhhK!hjhubah}(h]h ]h"]h$]h&]uh1hhjVubeh}(h]h ]h"]h$]h&]uh1hhhhK;hjSubah}(h]h ]h"]h$]h&]uh1hhjOubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhK hhhhubeh}(h] upstream-planah ]h"] upstream planah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h!TODOs for GuC submission upstreamh]h!TODOs for GuC submission upstream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK>ubh)}(hhh](h)}(hCNeed an update to GuC firmware / i915 to enable error state captureh]h)}(hjh]hCNeed an update to GuC firmware / i915 to enable error state capture}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h#Open source tool to decode GuC logsh]h)}(hjh]h#Open source tool to decode GuC logs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hPublic GuC spec h]h)}(hPublic GuC spech]hPublic GuC spec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhK@hjhhubeh}(h]!todos-for-guc-submission-upstreamah ]h"]!todos for guc submission upstreamah$]h&]uh1hhhhhhhhK>ubh)}(hhh](h)}(h!New uAPI for basic GuC submissionh]h!New uAPI for basic GuC submission}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhKEubh)}(hXNo major changes are required to the uAPI for basic GuC submission. The only change is a new scheduler attribute: I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP. This attribute indicates the 2k i915 user priority levels are statically mapped into 3 levels as follows:h]hXNo major changes are required to the uAPI for basic GuC submission. The only change is a new scheduler attribute: I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP. This attribute indicates the 2k i915 user priority levels are statically mapped into 3 levels as follows:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhj(hhubh)}(hhh](h)}(h-1k to -1 Low priorityh]h)}(hjLh]h-1k to -1 Low priority}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjJubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubh)}(h0 Medium priorityh]h)}(hjch]h0 Medium priority}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjaubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubh)}(h1 to 1k High priority h]h)}(h1 to 1k High priorityh]h1 to 1k High priority}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjxubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKKhj(hhubh)}(hThis is needed because the GuC only has 4 priority bands. The highest priority band is reserved with the kernel. This aligns with the DRM scheduler priority levels too.h]hThis is needed because the GuC only has 4 priority bands. The highest priority band is reserved with the kernel. This aligns with the DRM scheduler priority levels too.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhj(hhubh)}(hhh](h)}(hSpec references:h]hSpec references:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKTubh)}(hhh](h)}(hPhttps://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txth]h)}(hjh]h reference)}(hjh]hPhttps://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hchttps://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/chap5.html#devsandqueues-priorityh]h)}(hjh]j)}(hjh]hchttps://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/chap5.html#devsandqueues-priority}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hThttps://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priority-t h]h)}(hShttps://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priority-th]j)}(hjh]hShttps://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priority-t}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKUhjhhubeh}(h]spec-referencesah ]h"]spec references:ah$]h&]uh1hhj(hhhhhKTubeh}(h]!new-uapi-for-basic-guc-submissionah ]h"]!new uapi for basic guc submissionah$]h&]uh1hhhhhhhhKEubh)}(hhh](h)}(hNew parallel submission uAPIh]hNew parallel submission uAPI}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhKZubh)}(hXThe existing bonding uAPI is completely broken with GuC submission because whether a submission is a single context submit or parallel submit isn't known until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple contexts in parallel with the GuC the context must be explicitly registered with N contexts and all N contexts must be submitted in a single command to the GuC. The GuC interfaces do not support dynamically changing between N contexts as the bonding uAPI does. Hence the need for a new parallel submission interface. Also the legacy bonding uAPI is quite confusing and not intuitive at all. Furthermore I915_SUBMIT_FENCE is by design a future fence, so not really something we should continue to support.h]hXThe existing bonding uAPI is completely broken with GuC submission because whether a submission is a single context submit or parallel submit isn’t known until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple contexts in parallel with the GuC the context must be explicitly registered with N contexts and all N contexts must be submitted in a single command to the GuC. The GuC interfaces do not support dynamically changing between N contexts as the bonding uAPI does. Hence the need for a new parallel submission interface. Also the legacy bonding uAPI is quite confusing and not intuitive at all. Furthermore I915_SUBMIT_FENCE is by design a future fence, so not really something we should continue to support.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hj4hhubh)}(h5The new parallel submission uAPI consists of 3 parts:h]h5The new parallel submission uAPI consists of 3 parts:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhj4hhubh)}(hhh](h)}(hExport engines logical mappingh]h)}(hjfh]hExport engines logical mapping}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjdubah}(h]h ]h"]h$]h&]uh1hhjahhhhhNubh)}(hHA 'set_parallel' extension to configure contexts for parallel submissionh]h)}(hHA 'set_parallel' extension to configure contexts for parallel submissionh]hLA ‘set_parallel’ extension to configure contexts for parallel submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihj{ubah}(h]h ]h"]h$]h&]uh1hhjahhhhhNubh)}(hDExtend execbuf2 IOCTL to support submitting N BBs in a single IOCTL h]h)}(hCExtend execbuf2 IOCTL to support submitting N BBs in a single IOCTLh]hCExtend execbuf2 IOCTL to support submitting N BBs in a single IOCTL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjubah}(h]h ]h"]h$]h&]uh1hhjahhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKhhj4hhubh)}(hhh](h)}(hExport engines logical mappingh]hExport engines logical mapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKnubh)}(hXCertain use cases require BBs to be placed on engine instances in logical order (e.g. split-frame on gen11+). The logical mapping of engine instances can change based on fusing. Rather than making UMDs be aware of fusing, simply expose the logical mapping with the existing query engine info IOCTL. Also the GuC submission interface currently only supports submitting multiple contexts to engines in logical order which is a new requirement compared to execlists. Lastly, all current platforms have at most 2 engine instances and the logical order is the same as uAPI order. This will change on platforms with more than 2 engine instances.h]hXCertain use cases require BBs to be placed on engine instances in logical order (e.g. split-frame on gen11+). The logical mapping of engine instances can change based on fusing. Rather than making UMDs be aware of fusing, simply expose the logical mapping with the existing query engine info IOCTL. Also the GuC submission interface currently only supports submitting multiple contexts to engines in logical order which is a new requirement compared to execlists. Lastly, all current platforms have at most 2 engine instances and the logical order is the same as uAPI order. This will change on platforms with more than 2 engine instances.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjhhubh)}(hA single bit will be added to drm_i915_engine_info.flags indicating that the logical instance has been returned and a new field, drm_i915_engine_info.logical_instance, returns the logical instance.h]hA single bit will be added to drm_i915_engine_info.flags indicating that the logical instance has been returned and a new field, drm_i915_engine_info.logical_instance, returns the logical instance.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjhhubeh}(h]export-engines-logical-mappingah ]h"]export engines logical mappingah$]h&]uh1hhj4hhhhhKnubh)}(hhh](h)}(hHA 'set_parallel' extension to configure contexts for parallel submissionh]hLA ‘set_parallel’ extension to configure contexts for parallel submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK~ubh)}(hXThe 'set_parallel' extension configures a slot for parallel submission of N BBs. It is a setup step that must be called before using any of the contexts. See I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for similar existing examples. Once a slot is configured for parallel submission the execbuf2 IOCTL can be called submitting N BBs in a single IOCTL. Initially only supports GuC submission. Execlists supports can be added later if needed.h]hXThe ‘set_parallel’ extension configures a slot for parallel submission of N BBs. It is a setup step that must be called before using any of the contexts. See I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for similar existing examples. Once a slot is configured for parallel submission the execbuf2 IOCTL can be called submitting N BBs in a single IOCTL. Initially only supports GuC submission. Execlists supports can be added later if needed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hAdd I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and drm_i915_context_engines_parallel_submit to the uAPI to implement this extension.h]hAdd I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and drm_i915_context_engines_parallel_submit to the uAPI to implement this extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single3rfc.i915_context_engines_parallel_submit (C struct)*c.rfc.i915_context_engines_parallel_submithNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(h$i915_context_engines_parallel_submith]hdesc_signature_line)}(h+struct i915_context_engines_parallel_submith](hdesc_sig_keyword)}(hstructh]hstruct}(hj7hhhNhNubah}(h]h ]kah"]h$]h&]uh1j5hj1hhhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhKubhdesc_sig_space)}(h h]h }(hjIhhhNhNubah}(h]h ]wah"]h$]h&]uh1jGhj1hhhjFhKubh desc_name)}(h$i915_context_engines_parallel_submith]h desc_sig_name)}(hj-h]h$i915_context_engines_parallel_submit}(hj`hhhNhNubah}(h]h ]nah"]h$]h&]uh1j^hjZubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jXhj1hhhjFhKubeh}(h]h ]h"]h$]h&]jvjw add_permalinkuh1j/sphinx_line_type declaratorhj+hhhjFhKubah}(h]j"ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j)hjFhKhj&hhubh desc_content)}(hhh]h)}(h)Configure engine for parallel submission.h]h)Configure engine for parallel submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhML hjhhubah}(h]h ]h"]h$]h&]uh1jhj&hhhjFhKubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j$hhhjhNhNubh container)}(hX**Definition**:: struct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; }; **Members** ``base`` base user extension. ``engine_index`` slot for parallel engine ``width`` number of contexts per parallel engine or in other words the number of batches in each submission ``num_siblings`` number of siblings per context or in other words the number of possible placements for each submission ``mbz16`` reserved for future use; must be zero ``flags`` all undefined flags must be zero, currently not defined flags ``mbz64`` reserved for future use; must be zero ``engines`` 2-d array of engine instances to configure parallel engine length = width (i) * num_siblings (j) index = j + i * num_siblingsh](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhMP hjubh literal_block)}(hstruct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; };h]hstruct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; };}hjsbah}(h]h ]h"]h$]h&]jvjwuh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhMR hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM] hjubh)}(hhh](h)}(h``base`` base user extension. h](h)}(h``base``h]hliteral)}(hj h]hbase}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hjubh)}(hhh]h)}(hbase user extension.h]hbase user extension.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj#ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhj"hM hjubh)}(h*``engine_index`` slot for parallel engine h](h)}(h``engine_index``h]j)}(hjFh]h engine_index}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjDubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hj@ubh)}(hhh]h)}(hslot for parallel engineh]hslot for parallel engine}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hM hj\ubah}(h]h ]h"]h$]h&]uh1hhj@ubeh}(h]h ]h"]h$]h&]uh1hhj[hM hjubh)}(hl``width`` number of contexts per parallel engine or in other words the number of batches in each submission h](h)}(h ``width``h]j)}(hjh]hwidth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj}ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hjyubh)}(hhh]h)}(hanumber of contexts per parallel engine or in other words the number of batches in each submissionh]hanumber of contexts per parallel engine or in other words the number of batches in each submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hjubah}(h]h ]h"]h$]h&]uh1hhjyubeh}(h]h ]h"]h$]h&]uh1hhjhM hjubh)}(hx``num_siblings`` number of siblings per context or in other words the number of possible placements for each submission h](h)}(h``num_siblings``h]j)}(hjh]h num_siblings}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hjubh)}(hhh]h)}(hfnumber of siblings per context or in other words the number of possible placements for each submissionh]hfnumber of siblings per context or in other words the number of possible placements for each submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjhM hjubh)}(h0``mbz16`` reserved for future use; must be zero h](h)}(h ``mbz16``h]j)}(hjh]hmbz16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hjubh)}(hhh]h)}(h%reserved for future use; must be zeroh]h%reserved for future use; must be zero}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhj hM hjubh)}(hH``flags`` all undefined flags must be zero, currently not defined flags h](h)}(h ``flags``h]j)}(hj, h]hflags}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj* ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hj& ubh)}(hhh]h)}(h=all undefined flags must be zero, currently not defined flagsh]h=all undefined flags must be zero, currently not defined flags}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjA hM hjB ubah}(h]h ]h"]h$]h&]uh1hhj& ubeh}(h]h ]h"]h$]h&]uh1hhjA hM hjubh)}(h0``mbz64`` reserved for future use; must be zero h](h)}(h ``mbz64``h]j)}(hje h]hmbz64}(hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjc ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hj_ ubh)}(hhh]h)}(h%reserved for future use; must be zeroh]h%reserved for future use; must be zero}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjz hM hj{ ubah}(h]h ]h"]h$]h&]uh1hhj_ ubeh}(h]h ]h"]h$]h&]uh1hhjz hM hjubh)}(h``engines`` 2-d array of engine instances to configure parallel engine length = width (i) * num_siblings (j) index = j + i * num_siblingsh](h)}(h ``engines``h]j)}(hj h]hengines}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hj ubh)}(hhh](h)}(h:2-d array of engine instances to configure parallel engineh]h:2-d array of engine instances to configure parallel engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hj ubh)}(hBlength = width (i) * num_siblings (j) index = j + i * num_siblingsh]hBlength = width (i) * num_siblings (j) index = j + i * num_siblings}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubeh}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhj hM hjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM hjhhubh)}(hXOSetup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot's configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.h]hXSSetup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn’t tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot’s configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhMM hjhhubh)}(hX9The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.h]hX9The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhMV hjhhubh)}(hReturns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn't supported on the platform / submission interface. Returns -ENODEV if extension isn't supported on the platform / submission interface.h]hReturns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn’t supported on the platform / submission interface. Returns -ENODEV if extension isn’t supported on the platform / submission interface.}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhM_ hjhhubj)}(hX3Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1]) Results in the following valid placement: CS[0], CS[1] Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3]) Results in the following valid placements: CS[0], CS[1] CS[2], CS[3] This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3] Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3]) Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVALh]hX3Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1]) Results in the following valid placement: CS[0], CS[1] Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3]) Results in the following valid placements: CS[0], CS[1] CS[2], CS[3] This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3] Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3]) Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVAL}hj2 sbah}(h]h ]h"]h$]h&]jvjwforcelanguagenonehighlight_args}uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/rfc/i915_scheduler:140: ./include/uapi/drm/i915_drm.hhMe hjhhubeh}(h]Fa-set-parallel-extension-to-configure-contexts-for-parallel-submissionah ]h"]Ha 'set_parallel' extension to configure contexts for parallel submissionah$]h&]uh1hhj4hhhhhK~ubh)}(hhh](h)}(hCExtend execbuf2 IOCTL to support submitting N BBs in a single IOCTLh]hCExtend execbuf2 IOCTL to support submitting N BBs in a single IOCTL}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjN hhhhhKubh)}(hXContexts that have been configured with the 'set_parallel' extension can only submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N objects in the drm_i915_gem_exec_object2 list or the first N if I915_EXEC_BATCH_FIRST is set. The number of BBs is implicit based on the slot submitted and how it has been configured by 'set_parallel' or other extensions. No uAPI changes are required to the execbuf2 IOCTL.h]hXContexts that have been configured with the ‘set_parallel’ extension can only submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N objects in the drm_i915_gem_exec_object2 list or the first N if I915_EXEC_BATCH_FIRST is set. The number of BBs is implicit based on the slot submitted and how it has been configured by ‘set_parallel’ or other extensions. No uAPI changes are required to the execbuf2 IOCTL.}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjN hhubeh}(h]Cextend-execbuf2-ioctl-to-support-submitting-n-bbs-in-a-single-ioctlah ]h"]Cextend execbuf2 ioctl to support submitting n bbs in a single ioctlah$]h&]uh1hhj4hhhhhKubeh}(h]new-parallel-submission-uapiah ]h"]new parallel submission uapiah$]h&]uh1hhhhhhhhKZubeh}(h])i915-guc-submission-drm-scheduler-sectionah ]h"])i915 guc submission/drm scheduler sectionah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j j jjj%j"j1j.j)j&jz jw jjjK jH jr jo u nametypes}(j jj%j1j)jz jjK jr uh}(j hjhj"jj.j(j&jjw j4jjjH jj"j+jo jN u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.