Jsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/gpu/nova/core/todomodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)h]h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/gpu/nova/core/todo.rsthKubhsection)}(hhh](htitle)}(h Task Listh]h Task List}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h$Tasks may have the following fields:h]h$Tasks may have the following fields:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(h``Complexity``: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.h]h)}(h``Complexity``: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.h](hliteral)}(h``Complexity``h]h Complexity}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, }(hhhhhNhNubh)}(h ``Beginner``h]hBeginner}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh, }(hhhhhNhNubh)}(h``Intermediate``h]h Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh, }hhsbh)}(h ``Advanced``h]hAdvanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh and }(hhhhhNhNubh)}(h ``Expert``h]hExpert}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h)``Reference``: References to other tasks.h]h)}(hjRh](h)}(h ``Reference``h]h Reference}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubh: References to other tasks.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjPubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h&``Link``: Links to external resources.h]h)}(hjwh](h)}(h``Link``h]hLink}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyubh: Links to external resources.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjuubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hV``Contact``: The person that can be contacted for further information about the task. h]h)}(hU``Contact``: The person that can be contacted for further information about the task.h](h)}(h ``Contact``h]hContact}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhJ: The person that can be contacted for further information about the task.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK hhhhubh)}(h}A task might have `[ABCD]` code after its name. This code can be used to grep into the code for `TODO` entries related to it.h](hA task might have }(hjhhhNhNubhtitle_reference)}(h`[ABCD]`h]h[ABCD]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhF code after its name. This code can be used to grep into the code for }(hjhhhNhNubj)}(h`TODO`h]hTODO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh entries related to it.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hEnablement (Rust)h]hEnablement (Rust)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hbTasks that are not directly related to nova-core, but are preconditions in terms of required APIs.h]hbTasks that are not directly related to nova-core, but are preconditions in terms of required APIs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hFromPrimitive API [FPRI]h]hFromPrimitive API [FPRI]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hSSometimes the need arises to convert a number to a value of an enum or a structure.h]hSSometimes the need arises to convert a number to a value of an enum or a structure.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXoA good example from nova-core would be the ``Chipset`` enum type, which defines the value ``AD102``. When probing the GPU the value ``0x192`` can be read from a certain register indication the chipset AD102. Hence, the enum value ``AD102`` should be derived from the number ``0x192``. Currently, nova-core uses a custom implementation (``Chipset::from_u32`` for this.h](h+A good example from nova-core would be the }(hj:hhhNhNubh)}(h ``Chipset``h]hChipset}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh$ enum type, which defines the value }(hj:hhhNhNubh)}(h ``AD102``h]hAD102}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh!. When probing the GPU the value }(hj:hhhNhNubh)}(h ``0x192``h]h0x192}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubhY can be read from a certain register indication the chipset AD102. Hence, the enum value }(hj:hhhNhNubh)}(h ``AD102``h]hAD102}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh# should be derived from the number }(hj:hhhNhNubh)}(h ``0x192``h]h0x192}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh5. Currently, nova-core uses a custom implementation (}(hj:hhhNhNubh)}(h``Chipset::from_u32``h]hChipset::from_u32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh for this.}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjhhubh)}(hiInstead, it would be desirable to have something like the ``FromPrimitive`` trait [1] from the num crate.h](h:Instead, it would be desirable to have something like the }(hjhhhNhNubh)}(h``FromPrimitive``h]h FromPrimitive}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh trait [1] from the num crate.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubh)}(hHaving this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number.h]hHaving this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjhhubh line_block)}(hhh](hh)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hindentKhjhhhhhK,ubj)}(h=Link: https://docs.rs/num/latest/num/trait.FromPrimitive.htmlh](hLink: }(hjhhhNhNubh reference)}(h7https://docs.rs/num/latest/num/trait.FromPrimitive.htmlh]h7https://docs.rs/num/latest/num/trait.FromPrimitive.html}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhK-ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhK,ubeh}(h]fromprimitive-api-fpriah ]h"]fromprimitive api [fpri]ah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hCConversion from byte slices for types implementing FromBytes [TRSM]h]hCConversion from byte slices for types implementing FromBytes [TRSM]}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhK0ubh)}(hX We retrieve several structures from byte streams coming from the BIOS or loaded firmware. At the moment converting the bytes slice into the proper type require an inelegant `unsafe` operation; this will go away once `FromBytes` implements a proper `from_bytes` method.h](hWe retrieve several structures from byte streams coming from the BIOS or loaded firmware. At the moment converting the bytes slice into the proper type require an inelegant }(hj5hhhNhNubj)}(h`unsafe`h]hunsafe}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh# operation; this will go away once }(hj5hhhNhNubj)}(h `FromBytes`h]h FromBytes}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh implements a proper }(hj5hhhNhNubj)}(h `from_bytes`h]h from_bytes}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh method.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK2hj$hhubj)}(hhh]j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjyhhhhhK7ubah}(h]h ]h"]h$]h&]uh1jhj$hhhhhK7ubeh}(h]Aconversion-from-byte-slices-for-types-implementing-frombytes-trsmah ]h"]Cconversion from byte slices for types implementing frombytes [trsm]ah$]h&]uh1hhjhhhhhK0ubh)}(hhh](h)}(h&CoherentAllocation improvements [COHA]h]h&CoherentAllocation improvements [COHA]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK:ubh)}(ho`CoherentAllocation` needs a safe way to write into the allocation, and to obtain slices within the allocation.h](j)}(h`CoherentAllocation`h]hCoherentAllocation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh[ needs a safe way to write into the allocation, and to obtain slices within the allocation.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK, Fields [ MINOR_REVISION(3:0, RO), MAJOR_REVISION(7:4, RO), REVISION(7:0, RO), // Virtual register combining major and minor rev. ])h]hregister!(BOOT0, 0x0, u32, pci::Bar, Fields [ MINOR_REVISION(3:0, RO), MAJOR_REVISION(7:4, RO), REVISION(7:0, RO), // Virtual register combining major and minor rev. ])}hj!sbah}(h]h ]h"]h$]h&]hhforcelanguagerusthighlight_args}uh1jhhhKJhjhhubh)}(h$This could expand to something like:h]h$This could expand to something like:}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjhhubj )}(hXconst BOOT0_OFFSET: usize = 0x00000000; const BOOT0_MINOR_REVISION_SHIFT: u8 = 0; const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f; const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4; const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0; const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT; const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK | BOOT0_MAJOR_REVISION_MASK; struct Boot0(u32); impl Boot0 { #[inline] fn read(bar: &RevocableGuard<'_, pci::Bar>) -> Self { Self(bar.readl(BOOT0_OFFSET)) } #[inline] fn minor_revision(&self) -> u32 { (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT } #[inline] fn major_revision(&self) -> u32 { (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT } #[inline] fn revision(&self) -> u32 { (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT } }h]hXconst BOOT0_OFFSET: usize = 0x00000000; const BOOT0_MINOR_REVISION_SHIFT: u8 = 0; const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f; const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4; const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0; const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT; const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK | BOOT0_MAJOR_REVISION_MASK; struct Boot0(u32); impl Boot0 { #[inline] fn read(bar: &RevocableGuard<'_, pci::Bar>) -> Self { Self(bar.readl(BOOT0_OFFSET)) } #[inline] fn minor_revision(&self) -> u32 { (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT } #[inline] fn major_revision(&self) -> u32 { (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT } #[inline] fn revision(&self) -> u32 { (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT } }}hjBsbah}(h]h ]h"]h$]h&]hhj/j0rustj2}uh1jhhhKThjhhubh)}(hUsage:h]hUsage:}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjhhubj )}(hwlet bar = bar.try_access().ok_or(ENXIO)?; let boot0 = Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision());h]hwlet bar = bar.try_access().ok_or(ENXIO)?; let boot0 = Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision());}hj`sbah}(h]h ]h"]h$]h&]hhj/j0rustj2}uh1jhhhKxhjhhubh)}(hXA work-in-progress implementation currently resides in `drivers/gpu/nova-core/regs/macros.rs` and is used in nova-core. It would be nice to improve it (possibly using proc macros) and move it to the `kernel` crate so it can be used by other components as well.h](h7A work-in-progress implementation currently resides in }(hjphhhNhNubj)}(h&`drivers/gpu/nova-core/regs/macros.rs`h]h$drivers/gpu/nova-core/regs/macros.rs}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubhj and is used in nova-core. It would be nice to improve it (possibly using proc macros) and move it to the }(hjphhhNhNubj)}(h`kernel`h]hkernel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubh5 crate so it can be used by other components as well.}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h%Features desired before this happens:h]h%Features desired before this happens:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(h@Make I/O optional I/O (for field values that are not registers),h]h)}(hjh]h@Make I/O optional I/O (for field values that are not registers),}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hSupport other sizes than `u32`,h]h)}(hjh](hSupport other sizes than }(hjhhhNhNubj)}(h`u32`h]hu32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh,}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h=Allow visibility control for registers and individual fields,h]h)}(hjh]h=Allow visibility control for registers and individual fields,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h0Use Rust slice syntax to express fields ranges. h]h)}(h/Use Rust slice syntax to express fields ranges.h]h/Use Rust slice syntax to express fields ranges.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j*uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj)hhhhhKubj)}(hContact: Alexandre Courboth]hContact: Alexandre Courbot}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj)hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]!generic-register-abstraction-regaah ]h"]#generic register abstraction [rega]ah$]h&]uh1hhjhhhhhKCubh)}(hhh](h)}(hNumerical operations [NUMM]h]hNumerical operations [NUMM]}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhhhhhKubh)}(hNova uses integer operations that are not part of the standard library (or not implemented in an optimized way for the kernel). These include:h]hNova uses integer operations that are not part of the standard library (or not implemented in an optimized way for the kernel). These include:}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjVhhubh)}(hhh]h)}(hPThe "Find Last Set Bit" (`fls` function of the C part of the kernel) operation. h]h)}(hOThe "Find Last Set Bit" (`fls` function of the C part of the kernel) operation.h](hThe “Find Last Set Bit” (}(hj|hhhNhNubj)}(h`fls`h]hfls}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh1 function of the C part of the kernel) operation.}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjxubah}(h]h ]h"]h$]h&]uh1hhjuhhhhhNubah}(h]h ]h"]h$]h&]jjuh1hhhhKhjVhhubh)}(hIA `num` core kernel module is being designed to provide these operations.h](hA }(hjhhhNhNubj)}(h`num`h]hnum}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhB core kernel module is being designed to provide these operations.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjVhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Alexandre Courboth]hContact: Alexandre Courbot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjVhhhhhKubeh}(h]numerical-operations-nummah ]h"]numerical operations [numm]ah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h!Delay / Sleep abstractions [DLAY]h]h!Delay / Sleep abstractions [DLAY]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hARust abstractions for the kernel's delay() and sleep() functions.h]hCRust abstractions for the kernel’s delay() and sleep() functions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h_FUJITA Tomonori plans to work on abstractions for read_poll_timeout_atomic() (and friends) [1].h]h_FUJITA Tomonori plans to work on abstractions for read_poll_timeout_atomic() (and friends) [1].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj"hhhhhKubj)}(hfLink: https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/ [1]h](hLink: }(hj3hhhNhNubj)}(h\https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/h]h\https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/}(hj;hhhNhNubah}(h]h ]h"]h$]h&]refurij=uh1jhj3ubh [1]}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhj"hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]delay-sleep-abstractions-dlayah ]h"]!delay / sleep abstractions [dlay]ah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hIRQ abstractionsh]hIRQ abstractions}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhhhhhKubh)}(h#Rust abstractions for IRQ handling.h]h#Rust abstractions for IRQ handling.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjbhhubh)}(haThere is active ongoing work from Daniel Almeida [1] for the "core" abstractions to request IRQs.h]heThere is active ongoing work from Daniel Almeida [1] for the “core” abstractions to request IRQs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjbhhubh)}(hBesides optional review and testing work, the required ``pci::Device`` code around those core abstractions needs to be worked out.h](h7Besides optional review and testing work, the required }(hjhhhNhNubh)}(h``pci::Device``h]h pci::Device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh< code around those core abstractions needs to be worked out.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjbhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(h[Link: https://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/ [1]h](hLink: }(hjhhhNhNubj)}(hQhttps://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/h]hQhttps://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubh [1]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Daniel Almeidah]hContact: Daniel Almeida}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjbhhhhhKubeh}(h]irq-abstractionsah ]h"]irq abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h"Page abstraction for foreign pagesh]h"Page abstraction for foreign pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h^Rust abstractions for pages not created by the Rust page abstraction without direct ownership.h]h^Rust abstractions for pages not created by the Rust page abstraction without direct ownership.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hBThere is active onging work from Abdiel Janulgue [1] and Lina [2].h]hBThere is active onging work from Abdiel Janulgue [1] and Lina [2].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj*hhhhhKubj)}(h]Link: https://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/ [1]h](hLink: }(hj;hhhNhNubj)}(hShttps://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/h]hShttps://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/}(hjChhhNhNubah}(h]h ]h"]h$]h&]refurijEuh1jhj;ubh [1]}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhj*hhhhhKubj)}(hdLink: https://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/ [2]h](hLink: }(hj\hhhNhNubj)}(hZhttps://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/h]hZhttps://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/}(hjdhhhNhNubah}(h]h ]h"]h$]h&]refurijfuh1jhj\ubh [2]}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhj*hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]"page-abstraction-for-foreign-pagesah ]h"]"page abstraction for foreign pagesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h#Scatterlist / sg_table abstractionsh]h#Scatterlist / sg_table abstractions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h-Rust abstractions for scatterlist / sg_table.h]h-Rust abstractions for scatterlist / sg_table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h[There is preceding work from Abdiel Janulgue, which hasn't made it to the mailing list yet.h]h]There is preceding work from Abdiel Janulgue, which hasn’t made it to the mailing list yet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]!scatterlist-sg-table-abstractionsah ]h"]#scatterlist / sg_table abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h PCI MISC APIsh]h PCI MISC APIs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hoExtend the existing PCI device / driver abstractions by SR-IOV, config space, capability, MSI API abstractions.h]hoExtend the existing PCI device / driver abstractions by SR-IOV, config space, capability, MSI API abstractions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh]j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h] pci-misc-apisah ]h"] pci misc apisah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hXArray bindings [XARR]h]hXArray bindings [XARR]}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhKubh)}(h`We need bindings for `xa_alloc`/`xa_alloc_cyclic` in order to generate the auxiliary device IDs.h](hWe need bindings for }(hj4hhhNhNubj)}(h `xa_alloc`h]hxa_alloc}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh/}(hj4hhhNhNubj)}(h`xa_alloc_cyclic`h]hxa_alloc_cyclic}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh/ in order to generate the auxiliary device IDs.}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj#hhubj)}(hhh]j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjfhhhhhKubah}(h]h ]h"]h$]h&]uh1jhj#hhhhhKubeh}(h]xarray-bindings-xarrah ]h"]xarray bindings [xarr]ah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hDebugfs abstractionsh]hDebugfs abstractions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h"Rust abstraction for debugfs APIs.h]h"Rust abstraction for debugfs APIs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(h!Reference: Export GSP log buffersh]h!Reference: Export GSP log buffers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]debugfs-abstractionsah ]h"]debugfs abstractionsah$]h&]uh1hhjhhhhhKubeh}(h]enablement-rustah ]h"]enablement (rust)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h GPU (general)h]h GPU (general)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hInitial Devinit supporth]hInitial Devinit support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hUImplement BIOS Device Initialization, i.e. memory sizing, waiting, PLL configuration.h]hUImplement BIOS Device Initialization, i.e. memory sizing, waiting, PLL configuration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhKubj)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]initial-devinit-supportah ]h"]initial devinit supportah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hMMU / PT managementh]hMMU / PT management}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6 hhhhhKubh)}(h:Work out the architecture for MMU / page table management.h]h:Work out the architecture for MMU / page table management.}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6 hhubh)}(hWe need to consider that nova-drm will need rather fine-grained control, especially in terms of locking, in order to be able to implement asynchronous Vulkan queues.h]hWe need to consider that nova-drm will need rather fine-grained control, especially in terms of locking, in order to be able to implement asynchronous Vulkan queues.}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6 hhubh)}(hWhile generally sharing the corresponding code is desirable, it needs to be evaluated how (and if at all) sharing the corresponding code is expedient.h]hWhile generally sharing the corresponding code is desirable, it needs to be evaluated how (and if at all) sharing the corresponding code is expedient.}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6 hhubj)}(hhh]j)}(hComplexity: Experth]hComplexity: Expert}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjq hhhhhKubah}(h]h ]h"]h$]h&]uh1jhj6 hhhhhKubeh}(h]mmu-pt-managementah ]h"]mmu / pt managementah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hVRAM memory allocatorh]hVRAM memory allocator}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(h0Investigate options for a VRAM memory allocator.h]h0Investigate options for a VRAM memory allocator.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubhdefinition_list)}(hhh]hdefinition_list_item)}(h}Some possible options: - Rust abstractions for - RB tree (interval tree) / drm_mm - maple_tree - native Rust collections h](hterm)}(hSome possible options:h]hSome possible options:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhj ubh definition)}(hhh]h)}(hhh](h)}(hERust abstractions for - RB tree (interval tree) / drm_mm - maple_treeh]h)}(hERust abstractions for - RB tree (interval tree) / drm_mm - maple_treeh]hERust abstractions for - RB tree (interval tree) / drm_mm - maple_tree}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(hnative Rust collections h]h)}(hnative Rust collectionsh]hnative Rust collections}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]jjuh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj hhhNhNubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhM ubeh}(h]vram-memory-allocatorah ]h"]vram memory allocatorah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hInstance Memoryh]hInstance Memory}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9 hhhhhM ubh)}(h?Implement support for instmem (bar2) used to store page tables.h]h?Implement support for instmem (bar2) used to store page tables.}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9 hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjX hhhhhMubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjX hhhhhMubeh}(h]h ]h"]h$]h&]uh1jhj9 hhhhhMubeh}(h]instance-memoryah ]h"]instance memoryah$]h&]uh1hhjhhhhhM ubeh}(h] gpu-generalah ]h"] gpu (general)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hGPU System Processor (GSP)h]hGPU System Processor (GSP)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hExport GSP log buffersh]hExport GSP log buffers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hRecent patches from Timur Tabi [1] added support to expose GSP-RM log buffers (even after failure to probe the driver) through debugfs.h]hRecent patches from Timur Tabi [1] added support to expose GSP-RM log buffers (even after failure to probe the driver) through debugfs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hPThis is also an interesting feature for nova-core, especially in the early days.h]hPThis is also an interesting feature for nova-core, especially in the early days.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hhh](j)}(hSLink: https://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/ [1]h](hLink: }(hj hhhNhNubj)}(hIhttps://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/h]hIhttps://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj ubh [1]}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubj)}(hReference: Debugfs abstractionsh]hReference: Debugfs abstractions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM ubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM!ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMubeh}(h]export-gsp-log-buffersah ]h"]export gsp log buffersah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hGSP firmware abstractionh]hGSP firmware abstraction}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM$ubh)}(hThe GSP-RM firmware API is unstable and may incompatibly change from version to version, in terms of data structures and semantics.h]hThe GSP-RM firmware API is unstable and may incompatibly change from version to version, in terms of data structures and semantics.}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hj hhubh)}(hThis problem is one of the big motivations for using Rust for nova-core, since it turns out that Rust's procedural macro feature provides a rather elegant way to address this issue:h]hThis problem is one of the big motivations for using Rust for nova-core, since it turns out that Rust’s procedural macro feature provides a rather elegant way to address this issue:}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hj hhubhenumerated_list)}(hhh](h)}(hOgenerate Rust structures from the C headers in a separate namespace per versionh]h)}(hjM h]hOgenerate Rust structures from the C headers in a separate namespace per version}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjK ubah}(h]h ]h"]h$]h&]uh1hhjH hhhhhNubh)}(hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiersh]h)}(hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiersh]hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiers}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjb ubah}(h]h ]h"]h$]h&]uh1hhjH hhhhhNubh)}(h`use a procedural macro to generate the actual per version implementation out of this abstractionh]h)}(h`use a procedural macro to generate the actual per version implementation out of this abstractionh]h`use a procedural macro to generate the actual per version implementation out of this abstraction}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjz ubah}(h]h ]h"]h$]h&]uh1hhjH hhhhhNubh)}(hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it's defined by a common trait) h]h)}(hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it's defined by a common trait)h]hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it’s defined by a common trait)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hj ubah}(h]h ]h"]h$]h&]uh1hhjH hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jF hj hhhhhM-ubh)}(hZThere is a PoC implementation of this pattern, in the context of the nova-core PoC driver.h]hZThere is a PoC implementation of this pattern, in the context of the nova-core PoC driver.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj hhubh)}(hhThis task aims at refining the feature and ideally generalize it, to be usable by other drivers as well.h]hhThis task aims at refining the feature and ideally generalize it, to be usable by other drivers as well.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj hhubj)}(hhh]j)}(hComplexity: Experth]hComplexity: Expert}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM<ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhM<ubeh}(h]gsp-firmware-abstractionah ]h"]gsp firmware abstractionah$]h&]uh1hhj hhhhhM$ubh)}(hhh](h)}(hGSP message queueh]hGSP message queue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM?ubh)}(hlImplement low level GSP message queue (command, status) for communication between the kernel driver and GSP.h]hlImplement low level GSP message queue (command, status) for communication between the kernel driver and GSP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhj hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMDubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMEubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMDubeh}(h]gsp-message-queueah ]h"]gsp message queueah$]h&]uh1hhj hhhhhM?ubh)}(hhh](h)}(h Bootstrap GSPh]h Bootstrap GSP}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj< hhhhhMHubh)}(hSCall the boot firmware to boot the GSP processor; execute initial control messages.h]hSCall the boot firmware to boot the GSP processor; execute initial control messages.}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhj< hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj[ hhhhhMMubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj[ hhhhhMNubeh}(h]h ]h"]h$]h&]uh1jhj< hhhhhMMubeh}(h] bootstrap-gspah ]h"] bootstrap gspah$]h&]uh1hhj hhhhhMHubh)}(hhh](h)}(hClient / Device APIsh]hClient / Device APIs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMQubh)}(h{Implement the GSP message interface for client / device allocation and the corresponding client and device allocation APIs.h]h{Implement the GSP message interface for client / device allocation and the corresponding client and device allocation APIs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMVubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMWubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMVubeh}(h]client-device-apisah ]h"]client / device apisah$]h&]uh1hhj hhhhhMQubh)}(hhh](h)}(hBar PDE handlingh]hBar PDE handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMZubh)}(hKSynchronize page table handling for BARs between the kernel driver and GSP.h]hKSynchronize page table handling for BARs between the kernel driver and GSP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hj hhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM^ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM_ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhM^ubeh}(h]bar-pde-handlingah ]h"]bar pde handlingah$]h&]uh1hhj hhhhhMZubh)}(hhh](h)}(h FIFO engineh]h FIFO engine}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMbubh)}(hImplement support for the FIFO engine, i.e. the corresponding GSP message interface and provide an API for chid allocation and channel handling.h]hImplement support for the FIFO engine, i.e. the corresponding GSP message interface and provide an API for chid allocation and channel handling.}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhj hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj? hhhhhMgubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj? hhhhhMhubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMgubeh}(h] fifo-engineah ]h"] fifo engineah$]h&]uh1hhj hhhhhMbubh)}(hhh](h)}(h GR engineh]h GR engine}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl hhhhhMkubh)}(hImplement support for the graphics engine, i.e. the corresponding GSP message interface and provide an API for (golden) context creation and promotion.h]hImplement support for the graphics engine, i.e. the corresponding GSP message interface and provide an API for (golden) context creation and promotion.}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjl hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMpubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMqubeh}(h]h ]h"]h$]h&]uh1jhjl hhhhhMpubeh}(h] gr-engineah ]h"] gr engineah$]h&]uh1hhj hhhhhMkubh)}(hhh](h)}(h CE engineh]h CE engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMtubh)}(hTImplement support for the copy engine, i.e. the corresponding GSP message interface.h]hTImplement support for the copy engine, i.e. the corresponding GSP message interface.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhj hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMyubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMzubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMyubeh}(h] ce-engineah ]h"] ce engineah$]h&]uh1hhj hhhhhMtubh)}(hhh](h)}(hVFN IRQ controllerh]hVFN IRQ controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM}ubh)}(h)Support for the VFN interrupt controller.h]h)Support for the VFN interrupt controller.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj#hhhhhMubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj#hhhhhMubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhMubeh}(h]vfn-irq-controllerah ]h"]vfn irq controllerah$]h&]uh1hhj hhhhhM}ubeh}(h]gpu-system-processor-gspah ]h"]gpu system processor (gsp)ah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h External APIsh]h External APIs}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhhhhhMubh)}(hhh](h)}(hnova-core base APIh]hnova-core base API}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihhhhhMubh)}(hcWork out the common pieces of the API to connect 2nd level drivers, i.e. vGPU manager and nova-drm.h]hcWork out the common pieces of the API to connect 2nd level drivers, i.e. vGPU manager and nova-drm.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjihhubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhMubah}(h]h ]h"]h$]h&]uh1jhjihhhhhMubeh}(h]nova-core-base-apiah ]h"]nova-core base apiah$]h&]uh1hhjXhhhhhMubh)}(hhh](h)}(hvGPU manager APIh]hvGPU manager API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h[Work out the API parts required by the vGPU manager, which are not covered by the base API.h]h[Work out the API parts required by the vGPU manager, which are not covered by the base API.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhMubah}(h]h ]h"]h$]h&]uh1jhjhhhhhMubeh}(h]vgpu-manager-apiah ]h"]vgpu manager apiah$]h&]uh1hhjXhhhhhMubh)}(hhh](h)}(hnova-core C APIh]hnova-core C API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hGImplement a C wrapper for the APIs required by the vGPU manager driver.h]hGImplement a C wrapper for the APIs required by the vGPU manager driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh]j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhMubah}(h]h ]h"]h$]h&]uh1jhjhhhhhMubeh}(h]nova-core-c-apiah ]h"]nova-core c apiah$]h&]uh1hhjXhhhhhMubeh}(h] external-apisah ]h"] external apisah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hTestingh]hTesting}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhMubh)}(hhh](h)}(h CI pipelineh]h CI pipeline}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhMubh)}(h6Investigate option for continuous integration testing.h]h6Investigate option for continuous integration testing.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<hhubh)}(hThis can go from as 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