sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/gpu/nova/core/todomodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)h]h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/gpu/nova/core/todo.rsthKubhsection)}(hhh](htitle)}(h Task Listh]h Task List}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h$Tasks may have the following fields:h]h$Tasks may have the following fields:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(h``Complexity``: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.h]h)}(h``Complexity``: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.h](hliteral)}(h``Complexity``h]h Complexity}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, }(hhhhhNhNubh)}(h ``Beginner``h]hBeginner}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh, }(hhhhhNhNubh)}(h``Intermediate``h]h Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh, }hhsbh)}(h ``Advanced``h]hAdvanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh and }(hhhhhNhNubh)}(h ``Expert``h]hExpert}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h)``Reference``: References to other tasks.h]h)}(hjRh](h)}(h ``Reference``h]h Reference}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubh: References to other tasks.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjPubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h&``Link``: Links to external resources.h]h)}(hjwh](h)}(h``Link``h]hLink}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyubh: Links to external resources.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjuubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hV``Contact``: The person that can be contacted for further information about the task. h]h)}(hU``Contact``: The person that can be contacted for further information about the task.h](h)}(h ``Contact``h]hContact}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhJ: The person that can be contacted for further information about the task.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK hhhhubh)}(hhh](h)}(hEnablement (Rust)h]hEnablement (Rust)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hbTasks that are not directly related to nova-core, but are preconditions in terms of required APIs.h]hbTasks that are not directly related to nova-core, but are preconditions in terms of required APIs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hFromPrimitive APIh]hFromPrimitive API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hSSometimes the need arises to convert a number to a value of an enum or a structure.h]hSSometimes the need arises to convert a number to a value of an enum or a structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXoA good example from nova-core would be the ``Chipset`` enum type, which defines the value ``AD102``. When probing the GPU the value ``0x192`` can be read from a certain register indication the chipset AD102. Hence, the enum value ``AD102`` should be derived from the number ``0x192``. Currently, nova-core uses a custom implementation (``Chipset::from_u32`` for this.h](h+A good example from nova-core would be the }(hjhhhNhNubh)}(h ``Chipset``h]hChipset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh$ enum type, which defines the value }(hjhhhNhNubh)}(h ``AD102``h]hAD102}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh!. When probing the GPU the value }(hjhhhNhNubh)}(h ``0x192``h]h0x192}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhY can be read from a certain register indication the chipset AD102. Hence, the enum value }(hjhhhNhNubh)}(h ``AD102``h]hAD102}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh# should be derived from the number }(hjhhhNhNubh)}(h ``0x192``h]h0x192}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh5. Currently, nova-core uses a custom implementation (}(hjhhhNhNubh)}(h``Chipset::from_u32``h]hChipset::from_u32}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh for this.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hiInstead, it would be desirable to have something like the ``FromPrimitive`` trait [1] from the num crate.h](h:Instead, it would be desirable to have something like the }(hjhhhNhNubh)}(h``FromPrimitive``h]h FromPrimitive}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh trait [1] from the num crate.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK#hjhhubh)}(hHaving this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number.h]hHaving this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubh line_block)}(hhh](hh)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hindentKhjhhhhhK)ubj)}(h=Link: https://docs.rs/num/latest/num/trait.FromPrimitive.htmlh](hLink: }(hjhhhNhNubh reference)}(h7https://docs.rs/num/latest/num/trait.FromPrimitive.htmlh]h7https://docs.rs/num/latest/num/trait.FromPrimitive.html}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhK*ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhK)ubeh}(h]fromprimitive-apiah ]h"]fromprimitive apiah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hGeneric register abstractionh]hGeneric register abstraction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK-ubh)}(hiWork out how register constants and structures can be automatically generated through generalized macros.h]hiWork out how register constants and structures can be automatically generated through generalized macros.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjhhubh)}(hExample:h]hExample:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjhhubh literal_block)}(hregister!(BOOT0, 0x0, u32, pci::Bar, Fields [ MINOR_REVISION(3:0, RO), MAJOR_REVISION(7:4, RO), REVISION(7:0, RO), // Virtual register combining major and minor rev. ])h]hregister!(BOOT0, 0x0, u32, pci::Bar, Fields [ MINOR_REVISION(3:0, RO), MAJOR_REVISION(7:4, RO), REVISION(7:0, RO), // Virtual register combining major and minor rev. ])}hjsbah}(h]h ]h"]h$]h&]hhforcelanguagerusthighlight_args}uh1jhhhK4hjhhubh)}(h$This could expand to something like:h]h$This could expand to something like:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>) -> Self { Self(bar.readl(BOOT0_OFFSET)) } #[inline] fn minor_revision(&self) -> u32 { (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT } #[inline] fn major_revision(&self) -> u32 { (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT } #[inline] fn revision(&self) -> u32 { (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT } }h]hXconst BOOT0_OFFSET: usize = 0x00000000; const BOOT0_MINOR_REVISION_SHIFT: u8 = 0; const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f; const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4; const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0; const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT; const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK | BOOT0_MAJOR_REVISION_MASK; struct Boot0(u32); impl Boot0 { #[inline] fn read(bar: &RevocableGuard<'_, pci::Bar>) -> Self { Self(bar.readl(BOOT0_OFFSET)) } #[inline] fn minor_revision(&self) -> u32 { (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT } #[inline] fn major_revision(&self) -> u32 { (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT } #[inline] fn revision(&self) -> u32 { (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT } }}hj@sbah}(h]h ]h"]h$]h&]hhj-j.rustj0}uh1jhhhK>hjhhubh)}(hUsage:h]hUsage:}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjhhubj)}(hwlet bar = bar.try_access().ok_or(ENXIO)?; let boot0 = Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision());h]hwlet bar = bar.try_access().ok_or(ENXIO)?; let boot0 = Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision());}hj^sbah}(h]h ]h"]h$]h&]hhj-j.rustj0}uh1jhhhKbhjhhubh)}(hX Note: a work-in-progress implementation currently resides in `drivers/gpu/nova-core/regs/macros.rs` and is used in nova-core. It would be nice to improve it (possibly using proc macros) and move it to the `kernel` crate so it can be used by other components as well.h](h=Note: a work-in-progress implementation currently resides in }(hjnhhhNhNubhtitle_reference)}(h&`drivers/gpu/nova-core/regs/macros.rs`h]h$drivers/gpu/nova-core/regs/macros.rs}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjnubhj and is used in nova-core. It would be nice to improve it (possibly using proc macros) and move it to the }(hjnhhhNhNubjw)}(h`kernel`h]hkernel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjnubh5 crate so it can be used by other components as well.}(hjnhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKihjhhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKnubj)}(hContact: Alexandre Courboth]hContact: Alexandre Courbot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKoubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKnubeh}(h]generic-register-abstractionah ]h"]generic register abstractionah$]h&]uh1hhjhhhhhK-ubh)}(hhh](h)}(hDelay / Sleep abstractionsh]hDelay / Sleep abstractions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKrubh)}(hARust abstractions for the kernel's delay() and sleep() functions.h]hCRust abstractions for the kernel’s delay() and sleep() functions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjhhubh)}(h_FUJITA Tomonori plans to work on abstractions for read_poll_timeout_atomic() (and friends) [1].h]h_FUJITA Tomonori plans to work on abstractions for read_poll_timeout_atomic() (and friends) [1].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjhhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKyubj)}(hfLink: https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/ [1]h](hLink: }(hj hhhNhNubj)}(h\https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/h]h\https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhj ubh [1]}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKzubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKyubeh}(h]delay-sleep-abstractionsah ]h"]delay / sleep abstractionsah$]h&]uh1hhjhhhhhKrubh)}(hhh](h)}(hIRQ abstractionsh]hIRQ abstractions}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhK}ubh)}(h#Rust abstractions for IRQ handling.h]h#Rust abstractions for IRQ handling.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj<hhubh)}(haThere is active ongoing work from Daniel Almeida [1] for the "core" abstractions to request IRQs.h]heThere is active ongoing work from Daniel Almeida [1] for the “core” abstractions to request IRQs.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj<hhubh)}(hBesides optional review and testing work, the required ``pci::Device`` code around those core abstractions needs to be worked out.h](h7Besides optional review and testing work, the required }(hjihhhNhNubh)}(h``pci::Device``h]h pci::Device}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjiubh< code around those core abstractions needs to be worked out.}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj<hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(h[Link: https://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/ [1]h](hLink: }(hjhhhNhNubj)}(hQhttps://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/h]hQhttps://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubh [1]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Daniel Almeidah]hContact: Daniel Almeida}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhj<hhhhhKubeh}(h]irq-abstractionsah ]h"]irq abstractionsah$]h&]uh1hhjhhhhhK}ubh)}(hhh](h)}(h"Page abstraction for foreign pagesh]h"Page abstraction for foreign pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h^Rust abstractions for pages not created by the Rust page abstraction without direct ownership.h]h^Rust abstractions for pages not created by the Rust page abstraction without direct ownership.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hBThere is active onging work from Abdiel Janulgue [1] and Lina [2].h]hBThere is active onging work from Abdiel Janulgue [1] and Lina [2].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(h]Link: https://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/ [1]h](hLink: }(hjhhhNhNubj)}(hShttps://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/h]hShttps://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubh [1]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hdLink: https://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/ [2]h](hLink: }(hj6hhhNhNubj)}(hZhttps://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/h]hZhttps://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/}(hj>hhhNhNubah}(h]h ]h"]h$]h&]refurij@uh1jhj6ubh [2]}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]"page-abstraction-for-foreign-pagesah ]h"]"page abstraction for foreign pagesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h#Scatterlist / sg_table abstractionsh]h#Scatterlist / sg_table abstractions}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehhhhhKubh)}(h-Rust abstractions for scatterlist / sg_table.h]h-Rust abstractions for scatterlist / sg_table.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjehhubh)}(h[There is preceding work from Abdiel Janulgue, which hasn't made it to the mailing list yet.h]h]There is preceding work from Abdiel Janulgue, which hasn’t made it to the mailing list yet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjehhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjehhhhhKubeh}(h]!scatterlist-sg-table-abstractionsah ]h"]#scatterlist / sg_table abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h ELF utilsh]h ELF utils}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hRust implementation of ELF header representation to retrieve section header tables, names, and data from an ELF-formatted images.h]hRust implementation of ELF header representation to retrieve section header tables, names, and data from an ELF-formatted images.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h[There is preceding work from Abdiel Janulgue, which hasn't made it to the mailing list yet.h]h]There is preceding work from Abdiel Janulgue, which hasn’t made it to the mailing list yet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h] elf-utilsah ]h"] elf utilsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h PCI MISC APIsh]h PCI MISC APIs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hoExtend the existing PCI device / driver abstractions by SR-IOV, config space, capability, MSI API abstractions.h]hoExtend the existing PCI device / driver abstractions by SR-IOV, config space, capability, MSI API abstractions.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh]j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj8hhhhhKubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h] pci-misc-apisah ]h"] pci misc apisah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hAuxiliary bus abstractionsh]hAuxiliary bus abstractions}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhhhhhKubh)}(h,Rust abstraction for the auxiliary bus APIs.h]h,Rust abstraction for the auxiliary bus APIs.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjWhhubh)}(h;This is needed to connect nova-core to the nova-drm driver.h]h;This is needed to connect nova-core to the nova-drm driver.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjWhhubj)}(hhh]j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubah}(h]h ]h"]h$]h&]uh1jhjWhhhhhKubeh}(h]auxiliary-bus-abstractionsah ]h"]auxiliary bus abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hDebugfs abstractionsh]hDebugfs abstractions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h"Rust abstraction for debugfs APIs.h]h"Rust abstraction for debugfs APIs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(h!Reference: Export GSP log buffersh]h!Reference: Export GSP log buffers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]debugfs-abstractionsah ]h"]debugfs abstractionsah$]h&]uh1hhjhhhhhKubeh}(h]enablement-rustah ]h"]enablement (rust)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h GPU (general)h]h GPU (general)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hParse firmware headersh]hParse firmware headers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hEParse ELF headers from the firmware files loaded from the filesystem.h]hEParse ELF headers from the firmware files loaded from the filesystem.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hReference: ELF utilsh]hReference: ELF utils}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj'hhhhhKubj)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj'hhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj'hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]parse-firmware-headersah ]h"]parse firmware headersah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hBuild radix3 page tableh]hBuild radix3 page table}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhhhhhKubh)}(h0Build the radix3 page table to map the firmware.h]h0Build the radix3 page table to map the firmware.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjbhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjbhhhhhKubeh}(h]build-radix3-page-tableah ]h"]build radix3 page tableah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h vBIOS supporth]h vBIOS support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hLParse the vBIOS and probe the structures required for driver initialization.h]hLParse the vBIOS and probe the structures required for driver initialization.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hReference: Vec extensionsh]hReference: Vec extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h] vbios-supportah ]h"] vbios supportah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hInitial Devinit supporth]hInitial Devinit support}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hUImplement BIOS Device Initialization, i.e. memory sizing, waiting, PLL configuration.h]hUImplement BIOS Device Initialization, i.e. memory sizing, waiting, PLL configuration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj'hhhhhKubj)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj'hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]initial-devinit-supportah ]h"]initial devinit supportah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hBoot Falcon controllerh]hBoot Falcon controller}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThhhhhKubh)}(htInfrastructure to load and execute falcon (sec2) firmware images; handle the GSP falcon processor and fwsec loading.h]htInfrastructure to load and execute falcon (sec2) firmware images; handle the GSP falcon processor and fwsec loading.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjThhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjshhhhhKubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjshhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjThhhhhKubeh}(h]boot-falcon-controllerah ]h"]boot falcon controllerah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hGPU Timer supporth]hGPU Timer support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h0Support for the GPU's internal timer peripheral.h]h2Support for the GPU’s internal timer peripheral.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]gpu-timer-supportah ]h"]gpu timer supportah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hMMU / PT managementh]hMMU / PT management}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h:Work out the architecture for MMU / page table management.h]h:Work out the architecture for MMU / page table management.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hWe need to consider that nova-drm will need rather fine-grained control, especially in terms of locking, in order to be able to implement asynchronous Vulkan queues.h]hWe need to consider that nova-drm will need rather fine-grained control, especially in terms of locking, in order to be able to implement asynchronous Vulkan queues.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hWhile generally sharing the corresponding code is desirable, it needs to be evaluated how (and if at all) sharing the corresponding code is expedient.h]hWhile generally sharing the corresponding code is desirable, it needs to be evaluated how (and if at all) sharing the corresponding code is expedient.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh]j)}(hComplexity: Experth]hComplexity: Expert}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj' hhhhhM ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhM ubeh}(h]mmu-pt-managementah ]h"]mmu / pt managementah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hVRAM memory allocatorh]hVRAM memory allocator}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF hhhhhM ubh)}(h0Investigate options for a VRAM memory allocator.h]h0Investigate options for a VRAM memory allocator.}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjF hhubhdefinition_list)}(hhh]hdefinition_list_item)}(h}Some possible options: - Rust abstractions for - RB tree (interval tree) / drm_mm - maple_tree - native Rust collections h](hterm)}(hSome possible options:h]hSome possible options:}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1jp hhhMhjl ubh definition)}(hhh]h)}(hhh](h)}(hERust abstractions for - RB tree (interval tree) / drm_mm - maple_treeh]h)}(hERust abstractions for - RB tree (interval tree) / drm_mm - maple_treeh]hERust abstractions for - RB tree (interval tree) / drm_mm - maple_tree}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(hnative Rust collections h]h)}(hnative Rust collectionsh]hnative Rust collections}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]jjuh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hjl ubeh}(h]h ]h"]h$]h&]uh1jj hhhMhjg ubah}(h]h ]h"]h$]h&]uh1je hjF hhhNhNubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubah}(h]h ]h"]h$]h&]uh1jhjF hhhhhMubeh}(h]vram-memory-allocatorah ]h"]vram memory allocatorah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(hInstance Memoryh]hInstance Memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(h?Implement support for instmem (bar2) used to store page tables.h]h?Implement support for instmem (bar2) used to store page tables.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMubeh}(h]instance-memoryah ]h"]instance memoryah$]h&]uh1hhjhhhhhMubeh}(h] gpu-generalah ]h"] gpu (general)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hGPU System Processor (GSP)h]hGPU System Processor (GSP)}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC hhhhhM"ubh)}(hhh](h)}(hExport GSP log buffersh]hExport GSP log buffers}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT hhhhhM%ubh)}(hRecent patches from Timur Tabi [1] added support to expose GSP-RM log buffers (even after failure to probe the driver) through debugfs.h]hRecent patches from Timur Tabi [1] added support to expose GSP-RM log buffers (even after failure to probe the driver) through debugfs.}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjT hhubh)}(hPThis is also an interesting feature for nova-core, especially in the early days.h]hPThis is also an interesting feature for nova-core, especially in the early days.}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hjT hhubj)}(hhh](j)}(hSLink: https://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/ [1]h](hLink: }(hj hhhNhNubj)}(hIhttps://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/h]hIhttps://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj ubh [1]}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM,ubj)}(hReference: Debugfs abstractionsh]hReference: Debugfs abstractions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM-ubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM.ubeh}(h]h ]h"]h$]h&]uh1jhjT hhhhhM,ubeh}(h]export-gsp-log-buffersah ]h"]export gsp log buffersah$]h&]uh1hhjC hhhhhM%ubh)}(hhh](h)}(hGSP firmware abstractionh]hGSP firmware abstraction}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM1ubh)}(hThe GSP-RM firmware API is unstable and may incompatibly change from version to version, in terms of data structures and semantics.h]hThe GSP-RM firmware API is unstable and may incompatibly change from version to version, in terms of data structures and semantics.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hj hhubh)}(hThis problem is one of the big motivations for using Rust for nova-core, since it turns out that Rust's procedural macro feature provides a rather elegant way to address this issue:h]hThis problem is one of the big motivations for using Rust for nova-core, since it turns out that Rust’s procedural macro feature provides a rather elegant way to address this issue:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj hhubhenumerated_list)}(hhh](h)}(hOgenerate Rust structures from the C headers in a separate namespace per versionh]h)}(hj h]hOgenerate Rust structures from the C headers in a separate namespace per version}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hj ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiersh]h)}(hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiersh]hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hj ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(h`use a procedural macro to generate the actual per version implementation out of this abstractionh]h)}(h`use a procedural macro to generate the actual per version implementation out of this abstractionh]h`use a procedural macro to generate the actual per version implementation out of this abstraction}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj0 ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it's defined by a common trait) h]h)}(hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it's defined by a common trait)h]hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it’s defined by a common trait)}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjH ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j hj hhhhhM:ubh)}(hZThere is a PoC implementation of this pattern, in the context of the nova-core PoC driver.h]hZThere is a PoC implementation of this pattern, in the context of the nova-core PoC driver.}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChj hhubh)}(hhThis task aims at refining the feature and ideally generalize it, to be usable by other drivers as well.h]hhThis task aims at refining the feature and ideally generalize it, to be usable by other drivers as well.}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj hhubj)}(hhh]j)}(hComplexity: Experth]hComplexity: Expert}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMIubah}(h]h ]h"]h$]h&]uh1jhj hhhhhMIubeh}(h]gsp-firmware-abstractionah ]h"]gsp firmware abstractionah$]h&]uh1hhjC hhhhhM1ubh)}(hhh](h)}(hGSP message queueh]hGSP message queue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMLubh)}(hlImplement low level GSP message queue (command, status) for communication between the kernel driver and GSP.h]hlImplement low level GSP message queue (command, status) for communication between the kernel driver and GSP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMQubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMRubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMQubeh}(h]gsp-message-queueah ]h"]gsp message queueah$]h&]uh1hhjC hhhhhMLubh)}(hhh](h)}(h Bootstrap GSPh]h Bootstrap GSP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMUubh)}(hSCall the boot firmware to boot the GSP processor; execute initial control messages.h]hSCall the boot firmware to boot the GSP processor; execute initial control messages.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhj hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMZubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM[ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMZubeh}(h] bootstrap-gspah ]h"] bootstrap gspah$]h&]uh1hhjC hhhhhMUubh)}(hhh](h)}(hClient / Device APIsh]hClient / Device APIs}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj> hhhhhM^ubh)}(h{Implement the GSP message interface for client / device allocation and the corresponding client and device allocation APIs.h]h{Implement the GSP message interface for client / device allocation and the corresponding client and device allocation APIs.}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hj> hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj] hhhhhMcubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj] hhhhhMdubeh}(h]h ]h"]h$]h&]uh1jhj> hhhhhMcubeh}(h]client-device-apisah ]h"]client / device apisah$]h&]uh1hhjC hhhhhM^ubh)}(hhh](h)}(hBar PDE handlingh]hBar PDE handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMgubh)}(hKSynchronize page table handling for BARs between the kernel driver and GSP.h]hKSynchronize page table handling for BARs between the kernel driver and GSP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihj hhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMkubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMlubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMkubeh}(h]bar-pde-handlingah ]h"]bar pde handlingah$]h&]uh1hhjC hhhhhMgubh)}(hhh](h)}(h FIFO engineh]h FIFO engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMoubh)}(hImplement support for the FIFO engine, i.e. the corresponding GSP message interface and provide an API for chid allocation and channel handling.h]hImplement support for the FIFO engine, i.e. the corresponding GSP message interface and provide an API for chid allocation and channel handling.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhj hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMtubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMuubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMtubeh}(h] fifo-engineah ]h"] fifo engineah$]h&]uh1hhjC hhhhhMoubh)}(hhh](h)}(h GR engineh]h GR engine}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj" hhhhhMxubh)}(hImplement support for the graphics engine, i.e. the corresponding GSP message interface and provide an API for (golden) context creation and promotion.h]hImplement support for the graphics engine, i.e. the corresponding GSP message interface and provide an API for (golden) context creation and promotion.}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj" hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjA hhhhhM}ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjA hhhhhM~ubeh}(h]h ]h"]h$]h&]uh1jhj" hhhhhM}ubeh}(h] gr-engineah ]h"] gr engineah$]h&]uh1hhjC hhhhhMxubh)}(hhh](h)}(h CE engineh]h CE engine}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn hhhhhMubh)}(hTImplement support for the copy engine, i.e. the corresponding GSP message interface.h]hTImplement support for the copy engine, i.e. the corresponding GSP message interface.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjn hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubeh}(h]h ]h"]h$]h&]uh1jhjn hhhhhMubeh}(h] ce-engineah ]h"] ce engineah$]h&]uh1hhjC hhhhhMubh)}(hhh](h)}(hVFN IRQ controllerh]hVFN IRQ controller}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(h)Support for the VFN interrupt controller.h]h)Support for the VFN interrupt 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]h"]h$]h&]uh1hjKhj>hhhhhMubah}(h]h ]h"]h$]h&]uh1jhjhhhhhMubeh}(h]nova-core-base-apiah ]h"]nova-core base apiah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hvGPU manager APIh]hvGPU manager API}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hhhhhMubh)}(h[Work out the API parts required by the vGPU manager, which are not covered by the base API.h]h[Work out the API parts required by the vGPU manager, which are not covered by the base API.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj]hhubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj|hhhhhMubah}(h]h ]h"]h$]h&]uh1jhj]hhhhhMubeh}(h]vgpu-manager-apiah ]h"]vgpu manager apiah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hnova-core C APIh]hnova-core C API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hGImplement a C wrapper for the APIs required by the vGPU manager driver.h]hGImplement a C wrapper for the APIs required by the vGPU manager driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh]j)}(hComplexity: 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