sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/gpu/nova/core/todomodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)h]h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/gpu/nova/core/todo.rsthKubhsection)}(hhh](htitle)}(h Task Listh]h Task List}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h$Tasks may have the following fields:h]h$Tasks may have the following fields:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(h``Complexity``: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.h]h)}(h``Complexity``: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.h](hliteral)}(h``Complexity``h]h Complexity}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, }(hhhhhNhNubh)}(h ``Beginner``h]hBeginner}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh, }(hhhhhNhNubh)}(h``Intermediate``h]h Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh, }hhsbh)}(h ``Advanced``h]hAdvanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh and }(hhhhhNhNubh)}(h ``Expert``h]hExpert}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h)``Reference``: References to other tasks.h]h)}(hjRh](h)}(h ``Reference``h]h Reference}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubh: References to other tasks.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjPubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h&``Link``: Links to external resources.h]h)}(hjwh](h)}(h``Link``h]hLink}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyubh: Links to external resources.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjuubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hV``Contact``: The person that can be contacted for further information about the task. h]h)}(hU``Contact``: The person that can be contacted for further information about the task.h](h)}(h ``Contact``h]hContact}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhJ: The person that can be contacted for further information about the task.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK hhhhubh)}(hhh](h)}(hEnablement (Rust)h]hEnablement (Rust)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hbTasks that are not directly related to nova-core, but are preconditions in terms of required APIs.h]hbTasks that are not directly related to nova-core, but are preconditions in terms of required APIs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hFromPrimitive APIh]hFromPrimitive API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hSSometimes the need arises to convert a number to a value of an enum or a structure.h]hSSometimes the need arises to convert a number to a value of an enum or a structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXoA good example from nova-core would be the ``Chipset`` enum type, which defines the value ``AD102``. When probing the GPU the value ``0x192`` can be read from a certain register indication the chipset AD102. Hence, the enum value ``AD102`` should be derived from the number ``0x192``. Currently, nova-core uses a custom implementation (``Chipset::from_u32`` for this.h](h+A good example from nova-core would be the }(hjhhhNhNubh)}(h ``Chipset``h]hChipset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh$ enum type, which defines the value }(hjhhhNhNubh)}(h ``AD102``h]hAD102}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh!. When probing the GPU the value }(hjhhhNhNubh)}(h ``0x192``h]h0x192}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhY can be read from a certain register indication the chipset AD102. Hence, the enum value }(hjhhhNhNubh)}(h ``AD102``h]hAD102}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh# should be derived from the number }(hjhhhNhNubh)}(h ``0x192``h]h0x192}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh5. Currently, nova-core uses a custom implementation (}(hjhhhNhNubh)}(h``Chipset::from_u32``h]hChipset::from_u32}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh for this.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hiInstead, it would be desirable to have something like the ``FromPrimitive`` trait [1] from the num crate.h](h:Instead, it would be desirable to have something like the }(hjhhhNhNubh)}(h``FromPrimitive``h]h FromPrimitive}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh trait [1] from the num crate.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK#hjhhubh)}(hHaving this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number.h]hHaving this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubh line_block)}(hhh](hh)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hindentKhjhhhhhK)ubj)}(h=Link: https://docs.rs/num/latest/num/trait.FromPrimitive.htmlh](hLink: }(hjhhhNhNubh reference)}(h7https://docs.rs/num/latest/num/trait.FromPrimitive.htmlh]h7https://docs.rs/num/latest/num/trait.FromPrimitive.html}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhK*ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhK)ubeh}(h]fromprimitive-apiah ]h"]fromprimitive apiah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hGeneric register abstractionh]hGeneric register abstraction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK-ubh)}(hiWork out how register constants and structures can be automatically generated through generalized macros.h]hiWork out how register constants and structures can be automatically generated through generalized macros.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjhhubh)}(hExample:h]hExample:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjhhubh literal_block)}(hregister!(BOOT0, 0x0, u32, pci::Bar, Fields [ MINOR_REVISION(3:0, RO), MAJOR_REVISION(7:4, RO), REVISION(7:0, RO), // Virtual register combining major and minor rev. ])h]hregister!(BOOT0, 0x0, u32, pci::Bar, Fields [ MINOR_REVISION(3:0, RO), MAJOR_REVISION(7:4, RO), REVISION(7:0, RO), // Virtual register combining major and minor rev. ])}hjsbah}(h]h ]h"]h$]h&]hhforcelanguagerusthighlight_args}uh1jhhhK4hjhhubh)}(h$This could expand to something like:h]h$This could expand to something like:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>) -> Self { Self(bar.readl(BOOT0_OFFSET)) } #[inline] fn minor_revision(&self) -> u32 { (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT } #[inline] fn major_revision(&self) -> u32 { (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT } #[inline] fn revision(&self) -> u32 { (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT } }h]hXconst BOOT0_OFFSET: usize = 0x00000000; const BOOT0_MINOR_REVISION_SHIFT: u8 = 0; const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f; const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4; const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0; const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT; const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK | BOOT0_MAJOR_REVISION_MASK; struct Boot0(u32); impl Boot0 { #[inline] fn read(bar: &RevocableGuard<'_, pci::Bar>) -> Self { Self(bar.readl(BOOT0_OFFSET)) } #[inline] fn minor_revision(&self) -> u32 { (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT } #[inline] fn major_revision(&self) -> u32 { (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT } #[inline] fn revision(&self) -> u32 { (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT } }}hj@sbah}(h]h ]h"]h$]h&]hhj-j.rustj0}uh1jhhhK>hjhhubh)}(hUsage:h]hUsage:}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjhhubj)}(hwlet bar = bar.try_access().ok_or(ENXIO)?; let boot0 = Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision());h]hwlet bar = bar.try_access().ok_or(ENXIO)?; let boot0 = Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision());}hj^sbah}(h]h ]h"]h$]h&]hhj-j.rustj0}uh1jhhhKbhjhhubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjnhhhhhKiubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKiubeh}(h]generic-register-abstractionah ]h"]generic register abstractionah$]h&]uh1hhjhhhhhK-ubh)}(hhh](h)}(hDelay / Sleep abstractionsh]hDelay / Sleep abstractions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKlubh)}(hARust abstractions for the kernel's delay() and sleep() functions.h]hCRust abstractions for the kernel’s delay() and sleep() functions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjhhubh)}(h_FUJITA Tomonori plans to work on abstractions for read_poll_timeout_atomic() (and friends) [1].h]h_FUJITA Tomonori plans to work on abstractions for read_poll_timeout_atomic() (and friends) [1].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjhhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKsubj)}(hfLink: https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/ [1]h](hLink: }(hjhhhNhNubj)}(h\https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/h]h\https://lore.kernel.org/netdev/20250228.080550.354359820929821928.fujita.tomonori@gmail.com/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubh [1]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKtubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKsubeh}(h]delay-sleep-abstractionsah ]h"]delay / sleep abstractionsah$]h&]uh1hhjhhhhhKlubh)}(hhh](h)}(hIRQ abstractionsh]hIRQ abstractions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKwubh)}(h#Rust abstractions for IRQ handling.h]h#Rust abstractions for IRQ handling.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjhhubh)}(haThere is active ongoing work from Daniel Almeida [1] for the "core" abstractions to request IRQs.h]heThere is active ongoing work from Daniel Almeida [1] for the “core” abstractions to request IRQs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjhhubh)}(hBesides optional review and testing work, the required ``pci::Device`` code around those core abstractions needs to be worked out.h](h7Besides optional review and testing work, the required }(hj'hhhNhNubh)}(h``pci::Device``h]h pci::Device}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubh< code around those core abstractions needs to be worked out.}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK~hjhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjGhhhhhKubj)}(h[Link: https://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/ [1]h](hLink: }(hjXhhhNhNubj)}(hQhttps://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/h]hQhttps://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/}(hj`hhhNhNubah}(h]h ]h"]h$]h&]refurijbuh1jhjXubh [1]}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjGhhhhhKubj)}(hContact: Daniel Almeidah]hContact: Daniel Almeida}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjGhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]irq-abstractionsah ]h"]irq abstractionsah$]h&]uh1hhjhhhhhKwubh)}(hhh](h)}(h"Page abstraction for foreign pagesh]h"Page abstraction for foreign pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h^Rust abstractions for pages not created by the Rust page abstraction without direct ownership.h]h^Rust abstractions for pages not created by the Rust page abstraction without direct ownership.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hBThere is active onging work from Abdiel Janulgue [1] and Lina [2].h]hBThere is active onging work from Abdiel Janulgue [1] and Lina [2].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(h]Link: https://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/ [1]h](hLink: }(hjhhhNhNubj)}(hShttps://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/h]hShttps://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubh [1]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hdLink: https://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/ [2]h](hLink: }(hjhhhNhNubj)}(hZhttps://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/h]hZhttps://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubh [2]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]"page-abstraction-for-foreign-pagesah ]h"]"page abstraction for foreign pagesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h#Scatterlist / sg_table abstractionsh]h#Scatterlist / sg_table abstractions}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhKubh)}(h-Rust abstractions for scatterlist / sg_table.h]h-Rust abstractions for scatterlist / sg_table.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj#hhubh)}(h[There is preceding work from Abdiel Janulgue, which hasn't made it to the mailing list yet.h]h]There is preceding work from Abdiel Janulgue, which hasn’t made it to the mailing list yet.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj#hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjPhhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjPhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhj#hhhhhKubeh}(h]!scatterlist-sg-table-abstractionsah ]h"]#scatterlist / sg_table abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h ELF utilsh]h ELF utils}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hhhhhKubh)}(hRust implementation of ELF header representation to retrieve section header tables, names, and data from an ELF-formatted images.h]hRust implementation of ELF header representation to retrieve section header tables, names, and data from an ELF-formatted images.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}hhubh)}(h[There is preceding work from Abdiel Janulgue, which hasn't made it to the mailing list yet.h]h]There is preceding work from Abdiel Janulgue, which hasn’t made it to the mailing list yet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}hhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhj}hhhhhKubeh}(h] elf-utilsah ]h"] elf utilsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h PCI MISC APIsh]h PCI MISC APIs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hoExtend the existing PCI device / driver abstractions by SR-IOV, config space, capability, MSI API abstractions.h]hoExtend the existing PCI device / driver abstractions by SR-IOV, config space, capability, MSI API abstractions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh]j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h] pci-misc-apisah ]h"] pci misc apisah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hAuxiliary bus abstractionsh]hAuxiliary bus abstractions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h,Rust abstraction for the auxiliary bus APIs.h]h,Rust abstraction for the auxiliary bus APIs.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h;This is needed to connect nova-core to the nova-drm driver.h]h;This is needed to connect nova-core to the nova-drm driver.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh]j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjBhhhhhKubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]auxiliary-bus-abstractionsah ]h"]auxiliary bus abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hDebugfs abstractionsh]hDebugfs abstractions}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahhhhhKubh)}(h"Rust abstraction for debugfs APIs.h]h"Rust abstraction for debugfs APIs.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjahhubj)}(hhh](j)}(h!Reference: Export GSP log buffersh]h!Reference: Export GSP log buffers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjahhhhhKubeh}(h]debugfs-abstractionsah ]h"]debugfs abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hVec extensionsh]hVec extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h0Implement ``Vec::truncate`` and ``Vec::resize``.h](h Implement }(hjhhhNhNubh)}(h``Vec::truncate``h]h Vec::truncate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh and }(hjhhhNhNubh)}(h``Vec::resize``h]h Vec::resize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hECurrently this is used for some experimental code to parse the vBIOS.h]hECurrently this is used for some experimental code to parse the vBIOS.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hReference vBIOS supporth]hReference vBIOS support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]vec-extensionsah ]h"]vec extensionsah$]h&]uh1hhjhhhhhKubeh}(h]enablement-rustah ]h"]enablement (rust)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h GPU (general)h]h GPU (general)}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhhhKubh)}(hhh](h)}(hParse firmware headersh]hParse firmware headers}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhKubh)}(hEParse ELF headers from the firmware files loaded from the filesystem.h]hEParse ELF headers from the firmware files loaded from the filesystem.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubj)}(hhh](j)}(hReference: ELF utilsh]hReference: ELF utils}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjchhhhhKubj)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjchhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjchhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjDhhhhhKubeh}(h]parse-firmware-headersah ]h"]parse firmware headersah$]h&]uh1hhj3hhhhhKubh)}(hhh](h)}(hBuild radix3 page tableh]hBuild radix3 page table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h0Build the radix3 page table to map the firmware.h]h0Build the radix3 page table to map the firmware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]build-radix3-page-tableah ]h"]build radix3 page tableah$]h&]uh1hhj3hhhhhKubh)}(hhh](h)}(h vBIOS supporth]h vBIOS support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hLParse the vBIOS and probe the structures required for driver initialization.h]hLParse the vBIOS and probe the structures required for driver initialization.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhKubj)}(hReference: Vec extensionsh]hReference: Vec extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhKubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h] vbios-supportah ]h"] vbios supportah$]h&]uh1hhj3hhhhhKubh)}(hhh](h)}(hInitial Devinit supporth]hInitial Devinit support}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhKubh)}(hUImplement BIOS Device Initialization, i.e. memory sizing, waiting, PLL configuration.h]hUImplement BIOS Device Initialization, i.e. memory sizing, waiting, PLL configuration.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubj)}(hhh](j)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjchhhhhKubj)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjchhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjDhhhhhKubeh}(h]initial-devinit-supportah ]h"]initial devinit supportah$]h&]uh1hhj3hhhhhKubh)}(hhh](h)}(hBoot Falcon controllerh]hBoot Falcon controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(htInfrastructure to load and execute falcon (sec2) firmware images; handle the GSP falcon processor and fwsec loading.h]htInfrastructure to load and execute falcon (sec2) firmware images; handle the GSP falcon processor and fwsec loading.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]boot-falcon-controllerah ]h"]boot falcon controllerah$]h&]uh1hhj3hhhhhKubh)}(hhh](h)}(hGPU Timer supporth]hGPU Timer support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h0Support for the GPU's internal timer peripheral.h]h2Support for the GPU’s internal timer peripheral.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhMubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]gpu-timer-supportah ]h"]gpu timer supportah$]h&]uh1hhj3hhhhhKubh)}(hhh](h)}(hMMU / PT managementh]hMMU / PT management}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj( hhhhhMubh)}(h:Work out the architecture for MMU / page table management.h]h:Work out the architecture for MMU / page table management.}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj( hhubh)}(hWe need to consider that nova-drm will need rather fine-grained control, especially in terms of locking, in order to be able to implement asynchronous Vulkan queues.h]hWe need to consider that nova-drm will need rather fine-grained control, especially in terms of locking, in order to be able to implement asynchronous Vulkan queues.}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj( hhubh)}(hWhile generally sharing the corresponding code is desirable, it needs to be evaluated how (and if at all) sharing the corresponding code is expedient.h]hWhile generally sharing the corresponding code is desirable, it needs to be evaluated how (and if at all) sharing the corresponding code is expedient.}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj( hhubj)}(hhh]j)}(hComplexity: Experth]hComplexity: Expert}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjc hhhhhMubah}(h]h ]h"]h$]h&]uh1jhj( hhhhhMubeh}(h]mmu-pt-managementah ]h"]mmu / pt managementah$]h&]uh1hhj3hhhhhMubh)}(hhh](h)}(hVRAM memory allocatorh]hVRAM memory allocator}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(h0Investigate options for a VRAM memory allocator.h]h0Investigate options for a VRAM memory allocator.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubhdefinition_list)}(hhh]hdefinition_list_item)}(h}Some possible options: - Rust abstractions for - RB tree (interval tree) / drm_mm - maple_tree - native Rust collections h](hterm)}(hSome possible options:h]hSome possible options:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhj ubh definition)}(hhh]h)}(hhh](h)}(hERust abstractions for - RB tree (interval tree) / drm_mm - maple_treeh]h)}(hERust abstractions for - RB tree (interval tree) / drm_mm - maple_treeh]hERust abstractions for - RB tree (interval tree) / drm_mm - maple_tree}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(hnative Rust collections h]h)}(hnative Rust collectionsh]hnative Rust collections}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]jjuh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj hhhNhNubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubah}(h]h ]h"]h$]h&]uh1jhj hhhhhMubeh}(h]vram-memory-allocatorah ]h"]vram memory allocatorah$]h&]uh1hhj3hhhhhMubh)}(hhh](h)}(hInstance Memoryh]hInstance Memory}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+ hhhhhMubh)}(h?Implement support for instmem (bar2) used to store page tables.h]h?Implement support for instmem (bar2) used to store page tables.}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj+ hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjJ hhhhhM"ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjJ hhhhhM#ubeh}(h]h ]h"]h$]h&]uh1jhj+ hhhhhM"ubeh}(h]instance-memoryah ]h"]instance memoryah$]h&]uh1hhj3hhhhhMubeh}(h] gpu-generalah ]h"] gpu (general)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hGPU System Processor (GSP)h]hGPU System Processor (GSP)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM&ubh)}(hhh](h)}(hExport GSP log buffersh]hExport GSP log buffers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM)ubh)}(hRecent patches from Timur Tabi [1] added support to expose GSP-RM log buffers (even after failure to probe the driver) through debugfs.h]hRecent patches from Timur Tabi [1] added support to expose GSP-RM log buffers (even after failure to probe the driver) through debugfs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj hhubh)}(hPThis is also an interesting feature for nova-core, especially in the early days.h]hPThis is also an interesting feature for nova-core, especially in the early days.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hj hhubj)}(hhh](j)}(hSLink: https://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/ [1]h](hLink: }(hj hhhNhNubj)}(hIhttps://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/h]hIhttps://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj ubh [1]}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM0ubj)}(hReference: Debugfs abstractionsh]hReference: Debugfs abstractions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM1ubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM2ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhM0ubeh}(h]export-gsp-log-buffersah ]h"]export gsp log buffersah$]h&]uh1hhj hhhhhM)ubh)}(hhh](h)}(hGSP firmware abstractionh]hGSP firmware abstraction}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM5ubh)}(hThe GSP-RM firmware API is unstable and may incompatibly change from version to version, in terms of data structures and semantics.h]hThe GSP-RM firmware API is unstable and may incompatibly change from version to version, in terms of data structures and semantics.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj hhubh)}(hThis problem is one of the big motivations for using Rust for nova-core, since it turns out that Rust's procedural macro feature provides a rather elegant way to address this issue:h]hThis problem is one of the big motivations for using Rust for nova-core, since it turns out that Rust’s procedural macro feature provides a rather elegant way to address this issue:}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hj hhubhenumerated_list)}(hhh](h)}(hOgenerate Rust structures from the C headers in a separate namespace per versionh]h)}(hj? h]hOgenerate Rust structures from the C headers in a separate namespace per version}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj= ubah}(h]h ]h"]h$]h&]uh1hhj: hhhhhNubh)}(hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiersh]h)}(hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiersh]hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiers}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hjT ubah}(h]h ]h"]h$]h&]uh1hhj: hhhhhNubh)}(h`use a procedural macro to generate the actual per version implementation out of this abstractionh]h)}(h`use a procedural macro to generate the actual per version implementation out of this abstractionh]h`use a procedural macro to generate the actual per version implementation out of this abstraction}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMBhjl ubah}(h]h ]h"]h$]h&]uh1hhj: hhhhhNubh)}(hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it's defined by a common trait) h]h)}(hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it's defined by a common trait)h]hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it’s defined by a common trait)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhj ubah}(h]h ]h"]h$]h&]uh1hhj: hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j8 hj hhhhhM>ubh)}(hZThere is a PoC implementation of this pattern, in the context of the nova-core PoC driver.h]hZThere is a PoC implementation of this pattern, in the context of the nova-core PoC driver.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhj hhubh)}(hhThis task aims at refining the feature and ideally generalize it, to be usable by other drivers as well.h]hhThis task aims at refining the feature and ideally generalize it, to be usable by other drivers as well.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhj hhubj)}(hhh]j)}(hComplexity: Experth]hComplexity: Expert}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMMubah}(h]h ]h"]h$]h&]uh1jhj hhhhhMMubeh}(h]gsp-firmware-abstractionah ]h"]gsp firmware abstractionah$]h&]uh1hhj hhhhhM5ubh)}(hhh](h)}(hGSP message queueh]hGSP message queue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMPubh)}(hlImplement low level GSP message queue (command, status) for communication between the kernel driver and GSP.h]hlImplement low level GSP message queue (command, status) for communication between the kernel driver and GSP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMUubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMVubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMUubeh}(h]gsp-message-queueah ]h"]gsp message queueah$]h&]uh1hhj hhhhhMPubh)}(hhh](h)}(h Bootstrap GSPh]h Bootstrap GSP}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj. hhhhhMYubh)}(hSCall the boot firmware to boot the GSP processor; execute initial control messages.h]hSCall the boot firmware to boot the GSP processor; execute initial control messages.}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hj. hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjM hhhhhM^ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjM hhhhhM_ubeh}(h]h ]h"]h$]h&]uh1jhj. hhhhhM^ubeh}(h] bootstrap-gspah ]h"] bootstrap gspah$]h&]uh1hhj hhhhhMYubh)}(hhh](h)}(hClient / Device APIsh]hClient / Device APIs}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjz hhhhhMbubh)}(h{Implement the GSP message interface for client / device allocation and the corresponding client and device allocation APIs.h]h{Implement the GSP message interface for client / device allocation and the corresponding client and device allocation APIs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhjz hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMgubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMhubeh}(h]h ]h"]h$]h&]uh1jhjz hhhhhMgubeh}(h]client-device-apisah ]h"]client / device apisah$]h&]uh1hhj hhhhhMbubh)}(hhh](h)}(hBar PDE handlingh]hBar PDE handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMkubh)}(hKSynchronize page table handling for BARs between the kernel driver and GSP.h]hKSynchronize page table handling for BARs between the kernel driver and GSP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhj hhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMoubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMpubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMoubeh}(h]bar-pde-handlingah ]h"]bar pde handlingah$]h&]uh1hhj hhhhhMkubh)}(hhh](h)}(h FIFO engineh]h FIFO engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMsubh)}(hImplement support for the FIFO engine, i.e. the corresponding GSP message interface and provide an API for chid allocation and channel handling.h]hImplement support for the FIFO engine, i.e. the corresponding GSP message interface and provide an API for chid allocation and channel handling.}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj1 hhhhhMxubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj1 hhhhhMyubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMxubeh}(h] fifo-engineah ]h"] fifo engineah$]h&]uh1hhj hhhhhMsubh)}(hhh](h)}(h GR engineh]h GR engine}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^ hhhhhM|ubh)}(hImplement support for the graphics engine, i.e. the corresponding GSP message interface and provide an API for (golden) context creation and promotion.h]hImplement support for the graphics engine, i.e. the corresponding GSP message interface and provide an API for (golden) context creation and promotion.}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hj^ hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj} hhhhhMubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj} hhhhhMubeh}(h]h ]h"]h$]h&]uh1jhj^ hhhhhMubeh}(h] gr-engineah ]h"] gr engineah$]h&]uh1hhj hhhhhM|ubh)}(hhh](h)}(h CE engineh]h CE engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hTImplement support for the copy engine, i.e. the corresponding GSP message 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