sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/gpu/nova/core/todomodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/gpu/nova/core/todomodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)h]h*SPDX-License-Identifier: (GPL-2.0+ OR MIT)}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/gpu/nova/core/todo.rsthKubhsection)}(hhh](htitle)}(h Task Listh]h Task List}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h$Tasks may have the following fields:h]h$Tasks may have the following fields:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(h``Complexity``: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.h]h)}(h``Complexity``: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.h](hliteral)}(h``Complexity``h]h Complexity}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh: Describes the required familiarity with Rust and / or the corresponding kernel APIs or subsystems. There are four different complexities, }(hhhhhNhNubh)}(h ``Beginner``h]hBeginner}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh, }(hhhhhNhNubh)}(h``Intermediate``h]h Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh, }hhsbh)}(h ``Advanced``h]hAdvanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh and }(hhhhhNhNubh)}(h ``Expert``h]hExpert}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h)``Reference``: References to other tasks.h]h)}(hjRh](h)}(h ``Reference``h]h Reference}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubh: References to other tasks.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjPubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h&``Link``: Links to external resources.h]h)}(hjwh](h)}(h``Link``h]hLink}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyubh: Links to external resources.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjuubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hV``Contact``: The person that can be contacted for further information about the task. h]h)}(hU``Contact``: The person that can be contacted for further information about the task.h](h)}(h ``Contact``h]hContact}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhJ: The person that can be contacted for further information about the task.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK hhhhubh)}(h}A task might have `[ABCD]` code after its name. This code can be used to grep into the code for `TODO` entries related to it.h](hA task might have }(hjhhhNhNubhtitle_reference)}(h`[ABCD]`h]h[ABCD]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhF code after its name. This code can be used to grep into the code for }(hjhhhNhNubj)}(h`TODO`h]hTODO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh entries related to it.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hEnablement (Rust)h]hEnablement (Rust)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hbTasks that are not directly related to nova-core, but are preconditions in terms of required APIs.h]hbTasks that are not directly related to nova-core, but are preconditions in terms of required APIs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hFromPrimitive API [FPRI]h]hFromPrimitive API [FPRI]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hSSometimes the need arises to convert a number to a value of an enum or a structure.h]hSSometimes the need arises to convert a number to a value of an enum or a structure.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXoA good example from nova-core would be the ``Chipset`` enum type, which defines the value ``AD102``. When probing the GPU the value ``0x192`` can be read from a certain register indication the chipset AD102. Hence, the enum value ``AD102`` should be derived from the number ``0x192``. Currently, nova-core uses a custom implementation (``Chipset::from_u32`` for this.h](h+A good example from nova-core would be the }(hj:hhhNhNubh)}(h ``Chipset``h]hChipset}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh$ enum type, which defines the value }(hj:hhhNhNubh)}(h ``AD102``h]hAD102}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh!. When probing the GPU the value }(hj:hhhNhNubh)}(h ``0x192``h]h0x192}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubhY can be read from a certain register indication the chipset AD102. Hence, the enum value }(hj:hhhNhNubh)}(h ``AD102``h]hAD102}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh# should be derived from the number }(hj:hhhNhNubh)}(h ``0x192``h]h0x192}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh5. Currently, nova-core uses a custom implementation (}(hj:hhhNhNubh)}(h``Chipset::from_u32``h]hChipset::from_u32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh for this.}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjhhubh)}(hiInstead, it would be desirable to have something like the ``FromPrimitive`` trait [1] from the num crate.h](h:Instead, it would be desirable to have something like the }(hjhhhNhNubh)}(h``FromPrimitive``h]h FromPrimitive}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh trait [1] from the num crate.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubh)}(hHaving this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number.h]hHaving this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjhhubh line_block)}(hhh](hh)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hindentKhjhhhhhK,ubj)}(h=Link: https://docs.rs/num/latest/num/trait.FromPrimitive.htmlh](hLink: }(hjhhhNhNubh reference)}(h7https://docs.rs/num/latest/num/trait.FromPrimitive.htmlh]h7https://docs.rs/num/latest/num/trait.FromPrimitive.html}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhK-ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhK,ubeh}(h]fromprimitive-api-fpriah ]h"]fromprimitive api [fpri]ah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h#Generic register abstraction [REGA]h]h#Generic register abstraction [REGA]}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhK0ubh)}(hiWork out how register constants and structures can be automatically generated through generalized macros.h]hiWork out how register constants and structures can be automatically generated through generalized macros.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hj$hhubh)}(hExample:h]hExample:}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hj$hhubh literal_block)}(hregister!(BOOT0, 0x0, u32, pci::Bar, Fields [ MINOR_REVISION(3:0, RO), MAJOR_REVISION(7:4, RO), REVISION(7:0, RO), // Virtual register combining major and minor rev. ])h]hregister!(BOOT0, 0x0, u32, pci::Bar, Fields [ MINOR_REVISION(3:0, RO), MAJOR_REVISION(7:4, RO), REVISION(7:0, RO), // Virtual register combining major and minor rev. ])}hjSsbah}(h]h ]h"]h$]h&]hhforcelanguagerusthighlight_args}uh1jQhhhK7hj$hhubh)}(h$This could expand to something like:h]h$This could expand to something like:}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hj$hhubjR)}(hXconst BOOT0_OFFSET: usize = 0x00000000; const BOOT0_MINOR_REVISION_SHIFT: u8 = 0; const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f; const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4; const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0; const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT; const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK | BOOT0_MAJOR_REVISION_MASK; struct Boot0(u32); impl Boot0 { #[inline] fn read(bar: &RevocableGuard<'_, pci::Bar>) -> Self { Self(bar.readl(BOOT0_OFFSET)) } #[inline] fn minor_revision(&self) -> u32 { (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT } #[inline] fn major_revision(&self) -> u32 { (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT } #[inline] fn revision(&self) -> u32 { (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT } }h]hXconst BOOT0_OFFSET: usize = 0x00000000; const BOOT0_MINOR_REVISION_SHIFT: u8 = 0; const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f; const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4; const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0; const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT; const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK | BOOT0_MAJOR_REVISION_MASK; struct Boot0(u32); impl Boot0 { #[inline] fn read(bar: &RevocableGuard<'_, pci::Bar>) -> Self { Self(bar.readl(BOOT0_OFFSET)) } #[inline] fn minor_revision(&self) -> u32 { (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT } #[inline] fn major_revision(&self) -> u32 { (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT } #[inline] fn revision(&self) -> u32 { (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT } }}hjtsbah}(h]h ]h"]h$]h&]hhjajbrustjd}uh1jQhhhKAhj$hhubh)}(hUsage:h]hUsage:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchj$hhubjR)}(hwlet bar = bar.try_access().ok_or(ENXIO)?; let boot0 = Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision());h]hwlet bar = bar.try_access().ok_or(ENXIO)?; let boot0 = Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision());}hjsbah}(h]h ]h"]h$]h&]hhjajbrustjd}uh1jQhhhKehj$hhubh)}(hXA work-in-progress implementation currently resides in `drivers/gpu/nova-core/regs/macros.rs` and is used in nova-core. It would be nice to improve it (possibly using proc macros) and move it to the `kernel` crate so it can be used by other components as well.h](h7A work-in-progress implementation currently resides in }(hjhhhNhNubj)}(h&`drivers/gpu/nova-core/regs/macros.rs`h]h$drivers/gpu/nova-core/regs/macros.rs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhj and is used in nova-core. It would be nice to improve it (possibly using proc macros) and move it to the }(hjhhhNhNubj)}(h`kernel`h]hkernel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh5 crate so it can be used by other components as well.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKlhj$hhubh)}(h%Features desired before this happens:h]h%Features desired before this happens:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhj$hhubh)}(hhh](h)}(h@Make I/O optional I/O (for field values that are not registers),h]h)}(hjh]h@Make I/O optional I/O (for field values that are not registers),}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hSupport other sizes than `u32`,h]h)}(hjh](hSupport other sizes than }(hjhhhNhNubj)}(h`u32`h]hu32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh,}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKthjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h=Allow visibility control for registers and individual fields,h]h)}(hj'h]h=Allow visibility control for registers and individual fields,}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhj%ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h0Use Rust slice syntax to express fields ranges. h]h)}(h/Use Rust slice syntax to express fields ranges.h]h/Use Rust slice syntax to express fields ranges.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhj<ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j*uh1hhhhKshj$hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj[hhhhhKxubj)}(hContact: Alexandre Courboth]hContact: Alexandre Courbot}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj[hhhhhKyubeh}(h]h ]h"]h$]h&]uh1jhj$hhhhhKxubeh}(h]!generic-register-abstraction-regaah ]h"]#generic register abstraction [rega]ah$]h&]uh1hhjhhhhhK0ubh)}(hhh](h)}(hNumerical operations [NUMM]h]hNumerical operations [NUMM]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK|ubh)}(hNova uses integer operations that are not part of the standard library (or not implemented in an optimized way for the kernel). These include:h]hNova uses integer operations that are not part of the standard library (or not implemented in an optimized way for the kernel). These include:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hjhhubh)}(hhh]h)}(hPThe "Find Last Set Bit" (`fls` function of the C part of the kernel) operation. h]h)}(hOThe "Find Last Set Bit" (`fls` function of the C part of the kernel) operation.h](hThe “Find Last Set Bit” (}(hjhhhNhNubj)}(h`fls`h]hfls}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh1 function of the C part of the kernel) operation.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubah}(h]h ]h"]h$]h&]jjuh1hhhhKhjhhubh)}(hIA `num` core kernel module is being designed to provide these operations.h](hA }(hjhhhNhNubj)}(h`num`h]hnum}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhB core kernel module is being designed to provide these operations.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hContact: Alexandre Courboth]hContact: Alexandre Courbot}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]numerical-operations-nummah ]h"]numerical operations [numm]ah$]h&]uh1hhjhhhhhK|ubh)}(hhh](h)}(hIRQ abstractionsh]hIRQ abstractions}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhKubh)}(h#Rust abstractions for IRQ handling.h]h#Rust abstractions for IRQ handling.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj'hhubh)}(haThere is active ongoing work from Daniel Almeida [1] for the "core" abstractions to request IRQs.h]heThere is active ongoing work from Daniel Almeida [1] for the “core” abstractions to request IRQs.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj'hhubh)}(hBesides optional review and testing work, the required ``pci::Device`` code around those core abstractions needs to be worked out.h](h7Besides optional review and testing work, the required }(hjThhhNhNubh)}(h``pci::Device``h]h pci::Device}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubh< code around those core abstractions needs to be worked out.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj'hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjthhhhhKubj)}(h[Link: https://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/ [1]h](hLink: }(hjhhhNhNubj)}(hQhttps://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/h]hQhttps://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubh [1]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjthhhhhKubj)}(hContact: Daniel Almeidah]hContact: Daniel Almeida}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjthhhhhKubeh}(h]h ]h"]h$]h&]uh1jhj'hhhhhKubeh}(h]irq-abstractionsah ]h"]irq abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h"Page abstraction for foreign pagesh]h"Page abstraction for foreign pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h^Rust abstractions for pages not created by the Rust page abstraction without direct ownership.h]h^Rust abstractions for pages not created by the Rust page abstraction without direct ownership.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hBThere is active onging work from Abdiel Janulgue [1] and Lina [2].h]hBThere is active onging work from Abdiel Janulgue [1] and Lina [2].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(h]Link: https://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/ [1]h](hLink: }(hjhhhNhNubj)}(hShttps://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/h]hShttps://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhjubh [1]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hdLink: https://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/ [2]h](hLink: }(hj!hhhNhNubj)}(hZhttps://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/h]hZhttps://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/}(hj)hhhNhNubah}(h]h ]h"]h$]h&]refurij+uh1jhj!ubh [2]}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]"page-abstraction-for-foreign-pagesah ]h"]"page abstraction for foreign pagesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h#Scatterlist / sg_table abstractionsh]h#Scatterlist / sg_table abstractions}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhhhhhKubh)}(h-Rust abstractions for scatterlist / sg_table.h]h-Rust abstractions for scatterlist / sg_table.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjPhhubh)}(h[There is preceding work from Abdiel Janulgue, which hasn't made it to the mailing list yet.h]h]There is preceding work from Abdiel Janulgue, which hasn’t made it to the mailing list yet.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjPhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj}hhhhhKubj)}(hContact: Abdiel Janulgueh]hContact: Abdiel Janulgue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj}hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjPhhhhhKubeh}(h]!scatterlist-sg-table-abstractionsah ]h"]#scatterlist / sg_table abstractionsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h PCI MISC APIsh]h PCI MISC APIs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hoExtend the existing PCI device / driver abstractions by SR-IOV, config space, capability, MSI API abstractions.h]hoExtend the existing PCI device / driver abstractions by SR-IOV, config space, capability, MSI API abstractions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh]j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h] pci-misc-apisah ]h"] pci misc apisah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hXArray bindings [XARR]h]hXArray bindings [XARR]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h`We need bindings for `xa_alloc`/`xa_alloc_cyclic` in order to generate the auxiliary device IDs.h](hWe need bindings for }(hjhhhNhNubj)}(h `xa_alloc`h]hxa_alloc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh/}(hjhhhNhNubj)}(h`xa_alloc_cyclic`h]hxa_alloc_cyclic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh/ in order to generate the auxiliary device IDs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh]j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj+hhhhhKubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]xarray-bindings-xarrah ]h"]xarray bindings [xarr]ah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hDebugfs abstractionsh]hDebugfs abstractions}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhhhhhKubh)}(h"Rust abstraction for debugfs APIs.h]h"Rust abstraction for debugfs APIs.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJhhubj)}(hhh](j)}(h!Reference: Export GSP log buffersh]h!Reference: Export GSP log buffers}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjihhhhhKubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjihhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjJhhhhhKubeh}(h]debugfs-abstractionsah ]h"]debugfs abstractionsah$]h&]uh1hhjhhhhhKubeh}(h]enablement-rustah ]h"]enablement (rust)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h GPU (general)h]h GPU (general)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hInitial Devinit supporth]hInitial Devinit support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hUImplement BIOS Device Initialization, i.e. memory sizing, waiting, PLL configuration.h]hUImplement BIOS Device Initialization, i.e. memory sizing, waiting, PLL configuration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubj)}(hComplexity: Beginnerh]hComplexity: Beginner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]initial-devinit-supportah ]h"]initial devinit supportah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hMMU / PT managementh]hMMU / PT management}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h:Work out the architecture for MMU / page table management.h]h:Work out the architecture for MMU / page table management.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hWe need to consider that nova-drm will need rather fine-grained control, especially in terms of locking, in order to be able to implement asynchronous Vulkan queues.h]hWe need to consider that nova-drm will need rather fine-grained control, especially in terms of locking, in order to be able to implement asynchronous Vulkan queues.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hWhile generally sharing the corresponding code is desirable, it needs to be evaluated how (and if at all) sharing the corresponding code is expedient.h]hWhile generally sharing the corresponding code is desirable, it needs to be evaluated how (and if at all) sharing the corresponding code is expedient.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh]j)}(hComplexity: Experth]hComplexity: Expert}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj6hhhhhKubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]mmu-pt-managementah ]h"]mmu / pt managementah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hVRAM memory allocatorh]hVRAM memory allocator}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhhhhhKubh)}(h0Investigate options for a VRAM memory allocator.h]h0Investigate options for a VRAM memory allocator.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjUhhubhdefinition_list)}(hhh]hdefinition_list_item)}(h}Some possible options: - Rust abstractions for - RB tree (interval tree) / drm_mm - maple_tree - native Rust collections h](hterm)}(hSome possible options:h]hSome possible options:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj{ubh definition)}(hhh]h)}(hhh](h)}(hERust abstractions for - RB tree (interval tree) / drm_mm - maple_treeh]h)}(hERust abstractions for - RB tree (interval tree) / drm_mm - maple_treeh]hERust abstractions for - RB tree (interval tree) / drm_mm - maple_tree}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hnative Rust collections h]h)}(hnative Rust collectionsh]hnative Rust collections}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jjuh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jyhhhKhjvubah}(h]h ]h"]h$]h&]uh1jthjUhhhNhNubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhhhKubah}(h]h ]h"]h$]h&]uh1jhjUhhhhhKubeh}(h]vram-memory-allocatorah ]h"]vram memory allocatorah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hInstance Memoryh]hInstance Memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h?Implement support for instmem (bar2) used to store page tables.h]h?Implement support for instmem (bar2) used to store page tables.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhKubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhKubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhKubeh}(h]instance-memoryah ]h"]instance memoryah$]h&]uh1hhjhhhhhKubeh}(h] gpu-generalah ]h"] gpu (general)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hGPU System Processor (GSP)h]hGPU System Processor (GSP)}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR hhhhhKubh)}(hhh](h)}(hExport GSP log buffersh]hExport GSP log buffers}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjc hhhhhKubh)}(hRecent patches from Timur Tabi [1] added support to expose GSP-RM log buffers (even after failure to probe the driver) through debugfs.h]hRecent patches from Timur Tabi [1] added support to expose GSP-RM log buffers (even after failure to probe the driver) through debugfs.}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjc hhubh)}(hPThis is also an interesting feature for nova-core, especially in the early days.h]hPThis is also an interesting feature for nova-core, especially in the early days.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjc hhubj)}(hhh](j)}(hSLink: https://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/ [1]h](hLink: }(hj hhhNhNubj)}(hIhttps://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/h]hIhttps://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi@nvidia.com/}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj ubh [1]}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubj)}(hReference: Debugfs abstractionsh]hReference: Debugfs abstractions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubj)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubeh}(h]h ]h"]h$]h&]uh1jhjc hhhhhMubeh}(h]export-gsp-log-buffersah ]h"]export gsp log buffersah$]h&]uh1hhjR hhhhhKubh)}(hhh](h)}(hGSP firmware abstractionh]hGSP firmware abstraction}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hThe GSP-RM firmware API is unstable and may incompatibly change from version to version, in terms of data structures and semantics.h]hThe GSP-RM firmware API is unstable and may incompatibly change from version to version, in terms of data structures and semantics.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hThis problem is one of the big motivations for using Rust for nova-core, since it turns out that Rust's procedural macro feature provides a rather elegant way to address this issue:h]hThis problem is one of the big motivations for using Rust for nova-core, since it turns out that Rust’s procedural macro feature provides a rather elegant way to address this issue:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj hhubhenumerated_list)}(hhh](h)}(hOgenerate Rust structures from the C headers in a separate namespace per versionh]h)}(hj h]hOgenerate Rust structures from the C headers in a separate namespace per version}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiersh]h)}(hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiersh]hbuild abstraction structures (within a generic namespace) that implement the firmware interfaces; annotate the differences in implementation with version identifiers}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj' ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(h`use a procedural macro to generate the actual per version implementation out of this abstractionh]h)}(h`use a procedural macro to generate the actual per version implementation out of this abstractionh]h`use a procedural macro to generate the actual per version implementation out of this abstraction}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj? ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it's defined by a common trait) h]h)}(hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it's defined by a common trait)h]hinstantiate the correct version type one on runtime (can be sure that all have the same interface because it’s defined by a common trait)}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjW ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j hj hhhhhMubh)}(hZThere is a PoC implementation of this pattern, in the context of the nova-core PoC driver.h]hZThere is a PoC implementation of this pattern, in the context of the nova-core PoC driver.}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hhThis task aims at refining the feature and ideally generalize it, to be usable by other drivers as well.h]hhThis task aims at refining the feature and ideally generalize it, to be usable by other drivers as well.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hhh]j)}(hComplexity: Experth]hComplexity: Expert}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMubah}(h]h ]h"]h$]h&]uh1jhj hhhhhMubeh}(h]gsp-firmware-abstractionah ]h"]gsp firmware abstractionah$]h&]uh1hhjR hhhhhMubh)}(hhh](h)}(hGSP message queueh]hGSP message queue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM!ubh)}(hlImplement low level GSP message queue (command, status) for communication between the kernel driver and GSP.h]hlImplement low level GSP message queue (command, status) for communication between the kernel driver and GSP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hj hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM&ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM'ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhM&ubeh}(h]gsp-message-queueah ]h"]gsp message queueah$]h&]uh1hhjR hhhhhM!ubh)}(hhh](h)}(h Bootstrap GSPh]h Bootstrap GSP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM*ubh)}(hSCall the boot firmware to boot the GSP processor; execute initial control messages.h]hSCall the boot firmware to boot the GSP processor; execute initial control messages.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hj hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM/ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM0ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhM/ubeh}(h] bootstrap-gspah ]h"] bootstrap gspah$]h&]uh1hhjR hhhhhM*ubh)}(hhh](h)}(hClient / Device APIsh]hClient / Device APIs}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM hhhhhM3ubh)}(h{Implement the GSP message interface for client / device allocation and the corresponding client and device allocation APIs.h]h{Implement the GSP message interface for client / device allocation and the corresponding client and device allocation APIs.}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hjM hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjl hhhhhM8ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjl hhhhhM9ubeh}(h]h ]h"]h$]h&]uh1jhjM hhhhhM8ubeh}(h]client-device-apisah ]h"]client / device apisah$]h&]uh1hhjR hhhhhM3ubh)}(hhh](h)}(hBar PDE handlingh]hBar PDE handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM<ubh)}(hKSynchronize page table handling for BARs between the kernel driver and GSP.h]hKSynchronize page table handling for BARs between the kernel driver and GSP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj hhubj)}(hhh](j)}(hComplexity: Beginnerh]hComplexity: Beginner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM@ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMAubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhM@ubeh}(h]bar-pde-handlingah ]h"]bar pde handlingah$]h&]uh1hhjR hhhhhM<ubh)}(hhh](h)}(h FIFO engineh]h FIFO engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMDubh)}(hImplement support for the FIFO engine, i.e. the corresponding GSP message interface and provide an API for chid allocation and channel handling.h]hImplement support for the FIFO engine, i.e. the corresponding GSP message interface and provide an API for chid allocation and channel handling.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMIubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMJubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMIubeh}(h] fifo-engineah ]h"] fifo engineah$]h&]uh1hhjR hhhhhMDubh)}(hhh](h)}(h GR engineh]h GR engine}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1 hhhhhMMubh)}(hImplement support for the graphics engine, i.e. the corresponding GSP message interface and provide an API for (golden) context creation and promotion.h]hImplement support for the graphics engine, i.e. the corresponding GSP message interface and provide an API for (golden) context creation and promotion.}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhj1 hhubj)}(hhh](j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjP hhhhhMRubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjP hhhhhMSubeh}(h]h ]h"]h$]h&]uh1jhj1 hhhhhMRubeh}(h] gr-engineah ]h"] gr engineah$]h&]uh1hhjR hhhhhMMubh)}(hhh](h)}(h CE engineh]h CE engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj} hhhhhMVubh)}(hTImplement support for the copy engine, i.e. the corresponding GSP message interface.h]hTImplement support for the copy engine, i.e. the corresponding GSP message interface.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhj} hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM[ubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM\ubeh}(h]h ]h"]h$]h&]uh1jhj} hhhhhM[ubeh}(h] ce-engineah ]h"] ce engineah$]h&]uh1hhjR hhhhhMVubh)}(hhh](h)}(hVFN IRQ controllerh]hVFN IRQ controller}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM_ubh)}(h)Support for the VFN interrupt controller.h]h)Support for the VFN interrupt controller.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahj hhubj)}(hhh](j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMcubj)}(hContact: Dave Airlieh]hContact: Dave Airlie}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMdubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMcubeh}(h]vfn-irq-controllerah ]h"]vfn irq controllerah$]h&]uh1hhjR hhhhhM_ubeh}(h]gpu-system-processor-gspah ]h"]gpu system processor (gsp)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h External APIsh]h External APIs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMgubh)}(hhh](h)}(hnova-core base APIh]hnova-core base API}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj. hhhhhMjubh)}(hcWork out the common pieces of the API to connect 2nd level drivers, i.e. vGPU manager and nova-drm.h]hcWork out the common pieces of the API to connect 2nd level drivers, i.e. vGPU manager and nova-drm.}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhj. hhubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjM hhhhhMoubah}(h]h ]h"]h$]h&]uh1jhj. hhhhhMoubeh}(h]nova-core-base-apiah ]h"]nova-core base apiah$]h&]uh1hhj hhhhhMjubh)}(hhh](h)}(hvGPU manager APIh]hvGPU manager API}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl hhhhhMrubh)}(h[Work out the API parts required by the vGPU manager, which are not covered by the base API.h]h[Work out the API parts required by the vGPU manager, which are not covered by the base API.}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthjl hhubj)}(hhh]j)}(hComplexity: Advancedh]hComplexity: Advanced}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhMwubah}(h]h ]h"]h$]h&]uh1jhjl hhhhhMwubeh}(h]vgpu-manager-apiah ]h"]vgpu manager apiah$]h&]uh1hhj hhhhhMrubh)}(hhh](h)}(hnova-core C APIh]hnova-core C API}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMzubh)}(hGImplement a C wrapper for the APIs required by the vGPU manager driver.h]hGImplement a C wrapper for the APIs required by the vGPU manager driver.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hj hhubj)}(hhh]j)}(hComplexity: Intermediateh]hComplexity: Intermediate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhhhM~ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhM~ubeh}(h]nova-core-c-apiah ]h"]nova-core c apiah$]h&]uh1hhj hhhhhMzubeh}(h] external-apisah ]h"] external apisah$]h&]uh1hhhhhhhhMgubh)}(hhh](h)}(hTestingh]hTesting}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(h CI pipelineh]h CI pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h6Investigate option for continuous integration testing.h]h6Investigate option for continuous integration testing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hThis can go from as simple as running KUnit tests over running (graphics) CTS to booting up (multiple) guest VMs to test VFIO use-cases.h]hThis can go from as simple as running KUnit tests over running (graphics) CTS to booting up (multiple) guest VMs to test VFIO use-cases.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hIt might also be worth to consider the introduction of a new test suite directly sitting on top of the uAPI for more targeted testing and debugging. There may be options for collaboration / shared code with the Mesa project.h]hIt might also be worth to consider the introduction of a new test suite directly sitting on top of the uAPI for more targeted testing and debugging. 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