€•ÞF      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ(/translations/zh_CN/gpu/nova/core/pramin”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/zh_TW/gpu/nova/core/pramin”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/it_IT/gpu/nova/core/pramin”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/ja_JP/gpu/nova/core/pramin”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/ko_KR/gpu/nova/core/pramin”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/pt_BR/gpu/nova/core/pramin”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/sp_SP/gpu/nova/core/pramin”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³ŒB/var/lib/git/docbuild/linux/Documentation/gpu/nova/core/pramin.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒPRAMIN aperture mechanism”h]”hŒPRAMIN aperture mechanism”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒnote”“”)”}”(hŒ®The following description is approximate and current as of the Ampere
family. It may change for future generations and is intended to assist in
understanding the driver code.”h]”hŒ	paragraph”“”)”}”(hŒ®The following description is approximate and current as of the Ampere
family. It may change for future generations and is intended to assist in
understanding the driver code.”h]”hŒ®The following description is approximate and current as of the Ampere
family. It may change for future generations and is intended to assist in
understanding the driver code.”…””}”(hhåh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãh³hÇh´Khhßubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhhÊh²hh³hÇh´NubhÉ)”}”(hhh]”(hÎ)”}”(hŒIntroduction”h]”hŒIntroduction”…””}”(hhüh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhùh²hh³hÇh´Kubhä)”}”(hXZ  PRAMIN is a hardware aperture mechanism that provides CPU access to GPU Video
RAM (VRAM) before the GPU's Memory Management Unit (MMU) and page tables are
initialized. This 1 MiB sliding window, located at a fixed offset within BAR0,
is essential for setting up page tables and other critical GPU data structures
without relying on the GPU's MMU.”h]”hX^  PRAMIN is a hardware aperture mechanism that provides CPU access to GPU Video
RAM (VRAM) before the GPUâ€™s Memory Management Unit (MMU) and page tables are
initialized. This 1 MiB sliding window, located at a fixed offset within BAR0,
is essential for setting up page tables and other critical GPU data structures
without relying on the GPUâ€™s MMU.”…””}”(hj
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãh³hÇh´Khhùh²hubeh}”(h]”Œintroduction”ah ]”h"]”Œintroduction”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒArchitecture Overview”h]”hŒArchitecture Overview”…””}”(hj#  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj   h²hh³hÇh´Kubhä)”}”(hŒ¯The PRAMIN aperture mechanism is logically implemented by the GPU's PBUS (PCIe
Bus Controller Unit) and provides a CPU-accessible window into VRAM through the
PCIe interface::”h]”hŒ°The PRAMIN aperture mechanism is logically implemented by the GPUâ€™s PBUS (PCIe
Bus Controller Unit) and provides a CPU-accessible window into VRAM through the
PCIe interface:”…””}”(hj1  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãh³hÇh´Khj   h²hubhŒliteral_block”“”)”}”(hXÇ  +-----------------+    PCIe     +------------------------------+
|      CPU        |<----------->|           GPU                |
+-----------------+             |                              |
                                |  +----------------------+    |
                                |  |       PBUS           |    |
                                |  |  (Bus Controller)    |    |
                                |  |                      |    |
                                |  |  +--------------+ <------------ [1]
                                |  |  |   PRAMIN     |    |    |
                                |  |  |   Window     |    |    |
                                |  |  |   (1 MiB)    |    |    |
                                |  |  +--------------+    |    |
                                |  |         |            |    |
                                |  +---------|------------+    |
                                |            |                 |
                                |            v                 |
                                |  +----------------------+ <------- [2]
                                |  |       VRAM           |    |
                                |  |    (Several GiB)     |    |
                                |  |                      |    |
                                |  |   FB[0x0000000000]   |    |
                                |  |          ...         |    |
                                |  |   FB[0xFFFFFFFFFF]   |    |
                                |  +----------------------+    |
                                +------------------------------+

[1] Window starts at BAR0 + 0x700000.
[2] Program PRAMIN to any 64 KiB-aligned VRAM boundary.”h]”hXÇ  +-----------------+    PCIe     +------------------------------+
|      CPU        |<----------->|           GPU                |
+-----------------+             |                              |
                                |  +----------------------+    |
                                |  |       PBUS           |    |
                                |  |  (Bus Controller)    |    |
                                |  |                      |    |
                                |  |  +--------------+ <------------ [1]
                                |  |  |   PRAMIN     |    |    |
                                |  |  |   Window     |    |    |
                                |  |  |   (1 MiB)    |    |    |
                                |  |  +--------------+    |    |
                                |  |         |            |    |
                                |  +---------|------------+    |
                                |            |                 |
                                |            v                 |
                                |  +----------------------+ <------- [2]
                                |  |       VRAM           |    |
                                |  |    (Several GiB)     |    |
                                |  |                      |    |
                                |  |   FB[0x0000000000]   |    |
                                |  |          ...         |    |
                                |  |   FB[0xFFFFFFFFFF]   |    |
                                |  +----------------------+    |
                                +------------------------------+

[1] Window starts at BAR0 + 0x700000.
[2] Program PRAMIN to any 64 KiB-aligned VRAM boundary.”…””}”hjA  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j?  h³hÇh´Khj   h²hubhä)”}”(hŒYPBUS is responsible for, among other things, handling MMIO
accesses to the BAR registers.”h]”hŒYPBUS is responsible for, among other things, handling MMIO
accesses to the BAR registers.”…””}”(hjO  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãh³hÇh´K9hj   h²hubeh}”(h]”Œarchitecture-overview”ah ]”h"]”Œarchitecture overview”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒPRAMIN Window Operation”h]”hŒPRAMIN Window Operation”…””}”(hjh  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhje  h²hh³hÇh´K=ubhä)”}”(hŒ›The PRAMIN window provides a 1 MiB sliding aperture that can be repositioned
over the entire VRAM address space using the ``NV_PBUS_BAR0_WINDOW`` register.”h]”(hŒzThe PRAMIN window provides a 1 MiB sliding aperture that can be repositioned
over the entire VRAM address space using the ”…””}”(hjv  h²hh³Nh´NubhŒliteral”“”)”}”(hŒ``NV_PBUS_BAR0_WINDOW``”h]”hŒNV_PBUS_BAR0_WINDOW”…””}”(hj€  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hjv  ubhŒ
 register.”…””}”(hjv  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hãh³hÇh´K?hje  h²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒWindow Control Mechanism”h]”hŒWindow Control Mechanism”…””}”(hj›  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj˜  h²hh³hÇh´KCubj@  )”}”(hX‹  NV_PBUS_BAR0_WINDOW Register (0x1700):
+-------+--------+--------------------------------------+
| 31:26 | 25:24  |               23:0                   |
| RSVD  | TARGET |            BASE_ADDR                 |
|       |        |        (bits 39:16 of VRAM address)  |
+-------+--------+--------------------------------------+

The 24-bit BASE_ADDR field encodes bits [39:16] of the target VRAM address,
providing 40-bit (1 TiB) address space coverage with 64 KiB alignment.

TARGET field (bits 25:24):
- 0x0: VRAM (Video Memory)
- 0x1: Reserved (unused)
- 0x2: SYS_MEM_COH (Coherent System Memory)
- 0x3: SYS_MEM_NONCOH (Non-coherent System Memory)”h]”hX‹  NV_PBUS_BAR0_WINDOW Register (0x1700):
+-------+--------+--------------------------------------+
| 31:26 | 25:24  |               23:0                   |
| RSVD  | TARGET |            BASE_ADDR                 |
|       |        |        (bits 39:16 of VRAM address)  |
+-------+--------+--------------------------------------+

The 24-bit BASE_ADDR field encodes bits [39:16] of the target VRAM address,
providing 40-bit (1 TiB) address space coverage with 64 KiB alignment.

TARGET field (bits 25:24):
- 0x0: VRAM (Video Memory)
- 0x1: Reserved (unused)
- 0x2: SYS_MEM_COH (Coherent System Memory)
- 0x3: SYS_MEM_NONCOH (Non-coherent System Memory)”…””}”hj©  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j?  h³hÇh´KGhj˜  h²hubhÞ)”}”(hŒ¡Nova only uses TARGET=VRAM (0x0) for video memory access. The SYS_MEM
target values are documented here for hardware completeness but are
not used by the driver.”h]”hä)”}”(hŒ¡Nova only uses TARGET=VRAM (0x0) for video memory access. The SYS_MEM
target values are documented here for hardware completeness but are
not used by the driver.”h]”hŒ¡Nova only uses TARGET=VRAM (0x0) for video memory access. The SYS_MEM
target values are documented here for hardware completeness but are
not used by the driver.”…””}”(hj»  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãh³hÇh´KXhj·  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhj˜  h²hh³hÇh´Nubeh}”(h]”Œwindow-control-mechanism”ah ]”h"]”Œwindow control mechanism”ah$]”h&]”uh1hÈhje  h²hh³hÇh´KCubhÉ)”}”(hhh]”(hÎ)”}”(hŒ64 KiB Alignment Requirement”h]”hŒ64 KiB Alignment Requirement”…””}”(hjÚ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj×  h²hh³hÇh´K]ubhä)”}”(hŒThe PRAMIN window must be aligned to 64 KiB boundaries in VRAM. This is enforced
by the ``BASE_ADDR`` field representing bits [39:16] of the target address::”h]”(hŒXThe PRAMIN window must be aligned to 64 KiB boundaries in VRAM. This is enforced
by the ”…””}”(hjè  h²hh³Nh´Nubj  )”}”(hŒ``BASE_ADDR``”h]”hŒ	BASE_ADDR”…””}”(hjð  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hjè  ubhŒ7 field representing bits [39:16] of the target address:”…””}”(hjè  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hãh³hÇh´K_hj×  h²hubj@  )”}”(hX•  VRAM Address Calculation:
actual_vram_addr = (BASE_ADDR << 16) + pramin_offset
Where:
- BASE_ADDR: 24-bit value from NV_PBUS_BAR0_WINDOW[23:0]
- pramin_offset: 20-bit offset within the PRAMIN window [0x00000-0xFFFFF]

Example Window Positioning:
+---------------------------------------------------------+
|                    VRAM Space                           |
|                                                         |
|  0x0000000000 +-----------------+ <-- 64 KiB aligned    |
|               | PRAMIN Window   |                       |
|               |    (1 MiB)      |                       |
|  0x00000FFFFF +-----------------+                       |
|                                                         |
|       |              ^                                  |
|       |              | Window can slide                 |
|       v              | to any 64 KiB-aligned boundary   |
|                                                         |
|  0x0123400000 +-----------------+ <-- 64 KiB aligned    |
|               | PRAMIN Window   |                       |
|               |    (1 MiB)      |                       |
|  0x01234FFFFF +-----------------+                       |
|                                                         |
|                       ...                               |
|                                                         |
|  0xFFFFF00000 +-----------------+ <-- 64 KiB aligned    |
|               | PRAMIN Window   |                       |
|               |    (1 MiB)      |                       |
|  0xFFFFFFFFFF +-----------------+                       |
+---------------------------------------------------------+”h]”hX•  VRAM Address Calculation:
actual_vram_addr = (BASE_ADDR << 16) + pramin_offset
Where:
- BASE_ADDR: 24-bit value from NV_PBUS_BAR0_WINDOW[23:0]
- pramin_offset: 20-bit offset within the PRAMIN window [0x00000-0xFFFFF]

Example Window Positioning:
+---------------------------------------------------------+
|                    VRAM Space                           |
|                                                         |
|  0x0000000000 +-----------------+ <-- 64 KiB aligned    |
|               | PRAMIN Window   |                       |
|               |    (1 MiB)      |                       |
|  0x00000FFFFF +-----------------+                       |
|                                                         |
|       |              ^                                  |
|       |              | Window can slide                 |
|       v              | to any 64 KiB-aligned boundary   |
|                                                         |
|  0x0123400000 +-----------------+ <-- 64 KiB aligned    |
|               | PRAMIN Window   |                       |
|               |    (1 MiB)      |                       |
|  0x01234FFFFF +-----------------+                       |
|                                                         |
|                       ...                               |
|                                                         |
|  0xFFFFF00000 +-----------------+ <-- 64 KiB aligned    |
|               | PRAMIN Window   |                       |
|               |    (1 MiB)      |                       |
|  0xFFFFFFFFFF +-----------------+                       |
+---------------------------------------------------------+”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j?  h³hÇh´Kbhj×  h²hubeh}”(h]”Œkib-alignment-requirement”ah ]”h"]”Œ64 kib alignment requirement”ah$]”h&]”uh1hÈhje  h²hh³hÇh´K]ubeh}”(h]”Œpramin-window-operation”ah ]”h"]”Œpramin window operation”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K=ubeh}”(h]”Œpramin-aperture-mechanism”ah ]”h"]”Œpramin aperture mechanism”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jQ  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j+  j(  j  j  jb  j_  j#  j   jÔ  jÑ  j  j  uŒ	nametypes”}”(j+  ‰j  ‰jb  ‰j#  ‰jÔ  ‰j  ‰uh}”(j(  hÊj  hùj_  j   j   je  jÑ  j˜  j  j×  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nh²hub.