sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget,/translations/zh_CN/gpu/nova/core/interruptsmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/zh_TW/gpu/nova/core/interruptsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/it_IT/gpu/nova/core/interruptsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ja_JP/gpu/nova/core/interruptsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ko_KR/gpu/nova/core/interruptsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/pt_BR/gpu/nova/core/interruptsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/sp_SP/gpu/nova/core/interruptsmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhF/var/lib/git/docbuild/linux/Documentation/gpu/nova/core/interrupts.rsthKubh)}(h`SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.h]h`SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(h-GPU interrupt handling: GIN and the GSP eventh]h-GPU interrupt handling: GIN and the GSP event}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThis document describes how nova-core receives interrupts from the GPU on Turing and later chipsets. It covers the GPU Interrupt and Notification unit (GIN), which is the GPU's interrupt controller, and the GSP event, the interrupt that nova-core services in normal operation.h]hXThis document describes how nova-core receives interrupts from the GPU on Turing and later chipsets. It covers the GPU Interrupt and Notification unit (GIN), which is the GPU’s interrupt controller, and the GSP event, the interrupt that nova-core services in normal operation.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThroughout, *CPU* means the CPU and the nova-core driver running on it. The GPU also has on-chip processors that run their own firmware and receive their own interrupts. The GSP (GPU System Processor) is one of them.h](h Throughout, }(hhhhhNhNubhemphasis)}(h*CPU*h]hCPU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhubh means the CPU and the nova-core driver running on it. The GPU also has on-chip processors that run their own firmware and receive their own interrupts. The GSP (GPU System Processor) is one of them.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hX|Register names are the names from the GPU hardware reference headers. The pre-Hopper headers call the controller ``NV_CTRL`` and the Hopper-plus headers call it ``NV_GIN``. This document calls it GIN throughout, because the tree that nova-core services is the same on every supported chipset. OpenRM, NVIDIA's open-source GPU kernel driver, is cited wherever nova-core follows it.h](hqRegister names are the names from the GPU hardware reference headers. The pre-Hopper headers call the controller }(hjhhhNhNubhliteral)}(h ``NV_CTRL``h]hNV_CTRL}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh% and the Hopper-plus headers call it }(hjhhhNhNubj&)}(h ``NV_GIN``h]hNV_GIN}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh. This document calls it GIN throughout, because the tree that nova-core services is the same on every supported chipset. OpenRM, NVIDIA’s open-source GPU kernel driver, is cited wherever nova-core follows it.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(h Terminologyh]h Terminology}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhhhhhKubh)}(h4The three levels of the controller, innermost first:h]h4The three levels of the controller, innermost first:}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjQhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hleaf One ``LEAF`` register. Each of its 32 bits is the pending bit of one interrupt source. A Turing, Ampere, or Ada tree has 8 leaves. A Hopper or Blackwell tree has 16. h](hterm)}(hleafh]hleaf}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKhjwubh definition)}(hhh]h)}(hOne ``LEAF`` register. Each of its 32 bits is the pending bit of one interrupt source. A Turing, Ampere, or Ada tree has 8 leaves. A Hopper or Blackwell tree has 16.h](hOne }(hjhhhNhNubj&)}(h``LEAF``h]hLEAF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh register. Each of its 32 bits is the pending bit of one interrupt source. A Turing, Ampere, or Ada tree has 8 leaves. A Hopper or Blackwell tree has 16.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1juhhhKhjrubjv)}(hsubtree Two consecutive leaves, summarized by one bit of ``TOP``. A subtree is the unit of enabling at ``TOP``, and under MSI-X it is the unit of delivery: every interrupt from one subtree arrives on one MSI-X entry. h](j|)}(hsubtreeh]hsubtree}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhK$hjubj)}(hhh]h)}(hTwo consecutive leaves, summarized by one bit of ``TOP``. A subtree is the unit of enabling at ``TOP``, and under MSI-X it is the unit of delivery: every interrupt from one subtree arrives on one MSI-X entry.h](h1Two consecutive leaves, summarized by one bit of }(hjhhhNhNubj&)}(h``TOP``h]hTOP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh'. A subtree is the unit of enabling at }(hjhhhNhNubj&)}(h``TOP``h]hTOP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubhj, and under MSI-X it is the unit of delivery: every interrupt from one subtree arrives on one MSI-X entry.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhK$hjrhhubjv)}(htree One ``TOP`` register and the leaves under it. Every PCIe function has its own tree, and nova-core services the CPU tree of one function. h](j|)}(htreeh]htree}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhK(hjubj)}(hhh]h)}(hOne ``TOP`` register and the leaves under it. Every PCIe function has its own tree, and nova-core services the CPU tree of one function.h](hOne }(hj$hhhNhNubj&)}(h``TOP``h]hTOP}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj$ubh} register and the leaves under it. Every PCIe function has its own tree, and nova-core services the CPU tree of one function.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK'hj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhK(hjrhhubeh}(h]h ]h"]h$]h&]uh1jphjQhhhhhNubh)}(hThe hardware headers, OpenRM, and the Linux PCI API all use the word "vector", each for a different number. This document gives each one its own name, and a bare "vector" always means a GIN vector.h]hThe hardware headers, OpenRM, and the Linux PCI API all use the word “vector”, each for a different number. This document gives each one its own name, and a bare “vector” always means a GIN vector.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjQhhubjq)}(hhh](jv)}(hGIN vector The GPU-internal interrupt source number. It addresses one bit of one leaf. A 16-leaf tree holds vectors 0 through 511, and an 8-leaf tree holds 0 through 255. The CPU doorbell is vector 129 and the GSP event is vector 155. h](j|)}(h GIN vectorh]h GIN vector}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhK2hjgubj)}(hhh]h)}(hThe GPU-internal interrupt source number. It addresses one bit of one leaf. A 16-leaf tree holds vectors 0 through 511, and an 8-leaf tree holds 0 through 255. The CPU doorbell is vector 129 and the GSP event is vector 155.h]hThe GPU-internal interrupt source number. It addresses one bit of one leaf. A 16-leaf tree holds vectors 0 through 511, and an 8-leaf tree holds 0 through 255. The CPU doorbell is vector 129 and the GSP event is vector 155.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjyubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1juhhhK2hjdubjv)}(hRMSI-X entry An index into the device's MSI-X table. One entry serves one subtree. h](j|)}(h MSI-X entryh]h MSI-X entry}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhK5hjubj)}(hhh]h)}(hEAn index into the device's MSI-X table. One entry serves one subtree.h]hGAn index into the device’s MSI-X table. One entry serves one subtree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhK5hjdhhubjv)}(hxPCI vector One of the interrupts that ``pci_alloc_irq_vectors()`` allocates: an MSI-X entry, or the single MSI message. h](j|)}(h PCI vectorh]h PCI vector}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhK9hjubj)}(hhh]h)}(hlOne of the interrupts that ``pci_alloc_irq_vectors()`` allocates: an MSI-X entry, or the single MSI message.h](hOne of the interrupts that }(hjhhhNhNubj&)}(h``pci_alloc_irq_vectors()``h]hpci_alloc_irq_vectors()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh6 allocates: an MSI-X entry, or the single MSI message.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhK9hjdhhubjv)}(hLinux IRQ number What ``request_irq()`` takes, obtained from ``pci_irq_vector()`` for a PCI vector. Linux's ``struct msix_entry`` calls this number ``.vector`` as well. h](j|)}(hLinux IRQ numberh]hLinux IRQ number}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhK>hjubj)}(hhh]h)}(hWhat ``request_irq()`` takes, obtained from ``pci_irq_vector()`` for a PCI vector. Linux's ``struct msix_entry`` calls this number ``.vector`` as well.h](hWhat }(hjhhhNhNubj&)}(h``request_irq()``h]h request_irq()}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh takes, obtained from }(hjhhhNhNubj&)}(h``pci_irq_vector()``h]hpci_irq_vector()}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh for a PCI vector. Linux’s }(hjhhhNhNubj&)}(h``struct msix_entry``h]hstruct msix_entry}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh calls this number }(hjhhhNhNubj&)}(h ``.vector``h]h.vector}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh as well.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubeh}(h]h ]h"]h$]h&]uh1jphjQhhhhhNubh)}(hVThe remaining terms, each named for the register or the specification that defines it:h]hVThe remaining terms, each named for the register or the specification that defines it:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjQhhubjq)}(hhh](jv)}(hJenable, disable a vector Writes to ``LEAF_EN_SET`` and ``LEAF_EN_CLEAR``. h](j|)}(henable, disable a vectorh]henable, disable a vector}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKDhjubj)}(hhh]h)}(h0Writes to ``LEAF_EN_SET`` and ``LEAF_EN_CLEAR``.h](h Writes to }(hjhhhNhNubj&)}(h``LEAF_EN_SET``h]h LEAF_EN_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh and }(hjhhhNhNubj&)}(h``LEAF_EN_CLEAR``h]h LEAF_EN_CLEAR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKDhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhKDhjubjv)}(hIenable, disable a subtree Writes to ``TOP_EN_SET`` and ``TOP_EN_CLEAR``. h](j|)}(henable, disable a subtreeh]henable, disable a subtree}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKGhjubj)}(hhh]h)}(h.Writes to ``TOP_EN_SET`` and ``TOP_EN_CLEAR``.h](h Writes to }(hjhhhNhNubj&)}(h``TOP_EN_SET``h]h TOP_EN_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh and }(hjhhhNhNubj&)}(h``TOP_EN_CLEAR``h]h TOP_EN_CLEAR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKGhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhKGhjhhubjv)}(hIserviced subtree A subtree that nova-core enables and has a handler for. h](j|)}(hserviced subtreeh]hserviced subtree}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKJhj:ubj)}(hhh]h)}(h7A subtree that nova-core enables and has a handler for.h]h7A subtree that nova-core enables and has a handler for.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjLubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1juhhhKJhjhhubjv)}(hlrearm Restoring PCI interrupt delivery after servicing an interrupt. See "Rearming PCI interrupt delivery". h](j|)}(hrearmh]hrearm}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKNhjiubj)}(hhh]h)}(heRestoring PCI interrupt delivery after servicing an interrupt. See "Rearming PCI interrupt delivery".h]hiRestoring PCI interrupt delivery after servicing an interrupt. See “Rearming PCI interrupt delivery”.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhj{ubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1juhhhKNhjhhubjv)}(hmask Reserved for the two places where hardware and the PCI specification use the word: the MSI-X per-entry Vector Control mask bit, which Linux controls, and the falcon interrupt masks. It never names a GIN enable. h](j|)}(hmaskh]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKShjubj)}(hhh]h)}(hReserved for the two places where hardware and the PCI specification use the word: the MSI-X per-entry Vector Control mask bit, which Linux controls, and the falcon interrupt masks. It never names a GIN enable.h]hReserved for the two places where hardware and the PCI specification use the word: the MSI-X per-entry Vector Control mask bit, which Linux controls, and the falcon interrupt masks. It never names a GIN enable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhKShjhhubjv)}(hlatched, pending Two names for one state, a set ``LEAF`` bit. The vector's source sets the bit whether or not the vector is enabled. h](j|)}(hlatched, pendingh]hlatched, pending}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKWhjubj)}(hhh]h)}(hsTwo names for one state, a set ``LEAF`` bit. The vector's source sets the bit whether or not the vector is enabled.h](hTwo names for one state, a set }(hjhhhNhNubj&)}(h``LEAF``h]hLEAF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubhN bit. The vector’s source sets the bit whether or not the vector is enabled.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKVhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhKWhjhhubjv)}(hwclear a vector Write a 1 to the vector's bit in ``LEAF``. OpenRM calls the same operation ``intrClearLeafVector_HAL``. h](j|)}(hclear a vectorh]hclear a vector}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhK[hjubj)}(hhh]h)}(hgWrite a 1 to the vector's bit in ``LEAF``. OpenRM calls the same operation ``intrClearLeafVector_HAL``.h](h#Write a 1 to the vector’s bit in }(hjhhhNhNubj&)}(h``LEAF``h]hLEAF}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh". OpenRM calls the same operation }(hjhhhNhNubj&)}(h``intrClearLeafVector_HAL``h]hintrClearLeafVector_HAL}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhK[hjhhubjv)}(hCpending bits The plain 32-bit value read from a ``LEAF`` register. h](j|)}(h pending bitsh]h pending bits}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhK^hj[ubj)}(hhh]h)}(h5The plain 32-bit value read from a ``LEAF`` register.h](h#The plain 32-bit value read from a }(hjphhhNhNubj&)}(h``LEAF``h]hLEAF}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjpubh register.}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK^hjmubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1juhhhK^hjhhubjv)}(hnotification An interrupt whose only content is that something happened, such as a posted message. Servicing a notification means reading what it announces. The unit that raised it needs no attention. The GSP event is one. h](j|)}(h notificationh]h notification}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKchjubj)}(hhh]h)}(hAn interrupt whose only content is that something happened, such as a posted message. Servicing a notification means reading what it announces. The unit that raised it needs no attention. The GSP event is one.h]hAn interrupt whose only content is that something happened, such as a posted message. Servicing a notification means reading what it announces. The unit that raised it needs no attention. The GSP event is one.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhKchjhhubjv)}(h}unit Any block that raises an interrupt. "Engine" is reserved for the blocks that do user work: GR, CE, NVDEC, and the like. h](j|)}(hunith]hunit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKghjubj)}(hhh]h)}(hwAny block that raises an interrupt. "Engine" is reserved for the blocks that do user work: GR, CE, NVDEC, and the like.h]h{Any block that raises an interrupt. “Engine” is reserved for the blocks that do user work: GR, CE, NVDEC, and the like.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhKghjhhubjv)}(hfalcon One of the GPU's microcontrollers (see Documentation/gpu/nova/core/falcon.rst). The GSP runs on the RISC-V core inside its falcon. A falcon latches each of its interrupt causes and routes it either to the host, meaning the CPU, or to its own core. h](j|)}(hfalconh]hfalcon}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hhhKmhjubj)}(hhh]h)}(hOne of the GPU's microcontrollers (see Documentation/gpu/nova/core/falcon.rst). The GSP runs on the RISC-V core inside its falcon. A falcon latches each of its interrupt causes and routes it either to the host, meaning the CPU, or to its own core.h]hOne of the GPU’s microcontrollers (see Documentation/gpu/nova/core/falcon.rst). The GSP runs on the RISC-V core inside its falcon. A falcon latches each of its interrupt causes and routes it either to the host, meaning the CPU, or to its own core.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhKmhjhhubeh}(h]h ]h"]h$]h&]uh1jphjQhhhhhNubeh}(h] terminologyah ]h"] terminologyah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hThe GIN controllerh]hThe GIN controller}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hhhhhKpubh)}(hA GPU has many interrupt sources: the GSP, the copy engines, the graphics engine, video decode and encode, the MMU fault path, timers, and others. GIN records which of them are pending and raises the PCI interrupt to the CPU.h]hA GPU has many interrupt sources: the GSP, the copy engines, the graphics engine, video decode and encode, the MMU fault path, timers, and others. GIN records which of them are pending and raises the PCI interrupt to the CPU.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhj7hhubh)}(hhh](h)}(hTreesh]hTrees}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhhhhhKwubh)}(hXGIN keeps one tree for each destination it can deliver an interrupt to. The CPU has one tree per PCIe function, so the physical function and each virtual function have their own. The GSP has a tree, and so do the other on-chip processors that receive interrupts. Every tree has the same two-level layout, and a function reaches its own tree through the per-function register aperture.h]hXGIN keeps one tree for each destination it can deliver an interrupt to. The CPU has one tree per PCIe function, so the physical function and each virtual function have their own. The GSP has a tree, and so do the other on-chip processors that receive interrupts. Every tree has the same two-level layout, and a function reaches its own tree through the per-function register aperture.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjVhhubh)}(hnova-core services the CPU tree of one function. A virtual function's tree belongs to that function's driver, and a processor's tree belongs to the firmware running on that processor.h]hnova-core services the CPU tree of one function. A virtual function’s tree belongs to that function’s driver, and a processor’s tree belongs to the firmware running on that processor.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjVhhubeh}(h]treesah ]h"]treesah$]h&]uh1hhj7hhhhhKwubh)}(hhh](h)}(hThe two-level treeh]hThe two-level tree}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h?A tree is a set of ``LEAF`` registers and one ``TOP`` register.h](hA tree is a set of }(hjhhhNhNubj&)}(h``LEAF``h]hLEAF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh registers and one }(hjhhhNhNubj&)}(h``TOP``h]hTOP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh register.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh bullet_list)}(hhh](h list_item)}(h``LEAF(i)`` is a 32-bit register that holds the pending bits of vectors ``32i`` through ``32i + 31``. A set bit is a pending vector.h]h)}(h``LEAF(i)`` is a 32-bit register that holds the pending bits of vectors ``32i`` through ``32i + 31``. A set bit is a pending vector.h](j&)}(h ``LEAF(i)``h]hLEAF(i)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh= is a 32-bit register that holds the pending bits of vectors }(hjhhhNhNubj&)}(h``32i``h]h32i}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh through }(hjhhhNhNubj&)}(h ``32i + 31``h]h32i + 31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh . A set bit is a pending vector.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h``TOP`` is a 32-bit read-only register. Bit ``N`` summarizes subtree ``N``, which is ``LEAF(2N)`` and ``LEAF(2N + 1)``. The bit is set when an enabled vector is pending in either leaf. h]h)}(h``TOP`` is a 32-bit read-only register. Bit ``N`` summarizes subtree ``N``, which is ``LEAF(2N)`` and ``LEAF(2N + 1)``. The bit is set when an enabled vector is pending in either leaf.h](j&)}(h``TOP``h]hTOP}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj#ubh% is a 32-bit read-only register. Bit }(hj#hhhNhNubj&)}(h``N``h]hN}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj#ubh summarizes subtree }(hj#hhhNhNubj&)}(h``N``h]hN}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj#ubh , which is }(hj#hhhNhNubj&)}(h ``LEAF(2N)``h]hLEAF(2N)}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj#ubh and }(hj#hhhNhNubj&)}(h``LEAF(2N + 1)``h]h LEAF(2N + 1)}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj#ubhB. The bit is set when an enabled vector is pending in either leaf.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1jhhhKhjhhubh)}(hXA tree with L leaves has L / 2 subtrees and uses TOP bits 0 through L / 2 - 1. The other TOP bits read 0. The leaves and subtrees that a chipset has are its implemented leaves and subtrees, and "Per-architecture differences" gives the counts. For an 8-leaf tree::h]hX A tree with L leaves has L / 2 subtrees and uses TOP bits 0 through L / 2 - 1. The other TOP bits read 0. The leaves and subtrees that a chipset has are its implemented leaves and subtrees, and “Per-architecture differences” gives the counts. For an 8-leaf tree:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh literal_block)}(hXTOP bit 0 -> subtree 0 -> LEAF(0), LEAF(1) vectors 0..63 TOP bit 1 -> subtree 1 -> LEAF(2), LEAF(3) vectors 64..127 TOP bit 2 -> subtree 2 -> LEAF(4), LEAF(5) vectors 128..191 TOP bit 3 -> subtree 3 -> LEAF(6), LEAF(7) vectors 192..255 LEAF(4), one bit per vector, holds vectors 128..159: bit 1 = vector 129 (CPU doorbell) bit 27 = vector 155 (GSP event)h]hXTOP bit 0 -> subtree 0 -> LEAF(0), LEAF(1) vectors 0..63 TOP bit 1 -> subtree 1 -> LEAF(2), LEAF(3) vectors 64..127 TOP bit 2 -> subtree 2 -> LEAF(4), LEAF(5) vectors 128..191 TOP bit 3 -> subtree 3 -> LEAF(6), LEAF(7) vectors 192..255 LEAF(4), one bit per vector, holds vectors 128..159: bit 1 = vector 129 (CPU doorbell) bit 27 = vector 155 (GSP event)}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubh)}(h/A vector's number fixes its place in the tree::h]h0A vector’s number fixes its place in the tree:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h>leaf = vector / 32 bit = vector % 32 subtree = leaf / 2h]h>leaf = vector / 32 bit = vector % 32 subtree = leaf / 2}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubeh}(h]the-two-level-treeah ]h"]the two-level treeah$]h&]uh1hhj7hhhhhKubh)}(hhh](h)}(h Registersh]h Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hnova-core defines the tree's registers in the ``irq`` module's ``regs.rs``. The leaf registers are arrays indexed by leaf number.h](h0nova-core defines the tree’s registers in the }(hjhhhNhNubj&)}(h``irq``h]hirq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh module’s }(hjhhhNhNubj&)}(h ``regs.rs``h]hregs.rs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh7. The leaf registers are arrays indexed by leaf number.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(h``LEAF(i)`` reads as the pending bits of leaf ``i``. Writing a 1 to a bit clears that vector, and a 0 leaves the bit as it was.h]h)}(h``LEAF(i)`` reads as the pending bits of leaf ``i``. Writing a 1 to a bit clears that vector, and a 0 leaves the bit as it was.h](j&)}(h ``LEAF(i)``h]hLEAF(i)}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj!ubh# reads as the pending bits of leaf }(hj!hhhNhNubj&)}(h``i``h]hi}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj!ubhL. Writing a 1 to a bit clears that vector, and a 0 leaves the bit as it was.}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hm``LEAF_EN_SET(i)`` and ``LEAF_EN_CLEAR(i)`` enable and disable the vectors of leaf ``i``, one bit per vector.h]h)}(hm``LEAF_EN_SET(i)`` and ``LEAF_EN_CLEAR(i)`` enable and disable the vectors of leaf ``i``, one bit per vector.h](j&)}(h``LEAF_EN_SET(i)``h]hLEAF_EN_SET(i)}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjYubh and }(hjYhhhNhNubj&)}(h``LEAF_EN_CLEAR(i)``h]hLEAF_EN_CLEAR(i)}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjYubh( enable and disable the vectors of leaf }(hjYhhhNhNubj&)}(h``i``h]hi}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjYubh, one bit per vector.}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjUubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hU``TOP_EN_SET`` and ``TOP_EN_CLEAR`` enable and disable subtrees, one bit per subtree.h]h)}(hU``TOP_EN_SET`` and ``TOP_EN_CLEAR`` enable and disable subtrees, one bit per subtree.h](j&)}(h``TOP_EN_SET``h]h TOP_EN_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh and }(hjhhhNhNubj&)}(h``TOP_EN_CLEAR``h]h TOP_EN_CLEAR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh2 enable and disable subtrees, one bit per subtree.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h``LEAF_TRIGGER`` takes a vector number and latches that vector, exactly as the vector's own source would. It is write-only. The self-test uses it. h]h)}(h``LEAF_TRIGGER`` takes a vector number and latches that vector, exactly as the vector's own source would. It is write-only. The self-test uses it.h](j&)}(h``LEAF_TRIGGER``h]h LEAF_TRIGGER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh takes a vector number and latches that vector, exactly as the vector’s own source would. It is write-only. The self-test uses it.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h?nova-core does not read ``TOP``. "Servicing the tree" says why.h](hnova-core does not read }(hj hhhNhNubj&)}(h``TOP``h]hTOP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubh$. “Servicing the tree” says why.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hEvery set and clear register acts per bit: a 1 performs the action for that bit, and a 0 leaves the bit alone. No register needs a read-modify-write.h]hEvery set and clear register acts per bit: a 1 performs the action for that bit, and a 0 leaves the bit alone. No register needs a read-modify-write.}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXGIN delivers a vector to the CPU only when its leaf enable bit and its subtree's TOP enable bit are both set. The enables do not affect the latch. The source of a disabled vector still sets its ``LEAF`` bit. ``TOP`` does not show that bit, so reading the leaf is the only way to see it.h](hGIN delivers a vector to the CPU only when its leaf enable bit and its subtree’s TOP enable bit are both set. The enables do not affect the latch. The source of a disabled vector still sets its }(hj1 hhhNhNubj&)}(h``LEAF``h]hLEAF}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj1 ubh bit. }(hj1 hhhNhNubj&)}(h``TOP``h]hTOP}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj1 ubhG does not show that bit, so reading the leaf is the only way to see it.}(hj1 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] registersah ]h"] registersah$]h&]uh1hhj7hhhhhKubh)}(hhh](h)}(h$How a unit interrupt reaches the CPUh]h$How a unit interrupt reaches the CPU}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk hhhhhKubh)}(hXcA unit does not write a ``LEAF`` register. Each unit has an interrupt control register that GSP firmware programs. The control register holds the unit's vector, the GFID that identifies the PCIe function whose tree receives the interrupt, and one enable bit per destination: the CPU, the GSP, and the other on-chip processors. When the unit has an event::h](hA unit does not write a }(hj| hhhNhNubj&)}(h``LEAF``h]hLEAF}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj| ubhXD register. Each unit has an interrupt control register that GSP firmware programs. The control register holds the unit’s vector, the GFID that identifies the PCIe function whose tree receives the interrupt, and one enable bit per destination: the CPU, the GSP, and the other on-chip processors. When the unit has an event:}(hj| hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjk hhubj)}(hXS1. The unit sends GIN an interrupt message carrying the vector, the GFID, and the destination enables from its control register. 2. In the tree of each destination that the message selects, GIN sets bit (vector % 32) of LEAF(vector / 32). 3. If the vector and its subtree are enabled in the CPU tree, GIN raises the PCI interrupt.h]hXS1. The unit sends GIN an interrupt message carrying the vector, the GFID, and the destination enables from its control register. 2. In the tree of each destination that the message selects, GIN sets bit (vector % 32) of LEAF(vector / 32). 3. If the vector and its subtree are enabled in the CPU tree, GIN raises the PCI interrupt.}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjk hhubh)}(hX5Because firmware assigns the vectors, nova-core does not hardcode which vector belongs to which unit, with two exceptions. The hardware headers of every supported chipset define the GSP event as vector 155, and GSP firmware's own interrupt table uses that definition. The CPU doorbell is vector 129. Pre-Hopper hardware fixes that number, and GSP firmware keeps it on Hopper and later. nova-core names both by number. A driver can fetch the full unit-to-vector table from the GSP by RPC, and nouveau does. nova-core does not, because a fixed vector needs no lookup.h]hX7Because firmware assigns the vectors, nova-core does not hardcode which vector belongs to which unit, with two exceptions. The hardware headers of every supported chipset define the GSP event as vector 155, and GSP firmware’s own interrupt table uses that definition. The CPU doorbell is vector 129. Pre-Hopper hardware fixes that number, and GSP firmware keeps it on Hopper and later. nova-core names both by number. A driver can fetch the full unit-to-vector table from the GSP by RPC, and nouveau does. nova-core does not, because a fixed vector needs no lookup.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjk hhubeh}(h]$how-a-unit-interrupt-reaches-the-cpuah ]h"]$how a unit interrupt reaches the cpuah$]h&]uh1hhj7hhhhhKubh)}(hhh](h)}(hEdge-triggered deliveryh]hEdge-triggered delivery}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hA ``LEAF`` bit is a latch. Its source sets it on a rising edge, and it stays set until the CPU clears it. A source that stays high does not set the bit again.h](hA }(hj hhhNhNubj&)}(h``LEAF``h]hLEAF}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubh bit is a latch. Its source sets it on a rising edge, and it stays set until the CPU clears it. A source that stays high does not set the bit again.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hkGIN raises the PCI interrupt for a subtree when the subtree's enabled pending state goes from low to high::h]hlGIN raises the PCI interrupt for a subtree when the subtree’s enabled pending state goes from low to high:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj)}(hPer vector, in leaf i at bit b: LEAF(i)[b] AND LEAF_EN(i)[b] Per subtree N, across leaves 2N and 2N + 1: OR of every enabled pending bit -> TOP[N] Delivery for subtree N: TOP[N] AND TOP_EN[N] -> rising edge -> PCI interrupth]hPer vector, in leaf i at bit b: LEAF(i)[b] AND LEAF_EN(i)[b] Per subtree N, across leaves 2N and 2N + 1: OR of every enabled pending bit -> TOP[N] Delivery for subtree N: TOP[N] AND TOP_EN[N] -> rising edge -> PCI interrupt}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj hhubh)}(hr``TOP_EN`` applies after the summary, so disabling a subtree stops delivery without changing what ``TOP`` reports.h](j&)}(h ``TOP_EN``h]hTOP_EN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubhX applies after the summary, so disabling a subtree stops delivery without changing what }(hj hhhNhNubj&)}(h``TOP``h]hTOP}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubh reports.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hThree consequences:h]hThree consequences:}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj)}(hhh](j)}(hrCode that must find every pending vector reads the leaves. A vector that latched while disabled is not in ``TOP``.h]h)}(hrCode that must find every pending vector reads the leaves. A vector that latched while disabled is not in ``TOP``.h](hjCode that must find every pending vector reads the leaves. A vector that latched while disabled is not in }(hjP hhhNhNubj&)}(h``TOP``h]hTOP}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjP ubh.}(hjP hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjL ubah}(h]h ]h"]h$]h&]uh1jhjI hhhhhNubj)}(hWriting ``TOP_EN_SET`` for a subtree with an enabled pending bit produces a new edge. GIN delivers an interrupt for a pending bit left uncleared as soon as its subtree is enabled again.h]h)}(hWriting ``TOP_EN_SET`` for a subtree with an enabled pending bit produces a new edge. GIN delivers an interrupt for a pending bit left uncleared as soon as its subtree is enabled again.h](hWriting }(hjz hhhNhNubj&)}(h``TOP_EN_SET``h]h TOP_EN_SET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjz ubh for a subtree with an enabled pending bit produces a new edge. GIN delivers an interrupt for a pending bit left uncleared as soon as its subtree is enabled again.}(hjz hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjv ubah}(h]h ]h"]h$]h&]uh1jhjI hhhhhNubj)}(hA source that holds its signal high produces no new edge after the CPU clears the leaf bit. Such a source has to re-emit its interrupt. The falcons do that through ``INTR_RETRIGGER`` (see "Retriggering a falcon"). h]h)}(hA source that holds its signal high produces no new edge after the CPU clears the leaf bit. Such a source has to re-emit its interrupt. The falcons do that through ``INTR_RETRIGGER`` (see "Retriggering a falcon").h](hA source that holds its signal high produces no new edge after the CPU clears the leaf bit. Such a source has to re-emit its interrupt. The falcons do that through }(hj hhhNhNubj&)}(h``INTR_RETRIGGER``h]hINTR_RETRIGGER}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubh# (see “Retriggering a falcon”).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjI hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKhj hhubeh}(h]edge-triggered-deliveryah ]h"]edge-triggered deliveryah$]h&]uh1hhj7hhhhhKubeh}(h]the-gin-controllerah ]h"]the gin controllerah$]h&]uh1hhhhhhhhKpubh)}(hhh](h)}(hDelivery over PCIh]hDelivery over PCI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hGIN delivers the tree's interrupts to the CPU as MSI or MSI-X, whichever Linux grants. nova-core requests MSI-X first and falls back to MSI, and never uses INTx.h]hGIN delivers the tree’s interrupts to the CPU as MSI or MSI-X, whichever Linux grants. nova-core requests MSI-X first and falls back to MSI, and never uses INTx.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hlMSI has a single message, and every subtree raises that one message, so one Linux IRQ serves the whole tree.h]hlMSI has a single message, and every subtree raises that one message, so one Linux IRQ serves the whole tree.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hXGMSI-X gives each subtree its own table entry, at the index equal to the subtree number. Linux masks every entry until a driver requests its Linux IRQ number, and a masked entry sends no message: the GPU records the interrupt in the MSI-X pending bit array, where it stays until Linux unmasks the entry. An entry that the driver never requests is never unmasked. A driver that enables a subtree without requesting that subtree's entry loses every interrupt from that subtree, with nothing reported: the leaf and TOP registers show the vector pending and enabled while no handler runs.h]hXIMSI-X gives each subtree its own table entry, at the index equal to the subtree number. Linux masks every entry until a driver requests its Linux IRQ number, and a masked entry sends no message: the GPU records the interrupt in the MSI-X pending bit array, where it stays until Linux unmasks the entry. An entry that the driver never requests is never unmasked. A driver that enables a subtree without requesting that subtree’s entry loses every interrupt from that subtree, with nothing reported: the leaf and TOP registers show the vector pending and enabled while no handler runs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hThe serviced-subtree invarianth]hThe serviced-subtree invariant}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM ubh)}(hWEvery subtree enabled at ``TOP`` has an allocated PCI vector with a registered handler.h](hEvery subtree enabled at }(hj, hhhNhNubj&)}(h``TOP``h]hTOP}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj, ubh7 has an allocated PCI vector with a registered handler.}(hj, hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM hj hhubh)}(hMSI satisfies this with its single message. MSI-X needs one allocated entry per serviced subtree, and a PCI allocation cannot be sparse, so nova-core requests entries 0 through the highest serviced subtree::h]hMSI satisfies this with its single message. MSI-X needs one allocated entry per serviced subtree, and a PCI allocation cannot be sparse, so nova-core requests entries 0 through the highest serviced subtree:}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hXMSI-X, with subtree 2 serviced: subtree 0 -> entry 0 allocated, no handler, stays masked subtree 1 -> entry 1 allocated, no handler, stays masked subtree 2 -> entry 2 handler here, and its rearm covers subtree 2 MSI, with any serviced set: every serviced subtree -> the one allocated PCI vector, whose handler's rearm covers the whole serviced seth]hXMSI-X, with subtree 2 serviced: subtree 0 -> entry 0 allocated, no handler, stays masked subtree 1 -> entry 1 allocated, no handler, stays masked subtree 2 -> entry 2 handler here, and its rearm covers subtree 2 MSI, with any serviced set: every serviced subtree -> the one allocated PCI vector, whose handler's rearm covers the whole serviced set}hjZ sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj hhubh)}(hAn allocated entry whose subtree nova-core does not service costs nothing. The entry stays masked, and a disabled subtree raises no interrupt.h]hAn allocated entry whose subtree nova-core does not service costs nothing. The entry stays masked, and a disabled subtree raises no interrupt.}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hX7nova-core services one subtree. The GSP event, vector 155, is in leaf 4, which is in subtree 2. OpenRM's headers place its UVM_SHARED interrupt category in subtree 2 on every chipset that nova-core supports. The self-test doorbell, vector 129, is in the same leaf, and the test allocates its own vectors for it.h]hX9nova-core services one subtree. The GSP event, vector 155, is in leaf 4, which is in subtree 2. OpenRM’s headers place its UVM_SHARED interrupt category in subtree 2 on every chipset that nova-core supports. The self-test doorbell, vector 129, is in the same leaf, and the test allocates its own vectors for it.}(hjv hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj hhubeh}(h]the-serviced-subtree-invariantah ]h"]the serviced-subtree invariantah$]h&]uh1hhj hhhhhM ubh)}(hhh](h)}(hRearming PCI interrupt deliveryh]hRearming PCI interrupt delivery}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM&ubh)}(hA message-signaled interrupt is delivered once per edge, and the PCI side delivers no further interrupt until the CPU rearms it. The rearm operation depends on the GPU family and on the interrupt type that Linux granted:h]hA message-signaled interrupt is delivered once per edge, and the PCI side delivers no further interrupt until the CPU rearms it. The rearm operation depends on the GPU family and on the interrupt type that Linux granted:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hj hhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthK+uh1j hj ubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(h Architectureh]h Architecture}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hRearm operationh]hRearm operation}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1j hj ubhtbody)}(hhh](j )}(hhh](j )}(hhh]h)}(hTuring through Adah]hTuring through Ada}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj: ubah}(h]h ]h"]h$]h&]uh1j hj7 ubj )}(hhh]h)}(hMSIh]hMSI}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hjQ ubah}(h]h ]h"]h$]h&]uh1j hj7 ubj )}(hhh]h)}(h+write the configuration-mirror EOI registerh]h+write the configuration-mirror EOI register}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hjh ubah}(h]h ]h"]h$]h&]uh1j hj7 ubeh}(h]h ]h"]h$]h&]uh1j hj4 ubj )}(hhh](j )}(hhh]h)}(hHopper and laterh]hHopper and later}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hMSIh]hMSI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(h'clear then set the serviced TOP enablesh]h'clear then set the serviced TOP enables}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hj4 ubj )}(hhh](j )}(hhh]h)}(hAnyh]hAny}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hMSI-Xh]hMSI-X}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(h+clear then set the handler's own TOP enableh]h-clear then set the handler’s own TOP enable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hj4 ubeh}(h]h ]h"]h$]h&]uh1j2 hj ubeh}(h]h ]h"]h$]h&]colsKuh1j hj ubah}(h]h ]h"]h$]h&]uh1j hj hhhhhNubh)}(hXvThe end-of-interrupt register is ``NV_XVE_CYA_2`` in the BAR0 mirror of PCI configuration space, and the value written does not matter. The ``TOP_EN`` cycle produces a new delivery edge. The MSI forms cover every serviced subtree, because one message serves all of them. The MSI-X form covers one subtree, because each serviced subtree has its own entry and its own handler.h](h!The end-of-interrupt register is }(hj4 hhhNhNubj&)}(h``NV_XVE_CYA_2``h]h NV_XVE_CYA_2}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj4 ubh[ in the BAR0 mirror of PCI configuration space, and the value written does not matter. The }(hj4 hhhNhNubj&)}(h ``TOP_EN``h]hTOP_EN}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj4 ubh cycle produces a new delivery edge. The MSI forms cover every serviced subtree, because one message serves all of them. The MSI-X form covers one subtree, because each serviced subtree has its own entry and its own handler.}(hj4 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM4hj hhubh)}(hA handler rearms once per delivered interrupt, on every path, including the path where it finds its vector not pending. A handler that skips the rearm receives no further interrupts.h]hA handler rearms once per delivered interrupt, on every path, including the path where it finds its vector not pending. A handler that skips the rearm receives no further interrupts.}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hj hhubh)}(hOpenRM makes the same split. It writes the configuration-space EOI for MSI on pre-Hopper chipsets, and cycles the TOP enables of the subtrees that it services for Hopper-plus MSI and for MSI-X.h]hOpenRM makes the same split. It writes the configuration-space EOI for MSI on pre-Hopper chipsets, and cycles the TOP enables of the subtrees that it services for Hopper-plus MSI and for MSI-X.}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj hhubeh}(h]rearming-pci-interrupt-deliveryah ]h"]rearming pci interrupt deliveryah$]h&]uh1hhj hhhhhM&ubeh}(h]delivery-over-pciah ]h"]delivery over pciah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hServicing the treeh]hServicing the tree}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMCubh)}(hXServicing a leaf has a required order: read its pending bits, then clear them. Clearing a leaf before reading it discards every vector latched in it, and no register reports the loss. In nova-core, reading a leaf produces the handle that clears it, so that the wrong order does not compile. The handle clears exactly the bits that it read, so a vector that latched after the read stays pending.h]hXServicing a leaf has a required order: read its pending bits, then clear them. Clearing a leaf before reading it discards every vector latched in it, and no register reports the loss. In nova-core, reading a leaf produces the handle that clears it, so that the wrong order does not compile. The handle clears exactly the bits that it read, so a vector that latched after the read stays pending.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhj hhubh)}(hA handler clears its bit before it services the vector. Clearing afterwards would discard an interrupt that the source raised while the handler ran.h]hA handler clears its bit before it services the vector. Clearing afterwards would discard an interrupt that the source raised while the handler ran.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhj hhubh)}(h(nova-core services the tree in two ways.h]h(nova-core services the tree in two ways.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj hhubh)}(hX?The notification path services one vector. It reads the vector's leaf, clears only the vector's bit, and rearms. The subtree stays enabled, and a vector pending beside it in the same leaf keeps its bit set for the code that services that vector. The GSP event handler takes this path, and so does the self-test handler.h]hXCThe notification path services one vector. It reads the vector’s leaf, clears only the vector’s bit, and rearms. The subtree stays enabled, and a vector pending beside it in the same leaf keeps its bit set for the code that services that vector. The GSP event handler takes this path, and so does the self-test handler.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhj hhubh)}(hX.The startup drain walks the whole tree, because it must clear whatever is pending across every subtree rather than one known vector. It disables the serviced subtrees at ``TOP``, reads and clears every implemented leaf, and leaves the subtrees disabled for its caller to enable once the caller is ready for deliveries. The drain reads every leaf rather than descending from ``TOP``, because sources latch vectors during boot while those vectors are disabled, and ``TOP`` does not show them. OpenRM's stall-interrupt path reads every leaf for the same reason.h](hThe startup drain walks the whole tree, because it must clear whatever is pending across every subtree rather than one known vector. It disables the serviced subtrees at }(hj hhhNhNubj&)}(h``TOP``h]hTOP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubh, reads and clears every implemented leaf, and leaves the subtrees disabled for its caller to enable once the caller is ready for deliveries. The drain reads every leaf rather than descending from }(hj hhhNhNubj&)}(h``TOP``h]hTOP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubhR, because sources latch vectors during boot while those vectors are disabled, and }(hj hhhNhNubj&)}(h``TOP``h]hTOP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj ubhZ does not show them. OpenRM’s stall-interrupt path reads every leaf for the same reason.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMVhj hhubh)}(h&The two paths as register operations::h]h%The two paths as register operations:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hj hhubj)}(hXStartup drain, run once during probe: write TOP_EN_CLEAR = serviced stop new deliveries for each implemented leaf i: pending = read LEAF(i) write LEAF(i) = pending clear what was read (returns with TOP_EN still clear) Notification, the subtree stays enabled: pending = read LEAF(leaf) is the handler's bit set? write LEAF(leaf) = bit clear that one bit rearm PCI interrupt deliveryh]hXStartup drain, run once during probe: write TOP_EN_CLEAR = serviced stop new deliveries for each implemented leaf i: pending = read LEAF(i) write LEAF(i) = pending clear what was read (returns with TOP_EN still clear) Notification, the subtree stays enabled: pending = read LEAF(leaf) is the handler's bit set? write LEAF(leaf) = bit clear that one bit rearm PCI interrupt delivery}hj-sbah}(h]h ]h"]h$]h&]hhuh1jhhhMahj hhubh)}(hThe drain clears every pending bit, including bits that nova-core never services. An uncleared bit holds its subtree in the pending state, and enabling that subtree again would deliver an interrupt for a vector that no handler services.h]hThe drain clears every pending bit, including bits that nova-core never services. An uncleared bit holds its subtree in the pending state, and enabling that subtree again would deliver an interrupt for a vector that no handler services.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhj hhubh)}(hX[The drain's ``TOP_EN_CLEAR`` is not a rearm, and pre-Hopper MSI rearms through the configuration mirror, which the drain never writes. An interrupt delivered before probe had no handler to rearm it, so the tree reset rearms explicitly after the drain. A TOP-enable rearm leaves the serviced subtrees enabled, so the reset then disables them again.h](hThe drain’s }(hjIhhhNhNubj&)}(h``TOP_EN_CLEAR``h]h TOP_EN_CLEAR}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjIubhX? is not a rearm, and pre-Hopper MSI rearms through the configuration mirror, which the drain never writes. An interrupt delivered before probe had no handler to rearm it, so the tree reset rearms explicitly after the drain. A TOP-enable rearm leaves the serviced subtrees enabled, so the reset then disables them again.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMrhj hhubh)}(hnova-core does not serialize access to the tree. The GSP event handler touches only its own leaf, and the drain runs during probe, before that handler is registered.h]hnova-core does not serialize access to the tree. The GSP event handler touches only its own leaf, and the drain runs during probe, before that handler is registered.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhj hhubeh}(h]servicing-the-treeah ]h"]servicing the treeah$]h&]uh1hhhhhhhhMCubh)}(hhh](h)}(hPer-architecture differencesh]hPer-architecture differences}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM}ubh)}(hYThe tree is the same on every supported GPU except for its size, which changes at Hopper:h]hYThe tree is the same on every supported GPU except for its size, which changes at Hopper:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj )}(hhh]j )}(hhh](j )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]j )}(hhh](j )}(hhh]h)}(hGPUsh]hGPUs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hLeavesh]hLeaves}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hSubtreesh]hSubtrees}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hImplemented subtreesh]hImplemented subtrees}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1j hjubj3 )}(hhh](j )}(hhh](j )}(hhh]h)}(hTuring, Ampere, Adah]hTuring, Ampere, Ada}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ubah}(h]h ]h"]h$]h&]uh1j hj=ubj )}(hhh]h)}(h8h]h8}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWubah}(h]h ]h"]h$]h&]uh1j hj=ubj )}(hhh]h)}(h4h]h4}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjnubah}(h]h ]h"]h$]h&]uh1j hj=ubj )}(hhh]h)}(h``0x0f``h]j&)}(hjh]h0x0f}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hj=ubeh}(h]h ]h"]h$]h&]uh1j hj:ubj )}(hhh](j )}(hhh]h)}(hHopper, Blackwellh]hHopper, Blackwell}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h16h]h16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hj\h]h8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h``0xff``h]j&)}(hjh]h0xff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hj:ubeh}(h]h ]h"]h$]h&]uh1j2 hjubeh}(h]h ]h"]h$]h&]colsKuh1j hjubah}(h]h ]h"]h$]h&]uh1j hjhhhhhNubh)}(hX;The interrupt HAL provides the leaf count, and the subtree count and the implemented-subtree set derive from it. A subtree that the chipset does not implement has no TOP bit, so building a tree that services one fails with ``EINVAL``. Vectors 129 and 155 are in the 8-leaf tree, so every supported chipset has them.h](hThe interrupt HAL provides the leaf count, and the subtree count and the implemented-subtree set derive from it. A subtree that the chipset does not implement has no TOP bit, so building a tree that services one fails with }(hj+hhhNhNubj&)}(h ``EINVAL``h]hEINVAL}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj+ubhR. Vectors 129 and 155 are in the 8-leaf tree, so every supported chipset has them.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hOpenRM's headers assign every interrupt category of a 16-leaf tree to leaves 0 through 11. The drain reads all 16, because a vector can be latched in any implemented leaf.h]hOpenRM’s headers assign every interrupt category of a 16-leaf tree to leaves 0 through 11. The drain reads all 16, because a vector can be latched in any implemented leaf.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXThe HAL performs the rearm as well (see "Rearming PCI interrupt delivery"). Two falcon properties also differ by family, and the falcon HAL carries them: Turing falcons have no ``INTR_RETRIGGER``, and the RISC-V routing registers moved at GA102 (see "Retriggering a falcon").h](hThe HAL performs the rearm as well (see “Rearming PCI interrupt delivery”). Two falcon properties also differ by family, and the falcon HAL carries them: Turing falcons have no }(hjYhhhNhNubj&)}(h``INTR_RETRIGGER``h]hINTR_RETRIGGER}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjYubhT, and the RISC-V routing registers moved at GA102 (see “Retriggering a falcon”).}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]per-architecture-differencesah ]h"]per-architecture differencesah$]h&]uh1hhhhhhhhM}ubh)}(hhh](h)}(h The GSP eventh]h The GSP event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hXWhen the GSP has output for the CPU, it writes messages into the GSP-to-CPU queue in shared memory and raises SWGEN0, one of the software-generated interrupt causes of the GSP falcon. SWGEN0 is routed to the host, at vector 155, leaf 4 bit 27, in subtree 2.h]hXWhen the GSP has output for the CPU, it writes messages into the GSP-to-CPU queue in shared memory and raises SWGEN0, one of the software-generated interrupt causes of the GSP falcon. SWGEN0 is routed to the host, at vector 155, leaf 4 bit 27, in subtree 2.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hThe queue carries notifications (log records, error records, lifecycle events) and command replies. A thread waiting for a reply reads the queue itself, so the interrupt is only the trigger to drain the queue (see "Draining the GSP-to-CPU queue").h]hThe queue carries notifications (log records, error records, lifecycle events) and command replies. A thread waiting for a reply reads the queue itself, so the interrupt is only the trigger to drain the queue (see “Draining the GSP-to-CPU queue”).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hX7The falcon latches every cause that it raises, SWGEN0 among them, in its ``IRQSTAT`` register. The handler services the host-routed causes and clears their latches, and then it writes ``INTR_RETRIGGER`` so that the falcon re-emits any cause that latched in the meantime. "Retriggering a falcon" has the details.h](hIThe falcon latches every cause that it raises, SWGEN0 among them, in its }(hjhhhNhNubj&)}(h ``IRQSTAT``h]hIRQSTAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubhd register. The handler services the host-routed causes and clears their latches, and then it writes }(hjhhhNhNubj&)}(h``INTR_RETRIGGER``h]hINTR_RETRIGGER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubhq so that the falcon re-emits any cause that latched in the meantime. “Retriggering a falcon” has the details.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXUDraining the queue takes the command-queue mutex and walks shared memory, so it cannot run in hard interrupt context. nova-core registers a threaded handler, under the name ``nova-core`` in ``/proc/interrupts``. The top half runs in hard interrupt context and reads and writes only registers, and it wakes the IRQ thread to drain the queue::h](hDraining the queue takes the command-queue mutex and walks shared memory, so it cannot run in hard interrupt context. nova-core registers a threaded handler, under the name }(hjhhhNhNubj&)}(h ``nova-core``h]h nova-core}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh in }(hjhhhNhNubj&)}(h``/proc/interrupts``h]h/proc/interrupts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh. The top half runs in hard interrupt context and reads and writes only registers, and it wakes the IRQ thread to drain the queue:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hXGSP writes messages into the GSP-to-CPU queue GSP raises SWGEN0 GIN sets bit 27 of LEAF(4), and subtree 2 becomes pending PCI interrupt -> Linux IRQ -> top half, in hard interrupt context: read LEAF(4), and if bit 27 is clear, rearm and return clear bit 27 (the subtree stays enabled) read the falcon causes routed to the host, clearing SWGEN0 if set for every other host cause: log it, clear its latch, and read the host causes back if the clear ended all of them: retrigger the falcon otherwise: disable vector 155 at its leaf and skip the retrigger rearm PCI interrupt delivery wake the IRQ thread if SWGEN0 was set IRQ thread, which may sleep: take the command-queue mutex and drain the GSP-to-CPU queueh]hXGSP writes messages into the GSP-to-CPU queue GSP raises SWGEN0 GIN sets bit 27 of LEAF(4), and subtree 2 becomes pending PCI interrupt -> Linux IRQ -> top half, in hard interrupt context: read LEAF(4), and if bit 27 is clear, rearm and return clear bit 27 (the subtree stays enabled) read the falcon causes routed to the host, clearing SWGEN0 if set for every other host cause: log it, clear its latch, and read the host causes back if the clear ended all of them: retrigger the falcon otherwise: disable vector 155 at its leaf and skip the retrigger rearm PCI interrupt delivery wake the IRQ thread if SWGEN0 was set IRQ thread, which may sleep: take the command-queue mutex and drain the GSP-to-CPU queue}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjhhubh)}(hrA halt and a posted message can be pending together, so the top half services every cause that the status reports.h]hrA halt and a posted message can be pending together, so the top half services every cause that the status reports.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hX-A drain fails when a message's framing or checksum is bad (see "Draining the GSP-to-CPU queue"). The message stays at the queue head, so every later drain would fail the same way, and the IRQ thread disables vector 155 and logs the failure, which leaves the queue unserviced until the device is reset.h]hX3A drain fails when a message’s framing or checksum is bad (see “Draining the GSP-to-CPU queue”). The message stays at the queue head, so every later drain would fail the same way, and the IRQ thread disables vector 155 and logs the failure, which leaves the queue unserviced until the device is reset.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hThe handler, the self-test, and the rest of the driver read BAR0 through one shared mapping. nova-core unregisters an interrupt handler when the device unbinds, so a handler runs only while the mapping exists.h]hThe handler, the self-test, and the rest of the driver read BAR0 through one shared mapping. nova-core unregisters an interrupt handler when the device unbinds, so a handler runs only while the mapping exists.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hRetriggering a falconh]hRetriggering a falcon}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhhhhhMubh)}(hXCA falcon signals the tree when its set of host-routed causes goes from empty to non-empty. A cause left latched keeps the set non-empty, so no later cause signals the tree, and the vector is lost. For a cause that stays latched, the handler can clear the tree leaf first or the falcon latch first, and the loss is the same.h]hXCA falcon signals the tree when its set of host-routed causes goes from empty to non-empty. A cause left latched keeps the set non-empty, so no later cause signals the tree, and the vector is lost. For a cause that stays latched, the handler can clear the tree leaf first or the falcon latch first, and the loss is the same.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJhhubh)}(hX``IRQSTAT`` latches every cause in the falcon, including the causes routed to the falcon's own RISC-V core and owned by the firmware running on it. A host handler owns only the causes that ``PRISCV_RISCV_IRQMASK`` and ``PRISCV_RISCV_IRQDEST`` both select, so it intersects ``IRQSTAT`` with both before it reads or clears a cause. OpenRM computes the same intersection in ``kflcnRiscvReadIntrStatus``. GA100 keeps the Turing offsets of the two routing registers and GA102 moves them, so the offsets change at GA102 rather than at the Ampere boundary. The handler masks no cause: ``PRISCV_RISCV_IRQMASK`` is read-only to the host, and ``FALCON_IRQMASK`` has no effect on host routing on a RISC-V falcon.h](j&)}(h ``IRQSTAT``h]hIRQSTAT}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjiubh latches every cause in the falcon, including the causes routed to the falcon’s own RISC-V core and owned by the firmware running on it. A host handler owns only the causes that }(hjihhhNhNubj&)}(h``PRISCV_RISCV_IRQMASK``h]hPRISCV_RISCV_IRQMASK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjiubh and }(hjihhhNhNubj&)}(h``PRISCV_RISCV_IRQDEST``h]hPRISCV_RISCV_IRQDEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjiubh both select, so it intersects }(hjihhhNhNubj&)}(h ``IRQSTAT``h]hIRQSTAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjiubhW with both before it reads or clears a cause. OpenRM computes the same intersection in }(hjihhhNhNubj&)}(h``kflcnRiscvReadIntrStatus``h]hkflcnRiscvReadIntrStatus}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjiubh. GA100 keeps the Turing offsets of the two routing registers and GA102 moves them, so the offsets change at GA102 rather than at the Ampere boundary. The handler masks no cause: }(hjihhhNhNubj&)}(h``PRISCV_RISCV_IRQMASK``h]hPRISCV_RISCV_IRQMASK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjiubh is read-only to the host, and }(hjihhhNhNubj&)}(h``FALCON_IRQMASK``h]hFALCON_IRQMASK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjiubh2 has no effect on host routing on a RISC-V falcon.}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjJhhubh)}(hXH``INTR_RETRIGGER`` makes the falcon re-emit its host-routed causes into the tree, which supplies the transition that clearing the leaf lost. The handler writes ``INTR_RETRIGGER`` only on a path where it ended every cause that it read, because a re-emitted cause that stays set arrives again at once and on every pass after that.h](j&)}(h``INTR_RETRIGGER``h]hINTR_RETRIGGER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh makes the falcon re-emit its host-routed causes into the tree, which supplies the transition that clearing the leaf lost. The handler writes }(hjhhhNhNubj&)}(h``INTR_RETRIGGER``h]hINTR_RETRIGGER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh only on a path where it ended every cause that it read, because a re-emitted cause that stays set arrives again at once and on every pass after that.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjJhhubh)}(hXt``IRQSCLR`` ends a latch and does not end the source behind it, so a cause driven from outside the falcon stays set after the write. On Blackwell the fault-containment and ECC causes are driven that way: they appear in ``IRQSTAT`` but come from ``PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT`` and ``PGSP_ECC_INTR_STATUS``, and only a device reset ends them. So the handler clears the latch of every host cause other than SWGEN0, reads the host causes back, and retriggers only when the read-back is empty. When a cause is still set, the handler disables vector 155 instead and reports that the device needs a reset. Disabling loses no notification: the cause that is still set holds the host-routed set non-empty, so the falcon would signal nothing further either way. OpenRM makes the same choice, and ``kgspService_TU102`` skips ``kflcnIntrRetrigger`` once it has recorded a fatal error.h](j&)}(h ``IRQSCLR``h]hIRQSCLR}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh ends a latch and does not end the source behind it, so a cause driven from outside the falcon stays set after the write. On Blackwell the fault-containment and ECC causes are driven that way: they appear in }(hjhhhNhNubj&)}(h ``IRQSTAT``h]hIRQSTAT}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh but come from }(hjhhhNhNubj&)}(h*``PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT``h]h&PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh and }(hjhhhNhNubj&)}(h``PGSP_ECC_INTR_STATUS``h]hPGSP_ECC_INTR_STATUS}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubhX, and only a device reset ends them. So the handler clears the latch of every host cause other than SWGEN0, reads the host causes back, and retriggers only when the read-back is empty. When a cause is still set, the handler disables vector 155 instead and reports that the device needs a reset. Disabling loses no notification: the cause that is still set holds the host-routed set non-empty, so the falcon would signal nothing further either way. OpenRM makes the same choice, and }(hjhhhNhNubj&)}(h``kgspService_TU102``h]hkgspService_TU102}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh skips }(hjhhhNhNubj&)}(h``kflcnIntrRetrigger``h]hkflcnIntrRetrigger}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh$ once it has recorded a fatal error.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjJhhubh)}(hThe handler cannot distinguish a fault cause that arrives after the clear from one that the clear failed to end, so it disables the vector in that case too. Both mean that the GSP has faulted.h]hThe handler cannot distinguish a fault cause that arrives after the clear from one that the clear failed to end, so it disables the vector in that case too. Both mean that the GSP has faulted.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJhhubh)}(hX\Turing falcons have no ``INTR_RETRIGGER``, so a Turing handler cannot re-create a transition that it has lost. It must leave no host cause latched: it reads the host-routed status once and takes every cause that the status reports, rather than stopping at the first one that it recognizes. One window stays open. A cause that arrives after the handler has read the status is not in the value that the handler clears, so it stays latched after the leaf has been cleared, and no later cause from that falcon signals the tree. OpenRM has the same window on Turing, where ``kflcnIntrRetrigger`` does nothing.h](hTuring falcons have no }(hjhhhNhNubj&)}(h``INTR_RETRIGGER``h]hINTR_RETRIGGER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubhX, so a Turing handler cannot re-create a transition that it has lost. It must leave no host cause latched: it reads the host-routed status once and takes every cause that the status reports, rather than stopping at the first one that it recognizes. One window stays open. A cause that arrives after the handler has read the status is not in the value that the handler clears, so it stays latched after the leaf has been cleared, and no later cause from that falcon signals the tree. OpenRM has the same window on Turing, where }(hjhhhNhNubj&)}(h``kflcnIntrRetrigger``h]hkflcnIntrRetrigger}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh does nothing.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjJhhubeh}(h]retriggering-a-falconah ]h"]retriggering a falconah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hEnabling the GSP eventh]hEnabling the GSP event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hX"SWGEN0 is a latch, and the GSP drives no new edge into the tree while it stays set. nova-core's GSP boot code consumes the GSP's notifications by polling the queue, which leaves the latch set and leaves pending bits in the tree. The handoff from polling to interrupts has a required order::h]hX%SWGEN0 is a latch, and the GSP drives no new edge into the tree while it stays set. nova-core’s GSP boot code consumes the GSP’s notifications by polling the queue, which leaves the latch set and leaves pending bits in the tree. The handoff from polling to interrupts has a required order:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hXdisable every implemented vector drop enables left by boot, or by a driver that ran before this one drain the tree clear stale pending bits rearm PCI interrupt delivery required under pre-Hopper MSI, which no later step rearms disable subtree 2 at TOP a TOP-enable rearm enabled it again clear the SWGEN0 latch so the next message makes an edge register the threaded handler no delivery can reach it yet enable vector 155 at LEAF(4) the subtree is still disabled enable subtree 2 at TOP deliveries become possible here drain the GSP-to-CPU queue messages posted before the clearh]hXdisable every implemented vector drop enables left by boot, or by a driver that ran before this one drain the tree clear stale pending bits rearm PCI interrupt delivery required under pre-Hopper MSI, which no later step rearms disable subtree 2 at TOP a TOP-enable rearm enabled it again clear the SWGEN0 latch so the next message makes an edge register the threaded handler no delivery can reach it yet enable vector 155 at LEAF(4) the subtree is still disabled enable subtree 2 at TOP deliveries become possible here drain the GSP-to-CPU queue messages posted before the clear}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjhhubh)}(hXhThe first four steps are the tree reset. nova-core runs them, and clears the latch, before it registers the handler. Registering unmasks the PCI interrupt, and GIN would then deliver a vector that boot left enabled to a handler that services one vector and has no way to service any other. OpenRM clears every leaf enable at the same point for the same reason.h]hXhThe first four steps are the tree reset. nova-core runs them, and clears the latch, before it registers the handler. Registering unmasks the PCI interrupt, and GIN would then deliver a vector that boot left enabled to a handler that services one vector and has no way to service any other. OpenRM clears every leaf enable at the same point for the same reason.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXAnova-core clears the latch after the drain. If nova-core cleared the latch first, a message posted before the drain could set it again, along with bit 27 of LEAF(4). The drain would then clear the leaf bit while the latch stays set, and no later message would signal the tree. Clearing after the drain can instead leave the leaf bit pending with the latch already clear. Enabling the subtree then delivers one interrupt whose ``IRQSTAT`` reads zero. The top half clears the leaf bit, rearms, and does not wake the IRQ thread, and the queue drain that follows reads the message.h](hXnova-core clears the latch after the drain. If nova-core cleared the latch first, a message posted before the drain could set it again, along with bit 27 of LEAF(4). The drain would then clear the leaf bit while the latch stays set, and no later message would signal the tree. Clearing after the drain can instead leave the leaf bit pending with the latch already clear. Enabling the subtree then delivers one interrupt whose }(hjhhhNhNubj&)}(h ``IRQSTAT``h]hIRQSTAT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh reads zero. The top half clears the leaf bit, rearms, and does not wake the IRQ thread, and the queue drain that follows reads the message.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hClearing the latch makes the first interrupt possible. A message that the GSP posted before that clear produces no interrupt, so the sequence ends by draining the queue.h]hClearing the latch makes the first interrupt possible. A message that the GSP posted before that clear produces no interrupt, so the sequence ends by draining the queue.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hXThe subtree is enabled at ``TOP`` only once the handler is registered. A TOP-enable rearm sets the enables that it cycles, so the reset disables the serviced subtrees again after its rearm, and the tree reaches the registration with subtree 2 disabled under every rearm method. On teardown nova-core disables the vector at its leaf, so that no vector in the subtree can be delivered, then calls ``free_irq()``, and disables the subtree last. Disabling the subtree earlier would let a handler still in flight enable it again through the ``TOP_EN`` cycle of its rearm, which would leave the subtree enabled with no handler registered. The driver's ``Gpu`` object, which owns the tree, holds the subtree enable, and a handler's registration holds only the enable of its own vector, so that tearing down one handler does not disable a subtree that another handler shares. nova-core tears down the registration before it frees the queue that the handler drains and the falcon that the handler reads, and before it unloads the GSP.h](hThe subtree is enabled at }(hjFhhhNhNubj&)}(h``TOP``h]hTOP}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjFubhXj only once the handler is registered. A TOP-enable rearm sets the enables that it cycles, so the reset disables the serviced subtrees again after its rearm, and the tree reaches the registration with subtree 2 disabled under every rearm method. On teardown nova-core disables the vector at its leaf, so that no vector in the subtree can be delivered, then calls }(hjFhhhNhNubj&)}(h``free_irq()``h]h free_irq()}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjFubh, and disables the subtree last. Disabling the subtree earlier would let a handler still in flight enable it again through the }(hjFhhhNhNubj&)}(h ``TOP_EN``h]hTOP_EN}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjFubhf cycle of its rearm, which would leave the subtree enabled with no handler registered. The driver’s }(hjFhhhNhNubj&)}(h``Gpu``h]hGpu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjFubhXv object, which owns the tree, holds the subtree enable, and a handler’s registration holds only the enable of its own vector, so that tearing down one handler does not disable a subtree that another handler shares. nova-core tears down the registration before it frees the queue that the handler drains and the falcon that the handler reads, and before it unloads the GSP.}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM'hjhhubeh}(h]enabling-the-gsp-eventah ]h"]enabling the gsp eventah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hDraining the GSP-to-CPU queueh]hDraining the GSP-to-CPU queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM7ubh)}(hiThe queue carries command replies and unsolicited events, and a message's function code says which it is.h]hkThe queue carries command replies and unsolicited events, and a message’s function code says which it is.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjhhubj)}(hhh](j)}(hxA function code that matches the awaited reply: the message is decoded and returned to the caller that sent the command.h]h)}(hxA function code that matches the awaited reply: the message is decoded and returned to the caller that sent the command.h]hxA function code that matches the awaited reply: the message is decoded and returned to the caller that sent the command.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXAnything else is an event. An OS error record and a robust-channel record are logged at error level, and an unrecognized function code at warning level. The other known events (GSP logs, libos prints, assertion records, lifecycle notices) need no action and get no line of their own, because the receive trace at debug level already records every message's arrival with its sequence number, function code, and length. h]h)}(hXAnything else is an event. An OS error record and a robust-channel record are logged at error level, and an unrecognized function code at warning level. The other known events (GSP logs, libos prints, assertion records, lifecycle notices) need no action and get no line of their own, because the receive trace at debug level already records every message's arrival with its sequence number, function code, and length.h]hXAnything else is an event. An OS error record and a robust-channel record are logged at error level, and an unrecognized function code at warning level. The other known events (GSP logs, libos prints, assertion records, lifecycle notices) need no action and get no line of their own, because the receive trace at debug level already records every message’s arrival with its sequence number, function code, and length.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM<hjhhubh)}(hThe sequence number takes no part in the match, because the GSP does not echo the command's sequence number on every reply. On r570 the reply to ``UnloadingGuestDriver`` carries sequence 0.h](hThe sequence number takes no part in the match, because the GSP does not echo the command’s sequence number on every reply. On r570 the reply to }(hjhhhNhNubj&)}(h``UnloadingGuestDriver``h]hUnloadingGuestDriver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjubh carries sequence 0.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMEhjhhubh)}(hThe read pointer advances past every message that passes framing and checksum validation, whether it matched or was an event. A matched message that is too short to decode is the exception, and it stays at the queue head.h]hThe read pointer advances past every message that passes framing and checksum validation, whether it matched or was an event. A matched message that is too short to decode is the exception, and it stays at the queue head.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhjhhubh)}(hX#A message's length is inside the region that the checksum covers, so once the framing or the checksum fails there is no trustworthy length with which to skip the message. Such a message also stays at the queue head, and every later receive fails on it with ``EIO`` until the device is reset.h](hXA message’s length is inside the region that the checksum covers, so once the framing or the checksum fails there is no trustworthy length with which to skip the message. Such a message also stays at the queue head, and every later receive fails on it with }(hj*hhhNhNubj&)}(h``EIO``h]hEIO}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj*ubh until the device is reset.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMMhjhhubh)}(hXThe polling path and the IRQ thread both read the queue under the command-queue mutex. Replies and events share one queue and one read pointer, so one lock is held across the whole drain. A thread waiting for a reply logs each event that arrives before the reply and keeps waiting. One deadline of 5 seconds applies to the whole wait, rather than a fresh timeout after each message, and the thread holds the mutex for the whole wait, so that no other caller consumes the message that it waits for.h]hXThe polling path and the IRQ thread both read the queue under the command-queue mutex. Replies and events share one queue and one read pointer, so one lock is held across the whole drain. A thread waiting for a reply logs each event that arrives before the reply and keeps waiting. One deadline of 5 seconds applies to the whole wait, rather than a fresh timeout after each message, and the thread holds the mutex for the whole wait, so that no other caller consumes the message that it waits for.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhjhhubh)}(hWith one lock, a drain waits for an in-flight command's receive to finish or time out. For log and error records that delay does not matter.h]hWith one lock, a drain waits for an in-flight command’s receive to finish or time out. For log and error records that delay does not matter.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjhhubeh}(h]draining-the-gsp-to-cpu-queueah ]h"]draining the gsp-to-cpu queueah$]h&]uh1hhjhhhhhM7ubeh}(h] the-gsp-eventah ]h"] the gsp eventah$]h&]uh1hhhhhhhhMubeh}(h],gpu-interrupt-handling-gin-and-the-gsp-eventah ]h"]-gpu interrupt handling: gin and the gsp eventah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksj footnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j{jxj4j1j j jjjjjh je j j j j j j j j j j j|jyj~j{jsjpjjjjjkjhu nametypes}(j{j4j jjjh j j j j j j|j~jsjjjkuh}(jxhj1jQj j7jjVjjje jj jk j j j j j j j j jyj j{jjpjjjJjjjhju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.