€•9^Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ%/translations/zh_CN/gpu/nova/core/fsp”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ%/translations/zh_TW/gpu/nova/core/fsp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ%/translations/it_IT/gpu/nova/core/fsp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ%/translations/ja_JP/gpu/nova/core/fsp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ%/translations/ko_KR/gpu/nova/core/fsp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ%/translations/pt_BR/gpu/nova/core/fsp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ%/translations/sp_SP/gpu/nova/core/fsp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³Œ?/var/lib/git/docbuild/linux/Documentation/gpu/nova/core/fsp.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ3FSP (Foundation Security Processor) and Secure Boot”h]”hŒ3FSP (Foundation Security Processor) and Secure Boot”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ paragraph”“”)”}”(hX½This document describes the role of the FSP in the GPU boot sequence on Hopper and Blackwell GPUs, and how it differs from the earlier Ampere boot flow. It also provides a brief overview of the PRC (Product Reconfiguration Control) protocol used to query device configuration through FSP. As with other documents in this directory, the information is subject to change and is intended to help developers understand the corresponding kernel code.”h]”hX½This document describes the role of the FSP in the GPU boot sequence on Hopper and Blackwell GPUs, and how it differs from the earlier Ampere boot flow. It also provides a brief overview of the PRC (Product Reconfiguration Control) protocol used to query device configuration through FSP. As with other documents in this directory, the information is subject to change and is intended to help developers understand the corresponding kernel code.”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒ What is FSP?”h]”hŒ What is FSP?”…””}”(hhðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhíh²hh³hÇh´KubhÞ)”}”(hXThe Foundation Security Processor (FSP) is the GPU's Internal Root of Trust (IROT). It is a dedicated security processor that boots from immutable ROM (Boot ROM) inside the GPU and is responsible for establishing the Chain of Trust before any other firmware is allowed to run.”h]”hXThe Foundation Security Processor (FSP) is the GPU’s Internal Root of Trust (IROT). It is a dedicated security processor that boots from immutable ROM (Boot ROM) inside the GPU and is responsible for establishing the Chain of Trust before any other firmware is allowed to run.”…””}”(hhþh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhíh²hubhÞ)”}”(hŒèFSP runs independently of the host CPU and starts executing as soon as the GPU is powered on. By the time the nova-core driver is loaded, FSP has already completed its own secure boot and is ready to accept commands from the driver.”h]”hŒèFSP runs independently of the host CPU and starts executing as soon as the GPU is powered on. By the time the nova-core driver is loaded, FSP has already completed its own secure boot and is ready to accept commands from the driver.”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhíh²hubeh}”(h]”Œ what-is-fsp”ah ]”h"]”Œ what is fsp?”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒ'Simplified boot flow (Hopper/Blackwell)”h]”hŒ'Simplified boot flow (Hopper/Blackwell)”…””}”(hj%h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj"h²hh³hÇh´KubhÞ)”}”(hŒpStarting with Hopper, the boot flow is significantly simplified compared to earlier GPU generations like Ampere.”h]”hŒpStarting with Hopper, the boot flow is significantly simplified compared to earlier GPU generations like Ampere.”…””}”(hj3h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj"h²hubhÞ)”}”(hŒ‹On an **Ampere** GPU, the boot verification chain involves multiple Falcon engines and multiple ucode stages (see falcon.rst for details)::”h]”(hŒOn an ”…””}”(hjAh²hh³Nh´NubhŒstrong”“”)”}”(hŒ **Ampere**”h]”hŒAmpere”…””}”(hjKh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jIhjAubhŒz GPU, the boot verification chain involves multiple Falcon engines and multiple ucode stages (see falcon.rst for details):”…””}”(hjAh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj"h²hubhŒ literal_block”“”)”}”(hŒJHardware BROM (SEC2) -> HS Booter (SEC2) -> LS GSP-RM (GSP)”h]”hŒJHardware BROM (SEC2) -> HS Booter (SEC2) -> LS GSP-RM (GSP)”…””}”hjesbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jch³hÇh´K!hj"h²hubhÞ)”}”(hŒ£The driver must extract ucode from VBIOS, manage SEC2 and GSP, and orchestrate the Booter to load GSP-RM. This involves FWSEC-FRTS, devinit, and the Booter stages.”h]”hŒ£The driver must extract ucode from VBIOS, manage SEC2 and GSP, and orchestrate the Booter to load GSP-RM. This involves FWSEC-FRTS, devinit, and the Booter stages.”…””}”(hjsh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K%hj"h²hubhÞ)”}”(hŒlOn **Hopper/Blackwell** GPUs, FSP replaces this multi-stage process with a single message-driven interface::”h]”(hŒOn ”…””}”(hjh²hh³Nh´NubjJ)”}”(hŒ**Hopper/Blackwell**”h]”hŒHopper/Blackwell”…””}”(hj‰h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jIhjubhŒT GPUs, FSP replaces this multi-stage process with a single message-driven interface:”…””}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K)hj"h²hubjd)”}”(hŒ“FSP (hardware root of trust, boots from ROM) -> FMC (Falcon Microcontroller, verified by FSP) -> GSP-RM (verified and loaded by FMC)”h]”hŒ“FSP (hardware root of trust, boots from ROM) -> FMC (Falcon Microcontroller, verified by FSP) -> GSP-RM (verified and loaded by FMC)”…””}”hj¡sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jch³hÇh´K,hj"h²hubhÞ)”}”(hŒThe driver only needs to:”h]”hŒThe driver only needs to:”…””}”(hj¯h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K0hj"h²hubhŒenumerated_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒJWait for FSP to complete its own secure boot (polling a scratch register).”h]”hÞ)”}”(hjÆh]”hŒJWait for FSP to complete its own secure boot (polling a scratch register).”…””}”(hjÈh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K2hjÄubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhj¿h²hh³hÇh´NubjÃ)”}”(hŒ}Send a Chain of Trust (COT) message to FSP with the FMC firmware location, cryptographic signatures, and GSP boot parameters.”h]”hÞ)”}”(hŒ}Send a Chain of Trust (COT) message to FSP with the FMC firmware location, cryptographic signatures, and GSP boot parameters.”h]”hŒ}Send a Chain of Trust (COT) message to FSP with the FMC firmware location, cryptographic signatures, and GSP boot parameters.”…””}”(hjßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K3hjÛubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhj¿h²hh³hÇh´NubjÃ)”}”(hŒKFSP authenticates the FMC firmware and boots it, FMC in turn loads GSP-RM. ”h]”hÞ)”}”(hŒJFSP authenticates the FMC firmware and boots it, FMC in turn loads GSP-RM.”h]”hŒJFSP authenticates the FMC firmware and boots it, FMC in turn loads GSP-RM.”…””}”(hj÷h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K5hjóubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhj¿h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ.”uh1j½hj"h²hh³hÇh´K2ubhÞ)”}”(hŒŠThere is no SEC2 involvement, no Booter ucode, and no FWSEC-FRTS stage. The entire secure boot is driven by a single FSP message exchange.”h]”hŒŠThere is no SEC2 involvement, no Booter ucode, and no FWSEC-FRTS stage. The entire secure boot is driven by a single FSP message exchange.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K7hj"h²hubeh}”(h]”Œ%simplified-boot-flow-hopper-blackwell”ah ]”h"]”Œ'simplified boot flow (hopper/blackwell)”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒChain of Trust (COT) protocol”h]”hŒChain of Trust (COT) protocol”…””}”(hj/h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj,h²hh³hÇh´K;ubhÞ)”}”(hŒ{The Chain of Trust establishes a cryptographically enforced boot sequence, ensuring the GPU reaches a known, trusted state.”h]”hŒ{The Chain of Trust establishes a cryptographically enforced boot sequence, ensuring the GPU reaches a known, trusted state.”…””}”(hj=h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KThe system memory address of the GSP boot arguments structure.”h]”hŒ>The system memory address of the GSP boot arguments structure.”…””}”(hj¶h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KJhj²ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjih²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jgh³hÇh´KFhj,h²hubhÞ)”}”(hŒ¡FSP verifies the signature against the provided public key and hash, and if verification succeeds, boots the FMC. The FMC then authenticates and launches GSP-RM.”h]”hŒ¡FSP verifies the signature against the provided public key and hash, and if verification succeeds, boots the FMC. The FMC then authenticates and launches GSP-RM.”…””}”(hjÒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KLhj,h²hubhÞ)”}”(hŒThe message flow is::”h]”hŒThe message flow is:”…””}”(hjàh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KPhj,h²hubjd)”}”(hX˜nova-core FSP | | | 1. Poll scratch register | | (wait for FSP boot complete) | | | | 2. COT message ------------> | | (FMC addr, signatures, | | boot params) | | | | |--- Verify FMC signature | |--- Boot FMC | |--- FMC loads GSP-RM | | | 3. COT response <------------ | | (success/error) | | |”h]”hX˜nova-core FSP | | | 1. Poll scratch register | | (wait for FSP boot complete) | | | | 2. COT message ------------> | | (FMC addr, signatures, | | boot params) | | | | |--- Verify FMC signature | |--- Boot FMC | |--- FMC loads GSP-RM | | | 3. COT response <------------ | | (success/error) | | |”…””}”hjîsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jch³hÇh´KRhj,h²hubeh}”(h]”Œchain-of-trust-cot-protocol”ah ]”h"]”Œchain of trust (cot) protocol”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K;ubhÉ)”}”(hhh]”(hÎ)”}”(hŒFSP message format”h]”hŒFSP message format”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´KdubhÞ)”}”(hŒMAll FSP messages share a common header format consisting of two 32-bit words:”h]”hŒMAll FSP messages share a common header format consisting of two 32-bit words:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kehjh²hubhÞ)”}”(hŒ:**MCTP header** (Management Component Transport Protocol):”h]”(jJ)”}”(hŒ**MCTP header**”h]”hŒ MCTP header”…””}”(hj'h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jIhj#ubhŒ+ (Management Component Transport Protocol):”…””}”(hj#h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kghjh²hubjh)”}”(hhh]”(jÃ)”}”(hŒBit 31: SOM (Start of Message)”h]”hÞ)”}”(hjDh]”hŒBit 31: SOM (Start of Message)”…””}”(hjFh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KihjBubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhj?h²hh³hÇh´NubjÃ)”}”(hŒBit 30: EOM (End of Message)”h]”hÞ)”}”(hj[h]”hŒBit 30: EOM (End of Message)”…””}”(hj]h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KjhjYubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhj?h²hh³hÇh´NubjÃ)”}”(hŒ"Bits 29:28: Packet sequence number”h]”hÞ)”}”(hjrh]”hŒ"Bits 29:28: Packet sequence number”…””}”(hjth²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kkhjpubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhj?h²hh³hÇh´NubjÃ)”}”(hŒBits 23:16: Source Endpoint ID ”h]”hÞ)”}”(hŒBits 23:16: Source Endpoint ID”h]”hŒBits 23:16: Source Endpoint ID”…””}”(hj‹h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Klhj‡ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhj?h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jÐjÑuh1jgh³hÇh´Kihjh²hubhÞ)”}”(hŒ0**NVDM header** (NVIDIA Vendor Defined Message):”h]”(jJ)”}”(hŒ**NVDM header**”h]”hŒ NVDM header”…””}”(hj©h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jIhj¥ubhŒ! (NVIDIA Vendor Defined Message):”…””}”(hj¥h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Knhjh²hubjh)”}”(hhh]”(jÃ)”}”(hŒ7Bits 6:0: MCTP message type (0x7e = vendor-defined PCI)”h]”hÞ)”}”(hjÆh]”hŒ7Bits 6:0: MCTP message type (0x7e = vendor-defined PCI)”…””}”(hjÈh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KphjÄubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjÁh²hh³hÇh´NubjÃ)”}”(hŒ*Bits 23:8: PCI vendor ID (0x10de = NVIDIA)”h]”hÞ)”}”(hjÝh]”hŒ*Bits 23:8: PCI vendor ID (0x10de = NVIDIA)”…””}”(hjßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KqhjÛubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjÁh²hh³hÇh´NubjÃ)”}”(hŒDBits 31:24: NVDM type (0x14 = COT, 0x13 = PRC, 0x15 = FSP response) ”h]”hÞ)”}”(hŒCBits 31:24: NVDM type (0x14 = COT, 0x13 = PRC, 0x15 = FSP response)”h]”hŒCBits 31:24: NVDM type (0x14 = COT, 0x13 = PRC, 0x15 = FSP response)”…””}”(hjöh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Krhjòubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjÁh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jÐjÑuh1jgh³hÇh´Kphjh²hubeh}”(h]”Œfsp-message-format”ah ]”h"]”Œfsp message format”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KdubhÉ)”}”(hhh]”(hÎ)”}”(hŒ.PRC (Product Reconfiguration Control) protocol”h]”hŒ.PRC (Product Reconfiguration Control) protocol”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´KuubhÞ)”}”(hŒ‘PRC is an API system exposed through FSP's Management Partition that allows querying and modifying device configuration without firmware updates.”h]”hŒ“PRC is an API system exposed through FSP’s Management Partition that allows querying and modifying device configuration without firmware updates.”…””}”(hj)h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kvhjh²hubhÞ)”}”(hŒÕConfiguration parameters are called "knobs". Each knob has a unique object ID and controls a specific device behavior. Examples include vGPU mode, ECC enable, confidential computing mode, and NVLINK configuration.”h]”hŒÙConfiguration parameters are called “knobsâ€. Each knob has a unique object ID and controls a specific device behavior. Examples include vGPU mode, ECC enable, confidential computing mode, and NVLINK configuration.”…””}”(hj7h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kyhjh²hubhÞ)”}”(hŒEach knob has two values:”h]”hŒEach knob has two values:”…””}”(hjEh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K}hjh²hubjh)”}”(hhh]”(jÃ)”}”(hŒ>**Active**: the currently effective value for this boot cycle.”h]”hÞ)”}”(hjXh]”(jJ)”}”(hŒ **Active**”h]”hŒActive”…””}”(hj]h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jIhjZubhŒ4: the currently effective value for this boot cycle.”…””}”(hjZh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhjVubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjSh²hh³hÇh´NubjÃ)”}”(hŒJ**Persistent**: the value stored in InfoROM, applied on subsequent boots. ”h]”hÞ)”}”(hŒI**Persistent**: the value stored in InfoROM, applied on subsequent boots.”h]”(jJ)”}”(hŒ**Persistent**”h]”hŒ Persistent”…””}”(hjƒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jIhjubhŒ;: the value stored in InfoROM, applied on subsequent boots.”…””}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K€hj{ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjSh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jÐjÑuh1jgh³hÇh´Khjh²hubhÞ)”}”(hŒ¯The nova-core driver uses PRC to read the vGPU mode knob (object ID 0x29) during early boot, before firmware loading, to determine whether the GPU should operate in vGPU mode.”h]”hŒ¯The nova-core driver uses PRC to read the vGPU mode knob (object ID 0x29) during early boot, before firmware loading, to determine whether the GPU should operate in vGPU mode.”…””}”(hj§h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‚hjh²hubhÞ)”}”(hŒuThe PRC message format follows the same MCTP/NVDM header structure as COT, with NVDM type 0x13. The payload contains:”h]”hŒuThe PRC message format follows the same MCTP/NVDM header structure as COT, with NVDM type 0x13. The payload contains:”…””}”(hjµh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K†hjh²hubjh)”}”(hhh]”(jÃ)”}”(hŒ$A sub-command (e.g., 0x0c for read).”h]”hÞ)”}”(hjÈh]”hŒ$A sub-command (e.g., 0x0c for read).”…””}”(hjÊh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‰hjÆubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjÃh²hh³hÇh´NubjÃ)”}”(hŒJFlags indicating which value to read (bit 0 = persistent, bit 1 = active).”h]”hÞ)”}”(hjßh]”hŒJFlags indicating which value to read (bit 0 = persistent, bit 1 = active).”…””}”(hjáh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KŠhjÝubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjÃh²hh³hÇh´NubjÃ)”}”(hŒThe knob object ID. ”h]”hÞ)”}”(hŒThe knob object ID.”h]”hŒThe knob object ID.”…””}”(hjøh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‹hjôubah}”(h]”h ]”h"]”h$]”h&]”uh1jÂhjÃh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jÐjÑuh1jgh³hÇh´K‰hjh²hubhÞ)”}”(hŒsThe response includes the common FSP response header (with error status) followed by the knob's 16-bit state value.”h]”hŒuThe response includes the common FSP response header (with error status) followed by the knob’s 16-bit state value.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjh²hubeh}”(h]”Œ,prc-product-reconfiguration-control-protocol”ah ]”h"]”Œ.prc (product reconfiguration control) protocol”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´Kuubeh}”(h]”Œ1fsp-foundation-security-processor-and-secure-boot”ah ]”h"]”Œ3fsp (foundation security processor) and secure boot”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jSŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j-j*jjj)j&jjþjjj%j"uŒ nametypes”}”(j-‰j‰j)‰j‰j‰j%‰uh}”(j*hÊjhíj&j"jþj,jjj"juŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.