€•Fe      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ(/translations/zh_CN/gpu/nova/core/falcon”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/zh_TW/gpu/nova/core/falcon”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/it_IT/gpu/nova/core/falcon”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/ja_JP/gpu/nova/core/falcon”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/ko_KR/gpu/nova/core/falcon”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ(/translations/sp_SP/gpu/nova/core/falcon”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1h¡hhhžhhŸŒB/var/lib/git/docbuild/linux/Documentation/gpu/nova/core/falcon.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒFalcon (FAst Logic Controller)”h]”hŒFalcon (FAst Logic Controller)”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ	paragraph”“”)”}”(hXi  The following sections describe the Falcon core and the ucode running on it.
The descriptions are based on the Ampere GPU or earlier designs; however, they
should mostly apply to future designs as well, but everything is subject to
change. The overview provided here is mainly tailored towards understanding the
interactions of nova-core driver with the Falcon.”h]”hXi  The following sections describe the Falcon core and the ucode running on it.
The descriptions are based on the Ampere GPU or earlier designs; however, they
should mostly apply to future designs as well, but everything is subject to
change. The overview provided here is mainly tailored towards understanding the
interactions of nova-core driver with the Falcon.”…””}”(hhËhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhÊ)”}”(hXu  NVIDIA GPUs embed small RISC-like microcontrollers called Falcon cores, which
handle secure firmware tasks, initialization, and power management. Modern
NVIDIA GPUs may have multiple such Falcon instances (e.g., GSP (the GPU system
processor) and SEC2 (the security engine)) and also may integrate a RISC-V core.
This core is capable of running both RISC-V and Falcon code.”h]”hXu  NVIDIA GPUs embed small RISC-like microcontrollers called Falcon cores, which
handle secure firmware tasks, initialization, and power management. Modern
NVIDIA GPUs may have multiple such Falcon instances (e.g., GSP (the GPU system
processor) and SEC2 (the security engine)) and also may integrate a RISC-V core.
This core is capable of running both RISC-V and Falcon code.”…””}”(hhÙhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhÊ)”}”(hŒwThe code running on the Falcon cores is also called 'ucode', and will be
referred to as such in the following sections.”h]”hŒ{The code running on the Falcon cores is also called â€˜ucodeâ€™, and will be
referred to as such in the following sections.”…””}”(hhçhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhÊ)”}”(hX  Falcons have separate instruction and data memories (IMEM/DMEM) and provide a
small DMA engine (via the FBIF - "Frame Buffer Interface") to load code from
system memory. The nova-core driver must reset and configure the Falcon, load
its firmware via DMA, and start its CPU.”h]”hX  Falcons have separate instruction and data memories (IMEM/DMEM) and provide a
small DMA engine (via the FBIF - â€œFrame Buffer Interfaceâ€) to load code from
system memory. The nova-core driver must reset and configure the Falcon, load
its firmware via DMA, and start its CPU.”…””}”(hhõhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒFalcon security levels”h]”hŒFalcon security levels”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj  hžhhŸh³h KubhÊ)”}”(hŒRFalcons can run in Non-secure (NS), Light Secure (LS), or Heavy Secure (HS)
modes.”h]”hŒRFalcons can run in Non-secure (NS), Light Secure (LS), or Heavy Secure (HS)
modes.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj  hžhubhµ)”}”(hhh]”(hº)”}”(hŒ8Heavy Secured (HS) also known as Privilege Level 3 (PL3)”h]”hŒ8Heavy Secured (HS) also known as Privilege Level 3 (PL3)”…””}”(hj%  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj"  hžhhŸh³h K ubhÊ)”}”(hXò  HS ucode is the most trusted code and has access to pretty much everything on
the chip. The HS binary includes a signature in it which is verified at boot.
This signature verification is done by the hardware itself, thus establishing a
root of trust. For example, the FWSEC-FRTS command (see fwsec.rst) runs on the
GSP in HS mode. FRTS, which involves setting up and loading content into the WPR
(Write Protect Region), has to be done by the HS ucode and cannot be done by the
host CPU or LS ucode.”h]”hXò  HS ucode is the most trusted code and has access to pretty much everything on
the chip. The HS binary includes a signature in it which is verified at boot.
This signature verification is done by the hardware itself, thus establishing a
root of trust. For example, the FWSEC-FRTS command (see fwsec.rst) runs on the
GSP in HS mode. FRTS, which involves setting up and loading content into the WPR
(Write Protect Region), has to be done by the HS ucode and cannot be done by the
host CPU or LS ucode.”…””}”(hj3  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K!hj"  hžhubeh}”(h]”Œ4heavy-secured-hs-also-known-as-privilege-level-3-pl3”ah ]”h"]”Œ8heavy secured (hs) also known as privilege level 3 (pl3)”ah$]”h&]”uh1h´hj  hžhhŸh³h K ubhµ)”}”(hhh]”(hº)”}”(hŒ5Light Secured (LS or PL2) and Non Secured (NS or PL0)”h]”hŒ5Light Secured (LS or PL2) and Non Secured (NS or PL0)”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjI  hžhhŸh³h K*ubhÊ)”}”(hXN  These modes are less secure than HS. Like HS, the LS or NS ucode binary also
typically includes a signature in it. To load firmware in LS or NS mode onto a
Falcon, another Falcon needs to be running in HS mode, which also establishes the
root of trust. For example, in the case of an Ampere GPU, the CPU runs the "Booter"
ucode in HS mode on the SEC2 Falcon, which then authenticates and runs the
run-time GSP binary (GSP-RM) in LS mode on the GSP Falcon. Similarly, as an
example, after reset on an Ampere, FWSEC runs on the GSP which then loads the
devinit engine onto the PMU in LS mode.”h]”hXR  These modes are less secure than HS. Like HS, the LS or NS ucode binary also
typically includes a signature in it. To load firmware in LS or NS mode onto a
Falcon, another Falcon needs to be running in HS mode, which also establishes the
root of trust. For example, in the case of an Ampere GPU, the CPU runs the â€œBooterâ€
ucode in HS mode on the SEC2 Falcon, which then authenticates and runs the
run-time GSP binary (GSP-RM) in LS mode on the GSP Falcon. Similarly, as an
example, after reset on an Ampere, FWSEC runs on the GSP which then loads the
devinit engine onto the PMU in LS mode.”…””}”(hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K+hjI  hžhubeh}”(h]”Œ1light-secured-ls-or-pl2-and-non-secured-ns-or-pl0”ah ]”h"]”Œ5light secured (ls or pl2) and non secured (ns or pl0)”ah$]”h&]”uh1h´hj  hžhhŸh³h K*ubhµ)”}”(hhh]”(hº)”}”(hŒRoot of trust establishment”h]”hŒRoot of trust establishment”…””}”(hjs  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjp  hžhhŸh³h K5ubhÊ)”}”(hXe  To establish a root of trust, the code running on a Falcon must be immutable and
hardwired into a read-only memory (ROM). This follows industry norms for
verification of firmware. This code is called the Boot ROM (BROM). The nova-core
driver on the CPU communicates with Falcon's Boot ROM through various Falcon
registers prefixed with "BROM" (see regs.rs).”h]”hXk  To establish a root of trust, the code running on a Falcon must be immutable and
hardwired into a read-only memory (ROM). This follows industry norms for
verification of firmware. This code is called the Boot ROM (BROM). The nova-core
driver on the CPU communicates with Falconâ€™s Boot ROM through various Falcon
registers prefixed with â€œBROMâ€ (see regs.rs).”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K6hjp  hžhubhÊ)”}”(hX  After nova-core driver reads the necessary ucode from VBIOS, it programs the
BROM and DMA registers to trigger the Falcon to load the HS ucode from the system
memory into the Falcon's IMEM/DMEM. Once the HS ucode is loaded, it is verified
by the Falcon's Boot ROM.”h]”hX  After nova-core driver reads the necessary ucode from VBIOS, it programs the
BROM and DMA registers to trigger the Falcon to load the HS ucode from the system
memory into the Falconâ€™s IMEM/DMEM. Once the HS ucode is loaded, it is verified
by the Falconâ€™s Boot ROM.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K<hjp  hžhubhÊ)”}”(hX  Once the verified HS code is running on a Falcon, it can verify and load other
LS/NS ucode binaries onto other Falcons and start them. The process of signature
verification is the same as HS; just in this case, the hardware (BROM) doesn't
compute the signature, but the HS ucode does.”h]”hX  Once the verified HS code is running on a Falcon, it can verify and load other
LS/NS ucode binaries onto other Falcons and start them. The process of signature
verification is the same as HS; just in this case, the hardware (BROM) doesnâ€™t
compute the signature, but the HS ucode does.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KAhjp  hžhubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hŒ}The root of trust is therefore established as follows:
Hardware (Boot ROM running on the Falcon) -> HS ucode -> LS/NS ucode.
”h]”(hŒterm”“”)”}”(hŒ6The root of trust is therefore established as follows:”h]”hŒ6The root of trust is therefore established as follows:”…””}”(hj¸  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¶  hŸh³h KGhj²  ubhŒ
definition”“”)”}”(hhh]”hÊ)”}”(hŒEHardware (Boot ROM running on the Falcon) -> HS ucode -> LS/NS ucode.”h]”hŒEHardware (Boot ROM running on the Falcon) -> HS ucode -> LS/NS ucode.”…””}”(hjË  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KGhjÈ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÆ  hj²  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j°  hŸh³h KGhj­  ubj±  )”}”(hŒÆOn an Ampere GPU, for example, the boot verification flow is:
Hardware (Boot ROM running on the SEC2) ->
     HS ucode (Booter running on the SEC2) ->
          LS ucode (GSP-RM running on the GSP)
”h]”(j·  )”}”(hŒ=On an Ampere GPU, for example, the boot verification flow is:”h]”hŒ=On an Ampere GPU, for example, the boot verification flow is:”…””}”(hjé  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¶  hŸh³h KLhjå  ubjÇ  )”}”(hhh]”j¬  )”}”(hhh]”j±  )”}”(hŒ~Hardware (Boot ROM running on the SEC2) ->
HS ucode (Booter running on the SEC2) ->
     LS ucode (GSP-RM running on the GSP)
”h]”(j·  )”}”(hŒ*Hardware (Boot ROM running on the SEC2) ->”h]”hŒ*Hardware (Boot ROM running on the SEC2) ->”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¶  hŸh³h KLhjý  ubjÇ  )”}”(hhh]”j¬  )”}”(hhh]”j±  )”}”(hŒNHS ucode (Booter running on the SEC2) ->
LS ucode (GSP-RM running on the GSP)
”h]”(j·  )”}”(hŒ(HS ucode (Booter running on the SEC2) ->”h]”hŒ(HS ucode (Booter running on the SEC2) ->”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¶  hŸh³h KLhj  ubjÇ  )”}”(hhh]”hÊ)”}”(hŒ$LS ucode (GSP-RM running on the GSP)”h]”hŒ$LS ucode (GSP-RM running on the GSP)”…””}”(hj*  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KLhj'  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÆ  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j°  hŸh³h KLhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j«  hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÆ  hjý  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j°  hŸh³h KLhjú  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j«  hj÷  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÆ  hjå  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j°  hŸh³h KLhj­  hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1j«  hjp  hžhhŸh³h NubhŒnote”“”)”}”(hX=  While the CPU can load HS ucode onto a Falcon microcontroller and have it
verified by the hardware and run, the CPU itself typically does not load
LS or NS ucode and run it. Loading of LS or NS ucode is done mainly by the
HS ucode. For example, on an Ampere GPU, after the Booter ucode runs on the
SEC2 in HS mode and loads the GSP-RM binary onto the GSP, it needs to run
the "SEC2-RTOS" ucode at runtime. This presents a problem: there is no
component to load the SEC2-RTOS ucode onto the SEC2. The CPU cannot load
LS code, and GSP-RM must run in LS mode. To overcome this, the GSP is
temporarily made to run HS ucode (which is itself loaded by the CPU via
the nova-core driver using a "GSP-provided sequencer") which then loads
the SEC2-RTOS ucode onto the SEC2 in LS mode. The GSP then resumes
running its own GSP-RM LS ucode.”h]”hÊ)”}”(hX=  While the CPU can load HS ucode onto a Falcon microcontroller and have it
verified by the hardware and run, the CPU itself typically does not load
LS or NS ucode and run it. Loading of LS or NS ucode is done mainly by the
HS ucode. For example, on an Ampere GPU, after the Booter ucode runs on the
SEC2 in HS mode and loads the GSP-RM binary onto the GSP, it needs to run
the "SEC2-RTOS" ucode at runtime. This presents a problem: there is no
component to load the SEC2-RTOS ucode onto the SEC2. The CPU cannot load
LS code, and GSP-RM must run in LS mode. To overcome this, the GSP is
temporarily made to run HS ucode (which is itself loaded by the CPU via
the nova-core driver using a "GSP-provided sequencer") which then loads
the SEC2-RTOS ucode onto the SEC2 in LS mode. The GSP then resumes
running its own GSP-RM LS ucode.”h]”hXE  While the CPU can load HS ucode onto a Falcon microcontroller and have it
verified by the hardware and run, the CPU itself typically does not load
LS or NS ucode and run it. Loading of LS or NS ucode is done mainly by the
HS ucode. For example, on an Ampere GPU, after the Booter ucode runs on the
SEC2 in HS mode and loads the GSP-RM binary onto the GSP, it needs to run
the â€œSEC2-RTOSâ€ ucode at runtime. This presents a problem: there is no
component to load the SEC2-RTOS ucode onto the SEC2. The CPU cannot load
LS code, and GSP-RM must run in LS mode. To overcome this, the GSP is
temporarily made to run HS ucode (which is itself loaded by the CPU via
the nova-core driver using a â€œGSP-provided sequencerâ€) which then loads
the SEC2-RTOS ucode onto the SEC2 in LS mode. The GSP then resumes
running its own GSP-RM LS ucode.”…””}”(hjt  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KOhjp  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jn  hjp  hžhhŸh³h Nubeh}”(h]”Œroot-of-trust-establishment”ah ]”h"]”Œroot of trust establishment”ah$]”h&]”uh1h´hj  hžhhŸh³h K5ubeh}”(h]”Œfalcon-security-levels”ah ]”h"]”Œfalcon security levels”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒ&Falcon memory subsystem and DMA engine”h]”hŒ&Falcon memory subsystem and DMA engine”…””}”(hj›  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj˜  hžhhŸh³h K]ubhÊ)”}”(hX   Falcons have separate instruction and data memories (IMEM/DMEM)
and contains a small DMA engine called FBDMA (Framebuffer DMA) which does
DMA transfers to/from the IMEM/DMEM memory inside the Falcon via the FBIF
(Framebuffer Interface), to external memory.”h]”hX   Falcons have separate instruction and data memories (IMEM/DMEM)
and contains a small DMA engine called FBDMA (Framebuffer DMA) which does
DMA transfers to/from the IMEM/DMEM memory inside the Falcon via the FBIF
(Framebuffer Interface), to external memory.”…””}”(hj©  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K^hj˜  hžhubhÊ)”}”(hŒpDMA transfers are possible from the Falcon's memory to both the system memory
and the framebuffer memory (VRAM).”h]”hŒrDMA transfers are possible from the Falconâ€™s memory to both the system memory
and the framebuffer memory (VRAM).”…””}”(hj·  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kchj˜  hžhubhÊ)”}”(hŒÆTo perform a DMA via the FBDMA, the FBIF is configured to decide how the memory
is accessed (also known as aperture type). In the nova-core driver, this is
determined by the `FalconFbifTarget` enum.”h]”(hŒ®To perform a DMA via the FBDMA, the FBIF is configured to decide how the memory
is accessed (also known as aperture type). In the nova-core driver, this is
determined by the ”…””}”(hjÅ  hžhhŸNh NubhŒtitle_reference”“”)”}”(hŒ`FalconFbifTarget`”h]”hŒFalconFbifTarget”…””}”(hjÏ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍ  hjÅ  ubhŒ enum.”…””}”(hjÅ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kfhj˜  hžhubhÊ)”}”(hŒ‚The IO-PMP block (Input/Output Physical Memory Protection) unit in the Falcon
controls access by the FBDMA to the external memory.”h]”hŒ‚The IO-PMP block (Input/Output Physical Memory Protection) unit in the Falcon
controls access by the FBDMA to the external memory.”…””}”(hjç  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kjhj˜  hžhubhÊ)”}”(hŒUConceptual diagram (not exact) of the Falcon and its memory subsystem is as follows::”h]”hŒTConceptual diagram (not exact) of the Falcon and its memory subsystem is as follows:”…””}”(hjõ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kmhj˜  hžhubhŒliteral_block”“”)”}”(hXâ	            External Memory (Framebuffer / System DRAM)
                         ^  |
                         |  |
                         |  v
+-----------------------------------------------------+
|                           |                         |
|   +---------------+       |                         |
|   |     FBIF      |-------+                         |  FALCON
|   | (FrameBuffer  |   Memory Interface              |  PROCESSOR
|   |  InterFace)   |                                 |
|   |  Apertures    |                                 |
|   |  Configures   |                                 |
|   |  mem access   |                                 |
|   +-------^-------+                                 |
|           |                                         |
|           | FBDMA uses configured FBIF apertures    |
|           | to access External Memory
|           |
|   +-------v--------+      +---------------+
|   |    FBDMA       |  cfg |     RISC      |
|   | (FrameBuffer   |<---->|     CORE      |----->. Direct Core Access
|   |  DMA Engine)   |      |               |      |
|   | - Master dev.  |      | (can run both |      |
|   +-------^--------+      | Falcon and    |      |
|           |        cfg--->| RISC-V code)  |      |
|           |        /      |               |      |
|           |        |      +---------------+      |    +------------+
|           |        |                             |    |   BROM     |
|           |        |                             <--->| (Boot ROM) |
|           |       /                              |    +------------+
|           |      v                               |
|   +---------------+                              |
|   |    IO-PMP     | Controls access by FBDMA     |
|   | (IO Physical  | and other IO Masters         |
|   | Memory Protect)                              |
|   +-------^-------+                              |
|           |                                      |
|           | Protected Access Path for FBDMA      |
|           v                                      |
|   +---------------------------------------+      |
|   |       Memory                          |      |
|   |   +---------------+  +------------+   |      |
|   |   |    IMEM       |  |    DMEM    |   |<-----+
|   |   | (Instruction  |  |   (Data    |   |
|   |   |  Memory)      |  |   Memory)  |   |
|   |   +---------------+  +------------+   |
|   +---------------------------------------+
+-----------------------------------------------------+”h]”hXâ	            External Memory (Framebuffer / System DRAM)
                         ^  |
                         |  |
                         |  v
+-----------------------------------------------------+
|                           |                         |
|   +---------------+       |                         |
|   |     FBIF      |-------+                         |  FALCON
|   | (FrameBuffer  |   Memory Interface              |  PROCESSOR
|   |  InterFace)   |                                 |
|   |  Apertures    |                                 |
|   |  Configures   |                                 |
|   |  mem access   |                                 |
|   +-------^-------+                                 |
|           |                                         |
|           | FBDMA uses configured FBIF apertures    |
|           | to access External Memory
|           |
|   +-------v--------+      +---------------+
|   |    FBDMA       |  cfg |     RISC      |
|   | (FrameBuffer   |<---->|     CORE      |----->. Direct Core Access
|   |  DMA Engine)   |      |               |      |
|   | - Master dev.  |      | (can run both |      |
|   +-------^--------+      | Falcon and    |      |
|           |        cfg--->| RISC-V code)  |      |
|           |        /      |               |      |
|           |        |      +---------------+      |    +------------+
|           |        |                             |    |   BROM     |
|           |        |                             <--->| (Boot ROM) |
|           |       /                              |    +------------+
|           |      v                               |
|   +---------------+                              |
|   |    IO-PMP     | Controls access by FBDMA     |
|   | (IO Physical  | and other IO Masters         |
|   | Memory Protect)                              |
|   +-------^-------+                              |
|           |                                      |
|           | Protected Access Path for FBDMA      |
|           v                                      |
|   +---------------------------------------+      |
|   |       Memory                          |      |
|   |   +---------------+  +------------+   |      |
|   |   |    IMEM       |  |    DMEM    |   |<-----+
|   |   | (Instruction  |  |   (Data    |   |
|   |   |  Memory)      |  |   Memory)  |   |
|   |   +---------------+  +------------+   |
|   +---------------------------------------+
+-----------------------------------------------------+”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h Kohj˜  hžhubeh}”(h]”Œ&falcon-memory-subsystem-and-dma-engine”ah ]”h"]”Œ&falcon memory subsystem and dma engine”ah$]”h&]”uh1h´hh¶hžhhŸh³h K]ubeh}”(h]”Œfalcon-fast-logic-controller”ah ]”h"]”Œfalcon (fast logic controller)”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jF  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j   j  j•  j’  jF  jC  jm  jj  j  jŠ  j  j  uŒ	nametypes”}”(j   ‰j•  ‰jF  ‰jm  ‰j  ‰j  ‰uh}”(j  h¶j’  j  jC  j"  jj  jI  jŠ  jp  j  j˜  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.