€•6E      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ&/translations/zh_CN/gpu/msm-preemption”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/zh_TW/gpu/msm-preemption”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/it_IT/gpu/msm-preemption”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/ja_JP/gpu/msm-preemption”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/ko_KR/gpu/msm-preemption”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/sp_SP/gpu/msm-preemption”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1h¡hhhžhhŸŒ@/var/lib/git/docbuild/linux/Documentation/gpu/msm-preemption.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒMSM Preemption”h]”hŒMSM Preemption”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ	paragraph”“”)”}”(hŒŒPreemption allows Adreno GPUs to switch to a higher priority ring when work is
pushed to it, reducing latency for high priority submissions.”h]”hŒŒPreemption allows Adreno GPUs to switch to a higher priority ring when work is
pushed to it, reducing latency for high priority submissions.”…””}”(hhËhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K	hh¶hžhubhÊ)”}”(hX`  When preemption is enabled 4 rings are initialized, corresponding to different
priority levels. Having multiple rings is purely a software concept as the GPU
only has registers to keep track of one graphics ring.
The kernel is able to switch which ring is currently being processed by
requesting preemption. When certain conditions are met, depending on the
priority level, the GPU will save its current state in a series of buffers,
then restores state from a similar set of buffers specified by the kernel. It
then resumes execution and fires an IRQ to let the kernel know the context
switch has completed.”h]”hX`  When preemption is enabled 4 rings are initialized, corresponding to different
priority levels. Having multiple rings is purely a software concept as the GPU
only has registers to keep track of one graphics ring.
The kernel is able to switch which ring is currently being processed by
requesting preemption. When certain conditions are met, depending on the
priority level, the GPU will save its current state in a series of buffers,
then restores state from a similar set of buffers specified by the kernel. It
then resumes execution and fires an IRQ to let the kernel know the context
switch has completed.”…””}”(hhÙhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhÊ)”}”(hXs  This mechanism can be used by the kernel to switch between rings. Whenever a
submission occurs the kernel finds the highest priority ring which isn't empty
and preempts to it if said ring is not the one being currently executed. This is
also done whenever a submission completes to make sure execution resumes on a
lower priority ring when a higher priority ring is done.”h]”hXu  This mechanism can be used by the kernel to switch between rings. Whenever a
submission occurs the kernel finds the highest priority ring which isnâ€™t empty
and preempts to it if said ring is not the one being currently executed. This is
also done whenever a submission completes to make sure execution resumes on a
lower priority ring when a higher priority ring is done.”…””}”(hhçhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒPreemption levels”h]”hŒPreemption levels”…””}”(hhøhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hhõhžhhŸh³h KubhÊ)”}”(hXJ  Preemption can only occur at certain boundaries. The exact conditions can be
configured by changing the preemption level, this allows to compromise between
latency (ie. the time that passes between when the kernel requests preemption
and when the SQE begins saving state) and overhead (the amount of state that
needs to be saved).”h]”hXJ  Preemption can only occur at certain boundaries. The exact conditions can be
configured by changing the preemption level, this allows to compromise between
latency (ie. the time that passes between when the kernel requests preemption
and when the SQE begins saving state) and overhead (the amount of state that
needs to be saved).”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhhõhžhubhÊ)”}”(hŒThe GPU offers 3 levels:”h]”hŒThe GPU offers 3 levels:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K%hhõhžhubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hX  Level 0
Preemption only occurs at the submission level. This requires the least amount
of state to be saved as the execution of userspace submitted IBs is never
interrupted, however it offers very little benefit compared to not enabling
preemption of any kind.
”h]”(hŒterm”“”)”}”(hŒLevel 0”h]”hŒLevel 0”…””}”(hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h K+hj)  ubhŒ
definition”“”)”}”(hhh]”hÊ)”}”(hŒüPreemption only occurs at the submission level. This requires the least amount
of state to be saved as the execution of userspace submitted IBs is never
interrupted, however it offers very little benefit compared to not enabling
preemption of any kind.”h]”hŒüPreemption only occurs at the submission level. This requires the least amount
of state to be saved as the execution of userspace submitted IBs is never
interrupted, however it offers very little benefit compared to not enabling
preemption of any kind.”…””}”(hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K(hj?  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=  hj)  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h K+hj$  ubj(  )”}”(hŒtLevel 1
Preemption occurs at either bin level, if using GMEM rendering, or draw level
in the sysmem rendering case.
”h]”(j.  )”}”(hŒLevel 1”h]”hŒLevel 1”…””}”(hj`  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h K/hj\  ubj>  )”}”(hhh]”hÊ)”}”(hŒkPreemption occurs at either bin level, if using GMEM rendering, or draw level
in the sysmem rendering case.”h]”hŒkPreemption occurs at either bin level, if using GMEM rendering, or draw level
in the sysmem rendering case.”…””}”(hjq  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K.hjn  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=  hj\  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h K/hj$  hžhubj(  )”}”(hŒ)Level 2
Preemption occurs at draw level.
”h]”(j.  )”}”(hŒLevel 2”h]”hŒLevel 2”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h K2hj‹  ubj>  )”}”(hhh]”hÊ)”}”(hŒ Preemption occurs at draw level.”h]”hŒ Preemption occurs at draw level.”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K2hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=  hj‹  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h K2hj$  hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1j"  hhõhžhhŸh³h NubhÊ)”}”(hŒ3Level 1 is the mode that is used by the msm driver.”h]”hŒ3Level 1 is the mode that is used by the msm driver.”…””}”(hjÀ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K4hhõhžhubhÊ)”}”(hXó  Additionally the GPU allows to specify a `skip_save_restore` option. This
disables the saving and restoring of all registers except those relating to the
operation of the SQE itself, reducing overhead. Saving and restoring is only
skipped when using GMEM with Level 1 preemption. When enabling this userspace is
expected to set the state that isn't preserved whenever preemption occurs which
is done by specifying preamble and postambles. Those are IBs that are executed
before and after preemption.”h]”(hŒ)Additionally the GPU allows to specify a ”…””}”(hjÎ  hžhhŸNh NubhŒtitle_reference”“”)”}”(hŒ`skip_save_restore`”h]”hŒskip_save_restore”…””}”(hjØ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjÎ  ubhX¹   option. This
disables the saving and restoring of all registers except those relating to the
operation of the SQE itself, reducing overhead. Saving and restoring is only
skipped when using GMEM with Level 1 preemption. When enabling this userspace is
expected to set the state that isnâ€™t preserved whenever preemption occurs which
is done by specifying preamble and postambles. Those are IBs that are executed
before and after preemption.”…””}”(hjÎ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K6hhõhžhubeh}”(h]”Œpreemption-levels”ah ]”h"]”Œpreemption levels”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒPreemption buffers”h]”hŒPreemption buffers”…””}”(hjû  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjø  hžhhŸh³h K?ubhÊ)”}”(hX„  A series of buffers are necessary to store the state of rings while they are not
being executed. There are different kinds of preemption records and most of
those require one buffer per ring. This is because preemption never occurs
between submissions on the same ring, which always run in sequence when the ring
is active. This means that only one context per ring is effectively active.”h]”hX„  A series of buffers are necessary to store the state of rings while they are not
being executed. There are different kinds of preemption records and most of
those require one buffer per ring. This is because preemption never occurs
between submissions on the same ring, which always run in sequence when the ring
is active. This means that only one context per ring is effectively active.”…””}”(hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KAhjø  hžhubj#  )”}”(hhh]”(j(  )”}”(hX9  SMMU_INFO
This buffer contains info about the current SMMU configuration such as the
ttbr0 register. The SQE firmware isn't actually able to save this record.
As a result SMMU info must be saved manually from the CP to a buffer and the
SMMU record updated with info from said buffer before triggering
preemption.
”h]”(j.  )”}”(hŒ	SMMU_INFO”h]”hŒ	SMMU_INFO”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h KLhj  ubj>  )”}”(hhh]”hÊ)”}”(hX.  This buffer contains info about the current SMMU configuration such as the
ttbr0 register. The SQE firmware isn't actually able to save this record.
As a result SMMU info must be saved manually from the CP to a buffer and the
SMMU record updated with info from said buffer before triggering
preemption.”h]”hX0  This buffer contains info about the current SMMU configuration such as the
ttbr0 register. The SQE firmware isnâ€™t actually able to save this record.
As a result SMMU info must be saved manually from the CP to a buffer and the
SMMU record updated with info from said buffer before triggering
preemption.”…””}”(hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KHhj,  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h KLhj  ubj(  )”}”(hŒ²NON_SECURE
This is the main preemption record where most state is saved. It is mostly
opaque to the kernel except for the first few words that must be initialized
by the kernel.
”h]”(j.  )”}”(hŒ
NON_SECURE”h]”hŒ
NON_SECURE”…””}”(hjM  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h KQhjI  ubj>  )”}”(hhh]”hÊ)”}”(hŒ¦This is the main preemption record where most state is saved. It is mostly
opaque to the kernel except for the first few words that must be initialized
by the kernel.”h]”hŒ¦This is the main preemption record where most state is saved. It is mostly
opaque to the kernel except for the first few words that must be initialized
by the kernel.”…””}”(hj^  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KOhj[  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=  hjI  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h KQhj  hžhubj(  )”}”(hŒ:SECURE
This saves state related to the GPU's secure mode.
”h]”(j.  )”}”(hŒSECURE”h]”hŒSECURE”…””}”(hj|  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h KThjx  ubj>  )”}”(hhh]”hÊ)”}”(hŒ2This saves state related to the GPU's secure mode.”h]”hŒ4This saves state related to the GPUâ€™s secure mode.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KThjŠ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=  hjx  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h KThj  hžhubj(  )”}”(hŒƒNON_PRIV
The intended purpose of this record is unknown. The SQE firmware actually
ignores it and therefore msm doesn't handle it.
”h]”(j.  )”}”(hŒNON_PRIV”h]”hŒNON_PRIV”…””}”(hj«  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h KXhj§  ubj>  )”}”(hhh]”hÊ)”}”(hŒyThe intended purpose of this record is unknown. The SQE firmware actually
ignores it and therefore msm doesn't handle it.”h]”hŒ{The intended purpose of this record is unknown. The SQE firmware actually
ignores it and therefore msm doesnâ€™t handle it.”…””}”(hj¼  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KWhj¹  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=  hj§  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h KXhj  hžhubj(  )”}”(hŒFCOUNTER
This record is used to save and restore performance counters.
”h]”(j.  )”}”(hŒCOUNTER”h]”hŒCOUNTER”…””}”(hjÚ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j-  hŸh³h K[hjÖ  ubj>  )”}”(hhh]”hÊ)”}”(hŒ=This record is used to save and restore performance counters.”h]”hŒ=This record is used to save and restore performance counters.”…””}”(hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K[hjè  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=  hjÖ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j'  hŸh³h K[hj  hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1j"  hjø  hžhhŸh³h NubhÊ)”}”(hXÌ  Handling the permissions of those buffers is critical for security. All but the
NON_PRIV records need to be inaccessible from userspace, so they must be mapped
in the kernel address space with the MSM_BO_MAP_PRIV flag.
For example, making the NON_SECURE record accessible from userspace would allow
any process to manipulate a saved ring's RPTR which can be used to skip the
execution of some packets in a ring and execute user commands with higher
privileges.”h]”hXÎ  Handling the permissions of those buffers is critical for security. All but the
NON_PRIV records need to be inaccessible from userspace, so they must be mapped
in the kernel address space with the MSM_BO_MAP_PRIV flag.
For example, making the NON_SECURE record accessible from userspace would allow
any process to manipulate a saved ringâ€™s RPTR which can be used to skip the
execution of some packets in a ring and execute user commands with higher
privileges.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K]hjø  hžhubeh}”(h]”Œpreemption-buffers”ah ]”h"]”Œpreemption buffers”ah$]”h&]”uh1h´hh¶hžhhŸh³h K?ubeh}”(h]”Œmsm-preemption”ah ]”h"]”Œmsm preemption”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jL  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j&  j#  jõ  jò  j  j  uŒ	nametypes”}”(j&  ‰jõ  ‰j  ‰uh}”(j#  h¶jò  hõj  jø  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.