Ksphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/gpu/msm-crash-dumpmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/gpu/msm-crash-dumpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/gpu/msm-crash-dumpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/gpu/msm-crash-dumpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/gpu/msm-crash-dumpmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/gpu/msm-crash-dumpmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hMSM Crash Dump Formath]hMSM Crash Dump Format}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/gpu/msm-crash-dump.rsthKubh paragraph)}(hFollowing a GPU hang the MSM driver outputs debugging information via /sys/kernel/dri/X/show or via devcoredump (/sys/class/devcoredump/dcdX/data). This document describes how the output is formatted.h]hFollowing a GPU hang the MSM driver outputs debugging information via /sys/kernel/dri/X/show or via devcoredump (/sys/class/devcoredump/dcdX/data). This document describes how the output is formatted.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hEach entry is in the form key: value. Sections headers will not have a value and all the contents of a section will be indented two spaces from the header. Each section might have multiple array entries the start of which is designated by a (-).h]hEach entry is in the form key: value. Sections headers will not have a value and all the contents of a section will be indented two spaces from the header. Each section might have multiple array entries the start of which is designated by a (-).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hMappingsh]hMappings}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubhdefinition_list)}(hhh](hdefinition_list_item)}(hAkernel The kernel version that generated the dump (UTS_RELEASE). h](hterm)}(hkernelh]hkernel}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubh definition)}(hhh]h)}(h9The kernel version that generated the dump (UTS_RELEASE).h]h9The kernel version that generated the dump (UTS_RELEASE).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubh)}(h0module The module that generated the crashdump. h](h)}(hmoduleh]hmodule}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubj)}(hhh]h)}(h(The module that generated the crashdump.h]h(The module that generated the crashdump.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hAtime The kernel time at crash formatted as seconds.microseconds. h](h)}(htimeh]htime}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjOubj)}(hhh]h)}(h;The kernel time at crash formatted as seconds.microseconds.h]h;The kernel time at crash formatted as seconds.microseconds.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjaubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h:comm Comm string for the binary that generated the fault. h](h)}(hcommh]hcomm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj~ubj)}(hhh]h)}(h4Comm string for the binary that generated the fault.h]h4Comm string for the binary that generated the fault.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h>cmdline Command line for the binary that generated the fault. h](h)}(hcmdlineh]hcmdline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubj)}(hhh]h)}(h5Command line for the binary that generated the fault.h]h5Command line for the binary that generated the fault.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hlrevision ID of the GPU that generated the crash formatted as core.major.minor.patchlevel separated by dots. h](h)}(hrevisionh]hrevision}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjubj)}(hhh]h)}(hbID of the GPU that generated the crash formatted as core.major.minor.patchlevel separated by dots.h]hbID of the GPU that generated the crash formatted as core.major.minor.patchlevel separated by dots.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK$hhhhubh)}(hxrbbm-status The current value of RBBM_STATUS which shows what top level GPU components are in use at the time of crash. h](h)}(h rbbm-statush]h rbbm-status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hj ubj)}(hhh]h)}(hkThe current value of RBBM_STATUS which shows what top level GPU components are in use at the time of crash.h]hkThe current value of RBBM_STATUS which shows what top level GPU components are in use at the time of crash.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhhhK(hhhhubh)}(hXringbuffer Section containing the contents of each ringbuffer. Each ringbuffer is identified with an id number. id Ringbuffer ID (0 based index). Each ringbuffer in the section will have its own unique id. iova GPU address of the ringbuffer. last-fence The last fence that was issued on the ringbuffer retired-fence The last fence retired on the ringbuffer. rptr The current read pointer (rptr) for the ringbuffer. wptr The current write pointer (wptr) for the ringbuffer. size Maximum size of the ringbuffer programmed in the hardware. data The contents of the ring encoded as ascii85. Only the used portions of the ring will be printed. h](h)}(h ringbufferh]h ringbuffer}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKEhj:ubj)}(hhh](h)}(hdSection containing the contents of each ringbuffer. Each ringbuffer is identified with an id number.h]hdSection containing the contents of each ringbuffer. Each ringbuffer is identified with an id number.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjLubh)}(hhh](h)}(h^id Ringbuffer ID (0 based index). Each ringbuffer in the section will have its own unique id.h](h)}(hidh]hid}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hj`ubj)}(hhh]h)}(h[Ringbuffer ID (0 based index). Each ringbuffer in the section will have its own unique id.h]h[Ringbuffer ID (0 based index). Each ringbuffer in the section will have its own unique id.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjrubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1hhhhK/hj]ubh)}(h$iova GPU address of the ringbuffer. h](h)}(hiovah]hiova}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubj)}(hhh]h)}(hGPU address of the ringbuffer.h]hGPU address of the ringbuffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK2hj]ubh)}(hhjKubj)}(hhh]h)}(h4The current write pointer (wptr) for the ringbuffer.h]h4The current write pointer (wptr) for the ringbuffer.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hj]ubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1hhhhK>hj]ubh)}(h@size Maximum size of the ringbuffer programmed in the hardware. h](h)}(hsizeh]hsize}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjzubj)}(hhh]h)}(h:Maximum size of the ringbuffer programmed in the hardware.h]h:Maximum size of the ringbuffer programmed in the hardware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1hhhhKAhj]ubh)}(hgdata The contents of the ring encoded as ascii85. Only the used portions of the ring will be printed. h](h)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKEhjubj)}(hhh]h)}(haThe contents of the ring encoded as ascii85. Only the used portions of the ring will be printed.h]haThe contents of the ring encoded as ascii85. Only the used portions of the ring will be printed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKEhj]ubeh}(h]h ]h"]h$]h&]uh1hhjLubeh}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1hhhhKEhhhhubh)}(hXYbo List of buffers from the hanging submission if available. Each buffer object will have a uinque iova. iova GPU address of the buffer object. size Allocated size of the buffer object. data The contents of the buffer object encoded with ascii85. Only Trailing zeros at the end of the buffer will be skipped. h](h)}(hboh]hbo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjubj)}(hhh](h)}(heList of buffers from the hanging submission if available. Each buffer object will have a uinque iova.h]heList of buffers from the hanging submission if available. Each buffer object will have a uinque iova.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubh)}(hhh](h)}(h'iova GPU address of the buffer object. h](h)}(hiovah]hiova}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjubj)}(hhh]h)}(h!GPU address of the buffer object.h]h!GPU address of the buffer object.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKLhj ubh)}(h*size Allocated size of the buffer object. h](h)}(hsizeh]hsize}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhj?ubj)}(hhh]h)}(h$Allocated size of the buffer object.h]h$Allocated size of the buffer object.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjQubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1hhhhKOhj ubh)}(h|data The contents of the buffer object encoded with ascii85. Only Trailing zeros at the end of the buffer will be skipped. h](h)}(hdatah]hdata}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjnubj)}(hhh]h)}(hvThe contents of the buffer object encoded with ascii85. Only Trailing zeros at the end of the buffer will be skipped.h]hvThe contents of the buffer object encoded with ascii85. Only Trailing zeros at the end of the buffer will be skipped.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1hhhhKShj ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKShhhhubh)}(hregisters Set of registers values. Each entry is on its own line enclosed by brackets { }. offset Byte offset of the register from the start of the GPU memory region. value Hexadecimal value of the register. h](h)}(h registersh]h registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubj)}(hhh](h)}(hPSet of registers values. Each entry is on its own line enclosed by brackets { }.h]hPSet of registers values. Each entry is on its own line enclosed by brackets { }.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubh)}(hhh](h)}(hLoffset Byte offset of the register from the start of the GPU memory region. h](h)}(hoffseth]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjubj)}(hhh]h)}(hDByte offset of the register from the start of the GPU memory region.h]hDByte offset of the register from the start of the GPU memory region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK[hjubh)}(h)value Hexadecimal value of the register. h](h)}(hvalueh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubj)}(hhh]h)}(h"Hexadecimal value of the register.h]h"Hexadecimal value of the register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK^hjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhK^hhhhubh)}(hfregisters-hlsq (5xx only) Register values from the HLSQ aperture. Same format as the register section.h](h)}(hregisters-hlsqh]hregisters-hlsq}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjEubj)}(hhh]h)}(hW(5xx only) Register values from the HLSQ aperture. Same format as the register section.h]hW(5xx only) Register values from the HLSQ aperture. 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