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|-------| |----| | | | | HDMI PLL | D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | R |-------| |----| Processing | | | | | | osd2 | | | |---| Enci ----------|----|-----VDAC------| R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | Encl ----------|----|---------------| M |-------|______|----|____________| |________________| | | ___|__________________________________________________________|_______________|h]hXDMC|---------------VPU (Video Processing Unit)----------------|------HHI------| | vd1 _______ _____________ _________________ | | D |-------| |----| | | | | HDMI PLL | D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | R |-------| |----| Processing | | | | | | osd2 | | | |---| Enci ----------|----|-----VDAC------| R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | Encl ----------|----|---------------| M |-------|______|----|____________| |________________| | | ___|__________________________________________________________|_______________|}hjsbah}(h]h ]h"]h$]h&]forcehighlight_args} xml:spacepreservelanguagenoneuh1jhhhKhjshhubeh}(h]video-processing-unitah ]h"]video processing unitah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hVideo Input Unith]hVideo Input Unit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(heVIU Handles the Pixel scanout and the basic Colorspace conversions We handle the following features :h]heVIU Handles the Pixel scanout and the basic Colorspace conversions We handle the following features :}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhjhhubh)}(hhh](h)}(h#OSD1 RGB565/RGB888/xRGB8888 scanouth]h)}(hjh]h#OSD1 RGB565/RGB888/xRGB8888 scanout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hRGB conversion to x/cb/crh]h)}(hjh]hRGB conversion to x/cb/cr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h'Progressive or Interlace buffer scanouth]h)}(hjh]h'Progressive or Interlace buffer scanout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hOSD1 Commit on Vsynch]h)}(hjh]hOSD1 Commit on Vsync}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hHDR OSD matrix for GXL/GXM h]h)}(hHDR OSD matrix for GXL/GXMh]hHDR OSD matrix for GXL/GXM}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhj4ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jqjruh1hhjhKhjhhubh)}(hWhat is missing :h]hWhat is missing :}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhjhhubh)}(hhh](h)}(h'BGR888/xBGR8888/BGRx8888/BGRx8888 modesh]h)}(hjgh]h'BGR888/xBGR8888/BGRx8888/BGRx8888 modes}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhjeubah}(h]h ]h"]h$]h&]uh1hhjbubh)}(hYUV4:2:2 Y0CbY1Cr scanouth]h)}(hjh]hYUV4:2:2 Y0CbY1Cr scanout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chKhj}ubah}(h]h ]h"]h$]h&]uh1hhjbubh)}(h(Conversion to YUV 4:4:4 from 4:2:2 inputh]h)}(hjh]h(Conversion to YUV 4:4:4 from 4:2:2 input}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chK hjubah}(h]h ]h"]h$]h&]uh1hhjbubh)}(hColorkey Alpha matchingh]h)}(hjh]hColorkey Alpha matching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chK!hjubah}(h]h ]h"]h$]h&]uh1hhjbubh)}(hBig endian scanouth]h)}(hjh]hBig endian scanout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chK"hjubah}(h]h ]h"]h$]h&]uh1hhjbubh)}(hX/Y reverse scanouth]h)}(hjh]hX/Y reverse scanout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chK#hjubah}(h]h ]h"]h$]h&]uh1hhjbubh)}(hGlobal alpha setuph]h)}(hjh]hGlobal alpha setup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chK$hjubah}(h]h ]h"]h$]h&]uh1hhjbubh)}(h5OSD2 support, would need interlace switching on vsynch]h)}(hjh]h5OSD2 support, would need interlace switching on vsync}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chK%hj ubah}(h]h ]h"]h$]h&]uh1hhjbubh)}(h*OSD1 full scaling to support TV overscan h]h)}(h(OSD1 full scaling to support TV overscanh]h(OSD1 full scaling to support TV overscan}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:30: ./drivers/gpu/drm/meson/meson_viu.chK&hj%ubah}(h]h ]h"]h$]h&]uh1hhjbubeh}(h]h ]h"]h$]h&]jqjruh1hhjvhKhjhhubeh}(h]video-input-unitah ]h"]video input unitah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hVideo Post Processingh]hVideo Post Processing}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhK"ubh)}(hmVPP Handles all the Post Processing after the Scanout from the VIU We handle the following post processings :h]hmVPP Handles all the Post Processing after the Scanout from the VIU We handle the following post processings :}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjLhhubh)}(hhh](h)}(hPPostblend, Blends the OSD1 only We exclude OSD2, VS1, VS1 and Preblend outputh]hdefinition_list)}(hhh]hdefinition_list_item)}(hMPostblend, Blends the OSD1 only We exclude OSD2, VS1, VS1 and Preblend outputh](hterm)}(hPostblend, Blends the OSD1 onlyh]hPostblend, Blends the OSD1 only}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j~h[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjzubh definition)}(hhh]h)}(h-We exclude OSD2, VS1, VS1 and Preblend outputh]h-We exclude OSD2, VS1, VS1 and Preblend output}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jxhjhKhjuubah}(h]h ]h"]h$]h&]uh1jshjoubah}(h]h ]h"]h$]h&]uh1hhjlubh)}(hfVertical OSD Scaler for OSD1 only, we disable vertical scaler and use it only for interlace scanouth]jt)}(hhh]jy)}(hcVertical OSD Scaler for OSD1 only, we disable vertical scaler and use it only for interlace scanouth](j)}(hAVertical OSD Scaler for OSD1 only, we disable vertical scaler andh]hAVertical OSD Scaler for OSD1 only, we disable vertical scaler and}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j~h[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjubj)}(hhh]h)}(h!use it only for interlace scanouth]h!use it only for interlace scanout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jxhjhKhjubah}(h]h ]h"]h$]h&]uh1jshjubah}(h]h ]h"]h$]h&]uh1hhjlubh)}(h.Intermediate FIFO with default Amlogic values h]h)}(h-Intermediate FIFO with default Amlogic valuesh]h-Intermediate FIFO with default Amlogic values}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjubah}(h]h ]h"]h$]h&]uh1hhjlubeh}(h]h ]h"]h$]h&]jqjruh1hhjhKhjLhhubh)}(hWhat is missing :h]hWhat is missing :}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjLhhubh)}(hhh](h)}(h&Preblend for video overlay pre-scalingh]h)}(hj2h]h&Preblend for video overlay pre-scaling}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhj0ubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(h#OSD2 support for cursor framebufferh]h)}(hjJh]h#OSD2 support for cursor framebuffer}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjHubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(h"Video pre-scaling before postblendh]h)}(hjbh]h"Video pre-scaling before postblend}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhj`ubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(h;Full Vertical/Horizontal OSD scaling to support TV overscanh]h)}(hjzh]h;Full Vertical/Horizontal OSD scaling to support TV overscan}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjxubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(hHDR conversion h]h)}(hHDR conversionh]hHDR conversion}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/meson:36: ./drivers/gpu/drm/meson/meson_vpp.chKhjubah}(h]h ]h"]h$]h&]uh1hhj-ubeh}(h]h ]h"]h$]h&]jqjruh1hhjAhKhjLhhubeh}(h]video-post-processingah ]h"]video post processingah$]h&]uh1hhhhhhhhK"ubh)}(hhh](h)}(h Video Encoderh]h Video Encoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK(ubh)}(hZVENC Handle the pixels encoding to the output formats. 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We handle the following encodings :}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chKhjhhubh)}(hhh](h)}(hGCVBS Encoding via the ENCI encoder and VDAC digital to analog converterh]h)}(hjh]hGCVBS Encoding via the ENCI encoder and VDAC digital to analog converter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h(TMDS/HDMI Encoding via ENCI_DIV and ENCPh]h)}(hjh]h(TMDS/HDMI Encoding via ENCI_DIV and ENCP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h)Setup of more clock rates for HDMI modes h]h)}(h(Setup of more clock rates for HDMI modesh]h(Setup of more clock rates for HDMI modes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chKhj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jqjruh1hhjhKhjhhubh)}(hWhat is missing :h]hWhat is missing :}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chKhjhhubh)}(hhh](h)}(hLCD Panel encoding via ENCLh]h)}(hj=h]hLCD Panel encoding via ENCL}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chKhj;ubah}(h]h ]h"]h$]h&]uh1hhj8ubh)}(hTV Panel encoding via ENCT h]h)}(hTV Panel encoding via ENCTh]hTV Panel encoding via ENCT}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chKhjSubah}(h]h ]h"]h$]h&]uh1hhj8ubeh}(h]h ]h"]h$]h&]jqjruh1hhjLhKhjhhubh)}(h VENC paths :h]h VENC paths :}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chK hjhhubj)}(hX _____ _____ ____________________ vd1---| |-| | | VENC /---------|----VDAC vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-| osd1--| |-| | | \ | X--HDMI-TX osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-| | | | | \--ENCL-----------|----LVDS |____________________|h]hX _____ _____ ____________________ vd1---| |-| | | VENC /---------|----VDAC vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-| osd1--| |-| | | \ | X--HDMI-TX osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-| | | | | \--ENCL-----------|----LVDS |____________________|}hjsbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chK"hjhhubh)}(hXThe ENCI is designed for PAl or NTSC encoding and can go through the VDAC directly for CVBS encoding or through the ENCI_DVI encoder for HDMI. The ENCP is designed for Progressive encoding but can also generate 1080i interlaced pixels, and was initially designed to encode pixels for VDAC to output RGB ou YUV analog outputs. It's output is only used through the ENCP_DVI encoder for HDMI. The ENCL LVDS encoder is not implemented.h]hXThe ENCI is designed for PAl or NTSC encoding and can go through the VDAC directly for CVBS encoding or through the ENCI_DVI encoder for HDMI. The ENCP is designed for Progressive encoding but can also generate 1080i interlaced pixels, and was initially designed to encode pixels for VDAC to output RGB ou YUV analog outputs. It’s output is only used through the ENCP_DVI encoder for HDMI. The ENCL LVDS encoder is not implemented.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chK-hjhhubh)}(hThe ENCI and ENCP encoders needs specially defined parameters for each supported mode and thus cannot be determined from standard video timings.h]hThe ENCI and ENCP encoders needs specially defined parameters for each supported mode and thus cannot be determined from standard video timings.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chK5hjhhubh)}(hThe ENCI end ENCP DVI encoders are more generic and can generate any timings from the pixel data generated by ENCI or ENCP, so can use the standard video timings are source for HW parameters.h]hThe ENCI end ENCP DVI encoders are more generic and can generate any timings from the pixel data generated by ENCI or ENCP, so can use the standard video timings are source for HW parameters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:42: ./drivers/gpu/drm/meson/meson_venc.chK8hjhhubeh}(h] video-encoderah ]h"] video encoderah$]h&]uh1hhhhhhhhK(ubh)}(hhh](h)}(h Video Clocksh]h Video Clocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK.ubh)}(hgVCLK is the "Pixel Clock" frequency generator from a dedicated PLL. We handle the following encodings :h]hkVCLK is the “Pixel Clock” frequency generator from a dedicated PLL. We handle the following encodings :}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chKhjhhubh)}(hhh](h)}(h?CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocksh]h)}(hjh]h?CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hHDMI Pixel Clocks generation h]h)}(hHDMI Pixel Clocks generationh]hHDMI Pixel Clocks generation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jqjruh1hhjhKhjhhubh)}(hWhat is missing :h]hWhat is missing :}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chKhjhhubh)}(hhh]h)}(h.Genenate Pixel clocks for 2K/4K 10bit formats h]h)}(h-Genenate Pixel clocks for 2K/4K 10bit formatsh]h-Genenate Pixel clocks for 2K/4K 10bit formats}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chKhj4ubah}(h]h ]h"]h$]h&]uh1hhj1ubah}(h]h ]h"]h$]h&]jqjruh1hhjFhKhjhhubh)}(hClock generator scheme :h]hClock generator scheme :}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chKhjhhubj)}(hX __________ _________ _____ | | | | | |--ENCI | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL |__________| |_________| \ | MUX |--ENCP --VCLK2-| |--VDAC |_____|--HDMI-TXh]hX __________ _________ _____ | | | | | |--ENCI | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL |__________| |_________| \ | MUX |--ENCP --VCLK2-| |--VDAC |_____|--HDMI-TX}hjbsbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chKhjhhubh)}(hFinal clocks can take input for either VCLK or VCLK2, but VCLK is the preferred path for HDMI clocking and VCLK2 is the preferred path for CVBS VDAC clocking.h]hFinal clocks can take input for either VCLK or VCLK2, but VCLK is the preferred path for HDMI clocking and VCLK2 is the preferred path for CVBS VDAC clocking.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chK%hjhhubh)}(hIVCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.h]hIVCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chK)hjhhubh)}(h|The PLL_DIV can achieve an additional fractional dividing like 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.h]h|The PLL_DIV can achieve an additional fractional dividing like 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/meson:48: ./drivers/gpu/drm/meson/meson_vclk.chK+hjhhubeh}(h] video-clocksah ]h"] video clocksah$]h&]uh1hhhhhhhhK.ubh)}(hhh](h)}(hHDMI Video Outputh]hHDMI Video Output}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK4ubh)}(hHDMI Output is composed of :h]hHDMI Output is composed of :}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chK$hjhhubh)}(hhh](h)}(h(A Synopsys DesignWare HDMI Controller IPh]h)}(hjh]h(A Synopsys DesignWare HDMI Controller IP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chK&hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h2A TOP control block controlling the Clocks and PHYh]h)}(hjh]h2A TOP control block controlling the Clocks and PHY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chK'hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h8A custom HDMI PHY in order convert video to TMDS signal h]h)}(h7A custom HDMI PHY in order convert video to TMDS signalh]h7A custom HDMI PHY in order convert video to TMDS signal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chK(hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jqjruh1hhjhK&hjhhubj)}(hX ___________________________________ | HDMI TOP |<= HPD |___________________________________| | | | | Synopsys HDMI | HDMI PHY |=> TMDS | Controller |________________| |___________________________________|<=> DDCh]hX ___________________________________ | HDMI TOP |<= HPD |___________________________________| | | | | Synopsys HDMI | HDMI PHY |=> TMDS | Controller |________________| |___________________________________|<=> DDC}hjsbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjjuh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chK*hjhhubh)}(hX/The HDMI TOP block only supports HPD sensing. The Synopsys HDMI Controller interrupt is routed through the TOP Block interrupt. Communication to the TOP Block and the Synopsys HDMI Controller is done a pair of addr+read/write registers. The HDMI PHY is configured by registers in the HHI register block.h]hX/The HDMI TOP block only supports HPD sensing. The Synopsys HDMI Controller interrupt is routed through the TOP Block interrupt. Communication to the TOP Block and the Synopsys HDMI Controller is done a pair of addr+read/write registers. The HDMI PHY is configured by registers in the HHI register block.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chK5hjhhubh)}(hXHPixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux selects either the ENCI encoder for the 576i or 480i formats or the ENCP encoder for all the other formats including interlaced HD formats. The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate DVI timings for the HDMI controller.h]hXHPixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux selects either the ENCI encoder for the 576i or 480i formats or the ENCP encoder for all the other formats including interlaced HD formats. The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate DVI timings for the HDMI controller.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chK>hjhhubh)}(h}GXBB, GXL and GXM embeds the Synopsys DesignWare HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF audio source interfaces.h]h}GXBB, GXL and GXM embeds the Synopsys DesignWare HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF audio source interfaces.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKGhjhhubh)}(h"We handle the following features :h]h"We handle the following features :}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKKhjhhubh)}(hhh](h)}(hHPD Rise & Fall interrupth]h)}(hjnh]hHPD Rise & Fall interrupt}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKMhjlubah}(h]h ]h"]h$]h&]uh1hhjiubh)}(hHDMI Controller Interrupth]h)}(hjh]hHDMI Controller Interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKNhjubah}(h]h ]h"]h$]h&]uh1hhjiubh)}(h!HDMI PHY Init for 480i to 1080p60h]h)}(hjh]h!HDMI PHY Init for 480i to 1080p60}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKOhjubah}(h]h ]h"]h$]h&]uh1hhjiubh)}(h+VENC & HDMI Clock setup for 480i to 1080p60h]h)}(hjh]h+VENC & HDMI Clock setup for 480i to 1080p60}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKPhjubah}(h]h ]h"]h$]h&]uh1hhjiubh)}(h$VENC Mode setup for 480i to 1080p60 h]h)}(h#VENC Mode setup for 480i to 1080p60h]h#VENC Mode setup for 480i to 1080p60}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKQhjubah}(h]h ]h"]h$]h&]uh1hhjiubeh}(h]h ]h"]h$]h&]jqjruh1hhj}hKMhjhhubh)}(hWhat is missing :h]hWhat is missing :}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKShjhhubh)}(hhh](h)}(h,PHY, Clock and Mode setup for 2k && 4k modesh]h)}(hjh]h,PHY, Clock and Mode setup for 2k && 4k modes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKUhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h"SDDC Scrambling mode for HDMI 2.0ah]h)}(hjh]h"SDDC Scrambling mode for HDMI 2.0a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/meson:54: ./drivers/gpu/drm/meson/meson_dw_hdmi.chKVhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h HDCP Setuph]h)}(hj/h]h HDCP Setup}(hj1hhhNhNubah}(h]h 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