Gsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget"/translations/zh_CN/gpu/komeda-kmsmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/zh_TW/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/it_IT/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/ja_JP/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/ko_KR/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/pt_BR/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/sp_SP/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhubh)}(hXD71 scaler mostly only has the half horizontal input/output capabilities compared with Layer, like if Layer supports 4K input size, the scaler only can support 2K input/output in the same time. To achieve the ful frame scaling, D71 introduces Layer Split, which splits the whole image to two half parts and feeds them to two Layers A and B, and does the scaling independently. After scaling the result need to be fed to merger to merge two part images together, and then output merged result to compiz.h]hXD71 scaler mostly only has the half horizontal input/output capabilities compared with Layer, like if Layer supports 4K input size, the scaler only can support 2K input/output in the same time. To achieve the ful frame scaling, D71 introduces Layer Split, which splits the whole image to two half parts and feeds them to two Layers A and B, and does the scaling independently. After scaling the result need to be fed to merger to merge two part images together, and then output merged result to compiz.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjhhubeh}(h]mergerah ]h"]mergerah$]h&]uh1hhhhhhhhK>ubh)}(hhh](h)}(hSplitterh]hSplitter}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhKHubh)}(hSimilar to Layer Split, but Splitter is used for writeback, which splits the compiz result to two parts and then feed them to two scalers.h]hSimilar to Layer Split, but Splitter is used for writeback, which splits the compiz result to two parts and then feed them to two scalers.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhj+hhubeh}(h]splitterah ]h"]splitterah$]h&]uh1hhhhhhhhKHubeh}(h] overview-of-d71-like-display-ipsah ]h"] overview of d71 like display ipsah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hPossible D71 Pipeline usageh]hPossible D71 Pipeline usage}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhKMubh)}(hBenefitting from the modularized architecture, D71 pipelines can be easily adjusted to fit different usages. And D71 has two pipelines, which support two types of working mode:h]hBenefitting from the modularized architecture, D71 pipelines can be easily adjusted to fit different usages. And D71 has two pipelines, which support two types of working mode:}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjZhhubh bullet_list)}(hhh](h list_item)}(h`Dual display mode Two pipelines work independently and separately to drive two display outputs. h]h)}(h_Dual display mode Two pipelines work independently and separately to drive two display outputs.h]h_Dual display mode Two pipelines work independently and separately to drive two display outputs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjubah}(h]h ]h"]h$]h&]uh1j~hj{hhhhhNubj)}(hX;Single display mode Two pipelines work together to drive only one display output. On this mode, pipeline_B doesn't work independently, but outputs its composition result into pipeline_A, and its pixel timing also derived from pipeline_A.timing_ctrlr. The pipeline_B works just like a "slave" of pipeline_A(master) h](h)}(hQSingle display mode Two pipelines work together to drive only one display output.h]hQSingle display mode Two pipelines work together to drive only one display output.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubh)}(hOn this mode, pipeline_B doesn't work independently, but outputs its composition result into pipeline_A, and its pixel timing also derived from pipeline_A.timing_ctrlr. The pipeline_B works just like a "slave" of pipeline_A(master)h]hOn this mode, pipeline_B doesn’t work independently, but outputs its composition result into pipeline_A, and its pixel timing also derived from pipeline_A.timing_ctrlr. The pipeline_B works just like a “slave” of pipeline_A(master)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubeh}(h]h ]h"]h$]h&]uh1j~hj{hhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jyhhhKShjZhhubh)}(hhh](h)}(hSingle pipeline data flowh]hSingle pipeline data flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK_ubhfigure)}(hhh](kfigure kernel_render)}(hhh]h literal_block)}(hXdigraph single_ppl { rankdir=LR; subgraph { "Memory"; "Monitor"; } subgraph cluster_pipeline { style=dashed node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-0"; "Scaler-1"; "Scaler-0/1" } node [bgcolor=grey style=filled] "Layer-0" -> "Scaler-0" "Layer-1" -> "Scaler-0" "Layer-2" -> "Scaler-1" "Layer-3" -> "Scaler-1" "Layer-0" -> "Compiz" "Layer-1" -> "Compiz" "Layer-2" -> "Compiz" "Layer-3" -> "Compiz" "Scaler-0" -> "Compiz" "Scaler-1" -> "Compiz" "Compiz" -> "Scaler-0/1" -> "Wb_layer" "Compiz" -> "Improc" -> "Timing Controller" } "Wb_layer" -> "Memory" "Timing Controller" -> "Monitor" }h]hXdigraph single_ppl { rankdir=LR; subgraph { "Memory"; "Monitor"; } subgraph cluster_pipeline { style=dashed node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-0"; "Scaler-1"; "Scaler-0/1" } node [bgcolor=grey style=filled] "Layer-0" -> "Scaler-0" "Layer-1" -> "Scaler-0" "Layer-2" -> "Scaler-1" "Layer-3" -> "Scaler-1" "Layer-0" -> "Compiz" "Layer-1" -> "Compiz" "Layer-2" -> "Compiz" "Layer-3" -> "Compiz" "Scaler-0" -> "Compiz" "Scaler-1" -> "Compiz" "Compiz" -> "Scaler-0/1" -> "Wb_layer" "Compiz" -> "Improc" -> "Timing Controller" } "Wb_layer" -> "Memory" "Timing Controller" -> "Monitor" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]altSingle pipeline digraphsrclangDOTuh1jhjubhcaption)}(hSingle pipeline data flowh]hSingle pipeline data flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id1ah ]h"]h$]h&]altjcaptionjuh1jhjhhhhhNubeh}(h]single-pipeline-data-flowah ]h"]single pipeline data flowah$]h&]uh1hhjZhhhhhK_ referencedKubh)}(hhh](h)}(h Dual pipeline with Slave enabledh]h Dual pipeline with Slave enabled}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj)}(hhh](j)}(hhh]j)}(hX&digraph slave_ppl { rankdir=LR; subgraph { "Memory"; "Monitor"; } node [shape=box] subgraph cluster_pipeline_slave { style=dashed label="Slave Pipeline_B" node [shape=box] { node [bgcolor=grey style=dashed] "Slave.Scaler-0"; "Slave.Scaler-1"; } node [bgcolor=grey style=filled] "Slave.Layer-0" -> "Slave.Scaler-0" "Slave.Layer-1" -> "Slave.Scaler-0" "Slave.Layer-2" -> "Slave.Scaler-1" "Slave.Layer-3" -> "Slave.Scaler-1" "Slave.Layer-0" -> "Slave.Compiz" "Slave.Layer-1" -> "Slave.Compiz" "Slave.Layer-2" -> "Slave.Compiz" "Slave.Layer-3" -> "Slave.Compiz" "Slave.Scaler-0" -> "Slave.Compiz" "Slave.Scaler-1" -> "Slave.Compiz" } subgraph cluster_pipeline_master { style=dashed label="Master Pipeline_A" node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-0"; "Scaler-1"; "Scaler-0/1" } node [bgcolor=grey style=filled] "Layer-0" -> "Scaler-0" "Layer-1" -> "Scaler-0" "Layer-2" -> "Scaler-1" "Layer-3" -> "Scaler-1" "Slave.Compiz" -> "Compiz" "Layer-0" -> "Compiz" "Layer-1" -> "Compiz" "Layer-2" -> "Compiz" "Layer-3" -> "Compiz" "Scaler-0" -> "Compiz" "Scaler-1" -> "Compiz" "Compiz" -> "Scaler-0/1" -> "Wb_layer" "Compiz" -> "Improc" -> "Timing Controller" } "Wb_layer" -> "Memory" "Timing Controller" -> "Monitor" }h]hX&digraph slave_ppl { rankdir=LR; subgraph { "Memory"; "Monitor"; } node [shape=box] subgraph cluster_pipeline_slave { style=dashed label="Slave Pipeline_B" node [shape=box] { node [bgcolor=grey style=dashed] "Slave.Scaler-0"; "Slave.Scaler-1"; } node [bgcolor=grey style=filled] "Slave.Layer-0" -> "Slave.Scaler-0" "Slave.Layer-1" -> "Slave.Scaler-0" "Slave.Layer-2" -> "Slave.Scaler-1" "Slave.Layer-3" -> "Slave.Scaler-1" "Slave.Layer-0" -> "Slave.Compiz" "Slave.Layer-1" -> "Slave.Compiz" "Slave.Layer-2" -> "Slave.Compiz" "Slave.Layer-3" -> "Slave.Compiz" "Slave.Scaler-0" -> "Slave.Compiz" "Slave.Scaler-1" -> "Slave.Compiz" } subgraph cluster_pipeline_master { style=dashed label="Master Pipeline_A" node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-0"; "Scaler-1"; "Scaler-0/1" } node [bgcolor=grey style=filled] "Layer-0" -> "Scaler-0" "Layer-1" -> "Scaler-0" "Layer-2" -> "Scaler-1" "Layer-3" -> "Scaler-1" "Slave.Compiz" -> "Compiz" "Layer-0" -> "Compiz" "Layer-1" -> "Compiz" "Layer-2" -> "Compiz" "Layer-3" -> "Compiz" "Scaler-0" -> "Compiz" "Scaler-1" -> "Compiz" "Compiz" -> "Scaler-0/1" -> "Wb_layer" "Compiz" -> "Improc" -> "Timing Controller" } "Wb_layer" -> "Memory" "Timing Controller" -> "Monitor" }}hj5sbah}(h]h ]h"]h$]h&]hhuh1jhj2hhubah}(h]h ]h"]h$]h&]jSlave pipeline digraphjDOTuh1jhj/ubj)}(h Slave pipeline enabled data flowh]h Slave pipeline enabled data flow}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj/ubeh}(h]id2ah ]h"]h$]h&]altjIcaptionjMuh1jhjhhhhhNubeh}(h] dual-pipeline-with-slave-enabledah ]h"] dual pipeline with slave enabledah$]h&]uh1hhjZhhhhhKjKubh)}(hhh](h)}(h"Sub-pipelines for input and outputh]h"Sub-pipelines for input and output}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhhhhhKubh)}(hiA complete display pipeline can be easily divided into three sub-pipelines according to the in/out usage.h]hiA complete display pipeline can be easily divided into three sub-pipelines according to the in/out usage.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjjhhubh)}(hhh](h)}(hLayer(input) pipelineh]hLayer(input) pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj)}(hhh](j)}(hhh]j)}(hdigraph layer_data_flow { rankdir=LR; node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-n"; } "Layer-n" -> "Scaler-n" -> "Compiz" }h]hdigraph layer_data_flow { rankdir=LR; node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-n"; } "Layer-n" -> "Scaler-n" -> "Compiz" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jLayer data digraphjDOTuh1jhjubj)}(hLayer (input) data flowh]hLayer (input) data flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id3ah ]h"]h$]h&]altjcaptionjuh1jhjhhhhhNubj)}(hhh](j)}(hhh]j)}(hdigraph layer_data_flow { rankdir=LR; node [shape=box] "Layer-0/1" -> "Scaler-0" -> "Merger" "Layer-2/3" -> "Scaler-1" -> "Merger" "Merger" -> "Compiz" }h]hdigraph layer_data_flow { rankdir=LR; node [shape=box] "Layer-0/1" -> "Scaler-0" -> "Merger" "Layer-2/3" -> "Scaler-1" -> "Merger" "Merger" -> "Compiz" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jLayer Split digraphjDOTuh1jhjubj)}(hLayer Split pipelineh]hLayer Split pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id4ah ]h"]h$]h&]altjcaptionjuh1jhjhhhhhNubeh}(h]layer-input-pipelineah ]h"]layer(input) pipelineah$]h&]uh1hhjjhhhhhKjKubh)}(hhh](h)}(hWriteback(output) pipelineh]hWriteback(output) pipeline}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj)}(hhh](j)}(hhh]j)}(hdigraph writeback_data_flow { rankdir=LR; node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-n"; } "Compiz" -> "Scaler-n" -> "Wb_layer" }h]hdigraph writeback_data_flow { rankdir=LR; node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-n"; } "Compiz" -> "Scaler-n" -> "Wb_layer" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jwriteback digraphjDOTuh1jhjubj)}(hWriteback(output) data flowh]hWriteback(output) data flow}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id5ah ]h"]h$]h&]altj3captionj7uh1jhjhhhhhNubj)}(hhh](j)}(hhh]j)}(hdigraph writeback_data_flow { rankdir=LR; node [shape=box] "Compiz" -> "Splitter" "Splitter" -> "Scaler-0" -> "Merger" "Splitter" -> "Scaler-1" -> "Merger" "Merger" -> "Wb_layer" }h]hdigraph writeback_data_flow { rankdir=LR; node [shape=box] "Compiz" -> "Splitter" "Splitter" -> "Scaler-0" -> "Merger" "Splitter" -> "Scaler-1" -> "Merger" "Merger" -> "Wb_layer" }}hjRsbah}(h]h ]h"]h$]h&]hhuh1jhjOhhubah}(h]h ]h"]h$]h&]jsplit writeback digraphjDOTuh1jhjLubj)}(h!Writeback(output) Split data flowh]h!Writeback(output) Split data flow}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjLubeh}(h]id6ah ]h"]h$]h&]altjfcaptionjjuh1jhjhhhhhNubeh}(h]writeback-output-pipelineah ]h"]writeback(output) pipelineah$]h&]uh1hhjjhhhhhKjKubh)}(hhh](h)}(hDisplay output pipelineh]hDisplay output pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hhh](j)}(hhh]j)}(hidigraph single_ppl { rankdir=LR; node [shape=box] "Compiz" -> "Improc" -> "Timing Controller" }h]hidigraph single_ppl { rankdir=LR; node [shape=box] "Compiz" -> "Improc" -> "Timing Controller" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jdisplay digraphjDOTuh1jhjubj)}(hdisplay output data flowh]hdisplay output data flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id7ah ]h"]h$]h&]altjcaptionjuh1jhjhhhhhNubh)}(htIn the following section we'll see these three sub-pipelines will be handled by KMS-plane/wb_conn/crtc respectively.h]hvIn the following section we’ll see these three sub-pipelines will be handled by KMS-plane/wb_conn/crtc respectively.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjhhubeh}(h]display-output-pipelineah ]h"]display output pipelineah$]h&]uh1hhjjhhhhhMjKubeh}(h]"sub-pipelines-for-input-and-outputah ]h"]"sub-pipelines for input and outputah$]h&]uh1hhjZhhhhhKubeh}(h]possible-d71-pipeline-usageah ]h"]possible d71 pipeline usageah$]h&]uh1hhhhhhhhKMubh)}(hhh](h)}(hKomeda Resource abstractionh]hKomeda Resource abstraction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM+ubh)}(hhh](h)}(h struct komeda_pipeline/componenth]h struct komeda_pipeline/component}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM.ubh)}(hTo fully utilize and easily access/configure the HW, the driver side also uses a similar architecture: Pipeline/Component to describe the HW features and capabilities, and a specific component includes two parts:h]hTo fully utilize and easily access/configure the HW, the driver side also uses a similar architecture: Pipeline/Component to describe the HW features and capabilities, and a specific component includes two parts:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjhhubjz)}(hhh](j)}(hData flow controlling.h]h)}(hj&h]hData flow controlling.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hj$ubah}(h]h ]h"]h$]h&]uh1j~hj!hhhhhNubj)}(h.Specific component capabilities and features. h]h)}(h-Specific component capabilities and features.h]h-Specific component capabilities and features.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj;ubah}(h]h ]h"]h$]h&]uh1j~hj!hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jyhhhM4hjhhubh)}(hSo the driver defines a common header struct komeda_component to describe the data flow control and all specific components are a subclass of this base structure.h]hSo the driver defines a common header struct komeda_component to describe the data flow control and all specific components are a subclass of this base structure.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlekomeda_component (C struct)c.komeda_componenthNtauh1jghjhhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhNubhdesc)}(hhh](hdesc_signature)}(hkomeda_componenth]hdesc_signature_line)}(hstruct komeda_componenth](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hkomeda_componenth]h desc_sig_name)}(hjh]hkomeda_component}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jvah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j~hjhKhj{hhubh desc_content)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj{hhhjhKubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jyhhhjhjxhNubh container)}(hXn**Definition**:: struct komeda_component { struct drm_private_obj obj; struct komeda_pipeline *pipeline; char name[32]; u32 __iomem *reg; u32 id; u32 hw_id; u8 max_active_inputs; u8 max_active_outputs; u32 supported_inputs; u32 supported_outputs; const struct komeda_component_funcs *funcs; }; **Members** ``obj`` treat component as private obj ``pipeline`` the komeda pipeline this component belongs to ``name`` component name ``reg`` component register base, which is initialized by chip and used by chip only ``id`` component id ``hw_id`` component hw id, which is initialized by chip and used by chip only ``max_active_inputs`` **max_active_outputs**: maximum number of inputs/outputs that can be active at the same time Note: the number isn't the bit number of **supported_inputs** or **supported_outputs**, but may be less than it, since component may not support enabling all **supported_inputs**/outputs at the same time. ``max_active_outputs`` maximum number of outputs ``supported_inputs`` **supported_outputs**: bitmask of BIT(component->id) for the supported inputs/outputs, describes the possibilities of how a component is linked into a pipeline. ``supported_outputs`` bitmask of supported output componenet ids ``funcs`` chip functions to access HWh](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKMhjubj)}(hX@struct komeda_component { struct drm_private_obj obj; struct komeda_pipeline *pipeline; char name[32]; u32 __iomem *reg; u32 id; u32 hw_id; u8 max_active_inputs; u8 max_active_outputs; u32 supported_inputs; u32 supported_outputs; const struct komeda_component_funcs *funcs; };h]hX@struct komeda_component { struct drm_private_obj obj; struct komeda_pipeline *pipeline; char name[32]; u32 __iomem *reg; u32 id; u32 hw_id; u8 max_active_inputs; u8 max_active_outputs; u32 supported_inputs; u32 supported_outputs; const struct komeda_component_funcs *funcs; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKOhjubh)}(h **Members**h]j)}(hj.h]hMembers}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhK]hjubhdefinition_list)}(hhh](hdefinition_list_item)}(h'``obj`` treat component as private obj h](hterm)}(h``obj``h]hliteral)}(hjSh]hobj}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjQubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKQhjKubh definition)}(hhh]h)}(htreat component as private objh]htreat component as private obj}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhKQhjmubah}(h]h ]h"]h$]h&]uh1jkhjKubeh}(h]h ]h"]h$]h&]uh1jIhjjhKQhjFubjJ)}(h;``pipeline`` the komeda pipeline this component belongs to h](jP)}(h ``pipeline``h]jV)}(hjh]hpipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKShjubjl)}(hhh]h)}(h-the komeda pipeline this component belongs toh]h-the komeda pipeline this component belongs to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKShjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKShjFubjJ)}(h``name`` component name h](jP)}(h``name``h]jV)}(hjh]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKUhjubjl)}(hhh]h)}(hcomponent nameh]hcomponent name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKUhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKUhjFubjJ)}(hT``reg`` component register base, which is initialized by chip and used by chip only h](jP)}(h``reg``h]jV)}(hjh]hreg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKYhjubjl)}(hhh]h)}(hKcomponent register base, which is initialized by chip and used by chip onlyh]hKcomponent register base, which is initialized by chip and used by chip only}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKXhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKYhjFubjJ)}(h``id`` component id h](jP)}(h``id``h]jV)}(hj<h]hid}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj:ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhK]hj6ubjl)}(hhh]h)}(h component idh]h component id}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhK]hjRubah}(h]h ]h"]h$]h&]uh1jkhj6ubeh}(h]h ]h"]h$]h&]uh1jIhjQhK]hjFubjJ)}(hN``hw_id`` component hw id, which is initialized by chip and used by chip only h](jP)}(h ``hw_id``h]jV)}(hjuh]hhw_id}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjsubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKahjoubjl)}(hhh]h)}(hCcomponent hw id, which is initialized by chip and used by chip onlyh]hCcomponent hw id, which is initialized by chip and used by chip only}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhK`hjubah}(h]h ]h"]h$]h&]uh1jkhjoubeh}(h]h ]h"]h$]h&]uh1jIhjhKahjFubjJ)}(hXA``max_active_inputs`` **max_active_outputs**: maximum number of inputs/outputs that can be active at the same time Note: the number isn't the bit number of **supported_inputs** or **supported_outputs**, but may be less than it, since component may not support enabling all **supported_inputs**/outputs at the same time. h](jP)}(h``max_active_inputs``h]jV)}(hjh]hmax_active_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKlhjubjl)}(hhh](h)}(h**max_active_outputs**:h](j)}(h**max_active_outputs**h]hmax_active_outputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKfhjubh)}(hXmaximum number of inputs/outputs that can be active at the same time Note: the number isn't the bit number of **supported_inputs** or **supported_outputs**, but may be less than it, since component may not support enabling all **supported_inputs**/outputs at the same time.h](hpmaximum number of inputs/outputs that can be active at the same time Note: the number isn’t the bit number of }(hjhhhNhNubj)}(h**supported_inputs**h]hsupported_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh or }(hjhhhNhNubj)}(h**supported_outputs**h]hsupported_outputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhH, but may be less than it, since component may not support enabling all }(hjhhhNhNubj)}(h**supported_inputs**h]hsupported_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh/outputs at the same time.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhhjubeh}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKlhjFubjJ)}(h1``max_active_outputs`` maximum number of outputs h](jP)}(h``max_active_outputs``h]jV)}(hj<h]hmax_active_outputs}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj:ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKphj6ubjl)}(hhh]h)}(hmaximum number of outputsh]hmaximum number of outputs}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhKphjRubah}(h]h ]h"]h$]h&]uh1jkhj6ubeh}(h]h ]h"]h$]h&]uh1jIhjQhKphjFubjJ)}(h``supported_inputs`` **supported_outputs**: bitmask of BIT(component->id) for the supported inputs/outputs, describes the possibilities of how a component is linked into a pipeline. h](jP)}(h``supported_inputs``h]jV)}(hjuh]hsupported_inputs}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjsubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKwhjoubjl)}(hhh](h)}(h**supported_outputs**:h](j)}(h**supported_outputs**h]hsupported_outputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKshjubh)}(hbitmask of BIT(component->id) for the supported inputs/outputs, describes the possibilities of how a component is linked into a pipeline.h]hbitmask of BIT(component->id) for the supported inputs/outputs, describes the possibilities of how a component is linked into a pipeline.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKuhjubeh}(h]h ]h"]h$]h&]uh1jkhjoubeh}(h]h ]h"]h$]h&]uh1jIhjhKwhjFubjJ)}(hA``supported_outputs`` bitmask of supported output componenet ids h](jP)}(h``supported_outputs``h]jV)}(hjh]hsupported_outputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhK{hjubjl)}(hhh]h)}(h*bitmask of supported output componenet idsh]h*bitmask of supported output componenet ids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK{hjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhK{hjFubjJ)}(h%``funcs`` chip functions to access HWh](jP)}(h ``funcs``h]jV)}(hj h]hfuncs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhK~hjubjl)}(hhh]h)}(hchip functions to access HWh]hchip functions to access HW}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhj hK~hjFubeh}(h]h ]h"]h$]h&]uh1jDhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjxhNubh)}(h**Description**h]j)}(hjH h]h Description}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjF ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjhhubh)}(hstruct komeda_component describe the data flow capabilities for how to link a component into the display pipeline. all specified components are subclass of this structure.h]hstruct komeda_component describe the data flow capabilities for how to link a component into the display pipeline. all specified components are subclass of this structure.}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKJhjhhubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jt"komeda_component_output (C struct)c.komeda_component_outputhNtauh1jghjhhhjxhNubjz)}(hhh](j)}(hkomeda_component_outputh]j)}(hstruct komeda_component_outputh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKQubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKQubj)}(hkomeda_component_outputh]j)}(hj h]hkomeda_component_output}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hKQubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj~ hhhj hKQubah}(h]jy ah ](jjeh"]h$]h&]jj)jhuh1j~hj hKQhj{ hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj{ hhhj hKQubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1jyhhhjhjxhNubj)}(hX4**Definition**:: struct komeda_component_output { struct komeda_component *component; u8 output_port; }; **Members** ``component`` indicate which component the data comes from ``output_port`` the output port of the :c:type:`komeda_component_output.component `h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubj)}(h_struct komeda_component_output { struct komeda_component *component; u8 output_port; };h]h_struct komeda_component_output { struct komeda_component *component; u8 output_port; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjE)}(hhh](jJ)}(h;``component`` indicate which component the data comes from h](jP)}(h ``component``h]jV)}(hj& h]h component}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj$ ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjl)}(hhh]h)}(h,indicate which component the data comes fromh]h,indicate which component the data comes from}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj; hKhj< ubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhj; hKhj ubjJ)}(hl``output_port`` the output port of the :c:type:`komeda_component_output.component `h](jP)}(h``output_port``h]jV)}(hj_ h]h output_port}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj] ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjY ubjl)}(hhh]h)}(h\the output port of the :c:type:`komeda_component_output.component `h](hthe output port of the }(hjx hhhNhNubh)}(hE:c:type:`komeda_component_output.component `h]jV)}(hj h]h!komeda_component_output.component}(hj hhhNhNubah}(h]h ](xrefjc-typeeh"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]refdocgpu/komeda-kms refdomainjreftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sb reftargetkomeda_component_outputuh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjx ubeh}(h]h ]h"]h$]h&]uh1hhj hKhju ubah}(h]h ]h"]h$]h&]uh1jkhjY ubeh}(h]h ]h"]h$]h&]uh1jIhjt hKhj ubeh}(h]h ]h"]h$]h&]uh1jDhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjxhNubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjhhubh)}(ha component has multiple outputs, if want to know where the data comes from, only know the component is not enough, we still need to know its output porth]ha component has multiple outputs, if want to know where the data comes from, only know the component is not enough, we still need to know its output port}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjhhubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jt!komeda_component_state (C struct)c.komeda_component_statehNtauh1jghjhhhjxhNubjz)}(hhh](j)}(hkomeda_component_stateh]j)}(hstruct komeda_component_stateh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hkomeda_component_stateh]j)}(hj h]hkomeda_component_state}(hj* hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj& ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j~hj hKhj hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjjU jjU jjjuh1jyhhhjhjxhNubj)}(hX**Definition**:: struct komeda_component_state { struct drm_private_state obj; struct komeda_component *component; union { struct drm_crtc *crtc; struct drm_plane *plane; struct drm_connector *wb_conn; void *binding_user; }; u16 active_inputs; u16 changed_active_inputs; u16 affected_inputs; struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS]; }; **Members** ``obj`` tracking component_state by drm_atomic_commit ``component`` backpointer to the component ``{unnamed_union}`` anonymous ``crtc`` backpointer for user crtc ``plane`` backpointer for user plane ``wb_conn`` backpointer for user wb_connector ``binding_user`` currently bound user, the user can be **crtc**, **plane** or **wb_conn**, which is valid decided by **component** and **inputs** - Layer: its user always is plane. - compiz/improc/timing_ctrlr: the user is crtc. - wb_layer: wb_conn; - scaler: plane when input is layer, wb_conn if input is compiz. ``active_inputs`` active_inputs is bitmask of **inputs** index - active_inputs = changed_active_inputs | unchanged_active_inputs - affected_inputs = old->active_inputs | new->active_inputs; - disabling_inputs = affected_inputs ^ active_inputs; - changed_inputs = disabling_inputs | changed_active_inputs; NOTE: changed_inputs doesn't include all active_input but only **changed_active_inputs**, and this bitmask can be used in chip level for dirty update. ``changed_active_inputs`` bitmask of the changed **active_inputs** ``affected_inputs`` bitmask for affected **inputs** ``inputs`` the specific inputs[i] only valid on BIT(i) has been set in **active_inputs**, if not the inputs[i] is undefined.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj] ubh:}(hj] hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjY ubj)}(hXstruct komeda_component_state { struct drm_private_state obj; struct komeda_component *component; union { struct drm_crtc *crtc; struct drm_plane *plane; struct drm_connector *wb_conn; void *binding_user; }; u16 active_inputs; u16 changed_active_inputs; u16 affected_inputs; struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS]; };h]hXstruct komeda_component_state { struct drm_private_state obj; struct komeda_component *component; union { struct drm_crtc *crtc; struct drm_plane *plane; struct drm_connector *wb_conn; void *binding_user; }; u16 active_inputs; u16 changed_active_inputs; u16 affected_inputs; struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS]; };}hjz sbah}(h]h ]h"]h$]h&]hhuh1jht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjY ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjY ubjE)}(hhh](jJ)}(h6``obj`` tracking component_state by drm_atomic_commit h](jP)}(h``obj``h]jV)}(hj h]hobj}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjl)}(hhh]h)}(h-tracking component_state by drm_atomic_commith]h-tracking component_state by drm_atomic_commit}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhj hKhj ubjJ)}(h+``component`` backpointer to the component h](jP)}(h ``component``h]jV)}(hj h]h component}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjl)}(hhh]h)}(hbackpointer to the componenth]hbackpointer to the component}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhj hKhj ubjJ)}(h``{unnamed_union}`` anonymous h](jP)}(h``{unnamed_union}``h]jV)}(hj h]h{unnamed_union}}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjl)}(hhh]h)}(h anonymoush]h anonymous}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1 hKhj2 ubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhj1 hKhj ubjJ)}(h#``crtc`` backpointer for user crtc h](jP)}(h``crtc``h]jV)}(hjU h]hcrtc}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjS ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjO ubjl)}(hhh]h)}(hbackpointer for user crtch]hbackpointer for user crtc}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj hKhjk ubah}(h]h ]h"]h$]h&]uh1jkhjO ubeh}(h]h ]h"]h$]h&]uh1jIhjj hKhj ubjJ)}(h%``plane`` backpointer for user plane h](jP)}(h ``plane``h]jV)}(hj h]hplane}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjl)}(hhh]h)}(hbackpointer for user planeh]hbackpointer for user plane}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhj hKhj ubjJ)}(h.``wb_conn`` backpointer for user wb_connector h](jP)}(h ``wb_conn``h]jV)}(hj h]hwb_conn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjl)}(hhh]h)}(h!backpointer for user wb_connectorh]h!backpointer for user wb_connector}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhj hKhj ubjJ)}(hX@``binding_user`` currently bound user, the user can be **crtc**, **plane** or **wb_conn**, which is valid decided by **component** and **inputs** - Layer: its user always is plane. - compiz/improc/timing_ctrlr: the user is crtc. - wb_layer: wb_conn; - scaler: plane when input is layer, wb_conn if input is compiz. h](jP)}(h``binding_user``h]jV)}(hj h]h binding_user}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjl)}(hhh](h)}(hcurrently bound user, the user can be **crtc**, **plane** or **wb_conn**, which is valid decided by **component** and **inputs**h](h¤tly bound user, the user can be }(hj hhhNhNubj)}(h**crtc**h]hcrtc}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }(hj hhhNhNubj)}(h **plane**h]hplane}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh or }(hj hhhNhNubj)}(h **wb_conn**h]hwb_conn}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, which is valid decided by }(hj hhhNhNubj)}(h **component**h]h component}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh and }(hj hhhNhNubj)}(h **inputs**h]hinputs}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjz)}(hhh](j)}(h Layer: its user always is plane.h]h)}(hj h]h Layer: its user always is plane.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubah}(h]h ]h"]h$]h&]uh1j~hj~ ubj)}(h-compiz/improc/timing_ctrlr: the user is crtc.h]h)}(hj h]h-compiz/improc/timing_ctrlr: the user is crtc.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubah}(h]h ]h"]h$]h&]uh1j~hj~ ubj)}(hwb_layer: wb_conn;h]h)}(hj h]hwb_layer: wb_conn;}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubah}(h]h ]h"]h$]h&]uh1j~hj~ ubj)}(h?scaler: plane when input is layer, wb_conn if input is compiz. h]h)}(h>scaler: plane when input is layer, wb_conn if input is compiz.h]h>scaler: plane when input is layer, wb_conn if input is compiz.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j~hj~ ubeh}(h]h ]h"]h$]h&]jjuh1jyhj hKhj ubeh}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhj hKhj ubjJ)}(hX``active_inputs`` active_inputs is bitmask of **inputs** index - active_inputs = changed_active_inputs | unchanged_active_inputs - affected_inputs = old->active_inputs | new->active_inputs; - disabling_inputs = affected_inputs ^ active_inputs; - changed_inputs = disabling_inputs | changed_active_inputs; NOTE: changed_inputs doesn't include all active_input but only **changed_active_inputs**, and this bitmask can be used in chip level for dirty update. h](jP)}(h``active_inputs``h]jV)}(hj h]h active_inputs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjl)}(hhh](h)}(h,active_inputs is bitmask of **inputs** indexh](hactive_inputs is bitmask of }(hjhhhNhNubj)}(h **inputs**h]hinputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh index}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjz)}(hhh](j)}(h?active_inputs = changed_active_inputs | unchanged_active_inputsh]h)}(hj8h]h?active_inputs = changed_active_inputs | unchanged_active_inputs}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj6ubah}(h]h ]h"]h$]h&]uh1j~hj3ubj)}(h:affected_inputs = old->active_inputs | new->active_inputs;h]h)}(hjPh]h:affected_inputs = old->active_inputs | new->active_inputs;}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjNubah}(h]h ]h"]h$]h&]uh1j~hj3ubj)}(h3disabling_inputs = affected_inputs ^ active_inputs;h]h)}(hjhh]h3disabling_inputs = affected_inputs ^ active_inputs;}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjfubah}(h]h ]h"]h$]h&]uh1j~hj3ubj)}(h;changed_inputs = disabling_inputs | changed_active_inputs; h]h)}(h:changed_inputs = disabling_inputs | changed_active_inputs;h]h:changed_inputs = disabling_inputs | changed_active_inputs;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj~ubah}(h]h ]h"]h$]h&]uh1j~hj3ubeh}(h]h ]h"]h$]h&]jjuh1jyhjGhKhjubh)}(hNOTE: changed_inputs doesn't include all active_input but only **changed_active_inputs**, and this bitmask can be used in chip level for dirty update.h](hANOTE: changed_inputs doesn’t include all active_input but only }(hjhhhNhNubj)}(h**changed_active_inputs**h]hchanged_active_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh>, and this bitmask can be used in chip level for dirty update.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubeh}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhjhKhj ubjJ)}(hC``changed_active_inputs`` bitmask of the changed **active_inputs** h](jP)}(h``changed_active_inputs``h]jV)}(hjh]hchanged_active_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjl)}(hhh]h)}(h(bitmask of the changed **active_inputs**h](hbitmask of the changed }(hjhhhNhNubj)}(h**active_inputs**h]h active_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKhj ubjJ)}(h4``affected_inputs`` bitmask for affected **inputs** h](jP)}(h``affected_inputs``h]jV)}(hjh]haffected_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjl)}(hhh]h)}(hbitmask for affected **inputs**h](hbitmask for affected }(hj0hhhNhNubj)}(h **inputs**h]hinputs}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1hhj,hKhj-ubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhj,hKhj ubjJ)}(h|``inputs`` the specific inputs[i] only valid on BIT(i) has been set in **active_inputs**, if not the inputs[i] is undefined.h](jP)}(h ``inputs``h]jV)}(hj^h]hinputs}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj\ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjXubjl)}(hhh]h)}(hqthe specific inputs[i] only valid on BIT(i) has been set in **active_inputs**, if not the inputs[i] is undefined.h](hubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhj:ubjl)}(hhh]h)}(h2for split the compiz output to two half data flowsh]h2for split the compiz output to two half data flows}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjVubah}(h]h ]h"]h$]h&]uh1jkhj:ubeh}(h]h ]h"]h$]h&]uh1jIhjUhMhjubjJ)}(h``merger`` merger h](jP)}(h ``merger``h]jV)}(hjyh]hmerger}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjwubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjsubjl)}(hhh]h)}(hmergerh]hmerger}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jkhjsubeh}(h]h ]h"]h$]h&]uh1jIhjhMhjubjJ)}(h``wb_layer`` writeback layer h](jP)}(h ``wb_layer``h]jV)}(hjh]hwb_layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(hwriteback layerh]hwriteback layer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhMhjubjJ)}(h ``improc`` post image processor h](jP)}(h ``improc``h]jV)}(hjh]himproc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(hpost image processorh]hpost image processor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhMhjubjJ)}(h``ctrlr`` timing controller h](jP)}(h ``ctrlr``h]jV)}(hj$h]hctrlr}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj"ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(htiming controllerh]htiming controller}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj:ubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhj9hMhjubjJ)}(h*``funcs`` chip private pipeline functions h](jP)}(h ``funcs``h]jV)}(hj]h]hfuncs}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj[ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjWubjl)}(hhh]h)}(hchip private pipeline functionsh]hchip private pipeline functions}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjsubah}(h]h ]h"]h$]h&]uh1jkhjWubeh}(h]h ]h"]h$]h&]uh1jIhjrhMhjubjJ)}(h``of_node`` pipeline dt node h](jP)}(h ``of_node``h]jV)}(hjh]hof_node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(hpipeline dt nodeh]hpipeline dt node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhMhjubjJ)}(h(``of_output_port`` pipeline output port h](jP)}(h``of_output_port``h]jV)}(hjh]hof_output_port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(hpipeline output porth]hpipeline output port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhMhjubjJ)}(h2``of_output_links`` output connector device nodes h](jP)}(h``of_output_links``h]jV)}(hjh]hof_output_links}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(houtput connector device nodesh]houtput connector device nodes}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhMhjubjJ)}(h?``dual_link`` true if of_output_links[0] and [1] are both validh](jP)}(h ``dual_link``h]jV)}(hjAh]h dual_link}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj?ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhj;ubjl)}(hhh]h)}(h1true if of_output_links[0] and [1] are both validh]h1true if of_output_links[0] and [1] are both valid}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjWubah}(h]h ]h"]h$]h&]uh1jkhj;ubeh}(h]h ]h"]h$]h&]uh1jIhjVhMhjubeh}(h]h ]h"]h$]h&]uh1jDhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjxhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjhhubh)}(hIRepresent a complete display pipeline and hold all functional components.h]hIRepresent a complete display pipeline and hold all functional components.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjhhubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jt komeda_pipeline_state (C struct)c.komeda_pipeline_statehNtauh1jghjhhhjxhNubjz)}(hhh](j)}(hkomeda_pipeline_stateh]j)}(hstruct komeda_pipeline_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hkomeda_pipeline_stateh]j)}(hjh]hkomeda_pipeline_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j~hjhMhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1jyhhhjhjxhNubj)}(hX**Definition**:: struct komeda_pipeline_state { struct drm_private_state obj; struct komeda_pipeline *pipe; struct drm_crtc *crtc; u32 active_comps; }; **Members** ``obj`` tracking pipeline_state by drm_atomic_commit ``pipe`` backpointer to the pipeline ``crtc`` currently bound crtc ``active_comps`` bitmask - BIT(component->id) of active componentsh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubj)}(hstruct komeda_pipeline_state { struct drm_private_state obj; struct komeda_pipeline *pipe; struct drm_crtc *crtc; u32 active_comps; };h]hstruct komeda_pipeline_state { struct drm_private_state obj; struct komeda_pipeline *pipe; struct drm_crtc *crtc; u32 active_comps; };}hj2sbah}(h]h ]h"]h$]h&]hhuh1jht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubh)}(h **Members**h]j)}(hjCh]hMembers}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjE)}(hhh](jJ)}(h5``obj`` tracking pipeline_state by drm_atomic_commit h](jP)}(h``obj``h]jV)}(hjbh]hobj}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj`ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhj\ubjl)}(hhh]h)}(h,tracking pipeline_state by drm_atomic_commith]h,tracking pipeline_state by drm_atomic_commit}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMhjxubah}(h]h ]h"]h$]h&]uh1jkhj\ubeh}(h]h ]h"]h$]h&]uh1jIhjwhMhjYubjJ)}(h%``pipe`` backpointer to the pipeline h](jP)}(h``pipe``h]jV)}(hjh]hpipe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(hbackpointer to the pipelineh]hbackpointer to the pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhMhjYubjJ)}(h``crtc`` currently bound crtc h](jP)}(h``crtc``h]jV)}(hjh]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(hcurrently bound crtch]hcurrently bound crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhMhjYubjJ)}(hB``active_comps`` bitmask - BIT(component->id) of active componentsh](jP)}(h``active_comps``h]jV)}(hj h]h active_comps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjl)}(hhh]h)}(h1bitmask - BIT(component->id) of active componentsh]h1bitmask - BIT(component->id) of active components}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhj#ubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhj"hMhjYubeh}(h]h ]h"]h$]h&]uh1jDhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjxhNubh)}(h**NOTE**h]j)}(hjPh]hNOTE}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjhhubh)}(hUnlike the pipeline, pipeline_state doesn’t gather any component_state into it. It because all component will be managed by drm_atomic_commit.h]hUnlike the pipeline, pipeline_state doesn’t gather any component_state into it. It because all component will be managed by drm_atomic_commit.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjhhubeh}(h] struct-komeda-pipeline-componentah ]h"] struct komeda_pipeline/componentah$]h&]uh1hhjhhhhhM.ubeh}(h]komeda-resource-abstractionah ]h"]komeda resource abstractionah$]h&]uh1hhhhhhhhM+ubh)}(hhh](h)}(h%Resource discovery and initializationh]h%Resource discovery and initialization}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM?ubh)}(hPipeline and component are used to describe how to handle the pixel data. We still need a @struct komeda_dev to describe the whole view of the device, and the control-abilites of device.h]hPipeline and component are used to describe how to handle the pixel data. We still need a @struct komeda_dev to describe the whole view of the device, and the control-abilites of device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjhhubh)}(hX8We have &komeda_dev, &komeda_pipeline, &komeda_component. Now fill devices with pipelines. Since komeda is not for D71 only but also intended for later products, of course we’d better share as much as possible between different products. To achieve this, split the komeda device into two layers: CORE and CHIP.h]hX8We have &komeda_dev, &komeda_pipeline, &komeda_component. Now fill devices with pipelines. Since komeda is not for D71 only but also intended for later products, of course we’d better share as much as possible between different products. To achieve this, split the komeda device into two layers: CORE and CHIP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjhhubjz)}(hhh](j)}(h4CORE: for common features and capabilities handling.h]h)}(hjh]h4CORE: for common features and capabilities handling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1j~hjhhhhhNubj)}(hNCHIP: for register programming and HW specific feature (limitation) handling. h]h)}(hMCHIP: for register programming and HW specific feature (limitation) handling.h]hMCHIP: for register programming and HW specific feature (limitation) handling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjubah}(h]h ]h"]h$]h&]uh1j~hjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jyhhhMJhjhhubh)}(h7CORE can access CHIP by three chip function structures:h]h7CORE can access CHIP by three chip function structures:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjhhubjz)}(hhh](j)}(hstruct komeda_dev_funcsh]h)}(hjh]hstruct komeda_dev_funcs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhjubah}(h]h ]h"]h$]h&]uh1j~hjhhhhhNubj)}(hstruct komeda_pipeline_funcsh]h)}(hjh]hstruct komeda_pipeline_funcs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjubah}(h]h ]h"]h$]h&]uh1j~hjhhhhhNubj)}(hstruct komeda_component_funcs h]h)}(hstruct komeda_component_funcsh]hstruct komeda_component_funcs}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhj)ubah}(h]h ]h"]h$]h&]uh1j~hjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jyhhhMOhjhhubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jtkomeda_dev_funcs (C struct)c.komeda_dev_funcshNtauh1jghjhhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhNubjz)}(hhh](j)}(hkomeda_dev_funcsh]j)}(hstruct komeda_dev_funcsh](j)}(hjh]hstruct}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKubj)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhjnhKubj)}(hkomeda_dev_funcsh]j)}(hj[h]hkomeda_dev_funcs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]hhhjnhKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjYhhhjnhKubah}(h]jSah ](jjeh"]h$]h&]jj)jhuh1j~hjnhKhjVhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjVhhhjnhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jyhhhjhjUhNubj)}(hXn**Definition**:: struct komeda_dev_funcs { void (*init_format_table)(struct komeda_dev *mdev); int (*enum_resources)(struct komeda_dev *mdev); void (*cleanup)(struct komeda_dev *mdev); int (*connect_iommu)(struct komeda_dev *mdev); int (*disconnect_iommu)(struct komeda_dev *mdev); irqreturn_t (*irq_handler)(struct komeda_dev *mdev, struct komeda_events *events); int (*enable_irq)(struct komeda_dev *mdev); int (*disable_irq)(struct komeda_dev *mdev); void (*on_off_vblank)(struct komeda_dev *mdev, int master_pipe, bool on); void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); int (*change_opmode)(struct komeda_dev *mdev, int new_mode); void (*flush)(struct komeda_dev *mdev, int master_pipe, u32 active_pipes); }; **Members** ``init_format_table`` initialize :c:type:`komeda_dev->format_table `, this function should be called before the :c:type:`enum_resource <_resource>` ``enum_resources`` for CHIP to report or add pipeline and component resources to CORE ``cleanup`` call to chip to cleanup komeda_dev->chip data ``connect_iommu`` Optional, connect to external iommu ``disconnect_iommu`` Optional, disconnect to external iommu ``irq_handler`` for CORE to get the HW event from the CHIP when interrupt happened. ``enable_irq`` enable irq ``disable_irq`` disable irq ``on_off_vblank`` notify HW to on/off vblank ``dump_register`` Optional, dump registers to seq_file ``change_opmode`` Notify HW to switch to a new display operation mode. ``flush`` Notify the HW to flush or kickoff the updateh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKYhjubj)}(hXstruct komeda_dev_funcs { void (*init_format_table)(struct komeda_dev *mdev); int (*enum_resources)(struct komeda_dev *mdev); void (*cleanup)(struct komeda_dev *mdev); int (*connect_iommu)(struct komeda_dev *mdev); int (*disconnect_iommu)(struct komeda_dev *mdev); irqreturn_t (*irq_handler)(struct komeda_dev *mdev, struct komeda_events *events); int (*enable_irq)(struct komeda_dev *mdev); int (*disable_irq)(struct komeda_dev *mdev); void (*on_off_vblank)(struct komeda_dev *mdev, int master_pipe, bool on); void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); int (*change_opmode)(struct komeda_dev *mdev, int new_mode); void (*flush)(struct komeda_dev *mdev, int master_pipe, u32 active_pipes); };h]hXstruct komeda_dev_funcs { void (*init_format_table)(struct komeda_dev *mdev); int (*enum_resources)(struct komeda_dev *mdev); void (*cleanup)(struct komeda_dev *mdev); int (*connect_iommu)(struct komeda_dev *mdev); int (*disconnect_iommu)(struct komeda_dev *mdev); irqreturn_t (*irq_handler)(struct komeda_dev *mdev, struct komeda_events *events); int (*enable_irq)(struct komeda_dev *mdev); int (*disable_irq)(struct komeda_dev *mdev); void (*on_off_vblank)(struct komeda_dev *mdev, int master_pipe, bool on); void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); int (*change_opmode)(struct komeda_dev *mdev, int new_mode); void (*flush)(struct komeda_dev *mdev, int master_pipe, u32 active_pipes); };}hjsbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhK[hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKjhjubjE)}(hhh](jJ)}(h``init_format_table`` initialize :c:type:`komeda_dev->format_table `, this function should be called before the :c:type:`enum_resource <_resource>` h](jP)}(h``init_format_table``h]jV)}(hjh]hinit_format_table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhK]hjubjl)}(hhh]h)}(hinitialize :c:type:`komeda_dev->format_table `, this function should be called before the :c:type:`enum_resource <_resource>`h](h initialize }(hjhhhNhNubh)}(h/:c:type:`komeda_dev->format_table `h]jV)}(hj$h]hkomeda_dev->format_table}(hj&hhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhj"ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_devuh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhK\hjubh,, this function should be called before the }(hjhhhNhNubh)}(h#:c:type:`enum_resource <_resource>`h]jV)}(hjHh]h enum_resource}(hjJhhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhjFubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j _resourceuh1hhjAhK\hjubeh}(h]h ]h"]h$]h&]uh1hhjAhK\hjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhK]hjubjJ)}(hV``enum_resources`` for CHIP to report or add pipeline and component resources to CORE h](jP)}(h``enum_resources``h]jV)}(hj}h]henum_resources}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj{ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKchjwubjl)}(hhh]h)}(hBfor CHIP to report or add pipeline and component resources to COREh]hBfor CHIP to report or add pipeline and component resources to CORE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKchjubah}(h]h ]h"]h$]h&]uh1jkhjwubeh}(h]h ]h"]h$]h&]uh1jIhjhKchjubjJ)}(h:``cleanup`` call to chip to cleanup komeda_dev->chip data h](jP)}(h ``cleanup``h]jV)}(hjh]hcleanup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhhjubjl)}(hhh]h)}(h-call to chip to cleanup komeda_dev->chip datah]h-call to chip to cleanup komeda_dev->chip data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKhhjubjJ)}(h6``connect_iommu`` Optional, connect to external iommu h](jP)}(h``connect_iommu``h]jV)}(hjh]h connect_iommu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKjhjubjl)}(hhh]h)}(h#Optional, connect to external iommuh]h#Optional, connect to external iommu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKjhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKjhjubjJ)}(h<``disconnect_iommu`` Optional, disconnect to external iommu h](jP)}(h``disconnect_iommu``h]jV)}(hj(h]hdisconnect_iommu}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj&ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKlhj"ubjl)}(hhh]h)}(h&Optional, disconnect to external iommuh]h&Optional, disconnect to external iommu}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKlhj>ubah}(h]h ]h"]h$]h&]uh1jkhj"ubeh}(h]h ]h"]h$]h&]uh1jIhj=hKlhjubjJ)}(hT``irq_handler`` for CORE to get the HW event from the CHIP when interrupt happened. h](jP)}(h``irq_handler``h]jV)}(hjah]h irq_handler}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj_ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKohj[ubjl)}(hhh]h)}(hCfor CORE to get the HW event from the CHIP when interrupt happened.h]hCfor CORE to get the HW event from the CHIP when interrupt happened.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhKohjwubah}(h]h ]h"]h$]h&]uh1jkhj[ubeh}(h]h ]h"]h$]h&]uh1jIhjvhKohjubjJ)}(h``enable_irq`` enable irq h](jP)}(h``enable_irq``h]jV)}(hjh]h enable_irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKuhjubjl)}(hhh]h)}(h enable irqh]h enable irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKuhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKuhjubjJ)}(h``disable_irq`` disable irq h](jP)}(h``disable_irq``h]jV)}(hjh]h disable_irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKwhjubjl)}(hhh]h)}(h disable irqh]h disable irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKwhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKwhjubjJ)}(h-``on_off_vblank`` notify HW to on/off vblank h](jP)}(h``on_off_vblank``h]jV)}(hj h]h on_off_vblank}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKyhjubjl)}(hhh]h)}(hnotify HW to on/off vblankh]hnotify HW to on/off vblank}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hKyhj"ubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhj!hKyhjubjJ)}(h7``dump_register`` Optional, dump registers to seq_file h](jP)}(h``dump_register``h]jV)}(hjEh]h dump_register}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjCubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhK}hj?ubjl)}(hhh]h)}(h$Optional, dump registers to seq_fileh]h$Optional, dump registers to seq_file}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhK}hj[ubah}(h]h ]h"]h$]h&]uh1jkhj?ubeh}(h]h ]h"]h$]h&]uh1jIhjZhK}hjubjJ)}(hG``change_opmode`` Notify HW to switch to a new display operation mode. h](jP)}(h``change_opmode``h]jV)}(hj~h]h change_opmode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj|ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjxubjl)}(hhh]h)}(h4Notify HW to switch to a new display operation mode.h]h4Notify HW to switch to a new display operation mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhjxubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubjJ)}(h6``flush`` Notify the HW to flush or kickoff the updateh](jP)}(h ``flush``h]jV)}(hjh]hflush}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjl)}(hhh]h)}(h,Notify the HW to flush or kickoff the updateh]h,Notify the HW to flush or kickoff the update}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubeh}(h]h ]h"]h$]h&]uh1jDhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjUhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjhhubh)}(hLSupplied by chip level and returned by the chip entry function xxx_identify,h]hLSupplied by chip level and returned by the chip entry function xxx_identify,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKVhjhhubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jtkomeda_dev (C struct) c.komeda_devhNtauh1jghjhhhjUhNubjz)}(hhh](j)}(h komeda_devh]j)}(hstruct komeda_devh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhK[ubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhjEhK[ubj)}(h komeda_devh]j)}(hj2h]h komeda_dev}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ](jjeh"]h$]h&]hhuh1jhj4hhhjEhK[ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj0hhhjEhK[ubah}(h]j+ah ](jjeh"]h$]h&]jj)jhuh1j~hjEhK[hj-hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj-hhhjEhK[ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jyhhhjhjUhNubj)}(hX**Definition**:: struct komeda_dev { struct device *dev; u32 __iomem *reg_base; struct komeda_chip_info chip; struct komeda_format_caps_table fmt_tbl; struct clk *aclk; int irq; struct mutex lock; u32 dpmode; int n_pipelines; struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES]; const struct komeda_dev_funcs *funcs; void *chip_data; struct iommu_domain *iommu; struct dentry *debugfs_root; u16 err_verbosity; #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0); #define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1); #define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2); #define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8); #define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12); }; **Members** ``dev`` the base device structure ``reg_base`` the base address of komeda io space ``chip`` the basic chip information ``fmt_tbl`` initialized by :c:type:`komeda_dev_funcs->init_format_table ` ``aclk`` HW main engine clk ``irq`` irq number ``lock`` used to protect dpmode ``dpmode`` current display mode ``n_pipelines`` the number of pipe in **pipelines** ``pipelines`` the komeda pipelines ``funcs`` chip funcs to access to HW ``chip_data`` chip data will be added by :c:type:`komeda_dev_funcs.enum_resources\(\) ` and destroyed by :c:type:`komeda_dev_funcs.cleanup\(\) ` ``iommu`` iommu domain ``debugfs_root`` root directory of komeda debugfs ``err_verbosity`` bitmask for how much extra info to print on error See KOMEDA_DEV_* macros for details. Low byte contains the debug level categories, the high byte contains extra debug options.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubj)}(hXstruct komeda_dev { struct device *dev; u32 __iomem *reg_base; struct komeda_chip_info chip; struct komeda_format_caps_table fmt_tbl; struct clk *aclk; int irq; struct mutex lock; u32 dpmode; int n_pipelines; struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES]; const struct komeda_dev_funcs *funcs; void *chip_data; struct iommu_domain *iommu; struct dentry *debugfs_root; u16 err_verbosity; #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0); #define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1); #define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2); #define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8); #define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12); };h]hXstruct komeda_dev { struct device *dev; u32 __iomem *reg_base; struct komeda_chip_info chip; struct komeda_format_caps_table fmt_tbl; struct clk *aclk; int irq; struct mutex lock; u32 dpmode; int n_pipelines; struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES]; const struct komeda_dev_funcs *funcs; void *chip_data; struct iommu_domain *iommu; struct dentry *debugfs_root; u16 err_verbosity; #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0); #define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1); #define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2); #define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8); #define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12); };}hjsbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjE)}(hhh](jJ)}(h"``dev`` the base device structure h](jP)}(h``dev``h]jV)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjl)}(hhh]h)}(hthe base device structureh]hthe base device structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubjJ)}(h1``reg_base`` the base address of komeda io space h](jP)}(h ``reg_base``h]jV)}(hjh]hreg_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj ubjl)}(hhh]h)}(h#the base address of komeda io spaceh]h#the base address of komeda io space}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKhj'ubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1jIhj&hKhjubjJ)}(h$``chip`` the basic chip information h](jP)}(h``chip``h]jV)}(hjJh]hchip}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjHubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjDubjl)}(hhh]h)}(hthe basic chip informationh]hthe basic chip information}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj`ubah}(h]h ]h"]h$]h&]uh1jkhjDubeh}(h]h ]h"]h$]h&]uh1jIhj_hKhjubjJ)}(h\``fmt_tbl`` initialized by :c:type:`komeda_dev_funcs->init_format_table ` h](jP)}(h ``fmt_tbl``h]jV)}(hjh]hfmt_tbl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj}ubjl)}(hhh]h)}(hOinitialized by :c:type:`komeda_dev_funcs->init_format_table `h](hinitialized by }(hjhhhNhNubh)}(h@:c:type:`komeda_dev_funcs->init_format_table `h]jV)}(hjh]h#komeda_dev_funcs->init_format_table}(hjhhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_dev_funcsuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhj}ubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubjJ)}(h``aclk`` HW main engine clk h](jP)}(h``aclk``h]jV)}(hjh]haclk}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjl)}(hhh]h)}(hHW main engine clkh]hHW main engine clk}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubjJ)}(h``irq`` irq number h](jP)}(h``irq``h]jV)}(hjh]hirq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjl)}(hhh]h)}(h irq numberh]h irq number}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKhj*ubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhj)hKhjubjJ)}(h ``lock`` used to protect dpmode h](jP)}(h``lock``h]jV)}(hjMh]hlock}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjKubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjGubjl)}(hhh]h)}(hused to protect dpmodeh]hused to protect dpmode}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhKhjcubah}(h]h ]h"]h$]h&]uh1jkhjGubeh}(h]h ]h"]h$]h&]uh1jIhjbhKhjubjJ)}(h ``dpmode`` current display mode h](jP)}(h ``dpmode``h]jV)}(hjh]hdpmode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjl)}(hhh]h)}(hcurrent display modeh]hcurrent display mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubjJ)}(h4``n_pipelines`` the number of pipe in **pipelines** h](jP)}(h``n_pipelines``h]jV)}(hjh]h n_pipelines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjl)}(hhh]h)}(h#the number of pipe in **pipelines**h](hthe number of pipe in }(hjhhhNhNubj)}(h **pipelines**h]h pipelines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubjJ)}(h#``pipelines`` the komeda pipelines h](jP)}(h ``pipelines``h]jV)}(hjh]h pipelines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjl)}(hhh]h)}(hthe komeda pipelinesh]hthe komeda pipelines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubjJ)}(h%``funcs`` chip funcs to access to HW h](jP)}(h ``funcs``h]jV)}(hj?h]hfuncs}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj=ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj9ubjl)}(hhh]h)}(hchip funcs to access to HWh]hchip funcs to access to HW}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThKhjUubah}(h]h ]h"]h$]h&]uh1jkhj9ubeh}(h]h ]h"]h$]h&]uh1jIhjThKhjubjJ)}(h``chip_data`` chip data will be added by :c:type:`komeda_dev_funcs.enum_resources\(\) ` and destroyed by :c:type:`komeda_dev_funcs.cleanup\(\) ` h](jP)}(h ``chip_data``h]jV)}(hjxh]h chip_data}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjvubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjrubjl)}(hhh]h)}(hchip data will be added by :c:type:`komeda_dev_funcs.enum_resources\(\) ` and destroyed by :c:type:`komeda_dev_funcs.cleanup\(\) `h](hchip data will be added by }(hjhhhNhNubh)}(h@:c:type:`komeda_dev_funcs.enum_resources\(\) `h]jV)}(hjh]h!komeda_dev_funcs.enum_resources()}(hjhhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_dev_funcsuh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubh and destroyed by }(hjhhhNhNubh)}(h9:c:type:`komeda_dev_funcs.cleanup\(\) `h]jV)}(hjh]hkomeda_dev_funcs.cleanup()}(hjhhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_dev_funcsuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jkhjrubeh}(h]h ]h"]h$]h&]uh1jIhjhKhjubjJ)}(h``iommu`` iommu domain h](jP)}(h ``iommu``h]jV)}(hjh]hiommu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjl)}(hhh]h)}(h iommu domainh]h iommu domain}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1jIhj hKhjubjJ)}(h2``debugfs_root`` root directory of komeda debugfs h](jP)}(h``debugfs_root``h]jV)}(hj- h]h debugfs_root}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj+ ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj' ubjl)}(hhh]h)}(h root directory of komeda debugfsh]h root directory of komeda debugfs}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB hKhjC ubah}(h]h ]h"]h$]h&]uh1jkhj' ubeh}(h]h ]h"]h$]h&]uh1jIhjB hKhjubjJ)}(h``err_verbosity`` bitmask for how much extra info to print on error See KOMEDA_DEV_* macros for details. Low byte contains the debug level categories, the high byte contains extra debug options.h](jP)}(h``err_verbosity``h]jV)}(hjf h]h err_verbosity}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjd ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj` ubjl)}(hhh](h)}(h1bitmask for how much extra info to print on errorh]h1bitmask for how much extra info to print on error}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj| ubh)}(h~See KOMEDA_DEV_* macros for details. Low byte contains the debug level categories, the high byte contains extra debug options.h]h~See KOMEDA_DEV_* macros for details. Low byte contains the debug level categories, the high byte contains extra debug options.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ hKhj| ubeh}(h]h ]h"]h$]h&]uh1jkhj` ubeh}(h]h ]h"]h$]h&]uh1jIhj{ hKhjubeh}(h]h ]h"]h$]h&]uh1jDhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjUhNubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjhhubh)}(hPipeline and component are used to describe how to handle the pixel data. komeda_device is for describing the whole view of the device, and the control-abilites of device.h]hPipeline and component are used to describe how to handle the pixel data. komeda_device is for describing the whole view of the device, and the control-abilites of device.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjhhubeh}(h]%resource-discovery-and-initializationah ]h"]%resource discovery and initializationah$]h&]uh1hhhhhhhhM?ubh)}(hhh](h)}(hFormat handlingh]hFormat handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMWubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jtkomeda_format_caps (C struct)c.komeda_format_capshNtauh1jghj hhhNhNubjz)}(hhh](j)}(hkomeda_format_capsh]j)}(hstruct komeda_format_capsh](j)}(hjh]hstruct}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj !hhhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj !hhhj!hKubj)}(hkomeda_format_capsh]j)}(hj!h]hkomeda_format_caps}(hj.!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*!ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj !hhhj!hKubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj!hhhj!hKubah}(h]j!ah ](jjeh"]h$]h&]jj)jhuh1j~hj!hKhj!hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj!hhhj!hKubeh}(h]h ](jstructeh"]h$]h&]jjjjY!jjY!jjjuh1jyhhhj hNhNubj)}(hX**Definition**:: struct komeda_format_caps { u32 hw_id; u32 fourcc; u32 supported_layer_types; u32 supported_rots; u32 supported_afbc_layouts; u64 supported_afbc_features; }; **Members** ``hw_id`` hw format id, hw specific value. ``fourcc`` drm fourcc format. ``supported_layer_types`` indicate which layer supports this format ``supported_rots`` allowed rotations for this format ``supported_afbc_layouts`` supported afbc layerout ``supported_afbc_features`` supported afbc featuresh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hje!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja!ubh:}(hja!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK.hj]!ubj)}(hstruct komeda_format_caps { u32 hw_id; u32 fourcc; u32 supported_layer_types; u32 supported_rots; u32 supported_afbc_layouts; u64 supported_afbc_features; };h]hstruct komeda_format_caps { u32 hw_id; u32 fourcc; u32 supported_layer_types; u32 supported_rots; u32 supported_afbc_layouts; u64 supported_afbc_features; };}hj~!sbah}(h]h ]h"]h$]h&]hhuh1jhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK0hj]!ubh)}(h **Members**h]j)}(hj!h]hMembers}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK9hj]!ubjE)}(hhh](jJ)}(h+``hw_id`` hw format id, hw specific value. h](jP)}(h ``hw_id``h]jV)}(hj!h]hhw_id}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj!ubah}(h]h ]h"]h$]h&]uh1jOhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK4hj!ubjl)}(hhh]h)}(h hw format id, hw specific value.h]h hw format id, hw specific value.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hK4hj!ubah}(h]h ]h"]h$]h&]uh1jkhj!ubeh}(h]h ]h"]h$]h&]uh1jIhj!hK4hj!ubjJ)}(h``fourcc`` drm fourcc format. h](jP)}(h ``fourcc``h]jV)}(hj!h]hfourcc}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj!ubah}(h]h ]h"]h$]h&]uh1jOhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK5hj!ubjl)}(hhh]h)}(hdrm fourcc format.h]hdrm fourcc format.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hK5hj!ubah}(h]h ]h"]h$]h&]uh1jkhj!ubeh}(h]h ]h"]h$]h&]uh1jIhj!hK5hj!ubjJ)}(hD``supported_layer_types`` indicate which layer supports this format h](jP)}(h``supported_layer_types``h]jV)}(hj "h]hsupported_layer_types}(hj""hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj"ubah}(h]h ]h"]h$]h&]uh1jOhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK6hj"ubjl)}(hhh]h)}(h)indicate which layer supports this formath]h)indicate which layer supports this format}(hj9"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5"hK6hj6"ubah}(h]h ]h"]h$]h&]uh1jkhj"ubeh}(h]h ]h"]h$]h&]uh1jIhj5"hK6hj!ubjJ)}(h5``supported_rots`` allowed rotations for this format h](jP)}(h``supported_rots``h]jV)}(hjY"h]hsupported_rots}(hj["hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjW"ubah}(h]h ]h"]h$]h&]uh1jOhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK7hjS"ubjl)}(hhh]h)}(h!allowed rotations for this formath]h!allowed rotations for this format}(hjr"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn"hK7hjo"ubah}(h]h ]h"]h$]h&]uh1jkhjS"ubeh}(h]h ]h"]h$]h&]uh1jIhjn"hK7hj!ubjJ)}(h3``supported_afbc_layouts`` supported afbc layerout h](jP)}(h``supported_afbc_layouts``h]jV)}(hj"h]hsupported_afbc_layouts}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj"ubah}(h]h ]h"]h$]h&]uh1jOhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK8hj"ubjl)}(hhh]h)}(hsupported afbc layerouth]hsupported afbc layerout}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hK8hj"ubah}(h]h ]h"]h$]h&]uh1jkhj"ubeh}(h]h ]h"]h$]h&]uh1jIhj"hK8hj!ubjJ)}(h3``supported_afbc_features`` supported afbc featuresh](jP)}(h``supported_afbc_features``h]jV)}(hj"h]hsupported_afbc_features}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj"ubah}(h]h ]h"]h$]h&]uh1jOhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK8hj"ubjl)}(hhh]h)}(hsupported afbc featuresh]hsupported afbc features}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK9hj"ubah}(h]h ]h"]h$]h&]uh1jkhj"ubeh}(h]h ]h"]h$]h&]uh1jIhj"hK8hj!ubeh}(h]h ]h"]h$]h&]uh1jDhj]!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj hhhNhNubh)}(h**Description**h]j)}(hj#h]h Description}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj #ubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKSo, one KMS-Obj represents a sub-pipeline of komeda resources.h]h>So, one KMS-Obj represents a sub-pipeline of komeda resources.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihj'hhubjz)}(hhh](j)}(hPlane: `Layer(input) pipeline`_h]h)}(hj'h](hPlane: }(hj'hhhNhNubh reference)}(h`Layer(input) pipeline`_h]hLayer(input) pipeline}(hj'hhhNhNubah}(h]h ]h"]h$]h&]nameLayer(input) pipelinerefidjuh1j'hj'resolvedKubeh}(h]h ]h"]h$]h&]uh1hhhhMkhj'ubah}(h]h ]h"]h$]h&]uh1j~hj'hhhhhNubj)}(h+Wb_connector: `Writeback(output) pipeline`_h]h)}(hj'h](hWb_connector: }(hj'hhhNhNubj')}(h`Writeback(output) pipeline`_h]hWriteback(output) pipeline}(hj(hhhNhNubah}(h]h ]h"]h$]h&]nameWriteback(output) pipelinej'juh1j'hj'j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhMlhj'ubah}(h]h ]h"]h$]h&]uh1j~hj'hhhhhNubj)}(h!Crtc: `Display output pipeline`_ h]h)}(h Crtc: `Display output pipeline`_h](hCrtc: }(hj"(hhhNhNubj')}(h`Display output pipeline`_h]hDisplay output pipeline}(hj*(hhhNhNubah}(h]h ]h"]h$]h&]nameDisplay output pipelinej'juh1j'hj"(j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhMmhj(ubah}(h]h ]h"]h$]h&]uh1j~hj'hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jyhhhMkhj'hhubh)}(hXSo, for komeda, we treat KMS crtc/plane/connector as users of pipeline and component, and at any one time a pipeline/component only can be used by one user. And pipeline/component will be treated as private object of DRM-KMS; the state will be managed by drm_atomic_commit as well.h]hXSo, for komeda, we treat KMS crtc/plane/connector as users of pipeline and component, and at any one time a pipeline/component only can be used by one user. And pipeline/component will be treated as private object of DRM-KMS; the state will be managed by drm_atomic_commit as well.}(hjL(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj'hhubh)}(hhh](h)}(h)How to map plane to Layer(input) pipelineh]h)How to map plane to Layer(input) pipeline}(hj](hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ(hhhhhMuubh)}(hxKomeda has multiple Layer input pipelines, see: - `Single pipeline data flow`_ - `Dual pipeline with Slave enabled`_h](h4Komeda has multiple Layer input pipelines, see: - }(hjk(hhhNhNubj')}(h`Single pipeline data flow`_h]hSingle pipeline data flow}(hjs(hhhNhNubah}(h]h ]h"]h$]h&]nameSingle pipeline data flowj'juh1j'hjk(j'Kubh - }(hjk(hhhNhNubj')}(h#`Dual pipeline with Slave enabled`_h]h Dual pipeline with Slave enabled}(hj(hhhNhNubah}(h]h ]h"]h$]h&]name Dual pipeline with Slave enabledj'jduh1j'hjk(j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhMwhjZ(hhubh)}(hcThe easiest way is binding a plane to a fixed Layer pipeline, but consider the komeda capabilities:h]hcThe easiest way is binding a plane to a fixed Layer pipeline, but consider the komeda capabilities:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjZ(hhubjz)}(hhh](j)}(hXLayer Split, See `Layer(input) pipeline`_ Layer_Split is quite complicated feature, which splits a big image into two parts and handles it by two layers and two scalers individually. But it imports an edge problem or effect in the middle of the image after the split. To avoid such a problem, it needs a complicated Split calculation and some special configurations to the layer and scaler. We'd better hide such HW related complexity to user mode. h](h)}(h)Layer Split, See `Layer(input) pipeline`_h](hLayer Split, See }(hj(hhhNhNubj')}(h`Layer(input) pipeline`_h]hLayer(input) pipeline}(hj(hhhNhNubah}(h]h ]h"]h$]h&]nameLayer(input) pipelinej'juh1j'hj(j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhM~hj(ubh)}(hXLayer_Split is quite complicated feature, which splits a big image into two parts and handles it by two layers and two scalers individually. But it imports an edge problem or effect in the middle of the image after the split. To avoid such a problem, it needs a complicated Split calculation and some special configurations to the layer and scaler. We'd better hide such HW related complexity to user mode.h]hXLayer_Split is quite complicated feature, which splits a big image into two parts and handles it by two layers and two scalers individually. But it imports an edge problem or effect in the middle of the image after the split. To avoid such a problem, it needs a complicated Split calculation and some special configurations to the layer and scaler. We’d better hide such HW related complexity to user mode.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubeh}(h]h ]h"]h$]h&]uh1j~hj(hhhhhNubj)}(hX?Slave pipeline, See `Dual pipeline with Slave enabled`_ Since the compiz component doesn't output alpha value, the slave pipeline only can be used for bottom layers composition. The komeda driver wants to hide this limitation to the user. The way to do this is to pick a suitable Layer according to plane_state->zpos. h](h)}(h7Slave pipeline, See `Dual pipeline with Slave enabled`_h](hSlave pipeline, See }(hj(hhhNhNubj')}(h#`Dual pipeline with Slave enabled`_h]h Dual pipeline with Slave enabled}(hj(hhhNhNubah}(h]h ]h"]h$]h&]name Dual pipeline with Slave enabledj'jduh1j'hj(j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhMhj(ubh)}(hXSince the compiz component doesn't output alpha value, the slave pipeline only can be used for bottom layers composition. The komeda driver wants to hide this limitation to the user. The way to do this is to pick a suitable Layer according to plane_state->zpos.h]hXSince the compiz component doesn’t output alpha value, the slave pipeline only can be used for bottom layers composition. The komeda driver wants to hide this limitation to the user. The way to do this is to pick a suitable Layer according to plane_state->zpos.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubeh}(h]h ]h"]h$]h&]uh1j~hj(hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jyhhhM~hjZ(hhubh)}(hSo for komeda, the KMS-plane doesn't represent a fixed komeda layer pipeline, but multiple Layers with same capabilities. Komeda will select one or more Layers to fit the requirement of one KMS-plane.h]hSo for komeda, the KMS-plane doesn’t represent a fixed komeda layer pipeline, but multiple Layers with same capabilities. Komeda will select one or more Layers to fit the requirement of one KMS-plane.}(hj )hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjZ(hhubeh}(h](how-to-map-plane-to-layer-input-pipelineah ]h"])how to map plane to layer(input) pipelineah$]h&]uh1hhj'hhhhhMuubh)}(hhh](h)}(h-Make component/pipeline to be drm_private_objh]h-Make component/pipeline to be drm_private_obj}(hj9)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6)hhhhhMubh)}(hVAdd :c:type:`drm_private_obj` to :c:type:`komeda_component`, :c:type:`komeda_pipeline`h](hAdd }(hjG)hhhNhNubh)}(h:c:type:`drm_private_obj`h]jV)}(hjQ)h]hdrm_private_obj}(hjS)hhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhjO)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_private_objuh1hhhhMhjG)ubh to }(hjG)hhhNhNubh)}(h:c:type:`komeda_component`h]jV)}(hjt)h]hkomeda_component}(hjv)hhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhjr)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_componentuh1hhhhMhjG)ubh, }(hjG)hhhNhNubh)}(h:c:type:`komeda_pipeline`h]jV)}(hj)h]hkomeda_pipeline}(hj)hhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhj)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_pipelineuh1hhhhMhjG)ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj6)hhubj)}(hstruct komeda_component { struct drm_private_obj obj; ... } struct komeda_pipeline { struct drm_private_obj obj; ... }h]hstruct komeda_component { struct drm_private_obj obj; ... } struct komeda_pipeline { struct drm_private_obj obj; ... }}hj)sbah}(h]h ]h"]h$]h&]hhƌforcelanguagejhighlight_args}uh1jhhhMhj6)hhubeh}(h]-make-component-pipeline-to-be-drm-private-objah ]h"]-make component/pipeline to be drm_private_objah$]h&]uh1hhj'hhhhhMubh)}(hhh](h)}(h` and :c:type:`komeda_plane.layer `.righth](hWThe plane_state can be split into two data flow (left/right) and handled by two layers }(hj-hhhNhNubh)}(h+:c:type:`komeda_plane.layer `h]jV)}(hj-h]hkomeda_plane.layer}(hj-hhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_planeuh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK&hj-ubh and }(hj-hhhNhNubh)}(h+:c:type:`komeda_plane.layer `h]jV)}(hj-h]hkomeda_plane.layer}(hj-hhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_planeuh1hhj-hK&hj-ubh.right}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj-hK&hj*hhubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jtkomeda_wb_connector (C struct)c.komeda_wb_connectorhNtauh1jghj*hhhNhNubjz)}(hhh](j)}(hkomeda_wb_connectorh]j)}(hstruct komeda_wb_connectorh](j)}(hjh]hstruct}(hj-.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj).hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK,ubj)}(h h]h }(hj;.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj).hhhj:.hK,ubj)}(hkomeda_wb_connectorh]j)}(hj'.h]hkomeda_wb_connector}(hjM.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI.ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj).hhhj:.hK,ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj%.hhhj:.hK,ubah}(h]j .ah ](jjeh"]h$]h&]jj)jhuh1j~hj:.hK,hj".hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj".hhhj:.hK,ubeh}(h]h ](jstructeh"]h$]h&]jjjjx.jjx.jjjuh1jyhhhj*hNhNubj)}(hX**Definition**:: struct komeda_wb_connector { struct drm_writeback_connector base; struct komeda_layer *wb_layer; }; **Members** ``base`` :c:type:`drm_writeback_connector` ``wb_layer`` represents associated writeback pipeline of komedah](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh:}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK9hj|.ubj)}(hkstruct komeda_wb_connector { struct drm_writeback_connector base; struct komeda_layer *wb_layer; };h]hkstruct komeda_wb_connector { struct drm_writeback_connector base; struct komeda_layer *wb_layer; };}hj.sbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK;hj|.ubh)}(h **Members**h]j)}(hj.h]hMembers}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK@hj|.ubjE)}(hhh](jJ)}(h+``base`` :c:type:`drm_writeback_connector` h](jP)}(h``base``h]jV)}(hj.h]hbase}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj.ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK9hj.ubjl)}(hhh]h)}(h!:c:type:`drm_writeback_connector`h]h)}(hj.h]jV)}(hj.h]hdrm_writeback_connector}(hj.hhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhj.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_writeback_connectoruh1hhj.hK9hj.ubah}(h]h ]h"]h$]h&]uh1hhj.hK9hj.ubah}(h]h ]h"]h$]h&]uh1jkhj.ubeh}(h]h ]h"]h$]h&]uh1jIhj.hK9hj.ubjJ)}(h?``wb_layer`` represents associated writeback pipeline of komedah](jP)}(h ``wb_layer``h]jV)}(hj /h]hwb_layer}(hj"/hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj/ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK;hj/ubjl)}(hhh]h)}(h2represents associated writeback pipeline of komedah]h2represents associated writeback pipeline of komeda}(hj9/hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK1ubah}(h]h ]h"]h$]h&]uh1jkhj"1ubeh}(h]h ]h"]h$]h&]uh1jIhj=1hKShj0ubjJ)}(h;``disable_done`` this flip_done is for tracing the disable h](jP)}(h``disable_done``h]jV)}(hja1h]h disable_done}(hjc1hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj_1ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKVhj[1ubjl)}(hhh]h)}(h)this flip_done is for tracing the disableh]h)this flip_done is for tracing the disable}(hjz1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv1hKVhjw1ubah}(h]h ]h"]h$]h&]uh1jkhj[1ubeh}(h]h ]h"]h$]h&]uh1jIhjv1hKVhj0ubjJ)}(h.``encoder`` encoder at the end of the pipelineh](jP)}(h ``encoder``h]jV)}(hj1h]hencoder}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj1ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKXhj1ubjl)}(hhh]h)}(h"encoder at the end of the pipelineh]h"encoder at the end of the pipeline}(hj1hhhNhNubah}(h]h ]h"]h$]h&]u>eh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKYhj1ubah}(h]h ]h"]h$]h&]uh1jkhj1ubeh}(h]h ]h"]h$]h&]uh1jIhj1hKXhj0ubeh}(h]h ]h"]h$]h&]uh1jDhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj*hhhNhNubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jtkomeda_crtc_state (C struct)c.komeda_crtc_statehNtauh1jghj*hhhNhNubjz)}(hhh](j)}(hkomeda_crtc_stateh]j)}(hstruct komeda_crtc_stateh](j)}(hjh]hstruct}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK_ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhj2hK_ubj)}(hkomeda_crtc_stateh]j)}(hj1h]hkomeda_crtc_state}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj1hhhj2hK_ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj1hhhj2hK_ubah}(h]j1ah ](jjeh"]h$]h&]jj)jhuh1j~hj2hK_hj1hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj1hhhj2hK_ubeh}(h]h ](jstructeh"]h$]h&]jjjj?2jj?2jjjuh1jyhhhj*hNhNubj)}(hX**Definition**:: struct komeda_crtc_state { struct drm_crtc_state base; u32 affected_pipes; u32 active_pipes; u64 clock_ratio; u32 max_slave_zorder; }; **Members** ``base`` :c:type:`drm_crtc_state` ``affected_pipes`` the affected pipelines in once display instance ``active_pipes`` the active pipelines in once display instance ``clock_ratio`` ratio of (aclk << 32)/pxlclk ``max_slave_zorder`` the maximum of slave zorderh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjK2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG2ubh:}(hjG2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKahjC2ubj)}(hstruct komeda_crtc_state { struct drm_crtc_state base; u32 affected_pipes; u32 active_pipes; u64 clock_ratio; u32 max_slave_zorder; };h]hstruct komeda_crtc_state { struct drm_crtc_state base; u32 affected_pipes; u32 active_pipes; u64 clock_ratio; u32 max_slave_zorder; };}hjd2sbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKchjC2ubh)}(h **Members**h]j)}(hju2h]hMembers}(hjw2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs2ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKkhjC2ubjE)}(hhh](jJ)}(h"``base`` :c:type:`drm_crtc_state` h](jP)}(h``base``h]jV)}(hj2h]hbase}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj2ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKahj2ubjl)}(hhh]h)}(h:c:type:`drm_crtc_state`h]h)}(hj2h]jV)}(hj2h]hdrm_crtc_state}(hj2hhhNhNubah}(h]h ](j jc-typeeh"]h$]h&]uh1jUhj2ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_crtc_stateuh1hhj2hKahj2ubah}(h]h ]h"]h$]h&]uh1hhj2hKahj2ubah}(h]h ]h"]h$]h&]uh1jkhj2ubeh}(h]h ]h"]h$]h&]uh1jIhj2hKahj2ubjJ)}(hC``affected_pipes`` the affected pipelines in once display instance h](jP)}(h``affected_pipes``h]jV)}(hj2h]haffected_pipes}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj2ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhhj2ubjl)}(hhh]h)}(h/the affected pipelines in once display instanceh]h/the affected pipelines in once display instance}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hKhhj2ubah}(h]h ]h"]h$]h&]uh1jkhj2ubeh}(h]h ]h"]h$]h&]uh1jIhj2hKhhj2ubjJ)}(h?``active_pipes`` the active pipelines in once display instance h](jP)}(h``active_pipes``h]jV)}(hj 3h]h active_pipes}(hj"3hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj3ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKmhj3ubjl)}(hhh]h)}(h-the active pipelines in once display instanceh]h-the active pipelines in once display instance}(hj93hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj53hKmhj63ubah}(h]h ]h"]h$]h&]uh1jkhj3ubeh}(h]h ]h"]h$]h&]uh1jIhj53hKmhj2ubjJ)}(h-``clock_ratio`` ratio of (aclk << 32)/pxlclk h](jP)}(h``clock_ratio``h]jV)}(hjY3h]h clock_ratio}(hj[3hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjW3ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKrhjS3ubjl)}(hhh]h)}(hratio of (aclk << 32)/pxlclkh]hratio of (aclk << 32)/pxlclk}(hjr3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn3hKrhjo3ubah}(h]h ]h"]h$]h&]uh1jkhjS3ubeh}(h]h ]h"]h$]h&]uh1jIhjn3hKrhj2ubjJ)}(h0``max_slave_zorder`` the maximum of slave zorderh](jP)}(h``max_slave_zorder``h]jV)}(hj3h]hmax_slave_zorder}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj3ubah}(h]h ]h"]h$]h&]uh1jOho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKthj3ubjl)}(hhh]h)}(hthe maximum of slave zorderh]hthe maximum of slave zorder}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKuhj3ubah}(h]h ]h"]h$]h&]uh1jkhj3ubeh}(h]h ]h"]h$]h&]uh1jIhj3hKthj2ubeh}(h]h ]h"]h$]h&]uh1jDhjC2ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj*hhhNhNubeh}(h]komeda-kms-abstractionah ]h"]komeda_kms abstractionah$]h&]uh1hhj'hhhhhMubh)}(hhh](h)}(hkomde_kms Functionsh]hkomde_kms Functions}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhhhMubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jt%komeda_crtc_atomic_check (C function)c.komeda_crtc_atomic_checkhNtauh1jghj3hhhNhNubjz)}(hhh](j)}(hUint komeda_crtc_atomic_check (struct drm_crtc *crtc, struct drm_atomic_commit *state)h]j)}(hTint komeda_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state)h](hdesc_sig_keyword_type)}(hinth]hint}(hj4hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j4hj4hhhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKAubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhj4hKAubj)}(hkomeda_crtc_atomic_checkh]j)}(hkomeda_crtc_atomic_checkh]hkomeda_crtc_atomic_check}(hj)4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%4ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj4hhhj4hKAubhdesc_parameterlist)}(h8(struct drm_crtc *crtc, struct drm_atomic_commit *state)h](hdesc_parameter)}(hstruct drm_crtc *crtch](j)}(hjh]hstruct}(hjI4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjE4ubj)}(h h]h }(hjV4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjE4ubh)}(hhh]j)}(hdrm_crtch]hdrm_crtc}(hjg4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjd4ubah}(h]h ]h"]h$]h&] refdomainjreftype identifier reftargetji4modnameN classnameNj j )}j ]j ASTIdentifier)}j}4j+4sbc.komeda_crtc_atomic_checkasbuh1hhjE4ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjE4ubhdesc_sig_punctuation)}(h*h]h*}(hj4hhhNhNubah}(h]h ]pah"]h$]h&]uh1j4hjE4ubj)}(hcrtch]hcrtc}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjE4ubeh}(h]h ]h"]h$]h&]noemphhhuh1jC4hj?4ubjD4)}(hstruct drm_atomic_commit *stateh](j)}(hjh]hstruct}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubh)}(hhh]j)}(hdrm_atomic_commith]hdrm_atomic_commit}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&] refdomainjreftypej}4 reftargetj4modnameN classnameNj j )}j ]j4c.komeda_crtc_atomic_checkasbuh1hhj4ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj4)}(hj4h]h*}(hj 5hhhNhNubah}(h]h ]j4ah"]h$]h&]uh1j4hj4ubj)}(hstateh]hstate}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]noemphhhuh1jC4hj?4ubeh}(h]h ]h"]h$]h&]hhuh1j=4hj4hhhj4hKAubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj3hhhj4hKAubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1j~hj4hKAhj3hhubj)}(hhh]h)}(hbuild display output data flowh]hbuild display output data flow}(hjC5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKAhj@5hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj4hKAubeh}(h]h ](jfunctioneh"]h$]h&]jjjj[5jj[5jjjuh1jyhhhj3hNhNubj)}(hXd**Parameters** ``struct drm_crtc *crtc`` DRM crtc ``struct drm_atomic_commit *state`` the crtc state object **Description** crtc_atomic_check is the final check stage, so beside build a display data pipeline according to the crtc_state, but still needs to release or disable the unclaimed pipeline resources. **Return** Zero for success or -errnoh](h)}(h**Parameters**h]j)}(hje5h]h Parameters}(hjg5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc5ubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKEhj_5ubjE)}(hhh](jJ)}(h#``struct drm_crtc *crtc`` DRM crtc h](jP)}(h``struct drm_crtc *crtc``h]jV)}(hj5h]hstruct drm_crtc *crtc}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj5ubah}(h]h ]h"]h$]h&]uh1jOhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKBhj~5ubjl)}(hhh]h)}(hDRM crtch]hDRM crtc}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hKBhj5ubah}(h]h ]h"]h$]h&]uh1jkhj~5ubeh}(h]h ]h"]h$]h&]uh1jIhj5hKBhj{5ubjJ)}(h:``struct drm_atomic_commit *state`` the crtc state object h](jP)}(h#``struct drm_atomic_commit *state``h]jV)}(hj5h]hstruct drm_atomic_commit *state}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj5ubah}(h]h ]h"]h$]h&]uh1jOhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKChj5ubjl)}(hhh]h)}(hthe crtc state objecth]hthe crtc state object}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hKChj5ubah}(h]h ]h"]h$]h&]uh1jkhj5ubeh}(h]h ]h"]h$]h&]uh1jIhj5hKChj{5ubeh}(h]h ]h"]h$]h&]uh1jDhj_5ubh)}(h**Description**h]j)}(hj5h]h Description}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKEhj_5ubh)}(hcrtc_atomic_check is the final check stage, so beside build a display data pipeline according to the crtc_state, but still needs to release or disable the unclaimed pipeline resources.h]hcrtc_atomic_check is the final check stage, so beside build a display data pipeline according to the crtc_state, but still needs to release or disable the unclaimed pipeline resources.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKDhj_5ubh)}(h **Return**h]j)}(hj6h]hReturn}(hj!6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKHhj_5ubh)}(hZero for success or -errnoh]hZero for success or -errno}(hj56hhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKIhj_5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj3hhhNhNubjh)}(hhh]h}(h]h ]h"]h$]h&]entries](jt&komeda_plane_atomic_check (C function)c.komeda_plane_atomic_checkhNtauh1jghj3hhhNhNubjz)}(hhh](j)}(hXint komeda_plane_atomic_check (struct drm_plane *plane, struct drm_atomic_commit *state)h]j)}(hWint komeda_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_commit *state)h](j4)}(hinth]hint}(hjd6hhhNhNubah}(h]h ]j4ah"]h$]h&]uh1j4hj`6hhhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chK?ubj)}(h h]h }(hjs6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`6hhhjr6hK?ubj)}(hkomeda_plane_atomic_checkh]j)}(hkomeda_plane_atomic_checkh]hkomeda_plane_atomic_check}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj`6hhhjr6hK?ubj>4)}(h:(struct drm_plane *plane, struct drm_atomic_commit *state)h](jD4)}(hstruct drm_plane *planeh](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubh)}(hhh]j)}(h drm_planeh]h drm_plane}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&] refdomainjreftypej}4 reftargetj6modnameN classnameNj j )}j ]j4)}j}4j6sbc.komeda_plane_atomic_checkasbuh1hhj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj4)}(hj4h]h*}(hj6hhhNhNubah}(h]h ]j4ah"]h$]h&]uh1j4hj6ubj)}(hplaneh]hplane}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]noemphhhuh1jC4hj6ubjD4)}(hstruct drm_atomic_commit *stateh](j)}(hjh]hstruct}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj)}(h h]h }(hj 7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubh)}(hhh]j)}(hdrm_atomic_commith]hdrm_atomic_commit}(hj17hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.7ubah}(h]h ]h"]h$]h&] refdomainjreftypej}4 reftargetj37modnameN classnameNj j )}j ]j6c.komeda_plane_atomic_checkasbuh1hhj7ubj)}(h h]h }(hjO7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj4)}(hj4h]h*}(hj]7hhhNhNubah}(h]h ]j4ah"]h$]h&]uh1j4hj7ubj)}(hstateh]hstate}(hjj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]noemphhhuh1jC4hj6ubeh}(h]h ]h"]h$]h&]hhuh1j=4hj`6hhhjr6hK?ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj\6hhhjr6hK?ubah}(h]jW6ah ](jjeh"]h$]h&]jj)jhuh1j~hjr6hK?hjY6hhubj)}(hhh]h)}(hbuild input data flowh]hbuild input data flow}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chK?hj7hhubah}(h]h ]h"]h$]h&]uh1jhjY6hhhjr6hK?ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj7jj7jjjuh1jyhhhj3hNhNubj)}(h**Parameters** ``struct drm_plane *plane`` DRM plane ``struct drm_atomic_commit *state`` the plane state object **Return** Zero for success or -errnoh](h)}(h**Parameters**h]j)}(hj7h]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKChj7ubjE)}(hhh](jJ)}(h&``struct drm_plane *plane`` DRM plane h](jP)}(h``struct drm_plane *plane``h]jV)}(hj7h]hstruct drm_plane *plane}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj7ubah}(h]h ]h"]h$]h&]uh1jOhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chK@hj7ubjl)}(hhh]h)}(h DRM planeh]h DRM plane}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hK@hj7ubah}(h]h ]h"]h$]h&]uh1jkhj7ubeh}(h]h ]h"]h$]h&]uh1jIhj7hK@hj7ubjJ)}(h;``struct drm_atomic_commit *state`` the plane state object h](jP)}(h#``struct drm_atomic_commit *state``h]jV)}(hj8h]hstruct drm_atomic_commit *state}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj 8ubah}(h]h ]h"]h$]h&]uh1jOhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKAhj8ubjl)}(hhh]h)}(hthe plane state objecth]hthe plane state object}(hj'8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#8hKAhj$8ubah}(h]h ]h"]h$]h&]uh1jkhj8ubeh}(h]h ]h"]h$]h&]uh1jIhj#8hKAhj7ubeh}(h]h ]h"]h$]h&]uh1jDhj7ubh)}(h **Return**h]j)}(hjI8h]hReturn}(hjK8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG8ubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKChj7ubh)}(hZero for success or -errnoh]hZero for success or -errno}(hj_8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKChj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj3hhhNhNubeh}(h]komde-kms-functionsah ]h"]komde_kms functionsah$]h&]uh1hhj'hhhhhMubeh}(h]attach-komeda-dev-to-drm-kmsah ]h"]attach komeda_dev to drm-kmsah$]h&]uh1hhhhhhhhM_ubh)}(hhh](h)}(h(Build komeda to be a Linux module driverh]h(Build komeda to be a Linux module driver}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhMubh)}(hNow we have two level devices:h]hNow we have two level devices:}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8hhubjz)}(hhh](j)}(h0komeda_dev: describes the real display hardware.h]h)}(hj8h]h0komeda_dev: describes the real display hardware.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1j~hj8hhhhhNubj)}(hj;jejbjjjjjjjjj(j%jOjLjjjjjgjdjjjjjjjjjjjzjwj j j'j'j8j8j3)j0)j)j)jl*ji*j*j*j3j3jz8jw8j8j8u nametypes}(j8jWj>jejjjjj(jOjjjgjjjjjjzj j'j8j3)j)jl*j*j3jz8j8uh}(j8hjThj;jjbjAjjhjjjjjjj%jjLj+jjZjjjdjjjjjjjjjjjjjwjjvjjy j~ j j jjjjj jjSjYj+j0j'j j!j!j#j#j'%j,%j8j'j0)jZ(j)j6)ji*j)j*jo*j3j*j*j*j-,j2,j .j%.jm/jr/j1j1jw8j3j3j3jW6j\6j8j8jjj[j/jjjjjEjjxjLjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}j+9KsRparse_messages]transform_messages] transformerN include_log] decorationNhhub.