sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget"/translations/zh_CN/gpu/komeda-kmsmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/zh_TW/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/it_IT/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/ja_JP/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/ko_KR/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/sp_SP/gpu/komeda-kmsmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubeh}(h]scalerah ]h"]scalerah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hCompositor (compiz)h]hCompositor (compiz)}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThhhhhK'ubh)}(hXcCompositor blends multiple layers or pixel data flows into one single display frame. its output frame can be fed into post image processor for showing it on the monitor or fed into wb_layer and written to memory at the same time. user can also insert a scaler between compositor and wb_layer to down scale the display frame first and then write to memory.h]hXcCompositor blends multiple layers or pixel data flows into one single display frame. its output frame can be fed into post image processor for showing it on the monitor or fed into wb_layer and written to memory at the same time. user can also insert a scaler between compositor and wb_layer to down scale the display frame first and then write to memory.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjThhubeh}(h]compositor-compizah ]h"]compositor (compiz)ah$]h&]uh1hhhhhhhhK'ubh)}(hhh](h)}(hWriteback Layer (wb_layer)h]hWriteback Layer (wb_layer)}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hhhhhK/ubh)}(hxWriteback layer does the opposite things of Layer, which connects to compiz and writes the composition result to memory.h]hxWriteback layer does the opposite things of Layer, which connects to compiz and writes the composition result to memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hj{hhubeh}(h]writeback-layer-wb-layerah ]h"]writeback layer (wb_layer)ah$]h&]uh1hhhhhhhhK/ubh)}(hhh](h)}(hPost image processor (improc)h]hPost image processor (improc)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK4ubh)}(hjPost image processor adjusts frame data like gamma and color space to fit the requirements of the monitor.h]hjPost image processor adjusts frame data like gamma and color space to fit the requirements of the monitor.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjhhubeh}(h]post-image-processor-improcah ]h"]post image processor (improc)ah$]h&]uh1hhhhhhhhK4ubh)}(hhh](h)}(h Timing controller (timing_ctrlr)h]h Timing controller (timing_ctrlr)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK9ubh)}(h~Final stage of display pipeline, Timing controller is not for the pixel handling, but only for controlling the display timing.h]h~Final stage of display pipeline, Timing controller is not for the pixel handling, but only for controlling the display timing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjhhubeh}(h]timing-controller-timing-ctrlrah ]h"] timing controller (timing_ctrlr)ah$]h&]uh1hhhhhhhhK9ubh)}(hhh](h)}(hMergerh]hMerger}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK>ubh)}(hXD71 scaler mostly only has the half horizontal input/output capabilities compared with Layer, like if Layer supports 4K input size, the scaler only can support 2K input/output in the same time. To achieve the ful frame scaling, D71 introduces Layer Split, which splits the whole image to two half parts and feeds them to two Layers A and B, and does the scaling independently. After scaling the result need to be fed to merger to merge two part images together, and then output merged result to compiz.h]hXD71 scaler mostly only has the half horizontal input/output capabilities compared with Layer, like if Layer supports 4K input size, the scaler only can support 2K input/output in the same time. To achieve the ful frame scaling, D71 introduces Layer Split, which splits the whole image to two half parts and feeds them to two Layers A and B, and does the scaling independently. After scaling the result need to be fed to merger to merge two part images together, and then output merged result to compiz.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjhhubeh}(h]mergerah ]h"]mergerah$]h&]uh1hhhhhhhhK>ubh)}(hhh](h)}(hSplitterh]hSplitter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKHubh)}(hSimilar to Layer Split, but Splitter is used for writeback, which splits the compiz result to two parts and then feed them to two scalers.h]hSimilar to Layer Split, but Splitter is used for writeback, which splits the compiz result to two parts and then feed them to two scalers.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjhhubeh}(h]splitterah ]h"]splitterah$]h&]uh1hhhhhhhhKHubeh}(h] overview-of-d71-like-display-ipsah ]h"] overview of d71 like display ipsah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hPossible D71 Pipeline usageh]hPossible D71 Pipeline usage}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhhhhhKMubh)}(hBenefitting from the modularized architecture, D71 pipelines can be easily adjusted to fit different usages. And D71 has two pipelines, which support two types of working mode:h]hBenefitting from the modularized architecture, D71 pipelines can be easily adjusted to fit different usages. And D71 has two pipelines, which support two types of working mode:}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjFhhubh bullet_list)}(hhh](h list_item)}(h`Dual display mode Two pipelines work independently and separately to drive two display outputs. h]h)}(h_Dual display mode Two pipelines work independently and separately to drive two display outputs.h]h_Dual display mode Two pipelines work independently and separately to drive two display outputs.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjlubah}(h]h ]h"]h$]h&]uh1jjhjghhhhhNubjk)}(hX;Single display mode Two pipelines work together to drive only one display output. On this mode, pipeline_B doesn't work independently, but outputs its composition result into pipeline_A, and its pixel timing also derived from pipeline_A.timing_ctrlr. The pipeline_B works just like a "slave" of pipeline_A(master) h](h)}(hQSingle display mode Two pipelines work together to drive only one display output.h]hQSingle display mode Two pipelines work together to drive only one display output.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubh)}(hOn this mode, pipeline_B doesn't work independently, but outputs its composition result into pipeline_A, and its pixel timing also derived from pipeline_A.timing_ctrlr. The pipeline_B works just like a "slave" of pipeline_A(master)h]hOn this mode, pipeline_B doesn’t work independently, but outputs its composition result into pipeline_A, and its pixel timing also derived from pipeline_A.timing_ctrlr. The pipeline_B works just like a “slave” of pipeline_A(master)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubeh}(h]h ]h"]h$]h&]uh1jjhjghhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jehhhKShjFhhubh)}(hhh](h)}(hSingle pipeline data flowh]hSingle pipeline data flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK_ubhfigure)}(hhh](kfigure kernel_render)}(hhh]h literal_block)}(hXdigraph single_ppl { rankdir=LR; subgraph { "Memory"; "Monitor"; } subgraph cluster_pipeline { style=dashed node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-0"; "Scaler-1"; "Scaler-0/1" } node [bgcolor=grey style=filled] "Layer-0" -> "Scaler-0" "Layer-1" -> "Scaler-0" "Layer-2" -> "Scaler-1" "Layer-3" -> "Scaler-1" "Layer-0" -> "Compiz" "Layer-1" -> "Compiz" "Layer-2" -> "Compiz" "Layer-3" -> "Compiz" "Scaler-0" -> "Compiz" "Scaler-1" -> "Compiz" "Compiz" -> "Scaler-0/1" -> "Wb_layer" "Compiz" -> "Improc" -> "Timing Controller" } "Wb_layer" -> "Memory" "Timing Controller" -> "Monitor" }h]hXdigraph single_ppl { rankdir=LR; subgraph { "Memory"; "Monitor"; } subgraph cluster_pipeline { style=dashed node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-0"; "Scaler-1"; "Scaler-0/1" } node [bgcolor=grey style=filled] "Layer-0" -> "Scaler-0" "Layer-1" -> "Scaler-0" "Layer-2" -> "Scaler-1" "Layer-3" -> "Scaler-1" "Layer-0" -> "Compiz" "Layer-1" -> "Compiz" "Layer-2" -> "Compiz" "Layer-3" -> "Compiz" "Scaler-0" -> "Compiz" "Scaler-1" -> "Compiz" "Compiz" -> "Scaler-0/1" -> "Wb_layer" "Compiz" -> "Improc" -> "Timing Controller" } "Wb_layer" -> "Memory" "Timing Controller" -> "Monitor" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]altSingle pipeline digraphsrclangDOTuh1jhjubhcaption)}(hSingle pipeline data flowh]hSingle pipeline data flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id1ah ]h"]h$]h&]altjcaptionjuh1jhjhhhhhNubeh}(h]single-pipeline-data-flowah ]h"]single pipeline data flowah$]h&]uh1hhjFhhhhhK_ referencedKubh)}(hhh](h)}(h Dual pipeline with Slave enabledh]h Dual pipeline with Slave enabled}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubj)}(hhh](j)}(hhh]j)}(hX&digraph slave_ppl { rankdir=LR; subgraph { "Memory"; "Monitor"; } node [shape=box] subgraph cluster_pipeline_slave { style=dashed label="Slave Pipeline_B" node [shape=box] { node [bgcolor=grey style=dashed] "Slave.Scaler-0"; "Slave.Scaler-1"; } node [bgcolor=grey style=filled] "Slave.Layer-0" -> "Slave.Scaler-0" "Slave.Layer-1" -> "Slave.Scaler-0" "Slave.Layer-2" -> "Slave.Scaler-1" "Slave.Layer-3" -> "Slave.Scaler-1" "Slave.Layer-0" -> "Slave.Compiz" "Slave.Layer-1" -> "Slave.Compiz" "Slave.Layer-2" -> "Slave.Compiz" "Slave.Layer-3" -> "Slave.Compiz" "Slave.Scaler-0" -> "Slave.Compiz" "Slave.Scaler-1" -> "Slave.Compiz" } subgraph cluster_pipeline_master { style=dashed label="Master Pipeline_A" node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-0"; "Scaler-1"; "Scaler-0/1" } node [bgcolor=grey style=filled] "Layer-0" -> "Scaler-0" "Layer-1" -> "Scaler-0" "Layer-2" -> "Scaler-1" "Layer-3" -> "Scaler-1" "Slave.Compiz" -> "Compiz" "Layer-0" -> "Compiz" "Layer-1" -> "Compiz" "Layer-2" -> "Compiz" "Layer-3" -> "Compiz" "Scaler-0" -> "Compiz" "Scaler-1" -> "Compiz" "Compiz" -> "Scaler-0/1" -> "Wb_layer" "Compiz" -> "Improc" -> "Timing Controller" } "Wb_layer" -> "Memory" "Timing Controller" -> "Monitor" }h]hX&digraph slave_ppl { rankdir=LR; subgraph { "Memory"; "Monitor"; } node [shape=box] subgraph cluster_pipeline_slave { style=dashed label="Slave Pipeline_B" node [shape=box] { node [bgcolor=grey style=dashed] "Slave.Scaler-0"; "Slave.Scaler-1"; } node [bgcolor=grey style=filled] "Slave.Layer-0" -> "Slave.Scaler-0" "Slave.Layer-1" -> "Slave.Scaler-0" "Slave.Layer-2" -> "Slave.Scaler-1" "Slave.Layer-3" -> "Slave.Scaler-1" "Slave.Layer-0" -> "Slave.Compiz" "Slave.Layer-1" -> "Slave.Compiz" "Slave.Layer-2" -> "Slave.Compiz" "Slave.Layer-3" -> "Slave.Compiz" "Slave.Scaler-0" -> "Slave.Compiz" "Slave.Scaler-1" -> "Slave.Compiz" } subgraph cluster_pipeline_master { style=dashed label="Master Pipeline_A" node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-0"; "Scaler-1"; "Scaler-0/1" } node [bgcolor=grey style=filled] "Layer-0" -> "Scaler-0" "Layer-1" -> "Scaler-0" "Layer-2" -> "Scaler-1" "Layer-3" -> "Scaler-1" "Slave.Compiz" -> "Compiz" "Layer-0" -> "Compiz" "Layer-1" -> "Compiz" "Layer-2" -> "Compiz" "Layer-3" -> "Compiz" "Scaler-0" -> "Compiz" "Scaler-1" -> "Compiz" "Compiz" -> "Scaler-0/1" -> "Wb_layer" "Compiz" -> "Improc" -> "Timing Controller" } "Wb_layer" -> "Memory" "Timing Controller" -> "Monitor" }}hj!sbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jSlave pipeline digraphjDOTuh1jhjubj)}(h Slave pipeline enabled data flowh]h Slave pipeline enabled data flow}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id2ah ]h"]h$]h&]altj5captionj9uh1jhj hhhhhNubeh}(h] dual-pipeline-with-slave-enabledah ]h"] dual pipeline with slave enabledah$]h&]uh1hhjFhhhhhKj Kubh)}(hhh](h)}(h"Sub-pipelines for input and outputh]h"Sub-pipelines for input and output}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhhhhhKubh)}(hiA complete display pipeline can be easily divided into three sub-pipelines according to the in/out usage.h]hiA complete display pipeline can be easily divided into three sub-pipelines according to the in/out usage.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjVhhubh)}(hhh](h)}(hLayer(input) pipelineh]hLayer(input) pipeline}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhhhhhKubj)}(hhh](j)}(hhh]j)}(hdigraph layer_data_flow { rankdir=LR; node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-n"; } "Layer-n" -> "Scaler-n" -> "Compiz" }h]hdigraph layer_data_flow { rankdir=LR; node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-n"; } "Layer-n" -> "Scaler-n" -> "Compiz" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jLayer data digraphjDOTuh1jhjubj)}(hLayer (input) data flowh]hLayer (input) data flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id3ah ]h"]h$]h&]altjcaptionjuh1jhjuhhhhhNubj)}(hhh](j)}(hhh]j)}(hdigraph layer_data_flow { rankdir=LR; node [shape=box] "Layer-0/1" -> "Scaler-0" -> "Merger" "Layer-2/3" -> "Scaler-1" -> "Merger" "Merger" -> "Compiz" }h]hdigraph layer_data_flow { rankdir=LR; node [shape=box] "Layer-0/1" -> "Scaler-0" -> "Merger" "Layer-2/3" -> "Scaler-1" -> "Merger" "Merger" -> "Compiz" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jLayer Split digraphjDOTuh1jhjubj)}(hLayer Split pipelineh]hLayer Split pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id4ah ]h"]h$]h&]altjcaptionjuh1jhjuhhhhhNubeh}(h]layer-input-pipelineah ]h"]layer(input) pipelineah$]h&]uh1hhjVhhhhhKj Kubh)}(hhh](h)}(hWriteback(output) pipelineh]hWriteback(output) pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj)}(hhh](j)}(hhh]j)}(hdigraph writeback_data_flow { rankdir=LR; node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-n"; } "Compiz" -> "Scaler-n" -> "Wb_layer" }h]hdigraph writeback_data_flow { rankdir=LR; node [shape=box] { node [bgcolor=grey style=dashed] "Scaler-n"; } "Compiz" -> "Scaler-n" -> "Wb_layer" }}hj sbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jwriteback digraphjDOTuh1jhjubj)}(hWriteback(output) data flowh]hWriteback(output) data flow}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id5ah ]h"]h$]h&]altjcaptionj#uh1jhjhhhhhNubj)}(hhh](j)}(hhh]j)}(hdigraph writeback_data_flow { rankdir=LR; node [shape=box] "Compiz" -> "Splitter" "Splitter" -> "Scaler-0" -> "Merger" "Splitter" -> "Scaler-1" -> "Merger" "Merger" -> "Wb_layer" }h]hdigraph writeback_data_flow { rankdir=LR; node [shape=box] "Compiz" -> "Splitter" "Splitter" -> "Scaler-0" -> "Merger" "Splitter" -> "Scaler-1" -> "Merger" "Merger" -> "Wb_layer" }}hj>sbah}(h]h ]h"]h$]h&]hhuh1jhj;hhubah}(h]h ]h"]h$]h&]jsplit writeback digraphjDOTuh1jhj8ubj)}(h!Writeback(output) Split data flowh]h!Writeback(output) Split data flow}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj8ubeh}(h]id6ah ]h"]h$]h&]altjRcaptionjVuh1jhjhhhhhNubeh}(h]writeback-output-pipelineah ]h"]writeback(output) pipelineah$]h&]uh1hhjVhhhhhKj Kubh)}(hhh](h)}(hDisplay output pipelineh]hDisplay output pipeline}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshhhhhMubj)}(hhh](j)}(hhh]j)}(hidigraph single_ppl { rankdir=LR; node [shape=box] "Compiz" -> "Improc" -> "Timing Controller" }h]hidigraph single_ppl { rankdir=LR; node [shape=box] "Compiz" -> "Improc" -> "Timing Controller" }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhjhhubah}(h]h ]h"]h$]h&]jdisplay digraphjDOTuh1jhjubj)}(hdisplay output data flowh]hdisplay output data flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]id7ah ]h"]h$]h&]altjcaptionjuh1jhjshhhhhNubh)}(htIn the following section we'll see these three sub-pipelines will be handled by KMS-plane/wb_conn/crtc respectively.h]hvIn the following section we’ll see these three sub-pipelines will be handled by KMS-plane/wb_conn/crtc respectively.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjshhubeh}(h]display-output-pipelineah ]h"]display output pipelineah$]h&]uh1hhjVhhhhhMj Kubeh}(h]"sub-pipelines-for-input-and-outputah ]h"]"sub-pipelines for input and outputah$]h&]uh1hhjFhhhhhKubeh}(h]possible-d71-pipeline-usageah ]h"]possible d71 pipeline usageah$]h&]uh1hhhhhhhhKMubh)}(hhh](h)}(hKomeda Resource abstractionh]hKomeda Resource abstraction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM+ubh)}(hhh](h)}(h struct komeda_pipeline/componenth]h struct komeda_pipeline/component}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM.ubh)}(hTo fully utilize and easily access/configure the HW, the driver side also uses a similar architecture: Pipeline/Component to describe the HW features and capabilities, and a specific component includes two parts:h]hTo fully utilize and easily access/configure the HW, the driver side also uses a similar architecture: Pipeline/Component to describe the HW features and capabilities, and a specific component includes two parts:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjhhubjf)}(hhh](jk)}(hData flow controlling.h]h)}(hjh]hData flow controlling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1jjhj hhhhhNubjk)}(h.Specific component capabilities and features. h]h)}(h-Specific component capabilities and features.h]h-Specific component capabilities and features.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj'ubah}(h]h ]h"]h$]h&]uh1jjhj hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jehhhM4hjhhubh)}(hSo the driver defines a common header struct komeda_component to describe the data flow control and all specific components are a subclass of this base structure.h]hSo the driver defines a common header struct komeda_component to describe the data flow control and all specific components are a subclass of this base structure.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlekomeda_component (C struct)c.komeda_componenthNtauh1jShjhhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhNubhdesc)}(hhh](hdesc_signature)}(hkomeda_componenth]hdesc_signature_line)}(hstruct komeda_componenth](hdesc_sig_keyword)}(hstructh]hstruct}(hjxhhhNhNubah}(h]h ]kah"]h$]h&]uh1jvhjrhhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjrhhhjhKubh desc_name)}(hkomeda_componenth]h desc_sig_name)}(hjnh]hkomeda_component}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjrhhhjhKubeh}(h]h ]h"]h$]h&]hh add_permalinkuh1jpsphinx_line_type declaratorhjlhhhjhKubah}(h]jbah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jjhjhKhjghhubh desc_content)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjghhhjhKubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jehhhjhjdhNubh container)}(hXn**Definition**:: struct komeda_component { struct drm_private_obj obj; struct komeda_pipeline *pipeline; char name[32]; u32 __iomem *reg; u32 id; u32 hw_id; u8 max_active_inputs; u8 max_active_outputs; u32 supported_inputs; u32 supported_outputs; const struct komeda_component_funcs *funcs; }; **Members** ``obj`` treat component as private obj ``pipeline`` the komeda pipeline this component belongs to ``name`` component name ``reg`` component register base, which is initialized by chip and used by chip only ``id`` component id ``hw_id`` component hw id, which is initialized by chip and used by chip only ``max_active_inputs`` **max_active_outputs**: maximum number of inputs/outputs that can be active at the same time Note: the number isn't the bit number of **supported_inputs** or **supported_outputs**, but may be less than it, since component may not support enabling all **supported_inputs**/outputs at the same time. ``max_active_outputs`` maximum number of outputs ``supported_inputs`` **supported_outputs**: bitmask of BIT(component->id) for the supported inputs/outputs, describes the possibilities of how a component is linked into a pipeline. ``supported_outputs`` bitmask of supported output componenet ids ``funcs`` chip functions to access HWh](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKLhjubj)}(hX@struct komeda_component { struct drm_private_obj obj; struct komeda_pipeline *pipeline; char name[32]; u32 __iomem *reg; u32 id; u32 hw_id; u8 max_active_inputs; u8 max_active_outputs; u32 supported_inputs; u32 supported_outputs; const struct komeda_component_funcs *funcs; };h]hX@struct komeda_component { struct drm_private_obj obj; struct komeda_pipeline *pipeline; char name[32]; u32 __iomem *reg; u32 id; u32 hw_id; u8 max_active_inputs; u8 max_active_outputs; u32 supported_inputs; u32 supported_outputs; const struct komeda_component_funcs *funcs; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKNhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhK\hjubhdefinition_list)}(hhh](hdefinition_list_item)}(h'``obj`` treat component as private obj h](hterm)}(h``obj``h]hliteral)}(hj?h]hobj}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj=ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKPhj7ubh definition)}(hhh]h)}(htreat component as private objh]htreat component as private obj}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhKPhjYubah}(h]h ]h"]h$]h&]uh1jWhj7ubeh}(h]h ]h"]h$]h&]uh1j5hjVhKPhj2ubj6)}(h;``pipeline`` the komeda pipeline this component belongs to h](j<)}(h ``pipeline``h]jB)}(hj|h]hpipeline}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjzubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjvubjX)}(hhh]h)}(h-the komeda pipeline this component belongs toh]h-the komeda pipeline this component belongs to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjvubeh}(h]h ]h"]h$]h&]uh1j5hjhKhj2ubj6)}(h``name`` component name h](j<)}(h``name``h]jB)}(hjh]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjX)}(hhh]h)}(hcomponent nameh]hcomponent name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhj2ubj6)}(hT``reg`` component register base, which is initialized by chip and used by chip only h](j<)}(h``reg``h]jB)}(hjh]hreg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h 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chip only h](j<)}(h ``hw_id``h]jB)}(hjah]hhw_id}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj_ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKahj[ubjX)}(hhh]h)}(hCcomponent hw id, which is initialized by chip and used by chip onlyh]hCcomponent hw id, which is initialized by chip and used by chip only}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhK`hjwubah}(h]h ]h"]h$]h&]uh1jWhj[ubeh}(h]h ]h"]h$]h&]uh1j5hjvhKahj2ubj6)}(hXA``max_active_inputs`` **max_active_outputs**: maximum number of inputs/outputs that can be active at the same time Note: the number isn't the bit number of **supported_inputs** or **supported_outputs**, but may be less than it, since component may not support enabling all **supported_inputs**/outputs at the same time. h](j<)}(h``max_active_inputs``h]jB)}(hjh]hmax_active_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKlhjubjX)}(hhh](h)}(h**max_active_outputs**:h](j)}(h**max_active_outputs**h]hmax_active_outputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKfhjubh)}(hXmaximum number of inputs/outputs that can be active at the same time Note: the number isn't the bit number of **supported_inputs** or **supported_outputs**, but may be less than it, since component may not support enabling all **supported_inputs**/outputs at the same time.h](hpmaximum number of inputs/outputs that can be active at the same time Note: the number isn’t the bit number of }(hjhhhNhNubj)}(h**supported_inputs**h]hsupported_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh or }(hjhhhNhNubj)}(h**supported_outputs**h]hsupported_outputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhH, but may be less than it, since component may not support enabling all }(hjhhhNhNubj)}(h**supported_inputs**h]hsupported_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh/outputs at the same time.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhhjubeh}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKlhj2ubj6)}(h1``max_active_outputs`` maximum number of outputs h](j<)}(h``max_active_outputs``h]jB)}(hj(h]hmax_active_outputs}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj&ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj"ubjX)}(hhh]h)}(hmaximum number of outputsh]hmaximum number of outputs}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKhj>ubah}(h]h ]h"]h$]h&]uh1jWhj"ubeh}(h]h ]h"]h$]h&]uh1j5hj=hKhj2ubj6)}(h``supported_inputs`` **supported_outputs**: bitmask of BIT(component->id) for the supported inputs/outputs, describes the possibilities of how a component is linked into a pipeline. h](j<)}(h``supported_inputs``h]jB)}(hjah]hsupported_inputs}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj_ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKwhj[ubjX)}(hhh](h)}(h**supported_outputs**:h](j)}(h**supported_outputs**h]hsupported_outputs}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubh:}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKshjwubh)}(hbitmask of BIT(component->id) for the supported inputs/outputs, describes the possibilities of how a component is linked into a pipeline.h]hbitmask of BIT(component->id) for the supported inputs/outputs, describes the possibilities of how a component is linked into a pipeline.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKuhjwubeh}(h]h ]h"]h$]h&]uh1jWhj[ubeh}(h]h ]h"]h$]h&]uh1j5hjvhKwhj2ubj6)}(hA``supported_outputs`` bitmask of supported output componenet ids h](j<)}(h``supported_outputs``h]jB)}(hjh]hsupported_outputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjX)}(hhh]h)}(h*bitmask of supported output componenet idsh]h*bitmask of supported output componenet ids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhj2ubj6)}(h%``funcs`` chip functions to access HWh](j<)}(h ``funcs``h]jB)}(hjh]hfuncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhK~hjubjX)}(hhh]h)}(hchip functions to access HWh]hchip functions to access HW}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hj hK~hj2ubeh}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjdhNubh)}(h**Description**h]j)}(hj4 h]h Description}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2 ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjhhubh)}(hstruct komeda_component describe the data flow capabilities for how to link a component into the display pipeline. all specified components are subclass of this structure.h]hstruct komeda_component describe the data flow capabilities for how to link a component into the display pipeline. all specified components are subclass of this structure.}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKJhjhhubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`"komeda_component_output (C struct)c.komeda_component_outputhNtauh1jShjhhhjdhNubjf)}(hhh](jk)}(hkomeda_component_outputh]jq)}(hstruct komeda_component_outputh](jw)}(hjzh]hstruct}(hjr hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhjn hhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKQubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn hhhj hKQubj)}(hkomeda_component_outputh]j)}(hjl h]hkomeda_component_output}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjn hhhj hKQubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhjj hhhj hKQubah}(h]je ah ](jjeh"]h$]h&]jj)jhuh1jjhj hKQhjg hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjg hhhj hKQubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1jehhhjhjdhNubj)}(hX4**Definition**:: struct komeda_component_output { struct komeda_component *component; u8 output_port; }; **Members** ``component`` indicate which component the data comes from ``output_port`` the output port of the :c:type:`komeda_component_output.component `h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubj)}(h_struct komeda_component_output { struct komeda_component *component; u8 output_port; };h]h_struct komeda_component_output { struct komeda_component *component; u8 output_port; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubj1)}(hhh](j6)}(h;``component`` indicate which component the data comes from h](j<)}(h ``component``h]jB)}(hj h]h component}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjX)}(hhh]h)}(h,indicate which component the data comes fromh]h,indicate which component the data comes from}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj' hKhj( ubah}(h]h ]h"]h$]h&]uh1jWhj ubeh}(h]h ]h"]h$]h&]uh1j5hj' hKhj ubj6)}(hl``output_port`` the output port of the :c:type:`komeda_component_output.component `h](j<)}(h``output_port``h]jB)}(hjK h]h output_port}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjI ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjE ubjX)}(hhh]h)}(h\the output port of the :c:type:`komeda_component_output.component `h](hthe output port of the }(hjd hhhNhNubh)}(hE:c:type:`komeda_component_output.component `h]jB)}(hjn h]h!komeda_component_output.component}(hjp hhhNhNubah}(h]h ](xrefjc-typeeh"]h$]h&]uh1jAhjl ubah}(h]h ]h"]h$]h&]refdocgpu/komeda-kms refdomainjreftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sb reftargetkomeda_component_outputuh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjd ubeh}(h]h ]h"]h$]h&]uh1hhj hKhja ubah}(h]h ]h"]h$]h&]uh1jWhjE ubeh}(h]h ]h"]h$]h&]uh1j5hj` hKhj ubeh}(h]h ]h"]h$]h&]uh1j0hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjdhNubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjhhubh)}(ha component has multiple outputs, if want to know where the data comes from, only know the component is not enough, we still need to know its output porth]ha component has multiple outputs, if want to know where the data comes from, only know the component is not enough, we still need to know its output port}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjhhubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`!komeda_component_state (C struct)c.komeda_component_statehNtauh1jShjhhhjdhNubjf)}(hhh](jk)}(hkomeda_component_stateh]jq)}(hstruct komeda_component_stateh](jw)}(hjzh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj hhht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hkomeda_component_stateh]j)}(hj h]hkomeda_component_state}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hKubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jjhj hKhj hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjjA jjA jjjuh1jehhhjhjdhNubj)}(hX**Definition**:: struct komeda_component_state { struct drm_private_state obj; struct komeda_component *component; union { struct drm_crtc *crtc; struct drm_plane *plane; struct drm_connector *wb_conn; void *binding_user; }; u16 active_inputs; u16 changed_active_inputs; u16 affected_inputs; struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS]; }; **Members** ``obj`` tracking component_state by drm_atomic_state ``component`` backpointer to the component ``{unnamed_union}`` anonymous ``crtc`` backpointer for user crtc ``plane`` backpointer for user plane ``wb_conn`` backpointer for user wb_connector ``binding_user`` currently bound user, the user can be **crtc**, **plane** or **wb_conn**, which is valid decided by **component** and **inputs** - Layer: its user always is plane. - compiz/improc/timing_ctrlr: the user is crtc. - wb_layer: wb_conn; - scaler: plane when input is layer, wb_conn if input is compiz. ``active_inputs`` active_inputs is bitmask of **inputs** index - active_inputs = changed_active_inputs | unchanged_active_inputs - affected_inputs = old->active_inputs | new->active_inputs; - disabling_inputs = affected_inputs ^ active_inputs; - changed_inputs = disabling_inputs | changed_active_inputs; NOTE: changed_inputs doesn't include all active_input but only **changed_active_inputs**, and this bitmask can be used in chip level for dirty update. ``changed_active_inputs`` bitmask of the changed **active_inputs** ``affected_inputs`` bitmask for affected **inputs** ``inputs`` the specific inputs[i] only valid on BIT(i) has been set in **active_inputs**, if not the inputs[i] is undefined.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI ubh:}(hjI hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjE ubj)}(hXstruct komeda_component_state { struct drm_private_state obj; struct komeda_component *component; union { struct drm_crtc *crtc; struct drm_plane *plane; struct drm_connector *wb_conn; void *binding_user; }; u16 active_inputs; u16 changed_active_inputs; u16 affected_inputs; struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS]; };h]hXstruct komeda_component_state { struct drm_private_state obj; struct komeda_component *component; union { struct drm_crtc *crtc; struct drm_plane *plane; struct drm_connector *wb_conn; void *binding_user; }; u16 active_inputs; u16 changed_active_inputs; u16 affected_inputs; struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS]; };}hjf sbah}(h]h ]h"]h$]h&]hhuh1jht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjE ubh)}(h **Members**h]j)}(hjw h]hMembers}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjE ubj1)}(hhh](j6)}(h5``obj`` tracking component_state by drm_atomic_state h](j<)}(h``obj``h]jB)}(hj h]hobj}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjX)}(hhh]h)}(h,tracking component_state by drm_atomic_stateh]h,tracking component_state by drm_atomic_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jWhj ubeh}(h]h ]h"]h$]h&]uh1j5hj hKhj ubj6)}(h+``component`` backpointer to the component h](j<)}(h ``component``h]jB)}(hj h]h component}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjX)}(hhh]h)}(hbackpointer to the componenth]hbackpointer to the component}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jWhj ubeh}(h]h ]h"]h$]h&]uh1j5hj hKhj ubj6)}(h``{unnamed_union}`` anonymous h](j<)}(h``{unnamed_union}``h]jB)}(hj h]h{unnamed_union}}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjX)}(hhh]h)}(h anonymoush]h anonymous}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jWhj ubeh}(h]h ]h"]h$]h&]uh1j5hj hKhj ubj6)}(h#``crtc`` backpointer for user crtc h](j<)}(h``crtc``h]jB)}(hjA h]hcrtc}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj? ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj; ubjX)}(hhh]h)}(hbackpointer for user crtch]hbackpointer for user crtc}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV hKhjW ubah}(h]h ]h"]h$]h&]uh1jWhj; ubeh}(h]h ]h"]h$]h&]uh1j5hjV hKhj ubj6)}(h%``plane`` backpointer for user plane h](j<)}(h ``plane``h]jB)}(hjz h]hplane}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjx ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjt ubjX)}(hhh]h)}(hbackpointer for user planeh]hbackpointer for user plane}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jWhjt ubeh}(h]h ]h"]h$]h&]uh1j5hj hKhj ubj6)}(h.``wb_conn`` backpointer for user wb_connector h](j<)}(h ``wb_conn``h]jB)}(hj h]hwb_conn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjX)}(hhh]h)}(h!backpointer for user wb_connectorh]h!backpointer for user wb_connector}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jWhj ubeh}(h]h ]h"]h$]h&]uh1j5hj hKhj ubj6)}(hX@``binding_user`` currently bound user, the user can be **crtc**, **plane** or **wb_conn**, which is valid decided by **component** and **inputs** - Layer: its user always is plane. - compiz/improc/timing_ctrlr: the user is crtc. - wb_layer: wb_conn; - scaler: plane when input is layer, wb_conn if input is compiz. h](j<)}(h``binding_user``h]jB)}(hj h]h binding_user}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjX)}(hhh](h)}(hcurrently bound user, the user can be **crtc**, **plane** or **wb_conn**, which is valid decided by **component** and **inputs**h](h¤tly bound user, the user can be }(hj hhhNhNubj)}(h**crtc**h]hcrtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, }(hj hhhNhNubj)}(h **plane**h]hplane}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh or }(hj hhhNhNubj)}(h **wb_conn**h]hwb_conn}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, which is valid decided by }(hj hhhNhNubj)}(h **component**h]h component}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh and }(hj hhhNhNubj)}(h **inputs**h]hinputs}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjf)}(hhh](jk)}(h Layer: its user always is plane.h]h)}(hjo h]h Layer: its user always is plane.}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjm ubah}(h]h ]h"]h$]h&]uh1jjhjj ubjk)}(h-compiz/improc/timing_ctrlr: the user is crtc.h]h)}(hj h]h-compiz/improc/timing_ctrlr: the user is crtc.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubah}(h]h ]h"]h$]h&]uh1jjhjj ubjk)}(hwb_layer: wb_conn;h]h)}(hj h]hwb_layer: wb_conn;}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubah}(h]h ]h"]h$]h&]uh1jjhjj ubjk)}(h?scaler: plane when input is layer, wb_conn if input is compiz. h]h)}(h>scaler: plane when input is layer, wb_conn if input is compiz.h]h>scaler: plane when input is layer, wb_conn if input is compiz.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jjhjj ubeh}(h]h ]h"]h$]h&]jjuh1jehj~ hKhj ubeh}(h]h ]h"]h$]h&]uh1jWhj ubeh}(h]h ]h"]h$]h&]uh1j5hj hKhj ubj6)}(hX``active_inputs`` active_inputs is bitmask of **inputs** index - active_inputs = changed_active_inputs | unchanged_active_inputs - affected_inputs = old->active_inputs | new->active_inputs; - disabling_inputs = affected_inputs ^ active_inputs; - changed_inputs = disabling_inputs | changed_active_inputs; NOTE: changed_inputs doesn't include all active_input but only **changed_active_inputs**, and this bitmask can be used in chip level for dirty update. h](j<)}(h``active_inputs``h]jB)}(hj h]h active_inputs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjX)}(hhh](h)}(h,active_inputs is bitmask of **inputs** indexh](hactive_inputs is bitmask of }(hj hhhNhNubj)}(h **inputs**h]hinputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh index}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubjf)}(hhh](jk)}(h?active_inputs = changed_active_inputs | unchanged_active_inputsh]h)}(hj$h]h?active_inputs = changed_active_inputs | unchanged_active_inputs}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj"ubah}(h]h ]h"]h$]h&]uh1jjhjubjk)}(h:affected_inputs = old->active_inputs | new->active_inputs;h]h)}(hj<h]h:affected_inputs = old->active_inputs | new->active_inputs;}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj:ubah}(h]h ]h"]h$]h&]uh1jjhjubjk)}(h3disabling_inputs = affected_inputs ^ active_inputs;h]h)}(hjTh]h3disabling_inputs = affected_inputs ^ active_inputs;}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjRubah}(h]h ]h"]h$]h&]uh1jjhjubjk)}(h;changed_inputs = disabling_inputs | changed_active_inputs; h]h)}(h:changed_inputs = disabling_inputs | changed_active_inputs;h]h:changed_inputs = disabling_inputs | changed_active_inputs;}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjjubah}(h]h ]h"]h$]h&]uh1jjhjubeh}(h]h ]h"]h$]h&]jjuh1jehj3hKhj ubh)}(hNOTE: changed_inputs doesn't include all active_input but only **changed_active_inputs**, and this bitmask can be used in chip level for dirty update.h](hANOTE: changed_inputs doesn’t include all active_input but only }(hjhhhNhNubj)}(h**changed_active_inputs**h]hchanged_active_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh>, and this bitmask can be used in chip level for dirty update.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhj ubeh}(h]h ]h"]h$]h&]uh1jWhj ubeh}(h]h ]h"]h$]h&]uh1j5hj hKhj ubj6)}(hC``changed_active_inputs`` bitmask of the changed **active_inputs** h](j<)}(h``changed_active_inputs``h]jB)}(hjh]hchanged_active_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjX)}(hhh]h)}(h(bitmask of the changed **active_inputs**h](hbitmask of the changed }(hjhhhNhNubj)}(h**active_inputs**h]h active_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhj ubj6)}(h4``affected_inputs`` bitmask for affected **inputs** h](j<)}(h``affected_inputs``h]jB)}(hjh]haffected_inputs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjX)}(hhh]h)}(hbitmask for affected **inputs**h](hbitmask for affected }(hjhhhNhNubj)}(h **inputs**h]hinputs}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhj ubj6)}(h|``inputs`` the specific inputs[i] only valid on BIT(i) has been set in **active_inputs**, if not the inputs[i] is undefined.h](j<)}(h ``inputs``h]jB)}(hjJh]hinputs}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjHubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjDubjX)}(hhh]h)}(hqthe specific inputs[i] only valid on BIT(i) has been set in **active_inputs**, if not the inputs[i] is undefined.h](hid) of active componentsh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubj)}(hstruct komeda_pipeline_state { struct drm_private_state obj; struct komeda_pipeline *pipe; struct drm_crtc *crtc; u32 active_comps; };h]hstruct komeda_pipeline_state { struct drm_private_state obj; struct komeda_pipeline *pipe; struct drm_crtc *crtc; u32 active_comps; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubh)}(h **Members**h]j)}(hj/h]hMembers}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubj1)}(hhh](j6)}(h4``obj`` tracking pipeline_state by drm_atomic_state h](j<)}(h``obj``h]jB)}(hjNh]hobj}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjLubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjHubjX)}(hhh]h)}(h+tracking pipeline_state by drm_atomic_stateh]h+tracking pipeline_state by drm_atomic_state}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjdubah}(h]h ]h"]h$]h&]uh1jWhjHubeh}(h]h ]h"]h$]h&]uh1j5hjchMhjEubj6)}(h%``pipe`` backpointer to the pipeline h](j<)}(h``pipe``h]jB)}(hjh]hpipe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjX)}(hhh]h)}(hbackpointer to the pipelineh]hbackpointer to the pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjEubj6)}(h``crtc`` currently bound crtc h](j<)}(h``crtc``h]jB)}(hjh]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhKhjubjX)}(hhh]h)}(hcurrently bound crtch]hcurrently bound crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjEubj6)}(hB``active_comps`` bitmask - BIT(component->id) of active componentsh](j<)}(h``active_comps``h]jB)}(hjh]h active_comps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubjX)}(hhh]h)}(h1bitmask - BIT(component->id) of active componentsh]h1bitmask - BIT(component->id) of active components}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhMhjEubeh}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjdhNubh)}(h**NOTE**h]j)}(hj<h]hNOTE}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjhhubh)}(hUnlike the pipeline, pipeline_state doesn’t gather any component_state into it. It because all component will be managed by drm_atomic_state.h]hUnlike the pipeline, pipeline_state doesn’t gather any component_state into it. It because all component will be managed by drm_atomic_state.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:315: ./drivers/gpu/drm/arm/display/komeda/komeda_pipeline.hhMhjhhubeh}(h] struct-komeda-pipeline-componentah ]h"] struct komeda_pipeline/componentah$]h&]uh1hhjhhhhhM.ubeh}(h]komeda-resource-abstractionah ]h"]komeda resource abstractionah$]h&]uh1hhhhhhhhM+ubh)}(hhh](h)}(h%Resource discovery and initializationh]h%Resource discovery and initialization}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhhhhhM?ubh)}(hPipeline and component are used to describe how to handle the pixel data. We still need a @struct komeda_dev to describe the whole view of the device, and the control-abilites of device.h]hPipeline and component are used to describe how to handle the pixel data. We still need a @struct komeda_dev to describe the whole view of the device, and the control-abilites of device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjqhhubh)}(hX8We have &komeda_dev, &komeda_pipeline, &komeda_component. Now fill devices with pipelines. Since komeda is not for D71 only but also intended for later products, of course we’d better share as much as possible between different products. To achieve this, split the komeda device into two layers: CORE and CHIP.h]hX8We have &komeda_dev, &komeda_pipeline, &komeda_component. Now fill devices with pipelines. Since komeda is not for D71 only but also intended for later products, of course we’d better share as much as possible between different products. To achieve this, split the komeda device into two layers: CORE and CHIP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjqhhubjf)}(hhh](jk)}(h4CORE: for common features and capabilities handling.h]h)}(hjh]h4CORE: for common features and capabilities handling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jjhjhhhhhNubjk)}(hNCHIP: for register programming and HW specific feature (limitation) handling. h]h)}(hMCHIP: for register programming and HW specific feature (limitation) handling.h]hMCHIP: for register programming and HW specific feature (limitation) handling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjubah}(h]h ]h"]h$]h&]uh1jjhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jehhhMJhjqhhubh)}(h7CORE can access CHIP by three chip function structures:h]h7CORE can access CHIP by three chip function structures:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjqhhubjf)}(hhh](jk)}(hstruct komeda_dev_funcsh]h)}(hjh]hstruct komeda_dev_funcs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhjubah}(h]h ]h"]h$]h&]uh1jjhjhhhhhNubjk)}(hstruct komeda_pipeline_funcsh]h)}(hjh]hstruct komeda_pipeline_funcs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjubah}(h]h ]h"]h$]h&]uh1jjhjhhhhhNubjk)}(hstruct komeda_component_funcs h]h)}(hstruct komeda_component_funcsh]hstruct komeda_component_funcs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhjubah}(h]h ]h"]h$]h&]uh1jjhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jehhhMOhjqhhubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_dev_funcs (C struct)c.komeda_dev_funcshNtauh1jShjqhhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhNubjf)}(hhh](jk)}(hkomeda_dev_funcsh]jq)}(hstruct komeda_dev_funcsh](jw)}(hjzh]hstruct}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhjIhhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKubj)}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhhjZhKubj)}(hkomeda_dev_funcsh]j)}(hjGh]hkomeda_dev_funcs}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubah}(h]h ](jjeh"]h$]h&]hhuh1jhjIhhhjZhKubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhjEhhhjZhKubah}(h]j?ah ](jjeh"]h$]h&]jj)jhuh1jjhjZhKhjBhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjBhhhjZhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jehhhjqhjAhNubj)}(hXn**Definition**:: struct komeda_dev_funcs { void (*init_format_table)(struct komeda_dev *mdev); int (*enum_resources)(struct komeda_dev *mdev); void (*cleanup)(struct komeda_dev *mdev); int (*connect_iommu)(struct komeda_dev *mdev); int (*disconnect_iommu)(struct komeda_dev *mdev); irqreturn_t (*irq_handler)(struct komeda_dev *mdev, struct komeda_events *events); int (*enable_irq)(struct komeda_dev *mdev); int (*disable_irq)(struct komeda_dev *mdev); void (*on_off_vblank)(struct komeda_dev *mdev, int master_pipe, bool on); void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); int (*change_opmode)(struct komeda_dev *mdev, int new_mode); void (*flush)(struct komeda_dev *mdev, int master_pipe, u32 active_pipes); }; **Members** ``init_format_table`` initialize :c:type:`komeda_dev->format_table `, this function should be called before the :c:type:`enum_resource <_resource>` ``enum_resources`` for CHIP to report or add pipeline and component resources to CORE ``cleanup`` call to chip to cleanup komeda_dev->chip data ``connect_iommu`` Optional, connect to external iommu ``disconnect_iommu`` Optional, disconnect to external iommu ``irq_handler`` for CORE to get the HW event from the CHIP when interrupt happened. ``enable_irq`` enable irq ``disable_irq`` disable irq ``on_off_vblank`` notify HW to on/off vblank ``dump_register`` Optional, dump registers to seq_file ``change_opmode`` Notify HW to switch to a new display operation mode. ``flush`` Notify the HW to flush or kickoff the updateh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKXhjubj)}(hXstruct komeda_dev_funcs { void (*init_format_table)(struct komeda_dev *mdev); int (*enum_resources)(struct komeda_dev *mdev); void (*cleanup)(struct komeda_dev *mdev); int (*connect_iommu)(struct komeda_dev *mdev); int (*disconnect_iommu)(struct komeda_dev *mdev); irqreturn_t (*irq_handler)(struct komeda_dev *mdev, struct komeda_events *events); int (*enable_irq)(struct komeda_dev *mdev); int (*disable_irq)(struct komeda_dev *mdev); void (*on_off_vblank)(struct komeda_dev *mdev, int master_pipe, bool on); void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); int (*change_opmode)(struct komeda_dev *mdev, int new_mode); void (*flush)(struct komeda_dev *mdev, int master_pipe, u32 active_pipes); };h]hXstruct komeda_dev_funcs { void (*init_format_table)(struct komeda_dev *mdev); int (*enum_resources)(struct komeda_dev *mdev); void (*cleanup)(struct komeda_dev *mdev); int (*connect_iommu)(struct komeda_dev *mdev); int (*disconnect_iommu)(struct komeda_dev *mdev); irqreturn_t (*irq_handler)(struct komeda_dev *mdev, struct komeda_events *events); int (*enable_irq)(struct komeda_dev *mdev); int (*disable_irq)(struct komeda_dev *mdev); void (*on_off_vblank)(struct komeda_dev *mdev, int master_pipe, bool on); void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); int (*change_opmode)(struct komeda_dev *mdev, int new_mode); void (*flush)(struct komeda_dev *mdev, int master_pipe, u32 active_pipes); };}hjsbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKZhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKihjubj1)}(hhh](j6)}(h``init_format_table`` initialize :c:type:`komeda_dev->format_table `, this function should be called before the :c:type:`enum_resource <_resource>` h](j<)}(h``init_format_table``h]jB)}(hjh]hinit_format_table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhK]hjubjX)}(hhh]h)}(hinitialize :c:type:`komeda_dev->format_table `, this function should be called before the :c:type:`enum_resource <_resource>`h](h initialize }(hjhhhNhNubh)}(h/:c:type:`komeda_dev->format_table `h]jB)}(hjh]hkomeda_dev->format_table}(hjhhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_devuh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhK\hjubh,, this function should be called before the }(hjhhhNhNubh)}(h#:c:type:`enum_resource <_resource>`h]jB)}(hj4h]h enum_resource}(hj6hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj2ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j _resourceuh1hhj-hK\hjubeh}(h]h ]h"]h$]h&]uh1hhj-hK\hjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhK]hjubj6)}(hV``enum_resources`` for CHIP to report or add pipeline and component resources to CORE h](j<)}(h``enum_resources``h]jB)}(hjih]henum_resources}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjgubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKchjcubjX)}(hhh]h)}(hBfor CHIP to report or add pipeline and component resources to COREh]hBfor CHIP to report or add pipeline and component resources to CORE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKchjubah}(h]h ]h"]h$]h&]uh1jWhjcubeh}(h]h ]h"]h$]h&]uh1j5hj~hKchjubj6)}(h:``cleanup`` call to chip to cleanup komeda_dev->chip data h](j<)}(h ``cleanup``h]jB)}(hjh]hcleanup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h-call to chip to cleanup komeda_dev->chip datah]h-call to chip to cleanup komeda_dev->chip data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h6``connect_iommu`` Optional, connect to external iommu h](j<)}(h``connect_iommu``h]jB)}(hjh]h connect_iommu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h#Optional, connect to external iommuh]h#Optional, connect to external iommu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h<``disconnect_iommu`` Optional, disconnect to external iommu h](j<)}(h``disconnect_iommu``h]jB)}(hjh]hdisconnect_iommu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h&Optional, disconnect to external iommuh]h&Optional, disconnect to external iommu}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKhj*ubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hj)hKhjubj6)}(hT``irq_handler`` for CORE to get the HW event from the CHIP when interrupt happened. h](j<)}(h``irq_handler``h]jB)}(hjMh]h irq_handler}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjKubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKohjGubjX)}(hhh]h)}(hCfor CORE to get the HW event from the CHIP when interrupt happened.h]hCfor CORE to get the HW event from the CHIP when interrupt happened.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhKohjcubah}(h]h ]h"]h$]h&]uh1jWhjGubeh}(h]h ]h"]h$]h&]uh1j5hjbhKohjubj6)}(h``enable_irq`` enable irq h](j<)}(h``enable_irq``h]jB)}(hjh]h enable_irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h enable irqh]h enable irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h``disable_irq`` disable irq h](j<)}(h``disable_irq``h]jB)}(hjh]h disable_irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h disable irqh]h disable irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h-``on_off_vblank`` notify HW to on/off vblank h](j<)}(h``on_off_vblank``h]jB)}(hjh]h on_off_vblank}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(hnotify HW to on/off vblankh]hnotify HW to on/off vblank}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hj hKhjubj6)}(h7``dump_register`` Optional, dump registers to seq_file h](j<)}(h``dump_register``h]jB)}(hj1h]h dump_register}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj/ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj+ubjX)}(hhh]h)}(h$Optional, dump registers to seq_fileh]h$Optional, dump registers to seq_file}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhKhjGubah}(h]h ]h"]h$]h&]uh1jWhj+ubeh}(h]h ]h"]h$]h&]uh1j5hjFhKhjubj6)}(hG``change_opmode`` Notify HW to switch to a new display operation mode. h](j<)}(h``change_opmode``h]jB)}(hjjh]h change_opmode}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjhubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjdubjX)}(hhh]h)}(h4Notify HW to switch to a new display operation mode.h]h4Notify HW to switch to a new display operation mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjdubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h6``flush`` Notify the HW to flush or kickoff the updateh](j<)}(h ``flush``h]jB)}(hjh]hflush}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h,Notify the HW to flush or kickoff the updateh]h,Notify the HW to flush or kickoff the update}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubeh}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjqhhhjAhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjqhhubh)}(hLSupplied by chip level and returned by the chip entry function xxx_identify,h]hLSupplied by chip level and returned by the chip entry function xxx_identify,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKVhjqhhubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_dev (C struct) c.komeda_devhNtauh1jShjqhhhjAhNubjf)}(hhh](jk)}(h komeda_devh]jq)}(hstruct komeda_devh](jw)}(hjzh]hstruct}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhK[ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj1hK[ubj)}(h komeda_devh]j)}(hjh]h komeda_dev}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj1hK[ubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhjhhhj1hK[ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jjhj1hK[hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhj1hK[ubeh}(h]h ](jstructeh"]h$]h&]jjjjojjojjjuh1jehhhjqhjAhNubj)}(hX**Definition**:: struct komeda_dev { struct device *dev; u32 __iomem *reg_base; struct komeda_chip_info chip; struct komeda_format_caps_table fmt_tbl; struct clk *aclk; int irq; struct mutex lock; u32 dpmode; int n_pipelines; struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES]; const struct komeda_dev_funcs *funcs; void *chip_data; struct iommu_domain *iommu; struct dentry *debugfs_root; u16 err_verbosity; #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0); #define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1); #define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2); #define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8); #define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12); }; **Members** ``dev`` the base device structure ``reg_base`` the base address of komeda io space ``chip`` the basic chip information ``fmt_tbl`` initialized by :c:type:`komeda_dev_funcs->init_format_table ` ``aclk`` HW main engine clk ``irq`` irq number ``lock`` used to protect dpmode ``dpmode`` current display mode ``n_pipelines`` the number of pipe in **pipelines** ``pipelines`` the komeda pipelines ``funcs`` chip funcs to access to HW ``chip_data`` chip data will be added by :c:type:`komeda_dev_funcs.enum_resources\(\) ` and destroyed by :c:type:`komeda_dev_funcs.cleanup\(\) ` ``iommu`` iommu domain ``debugfs_root`` root directory of komeda debugfs ``err_verbosity`` bitmask for how much extra info to print on error See KOMEDA_DEV_* macros for details. Low byte contains the debug level categories, the high byte contains extra debug options.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubh:}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjsubj)}(hXstruct komeda_dev { struct device *dev; u32 __iomem *reg_base; struct komeda_chip_info chip; struct komeda_format_caps_table fmt_tbl; struct clk *aclk; int irq; struct mutex lock; u32 dpmode; int n_pipelines; struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES]; const struct komeda_dev_funcs *funcs; void *chip_data; struct iommu_domain *iommu; struct dentry *debugfs_root; u16 err_verbosity; #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0); #define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1); #define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2); #define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8); #define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12); };h]hXstruct komeda_dev { struct device *dev; u32 __iomem *reg_base; struct komeda_chip_info chip; struct komeda_format_caps_table fmt_tbl; struct clk *aclk; int irq; struct mutex lock; u32 dpmode; int n_pipelines; struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES]; const struct komeda_dev_funcs *funcs; void *chip_data; struct iommu_domain *iommu; struct dentry *debugfs_root; u16 err_verbosity; #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0); #define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1); #define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2); #define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8); #define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12); };}hjsbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjsubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjsubj1)}(hhh](j6)}(h"``dev`` the base device structure h](j<)}(h``dev``h]jB)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(hthe base device structureh]hthe base device structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h1``reg_base`` the base address of komeda io space h](j<)}(h ``reg_base``h]jB)}(hjh]hreg_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h#the base address of komeda io spaceh]h#the base address of komeda io space}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h$``chip`` the basic chip information h](j<)}(h``chip``h]jB)}(hj6h]hchip}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj4ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj0ubjX)}(hhh]h)}(hthe basic chip informationh]hthe basic chip information}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhKhjLubah}(h]h ]h"]h$]h&]uh1jWhj0ubeh}(h]h ]h"]h$]h&]uh1j5hjKhKhjubj6)}(h\``fmt_tbl`` initialized by :c:type:`komeda_dev_funcs->init_format_table ` h](j<)}(h ``fmt_tbl``h]jB)}(hjoh]hfmt_tbl}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjmubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjiubjX)}(hhh]h)}(hOinitialized by :c:type:`komeda_dev_funcs->init_format_table `h](hinitialized by }(hjhhhNhNubh)}(h@:c:type:`komeda_dev_funcs->init_format_table `h]jB)}(hjh]h#komeda_dev_funcs->init_format_table}(hjhhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_dev_funcsuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjiubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h``aclk`` HW main engine clk h](j<)}(h``aclk``h]jB)}(hjh]haclk}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(hHW main engine clkh]hHW main engine clk}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h``irq`` irq number h](j<)}(h``irq``h]jB)}(hjh]hirq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h irq numberh]h irq number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h ``lock`` used to protect dpmode h](j<)}(h``lock``h]jB)}(hj9h]hlock}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj7ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj3ubjX)}(hhh]h)}(hused to protect dpmodeh]hused to protect dpmode}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhKhjOubah}(h]h ]h"]h$]h&]uh1jWhj3ubeh}(h]h ]h"]h$]h&]uh1j5hjNhKhjubj6)}(h ``dpmode`` current display mode h](j<)}(h ``dpmode``h]jB)}(hjrh]hdpmode}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjpubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjlubjX)}(hhh]h)}(hcurrent display modeh]hcurrent display mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjlubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h4``n_pipelines`` the number of pipe in **pipelines** h](j<)}(h``n_pipelines``h]jB)}(hjh]h n_pipelines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h#the number of pipe in **pipelines**h](hthe number of pipe in }(hjhhhNhNubj)}(h **pipelines**h]h pipelines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h#``pipelines`` the komeda pipelines h](j<)}(h ``pipelines``h]jB)}(hjh]h pipelines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(hthe komeda pipelinesh]hthe komeda pipelines}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h%``funcs`` chip funcs to access to HW h](j<)}(h ``funcs``h]jB)}(hj+h]hfuncs}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj)ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj%ubjX)}(hhh]h)}(hchip funcs to access to HWh]hchip funcs to access to HW}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hKhjAubah}(h]h ]h"]h$]h&]uh1jWhj%ubeh}(h]h ]h"]h$]h&]uh1j5hj@hKhjubj6)}(h``chip_data`` chip data will be added by :c:type:`komeda_dev_funcs.enum_resources\(\) ` and destroyed by :c:type:`komeda_dev_funcs.cleanup\(\) ` h](j<)}(h ``chip_data``h]jB)}(hjdh]h chip_data}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjbubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj^ubjX)}(hhh]h)}(hchip data will be added by :c:type:`komeda_dev_funcs.enum_resources\(\) ` and destroyed by :c:type:`komeda_dev_funcs.cleanup\(\) `h](hchip data will be added by }(hj}hhhNhNubh)}(h@:c:type:`komeda_dev_funcs.enum_resources\(\) `h]jB)}(hjh]h!komeda_dev_funcs.enum_resources()}(hjhhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_dev_funcsuh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj}ubh and destroyed by }(hj}hhhNhNubh)}(h9:c:type:`komeda_dev_funcs.cleanup\(\) `h]jB)}(hjh]hkomeda_dev_funcs.cleanup()}(hjhhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_dev_funcsuh1hhjhKhj}ubeh}(h]h ]h"]h$]h&]uh1hhjhKhjzubah}(h]h ]h"]h$]h&]uh1jWhj^ubeh}(h]h ]h"]h$]h&]uh1j5hjyhKhjubj6)}(h``iommu`` iommu domain h](j<)}(h ``iommu``h]jB)}(hjh]hiommu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjubjX)}(hhh]h)}(h iommu domainh]h iommu domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1j5hjhKhjubj6)}(h2``debugfs_root`` root directory of komeda debugfs h](j<)}(h``debugfs_root``h]jB)}(hj h]h debugfs_root}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhj ubjX)}(hhh]h)}(h root directory of komeda debugfsh]h root directory of komeda debugfs}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj. hKhj/ ubah}(h]h ]h"]h$]h&]uh1jWhj ubeh}(h]h ]h"]h$]h&]uh1j5hj. hKhjubj6)}(h``err_verbosity`` bitmask for how much extra info to print on error See KOMEDA_DEV_* macros for details. Low byte contains the debug level categories, the high byte contains extra debug options.h](j<)}(h``err_verbosity``h]jB)}(hjR h]h err_verbosity}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjP ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjL ubjX)}(hhh](h)}(h1bitmask for how much extra info to print on errorh]h1bitmask for how much extra info to print on error}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjh ubh)}(h~See KOMEDA_DEV_* macros for details. Low byte contains the debug level categories, the high byte contains extra debug options.h]h~See KOMEDA_DEV_* macros for details. Low byte contains the debug level categories, the high byte contains extra debug options.}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjg hKhjh ubeh}(h]h ]h"]h$]h&]uh1jWhjL ubeh}(h]h ]h"]h$]h&]uh1j5hjg hKhjubeh}(h]h ]h"]h$]h&]uh1j0hjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjqhhhjAhNubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjqhhubh)}(hPipeline and component are used to describe how to handle the pixel data. komeda_device is for describing the whole view of the device, and the control-abilites of device.h]hPipeline and component are used to describe how to handle the pixel data. komeda_device is for describing the whole view of the device, and the control-abilites of device.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:339: ./drivers/gpu/drm/arm/display/komeda/komeda_dev.hhKhjqhhubeh}(h]%resource-discovery-and-initializationah ]h"]%resource discovery and initializationah$]h&]uh1hhhhhhhhM?ubh)}(hhh](h)}(hFormat handlingh]hFormat handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMWubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_format_caps (C struct)c.komeda_format_capshNtauh1jShj hhhNhNubjf)}(hhh](jk)}(hkomeda_format_capsh]jq)}(hstruct komeda_format_capsh](jw)}(hjzh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj hhhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj!hKubj)}(hkomeda_format_capsh]j)}(hj h]hkomeda_format_caps}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj!hKubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj hhhj!hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jjhj!hKhj hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj hhhj!hKubeh}(h]h ](jstructeh"]h$]h&]jjjjE!jjE!jjjuh1jehhhj hNhNubj)}(hX**Definition**:: struct komeda_format_caps { u32 hw_id; u32 fourcc; u32 supported_layer_types; u32 supported_rots; u32 supported_afbc_layouts; u64 supported_afbc_features; }; **Members** ``hw_id`` hw format id, hw specific value. ``fourcc`` drm fourcc format. ``supported_layer_types`` indicate which layer supports this format ``supported_rots`` allowed rotations for this format ``supported_afbc_layouts`` supported afbc layerout ``supported_afbc_features`` supported afbc featuresh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjQ!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM!ubh:}(hjM!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK-hjI!ubj)}(hstruct komeda_format_caps { u32 hw_id; u32 fourcc; u32 supported_layer_types; u32 supported_rots; u32 supported_afbc_layouts; u64 supported_afbc_features; };h]hstruct komeda_format_caps { u32 hw_id; u32 fourcc; u32 supported_layer_types; u32 supported_rots; u32 supported_afbc_layouts; u64 supported_afbc_features; };}hjj!sbah}(h]h ]h"]h$]h&]hhuh1jhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK/hjI!ubh)}(h **Members**h]j)}(hj{!h]hMembers}(hj}!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy!ubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK8hjI!ubj1)}(hhh](j6)}(h+``hw_id`` hw format id, hw specific value. h](j<)}(h ``hw_id``h]jB)}(hj!h]hhw_id}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj!ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK4hj!ubjX)}(hhh]h)}(h hw format id, hw specific value.h]h hw format id, hw specific value.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hK4hj!ubah}(h]h ]h"]h$]h&]uh1jWhj!ubeh}(h]h ]h"]h$]h&]uh1j5hj!hK4hj!ubj6)}(h``fourcc`` drm fourcc format. h](j<)}(h ``fourcc``h]jB)}(hj!h]hfourcc}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj!ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK5hj!ubjX)}(hhh]h)}(hdrm fourcc format.h]hdrm fourcc format.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hK5hj!ubah}(h]h ]h"]h$]h&]uh1jWhj!ubeh}(h]h ]h"]h$]h&]uh1j5hj!hK5hj!ubj6)}(hD``supported_layer_types`` indicate which layer supports this format h](j<)}(h``supported_layer_types``h]jB)}(hj "h]hsupported_layer_types}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj "ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK6hj"ubjX)}(hhh]h)}(h)indicate which layer supports this formath]h)indicate which layer supports this format}(hj%"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!"hK6hj""ubah}(h]h ]h"]h$]h&]uh1jWhj"ubeh}(h]h ]h"]h$]h&]uh1j5hj!"hK6hj!ubj6)}(h5``supported_rots`` allowed rotations for this format h](j<)}(h``supported_rots``h]jB)}(hjE"h]hsupported_rots}(hjG"hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjC"ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK7hj?"ubjX)}(hhh]h)}(h!allowed rotations for this formath]h!allowed rotations for this format}(hj^"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ"hK7hj["ubah}(h]h ]h"]h$]h&]uh1jWhj?"ubeh}(h]h ]h"]h$]h&]uh1j5hjZ"hK7hj!ubj6)}(h3``supported_afbc_layouts`` supported afbc layerout h](j<)}(h``supported_afbc_layouts``h]jB)}(hj~"h]hsupported_afbc_layouts}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj|"ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK8hjx"ubjX)}(hhh]h)}(hsupported afbc layerouth]hsupported afbc layerout}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hK8hj"ubah}(h]h ]h"]h$]h&]uh1jWhjx"ubeh}(h]h ]h"]h$]h&]uh1j5hj"hK8hj!ubj6)}(h3``supported_afbc_features`` supported afbc featuresh](j<)}(h``supported_afbc_features``h]jB)}(hj"h]hsupported_afbc_features}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj"ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK8hj"ubjX)}(hhh]h)}(hsupported afbc featuresh]hsupported afbc features}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK9hj"ubah}(h]h ]h"]h$]h&]uh1jWhj"ubeh}(h]h ]h"]h$]h&]uh1j5hj"hK8hj!ubeh}(h]h ]h"]h$]h&]uh1j0hjI!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj hhhNhNubh)}(h**Description**h]j)}(hj"h]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK#h]hdrm_format_info}(hj@#hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj<#ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_format_infouh1hhj7#hK+hj#ubh.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj7#hK+hj hhubh)}(h**NOTE**h]j)}(hjg#h]hNOTE}(hji#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje#ubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK/hj hhubh)}(hQone fourcc may has two different format_caps items for fourcc and fourcc+modifierh]hQone fourcc may has two different format_caps items for fourcc and fourcc+modifier}(hj}#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK0hj hhubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`#komeda_format_caps_table (C struct)c.komeda_format_caps_tablehNtauh1jShj hhhNhNubjf)}(hhh](jk)}(hkomeda_format_caps_tableh]jq)}(hstruct komeda_format_caps_tableh](jw)}(hjzh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj#hhhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhK6ubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhj#hK6ubj)}(hkomeda_format_caps_tableh]j)}(hj#h]hkomeda_format_caps_table}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj#hhhj#hK6ubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj#hhhj#hK6ubah}(h]j#ah ](jjeh"]h$]h&]jj)jhuh1jjhj#hK6hj#hhubj)}(hhh]h)}(hformat_caps manangerh]hformat_caps mananger}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKDhj#hhubah}(h]h ]h"]h$]h&]uh1jhj#hhhj#hK6ubeh}(h]h ](jstructeh"]h$]h&]jjjj#jj#jjjuh1jehhhj hNhNubj)}(hX%**Definition**:: struct komeda_format_caps_table { u32 n_formats; const struct komeda_format_caps *format_caps; bool (*format_mod_supported)(const struct komeda_format_caps *caps, u32 layer_type, u64 modifier, u32 rot); }; **Members** ``n_formats`` the size of format_caps list. ``format_caps`` format_caps list. ``format_mod_supported`` Optional. Some HW may have special requirements or limitations which can not be described by format_caps, this func supply HW the ability to do the further HW specific check.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj $hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubh:}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKHhj$ubj)}(hstruct komeda_format_caps_table { u32 n_formats; const struct komeda_format_caps *format_caps; bool (*format_mod_supported)(const struct komeda_format_caps *caps, u32 layer_type, u64 modifier, u32 rot); };h]hstruct komeda_format_caps_table { u32 n_formats; const struct komeda_format_caps *format_caps; bool (*format_mod_supported)(const struct komeda_format_caps *caps, u32 layer_type, u64 modifier, u32 rot); };}hj$$sbah}(h]h ]h"]h$]h&]hhuh1jhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKJhj$ubh)}(h **Members**h]j)}(hj5$h]hMembers}(hj7$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3$ubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKPhj$ubj1)}(hhh](j6)}(h,``n_formats`` the size of format_caps list. h](j<)}(h ``n_formats``h]jB)}(hjT$h]h n_formats}(hjV$hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjR$ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKGhjN$ubjX)}(hhh]h)}(hthe size of format_caps list.h]hthe size of format_caps list.}(hjm$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji$hKGhjj$ubah}(h]h ]h"]h$]h&]uh1jWhjN$ubeh}(h]h ]h"]h$]h&]uh1j5hji$hKGhjK$ubj6)}(h"``format_caps`` format_caps list. h](j<)}(h``format_caps``h]jB)}(hj$h]h format_caps}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj$ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKHhj$ubjX)}(hhh]h)}(hformat_caps list.h]hformat_caps list.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hKHhj$ubah}(h]h ]h"]h$]h&]uh1jWhj$ubeh}(h]h ]h"]h$]h&]uh1j5hj$hKHhjK$ubj6)}(h``format_mod_supported`` Optional. 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Some HW may have special requirements or limitations which can not be described by format_caps, this func supply HW the ability to do the further HW specific check.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:345: ./drivers/gpu/drm/arm/display/komeda/komeda_format_caps.hhKIhj$ubah}(h]h ]h"]h$]h&]uh1jWhj$ubeh}(h]h ]h"]h$]h&]uh1j5hj$hKJhjK$ubeh}(h]h ]h"]h$]h&]uh1j0hj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj hhhNhNubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_fb (C struct) c.komeda_fbhNtauh1jShj hhhNhNubjf)}(hhh](jk)}(h komeda_fbh]jq)}(hstruct komeda_fbh](jw)}(hjzh]hstruct}(hj %hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj%hhhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKubj)}(h h]h }(hj.%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhhj-%hKubj)}(h komeda_fbh]j)}(hj%h]h komeda_fb}(hj@%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<%ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj%hhhj-%hKubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj%hhhj-%hKubah}(h]j%ah ](jjeh"]h$]h&]jj)jhuh1jjhj-%hKhj%hhubj)}(hhh]h)}(h/Entending drm_framebuffer with komeda attributeh]h/Entending drm_framebuffer with komeda attribute}(hjb%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj_%hhubah}(h]h ]h"]h$]h&]uh1jhj%hhhj-%hKubeh}(h]h ](jstructeh"]h$]h&]jjjjz%jjz%jjjuh1jehhhj hNhNubj)}(hXK**Definition**:: struct komeda_fb { struct drm_framebuffer base; const struct komeda_format_caps *format_caps; bool is_va; u32 aligned_w; u32 aligned_h; u32 afbc_size; u32 offset_payload; }; **Members** ``base`` :c:type:`drm_framebuffer` ``format_caps`` extends drm_format_info for komeda specific information ``is_va`` if smmu is enabled, it will be true ``aligned_w`` aligned frame buffer width ``aligned_h`` aligned frame buffer height ``afbc_size`` minimum size of afbc ``offset_payload`` start of afbc body bufferh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubh:}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj~%ubj)}(hstruct komeda_fb { struct drm_framebuffer base; const struct komeda_format_caps *format_caps; bool is_va; u32 aligned_w; u32 aligned_h; u32 afbc_size; u32 offset_payload; };h]hstruct komeda_fb { struct drm_framebuffer base; const struct komeda_format_caps *format_caps; bool is_va; u32 aligned_w; u32 aligned_h; u32 afbc_size; u32 offset_payload; };}hj%sbah}(h]h ]h"]h$]h&]hhuh1jhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj~%ubh)}(h **Members**h]j)}(hj%h]hMembers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj~%ubj1)}(hhh](j6)}(h#``base`` :c:type:`drm_framebuffer` h](j<)}(h``base``h]jB)}(hj%h]hbase}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj%ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj%ubjX)}(hhh]h)}(h:c:type:`drm_framebuffer`h]h)}(hj%h]jB)}(hj%h]hdrm_framebuffer}(hj%hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj%ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_framebufferuh1hhj%hKhj%ubah}(h]h ]h"]h$]h&]uh1hhj%hKhj%ubah}(h]h ]h"]h$]h&]uh1jWhj%ubeh}(h]h ]h"]h$]h&]uh1j5hj%hKhj%ubj6)}(hH``format_caps`` extends drm_format_info for komeda specific information h](j<)}(h``format_caps``h]jB)}(hj"&h]h format_caps}(hj$&hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj &ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj&ubjX)}(hhh]h)}(h7extends drm_format_info for komeda specific informationh]h7extends drm_format_info for komeda specific information}(hj;&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7&hKhj8&ubah}(h]h ]h"]h$]h&]uh1jWhj&ubeh}(h]h ]h"]h$]h&]uh1j5hj7&hKhj%ubj6)}(h.``is_va`` if smmu is enabled, it will be true h](j<)}(h ``is_va``h]jB)}(hj[&h]his_va}(hj]&hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjY&ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhjU&ubjX)}(hhh]h)}(h#if smmu is enabled, it will be trueh]h#if smmu is enabled, it will be true}(hjt&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp&hKhjq&ubah}(h]h ]h"]h$]h&]uh1jWhjU&ubeh}(h]h ]h"]h$]h&]uh1j5hjp&hKhj%ubj6)}(h)``aligned_w`` aligned frame buffer width h](j<)}(h ``aligned_w``h]jB)}(hj&h]h aligned_w}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj&ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj&ubjX)}(hhh]h)}(haligned frame buffer widthh]haligned frame buffer width}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKhj&ubah}(h]h ]h"]h$]h&]uh1jWhj&ubeh}(h]h ]h"]h$]h&]uh1j5hj&hKhj%ubj6)}(h*``aligned_h`` aligned frame buffer height h](j<)}(h ``aligned_h``h]jB)}(hj&h]h aligned_h}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj&ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj&ubjX)}(hhh]h)}(haligned frame buffer heighth]haligned frame buffer height}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKhj&ubah}(h]h ]h"]h$]h&]uh1jWhj&ubeh}(h]h ]h"]h$]h&]uh1j5hj&hKhj%ubj6)}(h#``afbc_size`` minimum size of afbc h](j<)}(h ``afbc_size``h]jB)}(hj'h]h afbc_size}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj'ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj'ubjX)}(hhh]h)}(hminimum size of afbch]hminimum size of afbc}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hKhj'ubah}(h]h ]h"]h$]h&]uh1jWhj'ubeh}(h]h ]h"]h$]h&]uh1j5hj'hKhj%ubj6)}(h,``offset_payload`` start of afbc body bufferh](j<)}(h``offset_payload``h]jB)}(hj?'h]hoffset_payload}(hjA'hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj='ubah}(h]h ]h"]h$]h&]uh1j;hw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhj9'ubjX)}(hhh]h)}(hstart of afbc body bufferh]hstart of afbc body buffer}(hjX'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhw/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:347: ./drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.hhKhjU'ubah}(h]h ]h"]h$]h&]uh1jWhj9'ubeh}(h]h ]h"]h$]h&]uh1j5hjT'hKhj%ubeh}(h]h ]h"]h$]h&]uh1j0hj~%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj hhhNhNubeh}(h]format-handlingah ]h"]format handlingah$]h&]uh1hhhhhhhhMWubh)}(hhh](h)}(hAttach komeda_dev to DRM-KMSh]hAttach komeda_dev to DRM-KMS}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhM_ubh)}(hXKomeda abstracts resources by pipeline/component, but DRM-KMS uses crtc/plane/connector. One KMS-obj cannot represent only one single component, since the requirements of a single KMS object cannot simply be achieved by a single component, usually that needs multiple components to fit the requirement. Like set mode, gamma, ctm for KMS all target on CRTC-obj, but komeda needs compiz, improc and timing_ctrlr to work together to fit these requirements. And a KMS-Plane may require multiple komeda resources: layer/scaler/compiz.h]hXKomeda abstracts resources by pipeline/component, but DRM-KMS uses crtc/plane/connector. One KMS-obj cannot represent only one single component, since the requirements of a single KMS object cannot simply be achieved by a single component, usually that needs multiple components to fit the requirement. Like set mode, gamma, ctm for KMS all target on CRTC-obj, but komeda needs compiz, improc and timing_ctrlr to work together to fit these requirements. And a KMS-Plane may require multiple komeda resources: layer/scaler/compiz.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahj'hhubh)}(h>So, one KMS-Obj represents a sub-pipeline of komeda resources.h]h>So, one KMS-Obj represents a sub-pipeline of komeda resources.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihj'hhubjf)}(hhh](jk)}(hPlane: `Layer(input) pipeline`_h]h)}(hj'h](hPlane: }(hj'hhhNhNubh reference)}(h`Layer(input) pipeline`_h]hLayer(input) pipeline}(hj'hhhNhNubah}(h]h ]h"]h$]h&]nameLayer(input) pipelinerefidjuh1j'hj'resolvedKubeh}(h]h ]h"]h$]h&]uh1hhhhMkhj'ubah}(h]h ]h"]h$]h&]uh1jjhj'hhhhhNubjk)}(h+Wb_connector: `Writeback(output) pipeline`_h]h)}(hj'h](hWb_connector: }(hj'hhhNhNubj')}(h`Writeback(output) pipeline`_h]hWriteback(output) pipeline}(hj'hhhNhNubah}(h]h ]h"]h$]h&]nameWriteback(output) pipelinej'jmuh1j'hj'j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhMlhj'ubah}(h]h ]h"]h$]h&]uh1jjhj'hhhhhNubjk)}(h!Crtc: `Display output pipeline`_ h]h)}(h Crtc: `Display output pipeline`_h](hCrtc: }(hj(hhhNhNubj')}(h`Display output pipeline`_h]hDisplay output pipeline}(hj(hhhNhNubah}(h]h ]h"]h$]h&]nameDisplay output pipelinej'juh1j'hj(j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhMmhj (ubah}(h]h ]h"]h$]h&]uh1jjhj'hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jehhhMkhj'hhubh)}(hXSo, for komeda, we treat KMS crtc/plane/connector as users of pipeline and component, and at any one time a pipeline/component only can be used by one user. And pipeline/component will be treated as private object of DRM-KMS; the state will be managed by drm_atomic_state as well.h]hXSo, for komeda, we treat KMS crtc/plane/connector as users of pipeline and component, and at any one time a pipeline/component only can be used by one user. And pipeline/component will be treated as private object of DRM-KMS; the state will be managed by drm_atomic_state as well.}(hj8(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj'hhubh)}(hhh](h)}(h)How to map plane to Layer(input) pipelineh]h)How to map plane to Layer(input) pipeline}(hjI(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF(hhhhhMuubh)}(hxKomeda has multiple Layer input pipelines, see: - `Single pipeline data flow`_ - `Dual pipeline with Slave enabled`_h](h4Komeda has multiple Layer input pipelines, see: - }(hjW(hhhNhNubj')}(h`Single pipeline data flow`_h]hSingle pipeline data flow}(hj_(hhhNhNubah}(h]h ]h"]h$]h&]nameSingle pipeline data flowj'juh1j'hjW(j'Kubh - }(hjW(hhhNhNubj')}(h#`Dual pipeline with Slave enabled`_h]h Dual pipeline with Slave enabled}(hjs(hhhNhNubah}(h]h ]h"]h$]h&]name Dual pipeline with Slave enabledj'jPuh1j'hjW(j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhMwhjF(hhubh)}(hcThe easiest way is binding a plane to a fixed Layer pipeline, but consider the komeda capabilities:h]hcThe easiest way is binding a plane to a fixed Layer pipeline, but consider the komeda capabilities:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjF(hhubjf)}(hhh](jk)}(hXLayer Split, See `Layer(input) pipeline`_ Layer_Split is quite complicated feature, which splits a big image into two parts and handles it by two layers and two scalers individually. But it imports an edge problem or effect in the middle of the image after the split. To avoid such a problem, it needs a complicated Split calculation and some special configurations to the layer and scaler. We'd better hide such HW related complexity to user mode. h](h)}(h)Layer Split, See `Layer(input) pipeline`_h](hLayer Split, See }(hj(hhhNhNubj')}(h`Layer(input) pipeline`_h]hLayer(input) pipeline}(hj(hhhNhNubah}(h]h ]h"]h$]h&]nameLayer(input) pipelinej'juh1j'hj(j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhM~hj(ubh)}(hXLayer_Split is quite complicated feature, which splits a big image into two parts and handles it by two layers and two scalers individually. But it imports an edge problem or effect in the middle of the image after the split. To avoid such a problem, it needs a complicated Split calculation and some special configurations to the layer and scaler. We'd better hide such HW related complexity to user mode.h]hXLayer_Split is quite complicated feature, which splits a big image into two parts and handles it by two layers and two scalers individually. But it imports an edge problem or effect in the middle of the image after the split. To avoid such a problem, it needs a complicated Split calculation and some special configurations to the layer and scaler. We’d better hide such HW related complexity to user mode.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubeh}(h]h ]h"]h$]h&]uh1jjhj(hhhhhNubjk)}(hX?Slave pipeline, See `Dual pipeline with Slave enabled`_ Since the compiz component doesn't output alpha value, the slave pipeline only can be used for bottom layers composition. The komeda driver wants to hide this limitation to the user. The way to do this is to pick a suitable Layer according to plane_state->zpos. h](h)}(h7Slave pipeline, See `Dual pipeline with Slave enabled`_h](hSlave pipeline, See }(hj(hhhNhNubj')}(h#`Dual pipeline with Slave enabled`_h]h Dual pipeline with Slave enabled}(hj(hhhNhNubah}(h]h ]h"]h$]h&]name Dual pipeline with Slave enabledj'jPuh1j'hj(j'Kubeh}(h]h ]h"]h$]h&]uh1hhhhMhj(ubh)}(hXSince the compiz component doesn't output alpha value, the slave pipeline only can be used for bottom layers composition. The komeda driver wants to hide this limitation to the user. The way to do this is to pick a suitable Layer according to plane_state->zpos.h]hXSince the compiz component doesn’t output alpha value, the slave pipeline only can be used for bottom layers composition. The komeda driver wants to hide this limitation to the user. The way to do this is to pick a suitable Layer according to plane_state->zpos.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubeh}(h]h ]h"]h$]h&]uh1jjhj(hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jehhhM~hjF(hhubh)}(hSo for komeda, the KMS-plane doesn't represent a fixed komeda layer pipeline, but multiple Layers with same capabilities. Komeda will select one or more Layers to fit the requirement of one KMS-plane.h]hSo for komeda, the KMS-plane doesn’t represent a fixed komeda layer pipeline, but multiple Layers with same capabilities. Komeda will select one or more Layers to fit the requirement of one KMS-plane.}(hj )hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjF(hhubeh}(h](how-to-map-plane-to-layer-input-pipelineah ]h"])how to map plane to layer(input) pipelineah$]h&]uh1hhj'hhhhhMuubh)}(hhh](h)}(h-Make component/pipeline to be drm_private_objh]h-Make component/pipeline to be drm_private_obj}(hj%)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj")hhhhhMubh)}(hVAdd :c:type:`drm_private_obj` to :c:type:`komeda_component`, :c:type:`komeda_pipeline`h](hAdd }(hj3)hhhNhNubh)}(h:c:type:`drm_private_obj`h]jB)}(hj=)h]hdrm_private_obj}(hj?)hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj;)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_private_objuh1hhhhMhj3)ubh to }(hj3)hhhNhNubh)}(h:c:type:`komeda_component`h]jB)}(hj`)h]hkomeda_component}(hjb)hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj^)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_componentuh1hhhhMhj3)ubh, }(hj3)hhhNhNubh)}(h:c:type:`komeda_pipeline`h]jB)}(hj)h]hkomeda_pipeline}(hj)hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_pipelineuh1hhhhMhj3)ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj")hhubj)}(hstruct komeda_component { struct drm_private_obj obj; ... } struct komeda_pipeline { struct drm_private_obj obj; ... }h]hstruct komeda_component { struct drm_private_obj obj; ... } struct komeda_pipeline { struct drm_private_obj obj; ... }}hj)sbah}(h]h ]h"]h$]h&]hhforcelanguagejhighlight_args}uh1jhhhMhj")hhubeh}(h]-make-component-pipeline-to-be-drm-private-objah ]h"]-make component/pipeline to be drm_private_objah$]h&]uh1hhj'hhhhhMubh)}(hhh](h)}(h;Tracking component_state/pipeline_state by drm_atomic_stateh]h;Tracking component_state/pipeline_state by drm_atomic_state}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhMubh)}(hmAdd :c:type:`drm_private_state` and user to :c:type:`komeda_component_state`, :c:type:`komeda_pipeline_state`h](hAdd }(hj)hhhNhNubh)}(h:c:type:`drm_private_state`h]jB)}(hj)h]hdrm_private_state}(hj)hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_private_stateuh1hhhhMhj)ubh and user to }(hj)hhhNhNubh)}(h :c:type:`komeda_component_state`h]jB)}(hj)h]hkomeda_component_state}(hj*hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_component_stateuh1hhhhMhj)ubh, }(hj)hhhNhNubh)}(h:c:type:`komeda_pipeline_state`h]jB)}(hj!*h]hkomeda_pipeline_state}(hj#*hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj*ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_pipeline_stateuh1hhhhMhj)ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj)hhubj)}(hstruct komeda_component_state { struct drm_private_state obj; void *binding_user; ... } struct komeda_pipeline_state { struct drm_private_state obj; struct drm_crtc *crtc; ... }h]hstruct komeda_component_state { struct drm_private_state obj; void *binding_user; ... } struct komeda_pipeline_state { struct drm_private_state obj; struct drm_crtc *crtc; ... }}hjD*sbah}(h]h ]h"]h$]h&]hhj)j)jj)}uh1jhhhMhj)hhubeh}(h];tracking-component-state-pipeline-state-by-drm-atomic-stateah ]h"];tracking component_state/pipeline_state by drm_atomic_stateah$]h&]uh1hhj'hhhhhMubh)}(hhh](h)}(hkomeda component validationh]hkomeda component validation}(hj^*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[*hhhhhMubh)}(hzKomeda has multiple types of components, but the process of validation are similar, usually including the following steps:h]hzKomeda has multiple types of components, but the process of validation are similar, usually including the following steps:}(hjl*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[*hhubj)}(hXint komeda_xxxx_validate(struct komeda_component_xxx xxx_comp, struct komeda_component_output *input_dflow, struct drm_plane/crtc/connector *user, struct drm_plane/crtc/connector_state, *user_state) { setup 1: check if component is needed, like the scaler is optional depending on the user_state; if unneeded, just return, and the caller will put the data flow into next stage. Setup 2: check user_state with component features and capabilities to see if requirements can be met; if not, return fail. Setup 3: get component_state from drm_atomic_state, and try set to set user to component; fail if component has been assigned to another user already. Setup 3: configure the component_state, like set its input component, convert user_state to component specific state. Setup 4: adjust the input_dflow and prepare it for the next stage. }h]hXint komeda_xxxx_validate(struct komeda_component_xxx xxx_comp, struct komeda_component_output *input_dflow, struct drm_plane/crtc/connector *user, struct drm_plane/crtc/connector_state, *user_state) { setup 1: check if component is needed, like the scaler is optional depending on the user_state; if unneeded, just return, and the caller will put the data flow into next stage. Setup 2: check user_state with component features and capabilities to see if requirements can be met; if not, return fail. Setup 3: get component_state from drm_atomic_state, and try set to set user to component; fail if component has been assigned to another user already. Setup 3: configure the component_state, like set its input component, convert user_state to component specific state. Setup 4: adjust the input_dflow and prepare it for the next stage. }}hjz*sbah}(h]h ]h"]h$]h&]hhj)j)jj)}uh1jhhhMhj[*hhubeh}(h]komeda-component-validationah ]h"]komeda component validationah$]h&]uh1hhj'hhhhhMubh)}(hhh](h)}(hkomeda_kms Abstractionh]hkomeda_kms Abstraction}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhhhMubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_plane (C struct)c.komeda_planehNtauh1jShj*hhhNhNubjf)}(hhh](jk)}(h komeda_planeh]jq)}(hstruct komeda_planeh](jw)}(hjzh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj*hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*hhhj*hKubj)}(h komeda_planeh]j)}(hj*h]h komeda_plane}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj*hhhj*hKubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj*hhhj*hKubah}(h]j*ah ](jjeh"]h$]h&]jj)jhuh1jjhj*hKhj*hhubj)}(hhh]h)}(hkomeda instance of drm_planeh]hkomeda instance of drm_plane}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj*hhubah}(h]h ]h"]h$]h&]uh1jhj*hhhj*hKubeh}(h]h ](jstructeh"]h$]h&]jjjj+jj+jjjuh1jehhhj*hNhNubj)}(hXM**Definition**:: struct komeda_plane { struct drm_plane base; struct komeda_layer *layer; }; **Members** ``base`` :c:type:`drm_plane` ``layer`` represents available layer input pipelines for this plane. NOTE: the layer is not for a specific Layer, but indicate a group of Layers with same capabilities.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj!+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubh:}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj+ubj)}(hSstruct komeda_plane { struct drm_plane base; struct komeda_layer *layer; };h]hSstruct komeda_plane { struct drm_plane base; struct komeda_layer *layer; };}hj:+sbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj+ubh)}(h **Members**h]j)}(hjK+h]hMembers}(hjM+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI+ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj+ubj1)}(hhh](j6)}(h``base`` :c:type:`drm_plane` h](j<)}(h``base``h]jB)}(hjj+h]hbase}(hjl+hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjh+ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhjd+ubjX)}(hhh]h)}(h:c:type:`drm_plane`h]h)}(hj+h]jB)}(hj+h]h drm_plane}(hj+hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj+ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_planeuh1hhj+hKhj+ubah}(h]h ]h"]h$]h&]uh1hhj+hKhj+ubah}(h]h ]h"]h$]h&]uh1jWhjd+ubeh}(h]h ]h"]h$]h&]uh1j5hj+hKhja+ubj6)}(h``layer`` represents available layer input pipelines for this plane. NOTE: the layer is not for a specific Layer, but indicate a group of Layers with same capabilities.h](j<)}(h ``layer``h]jB)}(hj+h]hlayer}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj+ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj+ubjX)}(hhh](h)}(h:represents available layer input pipelines for this plane.h]h:represents available layer input pipelines for this plane.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj+ubh)}(hcNOTE: the layer is not for a specific Layer, but indicate a group of Layers with same capabilities.h]hcNOTE: the layer is not for a specific Layer, but indicate a group of Layers with same capabilities.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj+ubeh}(h]h ]h"]h$]h&]uh1jWhj+ubeh}(h]h ]h"]h$]h&]uh1j5hj+hKhja+ubeh}(h]h ]h"]h$]h&]uh1j0hj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj*hhhNhNubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_plane_state (C struct)c.komeda_plane_statehNtauh1jShj*hhhNhNubjf)}(hhh](jk)}(hkomeda_plane_stateh]jq)}(hstruct komeda_plane_stateh](jw)}(hjzh]hstruct}(hj&,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj",hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK$ubj)}(h h]h }(hj4,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj",hhhj3,hK$ubj)}(hkomeda_plane_stateh]j)}(hj ,h]hkomeda_plane_state}(hjF,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjB,ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj",hhhj3,hK$ubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj,hhhj3,hK$ubah}(h]j,ah ](jjeh"]h$]h&]jj)jhuh1jjhj3,hK$hj,hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj,hhhj3,hK$ubeh}(h]h ](jstructeh"]h$]h&]jjjjq,jjq,jjjuh1jehhhj*hNhNubj)}(hX**Definition**:: struct komeda_plane_state { struct drm_plane_state base; struct list_head zlist_node; u8 layer_split : 1; }; **Members** ``base`` :c:type:`drm_plane_state` ``zlist_node`` zorder list node ``layer_split`` on/off layer_splith](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj},hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy,ubh:}(hjy,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK(hju,ubj)}(hxstruct komeda_plane_state { struct drm_plane_state base; struct list_head zlist_node; u8 layer_split : 1; };h]hxstruct komeda_plane_state { struct drm_plane_state base; struct list_head zlist_node; u8 layer_split : 1; };}hj,sbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK*hju,ubh)}(h **Members**h]j)}(hj,h]hMembers}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK0hju,ubj1)}(hhh](j6)}(h#``base`` :c:type:`drm_plane_state` h](j<)}(h``base``h]jB)}(hj,h]hbase}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj,ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK+hj,ubjX)}(hhh]h)}(h:c:type:`drm_plane_state`h]h)}(hj,h]jB)}(hj,h]hdrm_plane_state}(hj,hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj,ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_plane_stateuh1hhj,hK+hj,ubah}(h]h ]h"]h$]h&]uh1hhj,hK+hj,ubah}(h]h ]h"]h$]h&]uh1jWhj,ubeh}(h]h ]h"]h$]h&]uh1j5hj,hK+hj,ubj6)}(h ``zlist_node`` zorder list node h](j<)}(h``zlist_node``h]jB)}(hj-h]h zlist_node}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj-ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj-ubjX)}(hhh]h)}(hzorder list nodeh]hzorder list node}(hj2-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.-hKhj/-ubah}(h]h ]h"]h$]h&]uh1jWhj-ubeh}(h]h ]h"]h$]h&]uh1j5hj.-hKhj,ubj6)}(h"``layer_split`` on/off layer_splith](j<)}(h``layer_split``h]jB)}(hjR-h]h layer_split}(hjT-hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjP-ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhjL-ubjX)}(hhh]h)}(hon/off layer_splith]hon/off layer_split}(hjk-hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhjh-ubah}(h]h ]h"]h$]h&]uh1jWhjL-ubeh}(h]h ]h"]h$]h&]uh1j5hjg-hKhj,ubeh}(h]h ]h"]h$]h&]uh1j0hju,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj*hhhNhNubh)}(h**Description**h]j)}(hj-h]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj*hhubh)}(hThe plane_state can be split into two data flow (left/right) and handled by two layers :c:type:`komeda_plane.layer ` and :c:type:`komeda_plane.layer `.righth](hWThe plane_state can be split into two data flow (left/right) and handled by two layers }(hj-hhhNhNubh)}(h+:c:type:`komeda_plane.layer `h]jB)}(hj-h]hkomeda_plane.layer}(hj-hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_planeuh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK&hj-ubh and }(hj-hhhNhNubh)}(h+:c:type:`komeda_plane.layer `h]jB)}(hj-h]hkomeda_plane.layer}(hj-hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j komeda_planeuh1hhj-hK&hj-ubh.right}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj-hK&hj*hhubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_wb_connector (C struct)c.komeda_wb_connectorhNtauh1jShj*hhhNhNubjf)}(hhh](jk)}(hkomeda_wb_connectorh]jq)}(hstruct komeda_wb_connectorh](jw)}(hjzh]hstruct}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj.hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK,ubj)}(h h]h }(hj'.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hhhj&.hK,ubj)}(hkomeda_wb_connectorh]j)}(hj.h]hkomeda_wb_connector}(hj9.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5.ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj.hhhj&.hK,ubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj.hhhj&.hK,ubah}(h]j .ah ](jjeh"]h$]h&]jj)jhuh1jjhj&.hK,hj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj.hhhj&.hK,ubeh}(h]h ](jstructeh"]h$]h&]jjjjd.jjd.jjjuh1jehhhj*hNhNubj)}(hX**Definition**:: struct komeda_wb_connector { struct drm_writeback_connector base; struct komeda_layer *wb_layer; }; **Members** ``base`` :c:type:`drm_writeback_connector` ``wb_layer`` represents associated writeback pipeline of komedah](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjp.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl.ubh:}(hjl.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK8hjh.ubj)}(hkstruct komeda_wb_connector { struct drm_writeback_connector base; struct komeda_layer *wb_layer; };h]hkstruct komeda_wb_connector { struct drm_writeback_connector base; struct komeda_layer *wb_layer; };}hj.sbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK:hjh.ubh)}(h **Members**h]j)}(hj.h]hMembers}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK?hjh.ubj1)}(hhh](j6)}(h+``base`` :c:type:`drm_writeback_connector` h](j<)}(h``base``h]jB)}(hj.h]hbase}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj.ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK8hj.ubjX)}(hhh]h)}(h!:c:type:`drm_writeback_connector`h]h)}(hj.h]jB)}(hj.h]hdrm_writeback_connector}(hj.hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_writeback_connectoruh1hhj.hK8hj.ubah}(h]h ]h"]h$]h&]uh1hhj.hK8hj.ubah}(h]h ]h"]h$]h&]uh1jWhj.ubeh}(h]h ]h"]h$]h&]uh1j5hj.hK8hj.ubj6)}(h?``wb_layer`` represents associated writeback pipeline of komedah](j<)}(h ``wb_layer``h]jB)}(hj /h]hwb_layer}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj /ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj/ubjX)}(hhh]h)}(h2represents associated writeback pipeline of komedah]h2represents associated writeback pipeline of komeda}(hj%/hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj"/ubah}(h]h ]h"]h$]h&]uh1jWhj/ubeh}(h]h ]h"]h$]h&]uh1j5hj!/hKhj.ubeh}(h]h ]h"]h$]h&]uh1j0hjh.ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj*hhhNhNubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_crtc (C struct) c.komeda_crtchNtauh1jShj*hhhNhNubjf)}(hhh](jk)}(h komeda_crtch]jq)}(hstruct komeda_crtch](jw)}(hjzh]hstruct}(hjf/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhjb/hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKubj)}(h h]h }(hjt/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjb/hhhjs/hKubj)}(h komeda_crtch]j)}(hj`/h]h komeda_crtc}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjb/hhhjs/hKubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj^/hhhjs/hKubah}(h]jY/ah ](jjeh"]h$]h&]jj)jhuh1jjhjs/hKhj[/hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj[/hhhjs/hKubeh}(h]h ](jstructeh"]h$]h&]jjjj/jj/jjjuh1jehhhj*hNhNubj)}(hX**Definition**:: struct komeda_crtc { struct drm_crtc base; struct komeda_pipeline *master; struct komeda_pipeline *slave; u32 slave_planes; struct komeda_wb_connector *wb_conn; struct completion *disable_done; struct drm_encoder encoder; }; **Members** ``base`` :c:type:`drm_crtc` ``master`` only master has display output ``slave`` optional Doesn't have its own display output, the handled data flow will merge into the master. ``slave_planes`` komeda slave planes mask ``wb_conn`` komeda write back connector ``disable_done`` this flip_done is for tracing the disable ``encoder`` encoder at the end of the pipelineh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubh:}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKChj/ubj)}(hstruct komeda_crtc { struct drm_crtc base; struct komeda_pipeline *master; struct komeda_pipeline *slave; u32 slave_planes; struct komeda_wb_connector *wb_conn; struct completion *disable_done; struct drm_encoder encoder; };h]hstruct komeda_crtc { struct drm_crtc base; struct komeda_pipeline *master; struct komeda_pipeline *slave; u32 slave_planes; struct komeda_wb_connector *wb_conn; struct completion *disable_done; struct drm_encoder encoder; };}hj/sbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKEhj/ubh)}(h **Members**h]j)}(hj/h]hMembers}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKOhj/ubj1)}(hhh](j6)}(h``base`` :c:type:`drm_crtc` h](j<)}(h``base``h]jB)}(hj0h]hbase}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj0ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKChj0ubjX)}(hhh]h)}(h:c:type:`drm_crtc`h]h)}(hj!0h]jB)}(hj!0h]hdrm_crtc}(hj&0hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj#0ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_crtcuh1hhj0hKChj0ubah}(h]h ]h"]h$]h&]uh1hhj0hKChj0ubah}(h]h ]h"]h$]h&]uh1jWhj0ubeh}(h]h ]h"]h$]h&]uh1j5hj0hKChj/ubj6)}(h*``master`` only master has display output h](j<)}(h ``master``h]jB)}(hjY0h]hmaster}(hj[0hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjW0ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhjS0ubjX)}(hhh]h)}(honly master has display outputh]honly master has display output}(hjr0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn0hKhjo0ubah}(h]h ]h"]h$]h&]uh1jWhjS0ubeh}(h]h ]h"]h$]h&]uh1j5hjn0hKhj/ubj6)}(hk``slave`` optional Doesn't have its own display output, the handled data flow will merge into the master. h](j<)}(h ``slave``h]jB)}(hj0h]hslave}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj0ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKLhj0ubjX)}(hhh](h)}(hoptionalh]hoptional}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKIhj0ubh)}(hVDoesn't have its own display output, the handled data flow will merge into the master.h]hXDoesn’t have its own display output, the handled data flow will merge into the master.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKKhj0ubeh}(h]h ]h"]h$]h&]uh1jWhj0ubeh}(h]h ]h"]h$]h&]uh1j5hj0hKLhj/ubj6)}(h*``slave_planes`` komeda slave planes mask h](j<)}(h``slave_planes``h]jB)}(hj0h]h slave_planes}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj0ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj0ubjX)}(hhh]h)}(hkomeda slave planes maskh]hkomeda slave planes mask}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hKhj0ubah}(h]h ]h"]h$]h&]uh1jWhj0ubeh}(h]h ]h"]h$]h&]uh1j5hj0hKhj/ubj6)}(h(``wb_conn`` komeda write back connector h](j<)}(h ``wb_conn``h]jB)}(hj1h]hwb_conn}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj1ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj1ubjX)}(hhh]h)}(hkomeda write back connectorh]hkomeda write back connector}(hj-1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)1hKhj*1ubah}(h]h ]h"]h$]h&]uh1jWhj1ubeh}(h]h ]h"]h$]h&]uh1j5hj)1hKhj/ubj6)}(h;``disable_done`` this flip_done is for tracing the disable h](j<)}(h``disable_done``h]jB)}(hjM1h]h disable_done}(hjO1hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjK1ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhjG1ubjX)}(hhh]h)}(h)this flip_done is for tracing the disableh]h)this flip_done is for tracing the disable}(hjf1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb1hKhjc1ubah}(h]h ]h"]h$]h&]uh1jWhjG1ubeh}(h]h ]h"]h$]h&]uh1j5hjb1hKhj/ubj6)}(h.``encoder`` encoder at the end of the pipelineh](j<)}(h ``encoder``h]jB)}(hj1h]hencoder}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj1ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj1ubjX)}(hhh]h)}(h"encoder at the end of the pipelineh]h"encoder at the end of the pipeline}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj1ubah}(h]h ]h"]h$]h&]uh1jWhj1ubeh}(h]h ]h"]h$]h&]uh1j5hj1hOdKhj/ubeh}(h]h ]h"]h$]h&]uh1j0hj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj*hhhNhNubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`komeda_crtc_state (C struct)c.komeda_crtc_statehNtauh1jShj*hhhNhNubjf)}(hhh](jk)}(hkomeda_crtc_stateh]jq)}(hstruct komeda_crtc_stateh](jw)}(hjzh]hstruct}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj1hhho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKubj)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhj1hKubj)}(hkomeda_crtc_stateh]j)}(hj1h]hkomeda_crtc_state}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj1hhhj1hKubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj1hhhj1hKubah}(h]j1ah ](jjeh"]h$]h&]jj)jhuh1jjhj1hKhj1hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj1hhhj1hKubeh}(h]h ](jstructeh"]h$]h&]jjjj+2jj+2jjjuh1jehhhj*hNhNubj)}(hX**Definition**:: struct komeda_crtc_state { struct drm_crtc_state base; u32 affected_pipes; u32 active_pipes; u64 clock_ratio; u32 max_slave_zorder; }; **Members** ``base`` :c:type:`drm_crtc_state` ``affected_pipes`` the affected pipelines in once display instance ``active_pipes`` the active pipelines in once display instance ``clock_ratio`` ratio of (aclk << 32)/pxlclk ``max_slave_zorder`` the maximum of slave zorderh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj72hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj32ubh:}(hj32hhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK`hj/2ubj)}(hstruct komeda_crtc_state { struct drm_crtc_state base; u32 affected_pipes; u32 active_pipes; u64 clock_ratio; u32 max_slave_zorder; };h]hstruct komeda_crtc_state { struct drm_crtc_state base; u32 affected_pipes; u32 active_pipes; u64 clock_ratio; u32 max_slave_zorder; };}hjP2sbah}(h]h ]h"]h$]h&]hhuh1jho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKbhj/2ubh)}(h **Members**h]j)}(hja2h]hMembers}(hjc2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_2ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKjhj/2ubj1)}(hhh](j6)}(h"``base`` :c:type:`drm_crtc_state` h](j<)}(h``base``h]jB)}(hj2h]hbase}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj~2ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhK`hjz2ubjX)}(hhh]h)}(h:c:type:`drm_crtc_state`h]h)}(hj2h]jB)}(hj2h]hdrm_crtc_state}(hj2hhhNhNubah}(h]h ](jz jc-typeeh"]h$]h&]uh1jAhj2ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj j j drm_crtc_stateuh1hhj2hK`hj2ubah}(h]h ]h"]h$]h&]uh1hhj2hK`hj2ubah}(h]h ]h"]h$]h&]uh1jWhjz2ubeh}(h]h ]h"]h$]h&]uh1j5hj2hK`hjw2ubj6)}(hC``affected_pipes`` the affected pipelines in once display instance h](j<)}(h``affected_pipes``h]jB)}(hj2h]haffected_pipes}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj2ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhhj2ubjX)}(hhh]h)}(h/the affected pipelines in once display instanceh]h/the affected pipelines in once display instance}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hKhhj2ubah}(h]h ]h"]h$]h&]uh1jWhj2ubeh}(h]h ]h"]h$]h&]uh1j5hj2hKhhjw2ubj6)}(h?``active_pipes`` the active pipelines in once display instance h](j<)}(h``active_pipes``h]jB)}(hj 3h]h active_pipes}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj 3ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKmhj3ubjX)}(hhh]h)}(h-the active pipelines in once display instanceh]h-the active pipelines in once display instance}(hj%3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!3hKmhj"3ubah}(h]h ]h"]h$]h&]uh1jWhj3ubeh}(h]h ]h"]h$]h&]uh1j5hj!3hKmhjw2ubj6)}(h-``clock_ratio`` ratio of (aclk << 32)/pxlclk h](j<)}(h``clock_ratio``h]jB)}(hjE3h]h clock_ratio}(hjG3hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjC3ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj?3ubjX)}(hhh]h)}(hratio of (aclk << 32)/pxlclkh]hratio of (aclk << 32)/pxlclk}(hj^3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ3hKhj[3ubah}(h]h ]h"]h$]h&]uh1jWhj?3ubeh}(h]h ]h"]h$]h&]uh1j5hjZ3hKhjw2ubj6)}(h0``max_slave_zorder`` the maximum of slave zorderh](j<)}(h``max_slave_zorder``h]jB)}(hj~3h]hmax_slave_zorder}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj|3ubah}(h]h ]h"]h$]h&]uh1j;ho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhjx3ubjX)}(hhh]h)}(hthe maximum of slave zorderh]hthe maximum of slave zorder}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:468: ./drivers/gpu/drm/arm/display/komeda/komeda_kms.hhKhj3ubah}(h]h ]h"]h$]h&]uh1jWhjx3ubeh}(h]h ]h"]h$]h&]uh1j5hj3hKhjw2ubeh}(h]h ]h"]h$]h&]uh1j0hj/2ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj*hhhNhNubeh}(h]komeda-kms-abstractionah ]h"]komeda_kms abstractionah$]h&]uh1hhj'hhhhhMubh)}(hhh](h)}(hkomde_kms Functionsh]hkomde_kms Functions}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhhhMubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`%komeda_crtc_atomic_check (C function)c.komeda_crtc_atomic_checkhNtauh1jShj3hhhNhNubjf)}(hhh](jk)}(hTint komeda_crtc_atomic_check (struct drm_crtc *crtc, struct drm_atomic_state *state)h]jq)}(hSint komeda_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)h](hdesc_sig_keyword_type)}(hinth]hint}(hj3hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j3hj3hhhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKLubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3hhhj4hKLubj)}(hkomeda_crtc_atomic_checkh]j)}(hkomeda_crtc_atomic_checkh]hkomeda_crtc_atomic_check}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj3hhhj4hKLubhdesc_parameterlist)}(h7(struct drm_crtc *crtc, struct drm_atomic_state *state)h](hdesc_parameter)}(hstruct drm_crtc *crtch](jw)}(hjzh]hstruct}(hj54hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj14ubj)}(h h]h }(hjB4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj14ubh)}(hhh]j)}(hdrm_crtch]hdrm_crtc}(hjS4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP4ubah}(h]h ]h"]h$]h&] refdomainjreftype identifier reftargetjU4modnameN classnameNj j )}j ]j ASTIdentifier)}ji4j4sbc.komeda_crtc_atomic_checkasbuh1hhj14ubj)}(h h]h }(hjv4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj14ubhdesc_sig_punctuation)}(h*h]h*}(hj4hhhNhNubah}(h]h ]pah"]h$]h&]uh1j4hj14ubj)}(hcrtch]hcrtc}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj14ubeh}(h]h ]h"]h$]h&]noemphhhuh1j/4hj+4ubj04)}(hstruct drm_atomic_state *stateh](jw)}(hjzh]hstruct}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj4ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubh)}(hhh]j)}(hdrm_atomic_stateh]hdrm_atomic_state}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&] refdomainjreftypeji4 reftargetj4modnameN classnameNj j )}j ]jr4c.komeda_crtc_atomic_checkasbuh1hhj4ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj4)}(hj4h]h*}(hj4hhhNhNubah}(h]h ]j4ah"]h$]h&]uh1j4hj4ubj)}(hstateh]hstate}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]noemphhhuh1j/4hj+4ubeh}(h]h ]h"]h$]h&]hhuh1j)4hj3hhhj4hKLubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhj3hhhj4hKLubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1jjhj4hKLhj3hhubj)}(hhh]h)}(hbuild display output data flowh]hbuild display output data flow}(hj/5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKAhj,5hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj4hKLubeh}(h]h ](jfunctioneh"]h$]h&]jjjjG5jjG5jjjuh1jehhhj3hNhNubj)}(hXc**Parameters** ``struct drm_crtc *crtc`` DRM crtc ``struct drm_atomic_state *state`` the crtc state object **Description** crtc_atomic_check is the final check stage, so beside build a display data pipeline according to the crtc_state, but still needs to release or disable the unclaimed pipeline resources. **Return** Zero for success or -errnoh](h)}(h**Parameters**h]j)}(hjQ5h]h Parameters}(hjS5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjO5ubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKEhjK5ubj1)}(hhh](j6)}(h#``struct drm_crtc *crtc`` DRM crtc h](j<)}(h``struct drm_crtc *crtc``h]jB)}(hjp5h]hstruct drm_crtc *crtc}(hjr5hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjn5ubah}(h]h ]h"]h$]h&]uh1j;hp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKBhjj5ubjX)}(hhh]h)}(hDRM crtch]hDRM crtc}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hKBhj5ubah}(h]h ]h"]h$]h&]uh1jWhjj5ubeh}(h]h ]h"]h$]h&]uh1j5hj5hKBhjg5ubj6)}(h9``struct drm_atomic_state *state`` the crtc state object h](j<)}(h"``struct drm_atomic_state *state``h]jB)}(hj5h]hstruct drm_atomic_state *state}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj5ubah}(h]h ]h"]h$]h&]uh1j;hp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKChj5ubjX)}(hhh]h)}(hthe crtc state objecth]hthe crtc state object}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hKChj5ubah}(h]h ]h"]h$]h&]uh1jWhj5ubeh}(h]h ]h"]h$]h&]uh1j5hj5hKChjg5ubeh}(h]h ]h"]h$]h&]uh1j0hjK5ubh)}(h**Description**h]j)}(hj5h]h Description}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKEhjK5ubh)}(hcrtc_atomic_check is the final check stage, so beside build a display data pipeline according to the crtc_state, but still needs to release or disable the unclaimed pipeline resources.h]hcrtc_atomic_check is the final check stage, so beside build a display data pipeline according to the crtc_state, but still needs to release or disable the unclaimed pipeline resources.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKEhjK5ubh)}(h **Return**h]j)}(hj 6h]hReturn}(hj 6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 6ubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKIhjK5ubh)}(hZero for success or -errnoh]hZero for success or -errno}(hj!6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:473: ./drivers/gpu/drm/arm/display/komeda/komeda_crtc.chKIhjK5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj3hhhNhNubjT)}(hhh]h}(h]h ]h"]h$]h&]entries](j`&komeda_plane_atomic_check (C function)c.komeda_plane_atomic_checkhNtauh1jShj3hhhNhNubjf)}(hhh](jk)}(hWint komeda_plane_atomic_check (struct drm_plane *plane, struct drm_atomic_state *state)h]jq)}(hVint komeda_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state)h](j3)}(hinth]hint}(hjP6hhhNhNubah}(h]h ]j3ah"]h$]h&]uh1j3hjL6hhhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKFubj)}(h h]h }(hj_6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL6hhhj^6hKFubj)}(hkomeda_plane_atomic_checkh]j)}(hkomeda_plane_atomic_checkh]hkomeda_plane_atomic_check}(hjq6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm6ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjL6hhhj^6hKFubj*4)}(h9(struct drm_plane *plane, struct drm_atomic_state *state)h](j04)}(hstruct drm_plane *planeh](jw)}(hjzh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubh)}(hhh]j)}(h drm_planeh]h drm_plane}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&] refdomainjreftypeji4 reftargetj6modnameN classnameNj j )}j ]jq4)}ji4js6sbc.komeda_plane_atomic_checkasbuh1hhj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj4)}(hj4h]h*}(hj6hhhNhNubah}(h]h ]j4ah"]h$]h&]uh1j4hj6ubj)}(hplaneh]hplane}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]noemphhhuh1j/4hj6ubj04)}(hstruct drm_atomic_state *stateh](jw)}(hjzh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jvhj6ubj)}(h h]h }(hj 7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubh)}(hhh]j)}(hdrm_atomic_stateh]hdrm_atomic_state}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&] refdomainjreftypeji4 reftargetj7modnameN classnameNj j )}j ]j6c.komeda_plane_atomic_checkasbuh1hhj6ubj)}(h h]h }(hj;7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj4)}(hj4h]h*}(hjI7hhhNhNubah}(h]h ]j4ah"]h$]h&]uh1j4hj6ubj)}(hstateh]hstate}(hjV7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]noemphhhuh1j/4hj6ubeh}(h]h ]h"]h$]h&]hhuh1j)4hjL6hhhj^6hKFubeh}(h]h ]h"]h$]h&]hhjuh1jpjjhjH6hhhj^6hKFubah}(h]jC6ah ](jjeh"]h$]h&]jj)jhuh1jjhj^6hKFhjE6hhubj)}(hhh]h)}(hbuild input data flowh]hbuild input data flow}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chK?hj}7hhubah}(h]h ]h"]h$]h&]uh1jhjE6hhhj^6hKFubeh}(h]h ](jfunctioneh"]h$]h&]jjjj7jj7jjjuh1jehhhj3hNhNubj)}(h**Parameters** ``struct drm_plane *plane`` DRM plane ``struct drm_atomic_state *state`` the plane state object **Return** Zero for success or -errnoh](h)}(h**Parameters**h]j)}(hj7h]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKChj7ubj1)}(hhh](j6)}(h&``struct drm_plane *plane`` DRM plane h](j<)}(h``struct drm_plane *plane``h]jB)}(hj7h]hstruct drm_plane *plane}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj7ubah}(h]h ]h"]h$]h&]uh1j;hq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chK@hj7ubjX)}(hhh]h)}(h DRM planeh]h DRM plane}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hK@hj7ubah}(h]h ]h"]h$]h&]uh1jWhj7ubeh}(h]h ]h"]h$]h&]uh1j5hj7hK@hj7ubj6)}(h:``struct drm_atomic_state *state`` the plane state object h](j<)}(h"``struct drm_atomic_state *state``h]jB)}(hj7h]hstruct drm_atomic_state *state}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj7ubah}(h]h ]h"]h$]h&]uh1j;hq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKAhj7ubjX)}(hhh]h)}(hthe plane state objecth]hthe plane state object}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hKAhj8ubah}(h]h ]h"]h$]h&]uh1jWhj7ubeh}(h]h ]h"]h$]h&]uh1j5hj8hKAhj7ubeh}(h]h ]h"]h$]h&]uh1j0hj7ubh)}(h **Return**h]j)}(hj58h]hReturn}(hj78hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj38ubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKChj7ubh)}(hZero for success or -errnoh]hZero for success or -errno}(hjK8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/komeda-kms:475: ./drivers/gpu/drm/arm/display/komeda/komeda_plane.chKChj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj3hhhNhNubeh}(h]komde-kms-functionsah ]h"]komde_kms functionsah$]h&]uh1hhj'hhhhhMubeh}(h]attach-komeda-dev-to-drm-kmsah ]h"]attach komeda_dev to drm-kmsah$]h&]uh1hhhhhhhhM_ubh)}(hhh](h)}(h(Build komeda to be a Linux module driverh]h(Build komeda to be a Linux module driver}(hjt8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjq8hhhhhMubh)}(hNow we have two level devices:h]hNow we have two level devices:}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjq8hhubjf)}(hhh](jk)}(h0komeda_dev: describes the real display hardware.h]h)}(hj8h]h0komeda_dev: describes the real display hardware.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jjhj8hhhhhNubjk)}(h