gsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget)/translations/zh_CN/gpu/intel-display/psrmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/zh_TW/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/it_IT/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ja_JP/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ko_KR/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/pt_BR/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/sp_SP/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhC/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(h Panel Self Refresh PSR (PSR/SRD)h]h Panel Self Refresh PSR (PSR/SRD)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXSince Haswell Display controller supports Panel Self-Refresh on display panels witch have a remote frame buffer (RFB) implemented according to PSR spec in eDP1.3. PSR feature allows the display to go to lower standby states when system is idle but display is on as it eliminates display refresh request to DDR memory completely as long as the frame buffer for that display is unchanged.h]hXSince Haswell Display controller supports Panel Self-Refresh on display panels witch have a remote frame buffer (RFB) implemented according to PSR spec in eDP1.3. PSR feature allows the display to go to lower standby states when system is idle but display is on as it eliminates display refresh request to DDR memory completely as long as the frame buffer for that display is unchanged.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chK?hhhhubh)}(hPPanel Self Refresh must be supported by both Hardware (source) and Panel (sink).h]hPPanel Self Refresh must be supported by both Hardware (source) and Panel (sink).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chKFhhhhubh)}(hPSR saves power by caching the framebuffer in the panel RFB, which allows us to power down the link and memory controller. For DSI panels the same idea is called "manual mode".h]hPSR saves power by caching the framebuffer in the panel RFB, which allows us to power down the link and memory controller. For DSI panels the same idea is called “manual mode”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chKIhhhhubh)}(hXThe implementation uses the hardware-based PSR support which automatically enters/exits self-refresh mode. The hardware takes care of sending the required DP aux message and could even retrain the link (that part isn't enabled yet though). The hardware also keeps track of any frontbuffer changes to know when to exit self-refresh mode again. Unfortunately that part doesn't work too well, hence why the i915 PSR support uses the software frontbuffer tracking to make sure it doesn't miss a screen update. For this integration intel_psr_invalidate() and intel_psr_flush() get called by the frontbuffer tracking code. Note that because of locking issues the self-refresh re-enable code is done from a work queue, which must be correctly synchronized/cancelled when shutting down the pipe."h]hXThe implementation uses the hardware-based PSR support which automatically enters/exits self-refresh mode. The hardware takes care of sending the required DP aux message and could even retrain the link (that part isn’t enabled yet though). The hardware also keeps track of any frontbuffer changes to know when to exit self-refresh mode again. Unfortunately that part doesn’t work too well, hence why the i915 PSR support uses the software frontbuffer tracking to make sure it doesn’t miss a screen update. For this integration intel_psr_invalidate() and intel_psr_flush() get called by the frontbuffer tracking code. Note that because of locking issues the self-refresh re-enable code is done from a work queue, which must be correctly synchronized/cancelled when shutting down the pipe.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chKMhhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleintel_psr_disable (C function)c.intel_psr_disablehNtauh1j)hhhhhNhNubhdesc)}(hhh](hdesc_signature)}(havoid intel_psr_disable (struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h]hdesc_signature_line)}(h`void intel_psr_disable(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjMhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jKhjGhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM\ ubhdesc_sig_space)}(h h]h }(hj_hhhNhNubah}(h]h ]wah"]h$]h&]uh1j]hjGhhhj\hM\ ubh desc_name)}(hintel_psr_disableh]h desc_sig_name)}(hintel_psr_disableh]hintel_psr_disable}(hjvhhhNhNubah}(h]h ]nah"]h$]h&]uh1jthjpubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jnhjGhhhj\hM\ ubhdesc_parameterlist)}(hJ(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h](hdesc_parameter)}(hstruct intel_dp *intel_dph](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jjxsbc.intel_psr_disableasbuh1hhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhjubju)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h-const struct intel_crtc_state *old_crtc_stateh](j)}(hconsth]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hj*hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjEhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(hintel_crtc_stateh]hintel_crtc_state}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjSubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjXmodnameN classnameNjj)}j]jc.intel_psr_disableasbuh1hhjubj^)}(h h]h }(hjthhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(hold_crtc_stateh]hold_crtc_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjGhhhj\hM\ ubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1jEsphinx_line_type declaratorhjAhhhj\hM\ ubah}(h]j8ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j?hj\hM\ hj<hhubh desc_content)}(hhh]h)}(h Disable PSRh]h Disable PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM\ hjhhubah}(h]h ]h"]h$]h&]uh1jhj<hhhj\hM\ ubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j:hhhhhNhNubh container)}(h**Parameters** ``struct intel_dp *intel_dp`` Intel DP ``const struct intel_crtc_state *old_crtc_state`` old CRTC state **Description** This function needs to be called before disabling pipe.h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM` hjubhdefinition_list)}(hhh](hdefinition_list_item)}(h'``struct intel_dp *intel_dp`` Intel DP h](hterm)}(h``struct intel_dp *intel_dp``h]hliteral)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM] hj ubh definition)}(hhh]h)}(hIntel DPh]hIntel DP}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hM] hj.ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj+hM] hjubj )}(hA``const struct intel_crtc_state *old_crtc_state`` old CRTC state h](j)}(h1``const struct intel_crtc_state *old_crtc_state``h]j)}(hjQh]h-const struct intel_crtc_state *old_crtc_state}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM^ hjKubj-)}(hhh]h)}(hold CRTC stateh]hold CRTC state}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhM^ hjgubah}(h]h ]h"]h$]h&]uh1j,hjKubeh}(h]h ]h"]h$]h&]uh1j hjfhM^ hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM` hjubh)}(h7This function needs to be called before disabling pipe.h]h7This function needs to be called before disabling pipe.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM_ hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6intel_psr_pause (C function)c.intel_psr_pausehNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(h0void intel_psr_pause (struct intel_dp *intel_dp)h]jF)}(h/void intel_psr_pause(struct intel_dp *intel_dp)h](jL)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMz ubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhjhMz ubjo)}(hintel_psr_pauseh]ju)}(hintel_psr_pauseh]hintel_psr_pause}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhjhMz ubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubh)}(hhh]ju)}(hintel_dph]hintel_dp}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj.modnameN classnameNjj)}j]j)}jjsbc.intel_psr_pauseasbuh1hhj ubj^)}(h h]h }(hjLhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]h*}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubju)}(hintel_dph]hintel_dp}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMz ubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjhhhjhMz ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hjhMz hjhhubj)}(hhh]h)}(h Pause PSRh]h Pause PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMz hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMz ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(h~**Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function need to be called after enabling psr.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM~ hjubj)}(hhh]j )}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM{ hjubj-)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM{ hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM{ hjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM} hjubh)}(h3This function need to be called after enabling psr.h]h3This function need to be called after enabling psr.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM| hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6intel_psr_resume (C function)c.intel_psr_resumehNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(h1void intel_psr_resume (struct intel_dp *intel_dp)h]jF)}(h0void intel_psr_resume(struct intel_dp *intel_dp)h](jL)}(hvoidh]hvoid}(hjRhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjNhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj^)}(h h]h }(hjahhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjNhhhj`hM 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./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjGhhhj`hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj*jj*jjjuh1j:hhhhhNhNubj)}(h}**Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function need to be called after pausing psr.h](h)}(h**Parameters**h]j)}(hj4h]h Parameters}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj.ubj)}(hhh]j )}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjSh]hstruct intel_dp *intel_dp}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjMubj-)}(hhh]h)}(hIntel DPh]hIntel DP}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhM hjiubah}(h]h ]h"]h$]h&]uh1j,hjMubeh}(h]h ]h"]h$]h&]uh1j hjhhM hjJubah}(h]h ]h"]h$]h&]uh1jhj.ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj.ubh)}(h2This function need to be called after pausing psr.h]h2This function need to be called after pausing psr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj.ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j60intel_psr_needs_vblank_notification (C function)%c.intel_psr_needs_vblank_notificationhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hTbool intel_psr_needs_vblank_notification (const struct intel_crtc_state *crtc_state)h]jF)}(hSbool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state)h](jL)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhjhM ubjo)}(h#intel_psr_needs_vblank_notificationh]ju)}(h#intel_psr_needs_vblank_notificationh]h#intel_psr_needs_vblank_notification}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhjhM ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]hstruct}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hj8hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubh)}(hhh]ju)}(hintel_crtc_stateh]hintel_crtc_state}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjFubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjKmodnameN classnameNjj)}j]j)}jjsb%c.intel_psr_needs_vblank_notificationasbuh1hhj ubj^)}(h h]h }(hjihhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]h*}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubju)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hjhM hjhhubj)}(hhh]h)}(h5Check if PSR need vblank enable/disable notification.h]h5Check if PSR need vblank enable/disable notification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(hX**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC status **Description** We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events. Also Wa_16025596647 needs information when vblank is enabled/disabled.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj)}(hhh]j )}(h:``const struct intel_crtc_state *crtc_state`` CRTC status h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj-)}(hhh]h)}(h CRTC statush]h CRTC status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj*h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hXNWe need to block DC6 entry in case of Panel Replay as enabling VBI doesn't prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events. Also Wa_16025596647 needs information when vblank is enabled/disabled.h]hXPWe need to block DC6 entry in case of Panel Replay as enabling VBI doesn’t prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events. Also Wa_16025596647 needs information when vblank is enabled/disabled.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j61intel_psr_trigger_frame_change_event (C function)&c.intel_psr_trigger_frame_change_eventhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(h|void intel_psr_trigger_frame_change_event (struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h]jF)}(h{void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h](jL)}(hvoidh]hvoid}(hjohhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjkhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj^)}(h h]h }(hj~hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjkhhhj}hM ubjo)}(h$intel_psr_trigger_frame_change_eventh]ju)}(h$intel_psr_trigger_frame_change_eventh]h$intel_psr_trigger_frame_change_event}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjkhhhj}hM ubj)}(hR(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(h intel_dsbh]h intel_dsb}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb&c.intel_psr_trigger_frame_change_eventasbuh1hhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(hdsbh]hdsb}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hj+ hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubh)}(hhh]ju)}(hintel_atomic_stateh]hintel_atomic_state}(hj< hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj9 ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj> modnameN classnameNjj)}j]j&c.intel_psr_trigger_frame_change_eventasbuh1hhj ubj^)}(h h]h }(hjZ hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]h*}(hjh hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubju)}(hstateh]hstate}(hju hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubh)}(hhh]ju)}(h intel_crtch]h intel_crtc}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j&c.intel_psr_trigger_frame_change_eventasbuh1hhj ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubju)}(hcrtch]hcrtc}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjkhhhj}hM ubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjghhhj}hM ubah}(h]jbah ](jjeh"]h$]h&]jj)jhuh1j?hj}hM hjdhhubj)}(hhh]h)}(hTrigger "Frame Change" eventh]h Trigger “Frame Change” event}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj hhubah}(h]h ]h"]h$]h&]uh1jhjdhhhj}hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj' jj' jjjuh1j:hhhhhNhNubj)}(h**Parameters** ``struct intel_dsb *dsb`` DSB context ``struct intel_atomic_state *state`` the atomic state ``struct intel_crtc *crtc`` the CRTC **Description** Generate PSR "Frame Change" event.h](h)}(h**Parameters**h]j)}(hj1 h]h Parameters}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj+ ubj)}(hhh](j )}(h&``struct intel_dsb *dsb`` DSB context h](j)}(h``struct intel_dsb *dsb``h]j)}(hjP h]hstruct intel_dsb *dsb}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjJ ubj-)}(hhh]h)}(h DSB contexth]h DSB context}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1hhje hM hjf ubah}(h]h ]h"]h$]h&]uh1j,hjJ ubeh}(h]h ]h"]h$]h&]uh1j hje hM hjG ubj )}(h6``struct intel_atomic_state *state`` the atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hj h]h struct intel_atomic_state *state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj ubj-)}(hhh]h)}(hthe atomic stateh]hthe atomic state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hM hjG ubj )}(h%``struct intel_crtc *crtc`` the CRTC h](j)}(h``struct intel_crtc *crtc``h]j)}(hj h]hstruct intel_crtc *crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj ubj-)}(hhh]h)}(hthe CRTCh]hthe CRTC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hM hjG ubeh}(h]h ]h"]h$]h&]uh1jhj+ ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj+ ubh)}(h"Generate PSR "Frame Change" event.h]h&Generate PSR “Frame Change” event.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj+ ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6.intel_psr_min_set_context_latency (C function)#c.intel_psr_min_set_context_latencyhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hQint intel_psr_min_set_context_latency (const struct intel_crtc_state *crtc_state)h]jF)}(hPint intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)h](jL)}(hinth]hint}(hjB hhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhj> hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj^)}(h h]h }(hjQ hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj> hhhjP hM ubjo)}(h!intel_psr_min_set_context_latencyh]ju)}(h!intel_psr_min_set_context_latencyh]h!intel_psr_min_set_context_latency}(hjc hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_ ubah}(h]h ](jjeh"]h$]h&]hhuh1jnhj> hhhjP hM ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjh]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj{ ubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj{ ubh)}(hhh]ju)}(hintel_crtc_stateh]hintel_crtc_state}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jje sb#c.intel_psr_min_set_context_latencyasbuh1hhj{ ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj{ ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubju)}(h crtc_stateh]h crtc_state}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj{ ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjw ubah}(h]h ]h"]h$]h&]hhuh1jhj> hhhjP hM ubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhj: hhhjP hM ubah}(h]j5 ah ](jjeh"]h$]h&]jj)jhuh1j?hjP hM hj7 hhubj)}(hhh]h)}(h1Minimum 'set context latency' lines needed by PSRh]h5Minimum ‘set context latency’ lines needed by PSR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj hhubah}(h]h ]h"]h$]h&]uh1jhj7 hhhjP hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj5 jj5 jjjuh1j:hhhhhNhNubj)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Return minimum SCL lines/delay needed by PSR.h](h)}(h**Parameters**h]j)}(hj? h]h Parameters}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj= ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj9 ubj)}(hhh]j )}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hj^ h]h)const struct intel_crtc_state *crtc_state}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjX ubj-)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs hM hjt ubah}(h]h ]h"]h$]h&]uh1j,hjX ubeh}(h]h ]h"]h$]h&]uh1j hjs hM hjU ubah}(h]h ]h"]h$]h&]uh1jhj9 ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj9 ubh)}(h-Return minimum SCL lines/delay needed by PSR.h]h-Return minimum SCL lines/delay needed by PSR.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj9 ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6+intel_psr_wait_for_idle_locked (C function) c.intel_psr_wait_for_idle_lockedhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hSvoid intel_psr_wait_for_idle_locked (const struct intel_crtc_state *new_crtc_state)h]jF)}(hRvoid intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)h](jL)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhj hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj hhhj hM ubjo)}(hintel_psr_wait_for_idle_lockedh]ju)}(hintel_psr_wait_for_idle_lockedh]hintel_psr_wait_for_idle_locked}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubah}(h]h ](jjeh"]h$]h&]hhuh1jnhj hhhj hM ubj)}(h/(const struct intel_crtc_state *new_crtc_state)h]j)}(h-const struct intel_crtc_state *new_crtc_stateh](j)}(hjh]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hj( hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]hstruct}(hj6 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hjC hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubh)}(hhh]ju)}(hintel_crtc_stateh]hintel_crtc_state}(hjT hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjQ ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjV modnameN classnameNjj)}j]j)}jj sb c.intel_psr_wait_for_idle_lockedasbuh1hhj ubj^)}(h h]h }(hjt hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubju)}(hnew_crtc_stateh]hnew_crtc_state}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubah}(h]h ]h"]h$]h&]hhuh1jhj hhhj hM ubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhj hhhj hM ubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j?hj hM hj hhubj)}(hhh]h)}(h'wait for PSR be ready for a pipe updateh]h'wait for PSR be ready for a pipe update}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1j:hhhhhNhNubj)}(h**Parameters** ``const struct intel_crtc_state *new_crtc_state`` new CRTC state **Description** This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj ubj)}(hhh]j )}(hA``const struct intel_crtc_state *new_crtc_state`` new CRTC state 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]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6!intel_psr_invalidate (C function)c.intel_psr_invalidatehNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hnvoid intel_psr_invalidate (struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h]jF)}(hmvoid intel_psr_invalidate(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](jL)}(hvoidh]hvoid}(hjzhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjvhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjvhhhjhM ubjo)}(hintel_psr_invalidateh]ju)}(hintel_psr_invalidateh]hintel_psr_invalidate}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjvhhhjhM ubj)}(hT(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.intel_psr_invalidateasbuh1hhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned frontbuffer_bitsh](jL)}(hunsignedh]hunsigned}(hj)hhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhj%ubj^)}(h h]h }(hj7hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj%ubju)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum fb_op_origin originh](j)}(henumh]henum}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj^)}(h h]h }(hjlhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjZubh)}(hhh]ju)}(h fb_op_originh]h fb_op_origin}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjzubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.intel_psr_invalidateasbuh1hhjZubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjZubju)}(horiginh]horigin}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjZubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjvhhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjrhhhjhM ubah}(h]jmah ](jjeh"]h$]h&]jj)jhuh1j?hjhM hjohhubj)}(hhh]h)}(hInvalidate PSRh]hInvalidate PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjohhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(hXA**Parameters** ``struct intel_display *display`` display device ``unsigned frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the invalidate **Description** Since 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This function gets called every time frontbuffer rendering starts and a buffer gets dirtied. PSR must be disabled if the frontbuffer mask contains a buffer relevant to PSR. Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh](j )}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj-)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hM hj*ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj)hM hj ubj )}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h``unsigned frontbuffer_bits``h]j)}(hjMh]hunsigned frontbuffer_bits}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjGubj-)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhM hjcubah}(h]h ]h"]h$]h&]uh1j,hjGubeh}(h]h ]h"]h$]h&]uh1j hjbhM hj ubj )}(hC``enum fb_op_origin origin`` which operation caused the invalidate h](j)}(h``enum fb_op_origin origin``h]j)}(hjh]henum fb_op_origin origin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj-)}(hhh]h)}(h%which operation caused the invalidateh]h%which operation caused the invalidate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM hj ubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. 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PSR must be disabled if the frontbuffer mask contains a buffer relevant to PSR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hIDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."h]hKDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6intel_psr_flush (C function)c.intel_psr_flushhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hivoid intel_psr_flush (struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h]jF)}(hhvoid intel_psr_flush(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](jL)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM^ubj^)}(h h]h }(hj$hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhj#hM^ubjo)}(hintel_psr_flushh]ju)}(hintel_psr_flushh]hintel_psr_flush}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj2ubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhj#hM^ubj)}(hT(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubj^)}(h h]h }(hj_hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjNubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjmubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjrmodnameN classnameNjj)}j]j)}jj8sbc.intel_psr_flushasbuh1hhjNubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjNubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubju)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjNubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjJubj)}(hunsigned frontbuffer_bitsh](jL)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubju)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjJubj)}(henum fb_op_origin originh](j)}(hj`h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(h fb_op_originh]h fb_op_origin}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.intel_psr_flushasbuh1hhjubj^)}(h h]h }(hj5hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubju)}(horiginh]horigin}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjJubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj#hM^ubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhj hhhj#hM^ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hj#hM^hj hhubj)}(hhh]h)}(h Flush PSRh]h Flush PSR}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM^hjjhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj#hM^ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(hX=**Parameters** ``struct intel_display *display`` display device ``unsigned frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the flush **Description** Since the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty. Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMbhjubj)}(hhh](j )}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM_hjubj-)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM_hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM_hjubj )}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h``unsigned frontbuffer_bits``h]j)}(hjh]hunsigned frontbuffer_bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM`hjubj-)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM`hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM`hjubj )}(h>``enum fb_op_origin origin`` which operation caused the flush h](j)}(h``enum fb_op_origin origin``h]j)}(hj h]henum fb_op_origin origin}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMahjubj-)}(hhh]h)}(h which operation caused the flushh]h which operation caused the flush}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMahj6ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj5hMahjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj[h]h Description}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMchjubh)}(hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty.h]hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMbhjubh)}(hHDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.h]hHDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMghjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6intel_psr_init (C function)c.intel_psr_inithNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(h/void intel_psr_init (struct intel_dp *intel_dp)h]jF)}(h.void intel_psr_init(struct intel_dp *intel_dp)h](jL)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhjhMubjo)}(hintel_psr_inith]ju)}(hintel_psr_inith]hintel_psr_init}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhjhMubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(hintel_dph]hintel_dp}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jjsbc.intel_psr_initasbuh1hhjubj^)}(h h]h }(hj*hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(hintel_dph]hintel_dp}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hjhMhjhhubj)}(hhh]h)}(hInit basic PSR work and mutex.h]hInit basic PSR work and mutex.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjlhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(hX **Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]j )}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj-)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hThis function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.h]hThis function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6intel_psr_link_ok (C function)c.intel_psr_link_okhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(h2bool intel_psr_link_ok (struct intel_dp *intel_dp)h]jF)}(h1bool intel_psr_link_ok(struct intel_dp *intel_dp)h](jL)}(hjh]hbool}(hj0hhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhj,hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMYubj^)}(h h]h }(hj>hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj,hhhj=hMYubjo)}(hintel_psr_link_okh]ju)}(hintel_psr_link_okh]hintel_psr_link_ok}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjLubah}(h]h ](jjeh"]h$]h&]hhuh1jnhj,hhhj=hMYubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj^)}(h h]h }(hjyhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhubh)}(hhh]ju)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjRsbc.intel_psr_link_okasbuh1hhjhubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubju)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjdubah}(h]h ]h"]h$]h&]hhuh1jhj,hhhj=hMYubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhj(hhhj=hMYubah}(h]j#ah ](jjeh"]h$]h&]jj)jhuh1j?hj=hMYhj%hhubj)}(hhh]h)}(hreturn psr->link_okh]hreturn psr->link_ok}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMYhjhhubah}(h]h ]h"]h$]h&]uh1jhj%hhhj=hMYubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(hX**Parameters** ``struct intel_dp *intel_dp`` struct intel_dp **Description** We are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter. Return value of link_okh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM]hj ubj)}(hhh]j )}(h.``struct intel_dp *intel_dp`` struct intel_dp h](j)}(h``struct intel_dp *intel_dp``h]j)}(hj0h]hstruct intel_dp *intel_dp}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMZhj*ubj-)}(hhh]h)}(hstruct intel_dph]hstruct intel_dp}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMZhjFubah}(h]h ]h"]h$]h&]uh1j,hj*ubeh}(h]h ]h"]h$]h&]uh1j hjEhMZhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hjkh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM\hj ubh)}(hXRWe are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter.h]hXRWe are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM[hj ubh)}(hReturn value of link_okh]hReturn value of link_ok}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMahj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6intel_psr_lock (C function)c.intel_psr_lockhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(h?void intel_psr_lock (const struct intel_crtc_state *crtc_state)h]jF)}(h>void intel_psr_lock(const struct intel_crtc_state *crtc_state)h](jL)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMtubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhjhMtubjo)}(hintel_psr_lockh]ju)}(hintel_psr_lockh]hintel_psr_lock}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhjhMtubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hj$hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(hintel_crtc_stateh]hintel_crtc_state}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj2ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj7modnameN classnameNjj)}j]j)}jjsbc.intel_psr_lockasbuh1hhjubj^)}(h h]h }(hjUhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h crtc_stateh]h crtc_state}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMtubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjhhhjhMtubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hjhMthjhhubj)}(hhh]h)}(h grab PSR lockh]h grab PSR lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMthjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMtubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(hX**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** This is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMxhjubj)}(hhh]j )}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMuhjubj-)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMuhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMuhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMwhjubh)}(hThis is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.h]hThis is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMvhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6intel_psr_unlock (C function)c.intel_psr_unlockhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hAvoid intel_psr_unlock (const struct intel_crtc_state *crtc_state)h]jF)}(h@void intel_psr_unlock(const struct intel_crtc_state *crtc_state)h](jL)}(hvoidh]hvoid}(hj[hhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjWhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj^)}(h h]h }(hjjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjWhhhjihMubjo)}(hintel_psr_unlockh]ju)}(hintel_psr_unlockh]hintel_psr_unlock}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjxubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjWhhhjihMubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jj~sbc.intel_psr_unlockasbuh1hhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h crtc_stateh]h crtc_state}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjWhhhjihMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjShhhjihMubah}(h]jNah ](jjeh"]h$]h&]jj)jhuh1j?hjihMhjPhhubj)}(hhh]h)}(hrelease PSR lockh]hrelease PSR lock}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj3hhubah}(h]h ]h"]h$]h&]uh1jhjPhhhjihMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjNjjNjjjuh1j:hhhhhNhNubj)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Release the PSR lock that was held during pipe update.h](h)}(h**Parameters**h]j)}(hjXh]h Parameters}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjRubj)}(hhh]j )}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjwh]h)const struct intel_crtc_state *crtc_state}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjqubj-)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjqubeh}(h]h ]h"]h$]h&]uh1j hjhMhjnubah}(h]h ]h"]h$]h&]uh1jhjRubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjRubh)}(h6Release the PSR lock that was held during pipe update.h]h6Release the PSR lock that was held during pipe update.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjRubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6%intel_psr_notify_dc5_dc6 (C function)c.intel_psr_notify_dc5_dc6hNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(h=void intel_psr_notify_dc5_dc6 (struct intel_display *display)h]jF)}(hvoid intel_psr_dc5_dc6_wa_init (struct intel_display *display)h]jF)}(h=void intel_psr_dc5_dc6_wa_init(struct intel_display *display)h](jL)}(hvoidh]hvoid}(hjxhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjthhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjthhhjhMubjo)}(hintel_psr_dc5_dc6_wa_inith]ju)}(hintel_psr_dc5_dc6_wa_inith]hintel_psr_dc5_dc6_wa_init}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjthhhjhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.intel_psr_dc5_dc6_wa_initasbuh1hhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjthhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjphhhjhMubah}(h]jkah ](jjeh"]h$]h&]jj)jhuh1j?hjhMhjmhhubj)}(hhh]h)}(h,Init work for underrun on idle PSR HW bug wah]h,Init work for underrun on idle PSR HW bug wa}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj5hhubah}(h]h ]h"]h$]h&]uh1jhjmhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjPjjPjjjuh1j:hhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` intel atomic state **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.h](h)}(h**Parameters**h]j)}(hjZh]h Parameters}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjTubj)}(hhh]j )}(h5``struct intel_display *display`` intel atomic state h](j)}(h!``struct intel_display *display``h]j)}(hjyh]hstruct intel_display *display}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjsubj-)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjsubeh}(h]h ]h"]h$]h&]uh1j hjhMhjpubah}(h]h ]h"]h$]h&]uh1jhjTubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjTubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.h]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjTubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6)intel_psr_notify_pipe_change (C function)c.intel_psr_notify_pipe_changehNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hjvoid intel_psr_notify_pipe_change (struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h]jF)}(hivoid intel_psr_notify_pipe_change(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h](jL)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhjhMubjo)}(hintel_psr_notify_pipe_changeh]ju)}(hintel_psr_notify_pipe_changeh]hintel_psr_notify_pipe_change}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhjhMubj)}(hH(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj^)}(h h]h }(hjChhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj2ubh)}(hhh]ju)}(hintel_atomic_stateh]hintel_atomic_state}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjQubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjVmodnameN classnameNjj)}j]j)}jjsbc.intel_psr_notify_pipe_changeasbuh1hhj2ubj^)}(h h]h }(hjthhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj2ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubju)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj2ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj.ubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jpc.intel_psr_notify_pipe_changeasbuh1hhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj.ubj)}(h bool enableh](jL)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjubj^)}(h h]h }(hj%hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubju)}(henableh]henable}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj.ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hjhMhjhhubj)}(hhh]h)}(h)Notify PSR about enable/disable of a pipeh]h)Notify PSR about enable/disable of a pipe}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjZhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjujjujjjuh1j:hhhhhNhNubj)}(hX.**Parameters** ``struct intel_atomic_state *state`` intel atomic state ``struct intel_crtc *crtc`` intel crtc ``bool enable`` enable/disable **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabledh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjyubj)}(hhh](j )}(h8``struct intel_atomic_state *state`` intel atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj-)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(h'``struct intel_crtc *crtc`` intel crtc h](j)}(h``struct intel_crtc *crtc``h]j)}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj-)}(hhh]h)}(h intel crtch]h intel crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(h``bool enable`` enable/disable h](j)}(h``bool enable``h]j)}(hjh]h bool enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj ubj-)}(hhh]h)}(henable/disableh]henable/disable}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMhj&ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj%hMhjubeh}(h]h ]h"]h$]h&]uh1jhjyubh)}(h**Description**h]j)}(hjKh]h Description}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjyubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabledh]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabled}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjyubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j63intel_psr_notify_vblank_enable_disable (C function)(c.intel_psr_notify_vblank_enable_disablehNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hXvoid intel_psr_notify_vblank_enable_disable (struct intel_display *display, bool enable)h]jF)}(hWvoid intel_psr_notify_vblank_enable_disable(struct intel_display *display, bool enable)h](jL)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhjhMubjo)}(h&intel_psr_notify_vblank_enable_disableh]ju)}(h&intel_psr_notify_vblank_enable_disableh]h&intel_psr_notify_vblank_enable_disable}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhjhMubj)}(h,(struct intel_display *display, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb(c.intel_psr_notify_vblank_enable_disableasbuh1hhjubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(hdisplayh]hdisplay}(hj& hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h bool enableh](jL)}(hjh]hbool}(hj? hhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhj; ubj^)}(h h]h }(hjL hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj; ubju)}(henableh]henable}(hjZ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj; ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hjhMhjhhubj)}(hhh]h)}(h)Notify PSR about enable/disable of vblankh]h)Notify PSR about enable/disable of vblank}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1j:hhhhhNhNubj)}(hX**Parameters** ``struct intel_display *display`` intel display struct ``bool enable`` enable/disable **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when vblank is getting enabled/disabledh](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM!hj ubj)}(hhh](j )}(h7``struct intel_display *display`` intel display struct h](j)}(h!``struct intel_display *display``h]j)}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj ubj-)}(hhh]h)}(hintel display structh]hintel display struct}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hMhj ubj )}(h``bool enable`` enable/disable h](j)}(h``bool enable``h]j)}(hj h]h bool enable}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj ubj-)}(hhh]h)}(henable/disableh]henable/disable}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMhj!ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj!hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj 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