Isphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget)/translations/zh_CN/gpu/intel-display/psrmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/zh_TW/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/it_IT/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ja_JP/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ko_KR/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/pt_BR/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/sp_SP/gpu/intel-display/psrmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhC/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(h Panel Self Refresh PSR (PSR/SRD)h]h Panel Self Refresh PSR (PSR/SRD)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXSince Haswell Display controller supports Panel Self-Refresh on display panels witch have a remote frame buffer (RFB) implemented according to PSR spec in eDP1.3. PSR feature allows the display to go to lower standby states when system is idle but display is on as it eliminates display refresh request to DDR memory completely as long as the frame buffer for that display is unchanged.h]hXSince Haswell Display controller supports Panel Self-Refresh on display panels witch have a remote frame buffer (RFB) implemented according to PSR spec in eDP1.3. PSR feature allows the display to go to lower standby states when system is idle but display is on as it eliminates display refresh request to DDR memory completely as long as the frame buffer for that display is unchanged.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chK?hhhhubh)}(hPPanel Self Refresh must be supported by both Hardware (source) and Panel (sink).h]hPPanel Self Refresh must be supported by both Hardware (source) and Panel (sink).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chKFhhhhubh)}(hPSR saves power by caching the framebuffer in the panel RFB, which allows us to power down the link and memory controller. For DSI panels the same idea is called "manual mode".h]hPSR saves power by caching the framebuffer in the panel RFB, which allows us to power down the link and memory controller. For DSI panels the same idea is called “manual mode”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chKIhhhhubh)}(hXThe implementation uses the hardware-based PSR support which automatically enters/exits self-refresh mode. The hardware takes care of sending the required DP aux message and could even retrain the link (that part isn't enabled yet though). The hardware also keeps track of any frontbuffer changes to know when to exit self-refresh mode again. Unfortunately that part doesn't work too well, hence why the i915 PSR support uses the software frontbuffer tracking to make sure it doesn't miss a screen update. For this integration intel_psr_invalidate() and intel_psr_flush() get called by the frontbuffer tracking code. Note that because of locking issues the self-refresh re-enable code is done from a work queue, which must be correctly synchronized/cancelled when shutting down the pipe."h]hXThe implementation uses the hardware-based PSR support which automatically enters/exits self-refresh mode. The hardware takes care of sending the required DP aux message and could even retrain the link (that part isn’t enabled yet though). The hardware also keeps track of any frontbuffer changes to know when to exit self-refresh mode again. Unfortunately that part doesn’t work too well, hence why the i915 PSR support uses the software frontbuffer tracking to make sure it doesn’t miss a screen update. For this integration intel_psr_invalidate() and intel_psr_flush() get called by the frontbuffer tracking code. Note that because of locking issues the self-refresh re-enable code is done from a work queue, which must be correctly synchronized/cancelled when shutting down the pipe.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chKMhhhhubh)}(hDC3CO (DC3 clock off)h]hDC3CO (DC3 clock off)}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chKYhhhhubh)}(hXNOn top of PSR2, GEN12 adds a intermediate power savings state that turns clock off automatically during PSR2 idle state. The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep entry/exit allows the HW to enter a low-power state even when page flipping periodically (for instance a 30fps video playback scenario).h]hXNOn top of PSR2, GEN12 adds a intermediate power savings state that turns clock off automatically during PSR2 idle state. The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep entry/exit allows the HW to enter a low-power state even when page flipping periodically (for instance a 30fps video playback scenario).}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chK[hhhhubh)}(hXEvery time a flips occurs PSR2 will get out of deep sleep state(if it was), so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 frames, if no other flip occurs and the function above is executed, DC3CO is disabled and PSR2 is configured to enter deep sleep, resetting again in case of another flip. Front buffer modifications do not trigger DC3CO activation on purpose as it would bring a lot of complexity and most of the moderns systems will only use page flips.h]hXEvery time a flips occurs PSR2 will get out of deep sleep state(if it was), so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 frames, if no other flip occurs and the function above is executed, DC3CO is disabled and PSR2 is configured to enter deep sleep, resetting again in case of another flip. Front buffer modifications do not trigger DC3CO activation on purpose as it would bring a lot of complexity and most of the moderns systems will only use page flips.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:7: ./drivers/gpu/drm/i915/display/intel_psr.chKahhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleintel_psr_disable (C function)c.intel_psr_disablehNtauh1jVhhhhhNhNubhdesc)}(hhh](hdesc_signature)}(havoid intel_psr_disable (struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h]hdesc_signature_line)}(h`void intel_psr_disable(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjzhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jxhjthhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjthhhjhM ubh desc_name)}(hintel_psr_disableh]h desc_sig_name)}(hintel_psr_disableh]hintel_psr_disable}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjthhhjhM ubhdesc_parameterlist)}(hJ(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h](hdesc_parameter)}(hstruct intel_dp *intel_dph](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jjsbc.intel_psr_disableasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubhdesc_sig_punctuation)}(h*h]h*}(hj!hhhNhNubah}(h]h ]pah"]h$]h&]uh1jhjubj)}(hintel_dph]hintel_dp}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h-const struct intel_crtc_state *old_crtc_stateh](j)}(hconsth]hconst}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(hjh]hstruct}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubh)}(hhh]j)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j c.intel_psr_disableasbuh1hhjEubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjEubj)}(hold_crtc_stateh]hold_crtc_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjthhhjhM ubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1jrsphinx_line_type declaratorhjnhhhjhM ubah}(h]jeah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jlhjhM hjihhubh desc_content)}(hhh]h)}(h Disable PSRh]h Disable PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjihhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jghhhhhNhNubh container)}(h**Parameters** ``struct intel_dp *intel_dp`` Intel DP ``const struct intel_crtc_state *old_crtc_state`` old CRTC state **Description** This function needs to be called before disabling pipe.h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubhdefinition_list)}(hhh](hdefinition_list_item)}(h'``struct intel_dp *intel_dp`` Intel DP h](hterm)}(h``struct intel_dp *intel_dp``h]hliteral)}(hjAh]hstruct intel_dp *intel_dp}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jChj?ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj9ubh definition)}(hhh]h)}(hIntel DPh]hIntel DP}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhM hj[ubah}(h]h ]h"]h$]h&]uh1jYhj9ubeh}(h]h ]h"]h$]h&]uh1j7hjXhM hj4ubj8)}(hA``const struct intel_crtc_state *old_crtc_state`` old CRTC state h](j>)}(h1``const struct intel_crtc_state *old_crtc_state``h]jD)}(hj~h]h-const struct intel_crtc_state *old_crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChj|ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjxubjZ)}(hhh]h)}(hold CRTC stateh]hold CRTC state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jYhjxubeh}(h]h ]h"]h$]h&]uh1j7hjhM hj4ubeh}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(h7This function needs to be called before disabling pipe.h]h7This function needs to be called before disabling pipe.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jcintel_psr_pause (C function)c.intel_psr_pausehNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(h0void intel_psr_pause (struct intel_dp *intel_dp)h]js)}(h/void intel_psr_pause(struct intel_dp *intel_dp)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj hM ubj)}(hintel_psr_pauseh]j)}(hintel_psr_pauseh]hintel_psr_pause}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj hM ubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj)}(h h]h }(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubh)}(hhh]j)}(hintel_dph]hintel_dp}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj[modnameN classnameNjj)}j ]j )}jj!sbc.intel_psr_pauseasbuh1hhj7ubj)}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhj7ubj)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj3ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj hM ubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhj hM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhj hM hjhhubj)}(hhh]h)}(h Pause PSRh]h Pause PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hM ubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jghhhhhNhNubj)}(h~**Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function need to be called after enabling psr.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj3)}(hhh]j8)}(h'``struct intel_dp *intel_dp`` Intel DP h](j>)}(h``struct intel_dp *intel_dp``h]jD)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubjZ)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhM hjubah}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hj:h]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(h3This function need to be called after enabling psr.h]h3This function need to be called after enabling psr.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jcintel_psr_resume (C function)c.intel_psr_resumehNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(h1void intel_psr_resume (struct intel_dp *intel_dp)h]js)}(h0void intel_psr_resume(struct intel_dp *intel_dp)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhj{hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{hhhjhM ubj)}(hintel_psr_resumeh]j)}(hintel_psr_resumeh]hintel_psr_resume}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj{hhhjhM ubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j )}jjsbc.intel_psr_resumeasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj{hhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjwhhhjhM ubah}(h]jrah ](jjeh"]h$]h&]jj)jhuh1jlhjhM hjthhubj)}(hhh]h)}(h Resume PSRh]h Resume PSR}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj<hhubah}(h]h ]h"]h$]h&]uh1jhjthhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]j jj jWjjWjjjuh1jghhhhhNhNubj)}(h}**Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function need to be called after pausing psr.h](h)}(h**Parameters**h]j)}(hjah]h Parameters}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj[ubj3)}(hhh]j8)}(h'``struct intel_dp *intel_dp`` Intel DP h](j>)}(h``struct intel_dp *intel_dp``h]jD)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChj~ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjzubjZ)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jYhjzubeh}(h]h ]h"]h$]h&]uh1j7hjhM hjwubah}(h]h ]h"]h$]h&]uh1j2hj[ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj[ubh)}(h2This function need to be called after pausing psr.h]h2This function need to be called after pausing psr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj[ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc0intel_psr_needs_vblank_notification (C function)%c.intel_psr_needs_vblank_notificationhNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(hTbool intel_psr_needs_vblank_notification (const struct intel_crtc_state *crtc_state)h]js)}(hSbool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state)h](jy)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM ubj)}(h#intel_psr_needs_vblank_notificationh]j)}(h#intel_psr_needs_vblank_notificationh]h#intel_psr_needs_vblank_notification}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjKh]hconst}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubj)}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubj)}(hjh]hstruct}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubj)}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubh)}(hhh]j)}(hintel_crtc_stateh]hintel_crtc_state}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjxmodnameN classnameNjj)}j ]j )}jj#sb%c.intel_psr_needs_vblank_notificationasbuh1hhj9ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhj9ubj)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj5ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhjhM hjhhubj)}(hhh]h)}(h5Check if PSR need vblank enable/disable notification.h]h5Check if PSR need vblank enable/disable notification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jghhhhhNhNubj)}(hX**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC status **Description** We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events. Also Wa_16025596647 needs information when vblank is enabled/disabled.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj3)}(hhh]j8)}(h:``const struct intel_crtc_state *crtc_state`` CRTC status h](j>)}(h-``const struct intel_crtc_state *crtc_state``h]jD)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubjZ)}(hhh]h)}(h CRTC statush]h CRTC status}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hM hj2ubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hj1hM hjubah}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjWh]h Description}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hXNWe need to block DC6 entry in case of Panel Replay as enabling VBI doesn't prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events. Also Wa_16025596647 needs information when vblank is enabled/disabled.h]hXPWe need to block DC6 entry in case of Panel Replay as enabling VBI doesn’t prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events. Also Wa_16025596647 needs information when vblank is enabled/disabled.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc1intel_psr_trigger_frame_change_event (C function)&c.intel_psr_trigger_frame_change_eventhNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(h|void intel_psr_trigger_frame_change_event (struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h]js)}(h{void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM ubj)}(h$intel_psr_trigger_frame_change_eventh]j)}(h$intel_psr_trigger_frame_change_eventh]h$intel_psr_trigger_frame_change_event}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(hR(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_dsbh]h intel_dsb}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j )}jjsb&c.intel_psr_trigger_frame_change_eventasbuh1hhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hj% hhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(hdsbh]hdsb}(hj2 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjK hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG ubj)}(h h]h }(hjX hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG ubh)}(hhh]j)}(hintel_atomic_stateh]hintel_atomic_state}(hji hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjf ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjk modnameN classnameNjj)}j ]j &c.intel_psr_trigger_frame_change_eventasbuh1hhjG ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG ubj )}(hj#h]h*}(hj hhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjG ubj)}(hstateh]hstate}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h intel_crtch]h intel_crtc}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j ]j &c.intel_psr_trigger_frame_change_eventasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj )}(hj#h]h*}(hj hhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhj ubj)}(hcrtch]hcrtc}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhjhM hjhhubj)}(hhh]h)}(hTrigger "Frame Change" eventh]h Trigger “Frame Change” event}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj9 hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]j jj jT jjT jjjuh1jghhhhhNhNubj)}(h**Parameters** ``struct intel_dsb *dsb`` DSB context ``struct intel_atomic_state *state`` the atomic state ``struct intel_crtc *crtc`` the CRTC **Description** Generate PSR "Frame Change" event.h](h)}(h**Parameters**h]j)}(hj^ h]h Parameters}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjX ubj3)}(hhh](j8)}(h&``struct intel_dsb *dsb`` DSB context h](j>)}(h``struct intel_dsb *dsb``h]jD)}(hj} h]hstruct intel_dsb *dsb}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj{ ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjw ubjZ)}(hhh]h)}(h DSB contexth]h DSB context}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jYhjw ubeh}(h]h ]h"]h$]h&]uh1j7hj hM hjt ubj8)}(h6``struct intel_atomic_state *state`` the atomic state h](j>)}(h$``struct intel_atomic_state *state``h]jD)}(hj h]h struct intel_atomic_state *state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj ubjZ)}(hhh]h)}(hthe atomic stateh]hthe atomic state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jYhj ubeh}(h]h ]h"]h$]h&]uh1j7hj hM hjt ubj8)}(h%``struct intel_crtc *crtc`` the CRTC h](j>)}(h``struct intel_crtc *crtc``h]jD)}(hj h]hstruct intel_crtc *crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj ubjZ)}(hhh]h)}(hthe CRTCh]hthe CRTC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jYhj ubeh}(h]h ]h"]h$]h&]uh1j7hj hM hjt ubeh}(h]h ]h"]h$]h&]uh1j2hjX ubh)}(h**Description**h]j)}(hj* h]h Description}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj( ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjX ubh)}(h"Generate PSR "Frame Change" event.h]h&Generate PSR “Frame Change” event.}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjX ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc.intel_psr_min_set_context_latency (C function)#c.intel_psr_min_set_context_latencyhNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(hQint intel_psr_min_set_context_latency (const struct intel_crtc_state *crtc_state)h]js)}(hPint intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)h](jy)}(hinth]hint}(hjo hhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjk hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM. ubj)}(h h]h }(hj~ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjk hhhj} hM. ubj)}(h!intel_psr_min_set_context_latencyh]j)}(h!intel_psr_min_set_context_latencyh]h!intel_psr_min_set_context_latency}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjk hhhj} hM. ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjKh]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(hintel_crtc_stateh]hintel_crtc_state}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j ]j )}jj sb#c.intel_psr_min_set_context_latencyasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj )}(hj#h]h*}(hj hhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhj ubj)}(h crtc_stateh]h crtc_state}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubah}(h]h ]h"]h$]h&]hhuh1jhjk hhhj} hM. ubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjg hhhj} hM. ubah}(h]jb ah ](jjeh"]h$]h&]jj)jhuh1jlhj} hM. hjd hhubj)}(hhh]h)}(h1Minimum 'set context latency' lines needed by PSRh]h5Minimum ‘set context latency’ lines needed by PSR}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM. hjG hhubah}(h]h ]h"]h$]h&]uh1jhjd hhhj} hM. ubeh}(h]h ](jfunctioneh"]h$]h&]j jj jb jjb jjjuh1jghhhhhNhNubj)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Return minimum SCL lines/delay needed by PSR.h](h)}(h**Parameters**h]j)}(hjl h]h Parameters}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM2 hjf ubj3)}(hhh]j8)}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j>)}(h-``const struct intel_crtc_state *crtc_state``h]jD)}(hj h]h)const struct intel_crtc_state *crtc_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM/ hj ubjZ)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM/ hj ubah}(h]h ]h"]h$]h&]uh1jYhj ubeh}(h]h ]h"]h$]h&]uh1j7hj hM/ hj ubah}(h]h ]h"]h$]h&]uh1j2hjf ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM1 hjf ubh)}(h-Return minimum SCL lines/delay needed by PSR.h]h-Return minimum SCL lines/delay needed by PSR.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM0 hjf ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc+intel_psr_wait_for_idle_locked (C function) c.intel_psr_wait_for_idle_lockedhNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(hSvoid intel_psr_wait_for_idle_locked (const struct intel_crtc_state *new_crtc_state)h]js)}(hRvoid intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)h](jy)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhj hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hM 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hhhj hM ubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhj hhhj hM ubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jlhj hM hj hhubj)}(hhh]h)}(h'wait for PSR be ready for a pipe updateh]h'wait for PSR be ready for a pipe update}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hM ubeh}(h]h ](jfunctioneh"]h$]h&]j jj j jj jjjuh1jghhhhhNhNubj)}(h**Parameters** ``const struct intel_crtc_state *new_crtc_state`` new CRTC state **Description** This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj3)}(hhh]j8)}(hA``const struct intel_crtc_state *new_crtc_state`` new CRTC state h](j>)}(h1``const struct intel_crtc_state *new_crtc_state``h]jD)}(hj'h]h-const struct intel_crtc_state *new_crtc_state}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj%ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hj!ubjZ)}(hhh]h)}(hnew CRTC stateh]hnew CRTC state}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM hj=ubah}(h]h ]h"]h$]h&]uh1jYhj!ubeh}(h]h ]h"]h$]h&]uh1j7hj<hM hjubah}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjbh]h Description}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(h|This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.h]h|This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc!intel_psr_invalidate (C function)c.intel_psr_invalidatehNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(hnvoid intel_psr_invalidate (struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h]js)}(hmvoid intel_psr_invalidate(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM#ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM#ubj)}(hintel_psr_invalidateh]j)}(hintel_psr_invalidateh]hintel_psr_invalidate}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM#ubj)}(hT(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j )}jjsbc.intel_psr_invalidateasbuh1hhjubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hj0hhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(hdisplayh]hdisplay}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned frontbuffer_bitsh](jy)}(hunsignedh]hunsigned}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjRubj)}(h h]h }(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum fb_op_origin originh](j)}(henumh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h fb_op_originh]h fb_op_origin}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]jc.intel_psr_invalidateasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(horiginh]horigin}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM#ubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhjhM#ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhjhM#hjhhubj)}(hhh]h)}(hInvalidate PSRh]hInvalidate PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM#hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM#ubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jghhhhhNhNubj)}(hXA**Parameters** ``struct intel_display *display`` display device ``unsigned frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the invalidate **Description** Since the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering starts and a buffer gets dirtied. PSR must be disabled if the frontbuffer mask contains a buffer relevant to PSR. Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."h](h)}(h**Parameters**h]j)}(hj"h]h Parameters}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM'hjubj3)}(hhh](j8)}(h1``struct intel_display *display`` display device h](j>)}(h!``struct intel_display *display``h]jD)}(hjAh]hstruct intel_display *display}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jChj?ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM$hj;ubjZ)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhM$hjWubah}(h]h ]h"]h$]h&]uh1jYhj;ubeh}(h]h ]h"]h$]h&]uh1j7hjVhM$hj8ubj8)}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j>)}(h``unsigned frontbuffer_bits``h]jD)}(hjzh]hunsigned frontbuffer_bits}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jChjxubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM%hjtubjZ)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM%hjubah}(h]h ]h"]h$]h&]uh1jYhjtubeh}(h]h ]h"]h$]h&]uh1j7hjhM%hj8ubj8)}(hC``enum fb_op_origin origin`` which operation caused the invalidate h](j>)}(h``enum fb_op_origin origin``h]jD)}(hjh]henum fb_op_origin origin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM&hjubjZ)}(hhh]h)}(h%which operation caused the invalidateh]h%which operation caused the invalidate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM&hjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhM&hj8ubeh}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM(hjubh)}(hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. 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PSR must be disabled if the frontbuffer mask contains a buffer relevant to PSR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM'hjubh)}(hIDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."h]hKDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM,hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jcintel_psr_flush (C function)c.intel_psr_flushhNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(hivoid intel_psr_flush (struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h]js)}(hhvoid intel_psr_flush(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](jy)}(hvoidh]hvoid}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhj>hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>hhhjPhMubj)}(hintel_psr_flushh]j)}(hintel_psr_flushh]hintel_psr_flush}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj>hhhjPhMubj)}(hT(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubh)}(hhh]j)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j )}jjesbc.intel_psr_flushasbuh1hhj{ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhj{ubj)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubj)}(hunsigned frontbuffer_bitsh](jy)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubj)}(henum fb_op_origin originh](j)}(hjh]henum}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubh)}(hhh]j)}(h fb_op_originh]h fb_op_origin}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjFmodnameN classnameNjj)}j ]jc.intel_psr_flushasbuh1hhj"ubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj)}(horiginh]horigin}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubeh}(h]h ]h"]h$]h&]hhuh1jhj>hhhjPhMubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhj:hhhjPhMubah}(h]j5ah ](jjeh"]h$]h&]jj)jhuh1jlhjPhMhj7hhubj)}(hhh]h)}(h Flush PSRh]h Flush PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj7hhhjPhMubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jghhhhhNhNubj)}(hX=**Parameters** ``struct intel_display *display`` display device ``unsigned frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the flush **Description** Since the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty. Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj3)}(hhh](j8)}(h1``struct intel_display *display`` display device h](j>)}(h!``struct intel_display *display``h]jD)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjZ)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhMhjubj8)}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j>)}(h``unsigned frontbuffer_bits``h]jD)}(hjh]hunsigned frontbuffer_bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjZ)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hMhj*ubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hj)hMhjubj8)}(h>``enum fb_op_origin origin`` which operation caused the flush h](j>)}(h``enum fb_op_origin origin``h]jD)}(hjMh]henum fb_op_origin origin}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjKubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjGubjZ)}(hhh]h)}(h which operation caused the flushh]h which operation caused the flush}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMhjcubah}(h]h ]h"]h$]h&]uh1jYhjGubeh}(h]h ]h"]h$]h&]uh1j7hjbhMhjubeh}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty.h]hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hHDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.h]hHDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jcintel_psr_init (C function)c.intel_psr_inithNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(h/void intel_psr_init (struct intel_dp *intel_dp)h]js)}(h.void intel_psr_init(struct intel_dp *intel_dp)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.cܰhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hintel_psr_inith]j)}(hintel_psr_inith]hintel_psr_init}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hintel_dph]hintel_dp}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj9modnameN classnameNjj)}j ]j )}jjsbc.intel_psr_initasbuh1hhjubj)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hjehhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(hintel_dph]hintel_dp}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhjhMhjhhubj)}(hhh]h)}(hInit basic PSR work and mutex.h]hInit basic PSR work and mutex.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jghhhhhNhNubj)}(hX **Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj3)}(hhh]j8)}(h'``struct intel_dp *intel_dp`` Intel DP h](j>)}(h``struct intel_dp *intel_dp``h]jD)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjZ)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhMhjubah}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hThis function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.h]hThis function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jcintel_psr_link_ok (C function)c.intel_psr_link_okhNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(h2bool intel_psr_link_ok (struct intel_dp *intel_dp)h]js)}(h1bool intel_psr_link_ok(struct intel_dp *intel_dp)h](jy)}(hjh]hbool}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjYhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj)}(h h]h }(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYhhhjjhMubj)}(hintel_psr_link_okh]j)}(hintel_psr_link_okh]hintel_psr_link_ok}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubah}(h]h ](jjeh"]h$]h&]hhuh1jhjYhhhjjhMubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j )}jjsbc.intel_psr_link_okasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjYhhhjjhMubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjUhhhjjhMubah}(h]jPah ](jjeh"]h$]h&]jj)jhuh1jlhjjhMhjRhhubj)}(hhh]h)}(hreturn psr->link_okh]hreturn psr->link_ok}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjRhhhjjhMubeh}(h]h ](jfunctioneh"]h$]h&]j jj j4jj4jjjuh1jghhhhhNhNubj)}(hX**Parameters** ``struct intel_dp *intel_dp`` struct intel_dp **Description** We are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter. Return value of link_okh](h)}(h**Parameters**h]j)}(hj>h]h Parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj8ubj3)}(hhh]j8)}(h.``struct intel_dp *intel_dp`` struct intel_dp h](j>)}(h``struct intel_dp *intel_dp``h]jD)}(hj]h]hstruct intel_dp *intel_dp}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj[ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjWubjZ)}(hhh]h)}(hstruct intel_dph]hstruct intel_dp}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjsubah}(h]h ]h"]h$]h&]uh1jYhjWubeh}(h]h ]h"]h$]h&]uh1j7hjrhMhjTubah}(h]h ]h"]h$]h&]uh1j2hj8ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj8ubh)}(hXRWe are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter.h]hXRWe are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj8ubh)}(hReturn value of link_okh]hReturn value of link_ok}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jcintel_psr_lock (C function)c.intel_psr_lockhNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(h?void intel_psr_lock (const struct intel_crtc_state *crtc_state)h]js)}(h>void intel_psr_lock(const struct intel_crtc_state *crtc_state)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hintel_psr_lockh]j)}(hintel_psr_lockh]hintel_psr_lock}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjKh]hconst}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(hjh]hstruct}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubh)}(hhh]j)}(hintel_crtc_stateh]hintel_crtc_state}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjdmodnameN classnameNjj)}j ]j )}jjsbc.intel_psr_lockasbuh1hhj%ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhj%ubj)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj!ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhjhMhjhhubj)}(hhh]h)}(h grab PSR lockh]h grab PSR lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jghhhhhNhNubj)}(hX**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** This is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj3)}(hhh]j8)}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j>)}(h-``const struct intel_crtc_state *crtc_state``h]jD)}(hjh]h)const struct intel_crtc_state *crtc_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjZ)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhMhjubah}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjCh]h Description}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hThis is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.h]hThis is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jcintel_psr_unlock (C function)c.intel_psr_unlockhNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(hAvoid intel_psr_unlock (const struct intel_crtc_state *crtc_state)h]js)}(h@void intel_psr_unlock(const struct intel_crtc_state *crtc_state)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hintel_psr_unlockh]j)}(hintel_psr_unlockh]hintel_psr_unlock}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjKh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j )}jjsbc.intel_psr_unlockasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hj,hhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(h crtc_stateh]h crtc_state}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhjhMubah}(h]j{ah ](jjeh"]h$]h&]jj)jhuh1jlhjhMhj}hhubj)}(hhh]h)}(hrelease PSR lockh]hrelease PSR lock}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhj`hhubah}(h]h ]h"]h$]h&]uh1jhj}hhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]j jj j{jj{jjjuh1jghhhhhNhNubj)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Release the PSR lock that was held during pipe update.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj3)}(hhh]j8)}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j>)}(h-``const struct intel_crtc_state *crtc_state``h]jD)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjZ)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhMhjubah}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(h6Release the PSR lock that was held during pipe update.h]h6Release the PSR lock that was held during pipe update.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc%intel_psr_notify_dc5_dc6 (C function)c.intel_psr_notify_dc5_dc6hNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(h=void intel_psr_notify_dc5_dc6 (struct intel_display *display)h]js)}(h)}(h!``struct intel_display *display``h]jD)}(hj%h]hstruct intel_display *display}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj#ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjZ)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj;ubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hj:hMhjubah}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hj`h]h Description}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule psr_dc5_dc6_wa_work used for applying/removing the workaround.h]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule psr_dc5_dc6_wa_work used for applying/removing the workaround.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc&intel_psr_dc5_dc6_wa_init (C function)c.intel_psr_dc5_dc6_wa_inithNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(h>void intel_psr_dc5_dc6_wa_init (struct intel_display *display)h]js)}(h=void intel_psr_dc5_dc6_wa_init(struct intel_display *display)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hintel_psr_dc5_dc6_wa_inith]j)}(hintel_psr_dc5_dc6_wa_inith]hintel_psr_dc5_dc6_wa_init}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j )}jjsbc.intel_psr_dc5_dc6_wa_initasbuh1hhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hj.hhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(hdisplayh]hdisplay}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhjhMhjhhubj)}(hhh]h)}(h,Init work for underrun on idle PSR HW bug wah]h,Init work for underrun on idle PSR HW bug wa}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjbhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]j jj j}jj}jjjuh1jghhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` intel atomic state **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj3)}(hhh]j8)}(h5``struct intel_display *display`` intel atomic state h](j>)}(h!``struct intel_display *display``h]jD)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjZ)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhMhjubah}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.h]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc)intel_psr_notify_pipe_change (C function)c.intel_psr_notify_pipe_changehNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(hjvoid intel_psr_notify_pipe_change (struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h]js)}(hivoid intel_psr_notify_pipe_change(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h](jy)}(hvoidh]hvoid}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhj"hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"hhhj4hMubj)}(hintel_psr_notify_pipe_changeh]j)}(hintel_psr_notify_pipe_changeh]hintel_psr_notify_pipe_change}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ](jjeh"]h$]h&]hhuh1jhj"hhhj4hMubj)}(hH(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj)}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubh)}(hhh]j)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]j )}jjIsbc.intel_psr_notify_pipe_changeasbuh1hhj_ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhj_ubj)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj[ubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j ]jc.intel_psr_notify_pipe_changeasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hjhhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(hcrtch]hcrtc}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj[ubj)}(h bool enableh](jy)}(hjh]hbool}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjAubj)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubj)}(henableh]henable}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj[ubeh}(h]h ]h"]h$]h&]hhuh1jhj"hhhj4hMubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhj4hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhj4hMhjhhubj)}(hhh]h)}(h)Notify PSR about enable/disable of a pipeh]h)Notify PSR about enable/disable of a pipe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj4hMubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jghhhhhNhNubj)}(hX.**Parameters** ``struct intel_atomic_state *state`` intel atomic state ``struct intel_crtc *crtc`` intel crtc ``bool enable`` enable/disable **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabledh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM"hjubj3)}(hhh](j8)}(h8``struct intel_atomic_state *state`` intel atomic state h](j>)}(h$``struct intel_atomic_state *state``h]jD)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjZ)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhMhjubj8)}(h'``struct intel_crtc *crtc`` intel crtc h](j>)}(h``struct intel_crtc *crtc``h]jD)}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubjZ)}(hhh]h)}(h intel crtch]h intel crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1j7hjhM hjubj8)}(h``bool enable`` enable/disable h](j>)}(h``bool enable``h]jD)}(hj=h]h bool enable}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj;ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM!hj7ubjZ)}(hhh]h)}(henable/disableh]henable/disable}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhM!hjSubah}(h]h ]h"]h$]h&]uh1jYhj7ubeh}(h]h ]h"]h$]h&]uh1j7hjRhM!hjubeh}(h]h ]h"]h$]h&]uh1j2hjubh)}(h**Description**h]j)}(hjxh]h Description}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM#hjubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabledh]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chM"hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjW)}(hhh]h}(h]h ]h"]h$]h&]entries](jc3intel_psr_notify_vblank_enable_disable (C function)(c.intel_psr_notify_vblank_enable_disablehNtauh1jVhhhhhNhNubjh)}(hhh](jm)}(hXvoid intel_psr_notify_vblank_enable_disable (struct intel_display *display, bool enable)h]js)}(hWvoid intel_psr_notify_vblank_enable_disable(struct intel_display *display, bool enable)h](jy)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMRubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMRubj)}(h&intel_psr_notify_vblank_enable_disableh]j)}(h&intel_psr_notify_vblank_enable_disableh]h&intel_psr_notify_vblank_enable_disable}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMRubj)}(h,(struct intel_display *display, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j ]j )}jjsb(c.intel_psr_notify_vblank_enable_disableasbuh1hhjubj)}(h h]h }(hj8 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hj#h]h*}(hjF hhhNhNubah}(h]h ]j,ah"]h$]h&]uh1jhjubj)}(hdisplayh]hdisplay}(hjS hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h bool enableh](jy)}(hjh]hbool}(hjl hhhNhNubah}(h]h ]jah"]h$]h&]uh1jxhjh ubj)}(h h]h }(hjy hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjh ubj)}(henableh]henable}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjh ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMRubeh}(h]h ]h"]h$]h&]hhjuh1jrjjhjhhhjhMRubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jlhjhMRhjhhubj)}(hhh]h)}(h)Notify PSR about enable/disable of vblankh]h)Notify PSR about enable/disable of vblank}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMRhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMRubeh}(h]h ](jfunctioneh"]h$]h&]j jj j jj jjjuh1jghhhhhNhNubj)}(hX**Parameters** ``struct intel_display *display`` intel display struct ``bool enable`` enable/disable **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when vblank is getting enabled/disabledh](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMVhj ubj3)}(hhh](j8)}(h7``struct intel_display *display`` intel display struct h](j>)}(h!``struct intel_display *display``h]jD)}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: ./drivers/gpu/drm/i915/display/intel_psr.chMShj ubjZ)}(hhh]h)}(hintel display structh]hintel display struct}(hj !hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMShj!ubah}(h]h ]h"]h$]h&]uh1jYhj ubeh}(h]h ]h"]h$]h&]uh1j7hj!hMShj ubj8)}(h``bool enable`` enable/disable h](j>)}(h``bool enable``h]jD)}(hj+!h]h bool enable}(hj-!hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj)!ubah}(h]h ]h"]h$]h&]uh1j=hn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/psr:10: 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