sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget3/translations/zh_CN/gpu/intel-display/fifo-underrunmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/zh_TW/gpu/intel-display/fifo-underrunmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/it_IT/gpu/intel-display/fifo-underrunmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ja_JP/gpu/intel-display/fifo-underrunmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ko_KR/gpu/intel-display/fifo-underrunmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/pt_BR/gpu/intel-display/fifo-underrunmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/sp_SP/gpu/intel-display/fifo-underrunmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhM/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(hDisplay FIFO Underrun Reportingh]hDisplay FIFO Underrun Reporting}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThe i915 driver checks for display fifo underruns using the interrupt signals provided by the hardware. This is enabled by default and fairly useful to debug display issues, especially watermark settings.h]hThe i915 driver checks for display fifo underruns using the interrupt signals provided by the hardware. This is enabled by default and fairly useful to debug display issues, especially watermark settings.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:7: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK*hhhhubh)}(hIf an underrun is detected this is logged into dmesg. To avoid flooding logs and occupying the cpu underrun interrupts are disabled after the first occurrence until the next modeset on a given pipe.h]hIf an underrun is detected this is logged into dmesg. To avoid flooding logs and occupying the cpu underrun interrupts are disabled after the first occurrence until the next modeset on a given pipe.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:7: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK.hhhhubh)}(hXFNote that underrun detection on gmch platforms is a bit more ugly since there is no interrupt (despite that the signalling bit is in the PIPESTAT pipe interrupt register). Also on some other platforms underrun interrupts are shared, which means that if we detect an underrun we need to disable underrun reporting on all pipes.h]hXFNote that underrun detection on gmch platforms is a bit more ugly since there is no interrupt (despite that the signalling bit is in the PIPESTAT pipe interrupt register). Also on some other platforms underrun interrupts are shared, which means that if we detect an underrun we need to disable underrun reporting on all pipes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:7: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK2hhhhubh)}(h@The code also supports underrun detection on the PCH transcoder.h]h@The code also supports underrun detection on the PCH transcoder.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:7: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK8hhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single2intel_set_cpu_fifo_underrun_reporting (C function)'c.intel_set_cpu_fifo_underrun_reportinghNtauh1j)hhhhhNhNubhdesc)}(hhh](hdesc_signature)}(hgbool intel_set_cpu_fifo_underrun_reporting (struct intel_display *display, enum pipe pipe, bool enable)h]hdesc_signature_line)}(hfbool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable)h](hdesc_sig_keyword_type)}(hboolh]hbool}(hjMhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jKhjGhhh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMubhdesc_sig_space)}(h h]h }(hj_hhhNhNubah}(h]h ]wah"]h$]h&]uh1j]hjGhhhj\hMubh desc_name)}(h%intel_set_cpu_fifo_underrun_reportingh]h desc_sig_name)}(h%intel_set_cpu_fifo_underrun_reportingh]h%intel_set_cpu_fifo_underrun_reporting}(hjvhhhNhNubah}(h]h ]nah"]h$]h&]uh1jthjpubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jnhjGhhhj\hMubhdesc_parameterlist)}(h<(struct intel_display *display, enum pipe pipe, bool enable)h](hdesc_parameter)}(hstruct intel_display *displayh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jjxsb'c.intel_set_cpu_fifo_underrun_reportingasbuh1hhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhjubju)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum pipe pipeh](j)}(henumh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hj*hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(hpipeh]hpipe}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj8ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj=modnameN classnameNjj)}j]j'c.intel_set_cpu_fifo_underrun_reportingasbuh1hhjubj^)}(h h]h }(hjYhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubju)}(hpipeh]hpipe}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h bool enableh](jL)}(hjOh]hbool}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhj|ubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj|ubju)}(henableh]henable}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj|ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjGhhhj\hMubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1jEsphinx_line_type declaratorhjAhhhj\hMubah}(h]j8ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j?hj\hMhj<hhubh desc_content)}(hhh]h)}(h%set cpu fifo underrun reporting stateh]h%set cpu fifo underrun reporting state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj<hhhj\hMubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j:hhhhhNhNubh container)}(hXc**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pipe`` (CPU) pipe to set state for ``bool enable`` whether underruns should be reported or not **Description** This function sets the fifo underrun state for **pipe**. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe. Notice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though. Returns the previous state of underrun reporting.h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubhdefinition_list)}(hhh](hdefinition_list_item)}(h:``struct intel_display *display`` display device instance h](hterm)}(h!``struct intel_display *display``h]hliteral)}(hj h]hstruct intel_display *display}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubh definition)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj:ubah}(h]h ]h"]h$]h&]uh1j8hjubeh}(h]h ]h"]h$]h&]uh1jhj7hMhjubj)}(h/``enum pipe pipe`` (CPU) pipe to set state for h](j)}(h``enum pipe pipe``h]j#)}(hj]h]henum pipe pipe}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j"hj[ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjWubj9)}(hhh]h)}(h(CPU) pipe to set state forh]h(CPU) pipe to set state for}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjsubah}(h]h ]h"]h$]h&]uh1j8hjWubeh}(h]h ]h"]h$]h&]uh1jhjrhMhjubj)}(h<``bool enable`` whether underruns should be reported or not h](j)}(h``bool enable``h]j#)}(hjh]h bool enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubj9)}(hhh]h)}(h+whether underruns should be reported or noth]h+whether underruns should be reported or not}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j8hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubh)}(hThis function sets the fifo underrun state for **pipe**. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe.h](h/This function sets the fifo underrun state for }(hjhhhNhNubj)}(h**pipe**h]hpipe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubh)}(hNotice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though.h]hNotice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubh)}(h1Returns the previous state of underrun reporting.h]h1Returns the previous state of underrun reporting.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j62intel_set_pch_fifo_underrun_reporting (C function)'c.intel_set_pch_fifo_underrun_reportinghNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hqbool intel_set_pch_fifo_underrun_reporting (struct intel_display *display, enum pipe pch_transcoder, bool enable)h]jF)}(hpbool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable)h](jL)}(hjOh]hbool}(hjFhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjBhhh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMubj^)}(h h]h }(hjThhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjBhhhjShMubjo)}(h%intel_set_pch_fifo_underrun_reportingh]ju)}(h%intel_set_pch_fifo_underrun_reportingh]h%intel_set_pch_fifo_underrun_reporting}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjbubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjBhhhjShMubj)}(hF(struct intel_display *display, enum pipe pch_transcoder, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj~ubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjhsb'c.intel_set_pch_fifo_underrun_reportingasbuh1hhj~ubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj~ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubju)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj~ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjzubj)}(henum pipe pch_transcoderh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j'c.intel_set_pch_fifo_underrun_reportingasbuh1hhjubj^)}(h h]h }(hj0hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubju)}(hpch_transcoderh]hpch_transcoder}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjzubj)}(h bool enableh](jL)}(hjOh]hbool}(hjWhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjSubj^)}(h h]h }(hjdhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjSubju)}(henableh]henable}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjSubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjzubeh}(h]h ]h"]h$]h&]hhuh1jhjBhhhjShMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhj>hhhjShMubah}(h]j9ah ](jjeh"]h$]h&]jj)jhuh1j?hjShMhj;hhubj)}(hhh]h)}(h%set PCH fifo underrun reporting stateh]h%set PCH fifo underrun reporting state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj;hhhjShMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(hX**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) ``bool enable`` whether underruns should be reported or not **Description** This function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there's just one interrupt mask/enable bit for all the transcoders. Returns the previous state of underrun reporting.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubj)}(hhh](j)}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j#)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubj9)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j8hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hP``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) h](j)}(h``enum pipe pch_transcoder``h]j#)}(hjh]henum pipe pch_transcoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubj9)}(hhh]h)}(h2the PCH transcoder (same as pipe on IVB and older)h]h2the PCH transcoder (same as pipe on IVB and older)}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hMhj,ubah}(h]h ]h"]h$]h&]uh1j8hjubeh}(h]h ]h"]h$]h&]uh1jhj+hMhjubj)}(h<``bool enable`` whether underruns should be reported or not h](j)}(h``bool enable``h]j#)}(hjOh]h bool enable}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j"hjMubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjIubj9)}(hhh]h)}(h+whether underruns should be reported or noth]h+whether underruns should be reported or not}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjeubah}(h]h ]h"]h$]h&]uh1j8hjIubeh}(h]h ]h"]h$]h&]uh1jhjdhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubh)}(hX_This function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there's just one interrupt mask/enable bit for all the transcoders.h]hXaThis function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there’s just one interrupt mask/enable bit for all the transcoders.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubh)}(h1Returns the previous state of underrun reporting.h]h1Returns the previous state of underrun reporting.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j60intel_cpu_fifo_underrun_irq_handler (C function)%c.intel_cpu_fifo_underrun_irq_handlerhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hXvoid intel_cpu_fifo_underrun_irq_handler (struct intel_display *display, enum pipe pipe)h]jF)}(hWvoid intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pipe)h](jL)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhjhMubjo)}(h#intel_cpu_fifo_underrun_irq_handlerh]ju)}(h#intel_cpu_fifo_underrun_irq_handlerh]h#intel_cpu_fifo_underrun_irq_handler}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhjhMubj)}(h/(struct intel_display *display, enum pipe pipe)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hj(hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj6ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj;modnameN classnameNjj)}j]j)}jjsb%c.intel_cpu_fifo_underrun_irq_handlerasbuh1hhjubj^)}(h h]h }(hjYhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hjh]h*}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(hdisplayh]hdisplay}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum pipe pipeh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubh)}(hhh]ju)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jU%c.intel_cpu_fifo_underrun_irq_handlerasbuh1hhjubj^)}(h h]h }(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubju)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hjhMhjhhubj)}(hhh]h)}(h"handle CPU fifo underrun interrupth]h"handle CPU fifo underrun interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j:hhhhhNhNubj)}(hXF**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pipe`` (CPU) pipe to set state for **Description** This handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h](h)}(h**Parameters**h]j)}(hj#h]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubj)}(hhh](j)}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j#)}(hjBh]hstruct intel_display *display}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j"hj@ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj<ubj9)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhMhjXubah}(h]h ]h"]h$]h&]uh1j8hj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhMhj9ubj)}(h/``enum pipe pipe`` (CPU) pipe to set state for h](j)}(h``enum pipe pipe``h]j#)}(hj{h]henum pipe pipe}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j"hjyubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjuubj9)}(hhh]h)}(h(CPU) pipe to set state forh]h(CPU) pipe to set state for}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j8hjuubeh}(h]h ]h"]h$]h&]uh1jhjhMhj9ubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubh)}(hThis handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h]hThis handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j60intel_pch_fifo_underrun_irq_handler (C function)%c.intel_pch_fifo_underrun_irq_handlerhNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hbvoid intel_pch_fifo_underrun_irq_handler (struct intel_display *display, enum pipe pch_transcoder)h]jF)}(havoid intel_pch_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pch_transcoder)h](jL)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjhhhj hMubjo)}(h#intel_pch_fifo_underrun_irq_handlerh]ju)}(h#intel_pch_fifo_underrun_irq_handlerh]h#intel_pch_fifo_underrun_irq_handler}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubah}(h]h ](jjeh"]h$]h&]hhuh1jnhjhhhj hMubj)}(h9(struct intel_display *display, enum pipe pch_transcoder)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj8 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4 ubj^)}(h h]h }(hjE hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj4 ubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hjV hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjS ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjX modnameN classnameNjj)}j]j)}jj sb%c.intel_pch_fifo_underrun_irq_handlerasbuh1hhj4 ubj^)}(h h]h }(hjv hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj4 ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4 ubju)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj4 ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj0 ubj)}(henum pipe pch_transcoderh](j)}(hjh]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubh)}(hhh]ju)}(hpipeh]hpipe}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jr %c.intel_pch_fifo_underrun_irq_handlerasbuh1hhj ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubju)}(hpch_transcoderh]hpch_transcoder}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj0 ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj hMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhjhhhj hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j?hj hMhjhhubj)}(hhh]h)}(h"handle PCH fifo underrun interrupth]h"handle PCH fifo underrun interrupt}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj6 jj6 jjjuh1j:hhhhhNhNubj)}(hXg**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) **Description** This handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h](h)}(h**Parameters**h]j)}(hj@ h]h Parameters}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj> ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj: ubj)}(hhh](j)}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j#)}(hj_ h]hstruct intel_display *display}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1j"hj] ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjY ubj9)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt hMhju ubah}(h]h ]h"]h$]h&]uh1j8hjY ubeh}(h]h ]h"]h$]h&]uh1jhjt hMhjV ubj)}(hP``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) h](j)}(h``enum pipe pch_transcoder``h]j#)}(hj h]henum pipe pch_transcoder}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j"hj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj ubj9)}(hhh]h)}(h2the PCH transcoder (same as pipe on IVB and older)h]h2the PCH transcoder (same as pipe on IVB and older)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j8hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjV ubeh}(h]h ]h"]h$]h&]uh1jhj: ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj: ubh)}(hThis handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h]hThis handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj: ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6+intel_check_cpu_fifo_underruns (C function) c.intel_check_cpu_fifo_underrunshNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hCvoid intel_check_cpu_fifo_underruns (struct intel_display *display)h]jF)}(hBvoid intel_check_cpu_fifo_underruns(struct intel_display *display)h](jL)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhj hhh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMubj^)}(h h]h }(hj' hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj hhhj& hMubjo)}(hintel_check_cpu_fifo_underrunsh]ju)}(hintel_check_cpu_fifo_underrunsh]hintel_check_cpu_fifo_underruns}(hj9 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5 ubah}(h]h ](jjeh"]h$]h&]hhuh1jnhj hhhj& hMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjU hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ ubj^)}(h h]h }(hjb hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjQ ubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hjs hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjp ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetju modnameN classnameNjj)}j]j)}jj; sb c.intel_check_cpu_fifo_underrunsasbuh1hhjQ ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjQ ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ ubju)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjQ ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjM ubah}(h]h ]h"]h$]h&]hhuh1jhj hhhj& hMubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhj hhhj& hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j?hj& hMhj hhubj)}(hhh]h)}(h(check for CPU fifo underruns immediatelyh]h(check for CPU fifo underruns immediately}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj& hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1j:hhhhhNhNubj)}(hXR**Parameters** ``struct intel_display *display`` display device instance **Description** Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared error interrupt may have been disabled, and so CPU fifo underruns won't necessarily raise an interrupt, and on GMCH platforms where underruns never raise an interrupt.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj ubj)}(hhh]j)}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j#)}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j"hj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj ubj9)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj. hMhj/ ubah}(h]h ]h"]h$]h&]uh1j8hj ubeh}(h]h ]h"]h$]h&]uh1jhj. hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hjT h]h Description}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj ubh)}(hCheck for CPU fifo underruns immediately. Useful on IVB/HSW where the shared error interrupt may have been disabled, and so CPU fifo underruns won't necessarily raise an interrupt, and on GMCH platforms where underruns never raise an interrupt.h]hCheck for CPU fifo underruns immediately. Useful on IVB/HSW where the shared error interrupt may have been disabled, and so CPU fifo underruns won’t necessarily raise an interrupt, and on GMCH platforms where underruns never raise an interrupt.}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj*)}(hhh]h}(h]h ]h"]h$]h&]entries](j6+intel_check_pch_fifo_underruns (C function) c.intel_check_pch_fifo_underrunshNtauh1j)hhhhhNhNubj;)}(hhh](j@)}(hCvoid intel_check_pch_fifo_underruns (struct intel_display *display)h]jF)}(hBvoid intel_check_pch_fifo_underruns(struct intel_display *display)h](jL)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jXah"]h$]h&]uh1jKhj hhh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj hhhj hM ubjo)}(hintel_check_pch_fifo_underrunsh]ju)}(hintel_check_pch_fifo_underrunsh]hintel_check_pch_fifo_underruns}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubah}(h]h ](jjeh"]h$]h&]hhuh1jnhj hhhj hM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubh)}(hhh]ju)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jj sb c.intel_check_pch_fifo_underrunsasbuh1hhj ubj^)}(h h]h }(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]h*}(hj" hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubju)}(hdisplayh]hdisplay}(hj/ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubah}(h]h ]h"]h$]h&]hhuh1jhj hhhj hM ubeh}(h]h ]h"]h$]h&]hhjuh1jEjjhj hhhj hM ubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j?hj hM hj hhubj)}(hhh]h)}(h(check for PCH fifo underruns immediatelyh]h(check for PCH fifo underruns immediately}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM hjV hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjq jjq jjjuh1j:hhhhhNhNubj)}(hX**Parameters** ``struct intel_display *display`` display device instance **Description** Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won't necessarily raise an interrupt.h](h)}(h**Parameters**h]j)}(hj{ h]h Parameters}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM$hju ubj)}(hhh]j)}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j#)}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j"hj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM!hj ubj9)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM!hj ubah}(h]h ]h"]h$]h&]uh1j8hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM!hj ubah}(h]h ]h"]h$]h&]uh1jhju ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fifo-underrun:10: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM#hju ubh)}(hCheck for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won't necessarily raise an interrupt.h]hCheck for PCH fifo underruns immediately. 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