sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget)/translations/zh_CN/gpu/intel-display/fbcmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/zh_TW/gpu/intel-display/fbcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/it_IT/gpu/intel-display/fbcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ja_JP/gpu/intel-display/fbcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ko_KR/gpu/intel-display/fbcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/pt_BR/gpu/intel-display/fbcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/sp_SP/gpu/intel-display/fbcmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhC/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(hFrame Buffer Compression (FBC)h]hFrame Buffer Compression (FBC)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hFBC tries to save memory bandwidth (and so power consumption) by compressing the amount of memory used by the display. It is total transparent to user space and completely handled in the kernel.h]hFBC tries to save memory bandwidth (and so power consumption) by compressing the amount of memory used by the display. It is total transparent to user space and completely handled in the kernel.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:7: ./drivers/gpu/drm/i915/display/intel_fbc.chKhhhhubh)}(hThe benefits of FBC are mostly visible with solid backgrounds and variation-less patterns. It comes from keeping the memory footprint small and having fewer memory pages opened and accessed for refreshing the display.h]hThe benefits of FBC are mostly visible with solid backgrounds and variation-less patterns. It comes from keeping the memory footprint small and having fewer memory pages opened and accessed for refreshing the display.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:7: ./drivers/gpu/drm/i915/display/intel_fbc.chKhhhhubh)}(hi915 is responsible to reserve stolen memory for FBC and configure its offset on proper registers. The hardware takes care of all compress/decompress. However there are many known cases where we have to forcibly disable it to allow proper screen updates.h]hi915 is responsible to reserve stolen memory for FBC and configure its offset on proper registers. The hardware takes care of all compress/decompress. However there are many known cases where we have to forcibly disable it to allow proper screen updates.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:7: ./drivers/gpu/drm/i915/display/intel_fbc.chK!hhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleintel_fbc_disable (C function)c.intel_fbc_disablehNtauh1jhhhhhNhNubhdesc)}(hhh](hdesc_signature)}(h0void intel_fbc_disable (struct intel_crtc *crtc)h]hdesc_signature_line)}(h/void intel_fbc_disable(struct intel_crtc *crtc)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hj>hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j<hj8hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chM)ubhdesc_sig_space)}(h h]h }(hjPhhhNhNubah}(h]h ]wah"]h$]h&]uh1jNhj8hhhjMhM)ubh desc_name)}(hintel_fbc_disableh]h desc_sig_name)}(hintel_fbc_disableh]hintel_fbc_disable}(hjghhhNhNubah}(h]h ]nah"]h$]h&]uh1jehjaubah}(h]h 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associated with crtch]h*disable FBC if it’s associated with crtc}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chM)hj%hhubah}(h]h ]h"]h$]h&]uh1j#hj-hhhjMhM)ubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypej@desctypej@noindex noindexentrynocontentsentryuh1j+hhhhhNhNubh container)}(h**Parameters** ``struct intel_crtc *crtc`` the CRTC **Description** This function disables FBC if it's associated with the provided CRTC.h](h)}(h**Parameters**h]hstrong)}(hjRh]h Parameters}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjPubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chM-hjLubhdefinition_list)}(hhh]hdefinition_list_item)}(h%``struct intel_crtc *crtc`` the CRTC h](hterm)}(h``struct intel_crtc *crtc``h]hliteral)}(hjyh]hstruct intel_crtc *crtc}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j{hjwubah}(h]h ]h"]h$]h&]uh1juhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chM*hjqubh definition)}(hhh]h)}(hthe CRTCh]hthe CRTC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM*hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1johjhM*hjlubah}(h]h ]h"]h$]h&]uh1jjhjLubh)}(h**Description**h]jU)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chM,hjLubh)}(hEThis function disables FBC if it's associated with the provided CRTC.h]hGThis function disables FBC if it’s associated with the provided CRTC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chM+hjLubeh}(h]h ] kernelindentah"]h$]h&]uh1jJhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'/intel_fbc_handle_fifo_underrun_irq (C function)$c.intel_fbc_handle_fifo_underrun_irqhNtauh1jhhhhhNhNubj,)}(hhh](j1)}(hGvoid intel_fbc_handle_fifo_underrun_irq (struct intel_display *display)h]j7)}(hFvoid intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)h](j=)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jIah"]h$]h&]uh1j<hjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMubjO)}(h h]h }(hj hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjhhhj hMubj`)}(h"intel_fbc_handle_fifo_underrun_irqh]jf)}(h"intel_fbc_handle_fifo_underrun_irqh]h"intel_fbc_handle_fifo_underrun_irq}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ](jyjzeh"]h$]h&]hhuh1j_hjhhhj hMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubjO)}(h h]h }(hjGhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj6ubh)}(hhh]jf)}(h intel_displayh]h intel_display}(hjXhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjZmodnameN classnameNjj)}j]j)}jj sb$c.intel_fbc_handle_fifo_underrun_irqasbuh1hhj6ubjO)}(h h]h }(hjxhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj6ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubjf)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj6ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubah}(h]h ]h"]h$]h&]hhuh1j~hjhhhj hMubeh}(h]h ]h"]h$]h&]hhjuh1j6jjhjhhhj hMubah}(h]jah ](jjeh"]h$]h&]j j!)j"huh1j0hj hMhjhhubj$)}(hhh]h)}(h'disable FBC when we get a FIFO underrunh]h'disable FBC when we get a FIFO underrun}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j#hjhhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jDjjEjjFjjGjHjIuh1j+hhhhhNhNubjK)}(hX=**Parameters** ``struct intel_display *display`` display **Description** Without FBC, most underruns are harmless and don't really cause too many problems, except for an annoying message on dmesg. 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This function is called from the IRQ handler.h](h)}(h**Parameters**h]jU)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubjk)}(hhh]jp)}(h*``struct intel_display *display`` display h](jv)}(h!``struct intel_display *display``h]j|)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hjubah}(h]h ]h"]h$]h&]uh1juhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubj)}(hhh]h)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1johjhMhjubah}(h]h ]h"]h$]h&]uh1jjhjubh)}(h**Description**h]jU)}(hj9h]h Description}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj7ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubh)}(hXWithout FBC, most underruns are harmless and don't really cause too many problems, except for an annoying message on dmesg. With FBC, underruns can become black screens or even worse, especially when paired with bad watermarks. So in order for us to be on the safe side, completely disable FBC in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe already suggests that watermarks may be bad, so try to be as safe as possible.h]hXWithout FBC, most underruns are harmless and don’t really cause too many problems, except for an annoying message on dmesg. With FBC, underruns can become black screens or even worse, especially when paired with bad watermarks. So in order for us to be on the safe side, completely disable FBC in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe already suggests that watermarks may be bad, so try to be as safe as possible.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubh)}(h-This function is called from the IRQ handler.h]h-This function is called from the IRQ handler.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jJhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'-intel_fbc_read_underrun_dbg_info (C function)"c.intel_fbc_read_underrun_dbg_infohNtauh1jhhhhhNhNubj,)}(hhh](j1)}(h_void intel_fbc_read_underrun_dbg_info (struct intel_display *display, enum pipe pipe, bool log)h]j7)}(h^void intel_fbc_read_underrun_dbg_info(struct intel_display *display, enum pipe pipe, bool log)h](j=)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jIah"]h$]h&]uh1j<hjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjhhhjhMubj`)}(h intel_fbc_read_underrun_dbg_infoh]jf)}(h intel_fbc_read_underrun_dbg_infoh]h intel_fbc_read_underrun_dbg_info}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ](jyjzeh"]h$]h&]hhuh1j_hjhhhjhMubj)}(h9(struct intel_display *display, enum pipe pipe, bool log)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubh)}(hhh]jf)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb"c.intel_fbc_read_underrun_dbg_infoasbuh1hhjubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjf)}(hdisplayh]hdisplay}(hj#hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum pipe pipeh](j)}(henumh]henum}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubjO)}(h h]h }(hjJhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj8ubh)}(hhh]jf)}(hpipeh]hpipe}(hj[hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjXubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj]modnameN classnameNjj)}j]j"c.intel_fbc_read_underrun_dbg_infoasbuh1hhj8ubjO)}(h h]h }(hjyhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj8ubjf)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj8ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hbool logh](j=)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]jIah"]h$]h&]uh1j<hjubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubjf)}(hlogh]hlog}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1j~hjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1j6jjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]j j!)j"huh1j0hjhMhjhhubj$)}(hhh]h)}(h1Read and log FBC-related FIFO underrun debug infoh]h1Read and log FBC-related FIFO underrun debug info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j#hjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jDjjEjjFjjGjHjIuh1j+hhhhhNhNubjK)}(hXq**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pipe`` the pipe possibly containing the FBC ``bool log`` log the info? **Description** If **pipe** does not contain an FBC instance, this function bails early. Otherwise, FBC-related FIFO underrun is read and cleared, and then, if **log** is true, printed with error level.h](h)}(h**Parameters**h]jU)}(hjh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubjk)}(hhh](jp)}(h:``struct intel_display *display`` display device instance h](jv)}(h!``struct intel_display *display``h]j|)}(hj'h]hstruct intel_display *display}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j{hj%ubah}(h]h ]h"]h$]h&]uh1juhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhj!ubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1johj<hMhjubjp)}(h8``enum pipe pipe`` the pipe possibly containing the FBC h](jv)}(h``enum pipe pipe``h]j|)}(hj`h]henum pipe pipe}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hj^ubah}(h]h ]h"]h$]h&]uh1juhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjZubj)}(hhh]h)}(h$the pipe possibly containing the FBCh]h$the pipe possibly containing the FBC}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1johjuhMhjubjp)}(h``bool log`` log the info? h](jv)}(h ``bool log``h]j|)}(hjh]hbool log}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j{hjubah}(h]h ]h"]h$]h&]uh1juhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubj)}(hhh]h)}(h log the info?h]h log the info?}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1johjhMhjubeh}(h]h ]h"]h$]h&]uh1jjhjubh)}(h**Description**h]jU)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubh)}(hIf **pipe** does not contain an FBC instance, this function bails early. Otherwise, FBC-related FIFO underrun is read and cleared, and then, if **log** is true, printed with error level.h](hIf }(hjhhhNhNubjU)}(h**pipe**h]hpipe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh does not contain an FBC instance, this function bails early. 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ubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjhhhjhM; ubj`)}(hintel_fbc_sanitizeh]jf)}(hintel_fbc_sanitizeh]hintel_fbc_sanitize}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ](jyjzeh"]h$]h&]hhuh1j_hjhhhjhM; ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjO)}(h h]h }(hj hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubh)}(hhh]jf)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jjsbc.intel_fbc_sanitizeasbuh1hhjubjO)}(h h]h }(hj9 hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubj)}(hjh]h*}(hjG hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjf)}(hdisplayh]hdisplay}(hjT hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1j~hjhhhjhM; ubeh}(h]h ]h"]h$]h&]hhjuh1j6jjhjhhhjhM; ubah}(h]jah ](jjeh"]h$]h&]j j!)j"huh1j0hjhM; hjhhubj$)}(hhh]h)}(h Sanitize FBCh]h Sanitize FBC}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/fbc:10: ./drivers/gpu/drm/i915/display/intel_fbc.chM; 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