lsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget)/translations/zh_CN/gpu/intel-display/dsbmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/zh_TW/gpu/intel-display/dsbmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/it_IT/gpu/intel-display/dsbmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ja_JP/gpu/intel-display/dsbmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ko_KR/gpu/intel-display/dsbmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/pt_BR/gpu/intel-display/dsbmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/sp_SP/gpu/intel-display/dsbmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhC/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(hDisplay State Bufferh]hDisplay State Buffer}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXA DSB (Display State Buffer) is a queue of MMIO instructions in the memory which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA engine that can be programmed to download the DSB from memory. It allows driver to batch submit display HW programming. This helps to reduce loading time and CPU activity, thereby making the context switch faster. DSB Support added from Gen12 Intel graphics based platform.h]hXA DSB (Display State Buffer) is a queue of MMIO instructions in the memory which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA engine that can be programmed to download the DSB from memory. It allows driver to batch submit display HW programming. This helps to reduce loading time and CPU activity, thereby making the context switch faster. DSB Support added from Gen12 Intel graphics based platform.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:7: ./drivers/gpu/drm/i915/display/intel_dsb.chK?hhhhubh)}(hSDSB's can access only the pipe, plane, and transcoder Data Island Packet registers.h]hUDSB’s can access only the pipe, plane, and transcoder Data Island Packet registers.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:7: ./drivers/gpu/drm/i915/display/intel_dsb.chKFhhhhubh)}(hDSB HW can support only register writes (both indexed and direct MMIO writes). There are no registers reads possible with DSB HW engine.h]hDSB HW can support only register writes (both indexed and direct MMIO writes). There are no registers reads possible with DSB HW engine.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:7: ./drivers/gpu/drm/i915/display/intel_dsb.chKIhhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single(intel_dsb_reg_write_indexed (C function)c.intel_dsb_reg_write_indexedhNtauh1jhhhhhNhNubhdesc)}(hhh](hdesc_signature)}(hRvoid intel_dsb_reg_write_indexed (struct intel_dsb *dsb, intel_reg_t reg, u32 val)h]hdesc_signature_line)}(hQvoid intel_dsb_reg_write_indexed(struct intel_dsb *dsb, intel_reg_t reg, u32 val)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hj>hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j<hj8hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMoubhdesc_sig_space)}(h h]h }(hjPhhhNhNubah}(h]h ]wah"]h$]h&]uh1jNhj8hhhjMhMoubh desc_name)}(hintel_dsb_reg_write_indexedh]h desc_sig_name)}(hintel_dsb_reg_write_indexedh]hintel_dsb_reg_write_indexed}(hjghhhNhNubah}(h]h ]nah"]h$]h&]uh1jehjaubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1j_hj8hhhjMhMoubhdesc_parameterlist)}(h1(struct intel_dsb *dsb, intel_reg_t reg, u32 val)h](hdesc_parameter)}(hstruct intel_dsb *dsbh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubh)}(hhh]jf)}(h intel_dsbh]h intel_dsb}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jjisbc.intel_dsb_reg_write_indexedasbuh1hhjubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhjubjf)}(hdsbh]hdsb}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hintel_reg_t regh](h)}(hhh]jf)}(h intel_reg_th]h intel_reg_t}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.intel_dsb_reg_write_indexedasbuh1hhj ubjO)}(h h]h }(hj.hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj ubjf)}(hregh]hreg}(hj<hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hu32 valh](h)}(hhh]jf)}(hu32h]hu32}(hjXhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjZmodnameN classnameNjj)}j]jc.intel_dsb_reg_write_indexedasbuh1hhjQubjO)}(h h]h }(hjvhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjQubjf)}(hvalh]hval}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjQubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1j~hj8hhhjMhMoubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1j6sphinx_line_type declaratorhj2hhhjMhMoubah}(h]j)ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j0hjMhMohj-hhubh desc_content)}(hhh]h)}(h.Emit indexed register write to the DSB contexth]h.Emit indexed register write to the DSB context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMohjhhubah}(h]h ]h"]h$]h&]uh1jhj-hhhjMhMoubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j+hhhhhNhNubh container)}(hX\**Parameters** ``struct intel_dsb *dsb`` DSB context ``intel_reg_t reg`` register address. ``u32 val`` value. **Description** This function is used for writing register-value pair in command buffer of DSB. Note that indexed writes are slower than normal MMIO writes for a small number (less than 5 or so) of writes to the same register.h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMshjubhdefinition_list)}(hhh](hdefinition_list_item)}(h&``struct intel_dsb *dsb`` DSB context h](hterm)}(h``struct intel_dsb *dsb``h]hliteral)}(hj h]hstruct intel_dsb *dsb}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMphjubh definition)}(hhh]h)}(h DSB contexth]h DSB context}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMphj#ubah}(h]h ]h"]h$]h&]uh1j!hjubeh}(h]h ]h"]h$]h&]uh1jhj hMphjubj)}(h&``intel_reg_t reg`` register address. h](j)}(h``intel_reg_t reg``h]j )}(hjFh]hintel_reg_t reg}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjDubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMqhj@ubj")}(hhh]h)}(hregister address.h]hregister address.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hMqhj\ubah}(h]h ]h"]h$]h&]uh1j!hj@ubeh}(h]h ]h"]h$]h&]uh1jhj[hMqhjubj)}(h``u32 val`` value. h](j)}(h ``u32 val``h]j )}(hjh]hu32 val}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj}ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMrhjyubj")}(hhh]h)}(hvalue.h]hvalue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMrhjubah}(h]h ]h"]h$]h&]uh1j!hjyubeh}(h]h ]h"]h$]h&]uh1jhjhMrhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMthjubh)}(hOThis function is used for writing register-value pair in command buffer of DSB.h]hOThis function is used for writing register-value pair in command buffer of DSB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMshjubh)}(hNote that indexed writes are slower than normal MMIO writes for a small number (less than 5 or so) of writes to the same register.h]hNote that indexed writes are slower than normal MMIO writes for a small number (less than 5 or so) of writes to the same register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMvhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'intel_dsb_commit (C function)c.intel_dsb_commithNtauh1jhhhhhNhNubj,)}(hhh](j1)}(h-void intel_dsb_commit (struct intel_dsb *dsb)h]j7)}(h,void intel_dsb_commit(struct intel_dsb *dsb)h](j=)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jIah"]h$]h&]uh1j<hj hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj hhhjhMubj`)}(hintel_dsb_commith]jf)}(hintel_dsb_commith]hintel_dsb_commit}(hj/hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj+ubah}(h]h ](jyjzeh"]h$]h&]hhuh1j_hj hhhjhMubj)}(h(struct intel_dsb *dsb)h]j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubjO)}(h h]h }(hjXhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjGubh)}(hhh]jf)}(h intel_dsbh]h intel_dsb}(hjihhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjfubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjkmodnameN classnameNjj)}j]j)}jj1sbc.intel_dsb_commitasbuh1hhjGubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjGubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubjf)}(hdsbh]hdsb}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjGubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjCubah}(h]h ]h"]h$]h&]hhuh1j~hj hhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1j6jjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j0hjhMhjhhubj)}(hhh]h)}(h"Trigger workload execution of DSB.h]h"Trigger workload execution of DSB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j+hhhhhNhNubj)}(h**Parameters** ``struct intel_dsb *dsb`` DSB context **Description** This function is used to do actual write to hardware using DSB.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjubj)}(hhh]j)}(h&``struct intel_dsb *dsb`` DSB context h](j)}(h``struct intel_dsb *dsb``h]j )}(hjh]hstruct intel_dsb *dsb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj ubj")}(hhh]h)}(h DSB contexth]h DSB context}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMhj%ubah}(h]h ]h"]h$]h&]uh1j!hj ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjJh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjubh)}(h?This function is used to do actual write to hardware using DSB.h]h?This function is used to do actual write to hardware using DSB.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'intel_dsb_prepare (C function)c.intel_dsb_preparehNtauh1jhhhhhNhNubj,)}(hhh](j1)}(hstruct intel_dsb * intel_dsb_prepare (struct intel_atomic_state *state, struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds)h]j7)}(hstruct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjhhhjhMubh)}(hhh]jf)}(h intel_dsbh]h intel_dsb}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jintel_dsb_preparesbc.intel_dsb_prepareasbuh1hhjhhhjhMubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjhhhjhMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj`)}(hintel_dsb_prepareh]jf)}(hjh]hintel_dsb_prepare}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ](jyjzeh"]h$]h&]hhuh1j_hjhhhjhMubj)}(hl(struct intel_atomic_state *state, struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubh)}(hhh]jf)}(hintel_atomic_stateh]hintel_atomic_state}(hj'hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj$ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj)modnameN classnameNjj)}j]jc.intel_dsb_prepareasbuh1hhjubjO)}(h h]h }(hjEhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubj)}(hjh]h*}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjf)}(hstateh]hstate}(hj`hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjuubh)}(hhh]jf)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.intel_dsb_prepareasbuh1hhjuubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjuubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubjf)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjuubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum intel_dsb_id dsb_idh](j)}(henumh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjO)}(h h]h }(hjhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubh)}(hhh]jf)}(h intel_dsb_idh]h intel_dsb_id}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jc.intel_dsb_prepareasbuh1hhjubjO)}(h h]h }(hj&hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjubjf)}(hdsb_idh]hdsb_id}(hj4hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int max_cmdsh](j=)}(hunsignedh]hunsigned}(hjMhhhNhNubah}(h]h ]jIah"]h$]h&]uh1j<hjIubjO)}(h h]h }(hj[hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjIubj=)}(hinth]hint}(hjihhhNhNubah}(h]h ]jIah"]h$]h&]uh1j<hjIubjO)}(h h]h }(hjwhhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhjIubjf)}(hmax_cmdsh]hmax_cmds}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehjIubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1j~hjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1j6jjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j0hjhMhjhhubj)}(hhh]h)}(h-Allocate, pin and map the DSB command buffer.h]h-Allocate, pin and map the DSB command buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j+hhhhhNhNubj)}(hX**Parameters** ``struct intel_atomic_state *state`` the atomic state ``struct intel_crtc *crtc`` the CRTC ``enum intel_dsb_id dsb_id`` the DSB engine to use ``unsigned int max_cmds`` number of commands we need to fit into command buffer **Description** This function prepare the command buffer which is used to store dsb instructions with data. **Return** DSB context, NULL on failureh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chM hjubj)}(hhh](j)}(h6``struct intel_atomic_state *state`` the atomic state h](j)}(h$``struct intel_atomic_state *state``h]j )}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjubj")}(hhh]h)}(hthe atomic stateh]hthe atomic state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j!hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h%``struct intel_crtc *crtc`` the CRTC h](j)}(h``struct intel_crtc *crtc``h]j )}(hj)h]hstruct intel_crtc *crtc}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj'ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj#ubj")}(hhh]h)}(hthe CRTCh]hthe CRTC}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj?ubah}(h]h ]h"]h$]h&]uh1j!hj#ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhjubj)}(h3``enum intel_dsb_id dsb_id`` the DSB engine to use h](j)}(h``enum intel_dsb_id dsb_id``h]j )}(hjbh]henum intel_dsb_id dsb_id}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj`ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj\ubj")}(hhh]h)}(hthe DSB engine to useh]hthe DSB engine to use}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMhjxubah}(h]h ]h"]h$]h&]uh1j!hj\ubeh}(h]h ]h"]h$]h&]uh1jhjwhMhjubj)}(hP``unsigned int max_cmds`` number of commands we need to fit into command buffer h](j)}(h``unsigned int max_cmds``h]j )}(hjh]hunsigned int max_cmds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chM hjubj")}(hhh]h)}(h5number of commands we need to fit into command bufferh]h5number of commands we need to fit into command buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j!hjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chM hjubh)}(h[This function prepare the command buffer which is used to store dsb instructions with data.h]h[This function prepare the command buffer which is used to store dsb instructions with data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chM hjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chM hjubh)}(hDSB context, NULL on failureh]hDSB context, NULL on failure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'intel_dsb_cleanup (C function)c.intel_dsb_cleanuphNtauh1jhhhhhNhNubj,)}(hhh](j1)}(h.void intel_dsb_cleanup (struct intel_dsb *dsb)h]j7)}(h-void intel_dsb_cleanup(struct intel_dsb *dsb)h](j=)}(hvoidh]hvoid}(hjB hhhNhNubah}(h]h ]jIah"]h$]h&]uh1j<hj> hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMIubjO)}(h h]h }(hjQ hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj> hhhjP hMIubj`)}(hintel_dsb_cleanuph]jf)}(hintel_dsb_cleanuph]hintel_dsb_cleanup}(hjc hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj_ ubah}(h]h ](jyjzeh"]h$]h&]hhuh1j_hj> hhhjP hMIubj)}(h(struct intel_dsb *dsb)h]j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubjO)}(h h]h }(hj hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj{ ubh)}(hhh]jf)}(h intel_dsbh]h intel_dsb}(hj hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jje sbc.intel_dsb_cleanupasbuh1hhj{ ubjO)}(h h]h }(hj hhhNhNubah}(h]h ]j[ah"]h$]h&]uh1jNhj{ ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubjf)}(hdsbh]hdsb}(hj hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jehj{ ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjw ubah}(h]h ]h"]h$]h&]hhuh1j~hj> hhhjP hMIubeh}(h]h ]h"]h$]h&]hhjuh1j6jjhj: hhhjP hMIubah}(h]j5 ah ](jjeh"]h$]h&]jj)jhuh1j0hjP hMIhj7 hhubj)}(hhh]h)}(hTo cleanup DSB context.h]hTo cleanup DSB context.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMIhj hhubah}(h]h ]h"]h$]h&]uh1jhj7 hhhjP hMIubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1j+hhhhhNhNubj)}(h**Parameters** ``struct intel_dsb *dsb`` DSB context **Description** This function cleanup the DSB context by unpinning and releasing the VMA object associated with it.h](h)}(h**Parameters**h]j)}(hj$ h]h Parameters}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj" ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMMhj ubj)}(hhh]j)}(h&``struct intel_dsb *dsb`` DSB context h](j)}(h``struct intel_dsb *dsb``h]j )}(hjC h]hstruct intel_dsb *dsb}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjA ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMJhj= ubj")}(hhh]h)}(h DSB contexth]h DSB context}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjX hMJhjY ubah}(h]h ]h"]h$]h&]uh1j!hj= ubeh}(h]h ]h"]h$]h&]uh1jhjX hMJhj: ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hj~ h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj| ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dsb:10: ./drivers/gpu/drm/i915/display/intel_dsb.chMLhj ubh)}(hcThis function cleanup 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