sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/gpu/intel-display/dpllmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/gpu/intel-display/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/gpu/intel-display/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/gpu/intel-display/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/gpu/intel-display/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/pt_BR/gpu/intel-display/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/gpu/intel-display/dpllmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(h Display PLLsh]h Display PLLs}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXDisplay PLLs used for driving outputs vary by platform. While some have per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL from a pool. In the latter scenario, it is possible that multiple pipes share a PLL if their configurations match.h]hXDisplay PLLs used for driving outputs vary by platform. While some have per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL from a pool. In the latter scenario, it is possible that multiple pipes share a PLL if their configurations match.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:7: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chK0hhhhubh)}(hXEThis file provides an abstraction over display PLLs. The function intel_dpll_init() initializes the PLLs for the given platform. The users of a PLL are tracked and that tracking is integrated with the atomic modset interface. During an atomic operation, required PLLs can be reserved for a given CRTC and encoder configuration by calling intel_dpll_reserve() and previously reserved PLLs can be released with intel_dpll_release(). Changes to the users are first staged in the atomic state, and then made effective by calling intel_dpll_swap_state() during the atomic commit phase.h]hXEThis file provides an abstraction over display PLLs. The function intel_dpll_init() initializes the PLLs for the given platform. The users of a PLL are tracked and that tracking is integrated with the atomic modset interface. During an atomic operation, required PLLs can be reserved for a given CRTC and encoder configuration by calling intel_dpll_reserve() and previously reserved PLLs can be released with intel_dpll_release(). Changes to the users are first staged in the atomic state, and then made effective by calling intel_dpll_swap_state() during the atomic commit phase.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:7: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chK5hhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single!intel_get_dpll_by_id (C function)c.intel_get_dpll_by_idhNtauh1j hhhhhNhNubhdesc)}(hhh](hdesc_signature)}(h_struct intel_dpll * intel_get_dpll_by_id (struct intel_display *display, enum intel_dpll_id id)h]hdesc_signature_line)}(h]struct intel_dpll *intel_get_dpll_by_id(struct intel_display *display, enum intel_dpll_id id)h](hdesc_sig_keyword)}(hstructh]hstruct}(hj/hhhNhNubah}(h]h ]kah"]h$]h&]uh1j-hj)hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKubhdesc_sig_space)}(h h]h }(hjAhhhNhNubah}(h]h ]wah"]h$]h&]uh1j?hj)hhhj>hKubh)}(hhh]h desc_sig_name)}(h intel_dpllh]h intel_dpll}(hjUhhhNhNubah}(h]h ]nah"]h$]h&]uh1jShjPubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjWmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]jr ASTIdentifier)}jmintel_get_dpll_by_idsbc.intel_get_dpll_by_idasbuh1hhj)hhhj>hKubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj)hhhj>hKubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhj)hhhj>hKubh desc_name)}(hintel_get_dpll_by_idh]jT)}(hj}h]hintel_get_dpll_by_id}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhj)hhhj>hKubhdesc_parameterlist)}(h6(struct intel_display *display, enum intel_dpll_id id)h](hdesc_parameter)}(hstruct intel_display *displayh](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]j{c.intel_get_dpll_by_idasbuh1hhjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum intel_dpll_id idh](j.)}(henumh]henum}(hj6hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj2ubj@)}(h h]h }(hjDhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj2ubh)}(hhh]jT)}(h intel_dpll_idh]h intel_dpll_id}(hjUhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjRubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjWmodnameN classnameNjqjt)}jw]j{c.intel_get_dpll_by_idasbuh1hhj2ubj@)}(h h]h }(hjshhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj2ubjT)}(hidh]hid}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj2ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj)hhhj>hKubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1j'sphinx_line_type declaratorhj#hhhj>hKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j!hj>hKhjhhubh desc_content)}(hhh]h)}(hget a DPLL given its idh]hget a DPLL given its id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj>hKubeh}(h]h ](jkfunctioneh"]h$]h&]domainjkobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhhhNhNubh container)}(h**Parameters** ``struct intel_display *display`` intel_display device instance ``enum intel_dpll_id id`` pll id **Return** A pointer to the DPLL with **id**h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubhdefinition_list)}(hhh](hdefinition_list_item)}(h@``struct intel_display *display`` intel_display device instance h](hterm)}(h!``struct intel_display *display``h]hliteral)}(hjh]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubh definition)}(hhh]h)}(hintel_display device instanceh]hintel_display device instance}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h!``enum intel_dpll_id id`` pll id h](j)}(h``enum intel_dpll_id id``h]j )}(hjCh]henum intel_dpll_id id}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhj=ubj)}(hhh]h)}(hpll idh]hpll id}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhKhjYubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhjXhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h **Return**h]j)}(hj~h]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubh)}(h!A pointer to the DPLL with **id**h](hA pointer to the DPLL with }(hjhhhNhNubj)}(h**id**h]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dpll_enable (C function)c.intel_dpll_enablehNtauh1j hhhhhNhNubj)}(hhh](j")}(hBvoid intel_dpll_enable (const struct intel_crtc_state *crtc_state)h]j()}(hAvoid intel_dpll_enable(const struct intel_crtc_state *crtc_state)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjhhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjhhhjhMubj)}(hintel_dpll_enableh]jT)}(hintel_dpll_enableh]hintel_dpll_enable}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j.)}(hconsth]hconst}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj ubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubj.)}(hj1h]hstruct}(hj-hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj ubj@)}(h h]h }(hj:hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubh)}(hhh]jT)}(hintel_crtc_stateh]hintel_crtc_state}(hjKhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjHubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjMmodnameN classnameNjqjt)}jw]jz)}jmjsbc.intel_dpll_enableasbuh1hhj ubj@)}(h h]h }(hjkhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjT)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j!hjhMhjhhubj)}(hhh]h)}(henable a CRTC's DPLLh]henable a CRTC’s DPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjjjjjjjuh1jhhhhhNhNubj)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a DPLL **Description** Enable DPLL used by **crtc**.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]j)}(hT``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a DPLL h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j )}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h%CRTC, and its state, which has a DPLLh]h%CRTC, and its state, which has a DPLL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj,h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hEnable DPLL used by **crtc**.h](hEnable DPLL used by }(hjBhhhNhNubj)}(h**crtc**h]hcrtc}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubh.}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dpll_disable (C function)c.intel_dpll_disablehNtauh1j hhhhhNhNubj)}(hhh](j")}(hCvoid intel_dpll_disable (const struct intel_crtc_state *crtc_state)h]j()}(hBvoid intel_dpll_disable(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM<ubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjhhhjhM<ubj)}(hintel_dpll_disableh]jT)}(hintel_dpll_disableh]hintel_dpll_disable}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM<ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j.)}(hjh]hconst}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jz)}jmjsbc.intel_dpll_disableasbuh1hhjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(h crtc_stateh]h crtc_state}(hj4hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM<ubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhj{hhhjhM<ubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1j!hjhM<hjxhhubj)}(hhh]h)}(hdisable a CRTC's shared DPLLh]hdisable a CRTC’s shared DPLL}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM<hj[hhubah}(h]h ]h"]h$]h&]uh1jhjxhhhjhM<ubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjjvjjvjjjuh1jhhhhhNhNubj)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL **Description** Disable DPLL used by **crtc**.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM@hjzubj)}(hhh]j)}(h[``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j )}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM=hjubj)}(hhh]h)}(h,CRTC, and its state, which has a shared DPLLh]h,CRTC, and its state, which has a shared DPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM=hjubah}(h]h ]h"]h$]h&]uh1jhjzubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM?hjzubh)}(hDisable DPLL used by **crtc**.h](hDisable DPLL used by }(hjhhhNhNubj)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM>hjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j intel_dpll_crtc_get (C function)c.intel_dpll_crtc_gethNtauh1j hhhhhNhNubj)}(hhh](j")}(h{void intel_dpll_crtc_get (const struct intel_crtc *crtc, const struct intel_dpll *pll, struct intel_dpll_state *dpll_state)h]j()}(hzvoid intel_dpll_crtc_get(const struct intel_crtc *crtc, const struct intel_dpll *pll, struct intel_dpll_state *dpll_state)h](j)}(hvoidh]hvoid}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubj@)}(h h]h }(hj@hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj-hhhj?hMubj)}(hintel_dpll_crtc_geth]jT)}(hintel_dpll_crtc_geth]hintel_dpll_crtc_get}(hjRhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjNubah}(h]h ](jjeh"]h$]h&]hhuh1jhj-hhhj?hMubj)}(hb(const struct intel_crtc *crtc, const struct intel_dpll *pll, struct intel_dpll_state *dpll_state)h](j)}(hconst struct intel_crtc *crtch](j.)}(hjh]hconst}(hjnhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjjubj@)}(h h]h }(hj{hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjjubj.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjjubh)}(hhh]jT)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jz)}jmjTsbc.intel_dpll_crtc_getasbuh1hhjjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubjT)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjfubj)}(hconst struct intel_dpll *pllh](j.)}(hjh]hconst}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hj#hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_dpllh]h intel_dpll}(hj4hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj1ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj6modnameN classnameNjqjt)}jw]jc.intel_dpll_crtc_getasbuh1hhjubj@)}(h h]h }(hjRhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hpllh]hpll}(hjmhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjfubj)}(h#struct intel_dpll_state *dpll_stateh](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(hintel_dpll_stateh]hintel_dpll_state}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jc.intel_dpll_crtc_getasbuh1hhjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(h dpll_stateh]h dpll_state}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjfubeh}(h]h ]h"]h$]h&]hhuh1jhj-hhhj?hMubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhj)hhhj?hMubah}(h]j$ah ](jjeh"]h$]h&]jj)jhuh1j!hj?hMhj&hhubj)}(hhh]h)}(hGet a DPLL reference for a CRTCh]hGet a DPLL reference for a CRTC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj&hhhj?hMubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjj jj jjjuh1jhhhhhNhNubj)}(hX_**Parameters** ``const struct intel_crtc *crtc`` CRTC on which behalf the reference is taken ``const struct intel_dpll *pll`` DPLL for which the reference is taken ``struct intel_dpll_state *dpll_state`` the DPLL atomic state in which the reference is tracked **Description** Take a reference for **pll** tracking the use of it by **crtc**.h](h)}(h**Parameters**h]j)}(hj) h]h Parameters}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj' ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj# ubj)}(hhh](j)}(hN``const struct intel_crtc *crtc`` CRTC on which behalf the reference is taken h](j)}(h!``const struct intel_crtc *crtc``h]j )}(hjH h]hconst struct intel_crtc *crtc}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjF ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjB ubj)}(hhh]h)}(h+CRTC on which behalf the reference is takenh]h+CRTC on which behalf the reference is taken}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj] hMhj^ ubah}(h]h ]h"]h$]h&]uh1jhjB ubeh}(h]h ]h"]h$]h&]uh1jhj] hMhj? ubj)}(hG``const struct intel_dpll *pll`` DPLL for which the reference is taken h](j)}(h ``const struct intel_dpll *pll``h]j )}(hj h]hconst struct intel_dpll *pll}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj{ ubj)}(hhh]h)}(h%DPLL for which the reference is takenh]h%DPLL for which the reference is taken}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj{ ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj? ubj)}(h```struct intel_dpll_state *dpll_state`` the DPLL atomic state in which the reference is tracked h](j)}(h'``struct intel_dpll_state *dpll_state``h]j )}(hj h]h#struct intel_dpll_state *dpll_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(h7the DPLL atomic state in which the reference is trackedh]h7the DPLL atomic state in which the reference is tracked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj? ubeh}(h]h ]h"]h$]h&]uh1jhj# ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj# ubh)}(h@Take a reference for **pll** tracking the use of it by **crtc**.h](hTake a reference for }(hj hhhNhNubj)}(h**pll**h]hpll}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh tracking the use of it by }(hj hhhNhNubj)}(h**crtc**h]hcrtc}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj# ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j intel_dpll_crtc_put (C function)c.intel_dpll_crtc_puthNtauh1j hhhhhNhNubj)}(hhh](j")}(h{void intel_dpll_crtc_put (const struct intel_crtc *crtc, const struct intel_dpll *pll, struct intel_dpll_state *dpll_state)h]j()}(hzvoid intel_dpll_crtc_put(const struct intel_crtc *crtc, const struct intel_dpll *pll, struct intel_dpll_state *dpll_state)h](j)}(hvoidh]hvoid}(hj^ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZ hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubj@)}(h h]h }(hjm hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjZ hhhjl hMubj)}(hintel_dpll_crtc_puth]jT)}(hintel_dpll_crtc_puth]hintel_dpll_crtc_put}(hj hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj{ ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjZ hhhjl hMubj)}(hb(const struct intel_crtc *crtc, const struct intel_dpll *pll, struct intel_dpll_state *dpll_state)h](j)}(hconst struct intel_crtc *crtch](j.)}(hjh]hconst}(hj hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj ubj@)}(h h]h }(hj hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubj.)}(hj1h]hstruct}(hj hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj ubj@)}(h h]h }(hj hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubh)}(hhh]jT)}(h intel_crtch]h intel_crtc}(hj hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj modnameN classnameNjqjt)}jw]jz)}jmj sbc.intel_dpll_crtc_putasbuh1hhj ubj@)}(h h]h }(hj hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjT)}(hcrtch]hcrtc}(hj hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubj)}(hconst struct intel_dpll *pllh](j.)}(hjh]hconst}(hj( hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj$ ubj@)}(h h]h }(hj5 hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj$ ubj.)}(hj1h]hstruct}(hjC hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj$ ubj@)}(h h]h }(hjP hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj$ ubh)}(hhh]jT)}(h intel_dpllh]h intel_dpll}(hja hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj^ ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjc modnameN classnameNjqjt)}jw]j c.intel_dpll_crtc_putasbuh1hhj$ ubj@)}(h h]h }(hj hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj$ ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ ubjT)}(hpllh]hpll}(hj hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj$ ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubj)}(h#struct intel_dpll_state *dpll_stateh](j.)}(hj1h]hstruct}(hj hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj ubj@)}(h h]h }(hj hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubh)}(hhh]jT)}(hintel_dpll_stateh]hintel_dpll_state}(hj hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj modnameN classnameNjqjt)}jw]j c.intel_dpll_crtc_putasbuh1hhj ubj@)}(h h]h }(hj hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjT)}(h dpll_stateh]h dpll_state}(hj hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubeh}(h]h ]h"]h$]h&]hhuh1jhjZ hhhjl hMubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhjV hhhjl hMubah}(h]jQ ah ](jjeh"]h$]h&]jj)jhuh1j!hjl hMhjS hhubj)}(hhh]h)}(h Drop a DPLL reference for a CRTCh]h Drop a DPLL reference for a CRTC}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj1 hhubah}(h]h ]h"]h$]h&]uh1jhjS hhhjl hMubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjjL jjL jjjuh1jhhhhhNhNubj)}(hXj**Parameters** ``const struct intel_crtc *crtc`` CRTC on which behalf the reference is dropped ``const struct intel_dpll *pll`` DPLL for which the reference is dropped ``struct intel_dpll_state *dpll_state`` the DPLL atomic state in which the reference is tracked **Description** Drop a reference for **pll** tracking the end of use of it by **crtc**.h](h)}(h**Parameters**h]j)}(hjV h]h Parameters}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjP ubj)}(hhh](j)}(hP``const struct intel_crtc *crtc`` CRTC on which behalf the reference is dropped h](j)}(h!``const struct intel_crtc *crtc``h]j )}(hju h]hconst struct intel_crtc *crtc}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjo ubj)}(hhh]h)}(h-CRTC on which behalf the reference is droppedh]h-CRTC on which behalf the reference is dropped}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjo ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjl ubj)}(hI``const struct intel_dpll *pll`` DPLL for which the reference is dropped h](j)}(h ``const struct intel_dpll *pll``h]j )}(hj h]hconst struct intel_dpll *pll}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(h'DPLL for which the reference is droppedh]h'DPLL for which the reference is dropped}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjl ubj)}(h```struct intel_dpll_state *dpll_state`` the DPLL atomic state in which the reference is tracked h](j)}(h'``struct intel_dpll_state *dpll_state``h]j )}(hj h]h#struct intel_dpll_state *dpll_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(h7the DPLL atomic state in which the reference is trackedh]h7the DPLL atomic state in which the reference is tracked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjl ubeh}(h]h ]h"]h$]h&]uh1jhjP ubh)}(h**Description**h]j)}(hj" h]h Description}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjP ubh)}(hGDrop a reference for **pll** tracking the end of use of it by **crtc**.h](hDrop a reference for }(hj8 hhhNhNubj)}(h**pll**h]hpll}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8 ubh" tracking the end of use of it by }(hj8 hhhNhNubj)}(h**crtc**h]hcrtc}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8 ubh.}(hj8 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjP ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dpll_swap_state (C function)c.intel_dpll_swap_statehNtauh1j hhhhhNhNubj)}(hhh](j")}(h=void intel_dpll_swap_state (struct intel_atomic_state *state)h]j()}(hhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj:ubj@)}(h h]h }(hjKhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj:ubh)}(hhh]jT)}(hintel_atomic_stateh]hintel_atomic_state}(hj\hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjYubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj^modnameN classnameNjqjt)}jw]jz)}jmj$sbc.intel_dpll_computeasbuh1hhj:ubj@)}(h h]h }(hj|hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj:ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubjT)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj:ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj6ubj)}(hstruct intel_crtc *crtch](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jxc.intel_dpll_computeasbuh1hhjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj6ubj)}(hstruct intel_encoder *encoderh](j.)}(hj1h]hstruct}(hj hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hj-hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_encoderh]h intel_encoder}(hj>hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj;ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj@modnameN classnameNjqjt)}jw]jxc.intel_dpll_computeasbuh1hhjubj@)}(h h]h }(hj\hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hencoderh]hencoder}(hjwhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj6ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j!hjhMhjhhubj)}(hhh]h)}(h/compute DPLL state CRTC and encoder combinationh]h/compute DPLL state CRTC and encoder combination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjjjjjjjuh1jhhhhhNhNubj)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` CRTC to compute DPLLs for ``struct intel_encoder *encoder`` encoder **Description** This function computes the DPLL state for the given CRTC and encoder. The new configuration in the atomic commit **state** is made effective by calling intel_dpll_swap_state(). **Return** 0 on success, negative error code on failure.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh](j)}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j )}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h6``struct intel_crtc *crtc`` CRTC to compute DPLLs for h](j)}(h``struct intel_crtc *crtc``h]j )}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(hCRTC to compute DPLLs forh]hCRTC to compute DPLLs for}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj0hMhjubj)}(h*``struct intel_encoder *encoder`` encoder h](j)}(h!``struct intel_encoder *encoder``h]j )}(hjTh]hstruct intel_encoder *encoder}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjNubj)}(hhh]h)}(hencoderh]hencoder}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMhjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjihMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hEThis function computes the DPLL state for the given CRTC and encoder.h]hEThis function computes the DPLL state for the given CRTC and encoder.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hjThe new configuration in the atomic commit **state** is made effective by calling intel_dpll_swap_state().h](h+The new configuration in the atomic commit }(hjhhhNhNubj)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh6 is made effective by calling intel_dpll_swap_state().}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(h-0 on success, negative error code on failure.h]h-0 on success, negative error code on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dpll_reserve (C function)c.intel_dpll_reservehNtauh1j hhhhhNhNubj)}(hhh](j")}(hqint intel_dpll_reserve (struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h]j()}(hpint intel_dpll_reserve(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubj@)}(h h]h }(hj+hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjhhhj*hMubj)}(hintel_dpll_reserveh]jT)}(hintel_dpll_reserveh]hintel_dpll_reserve}(hj=hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj9ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj*hMubj)}(hZ(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(h struct intel_atomic_state *stateh](j.)}(hj1h]hstruct}(hjYhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjUubj@)}(h h]h }(hjfhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjUubh)}(hhh]jT)}(hintel_atomic_stateh]hintel_atomic_state}(hjwhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjtubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjymodnameN classnameNjqjt)}jw]jz)}jmj?sbc.intel_dpll_reserveasbuh1hhjUubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjUubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubjT)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjUubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjQubj)}(hstruct intel_crtc *crtch](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jc.intel_dpll_reserveasbuh1hhjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hcrtch]hcrtc}(hj"hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjQubj)}(hstruct intel_encoder *encoderh](j.)}(hj1h]hstruct}(hj;hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj7ubj@)}(h h]h }(hjHhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj7ubh)}(hhh]jT)}(h intel_encoderh]h intel_encoder}(hjYhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjVubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj[modnameN classnameNjqjt)}jw]jc.intel_dpll_reserveasbuh1hhj7ubj@)}(h h]h }(hjwhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj7ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubjT)}(hencoderh]hencoder}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj7ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjQubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj*hMubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhjhhhj*hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j!hj*hMhjhhubj)}(hhh]h)}(h.reserve DPLLs for CRTC and encoder combinationh]h.reserve DPLLs for CRTC and encoder combination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj*hMubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjjjjjjjuh1jhhhhhNhNubj)}(hXn**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` CRTC to reserve DPLLs for ``struct intel_encoder *encoder`` encoder **Description** This function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit **state** and the new **crtc** atomic state. The new configuration in the atomic commit **state** is made effective by calling intel_dpll_swap_state(). The reserved DPLLs should be released by calling intel_dpll_release(). **Return** 0 if all required DPLLs were successfully reserved, negative error code otherwise.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh](j)}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j )}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h6``struct intel_crtc *crtc`` CRTC to reserve DPLLs for h](j)}(h``struct intel_crtc *crtc``h]j )}(hj6h]hstruct intel_crtc *crtc}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj0ubj)}(hhh]h)}(hCRTC to reserve DPLLs forh]hCRTC to reserve DPLLs for}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMhjLubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMhjubj)}(h*``struct intel_encoder *encoder`` encoder h](j)}(h!``struct intel_encoder *encoder``h]j )}(hjoh]hstruct intel_encoder *encoder}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjiubj)}(hhh]h)}(hencoderh]hencoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hThis function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit **state** and the new **crtc** atomic state.h](hrThis function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit }(hjhhhNhNubj)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and the new }(hjhhhNhNubj)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh atomic state.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hjThe new configuration in the atomic commit **state** is made effective by calling intel_dpll_swap_state().h](h+The new configuration in the atomic commit }(hjhhhNhNubj)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh6 is made effective by calling intel_dpll_swap_state().}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hFThe reserved DPLLs should be released by calling intel_dpll_release().h]hFThe reserved DPLLs should be released by calling intel_dpll_release().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(h **Return**h]j)}(hj%h]hReturn}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hR0 if all required DPLLs were successfully reserved, negative error code otherwise.h]hR0 if all required DPLLs were successfully reserved, negative error code otherwise.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dpll_release (C function)c.intel_dpll_releasehNtauh1j hhhhhNhNubj)}(hhh](j")}(hSvoid intel_dpll_release (struct intel_atomic_state *state, struct intel_crtc *crtc)h]j()}(hRvoid intel_dpll_release(struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hvoidh]hvoid}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfhhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM ubj@)}(h h]h }(hjyhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjfhhhjxhM ubj)}(hintel_dpll_releaseh]jT)}(hintel_dpll_releaseh]hintel_dpll_release}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjfhhhjxhM ubj)}(h;(struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(h struct intel_atomic_state *stateh](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jz)}jmjsbc.intel_dpll_releaseasbuh1hhjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct intel_crtc *crtch](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hj&hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_crtch]h intel_crtc}(hj7hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj4ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj9modnameN classnameNjqjt)}jw]jc.intel_dpll_releaseasbuh1hhjubj@)}(h h]h }(hjUhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hcrtch]hcrtc}(hjphhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjfhhhjxhM ubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhjbhhhjxhM ubah}(h]j]ah ](jjeh"]h$]h&]jj)jhuh1j!hjxhM hj_hhubj)}(hhh]h)}(h(end use of DPLLs by CRTC in atomic stateh]h(end use of DPLLs by CRTC in atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhj_hhhjxhM ubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjjjjjjjuh1jhhhhhNhNubj)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` crtc from which the DPLLs are to be released **Description** This function releases all DPLLs reserved by intel_dpll_reserve() from the current atomic commit **state** and the old **crtc** atomic state. The new configuration in the atomic commit **state** is made effective by calling intel_dpll_swap_state().h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubj)}(hhh](j)}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j )}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(hI``struct intel_crtc *crtc`` crtc from which the DPLLs are to be released h](j)}(h``struct intel_crtc *crtc``h]j )}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubj)}(hhh]h)}(h,crtc from which the DPLLs are to be releasedh]h,crtc from which the DPLLs are to be released}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hM hj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj)hM hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjOh]h Description}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubh)}(hThis function releases all DPLLs reserved by intel_dpll_reserve() from the current atomic commit **state** and the old **crtc** atomic state.h](haThis function releases all DPLLs reserved by intel_dpll_reserve() from the current atomic commit }(hjehhhNhNubj)}(h **state**h]hstate}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh and the old }(hjehhhNhNubj)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh atomic state.}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubh)}(hjThe new configuration in the atomic commit **state** is made effective by calling intel_dpll_swap_state().h](h+The new configuration in the atomic commit }(hjhhhNhNubj)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh6 is made effective by calling intel_dpll_swap_state().}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j%intel_dpll_update_active (C function)c.intel_dpll_update_activehNtauh1j hhhhhNhNubj)}(hhh](j")}(hxvoid intel_dpll_update_active (struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h]j()}(hwvoid intel_dpll_update_active(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM&ubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjhhhjhM&ubj)}(hintel_dpll_update_activeh]jT)}(hintel_dpll_update_activeh]hintel_dpll_update_active}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM&ubj)}(hZ(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(h struct intel_atomic_state *stateh](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hj#hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(hintel_atomic_stateh]hintel_atomic_state}(hj4hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj1ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj6modnameN classnameNjqjt)}jw]jz)}jmjsbc.intel_dpll_update_activeasbuh1hhjubj@)}(h h]h }(hjThhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hstateh]hstate}(hjohhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct intel_crtc *crtch](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jPc.intel_dpll_update_activeasbuh1hhjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct intel_encoder *encoderh](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_encoderh]h intel_encoder}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jPc.intel_dpll_update_activeasbuh1hhjubj@)}(h h]h }(hj4hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hencoderh]hencoder}(hjOhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM&ubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhjhhhjhM&ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j!hjhM&hjhhubj)}(hhh]h)}(h)update the active DPLL for a CRTC/encoderh]h)update the active DPLL for a CRTC/encoder}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM&hjvhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM&ubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjjjjjjjuh1jhhhhhNhNubj)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` the CRTC for which to update the active DPLL ``struct intel_encoder *encoder`` encoder determining the type of port DPLL **Description** Update the active DPLL for the given **crtc**/**encoder** in **crtc**'s atomic state, from the port DPLLs reserved previously by intel_dpll_reserve(). The DPLL selected will be based on the current mode of the encoder's port.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM*hjubj)}(hhh](j)}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j )}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM'hjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM'hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM'hjubj)}(hI``struct intel_crtc *crtc`` the CRTC for which to update the active DPLL h](j)}(h``struct intel_crtc *crtc``h]j )}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM(hjubj)}(hhh]h)}(h,the CRTC for which to update the active DPLLh]h,the CRTC for which to update the active DPLL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM(hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM(hjubj)}(hL``struct intel_encoder *encoder`` encoder determining the type of port DPLL h](j)}(h!``struct intel_encoder *encoder``h]j )}(hj,h]hstruct intel_encoder *encoder}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM)hj&ubj)}(hhh]h)}(h)encoder determining the type of port DPLLh]h)encoder determining the type of port DPLL}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhM)hjBubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhjAhM)hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjgh]h Description}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM+hjubh)}(hUpdate the active DPLL for the given **crtc**/**encoder** in **crtc**'s atomic state, from the port DPLLs reserved previously by intel_dpll_reserve(). The DPLL selected will be based on the current mode of the encoder's port.h](h%Update the active DPLL for the given }(hj}hhhNhNubj)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubh/}(hj}hhhNhNubj)}(h **encoder**h]hencoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubh in }(hj}hhhNhNubj)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubh’s atomic state, from the port DPLLs reserved previously by intel_dpll_reserve(). The DPLL selected will be based on the current mode of the encoder’s port.}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM*hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j intel_dpll_get_freq (C function)c.intel_dpll_get_freqhNtauh1j hhhhhNhNubj)}(hhh](j")}(hint intel_dpll_get_freq (struct intel_display *display, const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h]j()}(hint intel_dpll_get_freq(struct intel_display *display, const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM=ubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjhhhjhM=ubj)}(hintel_dpll_get_freqh]jT)}(hintel_dpll_get_freqh]hintel_dpll_get_freq}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM=ubj)}(hn(struct intel_display *display, const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hj,hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_displayh]h intel_display}(hj=hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj:ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj?modnameN classnameNjqjt)}jw]jz)}jmjsbc.intel_dpll_get_freqasbuh1hhjubj@)}(h h]h }(hj]hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hdisplayh]hdisplay}(hjxhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hconst struct intel_dpll *pllh](j.)}(hjh]hconst}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj.)}(hj1h]hstruct}(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubh)}(hhh]jT)}(h intel_dpllh]h intel_dpll}(hjhhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjmodnameN classnameNjqjt)}jw]jYc.intel_dpll_get_freqasbuh1hhjubj@)}(h h]h }(hjhhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjT)}(hpllh]hpll}(hj hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h/const struct intel_dpll_hw_state *dpll_hw_stateh](j.)}(hjh]hconst}(hj hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj ubj@)}(h h]h }(hj) hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubj.)}(hj1h]hstruct}(hj7 hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj ubj@)}(h h]h }(hjD hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubh)}(hhh]jT)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hjU hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjR ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjW modnameN classnameNjqjt)}jw]jYc.intel_dpll_get_freqasbuh1hhj ubj@)}(h h]h }(hjs hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjT)}(h dpll_hw_stateh]h dpll_hw_state}(hj hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM=ubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhjhhhjhM=ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j!hjhM=hjhhubj)}(hhh]h)}(h%calculate the DPLL's output frequencyh]h'calculate the DPLL’s output frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM=hj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM=ubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjj jj jjjuh1jhhhhhNhNubj)}(hXr**Parameters** ``struct intel_display *display`` intel_display device ``const struct intel_dpll *pll`` DPLL for which to calculate the output frequency ``const struct intel_dpll_hw_state *dpll_hw_state`` DPLL state from which to calculate the output frequency **Description** Return the output frequency corresponding to **pll**'s passed in **dpll_hw_state**.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMAhj ubj)}(hhh](j)}(h7``struct intel_display *display`` intel_display device h](j)}(h!``struct intel_display *display``h]j )}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM>hj ubj)}(hhh]h)}(hintel_display deviceh]hintel_display device}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM>hj!ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj!hM>hj ubj)}(hR``const struct intel_dpll *pll`` DPLL for which to calculate the output frequency h](j)}(h ``const struct intel_dpll *pll``h]j )}(hj2!h]hconst struct intel_dpll *pll}(hj4!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0!ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM?hj,!ubj)}(hhh]h)}(h0DPLL for which to calculate the output frequencyh]h0DPLL for which to calculate the output frequency}(hjK!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjG!hM?hjH!ubah}(h]h ]h"]h$]h&]uh1jhj,!ubeh}(h]h ]h"]h$]h&]uh1jhjG!hM?hj ubj)}(hl``const struct intel_dpll_hw_state *dpll_hw_state`` DPLL state from which to calculate the output frequency h](j)}(h3``const struct intel_dpll_hw_state *dpll_hw_state``h]j )}(hjk!h]h/const struct intel_dpll_hw_state *dpll_hw_state}(hjm!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji!ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM@hje!ubj)}(hhh]h)}(h7DPLL state from which to calculate the output frequencyh]h7DPLL state from which to calculate the output frequency}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM@hj!ubah}(h]h ]h"]h$]h&]uh1jhje!ubeh}(h]h ]h"]h$]h&]uh1jhj!hM@hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hj!h]h Description}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMBhj ubh)}(hSReturn the output frequency corresponding to **pll**'s passed in **dpll_hw_state**.h](h-Return the output frequency corresponding to }(hj!hhhNhNubj)}(h**pll**h]hpll}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubh’s passed in }(hj!hhhNhNubj)}(h**dpll_hw_state**h]h dpll_hw_state}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubh.}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMAhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j$intel_dpll_get_hw_state (C function)c.intel_dpll_get_hw_statehNtauh1j hhhhhNhNubj)}(hhh](j")}(hbool intel_dpll_get_hw_state (struct intel_display *display, struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h]j()}(h~bool intel_dpll_get_hw_state(struct intel_display *display, struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hboolh]hbool}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj "hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMOubj@)}(h h]h }(hj"hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj "hhhj"hMOubj)}(hintel_dpll_get_hw_stateh]jT)}(hintel_dpll_get_hw_stateh]hintel_dpll_get_hw_state}(hj0"hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj,"ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj "hhhj"hMOubj)}(hb(struct intel_display *display, struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j.)}(hj1h]hstruct}(hjL"hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjH"ubj@)}(h h]h }(hjY"hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjH"ubh)}(hhh]jT)}(h intel_displayh]h intel_display}(hjj"hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjg"ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjl"modnameN classnameNjqjt)}jw]jz)}jmj2"sbc.intel_dpll_get_hw_stateasbuh1hhjH"ubj@)}(h h]h }(hj"hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjH"ubj)}(hjh]h*}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjH"ubjT)}(hdisplayh]hdisplay}(hj"hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjH"ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjD"ubj)}(hstruct intel_dpll *pllh](j.)}(hj1h]hstruct}(hj"hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj"ubj@)}(h h]h }(hj"hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj"ubh)}(hhh]jT)}(h intel_dpllh]h intel_dpll}(hj"hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj"ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj"modnameN classnameNjqjt)}jw]j"c.intel_dpll_get_hw_stateasbuh1hhj"ubj@)}(h h]h }(hj"hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj"ubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubjT)}(hpllh]hpll}(hj#hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj"ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjD"ubj)}(h)struct intel_dpll_hw_state *dpll_hw_stateh](j.)}(hj1h]hstruct}(hj.#hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj*#ubj@)}(h h]h }(hj;#hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj*#ubh)}(hhh]jT)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hjL#hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjI#ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjN#modnameN classnameNjqjt)}jw]j"c.intel_dpll_get_hw_stateasbuh1hhj*#ubj@)}(h h]h }(hjj#hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj*#ubj)}(hjh]h*}(hjx#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*#ubjT)}(h dpll_hw_stateh]h dpll_hw_state}(hj#hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj*#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjD"ubeh}(h]h ]h"]h$]h&]hhuh1jhj "hhhj"hMOubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhj"hhhj"hMOubah}(h]j"ah ](jjeh"]h$]h&]jj)jhuh1j!hj"hMOhj"hhubj)}(hhh]h)}(h!readout the DPLL's hardware stateh]h#readout the DPLL’s hardware state}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMOhj#hhubah}(h]h ]h"]h$]h&]uh1jhj"hhhj"hMOubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjj#jj#jjjuh1jhhhhhNhNubj)}(hX3**Parameters** ``struct intel_display *display`` intel_display device instance ``struct intel_dpll *pll`` DPLL for which to calculate the output frequency ``struct intel_dpll_hw_state *dpll_hw_state`` DPLL's hardware state **Description** Read out **pll**'s hardware state into **dpll_hw_state**.h](h)}(h**Parameters**h]j)}(hj#h]h Parameters}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMShj#ubj)}(hhh](j)}(h@``struct intel_display *display`` intel_display device instance h](j)}(h!``struct intel_display *display``h]j )}(hj#h]hstruct intel_display *display}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMPhj#ubj)}(hhh]h)}(hintel_display device instanceh]hintel_display device instance}(hj $hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMPhj$ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj$hMPhj#ubj)}(hL``struct intel_dpll *pll`` DPLL for which to calculate the output frequency h](j)}(h``struct intel_dpll *pll``h]j )}(hj)$h]hstruct intel_dpll *pll}(hj+$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'$ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMQhj#$ubj)}(hhh]h)}(h0DPLL for which to calculate the output frequencyh]h0DPLL for which to calculate the output frequency}(hjB$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>$hMQhj?$ubah}(h]h ]h"]h$]h&]uh1jhj#$ubeh}(h]h ]h"]h$]h&]uh1jhj>$hMQhj#ubj)}(hD``struct intel_dpll_hw_state *dpll_hw_state`` DPLL's hardware state h](j)}(h-``struct intel_dpll_hw_state *dpll_hw_state``h]j )}(hjb$h]h)struct intel_dpll_hw_state *dpll_hw_state}(hjd$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`$ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMRhj\$ubj)}(hhh]h)}(hDPLL's hardware stateh]hDPLL’s hardware state}(hj{$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjw$hMRhjx$ubah}(h]h ]h"]h$]h&]uh1jhj\$ubeh}(h]h ]h"]h$]h&]uh1jhjw$hMRhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#ubh)}(h**Description**h]j)}(hj$h]h Description}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMThj#ubh)}(h9Read out **pll**'s hardware state into **dpll_hw_state**.h](h Read out }(hj$hhhNhNubj)}(h**pll**h]hpll}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubh’s hardware state into }(hj$hhhNhNubj)}(h**dpll_hw_state**h]h dpll_hw_state}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubh.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMShj#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j%intel_dpll_dump_hw_state (C function)c.intel_dpll_dump_hw_statehNtauh1j hhhhhNhNubj)}(hhh](j")}(hvoid intel_dpll_dump_hw_state (struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h]j()}(hvoid intel_dpll_dump_hw_state(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hvoidh]hvoid}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubj@)}(h h]h }(hj%hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj%hhhj%hMubj)}(hintel_dpll_dump_hw_stateh]jT)}(hintel_dpll_dump_hw_stateh]hintel_dpll_dump_hw_state}(hj'%hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj#%ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj%hhhj%hMubj)}(hg(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j.)}(hj1h]hstruct}(hjC%hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj?%ubj@)}(h h]h }(hjP%hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj?%ubh)}(hhh]jT)}(h intel_displayh]h intel_display}(hja%hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj^%ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjc%modnameN classnameNjqjt)}jw]jz)}jmj)%sbc.intel_dpll_dump_hw_stateasbuh1hhj?%ubj@)}(h h]h }(hj%hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj?%ubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?%ubjT)}(hdisplayh]hdisplay}(hj%hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj?%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj;%ubj)}(hstruct drm_printer *ph](j.)}(hj1h]hstruct}(hj%hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj%ubj@)}(h h]h }(hj%hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj%ubh)}(hhh]jT)}(h drm_printerh]h drm_printer}(hj%hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj%ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj%modnameN classnameNjqjt)}jw]j}%c.intel_dpll_dump_hw_stateasbuh1hhj%ubj@)}(h h]h }(hj%hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj%ubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubjT)}(hjh]hp}(hj &hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj;%ubj)}(h/const struct intel_dpll_hw_state *dpll_hw_stateh](j.)}(hjh]hconst}(hj$&hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj &ubj@)}(h h]h }(hj1&hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj &ubj.)}(hj1h]hstruct}(hj?&hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj &ubj@)}(h h]h }(hjL&hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj &ubh)}(hhh]jT)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hj]&hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjZ&ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj_&modnameN classnameNjqjt)}jw]j}%c.intel_dpll_dump_hw_stateasbuh1hhj &ubj@)}(h h]h }(hj{&hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj &ubj)}(hjh]h*}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj &ubjT)}(h dpll_hw_stateh]h dpll_hw_state}(hj&hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj &ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj;%ubeh}(h]h ]h"]h$]h&]hhuh1jhj%hhhj%hMubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhj$hhhj%hMubah}(h]j$ah ](jjeh"]h$]h&]jj)jhuh1j!hj%hMhj$hhubj)}(hhh]h)}(h dump hw_stateh]h dump hw_state}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj&hhubah}(h]h ]h"]h$]h&]uh1jhj$hhhj%hMubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjj&jj&jjjuh1jhhhhhNhNubj)}(hX**Parameters** ``struct intel_display *display`` intel_display structure ``struct drm_printer *p`` where to print the state to ``const struct intel_dpll_hw_state *dpll_hw_state`` hw state to be dumped **Description** Dumo out the relevant values in **dpll_hw_state**.h](h)}(h**Parameters**h]j)}(hj&h]h Parameters}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj&ubj)}(hhh](j)}(h:``struct intel_display *display`` intel_display structure h](j)}(h!``struct intel_display *display``h]j )}(hj'h]hstruct intel_display *display}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj&ubj)}(hhh]h)}(hintel_display structureh]hintel_display structure}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hMhj'ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhj&ubj)}(h6``struct drm_printer *p`` where to print the state to h](j)}(h``struct drm_printer *p``h]j )}(hj:'h]hstruct drm_printer *p}(hj<'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8'ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj4'ubj)}(hhh]h)}(hwhere to print the state toh]hwhere to print the state to}(hjS'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjO'hMhjP'ubah}(h]h ]h"]h$]h&]uh1jhj4'ubeh}(h]h ]h"]h$]h&]uh1jhjO'hMhj&ubj)}(hJ``const struct intel_dpll_hw_state *dpll_hw_state`` hw state to be dumped h](j)}(h3``const struct intel_dpll_hw_state *dpll_hw_state``h]j )}(hjs'h]h/const struct intel_dpll_hw_state *dpll_hw_state}(hju'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq'ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjm'ubj)}(hhh]h)}(hhw state to be dumpedh]hhw state to be dumped}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hMhj'ubah}(h]h ]h"]h$]h&]uh1jhjm'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhj&ubeh}(h]h ]h"]h$]h&]uh1jhj&ubh)}(h**Description**h]j)}(hj'h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj&ubh)}(h2Dumo out the relevant values in **dpll_hw_state**.h](h Dumo out the relevant values in }(hj'hhhNhNubj)}(h**dpll_hw_state**h]h dpll_hw_state}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubh.}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj&ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j(intel_dpll_compare_hw_state (C function)c.intel_dpll_compare_hw_statehNtauh1j hhhhhNhNubj)}(hhh](j")}(hbool intel_dpll_compare_hw_state (struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h]j()}(hbool intel_dpll_compare_hw_state(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h](j)}(hj"h]hbool}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubj@)}(h h]h }(hj(hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj(hhhj(hMubj)}(hintel_dpll_compare_hw_stateh]jT)}(hintel_dpll_compare_hw_stateh]hintel_dpll_compare_hw_state}(hj%(hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj!(ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj(hhhj(hMubj)}(hi(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h](j)}(hstruct intel_display *displayh](j.)}(hj1h]hstruct}(hjA(hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj=(ubj@)}(h h]h }(hjN(hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj=(ubh)}(hhh]jT)}(h intel_displayh]h intel_display}(hj_(hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj\(ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetja(modnameN classnameNjqjt)}jw]jz)}jmj'(sbc.intel_dpll_compare_hw_stateasbuh1hhj=(ubj@)}(h h]h }(hj(hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj=(ubj)}(hjh]h*}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=(ubjT)}(hdisplayh]hdisplay}(hj(hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj=(ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj9(ubj)}(h#const struct intel_dpll_hw_state *ah](j.)}(hjh]hconst}(hj(hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj(ubj@)}(h h]h }(hj(hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj(ubj.)}(hj1h]hstruct}(hj(hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj(ubj@)}(h h]h }(hj(hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj(ubh)}(hhh]jT)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hj(hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj(ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetj(modnameN classnameNjqjt)}jw]j{(c.intel_dpll_compare_hw_stateasbuh1hhj(ubj@)}(h h]h }(hj )hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj(ubj)}(hjh]h*}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubjT)}(hah]ha}(hj%)hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj(ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj9(ubj)}(h#const struct intel_dpll_hw_state *bh](j.)}(hjh]hconst}(hj>)hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj:)ubj@)}(h h]h }(hjK)hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj:)ubj.)}(hj1h]hstruct}(hjY)hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj:)ubj@)}(h h]h }(hjf)hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj:)ubh)}(hhh]jT)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hjw)hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjt)ubah}(h]h ]h"]h$]h&] refdomainjkreftypejm reftargetjy)modnameN classnameNjqjt)}jw]j{(c.intel_dpll_compare_hw_stateasbuh1hhj:)ubj@)}(h h]h }(hj)hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj:)ubj)}(hjh]h*}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:)ubjT)}(hbh]hb}(hj)hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj:)ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj9(ubeh}(h]h ]h"]h$]h&]hhuh1jhj(hhhj(hMubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhj'hhhj(hMubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1j!hj(hMhj'hhubj)}(hhh]h)}(hcompare the two statesh]hcompare the two states}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj)hhubah}(h]h ]h"]h$]h&]uh1jhj'hhhj(hMubeh}(h]h ](jkfunctioneh"]h$]h&]jjkjj)jj)jjjuh1jhhhhhNhNubj)}(hXC**Parameters** ``struct intel_display *display`` intel_display structure ``const struct intel_dpll_hw_state *a`` first DPLL hw state ``const struct intel_dpll_hw_state *b`` second DPLL hw state **Description** Compare DPLL hw states **a** and **b**. **Return** true if the states are equal, false if the differh](h)}(h**Parameters**h]j)}(hj)h]h Parameters}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj)ubj)}(hhh](j)}(h:``struct intel_display *display`` intel_display structure h](j)}(h!``struct intel_display *display``h]j )}(hj*h]hstruct intel_display *display}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj*ubj)}(hhh]h)}(hintel_display structureh]hintel_display structure}(hj4*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0*hMhj1*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj0*hMhj*ubj)}(h<``const struct intel_dpll_hw_state *a`` first DPLL hw state h](j)}(h'``const struct intel_dpll_hw_state *a``h]j )}(hjT*h]h#const struct intel_dpll_hw_state *a}(hjV*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR*ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjN*ubj)}(hhh]h)}(hfirst DPLL hw stateh]hfirst DPLL hw state}(hjm*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji*hMhjj*ubah}(h]h ]h"]h$]h&]uh1jhjN*ubeh}(h]h ]h"]h$]h&]uh1jhji*hMhj*ubj)}(h=``const struct intel_dpll_hw_state *b`` second DPLL hw state h](j)}(h'``const struct intel_dpll_hw_state *b``h]j )}(hj*h]h#const struct intel_dpll_hw_state *b}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj*ubj)}(hhh]h)}(hsecond DPLL hw stateh]hsecond DPLL hw state}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hMhj*ubeh}(h]h ]h"]h$]h&]uh1jhj)ubh)}(h**Description**h]j)}(hj*h]h Description}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj)ubh)}(h'Compare DPLL hw states **a** and **b**.h](hCompare DPLL hw states }(hj*hhhNhNubj)}(h**a**h]ha}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubh and }(hj*hhhNhNubj)}(h**b**h]hb}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubh.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj)ubh)}(h **Return**h]j)}(hj+h]hReturn}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj)ubh)}(h1true if the states are equal, false if the differh]h1true if the states are equal, false if the differ}(hj)+hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:10: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj)ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dpll_id (C enum)c.intel_dpll_idhNtauh1j hhhhhNhNubj)}(hhh](j")}(h intel_dpll_idh]j()}(henum intel_dpll_idh](j.)}(hj8h]henum}(hjX+hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjT+hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKubj@)}(h h]h }(hjf+hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hjT+hhhje+hKubj)}(h intel_dpll_idh]jT)}(hjR+h]h intel_dpll_id}(hjx+hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShjt+ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjT+hhhje+hKubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhjP+hhhje+hKubah}(h]jK+ah ](jjeh"]h$]h&]jj)jhuh1j!hje+hKhjM+hhubj)}(hhh]h)}(hpossible DPLL idsh]hpossible DPLL ids}(hj+hhhNhNubah}(Qh]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK/hj+hhubah}(h]h ]h"]h$]h&]uh1jhjM+hhhje+hKubeh}(h]h ](jkenumeh"]h$]h&]jjkjj+jj+jjjuh1jhhhhhNhNubj)}(hX**Constants** ``DPLL_ID_PRIVATE`` non-shared dpll in use ``DPLL_ID_PCH_PLL_A`` DPLL A in ILK, SNB and IVB ``DPLL_ID_PCH_PLL_B`` DPLL B in ILK, SNB and IVB ``DPLL_ID_WRPLL1`` HSW and BDW WRPLL1 ``DPLL_ID_WRPLL2`` HSW and BDW WRPLL2 ``DPLL_ID_SPLL`` HSW and BDW SPLL ``DPLL_ID_LCPLL_810`` HSW and BDW 0.81 GHz LCPLL ``DPLL_ID_LCPLL_1350`` HSW and BDW 1.35 GHz LCPLL ``DPLL_ID_LCPLL_2700`` HSW and BDW 2.7 GHz LCPLL ``DPLL_ID_SKL_DPLL0`` SKL and later DPLL0 ``DPLL_ID_SKL_DPLL1`` SKL and later DPLL1 ``DPLL_ID_SKL_DPLL2`` SKL and later DPLL2 ``DPLL_ID_SKL_DPLL3`` SKL and later DPLL3 ``DPLL_ID_ICL_DPLL0`` ICL/TGL combo PHY DPLL0 ``DPLL_ID_ICL_DPLL1`` ICL/TGL combo PHY DPLL1 ``DPLL_ID_EHL_DPLL4`` EHL combo PHY DPLL4 ``DPLL_ID_ICL_TBTPLL`` ICL/TGL TBT PLL ``DPLL_ID_ICL_MGPLL1`` ICL MG PLL 1 port 1 (C), TGL TC PLL 1 port 1 (TC1) ``DPLL_ID_ICL_MGPLL2`` ICL MG PLL 1 port 2 (D) TGL TC PLL 1 port 2 (TC2) ``DPLL_ID_ICL_MGPLL3`` ICL MG PLL 1 port 3 (E) TGL TC PLL 1 port 3 (TC3) ``DPLL_ID_ICL_MGPLL4`` ICL MG PLL 1 port 4 (F) TGL TC PLL 1 port 4 (TC4) ``DPLL_ID_TGL_MGPLL5`` TGL TC PLL port 5 (TC5) ``DPLL_ID_TGL_MGPLL6`` TGL TC PLL port 6 (TC6) ``DPLL_ID_DG1_DPLL0`` DG1 combo PHY DPLL0 ``DPLL_ID_DG1_DPLL1`` DG1 combo PHY DPLL1 ``DPLL_ID_DG1_DPLL2`` DG1 combo PHY DPLL2 ``DPLL_ID_DG1_DPLL3`` DG1 combo PHY DPLL3h](h)}(h **Constants**h]j)}(hj+h]h Constants}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK3hj+ubj)}(hhh](j)}(h+``DPLL_ID_PRIVATE`` non-shared dpll in use h](j)}(h``DPLL_ID_PRIVATE``h]j )}(hj+h]hDPLL_ID_PRIVATE}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK6hj+ubj)}(hhh]h)}(hnon-shared dpll in useh]hnon-shared dpll in use}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hK6hj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hK6hj+ubj)}(h1``DPLL_ID_PCH_PLL_A`` DPLL A in ILK, SNB and IVB h](j)}(h``DPLL_ID_PCH_PLL_A``h]j )}(hj,h]hDPLL_ID_PCH_PLL_A}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK9hj,ubj)}(hhh]h)}(hDPLL A in ILK, SNB and IVBh]hDPLL A in ILK, SNB and IVB}(hj-,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj),hK9hj*,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj),hK9hj+ubj)}(h1``DPLL_ID_PCH_PLL_B`` DPLL B in ILK, SNB and IVB h](j)}(h``DPLL_ID_PCH_PLL_B``h]j )}(hjM,h]hDPLL_ID_PCH_PLL_B}(hjO,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK,ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK= 0.h]hJEnumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK0hhhhubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dpll_state (C struct)c.intel_dpll_statehNtauh1j hhhhhNhNubj)}(hhh](j")}(hintel_dpll_stateh]j()}(hstruct intel_dpll_stateh](j.)}(hj1h]hstruct}(hj2hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj2hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK5ubj@)}(h h]h }(hj2hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj2hhhj2hK5ubj)}(hintel_dpll_stateh]jT)}(hj2h]hintel_dpll_state}(hj2hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj2ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj2hhhj2hK5ubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhj2hhhj2hK5ubah}(h]j2ah ](jjeh"]h$]h&]jj)jhuh1j!hj2hK5hj2hhubj)}(hhh]h)}(hhold the DPLL atomic stateh]hhold the DPLL atomic state}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM*hj 3hhubah}(h]h ]h"]h$]h&]uh1jhj2hhhj2hK5ubeh}(h]h ](jkstructeh"]h$]h&]jjkjj(3jj(3jjjuh1jhhhhhNhNubj)}(hX"**Definition**:: struct intel_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; }; **Members** ``pipe_mask`` mask of pipes using this DPLL, active or not ``hw_state`` hardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj43hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj03ubh:}(hj03hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM.hj,3ubh literal_block)}(hWstruct intel_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; };h]hWstruct intel_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; };}hjO3sbah}(h]h ]h"]h$]h&]hhuh1jM3ht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM0hj,3ubh)}(h **Members**h]j)}(hj`3h]hMembers}(hjb3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^3ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM5hj,3ubj)}(hhh](j)}(h;``pipe_mask`` mask of pipes using this DPLL, active or not h](j)}(h ``pipe_mask``h]j )}(hj3h]h pipe_mask}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}3ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM6hjy3ubj)}(hhh]h)}(h,mask of pipes using this DPLL, active or noth]h,mask of pipes using this DPLL, active or not}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hM6hj3ubah}(h]h ]h"]h$]h&]uh1jhjy3ubeh}(h]h ]h"]h$]h&]uh1jhj3hM6hjv3ubj)}(h```hw_state`` hardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](j)}(h ``hw_state``h]j )}(hj3h]hhw_state}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM;hj3ubj)}(hhh]h)}(hShardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](h5hardware configuration for the DPLL stored in struct }(hj3hhhNhNubh)}(h:c:type:`intel_dpll_hw_state`h]j )}(hj3h]hintel_dpll_hw_state}(hj3hhhNhNubah}(h]h ](xrefjkc-typeeh"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]refdocgpu/intel-display/dpll refdomainjkreftypetype refexplicitrefwarnjqjt)}jw]sb reftargetintel_dpll_hw_stateuh1hhj3hM;hj3ubh.}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj3hM;hj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hM;hjv3ubeh}(h]h ]h"]h$]h&]uh1jhj,3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubh)}(h**Description**h]j)}(hj#4h]h Description}(hj%4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!4ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM?hhhhubh)}(hXThis structure holds an atomic state for the DPLL, that can represent either its current state (in struct :c:type:`intel_shared_dpll`) or a desired future state which would be applied by an atomic mode set (stored in a struct :c:type:`intel_atomic_state`).h](hjThis structure holds an atomic state for the DPLL, that can represent either its current state (in struct }(hj94hhhNhNubh)}(h:c:type:`intel_shared_dpll`h]j )}(hjC4h]hintel_shared_dpll}(hjE4hhhNhNubah}(h]h ](j3jkc-typeeh"]h$]h&]uh1jhjA4ubah}(h]h ]h"]h$]h&]refdocj3 refdomainjkreftypetype refexplicitrefwarnjqj3j3intel_shared_dplluh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM+hj94ubh]) or a desired future state which would be applied by an atomic mode set (stored in a struct }(hj94hhhNhNubh)}(h:c:type:`intel_atomic_state`h]j )}(hjg4h]hintel_atomic_state}(hji4hhhNhNubah}(h]h ](j3jkc-typeeh"]h$]h&]uh1jhje4ubah}(h]h ]h"]h$]h&]refdocj3 refdomainjkreftypetype refexplicitrefwarnjqj3j3intel_atomic_stateuh1hhj`4hM+hj94ubh).}(hj94hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj`4hM+hhhhubh)}(hGSee also intel_reserve_shared_dplls() and intel_release_shared_dplls().h]hGSee also intel_reserve_shared_dplls() and intel_release_shared_dplls().}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM0hhhhubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jdpll_info (C struct) c.dpll_infohNtauh1j hhhhhNhNubj)}(hhh](j")}(h dpll_infoh]j()}(hstruct dpll_infoh](j.)}(hj1h]hstruct}(hj4hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj4hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM5ubj@)}(h h]h }(hj4hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj4hhhj4hM5ubj)}(h dpll_infoh]jT)}(hj4h]h dpll_info}(hj4hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj4ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj4hhhj4hM5ubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhj4hhhj4hM5ubah}(h]j4ah ](jjeh"]h$]h&]jj)jhuh1j!hj4hM5hj4hhubj)}(hhh]h)}(h"display PLL platform specific infoh]h"display PLL platform specific info}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMAhj4hhubah}(h]h ]h"]h$]h&]uh1jhj4hhhj4hM5ubeh}(h]h ](jkstructeh"]h$]h&]jjkjj5jj5jjjuh1jhhhhhNhNubj)}(hX**Definition**:: struct dpll_info { const char *name; const struct intel_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; }; **Members** ``name`` DPLL name; used for logging ``funcs`` platform specific hooks ``id`` unique identifier for this DPLL ``power_domain`` extra power domain required by the DPLL ``always_on`` Inform the state checker that the DPLL is kept enabled even if not in use by any CRTC. ``is_alt_port_dpll`` Inform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh:}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMEhj5ubjN3)}(hstruct dpll_info { const char *name; const struct intel_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; };h]hstruct dpll_info { const char *name; const struct intel_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; };}hj55sbah}(h]h ]h"]h$]h&]hhuh1jM3ht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMGhj5ubh)}(h **Members**h]j)}(hjF5h]hMembers}(hjH5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD5ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMPhj5ubj)}(hhh](j)}(h%``name`` DPLL name; used for logging h](j)}(h``name``h]j )}(hje5h]hname}(hjg5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc5ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMFhj_5ubj)}(hhh]h)}(hDPLL name; used for loggingh]hDPLL name; used for logging}(hj~5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjz5hMFhj{5ubah}(h]h ]h"]h$]h&]uh1jhj_5ubeh}(h]h ]h"]h$]h&]uh1jhjz5hMFhj\5ubj)}(h"``funcs`` platform specific hooks h](j)}(h ``funcs``h]j )}(hj5h]hfuncs}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMKhj5ubj)}(hhh]h)}(hplatform specific hooksh]hplatform specific hooks}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMKhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hMKhj\5ubj)}(h'``id`` unique identifier for this DPLL h](j)}(h``id``h]j )}(hj5h]hid}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMPhj5ubj)}(hhh]h)}(hunique identifier for this DPLLh]hunique identifier for this DPLL}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMPhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hMPhj\5ubj)}(h9``power_domain`` extra power domain required by the DPLL h](j)}(h``power_domain``h]j )}(hj6h]h power_domain}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMUhj 6ubj)}(hhh]h)}(h'extra power domain required by the DPLLh]h'extra power domain required by the DPLL}(hj)6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%6hMUhj&6ubah}(h]h ]h"]h$]h&]uh1jhj 6ubeh}(h]h ]h"]h$]h&]uh1jhj%6hMUhj\5ubj)}(he``always_on`` Inform the state checker that the DPLL is kept enabled even if not in use by any CRTC. h](j)}(h ``always_on``h]j )}(hjI6h]h always_on}(hjK6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG6ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM[hjC6ubj)}(hhh]h)}(hVInform the state checker that the DPLL is kept enabled even if not in use by any CRTC.h]hVInform the state checker that the DPLL is kept enabled even if not in use by any CRTC.}(hjb6hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMZhj_6ubah}(h]h ]h"]h$]h&]uh1jhjC6ubeh}(h]h ]h"]h$]h&]uh1jhj^6hM[hj\5ubj)}(hm``is_alt_port_dpll`` Inform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h](j)}(h``is_alt_port_dpll``h]j )}(hj6h]his_alt_port_dpll}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMbhj}6ubj)}(hhh]h)}(hXInform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h]hXInform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMbhj6ubah}(h]h ]h"]h$]h&]uh1jhj}6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMbhj\5ubeh}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dpll (C struct) c.intel_dpllhNtauh1j hhhhhNhNubj)}(hhh](j")}(h intel_dpllh]j()}(hstruct intel_dpllh](j.)}(hj1h]hstruct}(hj6hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj6hhht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMiubj@)}(h h]h }(hj6hhhNhNubah}(h]h ]jLah"]h$]h&]uh1j?hj6hhhj6hMiubj)}(h intel_dpllh]jT)}(hj6h]h intel_dpll}(hj6hhhNhNubah}(h]h ]j`ah"]h$]h&]uh1jShj6ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj6hhhj6hMiubeh}(h]h ]h"]h$]h&]hhjuh1j'jjhj6hhhj6hMiubah}(h]j6ah ](jjeh"]h$]h&]jj)jhuh1j!hj6hMihj6hhubj)}(hhh]h)}(h(display PLL with tracked state and usersh]h(display PLL with tracked state and users}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMjhj7hhubah}(h]h ]h"]h$]h&]uh1jhj6hhhj6hMiubeh}(h]h ](jkstructeh"]h$]h&]jjkjj67jj67jjjuh1jhhhhhNhNubj)}(hX**Definition**:: struct intel_dpll { struct intel_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; struct ref_tracker *wakeref; }; **Members** ``state`` Store the state for the pll, including its hw state and CRTCs using it. ``index`` index for atomic state ``active_mask`` mask of active pipes (i.e. DPMS on) using this DPLL ``on`` is the PLL actually active? Disabled during modeset ``info`` platform specific info ``wakeref`` In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabledh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjB7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>7ubh:}(hj>7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMnhj:7ubjN3)}(hstruct intel_dpll { struct intel_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; struct ref_tracker *wakeref; };h]hstruct intel_dpll { struct intel_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; struct ref_tracker *wakeref; };}hj[7sbah}(h]h ]h"]h$]h&]hhuh1jM3ht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMphj:7ubh)}(h **Members**h]j)}(hjl7h]hMembers}(hjn7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj7ubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMyhj:7ubj)}(hhh](j)}(hR``state`` Store the state for the pll, including its hw state and CRTCs using it. h](j)}(h ``state``h]j )}(hj7h]hstate}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMphj7ubj)}(hhh]h)}(hGStore the state for the pll, including its hw state and CRTCs using it.h]hGStore the state for the pll, including its hw state and CRTCs using it.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMohj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMphj7ubj)}(h!``index`` index for atomic state h](j)}(h ``index``h]j )}(hj7h]hindex}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMwhj7ubj)}(hhh]h)}(hindex for atomic stateh]hindex for atomic state}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMwhj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMwhj7ubj)}(hD``active_mask`` mask of active pipes (i.e. DPMS on) using this DPLL h](j)}(h``active_mask``h]j )}(hj7h]h active_mask}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM|hj7ubj)}(hhh]h)}(h3mask of active pipes (i.e. DPMS on) using this DPLLh]h3mask of active pipes (i.e. DPMS on) using this DPLL}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hM|hj8ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj8hM|hj7ubj)}(h;``on`` is the PLL actually active? Disabled during modeset h](j)}(h``on``h]j )}(hj78h]hon}(hj98hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj58ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhj18ubj)}(hhh]h)}(h3is the PLL actually active? Disabled during modeseth]h3is the PLL actually active? Disabled during modeset}(hjP8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjL8hMhjM8ubah}(h]h ]h"]h$]h&]uh1jhj18ubeh}(h]h ]h"]h$]h&]uh1jhjL8hMhj7ubj)}(h ``info`` platform specific info h](j)}(h``info``h]j )}(hjp8h]hinfo}(hjr8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjn8ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhjj8ubj)}(hhh]h)}(hplatform specific infoh]hplatform specific info}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhjj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhj7ubj)}(h``wakeref`` In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabledh](j)}(h ``wakeref``h]j )}(hj8h]hwakeref}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpll:13: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhj8ubj)}(hhh]h)}(h|In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabledh]h|In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabled}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhj7ubeh}(h]h ]h"]h$]h&]uh1jhj:7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubeh}(h] display-pllsah ]h"] display pllsah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj9error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}j8j8s nametypes}j8sh}(j8hjj#jjjvj{j$j)jQ jV j~ j j j%jajfjjjjj]jbjjjjj"j"j$j$j'j'jK+jP+j2j2j4j4j6j6u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.