€•¼8      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ*/translations/zh_CN/gpu/intel-display/dpio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/zh_TW/gpu/intel-display/dpio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/it_IT/gpu/intel-display/dpio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/ja_JP/gpu/intel-display/dpio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/ko_KR/gpu/intel-display/dpio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/pt_BR/gpu/intel-display/dpio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/sp_SP/gpu/intel-display/dpio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒSPDX-License-Identifier: MIT”h]”hŒSPDX-License-Identifier: MIT”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³ŒD/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio.rst”h´Kubh¶)”}”(hŒ#Copyright Â© 2026 Intel Corporation”h]”hŒ#Copyright Â© 2026 Intel Corporation”…””}”hhÈsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1hµhhh²hh³hÇh´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒDPIO”h]”hŒDPIO”…””}”(hhÝh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÛhhØh²hh³hÇh´KubhŒ	paragraph”“”)”}”(hXž  VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
ports. DPIO is the name given to such a display PHY. These PHYs
don't follow the standard programming model using direct MMIO
registers, and instead their registers must be accessed through IOSF
sideband. VLV has one such PHY for driving ports B and C, and CHV
adds another PHY for driving port D. Each PHY responds to specific
IOSF-SB port.”h]”hX   VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
ports. DPIO is the name given to such a display PHY. These PHYs
donâ€™t follow the standard programming model using direct MMIO
registers, and instead their registers must be accessed through IOSF
sideband. VLV has one such PHY for driving ports B and C, and CHV
adds another PHY for driving port D. Each PHY responds to specific
IOSF-SB port.”…””}”(hhíh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´K(hhØh²hubhì)”}”(hX9  Each display PHY is made up of one or two channels. Each channel
houses a common lane part which contains the PLL and other common
logic. CH0 common lane also contains the IOSF-SB logic for the
Common Register Interface (CRI) ie. the DPIO registers. CRI clock
must be running when any DPIO registers are accessed.”h]”hX9  Each display PHY is made up of one or two channels. Each channel
houses a common lane part which contains the PLL and other common
logic. CH0 common lane also contains the IOSF-SB logic for the
Common Register Interface (CRI) ie. the DPIO registers. CRI clock
must be running when any DPIO registers are accessed.”…””}”(hhüh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´K0hhØh²hubhì)”}”(hŒßIn addition to having their own registers, the PHYs are also
controlled through some dedicated signals from the display
controller. These include PLL reference clock enable, PLL enable,
and CRI clock selection, for example.”h]”hŒßIn addition to having their own registers, the PHYs are also
controlled through some dedicated signals from the display
controller. These include PLL reference clock enable, PLL enable,
and CRI clock selection, for example.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´K6hhØh²hubhì)”}”(hX,  Eeach channel also has two splines (also called data lanes), and
each spline is made up of one Physical Access Coding Sub-Layer
(PCS) block and two TX lanes. So each channel has two PCS blocks
and four TX lanes. The TX lanes are used as DP lanes or TMDS
data/clock pairs depending on the output type.”h]”hX,  Eeach channel also has two splines (also called data lanes), and
each spline is made up of one Physical Access Coding Sub-Layer
(PCS) block and two TX lanes. So each channel has two PCS blocks
and four TX lanes. The TX lanes are used as DP lanes or TMDS
data/clock pairs depending on the output type.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´K;hhØh²hubhì)”}”(hX$  Additionally the PHY also contains an AUX lane with AUX blocks
for each channel. This is used for DP AUX communication, but
this fact isn't really relevant for the driver since AUX is
controlled from the display controller side. No DPIO registers
need to be accessed during AUX communication,”h]”hX&  Additionally the PHY also contains an AUX lane with AUX blocks
for each channel. This is used for DP AUX communication, but
this fact isnâ€™t really relevant for the driver since AUX is
controlled from the display controller side. No DPIO registers
need to be accessed during AUX communication,”…””}”(hj)  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KAhhØh²hubhì)”}”(hŒmGenerally on VLV/CHV the common lane corresponds to the pipe and
the spline (PCS/TX) corresponds to the port.”h]”hŒmGenerally on VLV/CHV the common lane corresponds to the pipe and
the spline (PCS/TX) corresponds to the port.”…””}”(hj8  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KGhhØh²hubhì)”}”(hŒFor dual channel PHY (VLV/CHV):”h]”hŒFor dual channel PHY (VLV/CHV):”…””}”(hjG  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KJhhØh²hubhŒblock_quote”“”)”}”(hŒapipe A == CMN/PLL/REF CH0

pipe B == CMN/PLL/REF CH1

port B == PCS/TX CH0

port C == PCS/TX CH1
”h]”(hì)”}”(hŒpipe A == CMN/PLL/REF CH0”h]”hŒpipe A == CMN/PLL/REF CH0”…””}”(hj\  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KLhjX  ubhì)”}”(hŒpipe B == CMN/PLL/REF CH1”h]”hŒpipe B == CMN/PLL/REF CH1”…””}”(hjk  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KNhjX  ubhì)”}”(hŒport B == PCS/TX CH0”h]”hŒport B == PCS/TX CH0”…””}”(hjz  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KPhjX  ubhì)”}”(hŒport C == PCS/TX CH1”h]”hŒport C == PCS/TX CH1”…””}”(hj‰  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KRhjX  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jV  h³jj  h´KLhhØh²hubhì)”}”(hŒkThis is especially important when we cross the streams
ie. drive port B with pipe B, or port C with pipe A.”h]”hŒkThis is especially important when we cross the streams
ie. drive port B with pipe B, or port C with pipe A.”…””}”(hjž  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KThhØh²hubhì)”}”(hŒFor single channel PHY (CHV):”h]”hŒFor single channel PHY (CHV):”…””}”(hj­  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KWhhØh²hubjW  )”}”(hŒ0pipe C == CMN/PLL/REF CH0

port D == PCS/TX CH0
”h]”(hì)”}”(hŒpipe C == CMN/PLL/REF CH0”h]”hŒpipe C == CMN/PLL/REF CH0”…””}”(hjÀ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KYhj¼  ubhì)”}”(hŒport D == PCS/TX CH0”h]”hŒport D == PCS/TX CH0”…””}”(hjÏ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´K[hj¼  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jV  h³jÎ  h´KYhhØh²hubhì)”}”(hX3  On BXT the entire PHY channel corresponds to the port. That means
the PLL is also now associated with the port rather than the pipe,
and so the clock needs to be routed to the appropriate transcoder.
Port A PLL is directly connected to transcoder EDP and port B/C
PLLs can be routed to any transcoder A/B/C.”h]”hX3  On BXT the entire PHY channel corresponds to the port. That means
the PLL is also now associated with the port rather than the pipe,
and so the clock needs to be routed to the appropriate transcoder.
Port A PLL is directly connected to transcoder EDP and port B/C
PLLs can be routed to any transcoder A/B/C.”…””}”(hjä  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´K]hhØh²hubhì)”}”(hŒiNote: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
digital port D (CHV) or port A (BXT). ::”h]”hŒfNote: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
digital port D (CHV) or port A (BXT).”…””}”(hjó  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KchhØh²hubhŒliteral_block”“”)”}”(hXw  Dual channel PHY (VLV/CHV/BXT)
---------------------------------
|      CH0      |      CH1      |
|  CMN/PLL/REF  |  CMN/PLL/REF  |
|---------------|---------------| Display PHY
| PCS01 | PCS23 | PCS01 | PCS23 |
|-------|-------|-------|-------|
|TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
---------------------------------
|     DDI0      |     DDI1      | DP/HDMI ports
---------------------------------

Single channel PHY (CHV/BXT)
-----------------
|      CH0      |
|  CMN/PLL/REF  |
|---------------| Display PHY
| PCS01 | PCS23 |
|-------|-------|
|TX0|TX1|TX2|TX3|
-----------------
|     DDI2      | DP/HDMI port
-----------------”h]”hXw  Dual channel PHY (VLV/CHV/BXT)
---------------------------------
|      CH0      |      CH1      |
|  CMN/PLL/REF  |  CMN/PLL/REF  |
|---------------|---------------| Display PHY
| PCS01 | PCS23 | PCS01 | PCS23 |
|-------|-------|-------|-------|
|TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
---------------------------------
|     DDI0      |     DDI1      | DP/HDMI ports
---------------------------------

Single channel PHY (CHV/BXT)
-----------------
|      CH0      |
|  CMN/PLL/REF  |
|---------------| Display PHY
| PCS01 | PCS23 |
|-------|-------|
|TX0|TX1|TX2|TX3|
-----------------
|     DDI2      | DP/HDMI port
-----------------”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³Œs/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dpio:7: ./drivers/gpu/drm/i915/display/intel_dpio_phy.c”h´KghhØh²hubeh}”(h]”Œdpio”ah ]”h"]”Œdpio”ah$]”h&]”uh1hÖhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÛNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j>  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”j  j  sŒ	nametypes”}”j  ‰sh}”j  hØsŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nh²hub.