hsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget:/translations/zh_CN/gpu/intel-display/dp-link-capabilitiesmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/zh_TW/gpu/intel-display/dp-link-capabilitiesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/it_IT/gpu/intel-display/dp-link-capabilitiesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/ja_JP/gpu/intel-display/dp-link-capabilitiesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/ko_KR/gpu/intel-display/dp-link-capabilitiesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/pt_BR/gpu/intel-display/dp-link-capabilitiesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/sp_SP/gpu/intel-display/dp-link-capabilitiesmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhT/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(hDisplayPort Link Capabilitiesh]hDisplayPort Link Capabilities}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hX"The Intel DP link caps API tracks the supported and allowed DisplayPort link configurations for a DP encoder and its attached connectors, and provides helpers to iterate over the allowed configurations and constrain them by filtering, disabling, or limiting them to maximum link parameters.h]hX"The Intel DP link caps API tracks the supported and allowed DisplayPort link configurations for a DP encoder and its attached connectors, and provides helpers to iterate over the allowed configurations and constrain them by filtering, disabling, or limiting them to maximum link parameters.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:7: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.chKhhhhubh)}(hhh](h)}(hLockingh]hLocking}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhNhNubh)}(hX*All accesses to this API must be serialized. The only exception is intel_dp_link_caps_get_max_limits(), which allow lockless lookup. Such lookups may observe an out-of-sync :c:type:`struct intel_dp_link_config ` tuple, i.e. a rate from one state and a lane count from another.h](hAll accesses to this API must be serialized. The only exception is intel_dp_link_caps_get_max_limits(), which allow lockless lookup. Such lookups may observe an out-of-sync }(hj hhhNhNubh)}(h<:c:type:`struct intel_dp_link_config `h]hliteral)}(hjh]hstruct intel_dp_link_config}(hjhhhNhNubah}(h]h ](xrefcc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc&gpu/intel-display/dp-link-capabilities refdomainj&reftypetype refexplicitrefwarn reftargetintel_dp_link_configuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:7: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.chK!hj ubhA tuple, i.e. a rate from one state and a lane count from another.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj:hK!hhubh)}(hX=The Intel i915/xe drivers ensure the above serialization by holding :c:type:`drm_mode_config.connection_mutex ` and, while holding the lock, waiting for any pending asynchronous atomic commits. This also allows use of the API from the tails of asynchronous atomic commits, which cannot hold the lock.h](hDThe Intel i915/xe drivers ensure the above serialization by holding }(hjEhhhNhNubh)}(h<:c:type:`drm_mode_config.connection_mutex `h]j)}(hjOh]h drm_mode_config.connection_mutex}(hjQhhhNhNubah}(h]h ](j%j&c-typeeh"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]refdocj2 refdomainj&reftypetype refexplicitrefwarnj8drm_mode_configuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:7: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.chK'hjEubh and, while holding the lock, waiting for any pending asynchronous atomic commits. This also allows use of the API from the tails of asynchronous atomic commits, which cannot hold the lock.}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjlhK'hhubeh}(h]lockingah ]h"]lockingah$]h&]uh1hhhhhhNhNubh)}(hhh](h)}(h-Iterating and restricting link configurationsh]h-Iterating and restricting link configurations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhNhNubh)}(hThe link configuration iterators can iterate the ``allowed configurations`` during modeset configuration selection or link training fallback handling in a configurable order.h](h1The link configuration iterators can iterate the }(hjhhhNhNubj)}(h``allowed configurations``h]hallowed configurations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhc during modeset configuration selection or link training fallback handling in a configurable order.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:7: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.chK0hjubh)}(hThe iteration order can depend on connector type (eDP, DP SST, DP MST) and modeset-specific conditions or driver policies, such as DSC vs. non-DSC modes, power saving vs. better user experience, or policy changes after a link training failure.h]hThe iteration order can depend on connector type (eDP, DP SST, DP MST) and modeset-specific conditions or driver policies, such as DSC vs. non-DSC modes, power saving vs. better user experience, or policy changes after a link training failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:7: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.chK4hjubh)}(hcThe configurations exposed via the iterators can be additionally constrained in the following ways:h]hcThe configurations exposed via the iterators can be additionally constrained in the following ways:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:7: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.chK9hjubh bullet_list)}(hhh](h list_item)}(hXFiltered for a given modeset based on modeset-specific conditions. Examples for such conditions include driver policies preferring power saving or better user experience, post-link training failure preference changes, or sink automated test requests limiting the usable configurations. h]h)}(hXFiltered for a given modeset based on modeset-specific conditions. Examples for such conditions include driver policies preferring power saving or better user experience, post-link training failure preference changes, or sink automated test requests limiting the usable configurations.h]hXFiltered for a given modeset based on modeset-specific conditions. Examples for such conditions include driver policies preferring power saving or better user experience, post-link training failure preference changes, or sink automated test requests limiting the usable configurations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:7: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.chK`, for iteration queries.h](hSSelects how a caller wants the configuration table to be ordered, together with an }(hjXhhhNhNubh)}(hV:c:type:`enum intel_dp_link_caps_order_direction `h]j)}(hjbh]h'enum intel_dp_link_caps_order_direction}(hjdhhhNhNubah}(h]h ](j%j&c-typeeh"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]refdocj2 refdomainj&reftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sbj8"intel_dp_link_caps_order_directionuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKhjXubh, for iteration queries.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhhhhubjD)}(hhh]jI)}(hzSee also: - :c:type:`struct intel_dp_link_caps_order ` - intel_dp_link_caps_get_max_config() h](jO)}(h See also:h]h See also:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jNh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK"hjubji)}(hhh]j)}(hhh](j)}(hD:c:type:`struct intel_dp_link_caps_order `h]h)}(hjh]h)}(hjh]j)}(hjh]hstruct intel_dp_link_caps_order}(hjhhhNhNubah}(h]h ](j%j&c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj2 refdomainj&reftypetype refexplicitrefwarnj~jj8intel_dp_link_caps_orderuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKhjubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h'intel_dp_link_caps_get_max_config() h]h)}(h#intel_dp_link_caps_get_max_config()h]h#intel_dp_link_caps_get_max_config()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j6j7uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhhjubeh}(h]h ]h"]h$]h&]uh1jHhjhK"hjubah}(h]h ]h"]h$]h&]uh1jChhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+intel_dp_link_caps_order_direction (C enum)$c.intel_dp_link_caps_order_directionhNtauh1jhhhhhNhNubj)}(hhh](j)}(h"intel_dp_link_caps_order_directionh]j)}(h'enum intel_dp_link_caps_order_directionh](j)}(hjh]henum}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&hhh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK$ubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&hhhj7hK$ubj)}(h"intel_dp_link_caps_order_directionh]j)}(hj$h]h"intel_dp_link_caps_order_direction}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ](jjeh"]h$]h&]hhuh1jhj&hhhj7hK$ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj"hhhj7hK$ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj7hK$hjhhubj)}(hhh]h)}(hiteration directionh]hiteration direction}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK+hjihhubah}(h]h ]h"]h$]h&]uh1jhjhhhj7hK$ubeh}(h]h ](j&enumeh"]h$]h&]jj&jjjjj j!j"uh1jhhhhhNhNubj$)}(hX,**Constants** ``INTEL_DP_LINK_CAPS_ORDER_DIR_ASC`` Iterate in ascending order according to the selected ordering key. ``INTEL_DP_LINK_CAPS_ORDER_DIR_DESC`` Iterate in descending order according to the selected ordering key. ``INTEL_DP_LINK_CAPS_ORDER_DIR_NUM`` Number of ordering directions.h](h)}(h **Constants**h]j.)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j-hjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK/hjubjD)}(hhh](jI)}(hh``INTEL_DP_LINK_CAPS_ORDER_DIR_ASC`` Iterate in ascending order according to the selected ordering key. h](jO)}(h$``INTEL_DP_LINK_CAPS_ORDER_DIR_ASC``h]j)}(hjh]h INTEL_DP_LINK_CAPS_ORDER_DIR_ASC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jNh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK2hjubji)}(hhh]h)}(hBIterate in ascending order according to the selected ordering key.h]hBIterate in ascending order according to the selected ordering key.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK2hjubah}(h]h ]h"]h$]h&]uh1jhhjubeh}(h]h ]h"]h$]h&]uh1jHhjhK2hjubjI)}(hj``INTEL_DP_LINK_CAPS_ORDER_DIR_DESC`` Iterate in descending order according to the selected ordering key. h](jO)}(h%``INTEL_DP_LINK_CAPS_ORDER_DIR_DESC``h]j)}(hjh]h!INTEL_DP_LINK_CAPS_ORDER_DIR_DESC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jNh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK5hjubji)}(hhh]h)}(hCIterate in descending order according to the selected ordering key.h]hCIterate in descending order according to the selected ordering key.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK5hjubah}(h]h ]h"]h$]h&]uh1jhhjubeh}(h]h ]h"]h$]h&]uh1jHhjhK5hjubjI)}(hC``INTEL_DP_LINK_CAPS_ORDER_DIR_NUM`` Number of ordering directions.h](jO)}(h$``INTEL_DP_LINK_CAPS_ORDER_DIR_NUM``h]j)}(hjh]h INTEL_DP_LINK_CAPS_ORDER_DIR_NUM}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jNh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK7hjubji)}(hhh]h)}(hNumber of ordering directions.h]hNumber of ordering directions.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK8hj5ubah}(h]h ]h"]h$]h&]uh1jhhjubeh}(h]h ]h"]h$]h&]uh1jHhj4hK7hjubeh}(h]h ]h"]h$]h&]uh1jChjubeh}(h]h ] kernelindentah"]h$]h&]uh1j#hhhhhNhNubh)}(h**Description**h]j.)}(hjbh]h Description}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j-hj`ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK:hhhhubh)}(hSelects the direction associated with an :c:type:`enum intel_dp_link_caps_order_key ` for iteration queries.h](h)Selects the direction associated with an }(hjxhhhNhNubh)}(hJ:c:type:`enum intel_dp_link_caps_order_key `h]j)}(hjh]h!enum intel_dp_link_caps_order_key}(hjhhhNhNubah}(h]h ](j%j&c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj2 refdomainj&reftypetype refexplicitrefwarnj~jj8intel_dp_link_caps_order_keyuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK2hjxubh for iteration queries.}(hjxhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK2hhhhubjD)}(hhh]jI)}(hTSee also: - :c:type:`struct intel_dp_link_caps_order ` h](jO)}(h See also:h]h See also:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jNh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK9hjubji)}(hhh]j)}(hhh]j)}(hH:c:type:`struct intel_dp_link_caps_order ` h]h)}(hD:c:type:`struct intel_dp_link_caps_order `h]h)}(hjh]j)}(hjh]hstruct intel_dp_link_caps_order}(hjhhhNhNubah}(h]h ](j%j&c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj2 refdomainj&reftypetype refexplicitrefwarnj~jj8intel_dp_link_caps_orderuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK6hjubah}(h]h ]h"]h$]h&]uh1hhjhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j6j7uh1jhjhK6hjubah}(h]h ]h"]h$]h&]uh1jhhjubeh}(h]h ]h"]h$]h&]uh1jHhjhK9hjubah}(h]h ]h"]h$]h&]uh1jChhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#intel_dp_link_caps_order (C struct)c.intel_dp_link_caps_orderhNtauh1jhhhhhNhNubj)}(hhh](j)}(hintel_dp_link_caps_orderh]j)}(hstruct intel_dp_link_caps_orderh](j)}(hstructh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&hhh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhK;ubj)}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&hhhj8hK;ubj)}(hintel_dp_link_caps_orderh]j)}(hj$h]hintel_dp_link_caps_order}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubah}(h]h ](jjeh"]h$]h&]hhuh1jhj&hhhj8hK;ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj"hhhj8hK;ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj8hK;hjhhubj)}(hhh]h)}(hconfiguration orderingh]hconfiguration ordering}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKAhjjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj8hK;ubeh}(h]h ](j&structeh"]h$]h&]jj&jjjjj j!j"uh1jhhhhhNhNubj$)}(hX**Definition**:: struct intel_dp_link_caps_order { enum intel_dp_link_caps_order_key key; enum intel_dp_link_caps_order_direction dir; }; **Members** ``key`` Key used to order configurations. ``dir`` Direction of the selected ordering.h](h)}(h**Definition**::h](j.)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j-hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKEhjubh literal_block)}(hstruct intel_dp_link_caps_order { enum intel_dp_link_caps_order_key key; enum intel_dp_link_caps_order_direction dir; };h]hstruct intel_dp_link_caps_order { enum intel_dp_link_caps_order_key key; enum intel_dp_link_caps_order_direction dir; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKGhjubh)}(h **Members**h]j.)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j-hjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKLhjubjD)}(hhh](jI)}(h*``key`` Key used to order configurations. h](jO)}(h``key``h]j)}(hjh]hkey}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jNh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKChjubji)}(hhh]h)}(h!Key used to order configurations.h]h!Key used to order configurations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKChjubah}(h]h ]h"]h$]h&]uh1jhhjubeh}(h]h ]h"]h$]h&]uh1jHhjhKChjubjI)}(h+``dir`` Direction of the selected ordering.h](jO)}(h``dir``h]j)}(hj h]hdir}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jNh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKDhj ubji)}(hhh]h)}(h#Direction of the selected ordering.h]h#Direction of the selected ordering.}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKEhj+ ubah}(h]h ]h"]h$]h&]uh1jhhj ubeh}(h]h ]h"]h$]h&]uh1jHhj* hKDhjubeh}(h]h ]h"]h$]h&]uh1jChjubeh}(h]h ] kernelindentah"]h$]h&]uh1j#hhhhhNhNubh)}(h**Description**h]j.)}(hjX h]h Description}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1j-hjV ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dp-link-capabilities:10: ./drivers/gpu/drm/i915/display/intel_dp_link_caps.hhKHhhhhubh)}(h5Describes an iteration order for link configurations.h]h5Describes an iteration order for link configurations.}(hjn hhhNhNubah}(h]h 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