sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget)/translations/zh_CN/gpu/intel-display/dmcmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/zh_TW/gpu/intel-display/dmcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/it_IT/gpu/intel-display/dmcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ja_JP/gpu/intel-display/dmcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ko_KR/gpu/intel-display/dmcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/pt_BR/gpu/intel-display/dmcmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/sp_SP/gpu/intel-display/dmcmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhC/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhtarget)}(h.. _drm/intel-display/dmc:h]h}(h]h ]h"]h$]h&]refiddrm-intel-display-dmcuh1hhKhhhhhhubhsection)}(hhh](htitle)}(hDMC Firmware Supporth]hDMC Firmware Support}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hFrom gen9 onwards we have newly added DMC (Display microcontroller) in display engine to save and restore the state of display engine when it enter into low-power state and comes back to normal.h]hFrom gen9 onwards we have newly added DMC (Display microcontroller) in display engine to save and restore the state of display engine when it enter into low-power state and comes back to normal.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhm/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:9: ./drivers/gpu/drm/i915/display/intel_dmc.chK,hhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single!intel_dmc_block_pkgc (C function)c.intel_dmc_block_pkgchNtauh1j hhhhhNhNubhdesc)}(hhh](hdesc_signature)}(hUvoid intel_dmc_block_pkgc (struct intel_display *display, enum pipe pipe, bool block)h]hdesc_signature_line)}(hTvoid intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, bool block)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hj.hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j,hj(hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMlubhdesc_sig_space)}(h h]h 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]h"]h$]h&]noemphhhuh1jthjpubju)}(henum pipe pipeh](j{)}(henumh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhjubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjubh)}(hhh]jV)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.intel_dmc_block_pkgcasbuh1hhjubj?)}(h h]h }(hj:hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjubjV)}(hpipeh]hpipe}(hjHhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jthjpubju)}(h bool blockh](j-)}(hboolh]hbool}(hjahhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hj]ubj?)}(h h]h }(hjohhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj]ubjV)}(hblockh]hblock}(hj}hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj]ubeh}(h]h ]h"]h$]h&]noemphhhuh1jthjpubeh}(h]h ]h"]h$]h&]hhuh1jnhj(hhhj=hMlubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1j&sphinx_line_type declaratorhj"hhhj=hMlubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j hj=hMlhjhhubh desc_content)}(hhh]h)}(hblock PKG C-stateh]hblock PKG C-state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMlhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj=hMlubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhhhNhNubh container)}(hXA**Parameters** ``struct intel_display *display`` display instance ``enum pipe pipe`` pipe which register use to block ``bool block`` block/unblock **Description** This interface is target for Wa_16025596647 usage. I.e. to set/clear PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register.h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMphjubhdefinition_list)}(hhh](hdefinition_list_item)}(h3``struct intel_display *display`` display instance h](hterm)}(h!``struct intel_display *display``h]hliteral)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMmhjubh definition)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMmhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMmhjubj)}(h4``enum pipe pipe`` pipe which register use to block h](j)}(h``enum pipe pipe``h]j)}(hj?h]henum pipe pipe}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMnhj9ubj)}(hhh]h)}(h pipe which register use to blockh]h pipe which register use to block}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThMnhjUubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhjThMnhjubj)}(h``bool block`` block/unblock h](j)}(h``bool block``h]j)}(hjxh]h bool block}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMohjrubj)}(hhh]h)}(h block/unblockh]h block/unblock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMohjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jhjhMohjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMqhjubh)}(hThis interface is target for Wa_16025596647 usage. I.e. to set/clear PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register.h]hThis interface is target for Wa_16025596647 usage. I.e. to set/clear PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMphjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jCintel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank (C function)8c.intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankhNtauh1j hhhhhNhNubj)}(hhh](j!)}(hxvoid intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank (struct intel_display *display, enum pipe pipe, bool enable)h]j')}(hwvoid intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, enum pipe pipe, bool enable)h](j-)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chM}ubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjhhhjhM}ubjP)}(h6intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankh]jV)}(h6intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankh]h6intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubah}(h]h ](jijjeh"]h$]h&]hhuh1jOhjhhhjhM}ubjo)}(h<(struct intel_display *display, enum pipe pipe, bool enable)h](ju)}(hstruct intel_display *displayh](j{)}(hj~h]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhj1ubj?)}(h h]h }(hjBhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj1ubh)}(hhh]jV)}(h intel_displayh]h intel_display}(hjShhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjPubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]j)}jjsb8c.intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankasbuh1hhj1ubj?)}(h h]h }(hjshhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj1ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubjV)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj1ubeh}(h]h ]h"]h$]h&]noemphhhuh1jthj-ubju)}(henum pipe pipeh](j{)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhjubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjubh)}(hhh]jV)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jo8c.intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankasbuh1hhjubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjubjV)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jthj-ubju)}(h bool enableh](j-)}(hjch]hbool}(hj hhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hjubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjubjV)}(henableh]henable}(hj%hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jthj-ubeh}(h]h ]h"]h$]h&]hhuh1jnhjhhhjhM}ubeh}(h]h ]h"]h$]h&]hhjuh1j&jjhjhhhjhM}ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j hjhM}hjhhubj)}(hhh]h)}(hstart of PKG C-state exith]hstart of PKG C-state exit}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chM}hjLhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM}ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjgjjgjjjuh1jhhhhhNhNubj)}(hX%**Parameters** ``struct intel_display *display`` display instance ``enum pipe pipe`` pipe which register use to block ``bool enable`` enable/disable **Description** This interface is target for Wa_16025596647 usage. I.e. start the package C exit at the start of the undelayed vblankh](h)}(h**Parameters**h]j)}(hjqh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjkubj)}(hhh](j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h4``enum pipe pipe`` pipe which register use to block h](j)}(h``enum pipe pipe``h]j)}(hjh]henum pipe pipe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]h)}(h pipe which register use to blockh]h pipe which register use to block}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``bool enable`` enable/disable h](j)}(h``bool enable``h]j)}(hjh]h bool enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]h)}(henable/disableh]henable/disable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjkubh)}(h**Description**h]j)}(hj=h]h Description}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjkubh)}(huThis interface is target for Wa_16025596647 usage. I.e. start the package C exit at the start of the undelayed vblankh]huThis interface is target for Wa_16025596647 usage. I.e. start the package C exit at the start of the undelayed vblank}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjkubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j#intel_dmc_load_program (C function)c.intel_dmc_load_programhNtauh1j hhhhhNhNubj)}(hhh](j!)}(h;void intel_dmc_load_program (struct intel_display *display)h]j')}(h:void intel_dmc_load_program(struct intel_display *display)h](j-)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hj~hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj~hhhjhMubjP)}(hintel_dmc_load_programh]jV)}(hintel_dmc_load_programh]hintel_dmc_load_program}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubah}(h]h ](jijjeh"]h$]h&]hhuh1jOhj~hhhjhMubjo)}(h(struct intel_display *display)h]ju)}(hstruct intel_display *displayh](j{)}(hj~h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhjubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjubh)}(hhh]jV)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.intel_dmc_load_programasbuh1hhjubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjV)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jthjubah}(h]h ]h"]h$]h&]hhuh1jnhj~hhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1j&jjhjzhhhjhMubah}(h]juah ](jjeh"]h$]h&]jj)jhuh1j hjhMhjwhhubj)}(hhh]h)}(h+write the firmware from memory to register.h]h+write the firmware from memory to register.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj?hhubah}(h]h ]h"]h$]h&]uh1jhjwhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjZjjZjjjuh1jhhhhhNhNubj)}(hX$**Parameters** ``struct intel_display *display`` display instance **Description** DMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.h](h)}(h**Parameters**h]j)}(hjdh]h Parameters}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj^ubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj}ubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhjhMhjzubah}(h]h ]h"]h$]h&]uh1jhj^ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj^ubh)}(hDMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.h]hDMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj^ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](j&intel_dmc_disable_program (C function)c.intel_dmc_disable_programhNtauh1j hhhhhNhNubj)}(hhh](j!)}(h>void intel_dmc_disable_program (struct intel_display *display)h]j')}(h=void intel_dmc_disable_program(struct intel_display *display)h](j-)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjhhhjhMubjP)}(hintel_dmc_disable_programh]jV)}(hintel_dmc_disable_programh]hintel_dmc_disable_program}(hj$hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj ubah}(h]h ](jijjeh"]h$]h&]hhuh1jOhjhhhjhMubjo)}(h(struct intel_display *display)h]ju)}(hstruct intel_display *displayh](j{)}(hj~h]hstruct}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhj<ubj?)}(h h]h }(hjMhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj<ubh)}(hhh]jV)}(h intel_displayh]h intel_display}(hj^hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj[ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj`modnameN classnameNjj)}j]j)}jj&sbc.intel_dmc_disable_programasbuh1hhj<ubj?)}(h h]h }(hj~hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj<ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubjV)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj<ubeh}(h]h ]h"]h$]h&]noemphhhuh1jthj8ubah}(h]h ]h"]h$]h&]hhuh1jnhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1j&jjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j hjhMhjhhubj)}(hhh]h)}(hdisable the firmwareh]hdisable the firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Disable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj? h]h Description}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj= ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubh)}(htDisable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.h]htDisable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dmc_init (C function)c.intel_dmc_inithNtauh1j hhhhhNhNubj)}(hhh](j!)}(h3void intel_dmc_init (struct intel_display *display)h]j')}(h2void intel_dmc_init(struct intel_display *display)h](j-)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hj hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chM}ubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj hhhj hM}ubjP)}(hintel_dmc_inith]jV)}(hintel_dmc_inith]hintel_dmc_init}(hj hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj ubah}(h]h ](jijjeh"]h$]h&]hhuh1jOhj hhhj hM}ubjo)}(h(struct intel_display *display)h]ju)}(hstruct intel_display *displayh](j{)}(hj~h]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhj ubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj ubh)}(hhh]jV)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jj sbc.intel_dmc_initasbuh1hhj ubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjV)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jthj ubah}(h]h ]h"]h$]h&]hhuh1jnhj hhhj hM}ubeh}(h]h ]h"]h$]h&]hhjuh1j&jjhj| hhhj hM}ubah}(h]jw ah ](jjeh"]h$]h&]jj)jhuh1j hj hM}hjy hhubj)}(hhh]h)}(h initialize the firmware loading.h]h initialize the firmware loading.}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chM}hjA hhubah}(h]h ]h"]h$]h&]uh1jhjy hhhj hM}ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj\ jj\ jjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` display instance **Description** This function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.h](h)}(h**Parameters**h]j)}(hjf h]h Parameters}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjd ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj` ubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chM~hj ubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM~hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hM~hj| ubah}(h]h ]h"]h$]h&]uh1jhj` ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj` ubh)}(hThis function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.h]hThis function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj` ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dmc_suspend (C function)c.intel_dmc_suspendhNtauh1j hhhhhNhNubj)}(hhh](j!)}(h6void intel_dmc_suspend (struct intel_display *display)h]j')}(h5void intel_dmc_suspend(struct intel_display *display)h](j-)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hj hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj hhhj hMubjP)}(hintel_dmc_suspendh]jV)}(hintel_dmc_suspendh]hintel_dmc_suspend}(hj& hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj" ubah}(h]h ](jijjeh"]h$]h&]hhuh1jOhj hhhj hMubjo)}(h(struct intel_display *display)h]ju)}(hstruct intel_display *displayh](j{)}(hj~h]hstruct}(hjB hhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhj> ubj?)}(h h]h }(hjO hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj> ubh)}(hhh]jV)}(h intel_displayh]h intel_display}(hj` hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj] ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjb modnameN classnameNjj)}j]j)}jj( sbc.intel_dmc_suspendasbuh1hhj> ubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj> ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj> ubjV)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj> ubeh}(h]h ]h"]h$]h&]noemphhhuh1jthj: ubah}(h]h ]h"]h$]h&]hhuh1jnhj hhhj hMubeh}(h]h ]h"]h$]h&]hhjuh1j&jjhj hhhj hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j hj hMhj hhubj)}(hhh]h)}(h*prepare DMC firmware before system suspendh]h*prepare DMC firmware before system suspend}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Prepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj ubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj ubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hjA h]h Description}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj? ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj ubh)}(hPrepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.h]hPrepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dmc_resume (C function)c.intel_dmc_resumehNtauh1j hhhhhNhNubj)}(hhh](j!)}(h5void intel_dmc_resume (struct intel_display *display)h]j')}(h4void intel_dmc_resume(struct intel_display *display)h](j-)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hj hhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj hhhj hMubjP)}(hintel_dmc_resumeh]jV)}(hintel_dmc_resumeh]hintel_dmc_resume}(hj hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj ubah}(h]h ](jijjeh"]h$]h&]hhuh1jOhj hhhj hMubjo)}(h(struct intel_display *display)h]ju)}(hstruct intel_display *displayh](j{)}(hj~h]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhj ubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj ubh)}(hhh]jV)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jj sbc.intel_dmc_resumeasbuh1hhj ubj?)}(h h]h }(hj hhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjV)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jthj ubah}(h]h ]h"]h$]h&]hhuh1jnhj hhhj hMubeh}(h]h ]h"]h$]h&]hhjuh1j&jjhj~ hhhj hMubah}(h]jy ah ](jjeh"]h$]h&]jj)jhuh1j hj hMhj{ hhubj)}(hhh]h)}(h&init DMC firmware during system resumeh]h&init DMC firmware during system resume}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjC hhubah}(h]h ]h"]h$]h&]uh1jhj{ hhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj^ jj^ jjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Reinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().h](h)}(h**Parameters**h]j)}(hjh h]h Parameters}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjb ubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj h]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj ubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj~ ubah}(h]h ]h"]h$]h&]uh1jhjb ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjb ubh)}(hnReinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().h]hnReinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjb ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj )}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_dmc_fini (C function)c.intel_dmc_finihNtauh1j hhhhhNhNubj)}(hhh](j!)}(h3void intel_dmc_fini (struct intel_display *display)h]j')}(h2void intel_dmc_fini(struct intel_display *display)h](j-)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j9ah"]h$]h&]uh1j,hjhhhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hjhhhjhMubjP)}(hintel_dmc_finih]jV)}(hintel_dmc_finih]hintel_dmc_fini}(hj(hhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj$ubah}(h]h ](jijjeh"]h$]h&]hhuh1jOhjhhhjhMubjo)}(h(struct intel_display *display)h]ju)}(hstruct intel_display *displayh](j{)}(hj~h]hstruct}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhj@ubj?)}(h h]h }(hjQhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj@ubh)}(hhh]jV)}(h intel_displayh]h intel_display}(hjbhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj_ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjdmodnameN classnameNjj)}j]j)}jj*sbc.intel_dmc_finiasbuh1hhj@ubj?)}(h h]h }(hjhhhNhNubah}(h]h ]jKah"]h$]h&]uh1j>hj@ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubjV)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jbah"]h$]h&]uh1jUhj@ubeh}(h]h ]h"]h$]h&]noemphhhuh1jthj<ubah}(h]h ]h"]h$]h&]hhuh1jnhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1j&jjhj hhhjhMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j hjhMhj hhubj)}(hhh]h)}(hunload the DMC firmware.h]hunload the DMC firmware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj hhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Firmmware unloading includes freeing the internal memory and reset the firmware loading status.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjCh]h Description}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubh)}(h_Firmmware unloading includes freeing the internal memory and reset the firmware loading status.h]h_Firmmware unloading includes freeing the internal memory and reset the firmware loading status.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:12: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubeh}(h](dmc-firmware-supportheh ]h"](dmc firmware supportdrm/intel-display/dmceh$]h&]uh1hhhhhhhhKexpect_referenced_by_name}juhsexpect_referenced_by_id}hhsubh)}(hhh](h)}(hDMC Flip Queueh]hDMC Flip Queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hhhhhKubh)}(hA flip queue is a ring buffer implemented by the pipe DMC firmware. The driver inserts entries into the queues to be executed by the pipe DMC at a specified presentation timestamp (PTS).h]hA flip queue is a ring buffer implemented by the pipe DMC firmware. The driver inserts entries into the queues to be executed by the pipe DMC at a specified presentation timestamp (PTS).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:19: ./drivers/gpu/drm/i915/display/intel_flipq.chKhj|hhubh)}(h&Each pipe DMC provides several queues:h]h&Each pipe DMC provides several queues:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:19: ./drivers/gpu/drm/i915/display/intel_flipq.chKhj|hhubh bullet_list)}(hhh](h list_item)}(h41 general queue (two DSB buffers executed per entry)h]h)}(hjh]h41 general queue (two DSB buffers executed per entry)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:19: ./drivers/gpu/drm/i915/display/intel_flipq.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h23 plane queues (one DSB buffer executed per entry)h]h)}(hjh]h23 plane queues (one DSB buffer executed per entry)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:19: ./drivers/gpu/drm/i915/display/intel_flipq.chK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h1 fast queue (deprecated) h]h)}(h1 fast queue (deprecated)h]h1 fast queue (deprecated)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhp/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:19: ./drivers/gpu/drm/i915/display/intel_flipq.chK!hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhjhKhj|hhubeh}(h]dmc-flip-queueah ]h"]dmc flip queueah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDMC wakelock supporth]hDMC wakelock support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hXWake lock is the mechanism to cause display engine to exit DC states to allow programming to registers that are powered down in those states. Previous projects exited DC states automatically when detecting programming. Now software controls the exit by programming the wake lock. This improves system performance and system interactions and better fits the flip queue style of programming. Wake lock is only required when DC5, DC6, or DC6v have been enabled in DC_STATE_EN and the wake lock mode of operation has been enabled.h]hXWake lock is the mechanism to cause display engine to exit DC states to allow programming to registers that are powered down in those states. Previous projects exited DC states automatically when detecting programming. Now software controls the exit by programming the wake lock. This improves system performance and system interactions and better fits the flip queue style of programming. Wake lock is only required when DC5, DC6, or DC6v have been enabled in DC_STATE_EN and the wake lock mode of operation has been enabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:25: ./drivers/gpu/drm/i915/display/intel_dmc_wl.chKhj hhubh)}(hXThe wakelock mechanism in DMC allows the display engine to exit DC states explicitly before programming registers that may be powered down. In earlier hardware, this was done automatically and implicitly when the display engine accessed a register. With the wakelock implementation, the driver asserts a wakelock in DMC, which forces it to exit the DC state until the wakelock is deasserted.h]hXThe wakelock mechanism in DMC allows the display engine to exit DC states explicitly before programming registers that may be powered down. In earlier hardware, this was done automatically and implicitly when the display engine accessed a register. With the wakelock implementation, the driver asserts a wakelock in DMC, which forces it to exit the DC state until the wakelock is deasserted.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:25: ./drivers/gpu/drm/i915/display/intel_dmc_wl.chKhj hhubh)}(hXMThe mechanism can be enabled and disabled by writing to the DMC_WAKELOCK_CFG register. There are also 13 control registers that can be used to hold and release different wakelocks. In the current implementation, we only need one wakelock, so only DMC_WAKELOCK1_CTL is used. The other definitions are here for potential future use.h]hXMThe mechanism can be enabled and disabled by writing to the DMC_WAKELOCK_CFG register. There are also 13 control registers that can be used to hold and release different wakelocks. In the current implementation, we only need one wakelock, so only DMC_WAKELOCK1_CTL is used. The other definitions are here for potential future use.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/dmc:25: ./drivers/gpu/drm/i915/display/intel_dmc_wl.chK"hj hhubh)}(hXMThis is available starting with Xe2_LPD (display version 20) as an experimental feature and on Xe3_LPD (display version 30) as the first display release with official support. That means that we only enable the feature by default on the latter and using it on the former requires explicitly using the enable_dmc_wl module parameter.h]hXMThis is available starting with Xe2_LPD (display version 20) as an experimental feature and on Xe3_LPD (display version 30) as the first display release with official support. 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