€•#Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ*/translations/zh_CN/gpu/intel-display/cmtg”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/zh_TW/gpu/intel-display/cmtg”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/it_IT/gpu/intel-display/cmtg”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/ja_JP/gpu/intel-display/cmtg”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/ko_KR/gpu/intel-display/cmtg”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/pt_BR/gpu/intel-display/cmtg”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/sp_SP/gpu/intel-display/cmtg”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒSPDX-License-Identifier: MIT”h]”hŒSPDX-License-Identifier: MIT”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³ŒD/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cmtg.rst”h´Kubh¶)”}”(hŒ#Copyright © 2026 Intel Corporation”h]”hŒ#Copyright © 2026 Intel Corporation”…””}”hhÈsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1hµhhh²hh³hÇh´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ&Common Primary Timing Generator (CMTG)”h]”hŒ&Common Primary Timing Generator (CMTG)”…””}”(hhÝh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÛhhØh²hh³hÇh´KubhŒ paragraph”“”)”}”(hXThe CMTG is a timing generator that runs in parallel to transcoders timing generators (TG) to provide a synchronization mechanism where CMTG acts as primary and transcoders TGs act as secondary to the CMTG. The CMTG outputs its TG start and frame sync signals to the transcoders that are configured as secondary, which use those signals to synchronize their own timing with the CMTG's.”h]”hXƒThe CMTG is a timing generator that runs in parallel to transcoders timing generators (TG) to provide a synchronization mechanism where CMTG acts as primary and transcoders TGs act as secondary to the CMTG. The CMTG outputs its TG start and frame sync signals to the transcoders that are configured as secondary, which use those signals to synchronize their own timing with the CMTG’s.”…””}”(hhíh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œo/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cmtg:7: ./drivers/gpu/drm/i915/display/intel_cmtg.c”h´KhhØh²hubhì)”}”(hŒ]The CMTG can be used only with eDP or MIPI command mode and supports the following use cases:”h]”hŒ]The CMTG can be used only with eDP or MIPI command mode and supports the following use cases:”…””}”(hhüh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œo/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cmtg:7: ./drivers/gpu/drm/i915/display/intel_cmtg.c”h´KhhØh²hubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ€Dual eDP: The CMTG can be used to keep two eDP TGs in sync when on a dual eDP configuration (with or without PSR/PSR2 enabled). ”h]”hì)”}”(hŒDual eDP: The CMTG can be used to keep two eDP TGs in sync when on a dual eDP configuration (with or without PSR/PSR2 enabled).”h]”hŒDual eDP: The CMTG can be used to keep two eDP TGs in sync when on a dual eDP configuration (with or without PSR/PSR2 enabled).”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œo/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cmtg:7: ./drivers/gpu/drm/i915/display/intel_cmtg.c”h´Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj ubj)”}”(hX Single eDP as secondary: It is also possible to use a single eDP configuration with the transcoder TG as secondary to the CMTG. That would allow a flow that would not require a modeset on the existing eDP when a new eDP is added for a dual eDP configuration with CMTG. ”h]”hì)”}”(hX Single eDP as secondary: It is also possible to use a single eDP configuration with the transcoder TG as secondary to the CMTG. That would allow a flow that would not require a modeset on the existing eDP when a new eDP is added for a dual eDP configuration with CMTG.”h]”hX Single eDP as secondary: It is also possible to use a single eDP configuration with the transcoder TG as secondary to the CMTG. That would allow a flow that would not require a modeset on the existing eDP when a new eDP is added for a dual eDP configuration with CMTG.”…””}”(hj/h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³Œo/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cmtg:7: ./drivers/gpu/drm/i915/display/intel_cmtg.c”h´K"hj+ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj ubj)”}”(hŒ¤DC6v: In DC6v, the transcoder might be off but the CMTG keeps running to maintain frame timings. When exiting DC6v, the transcoder TG then is synced back the CMTG. ”h]”hì)”}”(hŒ£DC6v: In DC6v, the transcoder might be off but the CMTG keeps running to maintain frame timings. When exiting DC6v, the transcoder TG then is synced back the CMTG.”h]”hŒ£DC6v: In DC6v, the transcoder might be off but the CMTG keeps running to maintain frame timings. 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