Dsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget+/translations/zh_CN/gpu/intel-display/cdclkmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/zh_TW/gpu/intel-display/cdclkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/it_IT/gpu/intel-display/cdclkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/ja_JP/gpu/intel-display/cdclkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/ko_KR/gpu/intel-display/cdclkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/pt_BR/gpu/intel-display/cdclkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/sp_SP/gpu/intel-display/cdclkmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(hSPDX-License-Identifier: MITh]hSPDX-License-Identifier: MIT}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhE/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk.rsthKubh)}(h#Copyright © 2026 Intel Corporationh]h#Copyright © 2026 Intel Corporation}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsection)}(hhh](htitle)}(hDisplay clocksh]hDisplay clocks}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThe display engine uses several different clocks to do its work. There are two main clocks involved that aren't directly related to the actual pixel clock or any symbol/bit clock of the actual output port. These are the core display clock (CDCLK) and RAWCLK.h]hXThe display engine uses several different clocks to do its work. There are two main clocks involved that aren’t directly related to the actual pixel clock or any symbol/bit clock of the actual output port. These are the core display clock (CDCLK) and RAWCLK.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chK:hhhhubh)}(hCDCLK clocks most of the display pipe logic, and thus its frequency must be high enough to support the rate at which pixels are flowing through the pipes. Downscaling must also be accounted as that increases the effective pixel rate.h]hCDCLK clocks most of the display pipe logic, and thus its frequency must be high enough to support the rate at which pixels are flowing through the pipes. Downscaling must also be accounted as that increases the effective pixel rate.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chK?hhhhubh)}(hXOn several platforms the CDCLK frequency can be changed dynamically to minimize power consumption for a given display configuration. Typically changes to the CDCLK frequency require all the display pipes to be shut down while the frequency is being changed.h]hXOn several platforms the CDCLK frequency can be changed dynamically to minimize power consumption for a given display configuration. Typically changes to the CDCLK frequency require all the display pipes to be shut down while the frequency is being changed.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKDhhhhubh)}(hOn SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. DMC will not change the active CDCLK frequency however, so that part will still be performed by the driver directly.h]hOn SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. DMC will not change the active CDCLK frequency however, so that part will still be performed by the driver directly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKIhhhhubh)}(hPThere are multiple components involved in the generation of the CDCLK frequency:h]hPThere are multiple components involved in the generation of the CDCLK frequency:}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKMhhhhubh bullet_list)}(hhh](h list_item)}(hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.h]h)}(hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.h]hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKPhj?ubah}(h]h ]h"]h$]h&]uh1j=hj:ubj>)}(htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.h]h)}(htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.h]htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKRhjXubah}(h]h ]h"]h$]h&]uh1j=hj:ubj>)}(hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero "squashes out" a clock cycle.h]h)}(hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero "squashes out" a clock cycle.h]hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero “squashes out” a clock cycle.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKThjqubah}(h]h ]h"]h$]h&]uh1j=hj:ubj>)}(hFAnd, finally, a fixed divider that divides the output frequency by 2. h]h)}(hEAnd, finally, a fixed divider that divides the output frequency by 2.h]hEAnd, finally, a fixed divider that divides the output frequency by 2.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKWhjubah}(h]h ]h"]h$]h&]uh1j=hj:ubeh}(h]h ]h"]h$]h&]bullet-uh1j8hjQhKPhhhhubh)}(hTAs such, the resulting CDCLK frequency can be calculated with the following formula:h]hTAs such, the resulting CDCLK frequency can be calculated with the following formula:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKYhhhhubh block_quote)}(h/cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 h]h)}(h.cdclk = vco / cd2x_div / (sq_len / sq_div) / 2h]h.cdclk = vco / cd2x_div / (sq_len / sq_div) / 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chK\hjubah}(h]h ]h"]h$]h&]uh1jhjhK\hhhhubh)}(h, where vco is the frequency generated by the PLL; cd2x_div represents the CD2X Divider; sq_len and sq_div are the bit length and the number of high bits for the CD2X Squasher waveform, respectively; and 2 represents the fixed divider.h]h, where vco is the frequency generated by the PLL; cd2x_div represents the CD2X Divider; sq_len and sq_div are the bit length and the number of high bits for the CD2X Squasher waveform, respectively; and 2 represents the fixed divider.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chK^hhhhubh)}(hNote that some older platforms do not contain the CD2X Divider and/or CD2X Squasher, in which case we can ignore their respective factors in the formula above.h]hNote that some older platforms do not contain the CD2X Divider and/or CD2X Squasher, in which case we can ignore their respective factors in the formula above.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKchhhhubh)}(hfSeveral methods exist to change the CDCLK frequency, which ones are supported depends on the platform:h]hfSeveral methods exist to change the CDCLK frequency, which ones are supported depends on the platform:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKghhhhubj9)}(hhh](j>)}(hLFull PLL disable + re-enable with new VCO frequency. Pipes must be inactive.h]h)}(hjh]hLFull PLL disable + re-enable with new VCO frequency. Pipes must be inactive.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKjhjubah}(h]h ]h"]h$]h&]uh1j=hjubj>)}(hyCD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe's start of vblank.h]h)}(hyCD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe's start of vblank.h]h{CD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe’s start of vblank.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKkhjubah}(h]h ]h"]h$]h&]uh1j=hjubj>)}(hECrawl the PLL smoothly to the new VCO frequency. Pipes can be active.h]h)}(hj8h]hECrawl the PLL smoothly to the new VCO frequency. Pipes can be active.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKmhj6ubah}(h]h ]h"]h$]h&]uh1j=hjubj>)}(h,Squash waveform update. Pipes can be active.h]h)}(hjPh]h,Squash waveform update. Pipes can be active.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKnhjNubah}(h]h ]h"]h$]h&]uh1j=hjubj>)}(hECrawl and squash can also be done back to back. Pipes can be active. h]h)}(hDCrawl and squash can also be done back to back. Pipes can be active.h]hDCrawl and squash can also be done back to back. Pipes can be active.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKohjfubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]jjuh1j8hjhKjhhhhubh)}(hRAWCLK is a fixed frequency clock, often used by various auxiliary blocks such as AUX CH or backlight PWM. Hence the only thing we really need to know about RAWCLK is its frequency so that various dividers can be programmed correctly.h]hRAWCLK is a fixed frequency clock, often used by various auxiliary blocks such as AUX CH or backlight PWM. Hence the only thing we really need to know about RAWCLK is its frequency so that various dividers can be programmed correctly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhq/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:7: ./drivers/gpu/drm/i915/display/intel_cdclk.chKqhhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single intel_cdclk_init_hw (C function)c.intel_cdclk_init_hwhNtauh1jhhhhhNhNubhdesc)}(hhh](hdesc_signature)}(h8void intel_cdclk_init_hw (struct intel_display *display)h]hdesc_signature_line)}(h7void intel_cdclk_init_hw(struct intel_display *display)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjhhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhM ubh desc_name)}(hintel_cdclk_init_hwh]h desc_sig_name)}(hintel_cdclk_init_hwh]hintel_cdclk_init_hw}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjhhhjhM ubhdesc_parameterlist)}(h(struct intel_display *display)h]hdesc_parameter)}(hstruct intel_display *displayh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_displayh]h intel_display}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetj(modnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]jB ASTIdentifier)}j=jsbc.intel_cdclk_init_hwasbuh1hhjubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubhdesc_sig_punctuation)}(h*h]h*}(hj_hhhNhNubah}(h]h ]pah"]h$]h&]uh1j]hjubj)}(hdisplayh]hdisplay}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1jsphinx_line_type declaratorhjhhhjhM ubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhM hjhhubh desc_content)}(hhh]h)}(hInitialize CDCLK hardwareh]hInitialize CDCLK hardware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](j;functioneh"]h$]h&]domainj;objtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhhhNhNubh container)}(hXf**Parameters** ``struct intel_display *display`` display instance **Description** Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubhdefinition_list)}(hhh]hdefinition_list_item)}(h3``struct intel_display *display`` display instance h](hterm)}(h!``struct intel_display *display``h]hliteral)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh definition)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj hM hjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj2h]h Description}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh)}(hXInitialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.h]hXInitialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_cdclk_uninit_hw (C function)c.intel_cdclk_uninit_hwhNtauh1jhhhhhNhNubj)}(hhh](j)}(h:void intel_cdclk_uninit_hw (struct intel_display *display)h]j)}(h9void intel_cdclk_uninit_hw(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjshhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjshhhjhM ubj)}(hintel_cdclk_uninit_hwh]j)}(hintel_cdclk_uninit_hwh]hintel_cdclk_uninit_hw}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjshhhjhM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjmodnameN classnameNjAjD)}jG]jJ)}j=jsbc.intel_cdclk_uninit_hwasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(hjah]h*}(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjshhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjohhhjhM ubah}(h]jjah ](jjeh"]h$]h&]jj)jhuh1jhjhM hjlhhubj)}(hhh]h)}(hUninitialize CDCLK hardwareh]hUninitialize CDCLK hardware}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj4hhubah}(h]h ]h"]h$]h&]uh1jhjlhhhjhM ubeh}(h]h ](j;functioneh"]h$]h&]jj;jjOjjOjjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Uninitialize CDCLK. This is done only during the display core uninitialization sequence.h](h)}(h**Parameters**h]j)}(hjYh]h Parameters}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjSubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjxh]hstruct intel_display *display}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjrubj )}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j hjrubeh}(h]h ]h"]h$]h&]uh1jhjhM hjoubah}(h]h ]h"]h$]h&]uh1jhjSubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjSubh)}(hXUninitialize CDCLK. This is done only during the display core uninitialization sequence.h]hXUninitialize CDCLK. This is done only during the display core uninitialization sequence.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&intel_cdclk_clock_changed (C function)c.intel_cdclk_clock_changedhNtauh1jhhhhhNhNubj)}(hhh](j)}(hgbool intel_cdclk_clock_changed (const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j)}(hfbool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM ubj)}(hintel_cdclk_clock_changedh]j)}(hintel_cdclk_clock_changedh]hintel_cdclk_clock_changed}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(hH(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(h"const struct intel_cdclk_config *ah](j)}(hconsth]hconst}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj)}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubh)}(hhh]j)}(hintel_cdclk_configh]hintel_cdclk_config}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjqmodnameN classnameNjAjD)}jG]jJ)}j=jsbc.intel_cdclk_clock_changedasbuh1hhj1ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj^)}(hjah]h*}(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj1ubj)}(hah]ha}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj-ubj)}(h"const struct intel_cdclk_config *bh](j)}(hj7h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjmodnameN classnameNjAjD)}jG]jc.intel_cdclk_clock_changedasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(hjah]h*}(hj(hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hbh]hb}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj-ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM hjhhubj)}(hhh]h)}(hCheck whether the clock changedh]hCheck whether the clock changed}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj\hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](j;functioneh"]h$]h&]jj;jjwjjwjjjuh1jhhhhhNhNubj)}(h**Parameters** ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if CDCLK changed in a way that requires re-programming and False otherwise.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj{ubj)}(hhh](j)}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hjh]h"const struct intel_cdclk_config *a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj )}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hjh]h"const struct intel_cdclk_config *b}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj )}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhj{ubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj{ubh)}(hPTrue if CDCLK changed in a way that requires re-programming and False otherwise.h]hPTrue if CDCLK changed in a way that requires re-programming and False otherwise.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(intel_cdclk_can_cd2x_update (C function)c.intel_cdclk_can_cd2x_updatehNtauh1jhhhhhNhNubj)}(hhh](j)}(hbool intel_cdclk_can_cd2x_update (struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j)}(hbool intel_cdclk_can_cd2x_update(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hjh]hbool}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUhhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubj)}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUhhhjfhM ubj)}(hintel_cdclk_can_cd2x_updateh]j)}(hintel_cdclk_can_cd2x_updateh]hintel_cdclk_can_cd2x_update}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubah}(h]h ](jjeh"]h$]h&]hhuh1jhjUhhhjfhM ubj)}(hg(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjmodnameN classnameNjAjD)}jG]jJ)}j=j{sbc.intel_cdclk_can_cd2x_updateasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(hjah]h*}(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h"const struct intel_cdclk_config *ah](j)}(hj7h]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hjh]hstruct}(hj" hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj/ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(hintel_cdclk_configh]hintel_cdclk_config}(hj@ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj= ubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjB modnameN classnameNjAjD)}jG]jc.intel_cdclk_can_cd2x_updateasbuh1hhj ubj)}(h h]h }(hj^ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(hjah]h*}(hjl hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]ha}(hjy hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h"const struct intel_cdclk_config *bh](j)}(hj7h]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(hintel_cdclk_configh]hintel_cdclk_config}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetj modnameN classnameNjAjD)}jG]jc.intel_cdclk_can_cd2x_updateasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(hjah]h*}(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hj7h]hb}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjUhhhjfhM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjQhhhjfhM ubah}(h]jLah ](jjeh"]h$]h&]jj)jhuh1jhjfhM hjNhhubj)}(hhh]h)}(h^Determine if changing between the two CDCLK configurations requires only a cd2x divider updateh]h^Determine if changing between the two CDCLK configurations requires only a cd2x divider update}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj) hhubah}(h]h ]h"]h$]h&]uh1jhjNhhhjfhM ubeh}(h]h ](j;functioneh"]h$]h&]jj;jjD jjD jjjuh1jhhhhhNhNubj)}(hXK**Parameters** ``struct intel_display *display`` display instance ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.h](h)}(h**Parameters**h]j)}(hjN h]h Parameters}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL ubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjH ubj)}(hhh](j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjm h]hstruct intel_display *display}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk ubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjg ubj )}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j hjg ubeh}(h]h ]h"]h$]h&]uh1jhj hM hjd ubj)}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hj h]h"const struct intel_cdclk_config *a}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj ubj )}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM hjd ubj)}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hj h]h"const struct intel_cdclk_config *b}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj ubj )}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM hjd ubeh}(h]h ]h"]h$]h&]uh1jhjH ubh)}(h **Return**h]j)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjH ubh)}(hpTrue if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.h]hpTrue if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjH ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j intel_cdclk_changed (C function)c.intel_cdclk_changedhNtauh1jhhhhhNhNubj)}(hhh](j)}(habool intel_cdclk_changed (const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j)}(h`bool intel_cdclk_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hjh]hbool}(hj_ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ hhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM* ubj)}(h h]h }(hjm hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ hhhjl hM* ubj)}(hintel_cdclk_changedh]j)}(hintel_cdclk_changedh]hintel_cdclk_changed}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj[ hhhjl hM* ubj)}(hH(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(h"const struct intel_cdclk_config *ah](j)}(hj7h]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(hintel_cdclk_configh]hintel_cdclk_config}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetj modnameN classnameNjAjD)}jG]jJ)}j=j sbc.intel_cdclk_changedasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(hjah]h*}(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hjh]ha}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubj)}(h"const struct intel_cdclk_config *bh](j)}(hj7h]hconst}(hj' hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj# ubj)}(h h]h }(hj4 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj# ubj)}(hjh]hstruct}(hjB hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj# ubj)}(h h]h }(hjO hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj# ubh)}(hhh]j)}(hintel_cdclk_configh]hintel_cdclk_config}(hj` hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj] ubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjb modnameN classnameNjAjD)}jG]j c.intel_cdclk_changedasbuh1hhj# ubj)}(h h]h }(hj~ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj# ubj^)}(hjah]h*}(hj hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj# ubj)}(hj7h]hb}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj# ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubeh}(h]h ]h"]h$]h&]hhuh1jhj[ hhhjl hM* ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjW hhhjl hM* ubah}(h]jR ah ](jjeh"]h$]h&]jj)jhuh1jhjl hM* hjT hhubj)}(hhh]h)}(h3Determine if two CDCLK configurations are differenth]h3Determine if two CDCLK configurations are different}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM* hj hhubah}(h]h ]h"]h$]h&]uh1jhjT hhhjl hM* ubeh}(h]h ](j;functioneh"]h$]h&]jj;jj jj jjjuh1jhhhhhNhNubj)}(h**Parameters** ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if the CDCLK configurations don't match, false if they do.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM. hj ubj)}(hhh](j)}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hj h]h"const struct intel_cdclk_config *a}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM+ hj ubj )}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM+ hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM+ hj ubj)}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hj< h]h"const struct intel_cdclk_config *b}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj: ubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM, hj6 ubj )}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQ hM, hjR ubah}(h]h ]h"]h$]h&]uh1j hj6 ubeh}(h]h ]h"]h$]h&]uh1jhjQ hM, hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubh)}(h **Return**h]j)}(hjw h]hReturn}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju ubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM. hj ubh)}(h?True if the CDCLK configurations don't match, false if they do.h]hATrue if the CDCLK configurations don’t match, false if they do.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM. hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j-intel_set_cdclk_pre_plane_update (C function)"c.intel_set_cdclk_pre_plane_updatehNtauh1jhhhhhNhNubj)}(hhh](j)}(hHvoid intel_set_cdclk_pre_plane_update (struct intel_atomic_state *state)h]j)}(hGvoid intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hM ubj)}(h intel_set_cdclk_pre_plane_updateh]j)}(h intel_set_cdclk_pre_plane_updateh]h intel_set_cdclk_pre_plane_update}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhj hM ubj)}(h"(struct intel_atomic_state *state)h]j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjmodnameN classnameNjAjD)}jG]jJ)}j=j sb"c.intel_set_cdclk_pre_plane_updateasbuh1hhj ubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj^)}(hjah]h*}(hjEhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hj ubj)}(hstateh]hstate}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubah}(h]h ]h"]h$]h&]hhuh1jhj hhhj hM ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj hhhj hM ubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hM hj hhubj)}(hhh]h)}(h$Push the CDCLK state to the hardwareh]h$Push the CDCLK state to the hardware}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjyhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hM ubeh}(h]h ](j;functioneh"]h$]h&]jj;jjjjjjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_atomic_state *state`` intel atomic state **Description** Program the hardware before updating the HW plane state based on the new CDCLK state, if necessary.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]j)}(h8``struct intel_atomic_state *state`` intel atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj )}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh)}(hcProgram the hardware before updating the HW plane state based on the new CDCLK state, if necessary.h]hcProgram the hardware before updating the HW plane state based on the new CDCLK state, if necessary.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.intel_set_cdclk_post_plane_update (C function)#c.intel_set_cdclk_post_plane_updatehNtauh1jhhhhhNhNubj)}(hhh](j)}(hIvoid intel_set_cdclk_post_plane_update (struct intel_atomic_state *state)h]j)}(hHvoid intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)h](j)}(hvoidh]hvoid}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9hhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM: ubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9hhhjKhM: ubj)}(h!intel_set_cdclk_post_plane_updateh]j)}(h!intel_set_cdclk_post_plane_updateh]h!intel_set_cdclk_post_plane_update}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubah}(h]h ](jjeh"]h$]h&]hhuh1jhj9hhhjKhM: ubj)}(h"(struct intel_atomic_state *state)h]j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubh)}(hhh]j)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjmodnameN classnameNjAjD)}jG]jJ)}j=j`sb#c.intel_set_cdclk_post_plane_updateasbuh1hhjvubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj^)}(hjah]h*}(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjvubj)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjrubah}(h]h ]h"]h$]h&]hhuh1jhj9hhhjKhM: ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj5hhhjKhM: ubah}(h]j0ah ](jjeh"]h$]h&]jj)jhuh1jhjKhM: hj2hhubj)}(hhh]h)}(h$Push the CDCLK state to the hardwareh]h$Push the CDCLK state to the hardware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM: hjhhubah}(h]h ]h"]h$]h&]uh1jhj2hhhjKhM: ubeh}(h]h ](j;functioneh"]h$]h&]jj;jjjjjjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_atomic_state *state`` intel atomic state **Description** Program the hardware after updating the HW plane state based on the new CDCLK state, if necessary.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM> hjubj)}(hhh]j)}(h8``struct intel_atomic_state *state`` intel atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hj>h]h struct intel_atomic_state *state}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM; hj8ubj )}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShM; hjTubah}(h]h ]h"]h$]h&]uh1j hj8ubeh}(h]h ]h"]h$]h&]uh1jhjShM; hj5ubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjyh]h Description}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM= hjubh)}(hbProgram the hardware after updating the HW plane state based on the new CDCLK state, if necessary.h]hbProgram the hardware after updating the HW plane state based on the new CDCLK state, if necessary.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM< hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#intel_update_max_cdclk (C function)c.intel_update_max_cdclkhNtauh1jhhhhhNhNubj)}(hhh](j)}(h;void intel_update_max_cdclk (struct intel_display *display)h]j)}(h:void intel_update_max_cdclk(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hintel_update_max_cdclkh]j)}(hintel_update_max_cdclkh]hintel_update_max_cdclk}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjmodnameN classnameNjAjD)}jG]jJ)}j=jsbc.intel_update_max_cdclkasbuh1hhjubj)}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj^)}(hjah]h*}(hjGhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hdisplayh]hdisplay}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h-Determine the maximum support CDCLK frequencyh]h-Determine the maximum support CDCLK frequency}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhj{hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j;functioneh"]h$]h&]jj;jjjjjjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Determine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhjubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhjubj )}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhjubh)}(hDetermine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.h]hDetermine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_update_cdclk (C function)c.intel_update_cdclkhNtauh1jhhhhhNhNubj)}(hhh](j)}(h7void intel_update_cdclk (struct intel_display *display)h]j)}(h6void intel_update_cdclk(struct intel_display *display)h](j)}(hvoidh]hvoid}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMubj)}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhjMhMubj)}(hintel_update_cdclkh]j)}(hintel_update_cdclkh]hintel_update_cdclk}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj;hhhjMhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubh)}(hhh]j)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj;reftypej= reftargetjmodnameN classnameNjAjD)}jG]jJ)}j=jbsbc.intel_update_cdclkasbuh1hhjxubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj^)}(hjah]h*}(hjhhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjxubj)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjtubah}(h]h ]h"]h$]h&]hhuh1jhj;hhhjMhMubeh}(h]h ]h"]h$]h&]hhjuh1jjjhj7hhhjMhMubah}(h]j2ah ](jjeh"]h$]h&]jj)jhuh1jhjMhMhj4hhubj)}(hhh]h)}(h%Determine the current CDCLK frequencyh]h%Determine the current CDCLK frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj4hhhjMhMubeh}(h]h ](j;functioneh"]h$]h&]jj;jjjjjjjuh1jhhhhhNhNubj)}(h}**Parameters** ``struct intel_display *display`` display instance **Description** Determine the current CDCLK frequency.h](h)}(h**Parameters**h]j)}(hj!h]h Parameters}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhjubj)}(hhh]j)}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj@h]hstruct intel_display *display}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhj:ubj )}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjVubah}(h]h ]h"]h$]h&]uh1j hj:ubeh}(h]h ]h"]h$]h&]uh1jhjUhMhj7ubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj{h]h Description}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhjubh)}(h&Determine the current CDCLK frequency.h]h&Determine the current CDCLK frequency.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.ce+hMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_read_rawclk (C function)c.intel_read_rawclkhNtauh1jhhhhhNhNubj)}(hhh](j)}(h5u32 intel_read_rawclk (struct intel_display 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]jah"]h$]h&]uh1jhjubj^)}(hjah]h*}(hj\hhhNhNubah}(h]h ]jjah"]h$]h&]uh1j]hjubj)}(hdisplayh]hdisplay}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM-ubeh}(h]h ]h"]h$]h&]hhjuh1jjjhjhhhjhM-ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM-hjhhubj)}(hhh]h)}(h&Determine the current RAWCLK frequencyh]h&Determine the current RAWCLK frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhr/var/lib/git/docbuild/linux/Documentation/gpu/intel-display/cdclk:10: ./drivers/gpu/drm/i915/display/intel_cdclk.chM-hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM-ubeh}(h]h ](j;functioneh"]h$]h&]jj;jjjjjjjuh1jhhhhhNhNubj)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Determine the current RAWCLK frequency. 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