Isphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/gpu/i915modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/pt_BR/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/gpu/i915modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhtarget)}(h .. _drm/i915:h]h}(h]h ]h"]h$]h&]refiddrm-i915uh1hhKhhhhh6/var/lib/git/docbuild/linux/Documentation/gpu/i915.rstubhsection)}(hhh](htitle)}(hdrm/i915 Intel GFX Driverh]hdrm/i915 Intel GFX Driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThe drm/i915 driver supports all (with the exception of some very early models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver.h]hXThe drm/i915 driver supports all (with the exception of some very early models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThe display, or :ref:`drm-kms`, support for drm/i915 is provided by :ref:`drm/intel-display`, and shared with :ref:`drm/xe `.h](hThe display, or }(hhhhhNhNubh)}(h:ref:`drm-kms`h]hinline)}(hhh]hdrm-kms}(hhhhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]refdocgpu/i915 refdomainjreftyperef refexplicitrefwarn reftargetdrm-kmsuh1hhhhK hhubh&, support for drm/i915 is provided by }(hhhhhNhNubh)}(h:ref:`drm/intel-display`h]h)}(hjh]hdrm/intel-display}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocj refdomainj(reftyperef refexplicitrefwarnjdrm/intel-displayuh1hhhhK hhubh, and shared with }(hhhhhNhNubh)}(h:ref:`drm/xe `h]h)}(hj@h]hdrm/xe}(hjBhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1hhj>ubah}(h]h ]h"]h$]h&]refdocj refdomainjLreftyperef refexplicitrefwarnjdrm/xeuh1hhhhK hhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hCore Driver Infrastructureh]hCore Driver Infrastructure}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhhKubh)}(hhThis section covers core driver infrastructure used by both the display and the GEM parts of the driver.h]hhThis section covers core driver infrastructure used by both the display and the GEM parts of the driver.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhhubh)}(hhh](h)}(hRuntime Power Managementh]hRuntime Power Management}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXrThe i915 driver supports dynamic enabling and disabling of entire hardware blocks at runtime. This is especially important on the display side where software is supposed to control many power gates manually on recent hardware, since on the GT side a lot of the power management is done by the hardware. But even there some manual control at the device level is required.h]hXrThe i915 driver supports dynamic enabling and disabling of entire hardware blocks at runtime. This is especially important on the display side where software is supposed to control many power gates manually on recent hardware, since on the GT side a lot of the power management is done by the hardware. But even there some manual control at the device level is required.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_runtime_pm.chK&hjhhubh)}(hXSince i915 supports a diverse set of platforms with a unified codebase and hardware engineers just love to shuffle functionality around between power domains there's a sizeable amount of indirection required. This file provides generic functions to the driver for grabbing and releasing references for abstract power domains. It then maps those to the actual power wells present for a given platform.h]hXSince i915 supports a diverse set of platforms with a unified codebase and hardware engineers just love to shuffle functionality around between power domains there’s a sizeable amount of indirection required. This file provides generic functions to the driver for grabbing and releasing references for abstract power domains. It then maps those to the actual power wells present for a given platform.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_runtime_pm.chK,hjhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single%intel_runtime_pm_get_raw (C function)c.intel_runtime_pm_get_rawhNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(hGintel_wakeref_t intel_runtime_pm_get_raw (struct intel_runtime_pm *rpm)h]hdesc_signature_line)}(hFintel_wakeref_t intel_runtime_pm_get_raw(struct intel_runtime_pm *rpm)h](h)}(hhh]h desc_sig_name)}(hintel_wakeref_th]hintel_wakeref_t}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jintel_runtime_pm_get_rawsbc.intel_runtime_pm_get_rawasbuh1hhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMubhdesc_sig_space)}(h h]h }(hj hhhNhNubah}(h]h ]wah"]h$]h&]uh1j hjhhhjhMubh desc_name)}(hintel_runtime_pm_get_rawh]j)}(hjh]hintel_runtime_pm_get_raw}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhMubhdesc_parameterlist)}(h(struct intel_runtime_pm *rpm)h]hdesc_parameter)}(hstruct intel_runtime_pm *rpmh](hdesc_sig_keyword)}(hstructh]hstruct}(hjEhhhNhNubah}(h]h ]kah"]h$]h&]uh1jChj?ubj )}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj?ubh)}(hhh]j)}(hintel_runtime_pmh]hintel_runtime_pm}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjgmodnameN classnameNjj)}j]jc.intel_runtime_pm_get_rawasbuh1hhj?ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj?ubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhj?ubj)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj9ubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6 add_permalinkuh1jsphinx_line_type declaratorhjhhhjhMubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhMhjhhubh desc_content)}(hhh]h)}(hgrab a raw runtime pm referenceh]hgrab a raw runtime pm reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhjhNhNubh container)}(hX**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This is the unlocked version of intel_display_power_is_enabled() and should only be used from error capture and recovery code where deadlocks are possible. This function grabs a device-level runtime pm reference (mostly used for asynchronous PM management from display code) and ensures that it is powered up. Raw references are not considered during wakelock assert checks. Any runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put_raw() to release the reference again. **Return** the wakeref cookie to pass to intel_runtime_pm_put_raw(), evaluates as True if the wakeref was acquired, or False otherwise.h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubhdefinition_list)}(hhh]hdefinition_list_item)}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](hterm)}(h ``struct intel_runtime_pm *rpm``h]hliteral)}(hj'h]hstruct intel_runtime_pm *rpm}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj%ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubh definition)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhjAubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj>hMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjfh]h Description}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubh)}(hXvThis is the unlocked version of intel_display_power_is_enabled() and should only be used from error capture and recovery code where deadlocks are possible. This function grabs a device-level runtime pm reference (mostly used for asynchronous PM management from display code) and ensures that it is powered up. Raw references are not considered during wakelock assert checks.h]hXvThis is the unlocked version of intel_display_power_is_enabled() and should only be used from error capture and recovery code where deadlocks are possible. This function grabs a device-level runtime pm reference (mostly used for asynchronous PM management from display code) and ensures that it is powered up. Raw references are not considered during wakelock assert checks.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put_raw() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put_raw() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM hjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubh)}(h|the wakeref cookie to pass to intel_runtime_pm_put_raw(), evaluates as True if the wakeref was acquired, or False otherwise.h]h|the wakeref cookie to pass to intel_runtime_pm_put_raw(), evaluates as True if the wakeref was acquired, or False otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!intel_runtime_pm_get (C function)c.intel_runtime_pm_gethNtauh1jhjhhhNhNubj)}(hhh](j)}(hCintel_wakeref_t intel_runtime_pm_get (struct intel_runtime_pm *rpm)h]j)}(hBintel_wakeref_t intel_runtime_pm_get(struct intel_runtime_pm *rpm)h](h)}(hhh]j)}(hintel_wakeref_th]hintel_wakeref_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jintel_runtime_pm_getsbc.intel_runtime_pm_getasbuh1hhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hintel_runtime_pm_geth]j)}(hjh]hintel_runtime_pm_get}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(h(struct intel_runtime_pm *rpm)h]j>)}(hstruct intel_runtime_pm *rpmh](jD)}(hjGh]hstruct}(hj3hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj/ubj )}(h h]h }(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/ubh)}(hhh]j)}(hintel_runtime_pmh]hintel_runtime_pm}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjSmodnameN classnameNjj)}j]jc.intel_runtime_pm_getasbuh1hhj/ubj )}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/ubj)}(hjh]h*}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj+ubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hgrab a runtime pm referenceh]hgrab a runtime pm reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up. Any runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again. **Return** the wakeref cookie to pass to intel_runtime_pm_put()h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubj)}(hhh]j)}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j$)}(h ``struct intel_runtime_pm *rpm``h]j*)}(hjh]hstruct intel_runtime_pm *rpm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubj@)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj0h]h Description}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubh)}(hThis function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up.h]hThis function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubh)}(h **Return**h]j)}(hjfh]hReturn}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM hjubh)}(h4the wakeref cookie to pass to intel_runtime_pm_put()h]h4the wakeref cookie to pass to intel_runtime_pm_put()}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM!hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j-__intel_runtime_pm_get_if_active (C function)"c.__intel_runtime_pm_get_if_activehNtauh1jhjhhhNhNubj)}(hhh](j)}(heintel_wakeref_t __intel_runtime_pm_get_if_active (struct intel_runtime_pm *rpm, bool ignore_usecount)h]j)}(hdintel_wakeref_t __intel_runtime_pm_get_if_active(struct intel_runtime_pm *rpm, bool ignore_usecount)h](h)}(hhh]j)}(hintel_wakeref_th]hintel_wakeref_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}j __intel_runtime_pm_get_if_activesb"c.__intel_runtime_pm_get_if_activeasbuh1hhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM)ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhM)ubj)}(h __intel_runtime_pm_get_if_activeh]j)}(hjh]h __intel_runtime_pm_get_if_active}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhM)ubj8)}(h4(struct intel_runtime_pm *rpm, bool ignore_usecount)h](j>)}(hstruct intel_runtime_pm *rpmh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hintel_runtime_pmh]hintel_runtime_pm}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j"c.__intel_runtime_pm_get_if_activeasbuh1hhjubj )}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hrpmh]hrpm}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hbool ignore_usecounth](hdesc_sig_keyword_type)}(hboolh]hbool}(hjohhhNhNubah}(h]h ]ktah"]h$]h&]uh1jmhjiubj )}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjiubj)}(hignore_usecounth]hignore_usecount}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhM)ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhM)ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM)hjhhubj)}(hhh]h)}(h/grab a runtime pm reference if device is activeh]h/grab a runtime pm reference if device is active}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM)hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM)ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX-**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``bool ignore_usecount`` get a ref even if dev->power.usage_count is 0 **Description** This function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure. If **ignore_usecount** is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it's guaranteed that the device's runtime suspend hook has been called already or that it will be called (and hence it's also guaranteed that the device's runtime resume hook will be called eventually). Any runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again. **Return** the wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM-hjubj)}(hhh](j)}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j$)}(h ``struct intel_runtime_pm *rpm``h]j*)}(hjh]hstruct intel_runtime_pm *rpm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM*hjubj@)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM*hj ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hM*hjubj)}(hG``bool ignore_usecount`` get a ref even if dev->power.usage_count is 0 h](j$)}(h``bool ignore_usecount``h]j*)}(hj0h]hbool ignore_usecount}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj.ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM+hj*ubj@)}(hhh]h)}(h-get a ref even if dev->power.usage_count is 0h]h-get a ref even if dev->power.usage_count is 0}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhM+hjFubah}(h]h ]h"]h$]h&]uh1j?hj*ubeh}(h]h ]h"]h$]h&]uh1jhjEhM+hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjkh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM-hjubh)}(hThis function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure.h]hThis function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM,hjubh)}(hXIf **ignore_usecount** is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it's guaranteed that the device's runtime suspend hook has been called already or that it will be called (and hence it's also guaranteed that the device's runtime resume hook will be called eventually).h](hIf }(hjhhhNhNubj)}(h**ignore_usecount**h]hignore_usecount}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it’s guaranteed that the device’s runtime suspend hook has been called already or that it will be called (and hence it’s also guaranteed that the device’s runtime resume hook will be called eventually).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM0hjubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM7hjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM:hjubh)}(hxthe wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.h]hxthe wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM;hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*intel_runtime_pm_get_noresume (C function)c.intel_runtime_pm_get_noresumehNtauh1jhjhhhNhNubj)}(hhh](j)}(hLintel_wakeref_t intel_runtime_pm_get_noresume (struct intel_runtime_pm *rpm)h]j)}(hKintel_wakeref_t intel_runtime_pm_get_noresume(struct intel_runtime_pm *rpm)h](h)}(hhh]j)}(hintel_wakeref_th]hintel_wakeref_t}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jintel_runtime_pm_get_noresumesbc.intel_runtime_pm_get_noresumeasbuh1hhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM_ubj )}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhj+hM_ubj)}(hintel_runtime_pm_get_noresumeh]j)}(hj(h]hintel_runtime_pm_get_noresume}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhj+hM_ubj8)}(h(struct intel_runtime_pm *rpm)h]j>)}(hstruct intel_runtime_pm *rpmh](jD)}(hjGh]hstruct}(hjYhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjUubj )}(h h]h }(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjUubh)}(hhh]j)}(hintel_runtime_pmh]hintel_runtime_pm}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjymodnameN classnameNjj)}j]j&c.intel_runtime_pm_get_noresumeasbuh1hhjUubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjUubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubj)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjQubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhj+hM_ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhj+hM_ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj+hM_hjhhubj)}(hhh]h)}(hgrab a runtime pm referenceh]hgrab a runtime pm reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM_hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj+hM_ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX@**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function grabs a device-level runtime pm reference. It will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold. Any runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again. **Return** the wakeref cookie to pass to intel_runtime_pm_put()h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMchjubj)}(hhh]j)}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j$)}(h ``struct intel_runtime_pm *rpm``h]j*)}(hj h]hstruct intel_runtime_pm *rpm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chM`hj ubj@)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0 hM`hj1 ubah}(h]h ]h"]h$]h&]uh1j?hj ubeh}(h]h ]h"]h$]h&]uh1jhj0 hM`hj ubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjV h]h Description}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMbhjubh)}(h8This function grabs a device-level runtime pm reference.h]h8This function grabs a device-level runtime pm reference.}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMahjubh)}(hIt will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold.h]hIt will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold.}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMchjubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMghjubh)}(h **Return**h]j)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMjhjubh)}(h4the wakeref cookie to pass to intel_runtime_pm_put()h]h4the wakeref cookie to pass to intel_runtime_pm_put()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMkhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%intel_runtime_pm_put_raw (C function)c.intel_runtime_pm_put_rawhNtauh1jhjhhhNhNubj)}(hhh](j)}(hRvoid intel_runtime_pm_put_raw (struct intel_runtime_pm *rpm, intel_wakeref_t wref)h]j)}(hQvoid intel_runtime_pm_put_raw(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](jn)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj hhhj hMubj)}(hintel_runtime_pm_put_rawh]j)}(hintel_runtime_pm_put_rawh]hintel_runtime_pm_put_raw}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj hhhj hMubj8)}(h4(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j>)}(hstruct intel_runtime_pm *rpmh](jD)}(hjGh]hstruct}(hj hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj ubj )}(h h]h }(hj* hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubh)}(hhh]j)}(hintel_runtime_pmh]hintel_runtime_pm}(hj; hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8 ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj= modnameN classnameNjj)}j]j)}jj sbc.intel_runtime_pm_put_rawasbuh1hhj ubj )}(h h]h }(hj[ hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj)}(hjh]h*}(hji hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hrpmh]hrpm}(hjv hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj ubj>)}(hintel_wakeref_t wrefh](h)}(hhh]j)}(hintel_wakeref_th]hintel_wakeref_t}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jW c.intel_runtime_pm_put_rawasbuh1hhj ubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj)}(hwrefh]hwref}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj hhhj hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj hhhj hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hMhj hhubj)}(hhh]h)}(h"release a raw runtime pm referenceh]h"release a raw runtime pm reference}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhjhNhNubj)}(hXz**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``intel_wakeref_t wref`` wakeref acquired for the reference that is being released **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj ubj)}(hhh](j)}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j$)}(h ``struct intel_runtime_pm *rpm``h]j*)}(hj) h]hstruct intel_runtime_pm *rpm}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj' ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj# ubj@)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj> hMhj? ubah}(h]h ]h"]h$]h&]uh1j?hj# ubeh}(h]h ]h"]h$]h&]uh1jhj> hMhj ubj)}(hS``intel_wakeref_t wref`` wakeref acquired for the reference that is being released h](j$)}(h``intel_wakeref_t wref``h]j*)}(hjb h]hintel_wakeref_t wref}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj` ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj\ ubj@)}(hhh]h)}(h9wakeref acquired for the reference that is being releasedh]h9wakeref acquired for the reference that is being released}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjw hMhjx ubah}(h]h ]h"]h$]h&]uh1j?hj\ ubeh}(h]h ]h"]h$]h&]uh1jhjw hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj ubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+intel_runtime_pm_put_unchecked (C function) c.intel_runtime_pm_put_uncheckedhNtauh1jhjhhhNhNubj)}(hhh](j)}(hBvoid intel_runtime_pm_put_unchecked (struct intel_runtime_pm *rpm)h]j)}(hAvoid intel_runtime_pm_put_unchecked(struct intel_runtime_pm *rpm)h](jn)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj hhhj hMubj)}(hintel_runtime_pm_put_uncheckedh]j)}(hintel_runtime_pm_put_uncheckedh]hintel_runtime_pm_put_unchecked}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj hhhj hMubj8)}(h(struct intel_runtime_pm *rpm)h]j>)}(hstruct intel_runtime_pm *rpmh](jD)}(hjGh]hstruct}(hj hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj ubj )}(h h]h }(hj, hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubh)}(hhh]j)}(hintel_runtime_pmh]hintel_runtime_pm}(hj= hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj: ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj? modnameN classnameNjj)}j]j)}jj sb c.intel_runtime_pm_put_uncheckedasbuh1hhj ubj )}(h h]h }(hj] hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj)}(hjh]h*}(hjk hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hrpmh]hrpm}(hjx hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj hhhj hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj hhhj hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hMhj hhubj)}(hhh]h)}(h)release an unchecked runtime pm referenceh]h)release an unchecked runtime pm reference}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference. This function exists only for historical reasons and should be avoided in new code, as the correctness of its use cannot be checked. Always use intel_runtime_pm_put() instead.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj ubj)}(hhh]j)}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j$)}(h ``struct intel_runtime_pm *rpm``h]j*)}(hj h]hstruct intel_runtime_pm *rpm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj ubj@)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j?hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj ubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj ubh)}(hThis function exists only for historical reasons and should be avoided in new code, as the correctness of its use cannot be checked. Always use intel_runtime_pm_put() instead.h]hThis function exists only for historical reasons and should be avoided in new code, as the correctness of its use cannot be checked. Always use intel_runtime_pm_put() instead.}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!intel_runtime_pm_put (C function)c.intel_runtime_pm_puthNtauh1jhjhhhNhNubj)}(hhh](j)}(hNvoid intel_runtime_pm_put (struct intel_runtime_pm *rpm, intel_wakeref_t wref)h]j)}(hMvoid intel_runtime_pm_put(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](jn)}(hvoidh]hvoid}(hjr hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjn hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjn hhhj hMubj)}(hintel_runtime_pm_puth]j)}(hintel_runtime_pm_puth]hintel_runtime_pm_put}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjn hhhj hMubj8)}(h4(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j>)}(hstruct intel_runtime_pm *rpmh](jD)}(hjGh]hstruct}(hj hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj ubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubh)}(hhh]j)}(hintel_runtime_pmh]hintel_runtime_pm}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jj sbc.intel_runtime_pm_putasbuh1hhj ubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj ubj>)}(hintel_wakeref_t wrefh](h)}(hhh]j)}(hintel_wakeref_th]hintel_wakeref_t}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj&modnameN classnameNjj)}j]j c.intel_runtime_pm_putasbuh1hhjubj )}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hwrefh]hwref}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjn hhhj hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjj hhhj hMubah}(h]je ah ](jjeh"]h$]h&]jj)jhuh1jhj hMhjg hhubj)}(hhh]h)}(hrelease a runtime pm referenceh]hrelease a runtime pm reference}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjwhhubah}(h]h ]h"]h$]h&]uh1jhjg hhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hXv**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``intel_wakeref_t wref`` wakeref acquired for the reference that is being released **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubj)}(hhh](j)}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j$)}(h ``struct intel_runtime_pm *rpm``h]j*)}(hjh]hstruct intel_runtime_pm *rpm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubj@)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hS``intel_wakeref_t wref`` wakeref acquired for the reference that is being released h](j$)}(h``intel_wakeref_t wref``h]j*)}(hjh]hintel_wakeref_t wref}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubj@)}(hhh]h)}(h9wakeref acquired for the reference that is being releasedh]h9wakeref acquired for the reference that is being released}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj/h]h Description}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$intel_runtime_pm_enable (C function)c.intel_runtime_pm_enablehNtauh1jhjhhhNhNubj)}(hhh](j)}(h;void intel_runtime_pm_enable (struct intel_runtime_pm *rpm)h]j)}(h:void intel_runtime_pm_enable(struct intel_runtime_pm *rpm)h](jn)}(hvoidh]hvoid}(hjthhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjphhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjphhhjhMubj)}(hintel_runtime_pm_enableh]j)}(hintel_runtime_pm_enableh]hintel_runtime_pm_enable}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjphhhjhMubj8)}(h(struct intel_runtime_pm *rpm)h]j>)}(hstruct intel_runtime_pm *rpmh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hintel_runtime_pmh]hintel_runtime_pm}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.intel_runtime_pm_enableasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hrpmh]hrpm}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hjphhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjlhhhjhMubah}(h]jgah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjihhubj)}(hhh]h)}(henable runtime pmh]henable runtime pm}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj1hhubah}(h]h ]h"]h$]h&]uh1jhjihhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjLjjLjjjuh1jhhhjhNhNubj)}(hXC**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function enables runtime pm at the end of the driver load sequence. Note that this function does currently not enable runtime pm for the subordinate display power domains. That is done by intel_display_power_enable().h](h)}(h**Parameters**h]j)}(hjVh]h Parameters}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjPubj)}(hhh]j)}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j$)}(h ``struct intel_runtime_pm *rpm``h]j*)}(hjuh]hstruct intel_runtime_pm *rpm}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjsubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjoubj@)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjoubeh}(h]h ]h"]h$]h&]uh1jhjhMhjlubah}(h]h ]h"]h$]h&]uh1jhjPubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjPubh)}(hHThis function enables runtime pm at the end of the driver load sequence.h]hHThis function enables runtime pm at the end of the driver load sequence.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjPubh)}(hNote that this function does currently not enable runtime pm for the subordinate display power domains. That is done by intel_display_power_enable().h]hNote that this function does currently not enable runtime pm for the subordinate display power domains. That is done by intel_display_power_enable().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:28: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjPubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'intel_uncore_forcewake_get (C function)c.intel_uncore_forcewake_gethNtauh1jhjhhhNhNubj)}(hhh](j)}(h`void intel_uncore_forcewake_get (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j)}(h_void intel_uncore_forcewake_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](jn)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hintel_uncore_forcewake_geth]j)}(hintel_uncore_forcewake_geth]hintel_uncore_forcewake_get}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hjAhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj=ubj )}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj=ubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjamodnameN classnameNjj)}j]j)}jj'sbc.intel_uncore_forcewake_getasbuh1hhj=ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj=ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubj)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj9ubj>)}(h!enum forcewake_domains fw_domainsh](jD)}(henumh]henum}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hforcewake_domainsh]hforcewake_domains}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j{c.intel_uncore_forcewake_getasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj9ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h grab forcewake domain referencesh]h grab forcewake domain references}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhj%hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj@jj@jjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to get reference on **Description** This function can be used get GT's forcewake domain references. Normal register access will handle the forcewake domains automatically. However if some sequence requires the GT to not power down a particular forcewake domains this function should be called at the beginning of the sequence. And subsequently the reference should be dropped by symmetric call to intel_unforce_forcewake_put(). Usually caller wants all the domains to be kept awake so the **fw_domains** would be then FORCEWAKE_ALL.h](h)}(h**Parameters**h]j)}(hjJh]h Parameters}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjDubj)}(hhh](j)}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hjih]hstruct intel_uncore *uncore}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjgubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjcubj@)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hMhjubah}(h]h ]h"]h$]h&]uh1j?hjcubeh}(h]h ]h"]h$]h&]uh1jhj~hMhj`ubj)}(hL``enum forcewake_domains fw_domains`` forcewake domains to get reference on h](j$)}(h%``enum forcewake_domains fw_domains``h]j*)}(hjh]h!enum forcewake_domains fw_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj@)}(hhh]h)}(h%forcewake domains to get reference onh]h%forcewake domains to get reference on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj`ubeh}(h]h ]h"]h$]h&]uh1jhjDubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjDubh)}(hXThis function can be used get GT's forcewake domain references. Normal register access will handle the forcewake domains automatically. However if some sequence requires the GT to not power down a particular forcewake domains this function should be called at the beginning of the sequence. And subsequently the reference should be dropped by symmetric call to intel_unforce_forcewake_put(). Usually caller wants all the domains to be kept awake so the **fw_domains** would be then FORCEWAKE_ALL.h](hXThis function can be used get GT’s forcewake domain references. Normal register access will handle the forcewake domains automatically. However if some sequence requires the GT to not power down a particular forcewake domains this function should be called at the beginning of the sequence. And subsequently the reference should be dropped by symmetric call to intel_unforce_forcewake_put(). Usually caller wants all the domains to be kept awake so the }(hjhhhNhNubj)}(h**fw_domains**h]h fw_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh would be then FORCEWAKE_ALL.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjDubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,intel_uncore_forcewake_user_get (C function)!c.intel_uncore_forcewake_user_gethNtauh1jhjhhhNhNubj)}(hhh](j)}(hBvoid intel_uncore_forcewake_user_get (struct intel_uncore *uncore)h]j)}(hAvoid intel_uncore_forcewake_user_get(struct intel_uncore *uncore)h](jn)}(hvoidh]hvoid}(hj4hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj0hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMubj )}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj0hhhjBhMubj)}(hintel_uncore_forcewake_user_geth]j)}(hintel_uncore_forcewake_user_geth]hintel_uncore_forcewake_user_get}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj0hhhjBhMubj8)}(h(struct intel_uncore *uncore)h]j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hjqhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjmubj )}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjmubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjWsb!c.intel_uncore_forcewake_user_getasbuh1hhjmubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjmubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjiubah}(h]h ]h"]h$]h&]j5j6uh1j7hj0hhhjBhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj,hhhjBhMubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1jhjBhMhj)hhubj)}(hhh]h)}(h&claim forcewake on behalf of userspaceh]h&claim forcewake on behalf of userspace}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj)hhhjBhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhjhNhNubj)}(hX **Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure **Description** This function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace's bypass.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]j)}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hj5h]hstruct intel_uncore *uncore}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj3ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhj/ubj@)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMhjKubah}(h]h ]h"]h$]h&]uh1j?hj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhMhj,ubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjph]h Description}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubh)}(hThis function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace's bypass.h]hThis function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace’s bypass.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,intel_uncore_forcewake_user_put (C function)!c.intel_uncore_forcewake_user_puthNtauh1jhjhhhNhNubj)}(hhh](j)}(hBvoid intel_uncore_forcewake_user_put (struct intel_uncore *uncore)h]j)}(hAvoid intel_uncore_forcewake_user_put(struct intel_uncore *uncore)h](jn)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hintel_uncore_forcewake_user_puth]j)}(hintel_uncore_forcewake_user_puth]hintel_uncore_forcewake_user_put}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(h(struct intel_uncore *uncore)h]j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb!c.intel_uncore_forcewake_user_putasbuh1hhjubj )}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(huncoreh]huncore}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h(release forcewake on behalf of userspaceh]h(release forcewake on behalf of userspace}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjrhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure **Description** This function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]j)}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj@)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubh)}(hThis function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.h]hThis function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/intel_uncore_forcewake_get__locked (C function)$c.intel_uncore_forcewake_get__lockedhNtauh1jhjhhhNhNubj)}(hhh](j)}(hhvoid intel_uncore_forcewake_get__locked (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j)}(hgvoid intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](jn)}(hvoidh]hvoid}(hj6hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj2hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMubj )}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2hhhjDhMubj)}(h"intel_uncore_forcewake_get__lockedh]j)}(h"intel_uncore_forcewake_get__lockedh]h"intel_uncore_forcewake_get__locked}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj2hhhjDhMubj8)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hjshhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjoubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjoubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjYsb$c.intel_uncore_forcewake_get__lockedasbuh1hhjoubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjoubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjkubj>)}(h!enum forcewake_domains fw_domainsh](jD)}(hjh]henum}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hforcewake_domainsh]hforcewake_domains}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j$c.intel_uncore_forcewake_get__lockedasbuh1hhjubj )}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(h fw_domainsh]h fw_domains}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjkubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj2hhhjDhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj.hhhjDhMubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1jhjDhMhj+hhubj)}(hhh]h)}(h grab forcewake domain referencesh]h grab forcewake domain references}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjVhhubah}(h]h ]h"]h$]h&]uh1jhj+hhhjDhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjqjjqjjjuh1jhhhjhNhNubj)}(hX3**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to get reference on **Description** See intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h](h)}(h**Parameters**h]j)}(hj{h]h Parameters}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjuubj)}(hhh](j)}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj@)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hL``enum forcewake_domains fw_domains`` forcewake domains to get reference on h](j$)}(h%``enum forcewake_domains fw_domains``h]j*)}(hjh]h!enum forcewake_domains fw_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj@)}(hhh]h)}(h%forcewake domains to get reference onh]h%forcewake domains to get reference on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjuubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjuubh)}(hSee intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h]hSee intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMhjuubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'intel_uncore_forcewake_put (C function)c.intel_uncore_forcewake_puthNtauh1jhjhhhNhNubj)}(hhh](j)}(h`void intel_uncore_forcewake_put (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j)}(h_void intel_uncore_forcewake_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](jn)}(hvoidh]hvoid}(hjShhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjOhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM$ubj )}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjOhhhjahM$ubj)}(hintel_uncore_forcewake_puth]j)}(hintel_uncore_forcewake_puth]hintel_uncore_forcewake_put}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjOhhhjahM$ubj8)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjvsbc.intel_uncore_forcewake_putasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(h!enum forcewake_domains fw_domainsh](jD)}(hjh]henum}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hforcewake_domainsh]hforcewake_domains}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj"modnameN classnameNjj)}j]jc.intel_uncore_forcewake_putasbuh1hhjubj )}(h h]h }(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(h fw_domainsh]h fw_domains}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjOhhhjahM$ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjKhhhjahM$ubah}(h]jFah ](jjeh"]h$]h&]jj)jhuh1jhjahM$hjHhhubj)}(hhh]h)}(h$release a forcewake domain referenceh]h$release a forcewake domain reference}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM$hjshhubah}(h]h ]h"]h$]h&]uh1jhjHhhhjahM$ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to put references **Description** This function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM(hjubj)}(hhh](j)}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM%hjubj@)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM%hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM%hjubj)}(hJ``enum forcewake_domains fw_domains`` forcewake domains to put references h](j$)}(h%``enum forcewake_domains fw_domains``h]j*)}(hjh]h!enum forcewake_domains fw_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM&hjubj@)}(hhh]h)}(h#forcewake domains to put referencesh]h#forcewake domains to put references}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM&hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM&hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj+h]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM(hjubh)}(hoThis function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().h]hoThis function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM'hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)intel_uncore_forcewake_flush (C function)c.intel_uncore_forcewake_flushhNtauh1jhjhhhNhNubj)}(hhh](j)}(hbvoid intel_uncore_forcewake_flush (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j)}(havoid intel_uncore_forcewake_flush(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](jn)}(hvoidh]hvoid}(hjphhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjlhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMFubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjlhhhj~hMFubj)}(hintel_uncore_forcewake_flushh]j)}(hintel_uncore_forcewake_flushh]hintel_uncore_forcewake_flush}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjlhhhj~hMFubj8)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.intel_uncore_forcewake_flushasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(h!enum forcewake_domains fw_domainsh](jD)}(hjh]henum}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hforcewake_domainsh]hforcewake_domains}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj?modnameN classnameNjj)}j]jc.intel_uncore_forcewake_flushasbuh1hhjubj )}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(h fw_domainsh]h fw_domains}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjlhhhj~hMFubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhhj~hMFubah}(h]jcah ](jjeh"]h$]h&]jj)jhuh1jhj~hMFhjehhubj)}(hhh]h)}(hflush the delayed releaseh]hflush the delayed release}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMFhjhhubah}(h]h ]h"]h$]h&]uh1jhjehhhj~hMFubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to flushh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMJhjubj)}(hhh](j)}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMGhjubj@)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMGhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMGhjubj)}(h@``enum forcewake_domains fw_domains`` forcewake domains to flushh](j$)}(h%``enum forcewake_domains fw_domains``h]j*)}(hj h]h!enum forcewake_domains fw_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMIhjubj@)}(hhh]h)}(hforcewake domains to flushh]hforcewake domains to flush}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMHhj#ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj"hMIhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/intel_uncore_forcewake_put__locked (C function)$c.intel_uncore_forcewake_put__lockedhNtauh1jhjhhhNhNubj)}(hhh](j)}(hhvoid intel_uncore_forcewake_put__locked (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j)}(hgvoid intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](jn)}(hvoidh]hvoid}(hjghhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjchhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM\ubj )}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjchhhjuhM\ubj)}(h"intel_uncore_forcewake_put__lockedh]j)}(h"intel_uncore_forcewake_put__lockedh]h"intel_uncore_forcewake_put__locked}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjchhhjuhM\ubj8)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb$c.intel_uncore_forcewake_put__lockedasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(h!enum forcewake_domains fw_domainsh](jD)}(hjh]henum}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hforcewake_domainsh]hforcewake_domains}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj6modnameN classnameNjj)}j]j$c.intel_uncore_forcewake_put__lockedasbuh1hhjubj )}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(h fw_domainsh]h fw_domains}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjchhhjuhM\ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj_hhhjuhM\ubah}(h]jZah ](jjeh"]h$]h&]jj)jhuh1jhjuhM\hj\hhubj)}(hhh]h)}(h#release forcewake domain referencesh]h#release forcewake domain references}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM\hjhhubah}(h]h ]h"]h$]h&]uh1jhj\hhhjuhM\ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX1**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to put references **Description** See intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM`hjubj)}(hhh](j)}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM]hjubj@)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM]hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM]hjubj)}(hJ``enum forcewake_domains fw_domains`` forcewake domains to put references h](j$)}(h%``enum forcewake_domains fw_domains``h]j*)}(hjh]h!enum forcewake_domains fw_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM^hjubj@)}(hhh]h)}(h#forcewake domains to put referencesh]h#forcewake domains to put references}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM^hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM^hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj?h]h Description}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM`hjubh)}(hSee intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h]hSee intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM_hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)__intel_wait_for_register_fw (C function)c.__intel_wait_for_register_fwhNtauh1jhjhhhNhNubj)}(hhh](j)}(hint __intel_wait_for_register_fw (struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h]j)}(hint __intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](jn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhM ubj)}(h__intel_wait_for_register_fwh]j)}(h__intel_wait_for_register_fwh]h__intel_wait_for_register_fw}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhM ubj8)}(h(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.__intel_wait_for_register_fwasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hi915_reg_t regh](h)}(hhh]j)}(h i915_reg_th]h i915_reg_t}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj8modnameN classnameNjj)}j]jc.__intel_wait_for_register_fwasbuh1hhj/ubj )}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/ubj)}(hregh]hreg}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hu32 maskh](h)}(hhh]j)}(hu32h]hu32}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.__intel_wait_for_register_fwasbuh1hhjwubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjwubj)}(hmaskh]hmask}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(h u32 valueh](h)}(hhh]j)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.__intel_wait_for_register_fwasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hvalueh]hvalue}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hunsigned int fast_timeout_ush](jn)}(hunsignedh]hunsigned}(hj hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj ubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubjn)}(hinth]hint}(hj' hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj ubj )}(h h]h }(hj5 hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj)}(hfast_timeout_ush]hfast_timeout_us}(hjC hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hunsigned int slow_timeout_msh](jn)}(hunsignedh]hunsigned}(hj\ hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjX ubj )}(h h]h }(hjj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjX ubjn)}(hinth]hint}(hjx hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjX ubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjX ubj)}(hslow_timeout_msh]hslow_timeout_ms}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hu32 *out_valueh](h)}(hhh]j)}(hu32h]hu32}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jc.__intel_wait_for_register_fwasbuh1hhj ubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h out_valueh]h out_value}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj|hhhjhM ubah}(h]jwah ](jjeh"]h$]h&]jj)jhuh1jhjhM hjyhhubj)}(hhh]h)}(h*wait until register matches expected stateh]h*wait until register matches expected state}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj!hhubah}(h]h ]h"]h$]h&]uh1jhjyhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj+!jj+!jjjuh1jhhhjhNhNubj)}(hXr**Parameters** ``struct intel_uncore *uncore`` the struct intel_uncore ``i915_reg_t reg`` the register to read ``u32 mask`` mask to apply to register value ``u32 value`` expected value ``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait ``unsigned int slow_timeout_ms`` slow timeout in millisecond ``u32 *out_value`` optional placeholder to hold registry value **Description** This routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until :: (intel_uncore_read_fw(uncore, reg) & mask) == value Otherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds. Note that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow). **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]j)}(hj5!h]h Parameters}(hj7!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3!ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj/!ubj)}(hhh](j)}(h8``struct intel_uncore *uncore`` the struct intel_uncore h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hjT!h]hstruct intel_uncore *uncore}(hjV!hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjR!ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hjN!ubj@)}(hhh]h)}(hthe struct intel_uncoreh]hthe struct intel_uncore}(hjm!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji!hM hjj!ubah}(h]h ]h"]h$]h&]uh1j?hjN!ubeh}(h]h ]h"]h$]h&]uh1jhji!hM hjK!ubj)}(h(``i915_reg_t reg`` the register to read h](j$)}(h``i915_reg_t reg``h]j*)}(hj!h]hi915_reg_t reg}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj@)}(hhh]h)}(hthe register to readh]hthe register to read}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1j?hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hM hjK!ubj)}(h-``u32 mask`` mask to apply to register value h](j$)}(h ``u32 mask``h]j*)}(hj!h]hu32 mask}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj@)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1j?hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hM hjK!ubj)}(h``u32 value`` expected value h](j$)}(h ``u32 value``h]j*)}(hj!h]h u32 value}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj@)}(hhh]h)}(hexpected valueh]hexpected value}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1j?hj!ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hjK!ubj)}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j$)}(h ``unsigned int fast_timeout_us``h]j*)}(hj8"h]hunsigned int fast_timeout_us}(hj:"hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj6"ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj2"ubj@)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hjQ"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM"hM hjN"ubah}(h]h ]h"]h$]h&]uh1j?hj2"ubeh}(h]h ]h"]h$]h&]uh1jhjM"hM hjK!ubj)}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j$)}(h ``unsigned int slow_timeout_ms``h]j*)}(hjq"h]hunsigned int slow_timeout_ms}(hjs"hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjo"ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hjk"ubj@)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1j?hjk"ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hjK!ubj)}(h?``u32 *out_value`` optional placeholder to hold registry value h](j$)}(h``u32 *out_value``h]j*)}(hj"h]hu32 *out_value}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj"ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj"ubj@)}(hhh]h)}(h+optional placeholder to hold registry valueh]h+optional placeholder to hold registry value}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1j?hj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hjK!ubeh}(h]h ]h"]h$]h&]uh1jhj/!ubh)}(h**Description**h]j)}(hj"h]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj/!ubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hj"hhhNhNubj)}(h**reg**h]hreg}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubh contains the expected }(hj"hhhNhNubj)}(h **value**h]hvalue}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubh after applying the }(hj"hhhNhNubj)}(h**mask**h]hmask}(hj'#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubh, i.e. it waits until}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj/!ubh literal_block)}(h3(intel_uncore_read_fw(uncore, reg) & mask) == valueh]h3(intel_uncore_read_fw(uncore, reg) & mask) == value}hjB#sbah}(h]h ]h"]h$]h&]j5j6uh1j@#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj/!ubh)}(hOtherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds.h](h'Otherwise, the wait will timeout after }(hjQ#hhhNhNubj)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hjY#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ#ubh" milliseconds. For atomic context }(hjQ#hhhNhNubj)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hjk#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ#ubh must be zero and }(hjQ#hhhNhNubj)}(h**fast_timeout_us**h]hfast_timeout_us}(hj}#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ#ubh. must be not larger than 20,0000 microseconds.}(hjQ#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj/!ubh)}(hNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow).h]hNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow).}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj/!ubh)}(h **Return**h]j)}(hj#h]hReturn}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj/!ubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj/!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&__intel_wait_for_register (C function)c.__intel_wait_for_registerhNtauh1jhjhhhNhNubj)}(hhh](j)}(hint __intel_wait_for_register (struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h]j)}(hint __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](jn)}(hinth]hint}(hj#hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj#hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM ubj )}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj#hhhj#hM ubj)}(h__intel_wait_for_registerh]j)}(h__intel_wait_for_registerh]h__intel_wait_for_register}(hj $hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj $ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj#hhhj#hM ubj8)}(h(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hj)$hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj%$ubj )}(h h]h }(hj6$hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj%$ubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hjG$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjD$ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjI$modnameN classnameNjj)}j]j)}jj$sbc.__intel_wait_for_registerasbuh1hhj%$ubj )}(h h]h }(hjg$hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj%$ubj)}(hjh]h*}(hju$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%$ubj)}(huncoreh]huncore}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%$ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj!$ubj>)}(hi915_reg_t regh](h)}(hhh]j)}(h i915_reg_th]h i915_reg_t}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj$modnameN classnameNjj)}j]jc$c.__intel_wait_for_registerasbuh1hhj$ubj )}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj$ubj)}(hregh]hreg}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj!$ubj>)}(hu32 maskh](h)}(hhh]j)}(hu32h]hu32}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj$modnameN classnameNjj)}j]jc$c.__intel_wait_for_registerasbuh1hhj$ubj )}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj$ubj)}(hmaskh]hmask}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj!$ubj>)}(h u32 valueh](h)}(hhh]j)}(hu32h]hu32}(hj.%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+%ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj0%modnameN classnameNjj)}j]jc$c.__intel_wait_for_registerasbuh1hhj'%ubj )}(h h]h }(hjL%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj'%ubj)}(hvalueh]hvalue}(hjZ%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'%ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj!$ubj>)}(hunsigned int fast_timeout_ush](jn)}(hunsignedh]hunsigned}(hjs%hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjo%ubj )}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjo%ubjn)}(hinth]hint}(hj%hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjo%ubj )}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjo%ubj)}(hfast_timeout_ush]hfast_timeout_us}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjo%ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj!$ubj>)}(hunsigned int slow_timeout_msh](jn)}(hunsignedh]hunsigned}(hj%hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj%ubj )}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj%ubjn)}(hinth]hint}(hj%hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj%ubj )}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj%ubj)}(hslow_timeout_msh]hslow_timeout_ms}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj!$ubj>)}(hu32 *out_valueh](h)}(hhh]j)}(hu32h]hu32}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj&modnameN classnameNjj)}j]jc$c.__intel_wait_for_registerasbuh1hhj&ubj )}(h h]h }(hj6&hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj&ubj)}(hjh]h*}(hjD&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(h out_valueh]h out_value}(hjQ&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj!$ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj#hhhj#hM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj#hhhj#hM ubah}(h]j#ah ](jjeh"]h$]h&]jj)jhuh1jhj#hM hj#hhubj)}(hhh]h)}(h*wait until register matches expected stateh]h*wait until register matches expected state}(hj{&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hjx&hhubah}(h]h ]h"]h$]h&]uh1jhj#hhhj#hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj&jj&jjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct intel_uncore *uncore`` the struct intel_uncore ``i915_reg_t reg`` the register to read ``u32 mask`` mask to apply to register value ``u32 value`` expected value ``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait ``unsigned int slow_timeout_ms`` slow timeout in millisecond ``u32 *out_value`` optional placeholder to hold registry value **Description** This routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until :: (intel_uncore_read(uncore, reg) & mask) == value Otherwise, the wait will timeout after **timeout_ms** milliseconds. **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]j)}(hj&h]h Parameters}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh](j)}(h8``struct intel_uncore *uncore`` the struct intel_uncore h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hj&h]hstruct intel_uncore *uncore}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj&ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj@)}(hhh]h)}(hthe struct intel_uncoreh]hthe struct intel_uncore}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hM hj&ubah}(h]h ]h"]h$]h&]uh1j?hj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hM hj&ubj)}(h(``i915_reg_t reg`` the register to read h](j$)}(h``i915_reg_t reg``h]j*)}(hj&h]hi915_reg_t reg}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj&ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj@)}(hhh]h)}(hthe register to readh]hthe register to read}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 'hM hj 'ubah}(h]h ]h"]h$]h&]uh1j?hj&ubeh}(h]h ]h"]h$]h&]uh1jhj 'hM hj&ubj)}(h-``u32 mask`` mask to apply to register value h](j$)}(h ``u32 mask``h]j*)}(hj.'h]hu32 mask}(hj0'hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj,'ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj('ubj@)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hjG'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC'hM hjD'ubah}(h]h ]h"]h$]h&]uh1j?hj('ubeh}(h]h ]h"]h$]h&]uh1jhjC'hM hj&ubj)}(h``u32 value`` expected value h](j$)}(h ``u32 value``h]j*)}(hjg'h]h u32 value}(hji'hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hje'ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hja'ubj@)}(hhh]h)}(hexpected valueh]hexpected value}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|'hM hj}'ubah}(h]h ]h"]h$]h&]uh1j?hja'ubeh}(h]h ]h"]h$]h&]uh1jhj|'hM hj&ubj)}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j$)}(h ``unsigned int fast_timeout_us``h]j*)}(hj'h]hunsigned int fast_timeout_us}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj'ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj'ubj@)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM hj'ubah}(h]h ]h"]h$]h&]uh1j?hj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hM hj&ubj)}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j$)}(h ``unsigned int slow_timeout_ms``h]j*)}(hj'h]hunsigned int slow_timeout_ms}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj'ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj'ubj@)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM hj'ubah}(h]h ]h"]h$]h&]uh1j?hj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hM hj&ubj)}(h?``u32 *out_value`` optional placeholder to hold registry value h](j$)}(h``u32 *out_value``h]j*)}(hj(h]hu32 *out_value}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj(ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj (ubj@)}(hhh]h)}(h+optional placeholder to hold registry valueh]h+optional placeholder to hold registry value}(hj+(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'(hM hj((ubah}(h]h ]h"]h$]h&]uh1j?hj (ubeh}(h]h ]h"]h$]h&]uh1jhj'(hM hj&ubeh}(h]h ]h"]h$]h&]uh1jhj&ubh)}(h**Description**h]j)}(hjM(h]h Description}(hjO(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK(ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hjc(hhhNhNubj)}(h**reg**h]hreg}(hjk(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc(ubh contains the expected }(hjc(hhhNhNubj)}(h **value**h]hvalue}(hj}(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc(ubh after applying the }(hjc(hhhNhNubj)}(h**mask**h]hmask}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc(ubh, i.e. it waits until}(hjc(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubjA#)}(h0(intel_uncore_read(uncore, reg) & mask) == valueh]h0(intel_uncore_read(uncore, reg) & mask) == value}hj(sbah}(h]h ]h"]h$]h&]j5j6uh1j@#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubh)}(hCOtherwise, the wait will timeout after **timeout_ms** milliseconds.h](h'Otherwise, the wait will timeout after }(hj(hhhNhNubj)}(h**timeout_ms**h]h timeout_ms}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubh milliseconds.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubh)}(h **Return**h]j)}(hj(h]hReturn}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+intel_uncore_forcewake_for_reg (C function) c.intel_uncore_forcewake_for_reghNtauh1jhjhhhNhNubj)}(hhh](j)}(htenum forcewake_domains intel_uncore_forcewake_for_reg (struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h]j)}(hsenum forcewake_domains intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h](jD)}(hjh]henum}(hj)hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj)hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMJ ubj )}(h h]h }(hj-)hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj)hhhj,)hMJ ubh)}(hhh]j)}(hforcewake_domainsh]hforcewake_domains}(hj>)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;)ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj@)modnameN classnameNjj)}j]j)}jintel_uncore_forcewake_for_regsb c.intel_uncore_forcewake_for_regasbuh1hhj)hhhj,)hMJ ubj )}(h h]h }(hj_)hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj)hhhj,)hMJ ubj)}(hintel_uncore_forcewake_for_regh]j)}(hj\)h]hintel_uncore_forcewake_for_reg}(hjq)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm)ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj)hhhj,)hMJ ubj8)}(h>(struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h](j>)}(hstruct intel_uncore *uncoreh](jD)}(hjGh]hstruct}(hj)hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj)ubj )}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj)ubh)}(hhh]j)}(h intel_uncoreh]h intel_uncore}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj)modnameN classnameNjj)}j]jZ) c.intel_uncore_forcewake_for_regasbuh1hhj)ubj )}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj)ubj)}(hjh]h*}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj)}(huncoreh]huncore}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj)ubj>)}(hi915_reg_t regh](h)}(hhh]j)}(h i915_reg_th]h i915_reg_t}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj*modnameN classnameNjj)}j]jZ) c.intel_uncore_forcewake_for_regasbuh1hhj)ubj )}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj)ubj)}(hregh]hreg}(hj+*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj)ubj>)}(hunsigned int oph](jn)}(hunsignedh]hunsigned}(hjD*hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj@*ubj )}(h h]h }(hjR*hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj@*ubjn)}(hinth]hint}(hj`*hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj@*ubj )}(h h]h }(hjn*hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj@*ubj)}(hoph]hop}(hj|*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@*ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj)ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj)hhhj,)hMJ ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj)hhhj,)hMJ ubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1jhj,)hMJ hj)hhubj)}(hhh]h)}(h7which forcewake domains are needed to access a registerh]h7which forcewake domains are needed to access a register}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMJ hj*hhubah}(h]h ]h"]h$]h&]uh1jhj)hhhj,)hMJ ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj*jj*jjjuh1jhhhjhNhNubj)}(hXI**Parameters** ``struct intel_uncore *uncore`` pointer to struct intel_uncore ``i915_reg_t reg`` register in question ``unsigned int op`` operation bitmask of FW_REG_READ and/or FW_REG_WRITE **Description** Returns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors. **NOTE** On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.h](h)}(h**Parameters**h]j)}(hj*h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMN hj*ubj)}(hhh](j)}(h?``struct intel_uncore *uncore`` pointer to struct intel_uncore h](j$)}(h``struct intel_uncore *uncore``h]j*)}(hj*h]hstruct intel_uncore *uncore}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj*ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chML hj*ubj@)}(hhh]h)}(hpointer to struct intel_uncoreh]hpointer to struct intel_uncore}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hML hj*ubah}(h]h ]h"]h$]h&]uh1j?hj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hML hj*ubj)}(h(``i915_reg_t reg`` register in question h](j$)}(h``i915_reg_t reg``h]j*)}(hj +h]hi915_reg_t reg}(hj"+hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj+ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMM hj+ubj@)}(hhh]h)}(hregister in questionh]hregister in question}(hj9+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5+hMM hj6+ubah}(h]h ]h"]h$]h&]uh1j?hj+ubeh}(h]h ]h"]h$]h&]uh1jhj5+hMM hj*ubj)}(hI``unsigned int op`` operation bitmask of FW_REG_READ and/or FW_REG_WRITE h](j$)}(h``unsigned int op``h]j*)}(hjY+h]hunsigned int op}(hj[+hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjW+ubah}(h]h ]h"]h$]h&]uh1j#h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMN hjS+ubj@)}(hhh]h)}(h4operation bitmask of FW_REG_READ and/or FW_REG_WRITEh]h4operation bitmask of FW_REG_READ and/or FW_REG_WRITE}(hjr+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn+hMN hjo+ubah}(h]h ]h"]h$]h&]uh1j?hjS+ubeh}(h]h ]h"]h$]h&]uh1jhjn+hMN hj*ubeh}(h]h ]h"]h$]h&]uh1jhj*ubh)}(h**Description**h]j)}(hj+h]h Description}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMP hj*ubh)}(hReturns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors.h]hReturns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMO hj*ubh)}(h**NOTE**h]j)}(hj+h]hNOTE}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMS hj*ubh)}(hOn Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.h]hOn Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/intel_uncore.chMT hj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h]runtime-power-managementah ]h"]runtime power managementah$]h&]uh1hhjhhhhhhKubh)}(hhh](h)}(hInterrupt Handlingh]hInterrupt Handling}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhK#ubh)}(hThese functions provide the basic support for enabling and disabling the interrupt handling support. There's a lot more functionality in i915_irq.c and related files, but that will be described in separate chapters.h]hThese functions provide the basic support for enabling and disabling the interrupt handling support. There’s a lot more functionality in i915_irq.c and related files, but that will be described in separate chapters.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chK6hj+hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_irq_init (C function)c.intel_irq_inithNtauh1jhj+hhhNhNubj)}(hhh](j)}(h7void intel_irq_init (struct drm_i915_private *dev_priv)h]j)}(h6void intel_irq_init(struct drm_i915_private *dev_priv)h](jn)}(hvoidh]hvoid}(hj(,hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj$,hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMubj )}(h h]h }(hj7,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj$,hhhj6,hMubj)}(hintel_irq_inith]j)}(hintel_irq_inith]hintel_irq_init}(hjI,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjE,ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj$,hhhj6,hMubj8)}(h#(struct drm_i915_private *dev_priv)h]j>)}(h!struct drm_i915_private *dev_privh](jD)}(hjGh]hstruct}(hje,hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChja,ubj )}(h h]h }(hjr,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hja,ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj,modnameN classnameNjj)}j]j)}jjK,sbc.intel_irq_initasbuh1hhja,ubj )}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hja,ubj)}(hjh]h*}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhja,ubj)}(hdev_privh]hdev_priv}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhja,ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj],ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj$,hhhj6,hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj ,hhhj6,hMubah}(h]j,ah ](jjeh"]h$]h&]jj)jhuh1jhj6,hMhj,hhubj)}(hhh]h)}(hinitializes irq supporth]hinitializes irq support}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhj,hhubah}(h]h ]h"]h$]h&]uh1jhj,hhhj6,hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj-jj-jjjuh1jhhhj+hNhNubj)}(h**Parameters** ``struct drm_i915_private *dev_priv`` i915 device instance **Description** This function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.h](h)}(h**Parameters**h]j)}(hj -h]h Parameters}(hj -hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubj)}(hhh]j)}(h;``struct drm_i915_private *dev_priv`` i915 device instance h](j$)}(h%``struct drm_i915_private *dev_priv``h]j*)}(hj)-h]h!struct drm_i915_private *dev_priv}(hj+-hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj'-ubah}(h]h ]h"]h$]h&]uh1j#hX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhj#-ubj@)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hjB-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>-hMhj?-ubah}(h]h ]h"]h$]h&]uh1j?hj#-ubeh}(h]h ]h"]h$]h&]uh1jhj>-hMhj -ubah}(h]h ]h"]h$]h&]uh1jhj-ubh)}(h**Description**h]j)}(hjd-h]h Description}(hjf-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb-ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubh)}(hThis function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.h]hThis function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.}(hjz-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_irq_suspend (C function)c.intel_irq_suspendhNtauh1jhj+hhhNhNubj)}(hhh](j)}(h6void intel_irq_suspend (struct drm_i915_private *i915)h]j)}(h5void intel_irq_suspend(struct drm_i915_private *i915)h](jn)}(hvoidh]hvoid}(hj-hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj-hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:43: ./drivers/gpu/drm/i915/i915_irq.chMubj )}(h h]h }(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj-hhhj-hMubj)}(hintel_irq_suspendh]j)}(hintel_irq_suspendh]hintel_irq_suspend}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj-hhhj-hMubj8)}(h(struct drm_i915_private *i915)h]j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hj-hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj-ubj )}(h h]h }(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj-ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj.modnameN classnameNjj)}j]j)}jj-sbc.intel_irq_suspendasbuh1hhj-ubj )}(h h]h }(hj$.hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj-ubj)}(hjh]h*}(hj2.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hi915h]hi915}(hj?.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj-ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj-hhhj-hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj-hhhj-hMubah}(h]j-ah ](jjeh"]h$]h&]jj)jhuh1jhj-hMhj-hhubj)}(hhh]h)}(hSuspend interruptsh]hSuspend interrupts}(hji.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:43: ./drivers/gpu/drm/i915/i915_irq.chMhjf.hhubah}(h]h ]h"]h$]h&]uh1jhj-hhhj-hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj.jj.jjjuh1jhhhj+hNhNubj)}(h**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** This function is used to disable interrupts at runtime.h](h)}(h**Parameters**h]j)}(hj.h]h Parameters}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:43: ./drivers/gpu/drm/i915/i915_irq.chMhj.ubj)}(hhh]j)}(h7``struct drm_i915_private *i915`` i915 device instance h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hj.h]hstruct drm_i915_private *i915}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj.ubah}(h]h ]h"]h$]h&]uh1j#hX/var/lib/git/docbuild/linux/Documentation/gpu/i915:43: ./drivers/gpu/drm/i915/i915_irq.chMhj.ubj@)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj.ubah}(h]h ]h"]h$]h&]uh1j?hj.ubeh}(h]h ]h"]h$]h&]uh1jhj.hMhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubh)}(h**Description**h]j)}(hj.h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:43: ./drivers/gpu/drm/i915/i915_irq.chMhj.ubh)}(h7This function is used to disable interrupts at runtime.h]h7This function is used to disable interrupts at runtime.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:43: ./drivers/gpu/drm/i915/i915_irq.chMhj.ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_irq_resume (C function)c.intel_irq_resumehNtauh1jhj+hhhNhNubj)}(hhh](j)}(h5void intel_irq_resume (struct drm_i915_private *i915)h]j)}(h4void intel_irq_resume(struct drm_i915_private *i915)h](jn)}(hvoidh]hvoid}(hj*/hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj&/hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:46: ./drivers/gpu/drm/i915/i915_irq.chMubj )}(h h]h }(hj9/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj&/hhhj8/hMubj)}(hintel_irq_resumeh]j)}(hintel_irq_resumeh]hintel_irq_resume}(hjK/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG/ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj&/hhhj8/hMubj8)}(h(struct drm_i915_private *i915)h]j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hjg/hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjc/ubj )}(h h]h }(hjt/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjc/ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj/modnameN classnameNjj)}j]j)}jjM/sbc.intel_irq_resumeasbuh1hhjc/ubj )}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjc/ubj)}(hjh]h*}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc/ubj)}(hi915h]hi915}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc/ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj_/ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj&/hhhj8/hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj"/hhhj8/hMubah}(h]j/ah ](jjeh"]h$]h&]jj)jhuh1jhj8/hMhj/hhubj)}(hhh]h)}(hResume interruptsh]hResume interrupts}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:46: ./drivers/gpu/drm/i915/i915_irq.chMhj/hhubah}(h]h ]h"]h$]h&]uh1jhj/hhhj8/hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj0jj0jjjuh1jhhhj+hNhNubj)}(h**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** This function is used to enable interrupts at runtime.h](h)}(h**Parameters**h]j)}(hj 0h]h Parameters}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 0ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:46: ./drivers/gpu/drm/i915/i915_irq.chMhj0ubj)}(hhh]j)}(h7``struct drm_i915_private *i915`` i915 device instance h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hj+0h]hstruct drm_i915_private *i915}(hj-0hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj)0ubah}(h]h ]h"]h$]h&]uh1j#hX/var/lib/git/docbuild/linux/Documentation/gpu/i915:46: ./drivers/gpu/drm/i915/i915_irq.chMhj%0ubj@)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hjD0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@0hMhjA0ubah}(h]h ]h"]h$]h&]uh1j?hj%0ubeh}(h]h ]h"]h$]h&]uh1jhj@0hMhj"0ubah}(h]h ]h"]h$]h&]uh1jhj0ubh)}(h**Description**h]j)}(hjf0h]h Description}(hjh0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjd0ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:46: ./drivers/gpu/drm/i915/i915_irq.chMhj0ubh)}(h6This function is used to enable interrupts at runtime.h]h6This function is used to enable interrupts at runtime.}(hj|0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:46: ./drivers/gpu/drm/i915/i915_irq.chMhj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj+hhhNhNubeh}(h]interrupt-handlingah ]h"]interrupt handlingah$]h&]uh1hhjhhhhhhK#ubh)}(hhh](h)}(hIntel GVT-g Guest Support(vGPU)h]hIntel GVT-g Guest Support(vGPU)}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhhhK2ubh)}(hXIntel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine. This file provides vGPU specific optimizations when running in a virtual machine, to reduce the complexity of vGPU emulation and to improve the overall performance.h]hXIntel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine. This file provides vGPU specific optimizations when running in a virtual machine, to reduce the complexity of vGPU emulation and to improve the overall performance.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:52: ./drivers/gpu/drm/i915/i915_vgpu.chKhj0hhubh)}(hXA primary function introduced here is so-called "address space ballooning" technique. Intel GVT-g partitions global graphics memory among multiple VMs, so each VM can directly access a portion of the memory without hypervisor's intervention, e.g. filling textures or queuing commands. However with the partitioning an unmodified i915 driver would assume a smaller graphics memory starting from address ZERO, then requires vGPU emulation module to translate the graphics address between 'guest view' and 'host view', for all registers and command opcodes which contain a graphics memory address. To reduce the complexity, Intel GVT-g introduces "address space ballooning", by telling the exact partitioning knowledge to each guest i915 driver, which then reserves and prevents non-allocated portions from allocation. Thus vGPU emulation module only needs to scan and validate graphics addresses without complexity of address translation.h]hXA primary function introduced here is so-called “address space ballooning” technique. Intel GVT-g partitions global graphics memory among multiple VMs, so each VM can directly access a portion of the memory without hypervisor’s intervention, e.g. filling textures or queuing commands. However with the partitioning an unmodified i915 driver would assume a smaller graphics memory starting from address ZERO, then requires vGPU emulation module to translate the graphics address between ‘guest view’ and ‘host view’, for all registers and command opcodes which contain a graphics memory address. To reduce the complexity, Intel GVT-g introduces “address space ballooning”, by telling the exact partitioning knowledge to each guest i915 driver, which then reserves and prevents non-allocated portions from allocation. Thus vGPU emulation module only needs to scan and validate graphics addresses without complexity of address translation.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:52: ./drivers/gpu/drm/i915/i915_vgpu.chK'hj0hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_vgpu_detect (C function)c.intel_vgpu_detecthNtauh1jhj0hhhNhNubj)}(hhh](j)}(h:void intel_vgpu_detect (struct drm_i915_private *dev_priv)h]j)}(h9void intel_vgpu_detect(struct drm_i915_private *dev_priv)h](jn)}(hvoidh]hvoid}(hj0hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj0hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chK:ubj )}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj0hhhj0hK:ubj)}(hintel_vgpu_detecth]j)}(hintel_vgpu_detecth]hintel_vgpu_detect}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj0hhhj0hK:ubj8)}(h#(struct drm_i915_private *dev_priv)h]j>)}(h!struct drm_i915_private *dev_privh](jD)}(hjGh]hstruct}(hj1hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj1ubj )}(h h]h }(hj,1hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj1ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj=1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:1ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj?1modnameN classnameNjj)}j]j)}jj1sbc.intel_vgpu_detectasbuh1hhj1ubj )}(h h]h }(hj]1hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj1ubj)}(hjh]h*}(hjk1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj)}(hdev_privh]hdev_priv}(hjx1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj1ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj0hhhj0hK:ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj0hhhj0hK:ubah}(h]j0ah ](jjeh"]h$]h&]jj)jhuh1jhj0hK:hj0hhubj)}(hhh]h)}(hdetect virtual GPUh]hdetect virtual GPU}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chK:hj1hhubah}(h]h ]h"]h$]h&]uh1jhj0hhhj0hK:ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj1jj1jjjuh1jhhhj0hNhNubj)}(h**Parameters** ``struct drm_i915_private *dev_priv`` i915 device private **Description** This function is called at the initialization stage, to detect whether running on a vGPU.h](h)}(h**Parameters**h]j)}(hj1h]h Parameters}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chK>hj1ubj)}(hhh]j)}(h:``struct drm_i915_private *dev_priv`` i915 device private h](j$)}(h%``struct drm_i915_private *dev_priv``h]j*)}(hj1h]h!struct drm_i915_private *dev_priv}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj1ubah}(h]h ]h"]h$]h&]uh1j#hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chK;hj1ubj@)}(hhh]h)}(hi915 device privateh]hi915 device private}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hK;hj1ubah}(h]h ]h"]h$]h&]uh1j?hj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hK;hj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubh)}(h**Description**h]j)}(hj2h]h Description}(hj 2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chK=hj1ubh)}(hYThis function is called at the initialization stage, to detect whether running on a vGPU.h]hYThis function is called at the initialization stage, to detect whether running on a vGPU.}(hj42hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chK)}(hstruct i915_ggtt *ggtth](jD)}(hjGh]hstruct}(hj2hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj2ubj )}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2ubh)}(hhh]j)}(h i915_ggtth]h i915_ggtt}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj2modnameN classnameNjj)}j]j)}jj2sbc.intel_vgt_deballoonasbuh1hhj2ubj )}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2ubj)}(hjh]h*}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(hggtth]hggtt}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj2ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj_2hhhjq2hKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj[2hhhjq2hKubah}(h]jV2ah ](jjeh"]h$]h&]jj)jhuh1jhjq2hKhjX2hhubj)}(hhh]h)}(h*deballoon reserved graphics address trunksh]h*deballoon reserved graphics address trunks}(hj#3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj 3hhubah}(h]h ]h"]h$]h&]uh1jhjX2hhhjq2hKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj;3jj;3jjjuh1jhhhj0hNhNubj)}(h**Parameters** ``struct i915_ggtt *ggtt`` the global GGTT from which we reserved earlier **Description** This function is called to deallocate the ballooned-out graphic memory, when driver is unloaded or when ballooning fails.h](h)}(h**Parameters**h]j)}(hjE3h]h Parameters}(hjG3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC3ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj?3ubj)}(hhh]j)}(hJ``struct i915_ggtt *ggtt`` the global GGTT from which we reserved earlier h](j$)}(h``struct i915_ggtt *ggtt``h]j*)}(hjd3h]hstruct i915_ggtt *ggtt}(hjf3hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjb3ubah}(h]h ]h"]h$]h&]uh1j#hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj^3ubj@)}(hhh]h)}(h.the global GGTT from which we reserved earlierh]h.the global GGTT from which we reserved earlier}(hj}3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjy3hKhjz3ubah}(h]h ]h"]h$]h&]uh1j?hj^3ubeh}(h]h ]h"]h$]h&]uh1jhjy3hKhj[3ubah}(h]h ]h"]h$]h&]uh1jhj?3ubh)}(h**Description**h]j)}(hj3h]h Description}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj?3ubh)}(hyThis function is called to deallocate the ballooned-out graphic memory, when driver is unloaded or when ballooning fails.h]hyThis function is called to deallocate the ballooned-out graphic memory, when driver is unloaded or when ballooning fails.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj?3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj0hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_vgt_balloon (C function)c.intel_vgt_balloonhNtauh1jhj0hhhNhNubj)}(hhh](j)}(h.int intel_vgt_balloon (struct i915_ggtt *ggtt)h]j)}(h-int intel_vgt_balloon(struct i915_ggtt *ggtt)h](jn)}(hinth]hint}(hj3hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj3hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKubj )}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj3hhhj3hKubj)}(hintel_vgt_balloonh]j)}(hintel_vgt_balloonh]hintel_vgt_balloon}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj3hhhj3hKubj8)}(h(struct i915_ggtt *ggtt)h]j>)}(hstruct i915_ggtt *ggtth](jD)}(hjGh]hstruct}(hj!4hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj4ubj )}(h h]h }(hj.4hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj4ubh)}(hhh]j)}(h i915_ggtth]h i915_ggtt}(hj?4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<4ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjA4modnameN classnameNjj)}j]j)}jj4sbc.intel_vgt_balloonasbuh1hhj4ubj )}(h h]h }(hj_4hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj4ubj)}(hjh]h*}(hjm4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj)}(hggtth]hggtt}(hjz4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj4ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj3hhhj3hKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj3hhhj3hKubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1jhj3hKhj3hhubj)}(hhh]h)}(h,balloon out reserved graphics address trunksh]h,balloon out reserved graphics address trunks}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj3hKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj4jj4jjjuh1jhhhj0hNhNubj)}(hX**Parameters** ``struct i915_ggtt *ggtt`` the global GGTT from which to reserve **Description** This function is called at the initialization stage, to balloon out the graphic address space allocated to other vGPUs, by marking these spaces as reserved. The ballooning related knowledge(starting address and size of the mappable/unmappable graphic memory) is described in the vgt_if structure in a reserved mmio range. To give an example, the drawing below depicts one typical scenario after ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned out each for the mappable and the non-mappable part. From the vGPU1 point of view, the total size is the same as the physical one, with the start address of its graphic space being zero. Yet there are some portions ballooned out( the shadow part, which are marked as reserved by drm allocator). From the host point of view, the graphic address space is partitioned by multiple vGPUs in different VMs. :: vGPU1 view Host view 0 ------> +-----------+ +-----------+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ mappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | v |###########| | Host | +=======+===========+ +===========+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ unmappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | | |###########| | Host | v |###########| | | total GM size ------> +-----------+ +-----------+ **Return** zero on success, non-zero if configuration invalid or ballooning failedh](h)}(h**Parameters**h]j)}(hj4h]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubj)}(hhh]j)}(hA``struct i915_ggtt *ggtt`` the global GGTT from which to reserve h](j$)}(h``struct i915_ggtt *ggtt``h]j*)}(hj4h]hstruct i915_ggtt *ggtt}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj4ubah}(h]h ]h"]h$]h&]uh1j#hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubj@)}(hhh]h)}(h%the global GGTT from which to reserveh]h%the global GGTT from which to reserve}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hKhj4ubah}(h]h ]h"]h$]h&]uh1j?hj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hKhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubh)}(h**Description**h]j)}(hj 5h]h Description}(hj"5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(hXAThis function is called at the initialization stage, to balloon out the graphic address space allocated to other vGPUs, by marking these spaces as reserved. The ballooning related knowledge(starting address and size of the mappable/unmappable graphic memory) is described in the vgt_if structure in a reserved mmio range.h]hXAThis function is called at the initialization stage, to balloon out the graphic address space allocated to other vGPUs, by marking these spaces as reserved. The ballooning related knowledge(starting address and size of the mappable/unmappable graphic memory) is described in the vgt_if structure in a reserved mmio range.}(hj65hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(hX(To give an example, the drawing below depicts one typical scenario after ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned out each for the mappable and the non-mappable part. From the vGPU1 point of view, the total size is the same as the physical one, with the start address of its graphic space being zero. Yet there are some portions ballooned out( the shadow part, which are marked as reserved by drm allocator). From the host point of view, the graphic address space is partitioned by multiple vGPUs in different VMs. ::h]hX%To give an example, the drawing below depicts one typical scenario after ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned out each for the mappable and the non-mappable part. From the vGPU1 point of view, the total size is the same as the physical one, with the start address of its graphic space being zero. Yet there are some portions ballooned out( the shadow part, which are marked as reserved by drm allocator). From the host point of view, the graphic address space is partitioned by multiple vGPUs in different VMs.}(hjE5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubjA#)}(hXk vGPU1 view Host view 0 ------> +-----------+ +-----------+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ mappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | v |###########| | Host | +=======+===========+ +===========+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ unmappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | | |###########| | Host | v |###########| | | total GM size ------> +-----------+ +-----------+h]hXk vGPU1 view Host view 0 ------> +-----------+ +-----------+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ mappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | v |###########| | Host | +=======+===========+ +===========+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ unmappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | | |###########| | Host | v |###########| | | total GM size ------> +-----------+ +-----------+}hjT5sbah}(h]h ]h"]h$]h&]j5j6uh1j@#hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(h **Return**h]j)}(hje5h]hReturn}(hjg5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc5ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(hGzero on success, non-zero if configuration invalid or ballooning failedh]hGzero on success, non-zero if configuration invalid or ballooning failed}(hj{5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:55: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj0hhhNhNubeh}(h]intel-gvt-g-guest-support-vgpuah ]h"]intel gvt-g guest support(vgpu)ah$]h&]uh1hhjhhhhhhK2ubh)}(hhh](h)}(h+Intel GVT-g Host Support(vGPU device model)h]h+Intel GVT-g Host Support(vGPU device model)}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhK;ubh)}(hX6Intel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine.h]hX6Intel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:61: ./drivers/gpu/drm/i915/intel_gvt.chK'hj5hhubh)}(hXTo virtualize GPU resources GVT-g driver depends on hypervisor technology e.g KVM/VFIO/mdev, Xen, etc. to provide resource access trapping capability and be virtualized within GVT-g device module. More architectural design doc is available on https://github.com/intel/gvt-linux/wiki.h](hTo virtualize GPU resources GVT-g driver depends on hypervisor technology e.g KVM/VFIO/mdev, Xen, etc. to provide resource access trapping capability and be virtualized within GVT-g device module. More architectural design doc is available on }(hj5hhhNhNubh reference)}(h'https://github.com/intel/gvt-linux/wikih]h'https://github.com/intel/gvt-linux/wiki}(hj5hhhNhNubah}(h]h ]h"]h$]h&]refurij5uh1j5hj5ubh.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:61: ./drivers/gpu/drm/i915/intel_gvt.chK-hj5hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_gvt_init (C function)c.intel_gvt_inithNtauh1jhj5hhhNhNubj)}(hhh](j)}(h6int intel_gvt_init (struct drm_i915_private *dev_priv)h]j)}(h5int intel_gvt_init(struct drm_i915_private *dev_priv)h](jn)}(hinth]hint}(hj5hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj5hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKubj )}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj5hhhj6hKubj)}(hintel_gvt_inith]j)}(hintel_gvt_inith]hintel_gvt_init}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj5hhhj6hKubj8)}(h#(struct drm_i915_private *dev_priv)h]j>)}(h!struct drm_i915_private *dev_privh](jD)}(hjGh]hstruct}(hj36hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj/6ubj )}(h h]h }(hj@6hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/6ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hjQ6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjN6ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjS6modnameN classnameNjj)}j]j)}jj6sbc.intel_gvt_initasbuh1hhj/6ubj )}(h h]h }(hjq6hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/6ubj)}(hjh]h*}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/6ubj)}(hdev_privh]hdev_priv}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/6ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj+6ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj5hhhj6hKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj5hhhj6hKubah}(h]j5ah ](jjeh"]h$]h&]jj)jhuh1jhj6hKhj5hhubj)}(hhh]h)}(hinitialize GVT componentsh]hinitialize GVT components}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKhj6hhubah}(h]h ]h"]h$]h&]uh1jhj5hhhj6hKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj6jj6jjjuh1jhhhj5hNhNubj)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private data **Description** This function is called at the initialization stage to create a GVT device. **Return** Zero on success, negative error code if failed.h](h)}(h**Parameters**h]j)}(hj6h]h Parameters}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKhj6ubj)}(hhh]j)}(h<``struct drm_i915_private *dev_priv`` drm i915 private data h](j$)}(h%``struct drm_i915_private *dev_priv``h]j*)}(hj6h]h!struct drm_i915_private *dev_priv}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj6ubah}(h]h ]h"]h$]h&]uh1j#hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKhj6ubj@)}(hhh]h)}(hdrm i915 private datah]hdrm i915 private data}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 7hKhj 7ubah}(h]h ]h"]h$]h&]uh1j?hj6ubeh}(h]h ]h"]h$]h&]uh1jhj 7hKhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubh)}(h**Description**h]j)}(hj27h]h Description}(hj47hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj07ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKhj6ubh)}(hKThis function is called at the initialization stage to create a GVT device.h]hKThis function is called at the initialization stage to create a GVT device.}(hjH7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKhj6ubh)}(h **Return**h]j)}(hjY7h]hReturn}(hj[7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjW7ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKhj6ubh)}(h/Zero on success, negative error code if failed.h]h/Zero on success, negative error code if failed.}(hjo7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj5hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$intel_gvt_driver_remove (C function)c.intel_gvt_driver_removehNtauh1jhj5hhhNhNubj)}(hhh](j)}(h@void intel_gvt_driver_remove (struct drm_i915_private *dev_priv)h]j)}(h?void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)h](jn)}(hvoidh]hvoid}(hj7hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj7hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKubj )}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj7hhhj7hKubj)}(hintel_gvt_driver_removeh]j)}(hintel_gvt_driver_removeh]hintel_gvt_driver_remove}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj7hhhj7hKubj8)}(h#(struct drm_i915_private *dev_priv)h]j>)}(h!struct drm_i915_private *dev_privh](jD)}(hjGh]hstruct}(hj7hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj7ubj )}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj7ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj7modnameN classnameNjj)}j]j)}jj7sbc.intel_gvt_driver_removeasbuh1hhj7ubj )}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj7ubj)}(hjh]h*}(hj'8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj)}(hdev_privh]hdev_priv}(hj48hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj7ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj7hhhj7hKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj7hhhj7hKubah}(h]j7ah ](jjeh"]h$]h&]jj)jhuh1jhj7hKhj7hhubj)}(hhh]h)}(h4cleanup GVT components when i915 driver is unbindingh]h4cleanup GVT components when i915 driver is unbinding}(hj^8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chKhj[8hhubah}(h]h ]h"]h$]h&]uh1jhj7hhhj7hKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjv8jjv8jjjuh1jhhhj5hNhNubj)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private * **Description** This function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.h](h)}(h**Parameters**h]j)}(hj8h]h Parameters}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~8ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhjz8ubj)}(hhh]j)}(h9``struct drm_i915_private *dev_priv`` drm i915 private * h](j$)}(h%``struct drm_i915_private *dev_priv``h]j*)}(hj8h]h!struct drm_i915_private *dev_priv}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj8ubah}(h]h ]h"]h$]h&]uh1j#hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhj8ubj@)}(hhh]h)}(hdrm i915 private *h]hdrm i915 private *}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1j?hj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhjz8ubh)}(h**Description**h]j)}(hj8h]h Description}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhjz8ubh)}(hyThis function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.h]hyThis function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhjz8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj5hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_gvt_resume (C function)c.intel_gvt_resumehNtauh1jhj5hhhNhNubj)}(hhh](j)}(h9void intel_gvt_resume (struct drm_i915_private *dev_priv)h]j)}(h8void intel_gvt_resume(struct drm_i915_private *dev_priv)h](jn)}(hvoidh]hvoid}(hj9hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj9hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMubj )}(h h]h }(hj.9hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj9hhhj-9hMubj)}(hintel_gvt_resumeh]j)}(hintel_gvt_resumeh]hintel_gvt_resume}(hj@9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<9ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj9hhhj-9hMubj8)}(h#(struct drm_i915_private *dev_priv)h]j>)}(h!struct drm_i915_private *dev_privh](jD)}(hjGh]hstruct}(hj\9hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjX9ubj )}(h h]h }(hji9hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjX9ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hjz9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw9ubah}(h]h ]h"]h$]h&] refdomainXjreftypej reftargetj|9modnameN classnameNjj)}j]j)}jjB9sbc.intel_gvt_resumeasbuh1hhjX9ubj )}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjX9ubj)}(hjh]h*}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX9ubj)}(hdev_privh]hdev_priv}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX9ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjT9ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj9hhhj-9hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj9hhhj-9hMubah}(h]j9ah ](jjeh"]h$]h&]jj)jhuh1jhj-9hMhj9hhubj)}(hhh]h)}(hGVT resume routine wrapperh]hGVT resume routine wrapper}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhj9hhubah}(h]h ]h"]h$]h&]uh1jhj9hhhj-9hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj9jj9jjjuh1jhhhj5hNhNubj)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private * **Description** This function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.h](h)}(h**Parameters**h]j)}(hj:h]h Parameters}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhj9ubj)}(hhh]j)}(h9``struct drm_i915_private *dev_priv`` drm i915 private * h](j$)}(h%``struct drm_i915_private *dev_priv``h]j*)}(hj :h]h!struct drm_i915_private *dev_priv}(hj":hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj:ubah}(h]h ]h"]h$]h&]uh1j#hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhj:ubj@)}(hhh]h)}(hdrm i915 private *h]hdrm i915 private *}(hj9:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5:hMhj6:ubah}(h]h ]h"]h$]h&]uh1j?hj:ubeh}(h]h ]h"]h$]h&]uh1jhj5:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj9ubh)}(h**Description**h]j)}(hj[:h]h Description}(hj]:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY:ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhj9ubh)}(hThis function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.h]hThis function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.}(hjq:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/intel_gvt.chMhj9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj5hhhNhNubeh}(h]*intel-gvt-g-host-support-vgpu-device-modelah ]h"]+intel gvt-g host support(vgpu device model)ah$]h&]uh1hhjhhhhhhK;ubh)}(hhh](h)}(h Workaroundsh]h Workarounds}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hhhhhKDubh)}(hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:h]hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKhj:hhubh bullet_list)}(hhh](h list_item)}(hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers. Context workarounds should be implemented in the \*_ctx_workarounds_init() variants respective to the targeted platforms. h](h)}(hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers.h]hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a “primed golden context”, i.e. a context image that already contains the changes needed to all the registers.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKhj:ubh)}(hyContext workarounds should be implemented in the \*_ctx_workarounds_init() variants respective to the targeted platforms.h]hyContext workarounds should be implemented in the *_ctx_workarounds_init() variants respective to the targeted platforms.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK&hj:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hX Engine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. Workarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine's MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode(). h](h)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference.h](hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It’s also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See }(hj:hhhNhNubj*)}(h.``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c``h]h*drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj:ubh for reference.}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK)hj:ubh)}(hXWorkarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine's MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode().h]hXWorkarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine’s MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode().}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK5hj:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hXGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc. GT workarounds should be implemented in the \*_gt_workarounds_init() variants respective to the targeted platforms. h](h)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc.h](hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume }(hj;hhhNhNubhfootnote_reference)}(h[1]_h]h1}(hj&;hhhNhNubah}(h]id1ah ]h"]h$]h&]hid2docnamejuh1j$;hj;resolvedKubh, etc.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK=hj;ubh)}(hsGT workarounds should be implemented in the \*_gt_workarounds_init() variants respective to the targeted platforms.h]hsGT workarounds should be implemented in the *_gt_workarounds_init() variants respective to the targeted platforms.}(hjC;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK@hj;ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hXRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers). Register whitelisting should be done in the \*_whitelist_build() variants respective to the targeted platforms. h](h)}(hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).h]hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).}(hj\;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKChjX;ubh)}(hoRegister whitelisting should be done in the \*_whitelist_build() variants respective to the targeted platforms.h]hoRegister whitelisting should be done in the *_whitelist_build() variants respective to the targeted platforms.}(hjk;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKIhjX;ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hX`Workaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms: #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms. #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver. h](h)}(hXRWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms:h]hXRWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms:}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKLhj;ubhenumerated_list)}(hhh](j:)}(hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms. h]h)}(hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms.h]hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKRhj;ubah}(h]h ]h"]h$]h&]uh1j:hj;ubj:)}(hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver. h]h)}(hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver.h]hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKWhj;ubah}(h]h ]h"]h$]h&]uh1j:hj;ubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j;hj;ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example. h]h)}(hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example.h]hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK\hj;ubah}(h]h ]h"]h$]h&]uh1j:hj:ubeh}(h]h ]h"]h$]h&]bullet-uh1j:hj:hKhj:hhubhfootnote)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver. h](hlabel)}(h1h]h1}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j<hj;ubh)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver.h]hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it’s the approach taken in the driver.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:70: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK`hj;ubeh}(h]j5;ah ]h"]1ah$]h&]j0;aj6;juh1j;hj <hK`hj:hhj7;Kubeh}(h] workaroundsah ]h"] workaroundsah$]h&]uh1hhjhhhhhhKDubeh}(h]core-driver-infrastructureah ]h"]core driver infrastructureah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hGT Programmingh]hGT Programming}(hj;<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8<hhhhhKJubh)}(hhh](h)}(h$Multicast/Replicated (MCR) Registersh]h$Multicast/Replicated (MCR) Registers}(hjL<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI<hhhhhKMubh)}(hXwSome GT registers are designed as "multicast" or "replicated" registers: multiple instances of the same register share a single MMIO offset. MCR registers are generally used when the hardware needs to potentially track independent values of a register per hardware unit (e.g., per-subslice, per-L3bank, etc.). The specific types of replication that exist vary per-platform.h]hXSome GT registers are designed as “multicast” or “replicated” registers: multiple instances of the same register share a single MMIO offset. MCR registers are generally used when the hardware needs to potentially track independent values of a register per hardware unit (e.g., per-subslice, per-L3bank, etc.). The specific types of replication that exist vary per-platform.}(hjZ<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:79: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chKhjI<hhubh)}(hXMMIO accesses to MCR registers are controlled according to the settings programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR registers can be done in either a (i.e., a single write updates all instances of the register to the same value) or unicast (a write updates only one specific instance). Reads of MCR registers always operate in a unicast manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR. Selection of a specific MCR instance for unicast operations is referred to as "steering."h]hXMMIO accesses to MCR registers are controlled according to the settings programmed in the platform’s MCR_SELECTOR register(s). MMIO writes to MCR registers can be done in either a (i.e., a single write updates all instances of the register to the same value) or unicast (a write updates only one specific instance). Reads of MCR registers always operate in a unicast manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR. Selection of a specific MCR instance for unicast operations is referred to as “steering.”}(hji<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:79: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chKhjI<hhubh)}(hX,If MCR register operations are steered toward a hardware unit that is fused off or currently powered down due to power gating, the MMIO operation is "terminated" by the hardware. Terminated read operations will return a value of zero and terminated unicast write operations will be silently ignored.h]hX0If MCR register operations are steered toward a hardware unit that is fused off or currently powered down due to power gating, the MMIO operation is “terminated” by the hardware. Terminated read operations will return a value of zero and terminated unicast write operations will be silently ignored.}(hjx<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:79: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chKhjI<hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_gt_mcr_lock (C function)c.intel_gt_mcr_lockhNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hBvoid intel_gt_mcr_lock (struct intel_gt *gt, unsigned long *flags)h]j)}(hAvoid intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags)h](jn)}(hvoidh]hvoid}(hj<hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj<hhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM:ubj )}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj<hhhj<hM:ubj)}(hintel_gt_mcr_lockh]j)}(hintel_gt_mcr_lockh]hintel_gt_mcr_lock}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj<hhhj<hM:ubj8)}(h+(struct intel_gt *gt, unsigned long *flags)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hj<hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj<ubj )}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj<ubh)}(hhh]j)}(hintel_gth]hintel_gt}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj<modnameN classnameNjj)}j]j)}jj<sbc.intel_gt_mcr_lockasbuh1hhj<ubj )}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj<ubj)}(hjh]h*}(hj)=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubj)}(hgth]hgt}(hj6=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj<ubj>)}(hunsigned long *flagsh](jn)}(hunsignedh]hunsigned}(hjO=hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjK=ubj )}(h h]h }(hj]=hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjK=ubjn)}(hlongh]hlong}(hjk=hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjK=ubj )}(h h]h }(hjy=hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjK=ubj)}(hjh]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjK=ubj)}(hflagsh]hflags}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjK=ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj<ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj<hhhj<hM:ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj<hhhj<hM:ubah}(h]j<ah ](jjeh"]h$]h&]jj)jhuh1jhj<hM:hj<hhubj)}(hhh]h)}(hAcquire MCR steering lockh]hAcquire MCR steering lock}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM:hj=hhubah}(h]h ]h"]h$]h&]uh1jhj<hhhj<hM:ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj=jj=jjjuh1jhhhjI<hNhNubj)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``unsigned long *flags`` storage to save IRQ flags to **Description** Performs locking to protect the steering for the duration of an MCR operation. On MTL and beyond, a hardware lock will also be taken to serialize access not only for the driver, but also for external hardware and firmware agents. **Context** Takes gt->mcr_lock. uncore->lock should *not* be held when this function is called, although it may be acquired after this function call.h](h)}(h**Parameters**h]j)}(hj=h]h Parameters}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM>hj=ubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hj=h]hstruct intel_gt *gt}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj=ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM;hj=ubj@)}(hhh]h)}(h GT structureh]h GT structure}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hM;hj>ubah}(h]h ]h"]h$]h&]uh1j?hj=ubeh}(h]h ]h"]h$]h&]uh1jhj>hM;hj=ubj)}(h6``unsigned long *flags`` storage to save IRQ flags to h](j$)}(h``unsigned long *flags``h]j*)}(hj8>h]hunsigned long *flags}(hj:>hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj6>ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM<hj2>ubj@)}(hhh]h)}(hstorage to save IRQ flags toh]hstorage to save IRQ flags to}(hjQ>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM>hM<hjN>ubah}(h]h ]h"]h$]h&]uh1j?hj2>ubeh}(h]h ]h"]h$]h&]uh1jhjM>hM<hj=ubeh}(h]h ]h"]h$]h&]uh1jhj=ubh)}(h**Description**h]j)}(hjs>h]h Description}(hju>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq>ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM>hj=ubh)}(hPerforms locking to protect the steering for the duration of an MCR operation. On MTL and beyond, a hardware lock will also be taken to serialize access not only for the driver, but also for external hardware and firmware agents.h]hPerforms locking to protect the steering for the duration of an MCR operation. On MTL and beyond, a hardware lock will also be taken to serialize access not only for the driver, but also for external hardware and firmware agents.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM=hj=ubh)}(h **Context**h]j)}(hj>h]hContext}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMBhj=ubh)}(hTakes gt->mcr_lock. uncore->lock should *not* be held when this function is called, although it may be acquired after this function call.h](h)Takes gt->mcr_lock. uncore->lock should }(hj>hhhNhNubhemphasis)}(h*not*h]hnot}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j>hj>ubh\ be held when this function is called, although it may be acquired after this function call.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMChj=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j intel_gt_mcr_unlock (C function)c.intel_gt_mcr_unlockhNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hCvoid intel_gt_mcr_unlock (struct intel_gt *gt, unsigned long flags)h]j)}(hBvoid intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags)h](jn)}(hvoidh]hvoid}(hj>hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj>hhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM~ubj )}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj>hhhj?hM~ubj)}(hintel_gt_mcr_unlockh]j)}(hintel_gt_mcr_unlockh]hintel_gt_mcr_unlock}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj>hhhj?hM~ubj8)}(h*(struct intel_gt *gt, unsigned long flags)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hj0?hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj,?ubj )}(h h]h }(hj=?hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj,?ubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjN?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjK?ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjP?modnameN classnameNjj)}j]j)}jj?sbc.intel_gt_mcr_unlockasbuh1hhj,?ubj )}(h h]h }(hjn?hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj,?ubj)}(hjh]h*}(hj|?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,?ubj)}(hgth]hgt}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,?ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj(?ubj>)}(hunsigned long flagsh](jn)}(hunsignedh]hunsigned}(hj?hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj?ubj )}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj?ubjn)}(hlongh]hlong}(hj?hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj?ubj )}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj?ubj)}(hflagsh]hflags}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj(?ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj>hhhj?hM~ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj>hhhj?hM~ubah}(h]j>ah ](jjeh"]h$]h&]jj)jhuh1jhj?hM~hj>hhubj)}(hhh]h)}(hRelease MCR steering lockh]hRelease MCR steering lock}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM~hj@hhubah}(h]h ]h"]h$]h&]uh1jhj>hhhj?hM~ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj@jj@jjjuh1jhhhjI<hNhNubj)}(h**Parameters** ``struct intel_gt *gt`` GT structure ``unsigned long flags`` IRQ flags to restore **Description** Releases the lock acquired by intel_gt_mcr_lock(). **Context** Releases gt->mcr_lockh](h)}(h**Parameters**h]j)}(hj&@h]h Parameters}(hj(@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$@ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj @ubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hjE@h]hstruct intel_gt *gt}(hjG@hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjC@ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj?@ubj@)}(hhh]h)}(h GT structureh]h GT structure}(hj^@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ@hMhj[@ubah}(h]h ]h"]h$]h&]uh1j?hj?@ubeh}(h]h ]h"]h$]h&]uh1jhjZ@hMhj<@ubj)}(h-``unsigned long flags`` IRQ flags to restore h](j$)}(h``unsigned long flags``h]j*)}(hj~@h]hunsigned long flags}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj|@ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjx@ubj@)}(hhh]h)}(hIRQ flags to restoreh]hIRQ flags to restore}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1j?hjx@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj<@ubeh}(h]h ]h"]h$]h&]uh1jhj @ubh)}(h**Description**h]j)}(hj@h]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj @ubh)}(h2Releases the lock acquired by intel_gt_mcr_lock().h]h2Releases the lock acquired by intel_gt_mcr_lock().}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj @ubh)}(h **Context**h]j)}(hj@h]hContext}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj @ubh)}(hReleases gt->mcr_lockh]hReleases gt->mcr_lock}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj @ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'intel_gt_mcr_lock_sanitize (C function)c.intel_gt_mcr_lock_sanitizehNtauh1jhjI<hhhNhNubj)}(hhh](j)}(h5void intel_gt_mcr_lock_sanitize (struct intel_gt *gt)h]j)}(h4void intel_gt_mcr_lock_sanitize(struct intel_gt *gt)h](jn)}(hvoidh]hvoid}(hj%AhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj!Ahhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubj )}(h h]h }(hj4AhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj!Ahhhj3AhMubj)}(hintel_gt_mcr_lock_sanitizeh]j)}(hintel_gt_mcr_lock_sanitizeh]hintel_gt_mcr_lock_sanitize}(hjFAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBAubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj!Ahhhj3AhMubj8)}(h(struct intel_gt *gt)h]j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hjbAhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj^Aubj )}(h h]h }(hjoAhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^Aubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}Aubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjAmodnameN classnameNjj)}j]j)}jjHAsbc.intel_gt_mcr_lock_sanitizeasbuh1hhj^Aubj )}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^Aubj)}(hjh]h*}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^Aubj)}(hgth]hgt}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^Aubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjZAubah}(h]h ]h"]h$]h&]j5j6uh1j7hj!Ahhhj3AhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjAhhhj3AhMubah}(h]jAah ](jjeh"]h$]h&]jj)jhuh1jhj3AhMhjAhhubj)}(hhh]h)}(hSanitize MCR steering lockh]hSanitize MCR steering lock}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjAhhubah}(h]h ]h"]h$]h&]uh1jhjAhhhj3AhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjAjjAjjjuh1jhhhjI<hNhNubj)}(hXE**Parameters** ``struct intel_gt *gt`` GT structure **Description** This will be used to sanitize the initial status of the hardware lock during driver load and resume since there won't be any concurrent access from other agents at those times, but it's possible that boot firmware may have left the lock in a bad state.h](h)}(h**Parameters**h]j)}(hjBh]h Parameters}(hj BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjBubj)}(hhh]j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hj&Bh]hstruct intel_gt *gt}(hj(BhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj$Bubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj Bubj@)}(hhh]h)}(h GT structureh]h GT structure}(hj?BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;BhMhj)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hjBhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjBubj )}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjCmodnameN classnameNjj)}j]jBc.intel_gt_mcr_readasbuh1hhjBubj )}(h h]h }(hj4ChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBubj)}(hjh]h*}(hjBChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(hgth]hgt}(hjOChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjBubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjkChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhCubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmCmodnameN classnameNjj)}j]jBc.intel_gt_mcr_readasbuh1hhjdCubj )}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjdCubj)}(hregh]hreg}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdCubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjBubj>)}(h int grouph](jn)}(hinth]hint}(hjChhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjCubj )}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjCubj)}(hgrouph]hgroup}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjBubj>)}(h int instanceh](jn)}(hinth]hint}(hjChhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjCubj )}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjCubj)}(hinstanceh]hinstance}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjBubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjBhhhjBhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjBhhhjBhMubah}(h]jBah ](jjeh"]h$]h&]jj)jhuh1jhjBhMhjBhhubj)}(hhh]h)}(h+read a specific instance of an MCR registerh]h+read a specific instance of an MCR register}(hj+DhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj(Dhhubah}(h]h ]h"]h$]h&]uh1jhjBhhhjBhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjCDjjCDjjjuh1jhhhjI<hNhNubj)}(hXJ**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to read ``int group`` the MCR group ``int instance`` the MCR instance **Context** Takes and releases gt->mcr_lock **Description** Returns the value read from an MCR register after steering toward a specific group/instance.h](h)}(h**Parameters**h]j)}(hjMDh]h Parameters}(hjODhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKDubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGDubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hjlDh]hstruct intel_gt *gt}(hjnDhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjjDubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjfDubj@)}(hhh]h)}(h GT structureh]h GT structure}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjDubah}(h]h ]h"]h$]h&]uh1j?hjfDubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjcDubj)}(h0``i915_mcr_reg_t reg`` the MCR register to read h](j$)}(h``i915_mcr_reg_t reg``h]j*)}(hjDh]hi915_mcr_reg_t reg}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjDubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubj@)}(hhh]h)}(hthe MCR register to readh]hthe MCR register to read}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjDubah}(h]h ]h"]h$]h&]uh1j?hjDubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjcDubj)}(h``int group`` the MCR group h](j$)}(h ``int group``h]j*)}(hjDh]h int group}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjDubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubj@)}(hhh]h)}(h the MCR grouph]h the MCR group}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjDubah}(h]h ]h"]h$]h&]uh1j?hjDubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjcDubj)}(h"``int instance`` the MCR instance h](j$)}(h``int instance``h]j*)}(hjEh]h int instance}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjEubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjEubj@)}(hhh]h)}(hthe MCR instanceh]hthe MCR instance}(hj0EhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,EhMhj-Eubah}(h]h ]h"]h$]h&]uh1j?hjEubeh}(h]h ]h"]h$]h&]uh1jhj,EhMhjcDubeh}(h]h ]h"]h$]h&]uh1jhjGDubh)}(h **Context**h]j)}(hjREh]hContext}(hjTEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPEubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGDubh)}(hTakes and releases gt->mcr_lockh]hTakes and releases gt->mcr_lock}(hjhEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGDubh)}(h**Description**h]j)}(hjyEh]h Description}(hj{EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwEubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGDubh)}(h\Returns the value read from an MCR register after steering toward a specific group/instance.h]h\Returns the value read from an MCR register after steering toward a specific group/instance.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGDubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'intel_gt_mcr_unicast_write (C function)c.intel_gt_mcr_unicast_writehNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hmvoid intel_gt_mcr_unicast_write (struct intel_gt *gt, i915_mcr_reg_t reg, u32 value, int group, int instance)h]j)}(hlvoid intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value, int group, int instance)h](jn)}(hvoidh]hvoid}(hjEhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjEhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubj )}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjEhhhjEhMubj)}(hintel_gt_mcr_unicast_writeh]j)}(hintel_gt_mcr_unicast_writeh]hintel_gt_mcr_unicast_write}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjEhhhjEhMubj8)}(hM(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value, int group, int instance)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hjEhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjEubj )}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjEubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjFmodnameN classnameNjj)}j]j)}jjEsbc.intel_gt_mcr_unicast_writeasbuh1hhjEubj )}(h h]h }(hj9FhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjEubj)}(hjh]h*}(hjGFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(hgth]hgt}(hjTFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjpFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmFubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjrFmodnameN classnameNjj)}j]j5Fc.intel_gt_mcr_unicast_writeasbuh1hhjiFubj )}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjiFubj)}(hregh]hreg}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiFubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(h u32 valueh](h)}(hhh]j)}(hu32h]hu32}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjFmodnameN classnameNjj)}j]j5Fc.intel_gt_mcr_unicast_writeasbuh1hhjFubj )}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjFubj)}(hvalueh]hvalue}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(h int grouph](jn)}(hinth]hint}(hjFhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjFubj )}(h h]h }(hj GhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjFubj)}(hgrouph]hgroup}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(h int instanceh](jn)}(hinth]hint}(hj2GhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj.Gubj )}(h h]h }(hj@GhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj.Gubj)}(hinstanceh]hinstance}(hjNGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.Gubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjEhhhjEhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjEhhhjEhMubah}(h]jEah ](jjeh"]h$]h&]jj)jhuh1jhjEhMhjEhhubj)}(hhh]h)}(h,write a specific instance of an MCR registerh]h,write a specific instance of an MCR register}(hjxGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjuGhhubah}(h]h ]h"]h$]h&]uh1jhjEhhhjEhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjGjjGjjjuh1jhhhjI<hNhNubj)}(hX{**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to write ``u32 value`` value to write ``int group`` the MCR group ``int instance`` the MCR instance **Description** Write an MCR register in unicast mode after steering toward a specific group/instance. **Context** Calls a function that takes and releases gt->mcr_lockh](h)}(h**Parameters**h]j)}(hjGh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hjGh]hstruct intel_gt *gt}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjGubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubj@)}(hhh]h)}(h GT structureh]h GT structure}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjGubah}(h]h ]h"]h$]h&]uh1j?hjGubeh}(h]h ]h"]h$]h&]uh1jhjGhMhjGubj)}(h1``i915_mcr_reg_t reg`` the MCR register to write h](j$)}(h``i915_mcr_reg_t reg``h]j*)}(hjGh]hi915_mcr_reg_t reg}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjGubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubj@)}(hhh]h)}(hthe MCR register to writeh]hthe MCR register to write}(hj HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMhjHubah}(h]h ]h"]h$]h&]uh1j?hjGubeh}(h]h ]h"]h$]h&]uh1jhjHhMhjGubj)}(h``u32 value`` value to write h](j$)}(h ``u32 value``h]j*)}(hj+Hh]h u32 value}(hj-HhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj)Hubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj%Hubj@)}(hhh]h)}(hvalue to writeh]hvalue to write}(hjDHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@HhMhjAHubah}(h]h ]h"]h$]h&]uh1j?hj%Hubeh}(h]h ]h"]h$]h&]uh1jhj@HhMhjGubj)}(h``int group`` the MCR group h](j$)}(h ``int group``h]j*)}(hjdHh]h int group}(hjfHhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjbHubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj^Hubj@)}(hhh]h)}(h the MCR grouph]h the MCR group}(hj}HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyHhMhjzHubah}(h]h ]h"]h$]h&]uh1j?hj^Hubeh}(h]h ]h"]h$]h&]uh1jhjyHhMhjGubj)}(h"``int instance`` the MCR instance h](j$)}(h``int instance``h]j*)}(hjHh]h int instance}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjHubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjHubj@)}(hhh]h)}(hthe MCR instanceh]hthe MCR instance}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMhjHubah}(h]h ]h"]h$]h&]uh1j?hjHubeh}(h]h ]h"]h$]h&]uh1jhjHhMhjGubeh}(h]h ]h"]h$]h&]uh1jhjGubh)}(h**Description**h]j)}(hjHh]h Description}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubh)}(hVWrite an MCR register in unicast mode after steering toward a specific group/instance.h]hVWrite an MCR register in unicast mode after steering toward a specific group/instance.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubh)}(h **Context**h]j)}(hjHh]hContext}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubh)}(h5Calls a function that takes and releases gt->mcr_lockh]h5Calls a function that takes and releases gt->mcr_lock}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)intel_gt_mcr_multicast_write (C function)c.intel_gt_mcr_multicast_writehNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hVvoid intel_gt_mcr_multicast_write (struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h]j)}(hUvoid intel_gt_mcr_multicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](jn)}(hvoidh]hvoid}(hjDIhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj@Ihhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubj )}(h h]h }(hjSIhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj@IhhhjRIhMubj)}(hintel_gt_mcr_multicast_writeh]j)}(hintel_gt_mcr_multicast_writeh]hintel_gt_mcr_multicast_write}(hjeIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaIubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj@IhhhjRIhMubj8)}(h4(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hjIhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj}Iubj )}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj}Iubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjImodnameN classnameNjj)}j]j)}jjgIsbc.intel_gt_mcr_multicast_writeasbuh1hhj}Iubj )}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj}Iubj)}(hjh]h*}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}Iubj)}(hgth]hgt}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}Iubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjyIubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjImodnameN classnameNjj)}j]jIc.intel_gt_mcr_multicast_writeasbuh1hhjIubj )}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjIubj)}(hregh]hreg}(hj"JhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjyIubj>)}(h u32 valueh](h)}(hhh]j)}(hu32h]hu32}(hj>JhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;Jubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj@JmodnameN classnameNjj)}j]jIc.intel_gt_mcr_multicast_writeasbuh1hhj7Jubj )}(h h]h }(hj\JhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj7Jubj)}(hvalueh]hvalue}(hjjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7Jubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjyIubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj@IhhhjRIhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjmcr_lockh](h)}(h**Parameters**h]j)}(hjJh]h Parameters}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjJubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hjJh]hstruct intel_gt *gt}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjJubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjJubj@)}(hhh]h)}(h GT structureh]h GT structure}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMhjJubah}(h]h ]h"]h$]h&]uh1j?hjJubeh}(h]h ]h"]h$]h&]uh1jhjJhMhjJubj)}(h1``i915_mcr_reg_t reg`` the MCR register to write h](j$)}(h``i915_mcr_reg_t reg``h]j*)}(hjKh]hi915_mcr_reg_t reg}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj Kubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjKubj@)}(hhh]h)}(hthe MCR register to writeh]hthe MCR register to write}(hj'KhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#KhMhj$Kubah}(h]h ]h"]h$]h&]uh1j?hjKubeh}(h]h ]h"]h$]h&]uh1jhj#KhMhjJubj)}(h``u32 value`` value to write h](j$)}(h ``u32 value``h]j*)}(hjGKh]h u32 value}(hjIKhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjEKubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjAKubj@)}(hhh]h)}(hvalue to writeh]hvalue to write}(hj`KhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\KhMhj]Kubah}(h]h ]h"]h$]h&]uh1j?hjAKubeh}(h]h ]h"]h$]h&]uh1jhj\KhMhjJubeh}(h]h ]h"]h$]h&]uh1jhjJubh)}(h**Description**h]j)}(hjKh]h Description}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjJubh)}(h@Write an MCR register in multicast mode to update all instances.h]h@Write an MCR register in multicast mode to update all instances.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjJubh)}(h **Context**h]j)}(hjKh]hContext}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjJubh)}(hTakes and releases gt->mcr_lockh]hTakes and releases gt->mcr_lock}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjJubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,intel_gt_mcr_multicast_write_fw (C function)!c.intel_gt_mcr_multicast_write_fwhNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hYvoid intel_gt_mcr_multicast_write_fw (struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h]j)}(hXvoid intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](jn)}(hvoidh]hvoid}(hjKhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjKhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubj )}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjKhhhjKhMubj)}(hintel_gt_mcr_multicast_write_fwh]j)}(hintel_gt_mcr_multicast_write_fwh]hintel_gt_mcr_multicast_write_fw}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Lubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjKhhhjKhMubj8)}(h4(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hj+LhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj'Lubj )}(h h]h }(hj8LhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj'Lubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjILhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFLubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjKLmodnameN classnameNjj)}j]j)}jjLsb!c.intel_gt_mcr_multicast_write_fwasbuh1hhj'Lubj )}(h h]h }(hjiLhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj'Lubj)}(hjh]h*}(hjwLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'Lubj)}(hgth]hgt}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'Lubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj#Lubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjLmodnameN classnameNjj)}j]jeL!c.intel_gt_mcr_multicast_write_fwasbuh1hhjLubj )}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjLubj)}(hregh]hreg}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj#Lubj>)}(h u32 valueh](h)}(hhh]j)}(hu32h]hu32}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjLmodnameN classnameNjj)}j]jeL!c.intel_gt_mcr_multicast_write_fwasbuh1hhjLubj )}(h h]h }(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjLubj)}(hvalueh]hvalue}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj#Lubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjKhhhjKhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjKhhhjKhMubah}(h]jKah ](jjeh"]h$]h&]jj)jhuh1jhjKhMhjKhhubj)}(hhh]h)}(h1write a value to all instances of an MCR registerh]h1write a value to all instances of an MCR register}(hj>MhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj;Mhhubah}(h]h ]h"]h$]h&]uh1jhjKhhhjKhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjVMjjVMjjjuh1jhhhjI<hNhNubj)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to write ``u32 value`` value to write **Description** Write an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically. **Context** The caller must hold gt->mcr_lock.h](h)}(h**Parameters**h]j)}(hj`Mh]h Parameters}(hjbMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^Mubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjZMubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hjMh]hstruct intel_gt *gt}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj}Mubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjyMubj@)}(hhh]h)}(h GT structureh]h GT structure}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhMhjMubah}(h]h ]h"]h$]h&]uh1j?hjyMubeh}(h]h ]h"]h$]h&]uh1jhjMhMhjvMubj)}(h1``i915_mcr_reg_t reg`` the MCR register to write h](j$)}(h``i915_mcr_reg_t reg``h]j*)}(hjMh]hi915_mcr_reg_t reg}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjMubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjMubj@)}(hhh]h)}(hthe MCR register to writeh]hthe MCR register to write}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhMhjMubah}(h]h ]h"]h$]h&]uh1j?hjMubeh}(h]h ]h"]h$]h&]uh1jhjMhMhjvMubj)}(h``u32 value`` value to write h](j$)}(h ``u32 value``h]j*)}(hjMh]h u32 value}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjMubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjMubj@)}(hhh]h)}(hvalue to writeh]hvalue to write}(hj NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhMhjNubah}(h]h ]h"]h$]h&]uh1j?hjMubeh}(h]h ]h"]h$]h&]uh1jhjNhMhjvMubeh}(h]h ]h"]h$]h&]uh1jhjZMubh)}(h**Description**h]j)}(hj,Nh]h Description}(hj.NhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*Nubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjZMubh)}(hWrite an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically.h]hWrite an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically.}(hjBNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjZMubh)}(h **Context**h]j)}(hjSNh]hContext}(hjUNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjZMubh)}(h"The caller must hold gt->mcr_lock.h]h"The caller must hold gt->mcr_lock.}(hjiNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjZMubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'intel_gt_mcr_multicast_rmw (C function)c.intel_gt_mcr_multicast_rmwhNtauh1jhjI<hhhNhNubj)}(hhh](j)}(h\u32 intel_gt_mcr_multicast_rmw (struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h]j)}(h[u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h](h)}(hhh]j)}(hu32h]hu32}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjNmodnameN classnameNjj)}j]j)}jintel_gt_mcr_multicast_rmwsbc.intel_gt_mcr_multicast_rmwasbuh1hhjNhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubj )}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjNhhhjNhMubj)}(hintel_gt_mcr_multicast_rmwh]j)}(hjNh]hintel_gt_mcr_multicast_rmw}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjNhhhjNhMubj8)}(h=(struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hjNhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjNubj )}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjNubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj OmodnameN classnameNjj)}j]jNc.intel_gt_mcr_multicast_rmwasbuh1hhjNubj )}(h h]h }(hj&OhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjNubj)}(hjh]h*}(hj4OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubj)}(hgth]hgt}(hjAOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjNubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hj]OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZOubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj_OmodnameN classnameNjj)}j]jNc.intel_gt_mcr_multicast_rmwasbuh1hhjVOubj )}(h h]h }(hj{OhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjVOubj)}(hregh]hreg}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVOubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjNubj>)}(h u32 clearh](h)}(hhh]j)}(hu32h]hu32}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjOmodnameN classnameNjj)}j]jNc.intel_gt_mcr_multicast_rmwasbuh1hhjOubj )}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjOubj)}(hclearh]hclear}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjNubj>)}(hu32 seth](h)}(hhh]j)}(hu32h]hu32}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjOmodnameN classnameNjj)}j]jNc.intel_gt_mcr_multicast_rmwasbuh1hhjOubj )}(h h]h }(hj PhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjOubj)}(hseth]hset}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjNubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjNhhhjNhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjNhhhjNhMubah}(h]jNah ](jjeh"]h$]h&]jj)jhuh1jhjNhMhjNhhubj)}(hhh]h)}(h#Performs a multicast RMW operationsh]h#Performs a multicast RMW operations}(hjCPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj@Phhubah}(h]h ]h"]h$]h&]uh1jhjNhhhjNhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj[Pjj[Pjjjuh1jhhhjI<hNhNubj)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to read and write ``u32 clear`` bits to clear during RMW ``u32 set`` bits to set during RMW **Description** Performs a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically. Returns the old (unmodified) value read. **Context** Calls functions that take and release gt->mcr_lockh](h)}(h**Parameters**h]j)}(hjePh]h Parameters}(hjgPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcPubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj_Pubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hjPh]hstruct intel_gt *gt}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjPubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj~Pubj@)}(hhh]h)}(h GT structureh]h GT structure}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjPubah}(h]h ]h"]h$]h&]uh1j?hj~Pubeh}(h]h ]h"]h$]h&]uh1jhjPhMhj{Pubj)}(h:``i915_mcr_reg_t reg`` the MCR register to read and write h](j$)}(h``i915_mcr_reg_t reg``h]j*)}(hjPh]hi915_mcr_reg_t reg}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjPubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hjPubj@)}(hhh]h)}(h"the MCR register to read and writeh]h"the MCR register to read and write}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM hjPubah}(h]h ]h"]h$]h&]uh1j?hjPubeh}(h]h ]h"]h$]h&]uh1jhjPhM hj{Pubj)}(h'``u32 clear`` bits to clear during RMW h](j$)}(h ``u32 clear``h]j*)}(hjPh]h u32 clear}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjPubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hjPubj@)}(hhh]h)}(hbits to clear during RMWh]hbits to clear during RMW}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj QhM hj Qubah}(h]h ]h"]h$]h&]uh1j?hjPubeh}(h]h ]h"]h$]h&]uh1jhj QhM hj{Pubj)}(h#``u32 set`` bits to set during RMW h](j$)}(h ``u32 set``h]j*)}(hj/Qh]hu32 set}(hj1QhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj-Qubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj)Qubj@)}(hhh]h)}(hbits to set during RMWh]hbits to set during RMW}(hjHQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDQhM hjEQubah}(h]h ]h"]h$]h&]uh1j?hj)Qubeh}(h]h ]h"]h$]h&]uh1jhjDQhM hj{Pubeh}(h]h ]h"]h$]h&]uh1jhj_Pubh)}(h**Description**h]j)}(hjjQh]h Description}(hjlQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhQubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj_Pubh)}(hXPerforms a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances.h]hXPerforms a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj_Pubh)}(hThis function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically.h]hThis function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj_Pubh)}(h(Returns the old (unmodified) value read.h]h(Returns the old (unmodified) value read.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj_Pubh)}(h **Context**h]j)}(hjQh]hContext}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj_Pubh)}(h2Calls functions that take and release gt->mcr_lockh]h2Calls functions that take and release gt->mcr_lock}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj_Pubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j4intel_gt_mcr_get_nonterminated_steering (C function))c.intel_gt_mcr_get_nonterminated_steeringhNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hovoid intel_gt_mcr_get_nonterminated_steering (struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h]j)}(hnvoid intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h](jn)}(hvoidh]hvoid}(hjQhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjQhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubj )}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjQhhhjRhMubj)}(h'intel_gt_mcr_get_nonterminated_steeringh]j)}(h'intel_gt_mcr_get_nonterminated_steeringh]h'intel_gt_mcr_get_nonterminated_steering}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjQhhhjRhMubj8)}(hB(struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hj1RhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj-Rubj )}(h h]h }(hj>RhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj-Rubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjORhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLRubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjQRmodnameN classnameNjj)}j]j)}jjRsb)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhj-Rubj )}(h h]h }(hjoRhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj-Rubj)}(hjh]h*}(hj}RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-Rubj)}(hgth]hgt}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-Rubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj)Rubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjRmodnameN classnameNjj)}j]jkR)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhjRubj )}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjRubj)}(hregh]hreg}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj)Rubj>)}(h u8 *grouph](h)}(hhh]j)}(hu8h]hu8}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjRmodnameN classnameNjj)}j]jkR)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhjRubj )}(h h]h }(hj ShhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjRubj)}(hjh]h*}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(hgrouph]hgroup}(hj'ShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj)Rubj>)}(h u8 *instanceh](h)}(hhh]j)}(hu8h]hu8}(hjCShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@Subah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjESmodnameN classnameNjj)}j]jkR)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhj)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hjdUhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj`Uubj )}(h h]h }(hjqUhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj`Uubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]j1Uc.intel_gt_mcr_read_any_fwasbuh1hhj`Uubj )}(h h]h }(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj`Uubj)}(hjh]h*}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`Uubj)}(hgth]hgt}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`Uubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj\Uubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]j1Uc.intel_gt_mcr_read_any_fwasbuh1hhjUubj )}(h h]h }(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjUubj)}(hregh]hreg}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj\Uubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjUhhhj6UhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj Uhhhj6UhMubah}(h]jUah ](jjeh"]h$]h&]jj)jhuh1jhj6UhMhjUhhubj)}(hhh]h)}(h%reads one instance of an MCR registerh]h%reads one instance of an MCR register}(hj-VhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj*Vhhubah}(h]h ]h"]h$]h&]uh1jhjUhhhj6UhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjEVjjEVjjjuh1jhhhjI<hNhNubj)}(hX!**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` register to read **Description** Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically. Returns the value from a non-terminated instance of **reg**. **Context** The caller must hold gt->mcr_lock.h](h)}(h**Parameters**h]j)}(hjOVh]h Parameters}(hjQVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMVubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjIVubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hjnVh]hstruct intel_gt *gt}(hjpVhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjlVubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjhVubj@)}(hhh]h)}(h GT structureh]h GT structure}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhMhjVubah}(h]h ]h"]h$]h&]uh1j?hjhVubeh}(h]h ]h"]h$]h&]uh1jhjVhMhjeVubj)}(h(``i915_mcr_reg_t reg`` register to read h](j$)}(h``i915_mcr_reg_t reg``h]j*)}(hjVh]hi915_mcr_reg_t reg}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjVubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjVubj@)}(hhh]h)}(hregister to readh]hregister to read}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhMhjVubah}(h]h ]h"]h$]h&]uh1j?hjVubeh}(h]h ]h"]h$]h&]uh1jhjVhMhjeVubeh}(h]h ]h"]h$]h&]uh1jhjIVubh)}(h**Description**h]j)}(hjVh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjIVubh)}(hX=Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically.h]hX?Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn’t fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjIVubh)}(hmcr_lock.h]h"The caller must hold gt->mcr_lock.}(hj@WhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjIVubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_gt_mcr_read_any (C function)c.intel_gt_mcr_read_anyhNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hCu32 intel_gt_mcr_read_any (struct intel_gt *gt, i915_mcr_reg_t reg)h]j)}(hBu32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg)h](h)}(hhh]j)}(hu32h]hu32}(hjrWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoWubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjtWmodnameN classnameNjj)}j]j)}jintel_gt_mcr_read_anysbc.intel_gt_mcr_read_anyasbuh1hhjkWhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubj )}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjkWhhhjWhMubj)}(hintel_gt_mcr_read_anyh]j)}(hjWh]hintel_gt_mcr_read_any}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjkWhhhjWhMubj8)}(h)(struct intel_gt *gt, i915_mcr_reg_t reg)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hjWhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjWubj )}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjWubh)}(hhh]j)}(hintel_gth]hintel_gt}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjWmodnameN classnameNjj)}j]jWc.intel_gt_mcr_read_anyasbuh1hhjWubj )}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjWubj)}(hjh]h*}(hj XhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj)}(hgth]hgt}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hj4XhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1Xubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj6XmodnameN classnameNjj)}j]jWc.intel_gt_mcr_read_anyasbuh1hhj-Xubj )}(h h]h }(hjRXhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj-Xubj)}(hregh]hreg}(hj`XhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-Xubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjkWhhhjWhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjgWhhhjWhMubah}(h]jbWah ](jjeh"]h$]h&]jj)jhuh1jhjWhMhjdWhhubj)}(hhh]h)}(h%reads one instance of an MCR registerh]h%reads one instance of an MCR register}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXhhubah}(h]h ]h"]h$]h&]uh1jhjdWhhhjWhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjXjjXjjjuh1jhhhjI<hNhNubj)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` register to read **Description** Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). Returns the value from a non-terminated instance of **reg**. **Context** Calls a function that takes and releases gt->mcr_lock.h](h)}(h**Parameters**h]j)}(hjXh]h Parameters}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hjXh]hstruct intel_gt *gt}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjXubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubj@)}(hhh]h)}(h GT structureh]h GT structure}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhMhjXubah}(h]h ]h"]h$]h&]uh1j?hjXubeh}(h]h ]h"]h$]h&]uh1jhjXhMhjXubj)}(h(``i915_mcr_reg_t reg`` register to read h](j$)}(h``i915_mcr_reg_t reg``h]j*)}(hjYh]hi915_mcr_reg_t reg}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjYubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubj@)}(hhh]h)}(hregister to readh]hregister to read}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMhjYubah}(h]h ]h"]h$]h&]uh1j?hjXubeh}(h]h ]h"]h$]h&]uh1jhjYhMhjXubeh}(h]h ]h"]h$]h&]uh1jhjXubh)}(h**Description**h]j)}(hj?Yh]h Description}(hjAYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=Yubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubh)}(hReads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating).h]hReads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn’t fused off or powered down by power gating).}(hjUYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubh)}(hmcr_lock.h]h6Calls a function that takes and releases gt->mcr_lock.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)intel_gt_mcr_get_ss_steering (C function)c.intel_gt_mcr_get_ss_steeringhNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hvvoid intel_gt_mcr_get_ss_steering (struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance)h]j)}(huvoid intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance)h](jn)}(hvoidh]hvoid}(hjYhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjYhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubj )}(h h]h }(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjYhhhjYhMubj)}(hintel_gt_mcr_get_ss_steeringh]j)}(hintel_gt_mcr_get_ss_steeringh]hintel_gt_mcr_get_ss_steering}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjYhhhjYhMubj8)}(hT(struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hj ZhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjZubj )}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjZubh)}(hhh]j)}(hintel_gth]hintel_gt}(hj'ZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$Zubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj)ZmodnameN classnameNjj)}j]j)}jjYsbc.intel_gt_mcr_get_ss_steeringasbuh1hhjZubj )}(h h]h }(hjGZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjZubj)}(hjh]h*}(hjUZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj)}(hgth]hgt}(hjbZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjZubj>)}(hunsigned int dssh](jn)}(hunsignedh]hunsigned}(hj{ZhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjwZubj )}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjwZubjn)}(hinth]hint}(hjZhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjwZubj )}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjwZubj)}(hdssh]hdss}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwZubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjZubj>)}(hunsigned int *grouph](jn)}(hunsignedh]hunsigned}(hjZhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjZubj )}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjZubjn)}(hinth]hint}(hjZhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjZubj )}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjZubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj)}(hgrouph]hgroup}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjZubj>)}(hunsigned int *instanceh](jn)}(hunsignedh]hunsigned}(hj*[hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj&[ubj )}(h h]h }(hj8[hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj&[ubjn)}(hinth]hint}(hjF[hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj&[ubj )}(h h]h }(hjT[hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj&[ubj)}(hjh]h*}(hjb[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&[ubj)}(hinstanceh]hinstance}(hjo[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&[ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjZubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjYhhhjYhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjYhhhjYhMubah}(h]jYah ](jjeh"]h$]h&]jj)jhuh1jhjYhMhjYhhubj)}(hhh]h)}(h,returns the group/instance steering for a SSh]h,returns the group/instance steering for a SS}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj[hhubah}(h]h ]h"]h$]h&]uh1jhjYhhhjYhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj[jj[jjjuh1jhhhjI<hNhNubj)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``unsigned int dss`` DSS ID to obtain steering for ``unsigned int *group`` pointer to storage for steering group ID ``unsigned int *instance`` pointer to storage for steering instance ID **Description** Returns the steering IDs (via the **group** and **instance** parameters) that correspond to a specific subslice/DSS ID.h](h)}(h**Parameters**h]j)}(hj[h]h Parameters}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj[ubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hj[h]hstruct intel_gt *gt}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj[ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj[ubj@)}(hhh]h)}(h GT structureh]h GT structure}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hMhj[ubah}(h]h ]h"]h$]h&]uh1j?hj[ubeh}(h]h ]h"]h$]h&]uh1jhj[hMhj[ubj)}(h3``unsigned int dss`` DSS ID to obtain steering for h](j$)}(h``unsigned int dss``h]j*)}(hj\h]hunsigned int dss}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj\ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj \ubj@)}(hhh]h)}(hDSS ID to obtain steering forh]hDSS ID to obtain steering for}(hj,\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(\hMhj)\ubah}(h]h ]h"]h$]h&]uh1j?hj \ubeh}(h]h ]h"]h$]h&]uh1jhj(\hMhj[ubj)}(hA``unsigned int *group`` pointer to storage for steering group ID h](j$)}(h``unsigned int *group``h]j*)}(hjL\h]hunsigned int *group}(hjN\hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjJ\ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjF\ubj@)}(hhh]h)}(h(pointer to storage for steering group IDh]h(pointer to storage for steering group ID}(hje\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhja\hMhjb\ubah}(h]h ]h"]h$]h&]uh1j?hjF\ubeh}(h]h ]h"]h$]h&]uh1jhja\hMhj[ubj)}(hG``unsigned int *instance`` pointer to storage for steering instance ID h](j$)}(h``unsigned int *instance``h]j*)}(hj\h]hunsigned int *instance}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj\ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj\ubj@)}(hhh]h)}(h+pointer to storage for steering instance IDh]h+pointer to storage for steering instance ID}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMhj\ubah}(h]h ]h"]h$]h&]uh1j?hj\ubeh}(h]h ]h"]h$]h&]uh1jhj\hMhj[ubeh}(h]h ]h"]h$]h&]uh1jhj[ubh)}(h**Description**h]j)}(hj\h]h Description}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj[ubh)}(hwReturns the steering IDs (via the **group** and **instance** parameters) that correspond to a specific subslice/DSS ID.h](h"Returns the steering IDs (via the }(hj\hhhNhNubj)}(h **group**h]hgroup}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh and }(hj\hhhNhNubj)}(h **instance**h]hinstance}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh; parameters) that correspond to a specific subslice/DSS ID.}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj[ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&intel_gt_mcr_wait_for_reg (C function)c.intel_gt_mcr_wait_for_reghNtauh1jhjI<hhhNhNubj)}(hhh](j)}(hint intel_gt_mcr_wait_for_reg (struct intel_gt *gt, i915_mcr_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms)h]j)}(hint intel_gt_mcr_wait_for_reg(struct intel_gt *gt, i915_mcr_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms)h](jn)}(hinth]hint}(hj)]hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj%]hhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM/ubj )}(h h]h }(hj8]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj%]hhhj7]hM/ubj)}(hintel_gt_mcr_wait_for_regh]j)}(hintel_gt_mcr_wait_for_regh]hintel_gt_mcr_wait_for_reg}(hjJ]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjF]ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj%]hhhj7]hM/ubj8)}(hz(struct intel_gt *gt, i915_mcr_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms)h](j>)}(hstruct intel_gt *gth](jD)}(hjGh]hstruct}(hjf]hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjb]ubj )}(h h]h }(hjs]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjb]ubh)}(hhh]j)}(hintel_gth]hintel_gt}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj]modnameN classnameNjj)}j]j)}jjL]sbc.intel_gt_mcr_wait_for_regasbuh1hhjb]ubj )}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjb]ubj)}(hjh]h*}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjb]ubj)}(hgth]hgt}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjb]ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj^]ubj>)}(hi915_mcr_reg_t regh](h)}(hhh]j)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj]modnameN classnameNjj)}j]j]c.intel_gt_mcr_wait_for_regasbuh1hhj]ubj )}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj]ubj)}(hregh]hreg}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj^]ubj>)}(hu32 maskh](h)}(hhh]j)}(hu32h]hu32}(hj#^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ^ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj%^modnameN classnameNjj)}j]j]c.intel_gt_mcr_wait_for_regasbuh1hhj^ubj )}(h h]h }(hjA^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubj)}(hmaskh]hmask}(hjO^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj^]ubj>)}(h u32 valueh](h)}(hhh]j)}(hu32h]hu32}(hjk^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjh^ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjm^modnameN classnameNjj)}j]j]c.intel_gt_mcr_wait_for_regasbuh1hhjd^ubj )}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjd^ubj)}(hvalueh]hvalue}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjd^ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj^]ubj>)}(hunsigned int fast_timeout_ush](jn)}(hunsignedh]hunsigned}(hj^hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj^ubj )}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubjn)}(hinth]hint}(hj^hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj^ubj )}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubj)}(hfast_timeout_ush]hfast_timeout_us}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj^]ubj>)}(hunsigned int slow_timeout_msh](jn)}(hunsignedh]hunsigned}(hj_hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj^ubj )}(h h]h }(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubjn)}(hinth]hint}(hj_hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj^ubj )}(h h]h }(hj+_hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubj)}(hslow_timeout_msh]hslow_timeout_ms}(hj9_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj^]ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj%]hhhj7]hM/ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj!]hhhj7]hM/ubah}(h]j]ah ](jjeh"]h$]h&]jj)jhuh1jhj7]hM/hj]hhubj)}(hhh]h)}(h.wait until MCR register matches expected stateh]h.wait until MCR register matches expected state}(hjc_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM/hj`_hhubah}(h]h ]h"]h$]h&]uh1jhj]hhhj7]hM/ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj{_jj{_jjjuh1jhhhjI<hNhNubj)}(hX **Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the register to read ``u32 mask`` mask to apply to register value ``u32 value`` value to wait for ``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait ``unsigned int slow_timeout_ms`` slow timeout in millisecond **Description** This routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until :: (intel_gt_mcr_read_any_fw(gt, reg) & mask) == value Otherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds. This function is basically an MCR-friendly version of __intel_wait_for_register_fw(). Generally this function will only be used on GAM registers which are a bit special --- although they're MCR registers, reads (e.g., waiting for status updates) are always directed to the primary instance. Note that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. **Context** Calls a function that takes and releases gt->mcr_lock **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]j)}(hj_h]h Parameters}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM3hj_ubj)}(hhh](j)}(h%``struct intel_gt *gt`` GT structure h](j$)}(h``struct intel_gt *gt``h]j*)}(hj_h]hstruct intel_gt *gt}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj_ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM0hj_ubj@)}(hhh]h)}(h GT structureh]h GT structure}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM0hj_ubah}(h]h ]h"]h$]h&]uh1j?hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM0hj_ubj)}(h,``i915_mcr_reg_t reg`` the register to read h](j$)}(h``i915_mcr_reg_t reg``h]j*)}(hj_h]hi915_mcr_reg_t reg}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj_ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM1hj_ubj@)}(hhh]h)}(hthe register to readh]hthe register to read}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM1hj_ubah}(h]h ]h"]h$]h&]uh1j?hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM1hj_ubj)}(h-``u32 mask`` mask to apply to register value h](j$)}(h ``u32 mask``h]j*)}(hj`h]hu32 mask}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj`ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM2hj`ubj@)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hj/`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+`hM2hj,`ubah}(h]h ]h"]h$]h&]uh1j?hj`ubeh}(h]h ]h"]h$]h&]uh1jhj+`hM2hj_ubj)}(h ``u32 value`` value to wait for h](j$)}(h ``u32 value``h]j*)}(hjO`h]h u32 value}(hjQ`hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjM`ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM3hjI`ubj@)}(hhh]h)}(hvalue to wait forh]hvalue to wait for}(hjh`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjd`hM3hje`ubah}(h]h ]h"]h$]h&]uh1j?hjI`ubeh}(h]h ]h"]h$]h&]uh1jhjd`hM3hj_ubj)}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j$)}(h ``unsigned int fast_timeout_us``h]j*)}(hj`h]hunsigned int fast_timeout_us}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj`ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM4hj`ubj@)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hM4hj`ubah}(h]h ]h"]h$]h&]uh1j?hj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hM4hj_ubj)}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j$)}(h ``unsigned int slow_timeout_ms``h]j*)}(hj`h]hunsigned int slow_timeout_ms}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj`ubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM5hj`ubj@)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hM5hj`ubah}(h]h ]h"]h$]h&]uh1j?hj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hM5hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_ubh)}(h**Description**h]j)}(hj`h]h Description}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM7hj_ubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hjahhhNhNubj)}(h**reg**h]hreg}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubh contains the expected }(hjahhhNhNubj)}(h **value**h]hvalue}(hj,ahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubh after applying the }(hjahhhNhNubj)}(h**mask**h]hmask}(hj>ahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubh, i.e. it waits until}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM6hj_ubjA#)}(h3(intel_gt_mcr_read_any_fw(gt, reg) & mask) == valueh]h3(intel_gt_mcr_read_any_fw(gt, reg) & mask) == value}hjWasbah}(h]h ]h"]h$]h&]j5j6uh1j@#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM9hj_ubh)}(hOtherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds.h](h'Otherwise, the wait will timeout after }(hjfahhhNhNubj)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hjnahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfaubh" milliseconds. For atomic context }(hjfahhhNhNubj)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfaubh must be zero and }(hjfahhhNhNubj)}(h**fast_timeout_us**h]hfast_timeout_us}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfaubh. must be not larger than 20,0000 microseconds.}(hjfahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM;hj_ubh)}(hX#This function is basically an MCR-friendly version of __intel_wait_for_register_fw(). Generally this function will only be used on GAM registers which are a bit special --- although they're MCR registers, reads (e.g., waiting for status updates) are always directed to the primary instance.h]hX%This function is basically an MCR-friendly version of __intel_wait_for_register_fw(). Generally this function will only be used on GAM registers which are a bit special --- although they’re MCR registers, reads (e.g., waiting for status updates) are always directed to the primary instance.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM?hj_ubh)}(hkNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits.h]hkNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMEhj_ubh)}(h **Context**h]j)}(hjah]hContext}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMHhj_ubh)}(h5Calls a function that takes and releases gt->mcr_lockh]h5Calls a function that takes and releases gt->mcr_lock}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMIhj_ubh)}(h **Return**h]j)}(hjah]hReturn}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMKhj_ubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:82: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMJhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjI<hhhNhNubeh}(h]"multicast-replicated-mcr-registersah ]h"]$multicast/replicated (mcr) registersah$]h&]uh1hhj8<hhhhhKMubeh}(h]gt-programmingah ]h"]gt programmingah$]h&]uh1hhhhhhhhKJubh)}(hhh](h)}(h(Memory Management and Command Submissionh]h(Memory Management and Command Submission}(hj1bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.bhhhhhKVubh)}(hUThis sections covers all things related to the GEM implementation in the i915 driver.h]hUThis sections covers all things related to the GEM implementation in the i915 driver.}(hj?bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj.bhhubh)}(hhh](h)}(hIntel GPU Basicsh]hIntel GPU Basics}(hjPbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMbhhhhhK\ubh)}(hBAn Intel GPU has multiple engines. There are several engine types:h]hBAn Intel GPU has multiple engines. There are several engine types:}(hj^bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjMbhhubj:)}(hhh](j:)}(hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.h]h)}(hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.h]hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.}(hjsbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjobubah}(h]h ]h"]h$]h&]uh1j:hjlbhhhhhNubj:)}(h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.h]h)}(h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.h]h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjbubah}(h]h ]h"]h$]h&]uh1j:hjlbhhhhhNubj:)}(h~Video Command Streamer. An engine used for video encoding and decoding. Also sometimes called 'BSD' in hardware documentation.h]h)}(h~Video Command Streamer. An engine used for video encoding and decoding. Also sometimes called 'BSD' in hardware documentation.h]hVideo Command Streamer. An engine used for video encoding and decoding. Also sometimes called ‘BSD’ in hardware documentation.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjbubah}(h]h ]h"]h$]h&]uh1j:hjlbhhhhhNubj:)}(hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called 'VEBOX' in hardware documentation.h]h)}(hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called 'VEBOX' in hardware documentation.h]hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called ‘VEBOX’ in hardware documentation.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjbubah}(h]h ]h"]h$]h&]uh1j:hjlbhhhhhNubj:)}(htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.h]h)}(htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.h]htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjbubah}(h]h ]h"]h$]h&]uh1j:hjlbhhhhhNubj:)}(hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication. h]h)}(hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication.h]hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjbubah}(h]h ]h"]h$]h&]uh1j:hjlbhhhhhNubeh}(h]h ]h"]h$]h&]j;j;uh1j:hhhK`hjMbhhubh)}(hXThe Intel GPU family is a family of integrated GPU's using Unified Memory Access. For having the GPU "do work", user space will feed the GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will instruct the GPU to perform work (for example rendering) and that work needs memory from which to read and memory to which to write. All memory is encapsulated within GEM buffer objects (usually created with the ioctl `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU to create will also list all GEM buffer objects that the batchbuffer reads and/or writes. For implementation details of memory management see `GEM BO Management Implementation Details`_.h](hThe Intel GPU family is a family of integrated GPU’s using Unified Memory Access. For having the GPU “do work”, user space will feed the GPU batch buffers via one of the ioctls }(hjchhhNhNubhtitle_reference)}(h `DRM_IOCTL_I915_GEM_EXECBUFFER2`h]hDRM_IOCTL_I915_GEM_EXECBUFFER2}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1j chjcubh or }(hjchhhNhNubjc)}(h#`DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`h]h!DRM_IOCTL_I915_GEM_EXECBUFFER2_WR}(hj!chhhNhNubah}(h]h ]h"]h$]h&]uh1j chjcubh. Most such batchbuffers will instruct the GPU to perform work (for example rendering) and that work needs memory from which to read and memory to which to write. All memory is encapsulated within GEM buffer objects (usually created with the ioctl }(hjchhhNhNubjc)}(h`DRM_IOCTL_I915_GEM_CREATE`h]hDRM_IOCTL_I915_GEM_CREATE}(hj3chhhNhNubah}(h]h ]h"]h$]h&]uh1j chjcubh). An ioctl providing a batchbuffer for the GPU to create will also list all GEM buffer objects that the batchbuffer reads and/or writes. For implementation details of memory management see }(hjchhhNhNubj5)}(h+`GEM BO Management Implementation Details`_h]h(GEM BO Management Implementation Details}(hjEchhhNhNubah}(h]h ]h"]h$]h&]name(GEM BO Management Implementation Detailsh(gem-bo-management-implementation-detailsuh1j5hjcj7;Kubh.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKohjMbhhubh)}(hXThe i915 driver allows user space to create a context via the ioctl `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit integer. Such a context should be viewed by user-space as -loosely- analogous to the idea of a CPU process of an operating system. The i915 driver guarantees that commands issued to a fixed context are to be executed so that writes of a previously issued command are seen by reads of following commands. Actions issued between different contexts (even if from the same file descriptor) are NOT given that guarantee and the only way to synchronize across contexts (even from the same file descriptor) is through the use of fences. At least as far back as Gen4, also have that a context carries with it a GPU HW context; the HW context is essentially (most of at least) the state of a GPU. In addition to the ordering guarantees, the kernel will restore GPU state via HW context when commands are issued to a context, this saves user space the need to restore (most of at least) the GPU state at the start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use with the command.h](hDThe i915 driver allows user space to create a context via the ioctl }(hj`chhhNhNubjc)}(h#`DRM_IOCTL_I915_GEM_CONTEXT_CREATE`h]h!DRM_IOCTL_I915_GEM_CONTEXT_CREATE}(hjhchhhNhNubah}(h]h ]h"]h$]h&]uh1j chj`cubhXl which is identified by a 32-bit integer. Such a context should be viewed by user-space as -loosely- analogous to the idea of a CPU process of an operating system. The i915 driver guarantees that commands issued to a fixed context are to be executed so that writes of a previously issued command are seen by reads of following commands. Actions issued between different contexts (even if from the same file descriptor) are NOT given that guarantee and the only way to synchronize across contexts (even from the same file descriptor) is through the use of fences. At least as far back as Gen4, also have that a context carries with it a GPU HW context; the HW context is essentially (most of at least) the state of a GPU. In addition to the ordering guarantees, the kernel will restore GPU state via HW context when commands are issued to a context, this saves user space the need to restore (most of at least) the GPU state at the start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use with the command.}(hj`chhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK{hjMbhhubh)}(hXThe GPU has its own memory management and address space. The kernel driver maintains the memory translation table for the GPU. For older GPUs (i.e. those before Gen8), there is a single global such translation table, a global Graphics Translation Table (GTT). For newer generation GPUs each context has its own translation table, called Per-Process Graphics Translation Table (PPGTT). Of important note, is that although PPGTT is named per-process it is actually per context. When user space submits a batchbuffer, the kernel walks the list of GEM buffer objects used by the batchbuffer and guarantees that not only is the memory of each such GEM buffer object resident but it is also present in the (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, then it is given an address. Two consequences of this are: the kernel needs to edit the batchbuffer submitted to write the correct value of the GPU address when a GEM BO is assigned a GPU address and the kernel might evict a different GEM BO from the (PP)GTT to make address room for another GEM BO. Consequently, the ioctls submitting a batchbuffer for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation.h]hXThe GPU has its own memory management and address space. The kernel driver maintains the memory translation table for the GPU. For older GPUs (i.e. those before Gen8), there is a single global such translation table, a global Graphics Translation Table (GTT). For newer generation GPUs each context has its own translation table, called Per-Process Graphics Translation Table (PPGTT). Of important note, is that although PPGTT is named per-process it is actually per context. When user space submits a batchbuffer, the kernel walks the list of GEM buffer objects used by the batchbuffer and guarantees that not only is the memory of each such GEM buffer object resident but it is also present in the (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, then it is given an address. Two consequences of this are: the kernel needs to edit the batchbuffer submitted to write the correct value of the GPU address when a GEM BO is assigned a GPU address and the kernel might evict a different GEM BO from the (PP)GTT to make address room for another GEM BO. Consequently, the ioctls submitting a batchbuffer for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjMbhhubeh}(h]intel-gpu-basicsah ]h"]intel gpu basicsah$]h&]uh1hhj.bhhhhhK\ubh)}(hhh](h)}(hLocking Guidelinesh]hLocking Guidelines}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchhhhhKubhnote)}(hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.h]h)}(hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.h]hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjcubah}(h]h ]h"]h$]h&]uh1jchjchhhhhNubj;)}(hhh](j:)}(hqAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed. h]h)}(hpAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed.h]hpAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjcubah}(h]h ]h"]h$]h&]uh1j:hjchhhhhNubj:)}(hdma_resv will be the outermost lock (when needed) and ww_acquire_ctx is to be hoisted at highest level and passed down within i915_gem_ctx in the call chain h]h)}(hdma_resv will be the outermost lock (when needed) and ww_acquire_ctx is to be hoisted at highest level and passed down within i915_gem_ctx in the call chainh]hdma_resv will be the outermost lock (when needed) and ww_acquire_ctx is to be hoisted at highest level and passed down within i915_gem_ctx in the call chain}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjcubah}(h]h ]h"]h$]h&]uh1j:hjchhhhhNubj:)}(hkWhile holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowed h]h)}(hjWhile holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowedh]hjWhile holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowed}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjcubah}(h]h ]h"]h$]h&]uh1j:hjchhhhhNubj:)}(hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations. h]h)}(hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations.h]hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj dubah}(h]h ]h"]h$]h&]uh1j:hjchhhhhNubj:)}(h\The suggestion for lru/memory managers locks is that they are small enough to be spinlocks. h]h)}(h[The suggestion for lru/memory managers locks is that they are small enough to be spinlocks.h]h[The suggestion for lru/memory managers locks is that they are small enough to be spinlocks.}(hj(dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj$dubah}(h]h ]h"]h$]h&]uh1j:hjchhhhhNubj:)}(h]All features need to come with exhaustive kernel selftests and/or IGT tests when appropriate h]h)}(h\All features need to come with exhaustive kernel selftests and/or IGT tests when appropriateh]h\All features need to come with exhaustive kernel selftests and/or IGT tests when appropriate}(hj@dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj)}(hstruct i915_address_space *vmh](jD)}(hjGh]hstruct}(hjkehhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjgeubj )}(h h]h }(hjxehhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjgeubh)}(hhh]j)}(hi915_address_spaceh]hi915_address_space}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjemodnameN classnameNjj)}j]j)}jjQesbc.i915_gem_evict_somethingasbuh1hhjgeubj )}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjgeubj)}(hjh]h*}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgeubj)}(hvmh]hvm}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgeubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjceubj>)}(hstruct i915_gem_ww_ctx *wwh](jD)}(hjGh]hstruct}(hjehhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjeubj )}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjeubh)}(hhh]j)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjemodnameN classnameNjj)}j]jec.i915_gem_evict_somethingasbuh1hhjeubj )}(h h]h }(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjeubj)}(hjh]h*}(hj'fhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj)}(hwwh]hww}(hj4fhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjceubj>)}(h u64 min_sizeh](h)}(hhh]j)}(hu64h]hu64}(hjPfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMfubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjRfmodnameN classnameNjj)}j]jec.i915_gem_evict_somethingasbuh1hhjIfubj )}(h h]h }(hjnfhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjIfubj)}(hmin_sizeh]hmin_size}(hj|fhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIfubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjceubj>)}(h u64 alignmenth](h)}(hhh]j)}(hu64h]hu64}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjfmodnameN classnameNjj)}j]jec.i915_gem_evict_somethingasbuh1hhjfubj )}(h h]h }(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjfubj)}(h alignmenth]h alignment}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjceubj>)}(hunsigned long colorh](jn)}(hunsignedh]hunsigned}(hjfhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjfubj )}(h h]h }(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjfubjn)}(hlongh]hlong}(hjfhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjfubj )}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjfubj)}(hcolorh]hcolor}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjceubj>)}(h u64 starth](h)}(hhh]j)}(hu64h]hu64}(hj1ghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.gubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj3gmodnameN classnameNjj)}j]jec.i915_gem_evict_somethingasbuh1hhj*gubj )}(h h]h }(hjOghhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj*gubj)}(hstarth]hstart}(hj]ghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*gubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjceubj>)}(hu64 endh](h)}(hhh]j)}(hu64h]hu64}(hjyghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvgubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj{gmodnameN classnameNjj)}j]jec.i915_gem_evict_somethingasbuh1hhjrgubj )}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjrgubj)}(hendh]hend}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrgubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjceubj>)}(hunsigned flagsh](jn)}(hunsignedh]hunsigned}(hjghhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjgubj )}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjgubj)}(hflagsh]hflags}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjceubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj*ehhhjpages_pin_count does not protect against eviction. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]j)}(hj&hh]h Parameters}(hj(hhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$hubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj hubj)}(hhh](j)}(h>``struct i915_address_space *vm`` address space to evict from h](j$)}(h!``struct i915_address_space *vm``h]j*)}(hjEhh]hstruct i915_address_space *vm}(hjGhhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjChubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chK}hj?hubj@)}(hhh]h)}(haddress space to evict fromh]haddress space to evict from}(hj^hhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhK}hj[hubah}(h]h ]h"]h$]h&]uh1j?hj?hubeh}(h]h ]h"]h$]h&]uh1jhjZhhK}hjihKhj?iubah}(h]h ]h"]h$]h&]uh1j?hj#iubeh}(h]h ]h"]h$]h&]uh1jhj>ihKhjpages_pin_count does not protect against eviction.h]hSince this function is only used to free up virtual address space it only ignores pinned vmas, and not object where the backing storage itself is pinned. Hence obj->pages_pin_count does not protect against eviction.}(hjCjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj hubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hjRjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj hubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjdhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$i915_gem_evict_for_node (C function)c.i915_gem_evict_for_nodehNtauh1jhjdhhhNhNubj)}(hhh](j)}(hint i915_gem_evict_for_node (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h]j)}(hint i915_gem_evict_for_node(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h](jn)}(hinth]hint}(hjjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj}jhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chM=ubj )}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj}jhhhjjhM=ubj)}(hi915_gem_evict_for_nodeh]j)}(hi915_gem_evict_for_nodeh]hi915_gem_evict_for_node}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj}jhhhjjhM=ubj8)}(hk(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h](j>)}(hstruct i915_address_space *vmh](jD)}(hjGh]hstruct}(hjjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjjubj )}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjjubh)}(hhh]j)}(hi915_address_spaceh]hi915_address_space}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjjmodnameN classnameNjj)}j]j)}jjjsbc.i915_gem_evict_for_nodeasbuh1hhjjubj )}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjjubj)}(hjh]h*}(hj khhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj)}(hvmh]hvm}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjjubj>)}(hstruct i915_gem_ww_ctx *wwh](jD)}(hjGh]hstruct}(hj0khhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj,kubj )}(h h]h }(hj=khhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj,kubh)}(hhh]j)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjNkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKkubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjPkmodnameN classnameNjj)}j]jjc.i915_gem_evict_for_nodeasbuh1hhj,kubj )}(h h]h }(hjlkhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj,kubj)}(hjh]h*}(hjzkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,kubj)}(hwwh]hww}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,kubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjjubj>)}(hstruct drm_mm_node *targeth](jD)}(hjGh]hstruct}(hjkhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjkubj )}(h h]h }(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjkubh)}(hhh]j)}(h drm_mm_nodeh]h drm_mm_node}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjkmodnameN classnameNjj)}j]jjc.i915_gem_evict_for_nodeasbuh1hhjkubj )}(h h]h }(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjkubj)}(hjh]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubj)}(htargeth]htarget}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjjubj>)}(hunsigned int flagsh](jn)}(hunsignedh]hunsigned}(hjlhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj lubj )}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj lubjn)}(hinth]hint}(hj,lhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj lubj )}(h h]h }(hj:lhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj lubj)}(hflagsh]hflags}(hjHlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj lubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj}jhhhjjhM=ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjyjhhhjjhM=ubah}(h]jtjah ](jjeh"]h$]h&]jj)jhuh1jhjjhM=hjvjhhubj)}(hhh]h)}(h-Evict vmas to make room for binding a new oneh]h-Evict vmas to make room for binding a new one}(hjrlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chM=hjolhhubah}(h]h ]h"]h$]h&]uh1jhjvjhhhjjhM=ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjljjljjjuh1jhhhjdhNhNubj)}(hX**Parameters** ``struct i915_address_space *vm`` address space to evict from ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *target`` range (and color) to evict for ``unsigned int flags`` additional flags to control the eviction algorithm **Description** This function will try to evict vmas that overlap the target node. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]j)}(hjlh]h Parameters}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMAhjlubj)}(hhh](j)}(h>``struct i915_address_space *vm`` address space to evict from h](j$)}(h!``struct i915_address_space *vm``h]j*)}(hjlh]hstruct i915_address_space *vm}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjlubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chM>hjlubj@)}(hhh]h)}(haddress space to evict fromh]haddress space to evict from}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhM>hjlubah}(h]h ]h"]h$]h&]uh1j?hjlubeh}(h]h ]h"]h$]h&]uh1jhjlhM>hjlubj)}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j$)}(h``struct i915_gem_ww_ctx *ww``h]j*)}(hjlh]hstruct i915_gem_ww_ctx *ww}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjlubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chM?hjlubj@)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhM?hjmubah}(h]h ]h"]h$]h&]uh1j?hjlubeh}(h]h ]h"]h$]h&]uh1jhjmhM?hjlubj)}(h>``struct drm_mm_node *target`` range (and color) to evict for h](j$)}(h``struct drm_mm_node *target``h]j*)}(hj%mh]hstruct drm_mm_node *target}(hj'mhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj#mubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chM@hjmubj@)}(hhh]h)}(hrange (and color) to evict forh]hrange (and color) to evict for}(hj>mhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:mhM@hj;mubah}(h]h ]h"]h$]h&]uh1j?hjmubeh}(h]h ]h"]h$]h&]uh1jhj:mhM@hjlubj)}(hJ``unsigned int flags`` additional flags to control the eviction algorithm h](j$)}(h``unsigned int flags``h]j*)}(hj^mh]hunsigned int flags}(hj`mhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj\mubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMAhjXmubj@)}(hhh]h)}(h2additional flags to control the eviction algorithmh]h2additional flags to control the eviction algorithm}(hjwmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjsmhMAhjtmubah}(h]h ]h"]h$]h&]uh1j?hjXmubeh}(h]h ]h"]h$]h&]uh1jhjsmhMAhjlubeh}(h]h ]h"]h$]h&]uh1jhjlubh)}(h**Description**h]j)}(hjmh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMChjlubh)}(hBThis function will try to evict vmas that overlap the target node.h]hBThis function will try to evict vmas that overlap the target node.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMBhjlubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMDhjlubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjdhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_gem_evict_vm (C function)c.i915_gem_evict_vmhNtauh1jhjdhhhNhNubj)}(hhh](j)}(hwint i915_gem_evict_vm (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h]j)}(hvint i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h](jn)}(hinth]hint}(hjmhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjmhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMubj )}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjmhhhjmhMubj)}(hi915_gem_evict_vmh]j)}(hi915_gem_evict_vmh]hi915_gem_evict_vm}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj nubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjmhhhjmhMubj8)}(ha(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h](j>)}(hstruct i915_address_space *vmh](jD)}(hjGh]hstruct}(hj*nhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj&nubj )}(h h]h }(hj7nhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj&nubh)}(hhh]j)}(hi915_address_spaceh]hi915_address_space}(hjHnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEnubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjJnmodnameN classnameNjj)}j]j)}jjnsbc.i915_gem_evict_vmasbuh1hhj&nubj )}(h h]h }(hjhnhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj&nubj)}(hjh]h*}(hjvnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&nubj)}(hvmh]hvm}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&nubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj"nubj>)}(hstruct i915_gem_ww_ctx *wwh](jD)}(hjGh]hstruct}(hjnhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjnubj )}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjnubh)}(hhh]j)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjnmodnameN classnameNjj)}j]jdnc.i915_gem_evict_vmasbuh1hhjnubj )}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjnubj)}(hjh]h*}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(hwwh]hww}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj"nubj>)}(h$struct drm_i915_gem_object **busy_boh](jD)}(hjGh]hstruct}(hj ohhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjoubj )}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjoubh)}(hhh]j)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hj*ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'oubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj,omodnameN classnameNjj)}j]jdnc.i915_gem_evict_vmasbuh1hhjoubj )}(h h]h }(hjHohhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjoubj)}(hjh]h*}(hjVohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hjh]h*}(hjcohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hbusy_boh]hbusy_bo}(hjpohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj"nubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjmhhhjmhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjmhhhjmhMubah}(h]jmah ](jjeh"]h$]h&]jj)jhuh1jhjmhMhjmhhubj)}(hhh]h)}(hEvict all idle vmas from a vmh]hEvict all idle vmas from a vm}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjohhubah}(h]h ]h"]h$]h&]uh1jhjmhhhjmhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjojjojjjuh1jhhhjdhNhNubj)}(hXm**Parameters** ``struct i915_address_space *vm`` Address space to cleanse ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well. ``struct drm_i915_gem_object **busy_bo`` Optional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object. **Description** This function evicts all vmas from a vm. This is used by the execbuf code as a last-ditch effort to defragment the address space. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]j)}(hjoh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubj)}(hhh](j)}(h;``struct i915_address_space *vm`` Address space to cleanse h](j$)}(h!``struct i915_address_space *vm``h]j*)}(hjoh]hstruct i915_address_space *vm}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjoubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubj@)}(hhh]h)}(hAddress space to cleanseh]hAddress space to cleanse}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohMhjoubah}(h]h ]h"]h$]h&]uh1j?hjoubeh}(h]h ]h"]h$]h&]uh1jhjohMhjoubj)}(h``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well. h](j$)}(h``struct i915_gem_ww_ctx *ww``h]j*)}(hjph]hstruct i915_gem_ww_ctx *ww}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjpubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjpubj@)}(hhh]h)}(hxAn optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well.h]hzAn optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma’s locked by the ww as well.}(hj-phhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj*pubah}(h]h ]h"]h$]h&]uh1j?hjpubeh}(h]h ]h"]h$]h&]uh1jhj)phMhjoubj)}(hX|``struct drm_i915_gem_object **busy_bo`` Optional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object. h](j$)}(h(``struct drm_i915_gem_object **busy_bo``h]j*)}(hjNph]h$struct drm_i915_gem_object **busy_bo}(hjPphhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjLpubah}(h]h ]h"]h$]h&]uh1j#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjHpubj@)}(hhh]h)}(hXROptional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object.h](hOptional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then }(hjgphhhNhNubj)}(h **busy_bo**h]hbusy_bo}(hjophhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgpubh will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object.}(hjgphhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjdpubah}(h]h ]h"]h$]h&]uh1j?hjHpubeh}(h]h ]h"]h$]h&]uh1jhjcphMhjoubeh}(h]h ]h"]h$]h&]uh1jhjoubh)}(h**Description**h]j)}(hjph]h Description}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubh)}(h(This function evicts all vmas from a vm.h]h(This function evicts all vmas from a vm.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubh)}(hXThis is used by the execbuf code as a last-ditch effort to defragment the address space.h]hXThis is used by the execbuf code as a last-ditch effort to defragment the address space.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjdhhhNhNubeh}(h]buffer-object-evictionah ]h"]buffer object evictionah$]h&]uh1hhj.bhhhhhKubh)}(hhh](h)}(hBuffer Object Memory Shrinkingh]hBuffer Object Memory Shrinking}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphhhhhKubh)}(hXThis section documents the interface function for shrinking memory usage of buffer object caches. Shrinking is used to make main memory available. Note that this is mostly orthogonal to evicting buffer objects, which has the goal to make space in gpu virtual address spaces.h]hXThis section documents the interface function for shrinking memory usage of buffer object caches. Shrinking is used to make main memory available. Note that this is mostly orthogonal to evicting buffer objects, which has the goal to make space in gpu virtual address spaces.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjphhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_gem_shrink (C function)c.i915_gem_shrinkhNtauh1jhjphhhNhNubj)}(hhh](j)}(hunsigned long i915_gem_shrink (struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h]j)}(hunsigned long i915_gem_shrink(struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h](jn)}(hunsignedh]hunsigned}(hj&qhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj"qhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKNubj )}(h h]h }(hj5qhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj"qhhhj4qhKNubjn)}(hlongh]hlong}(hjCqhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj"qhhhj4qhKNubj )}(h h]h }(hjQqhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj"qhhhj4qhKNubj)}(hi915_gem_shrinkh]j)}(hi915_gem_shrinkh]hi915_gem_shrink}(hjcqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_qubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj"qhhhj4qhKNubj8)}(h(struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h](j>)}(hstruct i915_gem_ww_ctx *wwh](jD)}(hjGh]hstruct}(hjqhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj{qubj )}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj{qubh)}(hhh]j)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjqmodnameN classnameNjj)}j]j)}jjeqsbc.i915_gem_shrinkasbuh1hhj{qubj )}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj{qubj)}(hjh]h*}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{qubj)}(hwwh]hww}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{qubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjwqubj>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hjqhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjqubj )}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjqubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj rubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjrmodnameN classnameNjj)}j]jqc.i915_gem_shrinkasbuh1hhjqubj )}(h h]h }(hj-rhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjqubj)}(hjh]h*}(hj;rhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(hi915h]hi915}(hjHrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjwqubj>)}(hunsigned long targeth](jn)}(hunsignedh]hunsigned}(hjarhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj]rubj )}(h h]h }(hjorhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj]rubjn)}(hlongh]hlong}(hj}rhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj]rubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj]rubj)}(htargeth]htarget}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]rubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjwqubj>)}(hunsigned long *nr_scannedh](jn)}(hunsignedh]hunsigned}(hjrhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjrubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjrubjn)}(hlongh]hlong}(hjrhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjrubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjrubj)}(hjh]h*}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(h nr_scannedh]h nr_scanned}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjwqubj>)}(hunsigned int shrinkh](jn)}(hunsignedh]hunsigned}(hjshhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj subj )}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj subjn)}(hinth]hint}(hj,shhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj subj )}(h h]h }(hj:shhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj subj)}(hshrinkh]hshrink}(hjHshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj subeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjwqubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj"qhhhj4qhKNubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjqhhhj4qhKNubah}(h]jqah ](jjeh"]h$]h&]jj)jhuh1jhj4qhKNhjqhhubj)}(hhh]h)}(hShrink buffer object cachesh]hShrink buffer object caches}(hjrshhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKNhjoshhubah}(h]h ]h"]h$]h&]uh1jhjqhhhj4qhKNubeh}(h]h ](jfunctioneh"]h$]h&]jjjjsjjsjjjuh1jhhhjphNhNubj)}(hX **Parameters** ``struct i915_gem_ww_ctx *ww`` i915 gem ww acquire ctx, or NULL ``struct drm_i915_private *i915`` i915 device ``unsigned long target`` amount of memory to make available, in pages ``unsigned long *nr_scanned`` optional output for number of pages scanned (incremental) ``unsigned int shrink`` control flags for selecting cache types **Description** This function is the main interface to the shrinker. It will try to release up to **target** pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with **flags**. This is e.g. useful when purgeable objects should be removed from caches preferentially. Note that it's not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all(). Also note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object. **Return** The number of pages of backing storage actually released.h](h)}(h**Parameters**h]j)}(hjsh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKRhjsubj)}(hhh](j)}(h@``struct i915_gem_ww_ctx *ww`` i915 gem ww acquire ctx, or NULL h](j$)}(h``struct i915_gem_ww_ctx *ww``h]j*)}(hjsh]hstruct i915_gem_ww_ctx *ww}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjsubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKOhjsubj@)}(hhh]h)}(h i915 gem ww acquire ctx, or NULLh]h i915 gem ww acquire ctx, or NULL}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshKOhjsubah}(h]h ]h"]h$]h&]uh1j?hjsubeh}(h]h ]h"]h$]h&]uh1jhjshKOhjsubj)}(h.``struct drm_i915_private *i915`` i915 device h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hjsh]hstruct drm_i915_private *i915}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjsubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKPhjsubj@)}(hhh]h)}(h i915 deviceh]h i915 device}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthKPhjtubah}(h]h ]h"]h$]h&]uh1j?hjsubeh}(h]h ]h"]h$]h&]uh1jhjthKPhjsubj)}(hF``unsigned long target`` amount of memory to make available, in pages h](j$)}(h``unsigned long target``h]j*)}(hj%th]hunsigned long target}(hj'thhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj#tubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKQhjtubj@)}(hhh]h)}(h,amount of memory to make available, in pagesh]h,amount of memory to make available, in pages}(hj>thhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:thKQhj;tubah}(h]h ]h"]h$]h&]uh1j?hjtubeh}(h]h ]h"]h$]h&]uh1jhj:thKQhjsubj)}(hX``unsigned long *nr_scanned`` optional output for number of pages scanned (incremental) h](j$)}(h``unsigned long *nr_scanned``h]j*)}(hj^th]hunsigned long *nr_scanned}(hj`thhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj\tubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKRhjXtubj@)}(hhh]h)}(h9optional output for number of pages scanned (incremental)h]h9optional output for number of pages scanned (incremental)}(hjwthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjsthKRhjttubah}(h]h ]h"]h$]h&]uh1j?hjXtubeh}(h]h ]h"]h$]h&]uh1jhjsthKRhjsubj)}(h@``unsigned int shrink`` control flags for selecting cache types h](j$)}(h``unsigned int shrink``h]j*)}(hjth]hunsigned int shrink}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjtubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKShjtubj@)}(hhh]h)}(h'control flags for selecting cache typesh]h'control flags for selecting cache types}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthKShjtubah}(h]h ]h"]h$]h&]uh1j?hjtubeh}(h]h ]h"]h$]h&]uh1jhjthKShjsubeh}(h]h ]h"]h$]h&]uh1jhjsubh)}(h**Description**h]j)}(hjth]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKUhjsubh)}(hX,This function is the main interface to the shrinker. It will try to release up to **target** pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with **flags**. This is e.g. useful when purgeable objects should be removed from caches preferentially.h](hRThis function is the main interface to the shrinker. It will try to release up to }(hjthhhNhNubj)}(h **target**h]htarget}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubhm pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with }(hjthhhNhNubj)}(h **flags**h]hflags}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubhZ. This is e.g. useful when purgeable objects should be removed from caches preferentially.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKThjsubh)}(hX~Note that it's not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all().h]hXNote that it’s not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all().}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKYhjsubh)}(hAlso note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object.h]hAlso note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object.}(hj*uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chK_hjsubh)}(h **Return**h]j)}(hj;uh]hReturn}(hj=uhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9uubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKchjsubh)}(h9The number of pages of backing storage actually released.h]h9The number of pages of backing storage actually released.}(hjQuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKdhjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j i915_gem_shrink_all (C function)c.i915_gem_shrink_allhNtauh1jhjphhhNhNubj)}(hhh](j)}(hAunsigned long i915_gem_shrink_all (struct drm_i915_private *i915)h]j)}(h@unsigned long i915_gem_shrink_all(struct drm_i915_private *i915)h](jn)}(hunsignedh]hunsigned}(hjuhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj|uhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMubj )}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj|uhhhjuhMubjn)}(hlongh]hlong}(hjuhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj|uhhhjuhMubj )}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj|uhhhjuhMubj)}(hi915_gem_shrink_allh]j)}(hi915_gem_shrink_allh]hi915_gem_shrink_all}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj|uhhhjuhMubj8)}(h(struct drm_i915_private *i915)h]j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hjuhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjuubj )}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjuubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjumodnameN classnameNjj)}j]j)}jjusbc.i915_gem_shrink_allasbuh1hhjuubj )}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjuubj)}(hjh]h*}(hj%vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubj)}(hi915h]hi915}(hj2vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjuubah}(h]h ]h"]h$]h&]j5j6uh1j7hj|uhhhjuhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjxuhhhjuhMubah}(h]jsuah ](jjeh"]h$]h&]jj)jhuh1jhjuhMhjuuhhubj)}(hhh]h)}(h&Shrink buffer object caches completelyh]h&Shrink buffer object caches completely}(hj\vhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjYvhhubah}(h]h ]h"]h$]h&]uh1jhjuuhhhjuhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjtvjjtvjjjuh1jhhhjphNhNubj)}(hX**Parameters** ``struct drm_i915_private *i915`` i915 device **Description** This is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects. This should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out. **Return** The number of pages of backing storage actually released.h](h)}(h**Parameters**h]j)}(hj~vh]h Parameters}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|vubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM hjxvubj)}(hhh]j)}(h.``struct drm_i915_private *i915`` i915 device h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hjvh]hstruct drm_i915_private *i915}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjvubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjvubj@)}(hhh]h)}(h i915 deviceh]h i915 device}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjvubah}(h]h ]h"]h$]h&]uh1j?hjvubeh}(h]h ]h"]h$]h&]uh1jhjvhMhjvubah}(h]h ]h"]h$]h&]uh1jhjxvubh)}(h**Description**h]j)}(hjvh]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM hjxvubh)}(hThis is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects.h]hThis is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjxvubh)}(hThis should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out.h]hThis should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM hjxvubh)}(h **Return**h]j)}(hjwh]hReturn}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj wubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjxvubh)}(h9The number of pages of backing storage actually released.h]h9The number of pages of backing storage actually released.}(hj$whhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjxvubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.i915_gem_object_make_unshrinkable (C function)#c.i915_gem_object_make_unshrinkablehNtauh1jhjphhhNhNubj)}(hhh](j)}(hHvoid i915_gem_object_make_unshrinkable (struct drm_i915_gem_object *obj)h]j)}(hGvoid i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj)h](jn)}(hvoidh]hvoid}(hjSwhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjOwhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMubj )}(h h]h }(hjbwhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjOwhhhjawhMubj)}(h!i915_gem_object_make_unshrinkableh]j)}(h!i915_gem_object_make_unshrinkableh]h!i915_gem_object_make_unshrinkable}(hjtwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpwubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjOwhhhjawhMubj8)}(h!(struct drm_i915_gem_object *obj)h]j>)}(hstruct drm_i915_gem_object *objh](jD)}(hjGh]hstruct}(hjwhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjwubj )}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjwubh)}(hhh]j)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjwmodnameN classnameNjj)}j]j)}jjvwsb#c.i915_gem_object_make_unshrinkableasbuh1hhjwubj )}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjwubj)}(hjh]h*}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubj)}(hobjh]hobj}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjwubah}(h]h ]h"]h$]h&]j5j6uh1j7hjOwhhhjawhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjKwhhhjawhMubah}(h]jFwah ](jjeh"]h$]h&]jj)jhuh1jhjawhMhjHwhhubj)}(hhh]h)}(hHide the object from the shrinker. By default all object types that support shrinking(see IS_SHRINKABLE), will also make the object visible to the shrinker after allocating the system memory pages.h]hHide the object from the shrinker. By default all object types that support shrinking(see IS_SHRINKABLE), will also make the object visible to the shrinker after allocating the system memory pages.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjxhhubah}(h]h ]h"]h$]h&]uh1jhjHwhhhjawhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj+xjj+xjjjuh1jhhhjphNhNubj)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** This is typically used for special kernel internal objects that can't be easily processed by the shrinker, like if they are perma-pinned.h](h)}(h**Parameters**h]j)}(hj5xh]h Parameters}(hj7xhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3xubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj/xubj)}(hhh]j)}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j$)}(h#``struct drm_i915_gem_object *obj``h]j*)}(hjTxh]hstruct drm_i915_gem_object *obj}(hjVxhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjRxubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjNxubj@)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hjmxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjixhMhjjxubah}(h]h ]h"]h$]h&]uh1j?hjNxubeh}(h]h ]h"]h$]h&]uh1jhjixhMhjKxubah}(h]h ]h"]h$]h&]uh1jhj/xubh)}(h**Description**h]j)}(hjxh]h Description}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj/xubh)}(hThis is typically used for special kernel internal objects that can't be easily processed by the shrinker, like if they are perma-pinned.h]hThis is typically used for special kernel internal objects that can’t be easily processed by the shrinker, like if they are perma-pinned.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj/xubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.__i915_gem_object_make_shrinkable (C function)#c.__i915_gem_object_make_shrinkablehNtauh1jhjphhhNhNubj)}(hhh](j)}(hHvoid __i915_gem_object_make_shrinkable (struct drm_i915_gem_object *obj)h]j)}(hGvoid __i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj)h](jn)}(hvoidh]hvoid}(hjxhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjxhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMubj )}(h h]h }(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjxhhhjxhMubj)}(h!__i915_gem_object_make_shrinkableh]j)}(h!__i915_gem_object_make_shrinkableh]h!__i915_gem_object_make_shrinkable}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjxhhhjxhMubj8)}(h!(struct drm_i915_gem_object *obj)h]j>)}(hstruct drm_i915_gem_object *objh](jD)}(hjGh]hstruct}(hjyhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj yubj )}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj yubh)}(hhh]j)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hj/yhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,yubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj1ymodnameN classnameNjj)}j]j)}jjxsb#c.__i915_gem_object_make_shrinkableasbuh1hhj yubj )}(h h]h }(hjOyhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj yubj)}(hjh]h*}(hj]yhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj yubj)}(hobjh]hobj}(hjjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj yubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj yubah}(h]h ]h"]h$]h&]j5j6uh1j7hjxhhhjxhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjxhhhjxhMubah}(h]jxah ](jjeh"]h$]h&]jj)jhuh1jhjxhMhjxhhubj)}(hhh]h)}(hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.h]hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjyhhubah}(h]h ]h"]h$]h&]uh1jhjxhhhjxhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjyjjyjjjuh1jhhhjphNhNubj)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** DO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h](h)}(h**Parameters**h]j)}(hjyh]h Parameters}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjyubj)}(hhh]j)}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j$)}(h#``struct drm_i915_gem_object *obj``h]j*)}(hjyh]hstruct drm_i915_gem_object *obj}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjyubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjyubj@)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhMhjyubah}(h]h ]h"]h$]h&]uh1j?hjyubeh}(h]h ]h"]h$]h&]uh1jhjyhMhjyubah}(h]h ]h"]h$]h&]uh1jhjyubh)}(h**Description**h]j)}(hjzh]h Description}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjyubh)}(hDO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h]hDO NOT USE. This is intended to be called on very special objects that don’t yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.}(hj&zhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjyubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j-__i915_gem_object_make_purgeable (C function)"c.__i915_gem_object_make_purgeablehNtauh1jhjphhhNhNubj)}(hhh](j)}(hGvoid __i915_gem_object_make_purgeable (struct drm_i915_gem_object *obj)h]j)}(hFvoid __i915_gem_object_make_purgeable(struct drm_i915_gem_object *obj)h](jn)}(hvoidh]hvoid}(hjUzhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjQzhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM'ubj )}(h h]h }(hjdzhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjQzhhhjczhM'ubj)}(h __i915_gem_object_make_purgeableh]j)}(h __i915_gem_object_make_purgeableh]h __i915_gem_object_make_purgeable}(hjvzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrzubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjQzhhhjczhM'ubj8)}(h!(struct drm_i915_gem_object *obj)h]j>)}(hstruct drm_i915_gem_object *objh](jD)}(hjGh]hstruct}(hjzhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjzubj )}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjzubh)}(hhh]j)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjzmodnameN classnameNjj)}j]j)}jjxzsb"c.__i915_gem_object_make_purgeableasbuh1hhjzubj )}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjzubj)}(hjh]h*}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(hobjh]hobj}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjzubah}(h]h ]h"]h$]h&]j5j6uh1j7hjQzhhhjczhM'ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjMzhhhjczhM'ubah}(h]jHzah ](jjeh"]h$]h&]jj)jhuh1jhjczhM'hjJzhhubj)}(hhh]h)}(hyMove the object to the tail of the purgeable list. Objects on this list might be swapped out. Used with DONTNEED objects.h]hyMove the object to the tail of the purgeable list. Objects on this list might be swapped out. Used with DONTNEED objects.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM'hj{hhubah}(h]h ]h"]h$]h&]uh1jhjJzhhhjczhM'ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj-{jj-{jjjuh1jhhhjphNhNubj)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** DO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h](h)}(h**Parameters**h]j)}(hj7{h]h Parameters}(hj9{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5{ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM+hj1{ubj)}(hhh]j)}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j$)}(h#``struct drm_i915_gem_object *obj``h]j*)}(hjV{h]hstruct drm_i915_gem_object *obj}(hjX{hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjT{ubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM*hjP{ubj@)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hjo{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk{hM*hjl{ubah}(h]h ]h"]h$]h&]uh1j?hjP{ubeh}(h]h ]h"]h$]h&]uh1jhjk{hM*hjM{ubah}(h]h ]h"]h$]h&]uh1jhj1{ubh)}(h**Description**h]j)}(hj{h]h Description}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM,hj1{ubh)}(hDO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h]hDO NOT USE. This is intended to be called on very special objects that don’t yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM+hj1{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,i915_gem_object_make_shrinkable (C function)!c.i915_gem_object_make_shrinkablehNtauh1jhjphhhNhNubj)}(hhh](j)}(hFvoid i915_gem_object_make_shrinkable (struct drm_i915_gem_object *obj)h]j)}(hEvoid i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj)h](jn)}(hvoidh]hvoid}(hj{hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj{hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM7ubj )}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj{hhhj{hM7ubj)}(hi915_gem_object_make_shrinkableh]j)}(hi915_gem_object_make_shrinkableh]hi915_gem_object_make_shrinkable}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj{hhhj{hM7ubj8)}(h!(struct drm_i915_gem_object *obj)h]j>)}(hstruct drm_i915_gem_object *objh](jD)}(hjGh]hstruct}(hj|hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj|ubj )}(h h]h }(hj |hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj|ubh)}(hhh]j)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hj1|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.|ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj3|modnameN classnameNjj)}j]j)}jj{sb!c.i915_gem_object_make_shrinkableasbuh1hhj|ubj )}(h h]h }(hjQ|hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj|ubj)}(hjh]h*}(hj_|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubj)}(hobjh]hobj}(hjl|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj |ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj{hhhj{hM7ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj{hhhj{hM7ubah}(h]j{ah ](jjeh"]h$]h&]jj)jhuh1jhj{hM7hj{hhubj)}(hhh]h)}(hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.h]hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM7hj|hhubah}(h]h ]h"]h$]h&]uh1jhj{hhhj{hM7ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj|jj|jjjuh1jhhhjphNhNubj)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** MUST only be called on objects which have backing pages. MUST be balanced with previous call to i915_gem_object_make_unshrinkable().h](h)}(h**Parameters**h]j)}(hj|h]h Parameters}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM;hj|ubj)}(hhh]j)}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j$)}(h#``struct drm_i915_gem_object *obj``h]j*)}(hj|h]hstruct drm_i915_gem_object *obj}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj|ubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM:hj|ubj@)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hM:hj|ubah}(h]h ]h"]h$]h&]uh1j?hj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hM:hj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubh)}(h**Description**h]j)}(hj}h]h Description}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM<hj|ubh)}(h8MUST only be called on objects which have backing pages.h]h8MUST only be called on objects which have backing pages.}(hj(}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM;hj|ubh)}(hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().h]hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().}(hj7}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM=hj|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+i915_gem_object_make_purgeable (C function) c.i915_gem_object_make_purgeablehNtauh1jhjphhhNhNubj)}(hhh](j)}(hEvoid i915_gem_object_make_purgeable (struct drm_i915_gem_object *obj)h]j)}(hDvoid i915_gem_object_make_purgeable(struct drm_i915_gem_object *obj)h](jn)}(hvoidh]hvoid}(hjf}hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjb}hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMGubj )}(h h]h }(hju}hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjb}hhhjt}hMGubj)}(hi915_gem_object_make_purgeableh]j)}(hi915_gem_object_make_purgeableh]hi915_gem_object_make_purgeable}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjb}hhhjt}hMGubj8)}(h!(struct drm_i915_gem_object *obj)h]j>)}(hstruct drm_i915_gem_object *objh](jD)}(hjGh]hstruct}(hj}hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj}ubj )}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj}ubh)}(hhh]j)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj}modnameN classnameNjj)}j]j)}jj}sb c.i915_gem_object_make_purgeableasbuh1hhj}ubj )}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj}ubj)}(hjh]h*}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubj)}(hobjh]hobj}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj}ubah}(h]h ]h"]h$]h&]j5j6uh1j7hjb}hhhjt}hMGubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj^}hhhjt}hMGubah}(h]jY}ah ](jjeh"]h$]h&]jj)jhuh1jhjt}hMGhj[}hhubj)}(hhh]h)}(hMove the object to the tail of the purgeable list. Used with DONTNEED objects. Unlike with shrinkable objects, the shrinker will attempt to discard the backing pages, instead of trying to swap them out.h]hMove the object to the tail of the purgeable list. Used with DONTNEED objects. Unlike with shrinkable objects, the shrinker will attempt to discard the backing pages, instead of trying to swap them out.}(hj&~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMGhj#~hhubah}(h]h ]h"]h$]h&]uh1jhj[}hhhjt}hMGubeh}(h]h ](jfunctioneh"]h$]h&]jjjj>~jj>~jjjuh1jhhhjphNhNubj)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** MUST only be called on objects which have backing pages. MUST be balanced with previous call to i915_gem_object_make_unshrinkable().h](h)}(h**Parameters**h]j)}(hjH~h]h Parameters}(hjJ~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjF~ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMKhjB~ubj)}(hhh]j)}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j$)}(h#``struct drm_i915_gem_object *obj``h]j*)}(hjg~h]hstruct drm_i915_gem_object *obj}(hji~hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hje~ubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMKhja~ubj@)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|~hMKhj}~ubah}(h]h ]h"]h$]h&]uh1j?hja~ubeh}(h]h ]h"]h$]h&]uh1jhj|~hMKhj^~ubah}(h]h ]h"]h$]h&]uh1jhjB~ubh)}(h**Description**h]j)}(hj~h]h Description}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMMhjB~ubh)}(h8MUST only be called on objects which have backing pages.h]h8MUST only be called on objects which have backing pages.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMLhjB~ubh)}(hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().h]hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:227: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMNhjB~ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjphhhNhNubeh}(h]buffer-object-memory-shrinkingah ]h"]buffer object memory shrinkingah$]h&]uh1hhj.bhhhhhKubh)}(hhh](h)}(hBatchbuffer Parsingh]hBatchbuffer Parsing}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhhhKubh)}(hXMotivation: Certain OpenGL features (e.g. transform feedback, performance monitoring) require userspace code to submit batches containing commands such as MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some generations of the hardware will noop these commands in "unsecure" batches (which includes all userspace batches submitted via i915) even though the commands may be safe and represent the intended programming model of the device.h]hXMotivation: Certain OpenGL features (e.g. transform feedback, performance monitoring) require userspace code to submit batches containing commands such as MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some generations of the hardware will noop these commands in “unsecure” batches (which includes all userspace batches submitted via i915) even though the commands may be safe and represent the intended programming model of the device.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chK,hj~hhubh)}(hX6The software command parser is similar in operation to the command parsing done in hardware for unsecure batches. However, the software parser allows some operations that would be noop'd by hardware, if the parser determines the operation is safe, and submits the batch as "secure" to prevent hardware parsing.h]hX<The software command parser is similar in operation to the command parsing done in hardware for unsecure batches. However, the software parser allows some operations that would be noop’d by hardware, if the parser determines the operation is safe, and submits the batch as “secure” to prevent hardware parsing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chK5hj~hhubh)}(hThreats: At a high level, the hardware (and software) checks attempt to prevent granting userspace undue privileges. There are three categories of privilege.h]hThreats: At a high level, the hardware (and software) checks attempt to prevent granting userspace undue privileges. There are three categories of privilege.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chK;hj~hhubh)}(hFirst, commands which are explicitly defined as privileged or which should only be used by the kernel driver. The parser rejects such commandsh]hFirst, commands which are explicitly defined as privileged or which should only be used by the kernel driver. The parser rejects such commands}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chK?hj~hhubh)}(hSecond, commands which access registers. To support correct/enhanced userspace functionality, particularly certain OpenGL extensions, the parser provides a whitelist of registers which userspace may safely accessh]hSecond, commands which access registers. To support correct/enhanced userspace functionality, particularly certain OpenGL extensions, the parser provides a whitelist of registers which userspace may safely access}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chKBhj~hhubh)}(hsThird, commands which access privileged memory (i.e. GGTT, HWS page, etc). The parser always rejects such commands.h]hsThird, commands which access privileged memory (i.e. GGTT, HWS page, etc). The parser always rejects such commands.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chKFhj~hhubh)}(hThe majority of the problematic commands fall in the MI_* range, with only a few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).h]hThe majority of the problematic commands fall in the MI_* range, with only a few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chKIhj~hhubh)}(hImplementation: Each engine maintains tables of commands and registers which the parser uses in scanning batch buffers submitted to that engine.h]hImplementation: Each engine maintains tables of commands and registers which the parser uses in scanning batch buffers submitted to that engine.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chKLhj~hhubh)}(hXSince the set of commands that the parser must check for is significantly smaller than the number of commands supported, the parser tables contain only those commands required by the parser. This generally works because command opcode ranges have standard command length encodings. So for commands that the parser does not need to check, it can easily skip them. This is implemented via a per-engine length decoding vfunc.h]hXSince the set of commands that the parser must check for is significantly smaller than the number of commands supported, the parser tables contain only those commands required by the parser. This generally works because command opcode ranges have standard command length encodings. So for commands that the parser does not need to check, it can easily skip them. This is implemented via a per-engine length decoding vfunc.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chKPhj~hhubh)}(hXUnfortunately, there are a number of commands that do not follow the standard length encoding for their opcode range, primarily amongst the MI_* commands. To handle this, the parser provides a way to define explicit "skip" entries in the per-engine command tables.h]hX Unfortunately, there are a number of commands that do not follow the standard length encoding for their opcode range, primarily amongst the MI_* commands. To handle this, the parser provides a way to define explicit “skip” entries in the per-engine command tables.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chKWhj~hhubh)}(hOther command table entries map fairly directly to high level categories mentioned above: rejected, register whitelist. The parser implements a number of checks, including the privileged memory checks, via a general bitmasking mechanism.h]hOther command table entries map fairly directly to high level categories mentioned above: rejected, register whitelist. The parser implements a number of checks, including the privileged memory checks, via a general bitmasking mechanism.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:233: ./drivers/gpu/drm/i915/i915_cmd_parser.chK\hj~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)intel_engine_init_cmd_parser (C function)c.intel_engine_init_cmd_parserhNtauh1jhj~hhhNhNubj)}(hhh](j)}(hAint intel_engine_init_cmd_parser (struct intel_engine_cs *engine)h]j)}(h@int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)h](jn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hintel_engine_init_cmd_parserh]j)}(hintel_engine_init_cmd_parserh]hintel_engine_init_cmd_parser}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(h (struct intel_engine_cs *engine)h]j>)}(hstruct intel_engine_cs *engineh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hintel_engine_csh]hintel_engine_cs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.intel_engine_init_cmd_parserasbuh1hhjubj )}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hengineh]hengine}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h+set cmd parser related fields for an engineh]h+set cmd parser related fields for an engine}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjqhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhj~hNhNubj)}(hX**Parameters** ``struct intel_engine_cs *engine`` the engine to initialize **Description** Optionally initializes fields related to batch buffer command parsing in the struct intel_engine_cs based on whether the platform requires software command parsing.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjubj)}(hhh]j)}(h<``struct intel_engine_cs *engine`` the engine to initialize h](j$)}(h"``struct intel_engine_cs *engine``h]j*)}(hjh]hstruct intel_engine_cs *engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjubj@)}(hhh]h)}(hthe engine to initializeh]hthe engine to initialize}(hj΀hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjʀhMhjˀubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjʀhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjubh)}(hOptionally initializes fields related to batch buffer command parsing in the struct intel_engine_cs based on whether the platform requires software command parsing.h]hOptionally initializes fields related to batch buffer command parsing in the struct intel_engine_cs based on whether the platform requires software command parsing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,intel_engine_cleanup_cmd_parser (C function)!c.intel_engine_cleanup_cmd_parserhNtauh1jhj~hhhNhNubj)}(hhh](j)}(hEvoid intel_engine_cleanup_cmd_parser (struct intel_engine_cs *engine)h]j)}(hDvoid intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)h](jn)}(hvoidh]hvoid}(hj5hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj1hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM&ubj )}(h h]h }(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj1hhhjChM&ubj)}(hintel_engine_cleanup_cmd_parserh]j)}(hintel_engine_cleanup_cmd_parserh]hintel_engine_cleanup_cmd_parser}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj1hhhjChM&ubj8)}(h (struct intel_engine_cs *engine)h]j>)}(hstruct intel_engine_cs *engineh](jD)}(hjGh]hstruct}(hjrhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjnubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjnubh)}(hhh]j)}(hintel_engine_csh]hintel_engine_cs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjXsb!c.intel_engine_cleanup_cmd_parserasbuh1hhjnubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjnubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(hengineh]hengine}(hjˁhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjjubah}(h]h ]h"]h$]h&]j5j6uh1j7hj1hhhjChM&ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj-hhhjChM&ubah}(h]j(ah ](jjeh"]h$]h&]jj)jhuh1jhjChM&hj*hhubj)}(hhh]h)}(h"clean up cmd parser related fieldsh]h"clean up cmd parser related fields}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM&hjhhubah}(h]h ]h"]h$]h&]uh1jhj*hhhjChM&ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhj~hNhNubj)}(h**Parameters** ``struct intel_engine_cs *engine`` the engine to clean up **Description** Releases any resources related to command parsing that may have been initialized for the specified engine.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM*hjubj)}(hhh]j)}(h:``struct intel_engine_cs *engine`` the engine to clean up h](j$)}(h"``struct intel_engine_cs *engine``h]j*)}(hj6h]hstruct intel_engine_cs *engine}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj4ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM'hj0ubj@)}(hhh]h)}(hthe engine to clean uph]hthe engine to clean up}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM'hjLubah}(h]h ]h"]h$]h&]uh1j?hj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhM'hj-ubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjqh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM)hjubh)}(hjReleases any resources related to command parsing that may have been initialized for the specified engine.h]hjReleases any resources related to command parsing that may have been initialized for the specified engine.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM(hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$intel_engine_cmd_parser (C function)c.intel_engine_cmd_parserhNtauh1jhj~hhhNhNubj)}(hhh](j)}(hint intel_engine_cmd_parser (struct intel_engine_cs *engine, struct i915_vma *batch, unsigned long batch_offset, unsigned long batch_length, struct i915_vma *shadow, bool trampoline)h]j)}(hint intel_engine_cmd_parser(struct intel_engine_cs *engine, struct i915_vma *batch, unsigned long batch_offset, unsigned long batch_length, struct i915_vma *shadow, bool trampoline)h](jn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMubj )}(h h]h }(hjłhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjĂhMubj)}(hintel_engine_cmd_parserh]j)}(hintel_engine_cmd_parserh]hintel_engine_cmd_parser}(hjׂhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjӂubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjĂhMubj8)}(h(struct intel_engine_cs *engine, struct i915_vma *batch, unsigned long batch_offset, unsigned long batch_length, struct i915_vma *shadow, bool trampoline)h](j>)}(hstruct intel_engine_cs *engineh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hintel_engine_csh]hintel_engine_cs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjقsbc.intel_engine_cmd_parserasbuh1hhjubj )}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hengineh]hengine}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hstruct i915_vma *batchh](jD)}(hjGh]hstruct}(hjehhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjaubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjaubh)}(hhh]j)}(hi915_vmah]hi915_vma}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j-c.intel_engine_cmd_parserasbuh1hhjaubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjaubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj)}(hbatchh]hbatch}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hunsigned long batch_offseth](jn)}(hunsignedh]hunsigned}(hjՃhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjуubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjуubjn)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjуubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjуubj)}(h batch_offseth]h batch_offset}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjуubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hunsigned long batch_lengthh](jn)}(hunsignedh]hunsigned}(hj&hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj"ubj )}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj"ubjn)}(hlongh]hlong}(hjBhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj"ubj )}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj"ubj)}(h batch_lengthh]h batch_length}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hstruct i915_vma *shadowh](jD)}(hjGh]hstruct}(hjwhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjsubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjsubh)}(hhh]j)}(hi915_vmah]hi915_vma}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j-c.intel_engine_cmd_parserasbuh1hhjsubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjsubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj)}(hshadowh]hshadow}(hj΄hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hbool trampolineh](jn)}(hjqh]hbool}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(h trampolineh]h trampoline}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjĂhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjĂhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjĂhMhjhhubj)}(hhh]h)}(h-parse a batch buffer for privilege violationsh]h-parse a batch buffer for privilege violations}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhj)hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjĂhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjDjjDjjjuh1jhhhj~hNhNubj)}(hX**Parameters** ``struct intel_engine_cs *engine`` the engine on which the batch is to execute ``struct i915_vma *batch`` the batch buffer in question ``unsigned long batch_offset`` byte offset in the batch at which execution starts ``unsigned long batch_length`` length of the commands in batch_obj ``struct i915_vma *shadow`` validated copy of the batch buffer in question ``bool trampoline`` true if we need to trampoline into privileged execution **Description** Parses the specified batch buffer looking for privilege violations as described in the overview. **Return** non-zero if the parser finds violations or otherwise fails; -EACCES if the batch appears legal but should use hardware parsingh](h)}(h**Parameters**h]j)}(hjNh]h Parameters}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjHubj)}(hhh](j)}(hO``struct intel_engine_cs *engine`` the engine on which the batch is to execute h](j$)}(h"``struct intel_engine_cs *engine``h]j*)}(hjmh]hstruct intel_engine_cs *engine}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjkubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjgubj@)}(hhh]h)}(h+the engine on which the batch is to executeh]h+the engine on which the batch is to execute}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjgubeh}(h]h ]h"]h$]h&]uh1jhjhMhjdubj)}(h8``struct i915_vma *batch`` the batch buffer in question h](j$)}(h``struct i915_vma *batch``h]j*)}(hjh]hstruct i915_vma *batch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjubj@)}(hhh]h)}(hthe batch buffer in questionh]hthe batch buffer in question}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjdubj)}(hR``unsigned long batch_offset`` byte offset in the batch at which execution starts h](j$)}(h``unsigned long batch_offset``h]j*)}(hj߅h]hunsigned long batch_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj݅ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjمubj@)}(hhh]h)}(h2byte offset in the batch at which execution startsh]h2byte offset in the batch at which execution starts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjمubeh}(h]h ]h"]h$]h&]uh1jhjhMhjdubj)}(hC``unsigned long batch_length`` length of the commands in batch_obj h](j$)}(h``unsigned long batch_length``h]j*)}(hjh]hunsigned long batch_length}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjubj@)}(hhh]h)}(h#length of the commands in batch_objh]h#length of the commands in batch_obj}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMhj.ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj-hMhjdubj)}(hK``struct i915_vma *shadow`` validated copy of the batch buffer in question h](j$)}(h``struct i915_vma *shadow``h]j*)}(hjQh]hstruct i915_vma *shadow}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjOubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjKubj@)}(hhh]h)}(h.validated copy of the batch buffer in questionh]h.validated copy of the batch buffer in question}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMhjgubah}(h]h ]h"]h$]h&]uh1j?hjKubeh}(h]h ]h"]h$]h&]uh1jhjfhMhjdubj)}(hL``bool trampoline`` true if we need to trampoline into privileged execution h](j$)}(h``bool trampoline``h]j*)}(hjh]hbool trampoline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjubj@)}(hhh]h)}(h7true if we need to trampoline into privileged executionh]h7true if we need to trampoline into privileged execution}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjdubeh}(h]h ]h"]h$]h&]uh1jhjHubh)}(h**Description**h]j)}(hjņh]h Description}(hjdžhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjÆubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjHubh)}(h`Parses the specified batch buffer looking for privilege violations as described in the overview.h]h`Parses the specified batch buffer looking for privilege violations as described in the overview.}(hjۆhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjHubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjHubh)}(h~non-zero if the parser finds violations or otherwise fails; -EACCES if the batch appears legal but should use hardware parsingh]h~non-zero if the parser finds violations or otherwise fails; -EACCES if the batch appears legal but should use hardware parsing}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjHubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(i915_cmd_parser_get_version (C function)c.i915_cmd_parser_get_versionhNtauh1jhj~hhhNhNubj)}(hhh](j)}(hCint i915_cmd_parser_get_version (struct drm_i915_private *dev_priv)h]j)}(hBint i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)h](jn)}(hinth]hint}(hj1hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj-hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM-ubj )}(h h]h }(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj-hhhj?hM-ubj)}(hi915_cmd_parser_get_versionh]j)}(hi915_cmd_parser_get_versionh]hi915_cmd_parser_get_version}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj-hhhj?hM-ubj8)}(h#(struct drm_i915_private *dev_priv)h]j>)}(h!struct drm_i915_private *dev_privh](jD)}(hjGh]hstruct}(hjnhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjjubj )}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjjubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjTsbc.i915_cmd_parser_get_versionasbuh1hhjjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj)}(hdev_privh]hdev_priv}(hjLJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjfubah}(h]h ]h"]h$]h&]j5j6uh1j7hj-hhhj?hM-ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj)hhhj?hM-ubah}(h]j$ah ](jjeh"]h$]h&]jj)jhuh1jhj?hM-hj&hhubj)}(hhh]h)}(h!get the cmd parser version numberh]h!get the cmd parser version number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM-hjhhubah}(h]h ]h"]h$]h&]uh1jhj&hhhj?hM-ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhj~hNhNubj)}(hX1**Parameters** ``struct drm_i915_private *dev_priv`` i915 device private **Description** The cmd parser maintains a simple increasing integer version number suitable for passing to userspace clients to determine what operations are permitted. **Return** the current version number of the cmd parserh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM1hj ubj)}(hhh]j)}(h:``struct drm_i915_private *dev_priv`` i915 device private h](j$)}(h%``struct drm_i915_private *dev_priv``h]j*)}(hj2h]h!struct drm_i915_private *dev_priv}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj0ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM.hj,ubj@)}(hhh]h)}(hi915 device privateh]hi915 device private}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhM.hjHubah}(h]h ]h"]h$]h&]uh1j?hj,ubeh}(h]h ]h"]h$]h&]uh1jhjGhM.hj)ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hjmh]h Description}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM0hj ubh)}(hThe cmd parser maintains a simple increasing integer version number suitable for passing to userspace clients to determine what operations are permitted.h]hThe cmd parser maintains a simple increasing integer version number suitable for passing to userspace clients to determine what operations are permitted.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM/hj ubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM2hj ubh)}(h,the current version number of the cmd parserh]h,the current version number of the cmd parser}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:236: ./drivers/gpu/drm/i915/i915_cmd_parser.chM3hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj~hhhNhNubeh}(h]batchbuffer-parsingah ]h"]batchbuffer parsingah$]h&]uh1hhj.bhhhhhKubh)}(hhh](h)}(hUser Batchbuffer Executionh]hUser Batchbuffer Execution}(hjˈhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjȈhhhhhKubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_gem_engines (C struct)c.i915_gem_engineshNtauh1jhjȈhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhNubj)}(hhh](j)}(hi915_gem_enginesh]j)}(hstruct i915_gem_enginesh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhKubj)}(hi915_gem_enginesh]j)}(hjh]hi915_gem_engines}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hA set of enginesh]hA set of engines}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK!hj2hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjMjjMjjjuh1jhhhjȈhjhNubj)}(hXP**Definition**:: struct i915_gem_engines { union { struct list_head link; struct rcu_head rcu; }; struct i915_sw_fence fence; struct i915_gem_context *ctx; unsigned int num_engines; struct intel_context *engines[]; }; **Members** ``{unnamed_union}`` anonymous ``link`` Link in i915_gem_context::stale::engines ``rcu`` RCU to use when freeing ``fence`` Fence used for delayed destruction of engines ``ctx`` i915_gem_context backpointer ``num_engines`` Number of engines in this set ``engines`` Array of enginesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubh:}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK%hjQubjA#)}(hstruct i915_gem_engines { union { struct list_head link; struct rcu_head rcu; }; struct i915_sw_fence fence; struct i915_gem_context *ctx; unsigned int num_engines; struct intel_context *engines[]; };h]hstruct i915_gem_engines { union { struct list_head link; struct rcu_head rcu; }; struct i915_sw_fence fence; struct i915_gem_context *ctx; unsigned int num_engines; struct intel_context *engines[]; };}hjrsbah}(h]h ]h"]h$]h&]j5j6uh1j@#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK'hjQubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK2hjQubj)}(hhh](j)}(h``{unnamed_union}`` anonymous h](j$)}(h``{unnamed_union}``h]j*)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj@)}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h2``link`` Link in i915_gem_context::stale::engines h](j$)}(h``link``h]j*)}(hjۉh]hlink}(hj݉hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjىubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK&hjՉubj@)}(hhh]h)}(h(Link in i915_gem_context::stale::enginesh]h(Link in i915_gem_context::stale::engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK&hjubah}(h]h ]h"]h$]h&]uh1j?hjՉubeh}(h]h ]h"]h$]h&]uh1jhjhK&hjubj)}(h ``rcu`` RCU to use when freeing h](j$)}(h``rcu``h]j*)}(hjh]hrcu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK)hjubj@)}(hhh]h)}(hRCU to use when freeingh]hRCU to use when freeing}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hK)hj*ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj)hK)hjubj)}(h8``fence`` Fence used for delayed destruction of engines h](j$)}(h ``fence``h]j*)}(hjMh]hfence}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjKubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK-hjGubj@)}(hhh]h)}(h-Fence used for delayed destruction of enginesh]h-Fence used for delayed destruction of engines}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhK-hjcubah}(h]h ]h"]h$]h&]uh1j?hjGubeh}(h]h ]h"]h$]h&]uh1jhjbhK-hjubj)}(h%``ctx`` i915_gem_context backpointer h](j$)}(h``ctx``h]j*)}(hjh]hctx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK0hjubj@)}(hhh]h)}(hi915_gem_context backpointerh]hi915_gem_context backpointer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK0hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK0hjubj)}(h.``num_engines`` Number of engines in this set h](j$)}(h``num_engines``h]j*)}(hjh]h num_engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK3hjubj@)}(hhh]h)}(hNumber of engines in this seth]hNumber of engines in this set}(hj؊hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjԊhK3hjՊubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjԊhK3hjubj)}(h``engines`` Array of enginesh](j$)}(h ``engines``h]j*)}(hjh]hengines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK5hjubj@)}(hhh]h)}(hArray of enginesh]hArray of engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK6hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hK5hjubeh}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjȈhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j i915_gem_engines_iter (C struct)c.i915_gem_engines_iterhNtauh1jhjȈhhhjhNubj)}(hhh](j)}(hi915_gem_engines_iterh]j)}(hstruct i915_gem_engines_iterh](jD)}(hjGh]hstruct}(hjRhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjNhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubjA#)}(hcstruct i915_gem_engines_iter { unsigned int idx; const struct i915_gem_engines *engines; };h]hcstruct i915_gem_engines_iter { unsigned int idx; const struct i915_gem_engines *engines; };}hjыsbah}(h]h ]h"]h$]h&]j5j6uh1j@#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK@hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKEhjubj)}(hhh](j)}(h-``idx`` Index into i915_gem_engines::engines h](j$)}(h``idx``h]j*)}(hjh]hidx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK>hjubj@)}(hhh]h)}(h$Index into i915_gem_engines::enginesh]h$Index into i915_gem_engines::engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK>hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK>hjubj)}(h%``engines`` Engine set being iteratedh](j$)}(h ``engines``h]j*)}(hj:h]hengines}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj8ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK@hj4ubj@)}(hhh]h)}(hEngine set being iteratedh]hEngine set being iterated}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKAhjPubah}(h]h ]h"]h$]h&]uh1j?hj4ubeh}(h]h ]h"]h$]h&]uh1jhjOhK@hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjȈhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_gem_engine_type (C enum)c.i915_gem_engine_typehNtauh1jhjȈhhhjhNubj)}(hhh](j)}(hi915_gem_engine_typeh]j)}(henum i915_gem_engine_typeh](jD)}(hjh]henum}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKGubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhKGubj)}(hi915_gem_engine_typeh]j)}(hjh]hi915_gem_engine_type}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhKGubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhKGubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKGhjhhubj)}(hhh]h)}(h.Describes the type of an i915_gem_proto_engineh]h.Describes the type of an i915_gem_proto_engine}(hj֌hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKEhjӌhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKGubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1jhhhjȈhjhNubj)}(h**Constants** ``I915_GEM_ENGINE_TYPE_INVALID`` An invalid engine ``I915_GEM_ENGINE_TYPE_PHYSICAL`` A single physical engine ``I915_GEM_ENGINE_TYPE_BALANCED`` A load-balanced engine set ``I915_GEM_ENGINE_TYPE_PARALLEL`` A parallel engine seth](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKIhjubj)}(hhh](j)}(h3``I915_GEM_ENGINE_TYPE_INVALID`` An invalid engine h](j$)}(h ``I915_GEM_ENGINE_TYPE_INVALID``h]j*)}(hjh]hI915_GEM_ENGINE_TYPE_INVALID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKLhjubj@)}(hhh]h)}(hAn invalid engineh]hAn invalid engine}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hKLhj-ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj,hKLhjubj)}(h;``I915_GEM_ENGINE_TYPE_PHYSICAL`` A single physical engine h](j$)}(h!``I915_GEM_ENGINE_TYPE_PHYSICAL``h]j*)}(hjPh]hI915_GEM_ENGINE_TYPE_PHYSICAL}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjNubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKOhjJubj@)}(hhh]h)}(hA single physical engineh]hA single physical engine}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehKOhjfubah}(h]h ]h"]h$]h&]uh1j?hjJubeh}(h]h ]h"]h$]h&]uh1jhjehKOhjubj)}(h=``I915_GEM_ENGINE_TYPE_BALANCED`` A load-balanced engine set h](j$)}(h!``I915_GEM_ENGINE_TYPE_BALANCED``h]j*)}(hjh]hI915_GEM_ENGINE_TYPE_BALANCED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKRhjubj@)}(hhh]h)}(hA load-balanced engine seth]hA load-balanced engine set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKRhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKRhjubj)}(h7``I915_GEM_ENGINE_TYPE_PARALLEL`` A parallel engine seth](j$)}(h!``I915_GEM_ENGINE_TYPE_PARALLEL``h]j*)}(hjh]hI915_GEM_ENGINE_TYPE_PARALLEL}(hjčhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKThjubj@)}(hhh]h)}(hA parallel engine seth]hA parallel engine set}(hjۍhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKUhj؍ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj׍hKThjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjȈhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j i915_gem_proto_engine (C struct)c.i915_gem_proto_enginehNtauh1jhjȈhhhjhNubj)}(hhh](j)}(hi915_gem_proto_engineh]j)}(hstruct i915_gem_proto_engineh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKZubj )}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhj)hKZubj)}(hi915_gem_proto_engineh]j)}(hjh]hi915_gem_proto_engine}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhj)hKZubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhj)hKZubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj)hKZhjhhubj)}(hhh]h)}(hprototype engineh]hprototype engine}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKVhj[hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj)hKZubeh}(h]h ](jstructeh"]h$]h&]jjjjvjjvjjjuh1jhhhjȈhjhNubj)}(hX"**Definition**:: struct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; }; **Members** ``type`` Type of this engine ``engine`` Engine, for physical ``num_siblings`` Number of balanced or parallel siblings ``width`` Width of each sibling ``siblings`` Balanced siblings or num_siblings * width for parallel ``sseu`` Client-set SSEU parametersh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubh:}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKZhjzubjA#)}(hstruct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; };h]hstruct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; };}hjsbah}(h]h ]h"]h$]h&]j5j6uh1j@#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK\hjzubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKehjzubj)}(hhh](j)}(h``type`` Type of this engine h](j$)}(h``type``h]j*)}(hjˎh]htype}(hj͎hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjɎubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKmhjŎubj@)}(hhh]h)}(hType of this engineh]hType of this engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKmhjubah}(h]h ]h"]h$]h&]uh1j?hjŎubeh}(h]h ]h"]h$]h&]uh1jhjhKmhjŽubj)}(h ``engine`` Engine, for physical h](j$)}(h ``engine``h]j*)}(hjh]hengine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKphjubj@)}(hhh]h)}(hEngine, for physicalh]hEngine, for physical}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKphjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKphjŽubj)}(h9``num_siblings`` Number of balanced or parallel siblings h](j$)}(h``num_siblings``h]j*)}(hj=h]h num_siblings}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj;ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKshj7ubj@)}(hhh]h)}(h'Number of balanced or parallel siblingsh]h'Number of balanced or parallel siblings}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhKshjSubah}(h]h ]h"]h$]h&]uh1j?hj7ubeh}(h]h ]h"]h$]h&]uh1jhjRhKshjŽubj)}(h ``width`` Width of each sibling h](j$)}(h ``width``h]j*)}(hjvh]hwidth}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjtubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKvhjpubj@)}(hhh]h)}(hWidth of each siblingh]hWidth of each sibling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKvhjubah}(h]h ]h"]h$]h&]uh1j?hjpubeh}(h]h ]h"]h$]h&]uh1jhjhKvhjŽubj)}(hD``siblings`` Balanced siblings or num_siblings * width for parallel h](j$)}(h ``siblings``h]j*)}(hjh]hsiblings}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKyhjubj@)}(hhh]h)}(h6Balanced siblings or num_siblings * width for parallelh]h6Balanced siblings or num_siblings * width for parallel}(hjȏhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjďhKyhjŏubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjďhKyhjŽubj)}(h#``sseu`` Client-set SSEU parametersh](j$)}(h``sseu``h]j*)}(hjh]hsseu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK{hjubj@)}(hhh]h)}(hClient-set SSEU parametersh]hClient-set SSEU parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK|hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK{hjŽubeh}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjȈhhhjhNubh)}(h**Description**h]j)}(hj+h]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubh)}(hUThis struct describes an engine that a context may contain. Engines have four types:h]hUThis struct describes an engine that a context may contain. Engines have four types:}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKWhjȈhhubjgd)}(hX - I915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines. - I915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine. - I915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings. - I915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings. h]j:)}(hhh](j:)}(hXII915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines. h]h)}(hXHI915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines.h]hXHI915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKZhjWubah}(h]h ]h"]h$]h&]uh1j:hjTubj:)}(heI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine. h]h)}(hdI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine.h]hdI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK`hjpubah}(h]h ]h"]h$]h&]uh1j:hjTubj:)}(hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings. h]h)}(hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings.h]hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKchjubah}(h]h ]h"]h$]h&]uh1j:hjTubj:)}(hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings. h]h)}(hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings.h]hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKfhjubah}(h]h ]h"]h$]h&]uh1j:hjTubeh}(h]h ]h"]h$]h&]j;j;uh1j:hjihKZhjPubah}(h]h ]h"]h$]h&]uh1jfdhjihKZhjȈhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!i915_gem_proto_context (C struct)c.i915_gem_proto_contexthNtauh1jhjȈhhhjhNubj)}(hhh](j)}(hi915_gem_proto_contexth]j)}(hstruct i915_gem_proto_contexth](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjܐhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKmubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjܐhhhjhKmubj)}(hi915_gem_proto_contexth]j)}(hjڐh]hi915_gem_proto_context}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjܐhhhjhKmubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjؐhhhjhKmubah}(h]jӐah ](jjeh"]h$]h&]jj)jhuh1jhjhKmhjՐhhubj)}(hhh]h)}(hprototype contexth]hprototype context}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjՐhhhjhKmubeh}(h]h ](jstructeh"]h$]h&]jjjj:jj:jjjuh1jhhhjȈhjhNubj)}(hXo**Definition**:: struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct i915_gem_proto_engine *user_engines; struct intel_sseu legacy_rcs_sseu; bool single_timeline; bool uses_protected_content; intel_wakeref_t pxp_wakeref; }; **Members** ``fpriv`` Client which creates the context ``vm`` See :c:type:`i915_gem_context.vm ` ``user_flags`` See :c:type:`i915_gem_context.user_flags ` ``sched`` See :c:type:`i915_gem_context.sched ` ``num_user_engines`` Number of user-specified engines or -1 ``user_engines`` User-specified engines ``legacy_rcs_sseu`` Client-set SSEU parameters for the legacy RCS ``single_timeline`` See See :c:type:`i915_gem_context.syncobj ` ``uses_protected_content`` See :c:type:`i915_gem_context.uses_protected_content ` ``pxp_wakeref`` See :c:type:`i915_gem_context.pxp_wakeref `h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubh:}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj>ubjA#)}(hX{struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct i915_gem_proto_engine *user_engines; struct intel_sseu legacy_rcs_sseu; bool single_timeline; bool uses_protected_content; intel_wakeref_t pxp_wakeref; };h]hX{struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct i915_gem_proto_engine *user_engines; struct intel_sseu legacy_rcs_sseu; bool single_timeline; bool uses_protected_content; intel_wakeref_t pxp_wakeref; };}hj_sbah}(h]h ]h"]h$]h&]j5j6uh1j@#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj>ubh)}(h **Members**h]j)}(hjph]hMembers}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj>ubj)}(hhh](j)}(h+``fpriv`` Client which creates the context h](j$)}(h ``fpriv``h]j*)}(hjh]hfpriv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj@)}(hhh]h)}(h Client which creates the contexth]h Client which creates the context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h<``vm`` See :c:type:`i915_gem_context.vm ` h](j$)}(h``vm``h]j*)}(hjȑh]hvm}(hjʑhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjƑubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj‘ubj@)}(hhh]h)}(h4See :c:type:`i915_gem_context.vm `h](hSee }(hjhhhNhNubh)}(h0:c:type:`i915_gem_context.vm `h]j*)}(hjh]hi915_gem_context.vm}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]sbji915_gem_contextuh1hhjݑhKhjubeh}(h]h ]h"]h$]h&]uh1hhjݑhKhjޑubah}(h]h ]h"]h$]h&]uh1j?hj‘ubeh}(h]h ]h"]h$]h&]uh1jhjݑhKhjubj)}(hL``user_flags`` See :c:type:`i915_gem_context.user_flags ` h](j$)}(h``user_flags``h]j*)}(hj#h]h user_flags}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj@)}(hhh]h)}(h`h](hSee }(hj<hhhNhNubh)}(h8:c:type:`i915_gem_context.user_flags `h]j*)}(hjFh]hi915_gem_context.user_flags}(hjHhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjDubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_gem_contextuh1hhj8hKhj<ubeh}(h]h ]h"]h$]h&]uh1hhj8hKhj9ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj8hKhjubj)}(hB``sched`` See :c:type:`i915_gem_context.sched ` h](j$)}(h ``sched``h]j*)}(hj{h]hsched}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjyubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjuubj@)}(hhh]h)}(h7See :c:type:`i915_gem_context.sched `h](hSee }(hjhhhNhNubh)}(h3:c:type:`i915_gem_context.sched `h]j*)}(hjh]hi915_gem_context.sched}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_gem_contextuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjuubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h<``num_user_engines`` Number of user-specified engines or -1 h](j$)}(h``num_user_engines``h]j*)}(hjӒh]hnum_user_engines}(hjՒhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjђubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj͒ubj@)}(hhh]h)}(h&Number of user-specified engines or -1h]h&Number of user-specified engines or -1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hj͒ubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h(``user_engines`` User-specified engines h](j$)}(h``user_engines``h]j*)}(hj h]h user_engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj@)}(hhh]h)}(hUser-specified enginesh]hUser-specified engines}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hKhj"ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj!hKhjubj)}(hB``legacy_rcs_sseu`` Client-set SSEU parameters for the legacy RCS h](j$)}(h``legacy_rcs_sseu``h]j*)}(hjEh]hlegacy_rcs_sseu}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjCubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj?ubj@)}(hhh]h)}(h-Client-set SSEU parameters for the legacy RCSh]h-Client-set SSEU parameters for the legacy RCS}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhKhj[ubah}(h]h ]h"]h$]h&]uh1j?hj?ubeh}(h]h ]h"]h$]h&]uh1jhjZhKhjubj)}(hR``single_timeline`` See See :c:type:`i915_gem_context.syncobj ` h](j$)}(h``single_timeline``h]j*)}(hj~h]hsingle_timeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj|ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjxubj@)}(hhh]h)}(h=See See :c:type:`i915_gem_context.syncobj `h](hSee See }(hjhhhNhNubh)}(h5:c:type:`i915_gem_context.syncobj `h]j*)}(hjh]hi915_gem_context.syncobj}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_gem_contextuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjxubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hd``uses_protected_content`` See :c:type:`i915_gem_context.uses_protected_content ` h](j$)}(h``uses_protected_content``h]j*)}(hj֓h]huses_protected_content}(hjؓhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjԓubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjГubj@)}(hhh]h)}(hHSee :c:type:`i915_gem_context.uses_protected_content `h](hSee }(hjhhhNhNubh)}(hD:c:type:`i915_gem_context.uses_protected_content `h]j*)}(hjh]h'i915_gem_context.uses_protected_content}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_gem_contextuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjГubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hM``pxp_wakeref`` See :c:type:`i915_gem_context.pxp_wakeref `h](j$)}(h``pxp_wakeref``h]j*)}(hj.h]h pxp_wakeref}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj,ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj(ubj@)}(hhh]h)}(h=See :c:type:`i915_gem_context.pxp_wakeref `h](hSee }(hjGhhhNhNubh)}(h9:c:type:`i915_gem_context.pxp_wakeref `h]j*)}(hjQh]hi915_gem_context.pxp_wakeref}(hjShhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjOubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_gem_contextuh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjGubeh}(h]h ]h"]h$]h&]uh1hhjnhKhjDubah}(h]h ]h"]h$]h&]uh1j?hj(ubeh}(h]h ]h"]h$]h&]uh1jhjChKhjubeh}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjȈhhhjhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubh)}(hXThe struct i915_gem_proto_context represents the creation parameters for a struct i915_gem_context. This is used to gather parameters provided either through creation flags or via SET_CONTEXT_PARAM so that, when we create the final i915_gem_context, those parameters can be immutable.h]hXThe struct i915_gem_proto_context represents the creation parameters for a struct i915_gem_context. This is used to gather parameters provided either through creation flags or via SET_CONTEXT_PARAM so that, when we create the final i915_gem_context, those parameters can be immutable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubh)}(hXcThe context uAPI allows for two methods of setting context parameters: SET_CONTEXT_PARAM and CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called at any time while the later happens as part of GEM_CONTEXT_CREATE. When these were initially added, Currently, everything settable via one is settable via the other. While some params are fairly simple and setting them on a live context is harmless such the context priority, others are far trickier such as the VM or the set of engines. To avoid some truly nasty race conditions, we don't allow setting the VM or the set of engines on live contexts.h]hXeThe context uAPI allows for two methods of setting context parameters: SET_CONTEXT_PARAM and CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called at any time while the later happens as part of GEM_CONTEXT_CREATE. When these were initially added, Currently, everything settable via one is settable via the other. While some params are fairly simple and setting them on a live context is harmless such the context priority, others are far trickier such as the VM or the set of engines. To avoid some truly nasty race conditions, we don’t allow setting the VM or the set of engines on live contexts.l}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubh)}(hX The way we dealt with this without breaking older userspace that sets the VM or engine set via SET_CONTEXT_PARAM is to delay the creation of the actual context until after the client is done configuring it with SET_CONTEXT_PARAM. From the perspective of the client, it has the same u32 context ID the whole time. From the perspective of i915, however, it's an i915_gem_proto_context right up until the point where we attempt to do something which the proto-context can't handle at which point the real context gets created.h]hXThe way we dealt with this without breaking older userspace that sets the VM or engine set via SET_CONTEXT_PARAM is to delay the creation of the actual context until after the client is done configuring it with SET_CONTEXT_PARAM. From the perspective of the client, it has the same u32 context ID the whole time. From the perspective of i915, however, it’s an i915_gem_proto_context right up until the point where we attempt to do something which the proto-context can’t handle at which point the real context gets created.}(hjĔhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubh)}(hXThis is accomplished via a little xarray dance. When GEM_CONTEXT_CREATE is called, we create a proto-context, reserve a slot in context_xa but leave it NULL, the proto-context in the corresponding slot in proto_context_xa. Then, whenever we go to look up a context, we first check context_xa. If it's there, we return the i915_gem_context and we're done. If it's not, we look in proto_context_xa and, if we find it there, we create the actual context and kill the proto-context.h]hXThis is accomplished via a little xarray dance. When GEM_CONTEXT_CREATE is called, we create a proto-context, reserve a slot in context_xa but leave it NULL, the proto-context in the corresponding slot in proto_context_xa. Then, whenever we go to look up a context, we first check context_xa. If it’s there, we return the i915_gem_context and we’re done. If it’s not, we look in proto_context_xa and, if we find it there, we create the actual context and kill the proto-context.}(hjӔhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubh)}(hAt the time we made this change (April, 2021), we did a fairly complete audit of existing userspace to ensure this wouldn't break anything:h]hAt the time we made this change (April, 2021), we did a fairly complete audit of existing userspace to ensure this wouldn’t break anything:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubjgd)}(hX- Mesa/i965 didn't use the engines or VM APIs at all - Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API. - Mesa/iris didn't use the engines or VM APIs at all - The open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE. - The media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that. h]j:)}(hhh](j:)}(h3Mesa/i965 didn't use the engines or VM APIs at all h]h)}(h2Mesa/i965 didn't use the engines or VM APIs at allh]h4Mesa/i965 didn’t use the engines or VM APIs at all}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h]Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API. h]h)}(h\Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API.h]h^Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn’t use the VM API.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h3Mesa/iris didn't use the engines or VM APIs at all h]h)}(h2Mesa/iris didn't use the engines or VM APIs at allh]h4Mesa/iris didn’t use the engines or VM APIs at all}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj*ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hThe open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE. h]h)}(hThe open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE.h]hThe open-source compute-runtime didn’t yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjCubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that. h]h)}(hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that.h]hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj\ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j;j;uh1j:hj hKhjubah}(h]h ]h"]h$]h&]uh1jfdhj hKhjȈhhubh)}(hXiIn order for this dance to work properly, any modification to an i915_gem_proto_context that is exposed to the client via drm_i915_file_private::proto_context_xa must be guarded by drm_i915_file_private::proto_context_lock. The exception is when a proto-context has not yet been exposed such as when handling CONTEXT_CREATE_SET_PARAM during GEM_CONTEXT_CREATE.h]hXiIn order for this dance to work properly, any modification to an i915_gem_proto_context that is exposed to the client via drm_i915_file_private::proto_context_xa must be guarded by drm_i915_file_private::proto_context_lock. The exception is when a proto-context has not yet been exposed such as when handling CONTEXT_CREATE_SET_PARAM during GEM_CONTEXT_CREATE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_gem_context (C struct)c.i915_gem_contexthNtauh1jhjȈhhhjhNubj)}(hhh](j)}(hi915_gem_contexth]j)}(hstruct i915_gem_contexth](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhKubj)}(hi915_gem_contexth]j)}(hjh]hi915_gem_context}(hjɕhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjŕubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h client stateh]h client state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jhhhjȈhjhNubj)}(hX'**Definition**:: struct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; }; **Members** ``i915`` i915 device backpointer ``file_priv`` owning file descriptor ``engines`` User defined engines for this context Various uAPI offer the ability to lookup up an index from this array to select an engine operate on. Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines. Execbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index. User defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set). ``engines_mutex`` guards writes to engines ``syncobj`` Shared timeline syncobj When the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care. ``vm`` unique address space (GTT) In full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others. In other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT. ``pid`` process id of creator Note that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated. ``link`` place with :c:type:`drm_i915_private.context_list ` ``client`` struct i915_drm_client ``client_link`` for linking onto :c:type:`i915_drm_client.ctx_list ` ``ref`` reference count A reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access. ``release_work`` Work item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context. FIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock. ``rcu`` rcu_head for deferred freeing. ``user_flags`` small set of booleans controlled by the user ``flags`` small set of booleans ``uses_protected_content`` context uses PXP-encrypted objects. This flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts. ``pxp_wakeref`` wakeref to keep the device awake when PXP is in use PXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics. ``mutex`` guards everything that isn't engines or handles_vma ``sched`` scheduler parameters ``guilty_count`` How many times this context has caused a GPU hang. ``active_count`` How many times this context was active during a GPU hang, but did not cause it. ``hang_timestamp`` The last time(s) this context caused a GPU hang ``remap_slice`` Bitmask of cache lines that need remapping ``handles_vma`` rbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT) ``lut_mutex`` Locks handles_vma ``name`` arbitrary name, used for user debug A name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages. ``stale`` tracks stale engines to be destroyed ``stale.lock`` guards engines ``stale.engines`` list of stale enginesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubjA#)}(hXstruct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; };h]hXstruct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; };}hj(sbah}(h]h ]h"]h$]h&]j5j6uh1j@#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(h **Members**h]j)}(hj9h]hMembers}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM hjubj)}(hhh](j)}(h!``i915`` i915 device backpointer h](j$)}(h``i915``h]j*)}(hjXh]hi915}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjVubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjRubj@)}(hhh]h)}(hi915 device backpointerh]hi915 device backpointer}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhKhjnubah}(h]h ]h"]h$]h&]uh1j?hjRubeh}(h]h ]h"]h$]h&]uh1jhjmhKhjOubj)}(h%``file_priv`` owning file descriptor h](j$)}(h ``file_priv``h]j*)}(hjh]h file_priv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj@)}(hhh]h)}(howning file descriptorh]howning file descriptor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjOubj)}(hX``engines`` User defined engines for this context Various uAPI offer the ability to lookup up an index from this array to select an engine operate on. Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines. Execbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index. User defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set). h](j$)}(h ``engines``h]j*)}(hjʖh]hengines}(hj̖hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjȖubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjĖubj@)}(hhh](h)}(h%User defined engines for this contexth]h%User defined engines for this context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hdVarious uAPI offer the ability to lookup up an index from this array to select an engine operate on.h]hdVarious uAPI offer the ability to lookup up an index from this array to select an engine operate on.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(h{Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines.h]h{Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hXExecbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index.h]hXExecbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hVUser defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set).h]hVUser defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubeh}(h]h ]h"]h$]h&]uh1j?hjĖubeh}(h]h ]h"]h$]h&]uh1jhjߖhKhjOubj)}(h+``engines_mutex`` guards writes to engines h](j$)}(h``engines_mutex``h]j*)}(hj@h]h engines_mutex}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj>ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj:ubj@)}(hhh]h)}(hguards writes to enginesh]hguards writes to engines}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjVubah}(h]h ]h"]h$]h&]uh1j?hj:ubeh}(h]h ]h"]h$]h&]uh1jhjUhMhjOubj)}(hX``syncobj`` Shared timeline syncobj When the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care. h](j$)}(h ``syncobj``h]j*)}(hjyh]hsyncobj}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjwubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjsubj@)}(hhh](h)}(hShared timeline syncobjh]hShared timeline syncobj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubh)}(hXWhen the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care.h]hXWhen the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn’t provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that’s not likely to yield well- defined results anyway so we choose to not care.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubeh}(h]h ]h"]h$]h&]uh1j?hjsubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(hX``vm`` unique address space (GTT) In full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others. In other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT. h](j$)}(h``vm``h]j*)}(hj—h]hvm}(hjėhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj@)}(hhh](h)}(hunique address space (GTT)h]hunique address space (GTT)}(hjۗhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjؗubh)}(hvIn full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others.h]hvIn full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjؗubh)}(hgIn other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT.h]hgIn other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjؗubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjחhMhjOubj)}(hX``pid`` process id of creator Note that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated. h](j$)}(h``pid``h]j*)}(hjh]hpid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM$hjubj@)}(hhh](h)}(hprocess id of creatorh]hprocess id of creator}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj0ubh)}(hNote that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated.h]hNote that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM!hj0ubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj/hM$hjOubj)}(hO``link`` place with :c:type:`drm_i915_private.context_list ` h](j$)}(h``link``h]j*)}(hjch]hlink}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjaubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM(hj]ubj@)}(hhh]h)}(hEplace with :c:type:`drm_i915_private.context_list `h](h place with }(hj|hhhNhNubh)}(h::c:type:`drm_i915_private.context_list `h]j*)}(hjh]hdrm_i915_private.context_list}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_privateuh1hhjxhM(hj|ubeh}(h]h ]h"]h$]h&]uh1hhjxhM(hjyubah}(h]h ]h"]h$]h&]uh1j?hj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhM(hjOubj)}(h"``client`` struct i915_drm_client h](j$)}(h ``client``h]j*)}(hjh]hclient}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM+hjubj@)}(hhh]h)}(hstruct i915_drm_clienth]hstruct i915_drm_client}(hjԘhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjИhM+hjјubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjИhM+hjOubj)}(hV``client_link`` for linking onto :c:type:`i915_drm_client.ctx_list ` h](j$)}(h``client_link``h]j*)}(hjh]h client_link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM.hjubj@)}(hhh]h)}(hEfor linking onto :c:type:`i915_drm_client.ctx_list `h](hfor linking onto }(hj hhhNhNubh)}(h4:c:type:`i915_drm_client.ctx_list `h]j*)}(hjh]hi915_drm_client.ctx_list}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_drm_clientuh1hhj hM.hj ubeh}(h]h ]h"]h$]h&]uh1hhj hM.hj ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hM.hjOubj)}(hX9``ref`` reference count A reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access. h](j$)}(h``ref``h]j*)}(hjLh]href}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjJubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM8hjFubj@)}(hhh](h)}(hreference counth]hreference count}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM2hjbubh)}(hXA reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access.h]hXA reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM4hjbubeh}(h]h ]h"]h$]h&]uh1j?hjFubeh}(h]h ]h"]h$]h&]uh1jhjahM8hjOubj)}(hX```release_work`` Work item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context. FIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock. h](j$)}(h``release_work``h]j*)}(hjh]h release_work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMBhjubj@)}(hhh](h)}(heWork item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context.h]heWork item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM=hjubh)}(hFIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock.h](h(FIXME: The only real reason for this is }(hjhhhNhNubh)}(h3:c:type:`i915_gem_engines.fence `h]j*)}(hjǙh]hi915_gem_engines.fence}(hjəhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjřubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_gem_enginesuh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM@hjubh, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM@hjubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMBhjOubj)}(h'``rcu`` rcu_head for deferred freeing. h](j$)}(h``rcu``h]j*)}(hjh]hrcu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMIhjubj@)}(hhh]h)}(hrcu_head for deferred freeing.h]hrcu_head for deferred freeing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMIhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMIhjOubj)}(h<``user_flags`` small set of booleans controlled by the user h](j$)}(h``user_flags``h]j*)}(hj:h]h user_flags}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj8ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMNhj4ubj@)}(hhh]h)}(h,small set of booleans controlled by the userh]h,small set of booleans controlled by the user}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhMNhjPubah}(h]h ]h"]h$]h&]uh1j?hj4ubeh}(h]h ]h"]h$]h&]uh1jhjOhMNhjOubj)}(h ``flags`` small set of booleans h](j$)}(h ``flags``h]j*)}(hjsh]hflags}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjqubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMXhjmubj@)}(hhh]h)}(hsmall set of booleansh]hsmall set of booleans}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMXhjubah}(h]h ]h"]h$]h&]uh1j?hjmubeh}(h]h ]h"]h$]h&]uh1jhjhMXhjOubj)}(hX4``uses_protected_content`` context uses PXP-encrypted objects. This flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts. h](j$)}(h``uses_protected_content``h]j*)}(hjh]huses_protected_content}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMdhjubj@)}(hhh](h)}(h#context uses PXP-encrypted objects.h]h#context uses PXP-encrypted objects.}(hjŚhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM_hjšubh)}(hThis flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts.h]hThis flag can only be set at ctx creation time and it’s immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts.}(hjԚhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMahjšubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMdhjOubj)}(hX``pxp_wakeref`` wakeref to keep the device awake when PXP is in use PXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics. h](j$)}(h``pxp_wakeref``h]j*)}(hjh]h pxp_wakeref}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMphjubj@)}(hhh](h)}(h3wakeref to keep the device awake when PXP is in useh]h3wakeref to keep the device awake when PXP is in use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMihj ubh)}(hXgPXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics.h]hXiPXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn’t worsen our power metrics.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMkhj ubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hMphjOubj)}(h>``mutex`` guards everything that isn't engines or handles_vma h](j$)}(h ``mutex``h]j*)}(hj>h]hmutex}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj<ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMthj8ubj@)}(hhh]h)}(h3guards everything that isn't engines or handles_vmah]h5guards everything that isn’t engines or handles_vma}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMthjTubah}(h]h ]h"]h$]h&]uh1j?hj8ubeh}(h]h ]h"]h$]h&]uh1jhjShMthjOubj)}(h``sched`` scheduler parameters h](j$)}(h ``sched``h]j*)}(hjwh]hsched}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjuubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMwhjqubj@)}(hhh]h)}(hscheduler parametersh]hscheduler parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMwhjubah}(h]h ]h"]h$]h&]uh1j?hjqubeh}(h]h ]h"]h$]h&]uh1jhjhMwhjOubj)}(hD``guilty_count`` How many times this context has caused a GPU hang. h](j$)}(h``guilty_count``h]j*)}(hjh]h guilty_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMzhjubj@)}(hhh]h)}(h2How many times this context has caused a GPU hang.h]h2How many times this context has caused a GPU hang.}(hjɛhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjśhMzhjƛubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjśhMzhjOubj)}(ha``active_count`` How many times this context was active during a GPU hang, but did not cause it. h](j$)}(h``active_count``h]j*)}(hjh]h active_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM~hjubj@)}(hhh]h)}(hOHow many times this context was active during a GPU hang, but did not cause it.h]hOHow many times this context was active during a GPU hang, but did not cause it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM}hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM~hjOubj)}(hC``hang_timestamp`` The last time(s) this context caused a GPU hang h](j$)}(h``hang_timestamp``h]j*)}(hj#h]hhang_timestamp}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj@)}(hhh]h)}(h/The last time(s) this context caused a GPU hangh]h/The last time(s) this context caused a GPU hang}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj9ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj8hMhjOubj)}(h;``remap_slice`` Bitmask of cache lines that need remapping h](j$)}(h``remap_slice``h]j*)}(hj\h]h remap_slice}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjZubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjVubj@)}(hhh]h)}(h*Bitmask of cache lines that need remappingh]h*Bitmask of cache lines that need remapping}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhMhjrubah}(h]h ]h"]h$]h&]uh1j?hjVubeh}(h]h ]h"]h$]h&]uh1jhjqhMhjOubj)}(h``handles_vma`` rbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT) h](j$)}(h``handles_vma``h]j*)}(hjh]h handles_vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj@)}(hhh]h)}(hrbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT)h]hrbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(h ``lut_mutex`` Locks handles_vma h](j$)}(h ``lut_mutex``h]j*)}(hjϜh]h lut_mutex}(hjќhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj͜ubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjɜubj@)}(hhh]h)}(hLocks handles_vmah]hLocks handles_vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjɜubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(h``name`` arbitrary name, used for user debug A name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages. h](j$)}(h``name``h]j*)}(hjh]hname}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj@)}(hhh](h)}(h#arbitrary name, used for user debugh]h#arbitrary name, used for user debug}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubh)}(hA name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages.h]hA name is constructed for the context from the creator’s process name, pid and user handle in order to uniquely identify the context in messages.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(h/``stale`` tracks stale engines to be destroyed h](j$)}(h ``stale``h]j*)}(hjQh]hstale}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjOubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjKubj@)}(hhh]h)}(h$tracks stale engines to be destroyedh]h$tracks stale engines to be destroyed}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMhjgubah}(h]h ]h"]h$]h&]uh1j?hjKubeh}(h]h ]h"]h$]h&]uh1jhjfhMhjOubj)}(h``stale.lock`` guards engines h](j$)}(h``stale.lock``h]j*)}(hjh]h stale.lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj@)}(hhh]h)}(hguards enginesh]hguards engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(h'``stale.engines`` list of stale enginesh](j$)}(h``stale.engines``h]j*)}(hjÝh]h stale.engines}(hjŝhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj@)}(hhh]h)}(hlist of stale enginesh]hlist of stale engines}(hjܝhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjٝubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj؝hMhjOubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjȈhhhjhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjȈhhubh)}(hzThe struct i915_gem_context represents the combined view of the driver and logical hardware state for a particular client.h]hzThe struct i915_gem_context represents the combined view of the driver and logical hardware state for a particular client.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:242: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjȈhhubh)}(hXUserspace submits commands to be executed on the GPU as an instruction stream within a GEM object we call a batchbuffer. This instructions may refer to other GEM objects containing auxiliary state such as kernels, samplers, render targets and even secondary batchbuffers. Userspace does not know where in the GPU memory these objects reside and so before the batchbuffer is passed to the GPU for execution, those addresses in the batchbuffer and auxiliary objects are updated. This is known as relocation, or patching. To try and avoid having to relocate each object on the next execution, userspace is told the location of those objects in this pass, but this remains just a hint as the kernel may choose a new location for any object in the future.h]hXUserspace submits commands to be executed on the GPU as an instruction stream within a GEM object we call a batchbuffer. This instructions may refer to other GEM objects containing auxiliary state such as kernels, samplers, render targets and even secondary batchbuffers. Userspace does not know where in the GPU memory these objects reside and so before the batchbuffer is passed to the GPU for execution, those addresses in the batchbuffer and auxiliary objects are updated. This is known as relocation, or patching. To try and avoid having to relocate each object on the next execution, userspace is told the location of those objects in this pass, but this remains just a hint as the kernel may choose a new location for any object in the future.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKXhjȈhhubh)}(hAt the level of talking to the hardware, submitting a batchbuffer for the GPU to execute is to add content to a buffer from which the HW command streamer is reading.h]hAt the level of talking to the hardware, submitting a batchbuffer for the GPU to execute is to add content to a buffer from which the HW command streamer is reading.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKdhjȈhhubj;)}(hhh](j:)}(hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items. h]h)}(hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items.h]hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhhjLubah}(h]h ]h"]h$]h&]uh1j:hjIubj:)}(h2Add a command to invalidate caches to the buffer. h]h)}(h1Add a command to invalidate caches to the buffer.h]h1Add a command to invalidate caches to the buffer.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKlhjeubah}(h]h ]h"]h$]h&]uh1j:hjIubj:)}(hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed. h]h)}(hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed.h]hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKnhj~ubah}(h]h ]h"]h$]h&]uh1j:hjIubj:)}(h$Add a pipeline flush to the buffer. h]h)}(h#Add a pipeline flush to the buffer.h]h#Add a pipeline flush to the buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKrhjubah}(h]h ]h"]h$]h&]uh1j:hjIubj:)}(hX4Add a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, ``i915_request::global_seqno``; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer. h]h)}(hX3Add a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, ``i915_request::global_seqno``; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer.h](hAdd a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, }(hjhhhNhNubj*)}(h``i915_request::global_seqno``h]hi915_request::global_seqno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubho; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKthjubah}(h]h ]h"]h$]h&]uh1j:hjIubj:)}(hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed. h]h)}(hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed.h]hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed.}(hjߞhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKzhj۞ubah}(h]h ]h"]h$]h&]uh1j:hjIubj:)}(hcInform the hardware of the additional commands added to the buffer (by updating the tail pointer). h]h)}(hbInform the hardware of the additional commands added to the buffer (by updating the tail pointer).h]hbInform the hardware of the additional commands added to the buffer (by updating the tail pointer).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chK~hjubah}(h]h ]h"]h$]h&]uh1j:hjIubeh}(h]h ]h"]h$]h&]j;j;j;hj;j;uh1j;hjȈhhhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chNubh)}(hGProcessing an execbuf ioctl is conceptually split up into a few phases.h]hGProcessing an execbuf ioctl is conceptually split up into a few phases.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjȈhhubj;)}(hhh](j:)}(hBValidation - Ensure all the pointers, handles and flags are valid.h]h)}(hj(h]hBValidation - Ensure all the pointers, handles and flags are valid.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj&ubah}(h]h ]h"]h$]h&]uh1j:hj#ubj:)}(h7Reservation - Assign GPU address space for every objecth]h)}(hj@h]h7Reservation - Assign GPU address space for every object}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj>ubah}(h]h ]h"]h$]h&]uh1j:hj#ubj:)}(hARelocation - Update any addresses to point to the final locationsh]h)}(hjXh]hARelocation - Update any addresses to point to the final locations}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjVubah}(h]h ]h"]h$]h&]uh1j:hj#ubj:)}(hBSerialisation - Order the request with respect to its dependenciesh]h)}(hjph]hBSerialisation - Order the request with respect to its dependencies}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjnubah}(h]h ]h"]h$]h&]uh1j:hj#ubj:)}(h=Construction - Construct a request to execute the batchbufferh]h)}(hjh]h=Construction - Construct a request to execute the batchbuffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjubah}(h]h ]h"]h$]h&]uh1j:hj#ubj:)}(h3Submission (at some point in the future execution) h]h)}(h2Submission (at some point in the future execution)h]h2Submission (at some point in the future execution)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjubah}(h]h ]h"]h$]h&]uh1j:hj#ubeh}(h]h ]h"]h$]h&]j;j;j;hj;j;uh1j;hjȈhhhjhNubh)}(hXReserving resources for the execbuf is the most complicated phase. We neither want to have to migrate the object in the address space, nor do we want to have to update any relocations pointing to this object. Ideally, we want to leave the object where it is and for all the existing relocations to match. If the object is given a new address, or if userspace thinks the object is elsewhere, we have to parse all the relocation entries and update the addresses. Userspace can set the I915_EXEC_NO_RELOC flag to hint that all the target addresses in all of its objects match the value in the relocation entries and that they all match the presumed offsets given by the list of execbuffer objects. Using this knowledge, we know that if we haven't moved any buffers, all the relocation entries are valid and we can skip the update. (If userspace is wrong, the likely outcome is an impromptu GPU hang.) The requirement for using I915_EXEC_NO_RELOC are:h]hXReserving resources for the execbuf is the most complicated phase. We neither want to have to migrate the object in the address space, nor do we want to have to update any relocations pointing to this object. Ideally, we want to leave the object where it is and for all the existing relocations to match. If the object is given a new address, or if userspace thinks the object is elsewhere, we have to parse all the relocation entries and update the addresses. Userspace can set the I915_EXEC_NO_RELOC flag to hint that all the target addresses in all of its objects match the value in the relocation entries and that they all match the presumed offsets given by the list of execbuffer objects. Using this knowledge, we know that if we haven’t moved any buffers, all the relocation entries are valid and we can skip the update. (If userspace is wrong, the likely outcome is an impromptu GPU hang.) The requirement for using I915_EXEC_NO_RELOC are:#}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjȈhhubjgd)}(hX[The addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset. Any render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE. To avoid stalling, execobject.offset should match the current address of that object within the active context. h](h)}(hThe addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset.h]hThe addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset.}(hjПhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj̟ubh)}(hRAny render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE.h]hRAny render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE.}(hjߟhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj̟ubh)}(hoTo avoid stalling, execobject.offset should match the current address of that object within the active context.h]hoTo avoid stalling, execobject.offset should match the current address of that object within the active context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj̟ubeh}(h]h ]h"]h$]h&]uh1jfdhjޟhKhjȈhhubh)}(hXTThe reservation is done is multiple phases. First we try and keep any object already bound in its current location - so as long as meets the constraints imposed by the new execbuffer. Any object left unbound after the first pass is then fitted into any available idle space. If an object does not fit, all objects are removed from the reservation and the process rerun after sorting the objects into a priority order (more difficult to fit objects are tried first). Failing that, the entire VM is cleared and we try to fit the execbuf once last time before concluding that it simply will not fit.h]hXTThe reservation is done is multiple phases. First we try and keep any object already bound in its current location - so as long as meets the constraints imposed by the new execbuffer. Any object left unbound after the first pass is then fitted into any available idle space. If an object does not fit, all objects are removed from the reservation and the process rerun after sorting the objects into a priority order (more difficult to fit objects are tried first). Failing that, the entire VM is cleared and we try to fit the execbuf once last time before concluding that it simply will not fit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjȈhhubh)}(hXBA small complication to all of this is that we allow userspace not only to specify an alignment and a size for the object in the address space, but we also allow userspace to specify the exact offset. This objects are simpler to place (the location is known a priori) all we have to do is make sure the space is available.h]hXBA small complication to all of this is that we allow userspace not only to specify an alignment and a size for the object in the address space, but we also allow userspace to specify the exact offset. This objects are simpler to place (the location is known a priori) all we have to do is make sure the space is available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjȈhhubh)}(hX.Once all the objects are in place, patching up the buried pointers to point to the final locations is a fairly simple job of walking over the relocation entry arrays, looking up the right address and rewriting the value into the object. Simple! ... The relocation entries are stored in user memory and so to access them we have to copy them into a local buffer. That copy has to avoid taking any pagefaults as they may lead back to a GEM object requiring the vm->mutex (i.e. recursive deadlock). So once again we split the relocation into multiple passes. First we try to do everything within an atomic context (avoid the pagefaults) which requires that we never wait. If we detect that we may wait, or if we need to fault, then we have to fallback to a slower path. The slowpath has to drop the mutex. (Can you hear alarm bells yet?) Dropping the mutex means that we lose all the state we have built up so far for the execbuf and we must reset any global data. However, we do leave the objects pinned in their final locations - which is a potential issue for concurrent execbufs. Once we have left the mutex, we can allocate and copy all the relocation entries into a large array at our leisure, reacquire the mutex, reclaim all the objects and other state and then proceed to update any incorrect addresses with the objects.h]hX.Once all the objects are in place, patching up the buried pointers to point to the final locations is a fairly simple job of walking over the relocation entry arrays, looking up the right address and rewriting the value into the object. Simple! ... The relocation entries are stored in user memory and so to access them we have to copy them into a local buffer. That copy has to avoid taking any pagefaults as they may lead back to a GEM object requiring the vm->mutex (i.e. recursive deadlock). So once again we split the relocation into multiple passes. First we try to do everything within an atomic context (avoid the pagefaults) which requires that we never wait. If we detect that we may wait, or if we need to fault, then we have to fallback to a slower path. The slowpath has to drop the mutex. (Can you hear alarm bells yet?) Dropping the mutex means that we lose all the state we have built up so far for the execbuf and we must reset any global data. However, we do leave the objects pinned in their final locations - which is a potential issue for concurrent execbufs. Once we have left the mutex, we can allocate and copy all the relocation entries into a large array at our leisure, reacquire the mutex, reclaim all the objects and other state and then proceed to update any incorrect addresses with the objects.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjȈhhubh)}(hXAs we process the relocation entries, we maintain a record of whether the object is being written to. Using NORELOC, we expect userspace to provide this information instead. We also check whether we can skip the relocation by comparing the expected value inside the relocation entry with the target's final address. If they differ, we have to map the current object and rewrite the 4 or 8 byte pointer within.h]hXAs we process the relocation entries, we maintain a record of whether the object is being written to. Using NORELOC, we expect userspace to provide this information instead. We also check whether we can skip the relocation by comparing the expected value inside the relocation entry with the target’s final address. If they differ, we have to map the current object and rewrite the 4 or 8 byte pointer within.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjȈhhubh)}(hXSerialising an execbuf is quite simple according to the rules of the GEM ABI. Execution within each context is ordered by the order of submission. Writes to any GEM object are in order of submission and are exclusive. Reads from a GEM object are unordered with respect to other reads, but ordered by writes. A write submitted after a read cannot occur before the read, and similarly any read submitted after a write cannot occur before the write. Writes are ordered between engines such that only one write occurs at any time (completing any reads beforehand) - using semaphores where available and CPU serialisation otherwise. Other GEM access obey the same rules, any write (either via mmaps using set-domain, or via pwrite) must flush all GPU reads before starting, and any read (either using set-domain or pread) must flush all GPU writes before starting. (Note we only employ a barrier before, we currently rely on userspace not concurrently starting a new execution whilst reading or writing to an object. This may be an advantage or not depending on how much you trust userspace not to shoot themselves in the foot.) Serialisation may just result in the request being inserted into a DAG awaiting its turn, but most simple is to wait on the CPU until all dependencies are resolved.h]hXSerialising an execbuf is quite simple according to the rules of the GEM ABI. Execution within each context is ordered by the order of submission. Writes to any GEM object are in order of submission and are exclusive. Reads from a GEM object are unordered with respect to other reads, but ordered by writes. A write submitted after a read cannot occur before the read, and similarly any read submitted after a write cannot occur before the write. Writes are ordered between engines such that only one write occurs at any time (completing any reads beforehand) - using semaphores where available and CPU serialisation otherwise. Other GEM access obey the same rules, any write (either via mmaps using set-domain, or via pwrite) must flush all GPU reads before starting, and any read (either using set-domain or pread) must flush all GPU writes before starting. (Note we only employ a barrier before, we currently rely on userspace not concurrently starting a new execution whilst reading or writing to an object. This may be an advantage or not depending on how much you trust userspace not to shoot themselves in the foot.) Serialisation may just result in the request being inserted into a DAG awaiting its turn, but most simple is to wait on the CPU until all dependencies are resolved.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjȈhhubh)}(hX&After all of that, is just a matter of closing the request and handing it to the hardware (well, leaving it in a queue to be executed). However, we also offer the ability for batchbuffers to be run with elevated privileges so that they access otherwise hidden registers. (Used to adjust L3 cache etc.) Before any batch is given extra privileges we first must check that it contains no nefarious instructions, we check that each instruction is from our whitelist and all registers are also from an allowed list. We first copy the user's batchbuffer to a shadow (so that the user doesn't have access to it, either by the CPU or GPU as we scan it) and then parse each instruction. If everything is ok, we set a flag telling the hardware to run the batchbuffer in trusted mode, otherwise the ioctl is rejected.h]hX*After all of that, is just a matter of closing the request and handing it to the hardware (well, leaving it in a queue to be executed). However, we also offer the ability for batchbuffers to be run with elevated privileges so that they access otherwise hidden registers. (Used to adjust L3 cache etc.) Before any batch is given extra privileges we first must check that it contains no nefarious instructions, we check that each instruction is from our whitelist and all registers are also from an allowed list. We first copy the user’s batchbuffer to a shadow (so that the user doesn’t have access to it, either by the CPU or GPU as we scan it) and then parse each instruction. If everything is ok, we set a flag telling the hardware to run the batchbuffer in trusted mode, otherwise the ioctl is rejected.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:244: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjȈhhubeh}(h]user-batchbuffer-executionah ]h"]user batchbuffer executionah$]h&]uh1hhj.bhhhhhKubh)}(hhh](h)}(h Schedulingh]h Scheduling}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehhhhhKubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_sched_engine (C struct)c.i915_sched_enginehNtauh1jhjehhhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhNubj)}(hhh](j)}(hi915_sched_engineh]j)}(hstruct i915_sched_engineh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjhhhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhKubj)}(hi915_sched_engineh]j)}(hjh]hi915_sched_engine}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hscheduler engineh]hscheduler engine}(hjҠhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK_hjϠhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jhhhjehjhNubj)}(hXX **Definition**:: struct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); }; **Members** ``ref`` reference count of schedule engine object ``lock`` protects requests in priority lists, requests, hold and tasklet while running ``requests`` list of requests inflight on this schedule engine ``hold`` list of ready requests, but on hold ``tasklet`` softirq tasklet for submission ``default_priolist`` priority list for I915_PRIORITY_NORMAL ``queue_priority_hint`` Highest pending priority. When we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority. ``queue`` queue of requests, in priority lists ``no_priolist`` priority lists disabled ``private_data`` private data of the submission backend ``destroy`` destroy schedule engine / cleanup in backend ``disabled`` check if backend has disabled submission ``kick_backend`` kick backend after a request's priority has changed ``bump_inflight_request_prio`` update priority of an inflight request ``retire_inflight_request_prio`` indicate request is retired to priority tracking ``schedule`` adjust priority of request Call when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKchjubjA#)}(hXstruct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); };h]hXstruct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); };}hjsbah}(h]h ]h"]h$]h&]j5j6uh1j@#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKehjubh)}(h **Members**h]j)}(hj h]hMembers}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKxhjubj)}(hhh](j)}(h2``ref`` reference count of schedule engine object h](j$)}(h``ref``h]j*)}(hj?h]href}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj=ubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKlhj9ubj@)}(hhh]h)}(h)reference count of schedule engine objecth]h)reference count of schedule engine object}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThKlhjUubah}(h]h ]h"]h$]h&]uh1j?hj9ubeh}(h]h ]h"]h$]h&]uh1jhjThKlhj6ubj)}(hW``lock`` protects requests in priority lists, requests, hold and tasklet while running h](j$)}(h``lock``h]j*)}(hjxh]hlock}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjvubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKrhjrubj@)}(hhh]h)}(hMprotects requests in priority lists, requests, hold and tasklet while runningh]hMprotects requests in priority lists, requests, hold and tasklet while running}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKqhjubah}(h]h ]h"]h$]h&]uh1j?hjrubeh}(h]h ]h"]h$]h&]uh1jhjhKrhj6ubj)}(h?``requests`` list of requests inflight on this schedule engine h](j$)}(h ``requests``h]j*)}(hjh]hrequests}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKwhjubj@)}(hhh]h)}(h1list of requests inflight on this schedule engineh]h1list of requests inflight on this schedule engine}(hjˡhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjǡhKwhjȡubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjǡhKwhj6ubj)}(h-``hold`` list of ready requests, but on hold h](j$)}(h``hold``h]j*)}(hjh]hhold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK|hjubj@)}(hhh]h)}(h#list of ready requests, but on holdh]h#list of ready requests, but on hold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK|hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK|hj6ubj)}(h+``tasklet`` softirq tasklet for submission h](j$)}(h ``tasklet``h]j*)}(hj$h]htasklet}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj"ubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj@)}(hhh]h)}(hsoftirq tasklet for submissionh]hsoftirq tasklet for submission}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hKhj:ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj9hKhj6ubj)}(h<``default_priolist`` priority list for I915_PRIORITY_NORMAL h](j$)}(h``default_priolist``h]j*)}(hj]h]hdefault_priolist}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj[ubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjWubj@)}(hhh]h)}(h&priority list for I915_PRIORITY_NORMALh]h&priority list for I915_PRIORITY_NORMAL}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhKhjsubah}(h]h ]h"]h$]h&]uh1j?hjWubeh}(h]h ]h"]h$]h&]uh1jhjrhKhj6ubj)}(hX ``queue_priority_hint`` Highest pending priority. When we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority. h](j$)}(h``queue_priority_hint``h]j*)}(hjh]hqueue_priority_hint}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj@)}(hhh](h)}(hHighest pending priority.h]hHighest pending priority.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubh)}(hXWhen we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority.h]hXWhen we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj6ubj)}(h/``queue`` queue of requests, in priority lists h](j$)}(h ``queue``h]j*)}(hjߢh]hqueue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjݢubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhj٢ubj@)}(hhh]h)}(h$queue of requests, in priority listsh]h$queue of requests, in priority lists}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hj٢ubeh}(h]h ]h"]h$]h&]uh1jhjhKhj6ubj)}(h(``no_priolist`` priority lists disabled h](j$)}(h``no_priolist``h]j*)}(hjh]h no_priolist}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj@)}(hhh]h)}(hpriority lists disabledh]hpriority lists disabled}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hKhj.ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj-hKhj6ubj)}(h8``private_data`` private data of the submission backend h](j$)}(h``private_data``h]j*)}(hjQh]h private_data}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjOubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjKubj@)}(hhh]h)}(h&private data of the submission backendh]h&private data of the submission backend}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhKhjgubah}(h]h ]h"]h$]h&]uh1j?hjKubeh}(h]h ]h"]h$]h&]uh1jhjfhKhj6ubj)}(h9``destroy`` destroy schedule engine / cleanup in backend h](j$)}(h ``destroy``h]j*)}(hjh]hdestroy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj@)}(hhh]h)}(h,destroy schedule engine / cleanup in backendh]h,destroy schedule engine / cleanup in backend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj6ubj)}(h6``disabled`` check if backend has disabled submission h](j$)}(h ``disabled``h]j*)}(hjãh]hdisabled}(hjţhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj@)}(hhh]h)}(h(check if backend has disabled submissionh]h(check if backend has disabled submission}(hjܣhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjأhKhj٣ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjأhKhj6ubj)}(hE``kick_backend`` kick backend after a request's priority has changed h](j$)}(h``kick_backend``h]j*)}(hjh]h kick_backend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj@)}(hhh]h)}(h3kick backend after a request's priority has changedh]h5kick backend after a request’s priority has changed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj6ubj)}(hF``bump_inflight_request_prio`` update priority of an inflight request h](j$)}(h``bump_inflight_request_prio``h]j*)}(hj5h]hbump_inflight_request_prio}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj3ubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhj/ubj@)}(hhh]h)}(h&update priority of an inflight requesth]h&update priority of an inflight request}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhKhjKubah}(h]h ]h"]h$]h&]uh1j?hj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhKhj6ubj)}(hR``retire_inflight_request_prio`` indicate request is retired to priority tracking h](j$)}(h ``retire_inflight_request_prio``h]j*)}(hjnh]hretire_inflight_request_prio}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjlubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjhubj@)}(hhh]h)}(h0indicate request is retired to priority trackingh]h0indicate request is retired to priority tracking}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjhubeh}(h]h ]h"]h$]h&]uh1jhjhKhj6ubj)}(h``schedule`` adjust priority of request Call when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h](j$)}(h ``schedule``h]j*)}(hjh]hschedule}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#he/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj@)}(hhh](h)}(hadjust priority of requesth]hadjust priority of request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubh)}(hCall when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h]hCall when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!}(hjФhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj6ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjehhhjhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjehhubh)}(hA schedule engine represents a submission queue with different priority bands. It contains all the common state (relative to the backend) to queue, track, and submit a request.h]hA schedule engine represents a submission queue with different priority bands. It contains all the common state (relative to the backend) to queue, track, and submit a request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK`hjehhubh)}(hThis object at the moment is quite i915 specific but will transition into a container for the drm_gpu_scheduler plus a few other variables once the i915 is integrated with the DRM scheduler.h]hThis object at the moment is quite i915 specific but will transition into a container for the drm_gpu_scheduler plus a few other variables once the i915 is integrated with the DRM scheduler.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKdhjehhubeh}(h] schedulingah ]h"] schedulingah$]h&]uh1hhj.bhhhhhKubh)}(hhh](h)}(h2Logical Rings, Logical Ring Contexts and Execlistsh]h2Logical Rings, Logical Ring Contexts and Execlists}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhKubh)}(hMotivation: GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". These expanded contexts enable a number of new abilities, especially "Execlists" (also implemented in this file).h]hMotivation: GEN8 brings an expansion of the HW contexts: “Logical Ring Contexts”. These expanded contexts enable a number of new abilities, especially “Execlists” (also implemented in this file).}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhj6hhubh)}(hOne of the main differences with the legacy HW contexts is that logical ring contexts incorporate many more things to the context's state, like PDPs or ringbuffer control registers:h]hOne of the main differences with the legacy HW contexts is that logical ring contexts incorporate many more things to the context’s state, like PDPs or ringbuffer control registers:}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK hj6hhubh)}(hX The reason why PDPs are included in the context is straightforward: as PPGTTs (per-process GTTs) are actually per-context, having the PDPs contained there mean you don't need to do a ppgtt->switch_mm yourself, instead, the GPU will do it for you on the context switch.h]hXThe reason why PDPs are included in the context is straightforward: as PPGTTs (per-process GTTs) are actually per-context, having the PDPs contained there mean you don’t need to do a ppgtt->switch_mm yourself, instead, the GPU will do it for you on the context switch.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhj6hhubh)}(hXBut, what about the ringbuffer control registers (head, tail, etc..)? shouldn't we just need a set of those per engine command streamer? This is where the name "Logical Rings" starts to make sense: by virtualizing the rings, the engine cs shifts to a new "ring buffer" with every context switch. When you want to submit a workload to the GPU you: A) choose your context, B) find its appropriate virtualized ring, C) write commands to it and then, finally, D) tell the GPU to switch to that context.h]hXBut, what about the ringbuffer control registers (head, tail, etc..)? shouldn’t we just need a set of those per engine command streamer? This is where the name “Logical Rings” starts to make sense: by virtualizing the rings, the engine cs shifts to a new “ring buffer” with every context switch. When you want to submit a workload to the GPU you: A) choose your context, B) find its appropriate virtualized ring, C) write commands to it and then, finally, D) tell the GPU to switch to that context.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhj6hhubh)}(hInstead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch to a contexts is via a context execution list, ergo "Execlists".h]hInstead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch to a contexts is via a context execution list, ergo “Execlists”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhj6hhubh)}(h@LRC implementation: Regarding the creation of contexts, we have:h]h@LRC implementation: Regarding the creation of contexts, we have:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK hj6hhubj:)}(hhh](j:)}(hOne global default context.h]h)}(hjh]hOne global default context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK#hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h-One local default context for each opened fd.h]h)}(hjh]h-One local default context for each opened fd.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK$hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hhj6hhubh)}(hXWhen a request is committed, its commands (the BB start and any leading or trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer for the appropriate context. The tail pointer in the hardware context is not updated at this time, but instead, kept by the driver in the ringbuffer structure. A structure representing this request is added to a request queue for the appropriate engine: this structure contains a copy of the context's tail after the request was written to the ring buffer and a pointer to the context itself.h]hX!When a request is committed, its commands (the BB start and any leading or trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer for the appropriate context. The tail pointer in the hardware context is not updated at this time, but instead, kept by the driver in the ringbuffer structure. A structure representing this request is added to a request queue for the appropriate engine: this structure contains a copy of the context’s tail after the request was written to the ring buffer and a pointer to the context itself.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKChj6hhubh)}(hXQIf the engine's request queue was empty before the request was added, the queue is processed immediately. Otherwise the queue will be processed during a context switch interrupt. In any case, elements on the queue will get sent (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a globally unique 20-bits submission ID.h]hXUIf the engine’s request queue was empty before the request was added, the queue is processed immediately. Otherwise the queue will be processed during a context switch interrupt. In any case, elements on the queue will get sent (in pairs) to the GPU’s ExecLists Submit Port (ELSP, for short) with a globally unique 20-bits submission ID.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKLhj6hhubh)}(hXWhen execution of a request completes, the GPU updates the context status buffer with a context complete event and generates a context switch interrupt. During the interrupt handling, the driver examines the events in the buffer: for each context complete event, if the announced ID matches that on the head of the request queue, then that request is retired and removed from the queue.h]hXWhen execution of a request completes, the GPU updates the context status buffer with a context complete event and generates a context switch interrupt. During the interrupt handling, the driver examines the events in the buffer: for each context complete event, if the announced ID matches that on the head of the request queue, then that request is retired and removed from the queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKRhj6hhubh)}(hXAfter processing, if any requests were retired and the queue is not empty then a new execution list can be submitted. The two requests at the front of the queue are next to be submitted but since a context may not occur twice in an execution list, if subsequent requests have the same ID as the first then the two requests must be combined. This is done simply by discarding requests at the head of the queue until either only one requests is left (in which case we use a NULL second context) or the first two requests have unique IDs.h]hXAfter processing, if any requests were retired and the queue is not empty then a new execution list can be submitted. The two requests at the front of the queue are next to be submitted but since a context may not occur twice in an execution list, if subsequent requests have the same ID as the first then the two requests must be combined. This is done simply by discarding requests at the head of the queue until either only one requests is left (in which case we use a NULL second context) or the first two requests have unique IDs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKXhj6hhubh)}(hXBy always executing the first two requests in the queue the driver ensures that the GPU is kept as busy as possible. In the case where a single context completes but a second context is still executing, the request for this second context will be at the head of the queue when we remove the first one. This request will then be resubmitted along with a new request for a different context, which will cause the hardware to continue executing the second request and queue the new request (the GPU detects the condition of a context getting preempted with the same context and optimizes the context switch flow by not doing preemption, but just sampling the new tail pointer).h]hXBy always executing the first two requests in the queue the driver ensures that the GPU is kept as busy as possible. In the case where a single context completes but a second context is still executing, the request for this second context will be at the head of the queue when we remove the first one. This request will then be resubmitted along with a new request for a different context, which will cause the hardware to continue executing the second request and queue the new request (the GPU detects the condition of a context getting preempted with the same context and optimizes the context switch flow by not doing preemption, but just sampling the new tail pointer).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:255: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK`hj6hhubeh}(h]1logical-rings-logical-ring-contexts-and-execlistsah ]h"]2logical rings, logical ring contexts and execlistsah$]h&]uh1hhj.bhhhhhKubh)}(hhh](h)}(hGlobal GTT viewsh]hGlobal GTT views}(hjΦhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj˦hhhhhMubh)}(hBackground and previous stateh]hBackground and previous state}(hjܦhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhK&hj˦hhubh)}(hHistorically objects could exists (be bound) in global GTT space only as singular instances with a view representing all of the object's backing pages in a linear fashion. This view will be called a normal view.h]hHistorically objects could exists (be bound) in global GTT space only as singular instances with a view representing all of the object’s backing pages in a linear fashion. This view will be called a normal view.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhK(hj˦hhubh)}(hTo support multiple views of the same object, where the number of mapped pages is not equal to the backing store, or where the layout of the pages is not linear, concept of a GGTT view was added.h]hTo support multiple views of the same object, where the number of mapped pages is not equal to the backing store, or where the layout of the pages is not linear, concept of a GGTT view was added.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhK,hj˦hhubh)}(hOne example of an alternative view is a stereo display driven by a single image. In this case we would have a framebuffer looking like this (2x2 pages):h]hOne example of an alternative view is a stereo display driven by a single image. In this case we would have a framebuffer looking like this (2x2 pages):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhK0hj˦hhubjgd)}(h12 34 h]h)}(h12 34h]h12 34}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhK4hjubah}(h]h ]h"]h$]h&]uh1jfdhj*hK4hj˦hhubh)}(hAbove would represent a normal GGTT view as normally mapped for GPU or CPU rendering. In contrast, fed to the display engine would be an alternative view which could look something like this:h]hAbove would represent a normal GGTT view as normally mapped for GPU or CPU rendering. In contrast, fed to the display engine would be an alternative view which could look something like this:}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhK7hj˦hhubjgd)}(h 1212 3434 h]h)}(h 1212 3434h]h 1212 3434}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhK;hj@ubah}(h]h ]h"]h$]h&]uh1jfdhjRhK;hj˦hhubh)}(hlIn this example both the size and layout of pages in the alternative view is different from the normal view.h]hlIn this example both the size and layout of pages in the alternative view is different from the normal view.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhK>hj˦hhubh)}(hImplementation and usageh]hImplementation and usage}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKAhj˦hhubh)}(hqGGTT views are implemented using VMAs and are distinguished via enum i915_gtt_view_type and struct i915_gtt_view.h]hqGGTT views are implemented using VMAs and are distinguished via enum i915_gtt_view_type and struct i915_gtt_view.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKChj˦hhubh)}(hXA new flavour of core GEM functions which work with GGTT bound objects were added with the _ggtt_ infix, and sometimes with _view postfix to avoid renaming in large amounts of code. They take the struct i915_gtt_view parameter encapsulating all metadata required to implement a view.h]hXA new flavour of core GEM functions which work with GGTT bound objects were added with the _ggtt_ infix, and sometimes with _view postfix to avoid renaming in large amounts of code. They take the struct i915_gtt_view parameter encapsulating all metadata required to implement a view.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKFhj˦hhubh)}(hAs a helper for callers which are only interested in the normal view, globally const i915_gtt_view_normal singleton instance exists. All old core GEM API functions, the ones not taking the view parameter, are operating on, or with the normal GGTT view.h]hAs a helper for callers which are only interested in the normal view, globally const i915_gtt_view_normal singleton instance exists. All old core GEM API functions, the ones not taking the view parameter, are operating on, or with the normal GGTT view.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKKhj˦hhubh)}(h4Code wanting to add or use a new GGTT view needs to:h]h4Code wanting to add or use a new GGTT view needs to:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKPhj˦hhubj;)}(hhh](j:)}(h$Add a new enum with a suitable name.h]h)}(hjh]h$Add a new enum with a suitable name.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKRhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h?Extend the metadata in the i915_gtt_view structure if required.h]h)}(hjЧh]h?Extend the metadata in the i915_gtt_view structure if required.}(hjҧhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKShjΧubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h%Add support to i915_get_vma_pages(). h]h)}(h$Add support to i915_get_vma_pages().h]h$Add support to i915_get_vma_pages().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKThjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j;j;j;hj;j;uh1j;hj˦hhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhNubh)}(hNew views are required to build a scatter-gather table from within the i915_get_vma_pages function. This table is stored in the vma.gtt_view and exists for the lifetime of an VMA.h]hNew views are required to build a scatter-gather table from within the i915_get_vma_pages function. This table is stored in the vma.gtt_view and exists for the lifetime of an VMA.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKVhj˦hhubh)}(hCore API is designed to have copy semantics which means that passed in struct i915_gtt_view does not need to be persistent (left around after calling the core API functions).h]hCore API is designed to have copy semantics which means that passed in struct i915_gtt_view does not need to be persistent (left around after calling the core API functions).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/i915_vma_types.hhKZhj˦hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!i915_gem_gtt_reserve (C function)c.i915_gem_gtt_reservehNtauh1jhj˦hhhNhNubj)}(hhh](j)}(hint i915_gem_gtt_reserve (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h]j)}(hint i915_gem_gtt_reserve(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h](jn)}(hinth]hint}(hj=hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj9hhh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKGubj )}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj9hhhjKhKGubj)}(hi915_gem_gtt_reserveh]j)}(hi915_gem_gtt_reserveh]hi915_gem_gtt_reserve}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj9hhhjKhKGubj8)}(h(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h](j>)}(hstruct i915_address_space *vmh](jD)}(hjGh]hstruct}(hjzhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjvubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjvubh)}(hhh]j)}(hi915_address_spaceh]hi915_address_space}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jj`sbc.i915_gem_gtt_reserveasbuh1hhjvubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjvubj)}(hjh]h*}(hjƨhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(hvmh]hvm}(hjӨhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(hstruct i915_gem_ww_ctx *wwh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jc.i915_gem_gtt_reserveasbuh1hhjubj )}(h h]h }(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hwwh]hww}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(hstruct drm_mm_node *nodeh](jD)}(hjGh]hstruct}(hj\hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjXubj )}(h h]h }(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXubh)}(hhh]j)}(h drm_mm_nodeh]h drm_mm_node}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj|modnameN classnameNjj)}j]jc.i915_gem_gtt_reserveasbuh1hhjXubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj)}(hnodeh]hnode}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(hu64 sizeh](h)}(hhh]j)}(hu64h]hu64}(hjϩhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̩ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjѩmodnameN classnameNjj)}j]jc.i915_gem_gtt_reserveasbuh1hhjȩubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjȩubj)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȩubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(h u64 offseth](h)}(hhh]j)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.i915_gem_gtt_reserveasbuh1hhjubj )}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hoffseth]hoffset}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(hunsigned long colorh](jn)}(hunsignedh]hunsigned}(hj\hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjXubj )}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXubjn)}(hlongh]hlong}(hjxhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjXubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXubj)}(hcolorh]hcolor}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(hunsigned int flagsh](jn)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubjn)}(hinth]hint}(hjɪhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hjתhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hflagsh]hflags}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj9hhhjKhKGubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj5hhhjKhKGubah}(h]j0ah ](jjeh"]h$]h&]jj)jhuh1jhjKhKGhj2hhubj)}(hhh]h)}(h(reserve a node in an address_space (GTT)h]h(reserve a node in an address_space (GTT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKGhj hhubah}(h]h ]h"]h$]h&]uh1jhj2hhhjKhKGubeh}(h]h ](jfunctioneh"]h$]h&]jjjj'jj'jjjuh1jhhhj˦hNhNubj)}(hX**Parameters** ``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) ``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned ``u64 offset`` where to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address space ``unsigned long color`` color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE ``unsigned int flags`` control search and eviction behaviour **Description** i915_gem_gtt_reserve() tries to insert the **node** at the exact **offset** inside the address space (using **size** and **color**). If the **node** does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure. **Return** 0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h](h)}(h**Parameters**h]j)}(hj1h]h Parameters}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKKhj+ubj)}(hhh](j)}(h_``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` h](j$)}(h!``struct i915_address_space *vm``h]j*)}(hjPh]hstruct i915_address_space *vm}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjNubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKHhjJubj@)}(hhh]h)}(h`h](hthe }(hjihhhNhNubh)}(h8:c:type:`struct i915_address_space `h]j*)}(hjsh]hstruct i915_address_space}(hjuhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjqubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_address_spaceuh1hhjehKHhjiubeh}(h]h ]h"]h$]h&]uh1hhjehKHhjfubah}(h]h ]h"]h$]h&]uh1j?hjJubeh}(h]h ]h"]h$]h&]uh1jhjehKHhjGubj)}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j$)}(h``struct i915_gem_ww_ctx *ww``h]j*)}(hjh]hstruct i915_gem_ww_ctx *ww}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKIhjubj@)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKIhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKIhjGubj)}(hf``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) h](j$)}(h``struct drm_mm_node *node``h]j*)}(hjh]hstruct drm_mm_node *node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj߫ubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKJhj۫ubj@)}(hhh]h)}(hHthe :c:type:`struct drm_mm_node ` (typically i915_vma.node)h](hthe }(hjhhhNhNubh)}(h*:c:type:`struct drm_mm_node `h]j*)}(hjh]hstruct drm_mm_node}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_mm_nodeuh1hhjhKJhjubh (typically i915_vma.node)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKJhjubah}(h]h ]h"]h$]h&]uh1j?hj۫ubeh}(h]h ]h"]h$]h&]uh1jhjhKJhjGubj)}(h\``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned h](j$)}(h ``u64 size``h]j*)}(hj=h]hu64 size}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj;ubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKLhj7ubj@)}(hhh]h)}(hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE alignedh]hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKKhjSubah}(h]h ]h"]h$]h&]uh1j?hj7ubeh}(h]h ]h"]h$]h&]uh1jhjRhKLhjGubj)}(h``u64 offset`` where to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address space h](j$)}(h``u64 offset``h]j*)}(hjwh]h u64 offset}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjuubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKOhjqubj@)}(hhh]h)}(hwhere to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address spaceh](hWwhere to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (}(hjhhhNhNubj)}(h **offset**h]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh + }(hjhhhNhNubj)}(h**size**h]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh#) must fit within the address space}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKMhjubah}(h]h ]h"]h$]h&]uh1j?hjqubeh}(h]h ]h"]h$]h&]uh1jhjhKOhjGubj)}(hv``unsigned long color`` color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE h](j$)}(h``unsigned long color``h]j*)}(hjլh]hunsigned long color}(hj׬hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjӬubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKQhjϬubj@)}(hhh]h)}(h]color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLEh]h]color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKPhjubah}(h]h ]h"]h$]h&]uh1j?hjϬubeh}(h]h ]h"]h$]h&]uh1jhjhKQhjGubj)}(h=``unsigned int flags`` control search and eviction behaviour h](j$)}(h``unsigned int flags``h]j*)}(hjh]hunsigned int flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKRhj ubj@)}(hhh]h)}(h%control search and eviction behaviourh]h%control search and eviction behaviour}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hKRhj%ubah}(h]h ]h"]h$]h&]uh1j?hj ubeh}(h]h ]h"]h$]h&]uh1jhj$hKRhjGubeh}(h]h ]h"]h$]h&]uh1jhj+ubh)}(h**Description**h]j)}(hjJh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKThj+ubh)}(hXEi915_gem_gtt_reserve() tries to insert the **node** at the exact **offset** inside the address space (using **size** and **color**). If the **node** does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure.h](h+i915_gem_gtt_reserve() tries to insert the }(hj`hhhNhNubj)}(h**node**h]hnode}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubh at the exact }(hj`hhhNhNubj)}(h **offset**h]hoffset}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubh! inside the address space (using }(hj`hhhNhNubj)}(h**size**h]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubh and }(hj`hhhNhNubj)}(h **color**h]hcolor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubh ). If the }(hj`hhhNhNubj)}(h**node**h]hnode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubhX does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKShj+ubh)}(h **Return**h]j)}(hj˭h]hReturn}(hjͭhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjɭubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chK\hj+ubh)}(hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h]hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chK]hj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj˦hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j i915_gem_gtt_insert (C function)c.i915_gem_gtt_inserthNtauh1jhj˦hhhNhNubj)}(hhh](j)}(hint i915_gem_gtt_insert (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h]j)}(hint i915_gem_gtt_insert(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h](jn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj hhh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj hhhjhKubj)}(hi915_gem_gtt_inserth]j)}(hi915_gem_gtt_inserth]hi915_gem_gtt_insert}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj hhhjhKubj8)}(h(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h](j>)}(hstruct i915_address_space *vmh](jD)}(hjGh]hstruct}(hjMhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjIubj )}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjIubh)}(hhh]j)}(hi915_address_spaceh]hi915_address_space}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmmodnameN classnameNjj)}j]j)}jj3sbc.i915_gem_gtt_insertasbuh1hhjIubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjIubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(hvmh]hvm}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(hstruct i915_gem_ww_ctx *wwh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hj̮hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjݮhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjڮubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj߮modnameN classnameNjj)}j]jc.i915_gem_gtt_insertasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hwwh]hww}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(hstruct drm_mm_node *nodeh](jD)}(hjGh]hstruct}(hj/hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj+ubj )}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj+ubh)}(hhh]j)}(h drm_mm_nodeh]h drm_mm_node}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjOmodnameN classnameNjj)}j]jc.i915_gem_gtt_insertasbuh1hhj+ubj )}(h h]h }(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj+ubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubj)}(hnodeh]hnode}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(hu64 sizeh](h)}(hhh]j)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.i915_gem_gtt_insertasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hsizeh]hsize}(hjίhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(h u64 alignmenth](h)}(hhh]j)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.i915_gem_gtt_insertasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(h alignmenth]h alignment}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(hunsigned long colorh](jn)}(hunsignedh]hunsigned}(hj/hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj+ubj )}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj+ubjn)}(hlongh]hlong}(hjKhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj+ubj )}(h h]h }(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj+ubj)}(hcolorh]hcolor}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(h u64 starth](h)}(hhh]j)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.i915_gem_gtt_insertasbuh1hhj|ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj|ubj)}(hstarth]hstart}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(hu64 endh](h)}(hhh]j)}(hu64h]hu64}(hj˰hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȰubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjͰmodnameN classnameNjj)}j]jc.i915_gem_gtt_insertasbuh1hhjİubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjİubj)}(hendh]hend}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjİubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubj>)}(hunsigned int flagsh](jn)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubjn)}(hinth]hint}(hj,hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj ubj )}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj)}(hflagsh]hflags}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjEubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj hhhjhKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h)insert a node into an address_space (GTT)h]h)insert a node into an address_space (GTT)}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjohhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhj˦hNhNubj)}(hX**Parameters** ``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) ``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned ``u64 alignment`` required alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENT ``unsigned long color`` color to apply to node ``u64 start`` start of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned ``u64 end`` end of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX ``unsigned int flags`` control search and eviction behaviour **Description** i915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to **alignment** and its **size** must then fit entirely within the [**start**, **end**] bounds. The nodes on either side of the hole must match **color**, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node's VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm. **Return** 0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj)}(hhh](j)}(h_``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` h](j$)}(h!``struct i915_address_space *vm``h]j*)}(hjh]hstruct i915_address_space *vm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj@)}(hhh]h)}(h`h](hthe }(hj̱hhhNhNubh)}(h8:c:type:`struct i915_address_space `h]j*)}(hjֱh]hstruct i915_address_space}(hjرhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjԱubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_address_spaceuh1hhjȱhKhj̱ubeh}(h]h ]h"]h$]h&]uh1hhjȱhKhjɱubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjȱhKhjubj)}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j$)}(h``struct i915_gem_ww_ctx *ww``h]j*)}(hj h]hstruct i915_gem_ww_ctx *ww}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj@)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj!ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubj)}(hf``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) h](j$)}(h``struct drm_mm_node *node``h]j*)}(hjDh]hstruct drm_mm_node *node}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjBubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj>ubj@)}(hhh]h)}(hHthe :c:type:`struct drm_mm_node ` (typically i915_vma.node)h](hthe }(hj]hhhNhNubh)}(h*:c:type:`struct drm_mm_node `h]j*)}(hjgh]hstruct drm_mm_node}(hjihhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjeubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_mm_nodeuh1hhjYhKhj]ubh (typically i915_vma.node)}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjYhKhjZubah}(h]h ]h"]h$]h&]uh1j?hj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhKhjubj)}(h\``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned h](j$)}(h ``u64 size``h]j*)}(hjh]hu64 size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj@)}(hhh]h)}(hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE alignedh]hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``u64 alignment`` required alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENT h](j$)}(h``u64 alignment``h]j*)}(hjڲh]h u64 alignment}(hjܲhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjزubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjԲubj@)}(hhh]h)}(hrequired alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENTh]hrequired alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubah}(h]h ]h"]h$]h&]uh1j?hjԲubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h/``unsigned long color`` color to apply to node h](j$)}(h``unsigned long color``h]j*)}(hjh]hunsigned long color}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj@)}(hhh]h)}(hcolor to apply to nodeh]hcolor to apply to node}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKhj*ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj)hKhjubj)}(hi``u64 start`` start of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned h](j$)}(h ``u64 start``h]j*)}(hjMh]h u64 start}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjKubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjGubj@)}(hhh]h)}(hZstart of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE alignedh]hZstart of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjcubah}(h]h ]h"]h$]h&]uh1j?hjGubeh}(h]h ]h"]h$]h&]uh1jhjbhKhjubj)}(hz``u64 end`` end of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX h](j$)}(h ``u64 end``h]j*)}(hjh]hu64 end}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj@)}(hhh]h)}(hmend of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAXh]hmend of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h=``unsigned int flags`` control search and eviction behaviour h](j$)}(h``unsigned int flags``h]j*)}(hjh]hunsigned int flags}(hjóhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj@)}(hhh]h)}(h%control search and eviction behaviourh]h%control search and eviction behaviour}(hjڳhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjֳhKhj׳ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjֳhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubh)}(hXi915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to **alignment** and its **size** must then fit entirely within the [**start**, **end**] bounds. The nodes on either side of the hole must match **color**, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node's VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm.h](h}i915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to }(hjhhhNhNubj)}(h **alignment**h]h alignment}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and its }(hjhhhNhNubj)}(h**size**h]hsize}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh$ must then fit entirely within the [}(hjhhhNhNubj)}(h **start**h]hstart}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, }(hjhhhNhNubj)}(h**end**h]hend}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:] bounds. The nodes on either side of the hole must match }(hjhhhNhNubj)}(h **color**h]hcolor}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node’s VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubh)}(h **Return**h]j)}(hj}h]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubh)}(hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h]hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj˦hhhNhNubeh}(h]global-gtt-viewsah ]h"]global gtt viewsah$]h&]uh1hhj.bhhhhhMubh)}(hhh](h)}(hGTT Fences and Swizzlingh]hGTT Fences and Swizzling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_vma_revoke_fence (C function)c.i915_vma_revoke_fencehNtauh1jhjhhhNhNubj)}(hhh](j)}(h1void i915_vma_revoke_fence (struct i915_vma *vma)h]j)}(h0void i915_vma_revoke_fence(struct i915_vma *vma)h](jn)}(hvoidh]hvoid}(hj۴hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj״hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj״hhhjhM ubj)}(hi915_vma_revoke_fenceh]j)}(hi915_vma_revoke_fenceh]hi915_vma_revoke_fence}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj״hhhjhM ubj8)}(h(struct i915_vma *vma)h]j>)}(hstruct i915_vma *vmah](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hi915_vmah]hi915_vma}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj8modnameN classnameNjj)}j]j)}jjsbc.i915_vma_revoke_fenceasbuh1hhjubj )}(h h]h }(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hvmah]hvma}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hj״hhhjhM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjӴhhhjhM ubah}(h]jδah ](jjeh"]h$]h&]jj)jhuh1jhjhM hjдhhubj)}(hhh]h)}(hforce-remove fence for a VMAh]hforce-remove fence for a VMA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjдhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct i915_vma *vma`` vma to map linearly (not through a fence reg) **Description** This function force-removes any fence from the given object, which is useful if the kernel wants to do untiled GTT access.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM$hjubj)}(hhh]j)}(hG``struct i915_vma *vma`` vma to map linearly (not through a fence reg) h](j$)}(h``struct i915_vma *vma``h]j*)}(hjܵh]hstruct i915_vma *vma}(hj޵hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjڵubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM!hjֵubj@)}(hhh]h)}(h-vma to map linearly (not through a fence reg)h]h-vma to map linearly (not through a fence reg)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM!hjubah}(h]h ]h"]h$]h&]uh1j?hjֵubeh}(h]h ]h"]h$]h&]uh1jhjhM!hjӵubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM#hjubh)}(hzThis function force-removes any fence from the given object, which is useful if the kernel wants to do untiled GTT access.h]hzThis function force-removes any fence from the given object, which is useful if the kernel wants to do untiled GTT access.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM"hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_vma_pin_fence (C function)c.i915_vma_pin_fencehNtauh1jhjhhhNhNubj)}(hhh](j)}(h-int i915_vma_pin_fence (struct i915_vma *vma)h]j)}(h,int i915_vma_pin_fence(struct i915_vma *vma)h](jn)}(hinth]hint}(hj\hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjXhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubj )}(h h]h }(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXhhhjjhMubj)}(hi915_vma_pin_fenceh]j)}(hi915_vma_pin_fenceh]hi915_vma_pin_fence}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjXhhhjjhMubj8)}(h(struct i915_vma *vma)h]j>)}(hstruct i915_vma *vmah](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hi915_vmah]hi915_vma}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.i915_vma_pin_fenceasbuh1hhjubj )}(h h]h }(hj׶hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hvmah]hvma}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hjXhhhjjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjThhhjjhMubah}(h]jOah ](jjeh"]h$]h&]jj)jhuh1jhjjhMhjQhhubj)}(hhh]h)}(hset up fencing for a vmah]hset up fencing for a vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjQhhhjjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj4jj4jjjuh1jhhhjhNhNubj)}(hX)**Parameters** ``struct i915_vma *vma`` vma to map through a fence reg **Description** When mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for **obj**, stealing one if it can't find any. It then sets up the reg based on the object's properties: address, pitch and tiling format. For an untiled surface, this removes any existing fence. **Return** 0 on success, negative error code on failure.h](h)}(h**Parameters**h]j)}(hj>h]h Parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj8ubj)}(hhh]j)}(h8``struct i915_vma *vma`` vma to map through a fence reg h](j$)}(h``struct i915_vma *vma``h]j*)}(hj]h]hstruct i915_vma *vma}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj[ubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjWubj@)}(hhh]h)}(hvma to map through a fence regh]hvma to map through a fence reg}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjsubah}(h]h ]h"]h$]h&]uh1j?hjWubeh}(h]h ]h"]h$]h&]uh1jhjrhMhjTubah}(h]h ]h"]h$]h&]uh1jhj8ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj8ubh)}(hWhen mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for **obj**, stealing one if it can't find any.h](hWhen mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for }(hjhhhNhNubj)}(h**obj**h]hobj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh&, stealing one if it can’t find any.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj8ubh)}(h[It then sets up the reg based on the object's properties: address, pitch and tiling format.h]h]It then sets up the reg based on the object’s properties: address, pitch and tiling format.}(hjϷhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj8ubh)}(h8For an untiled surface, this removes any existing fence.h]h8For an untiled surface, this removes any existing fence.}(hj޷hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj8ubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj8ubh)}(h-0 on success, negative error code on failure.h]h-0 on success, negative error code on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_reserve_fence (C function)c.i915_reserve_fencehNtauh1jhjhhhNhNubj)}(hhh](j)}(hCstruct i915_fence_reg * i915_reserve_fence (struct i915_ggtt *ggtt)h]j)}(hAstruct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt)h](jD)}(hjGh]hstruct}(hj4hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj0hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubj )}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj0hhhjAhMubh)}(hhh]j)}(hi915_fence_regh]hi915_fence_reg}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]j)}ji915_reserve_fencesbc.i915_reserve_fenceasbuh1hhj0hhhjAhMubj )}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj0hhhjAhMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0hhhjAhMubj)}(hi915_reserve_fenceh]j)}(hjqh]hi915_reserve_fence}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj0hhhjAhMubj8)}(h(struct i915_ggtt *ggtt)h]j>)}(hstruct i915_ggtt *ggtth](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h i915_ggtth]h i915_ggtt}(hj̸hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjɸubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjθmodnameN classnameNjj)}j]joc.i915_reserve_fenceasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hggtth]hggtt}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hj0hhhjAhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj,hhhjAhMubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1jhjAhMhj)hhubj)}(hhh]h)}(hReserve a fence for vGPUh]hReserve a fence for vGPU}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj,hhubah}(h]h ]h"]h$]h&]uh1jhj)hhhjAhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjGjjGjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct i915_ggtt *ggtt`` Global GTT **Description** This function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.h](h)}(h**Parameters**h]j)}(hjQh]h Parameters}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjKubj)}(hhh]j)}(h&``struct i915_ggtt *ggtt`` Global GTT h](j$)}(h``struct i915_ggtt *ggtt``h]j*)}(hjph]hstruct i915_ggtt *ggtt}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjnubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjjubj@)}(hhh]h)}(h Global GTTh]h Global GTT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjgubah}(h]h ]h"]h$]h&]uh1jhjKubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjKubh)}(hThis function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.h]hThis function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjKubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!i915_unreserve_fence (C function)c.i915_unreserve_fencehNtauh1jhjhhhNhNubj)}(hhh](j)}(h8void i915_unreserve_fence (struct i915_fence_reg *fence)h]j)}(h7void i915_unreserve_fence(struct i915_fence_reg *fence)h](jn)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hi915_unreserve_fenceh]j)}(hi915_unreserve_fenceh]hi915_unreserve_fence}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(h(struct i915_fence_reg *fence)h]j>)}(hstruct i915_fence_reg *fenceh](jD)}(hjGh]hstruct}(hj-hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj)ubj )}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj)ubh)}(hhh]j)}(hi915_fence_regh]hi915_fence_reg}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjMmodnameN classnameNjj)}j]j)}jjsbc.i915_unreserve_fenceasbuh1hhj)ubj )}(h h]h }(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj)ubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj)}(hfenceh]hfence}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj%ubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hReclaim a reserved fenceh]hReclaim a reserved fence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjȺjjȺjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct i915_fence_reg *fence`` the fence reg **Description** This function add a reserved fence register from vGPU to the fence_list.h](h)}(h**Parameters**h]j)}(hjҺh]h Parameters}(hjԺhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjкubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj̺ubj)}(hhh]j)}(h/``struct i915_fence_reg *fence`` the fence reg h](j$)}(h ``struct i915_fence_reg *fence``h]j*)}(hjh]hstruct i915_fence_reg *fence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj@)}(hhh]h)}(h the fence regh]h the fence reg}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj̺ubh)}(h**Description**h]j)}(hj,h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj̺ubh)}(hHThis function add a reserved fence register from vGPU to the fence_list.h]hHThis function add a reserved fence register from vGPU to the fence_list.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj̺ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&intel_ggtt_restore_fences (C function)c.intel_ggtt_restore_fenceshNtauh1jhjhhhNhNubj)}(hhh](j)}(h7void intel_ggtt_restore_fences (struct i915_ggtt *ggtt)h]j)}(h6void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)h](jn)}(hvoidh]hvoid}(hjqhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjmhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjmhhhjhMubj)}(hintel_ggtt_restore_fencesh]j)}(hintel_ggtt_restore_fencesh]hintel_ggtt_restore_fences}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjmhhhjhMubj8)}(h(struct i915_ggtt *ggtt)h]j>)}(hstruct i915_ggtt *ggtth](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h i915_ggtth]h i915_ggtt}(hj̻hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjɻubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjλmodnameN classnameNjj)}j]j)}jjsbc.intel_ggtt_restore_fencesasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hggtth]hggtt}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hjmhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjihhhjhMubah}(h]jdah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjfhhubj)}(hhh]h)}(hrestore fence stateh]hrestore fence state}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj.hhubah}(h]h ]h"]h$]h&]uh1jhjfhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjIjjIjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct i915_ggtt *ggtt`` Global GTT **Description** Restore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.h](h)}(h**Parameters**h]j)}(hjSh]h Parameters}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjMubj)}(hhh]j)}(h&``struct i915_ggtt *ggtt`` Global GTT h](j$)}(h``struct i915_ggtt *ggtt``h]j*)}(hjrh]hstruct i915_ggtt *ggtt}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjpubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjlubj@)}(hhh]h)}(h Global GTTh]h Global GTT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjlubeh}(h]h ]h"]h$]h&]uh1jhjhMhjiubah}(h]h ]h"]h$]h&]uh1jhjMubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjMubh)}(hRestore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.h]hRestore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.}(hjühhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjMubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!detect_bit_6_swizzle (C function)c.detect_bit_6_swizzlehNtauh1jhjhhhNhNubj)}(hhh](j)}(h2void detect_bit_6_swizzle (struct i915_ggtt *ggtt)h]j)}(h1void detect_bit_6_swizzle(struct i915_ggtt *ggtt)h](jn)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM9ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhM9ubj)}(hdetect_bit_6_swizzleh]j)}(hdetect_bit_6_swizzleh]hdetect_bit_6_swizzle}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhM9ubj8)}(h(struct i915_ggtt *ggtt)h]j>)}(hstruct i915_ggtt *ggtth](jD)}(hjGh]hstruct}(hj/hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj+ubj )}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj+ubh)}(hhh]j)}(h i915_ggtth]h i915_ggtt}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjOmodnameN classnameNjj)}j]j)}jjsbc.detect_bit_6_swizzleasbuh1hhj+ubj )}(h h]h }(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj+ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubj)}(hggtth]hggtt}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj'ubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhM9ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhM9ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM9hjhhubj)}(hhh]h)}(hdetect bit 6 swizzling patternh]hdetect bit 6 swizzling pattern}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM9hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM9ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjʽjjʽjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct i915_ggtt *ggtt`` Global GGTT **Description** Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.h](h)}(h**Parameters**h]j)}(hjԽh]h Parameters}(hjֽhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjҽubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM=hjνubj)}(hhh]j)}(h'``struct i915_ggtt *ggtt`` Global GGTT h](j$)}(h``struct i915_ggtt *ggtt``h]j*)}(hjh]hstruct i915_ggtt *ggtt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM:hjubj@)}(hhh]h)}(h Global GGTTh]h Global GGTT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM:hj ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM:hjubah}(h]h ]h"]h$]h&]uh1jhjνubh)}(h**Description**h]j)}(hj.h]h Description}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM<hjνubh)}(h`Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.h]h`Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM;hjνubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.i915_gem_object_do_bit_17_swizzle (C function))#c.i915_gem_object_do_bit_17_swizzlehNtauh1jhjhhhNhNubj)}(hhh](j)}(h`void i915_gem_object_do_bit_17_swizzle (struct drm_i915_gem_object *obj, struct sg_table *pages)h]j)}(h_void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, struct sg_table *pages)h](jn)}(hvoidh]hvoid}(hjshhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjohhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjohhhjhMubj)}(h!i915_gem_object_do_bit_17_swizzleh]j)}(h!i915_gem_object_do_bit_17_swizzleh]h!i915_gem_object_do_bit_17_swizzle}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjohhhjhMubj8)}(h9(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j>)}(hstruct drm_i915_gem_object *objh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjξhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj˾ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjоmodnameN classnameNjj)}j]j)}jjsb#c.i915_gem_object_do_bit_17_swizzleasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hobjh]hobj}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hstruct sg_table *pagesh](jD)}(hjGh]hstruct}(hj"hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hsg_tableh]hsg_table}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjBmodnameN classnameNjj)}j]j#c.i915_gem_object_do_bit_17_swizzleasbuh1hhjubj )}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hpagesh]hpages}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjohhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjkhhhjhMubah}(h]jfah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhhubj)}(hhh]h)}(hfixup bit 17 swizzlingh]hfixup bit 17 swizzling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct drm_i915_gem_object *obj`` i915 GEM buffer object ``struct sg_table *pages`` the scattergather list of physical pages **Description** This function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle(). This is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).h](h)}(h**Parameters**h]j)}(hjſh]h Parameters}(hjǿhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjÿubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh](j)}(h;``struct drm_i915_gem_object *obj`` i915 GEM buffer object h](j$)}(h#``struct drm_i915_gem_object *obj``h]j*)}(hjh]hstruct drm_i915_gem_object *obj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj޿ubj@)}(hhh]h)}(hi915 GEM buffer objecth]hi915 GEM buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hj޿ubeh}(h]h ]h"]h$]h&]uh1jhjhMhjۿubj)}(hD``struct sg_table *pages`` the scattergather list of physical pages h](j$)}(h``struct sg_table *pages``h]j*)}(hjh]hstruct sg_table *pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj@)}(hhh]h)}(h(the scattergather list of physical pagesh]h(the scattergather list of physical pages}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMhj3ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj2hMhjۿubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjXh]h Description}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hThis function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle().h]hThis function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle().}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hThis is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).h]hThis is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j0i915_gem_object_save_bit_17_swizzle (C function)%c.i915_gem_object_save_bit_17_swizzlehNtauh1jhjhhhNhNubj)}(hhh](j)}(hbvoid i915_gem_object_save_bit_17_swizzle (struct drm_i915_gem_object *obj, struct sg_table *pages)h]j)}(havoid i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, struct sg_table *pages)h](jn)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM%ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhM%ubj)}(h#i915_gem_object_save_bit_17_swizzleh]j)}(h#i915_gem_object_save_bit_17_swizzleh]h#i915_gem_object_save_bit_17_swizzle}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhM%ubj8)}(h9(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j>)}(hstruct drm_i915_gem_object *objh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jjsb%c.i915_gem_object_save_bit_17_swizzleasbuh1hhjubj )}(h h]h }(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hobjh]hobj}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hstruct sg_table *pagesh](jD)}(hjGh]hstruct}(hj[hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjWubj )}(h h]h }(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjWubh)}(hhh]j)}(hsg_tableh]hsg_table}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj{modnameN classnameNjj)}j]j#%c.i915_gem_object_save_bit_17_swizzleasbuh1hhjWubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjWubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj)}(hpagesh]hpages}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhM%ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhM%ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM%hjhhubj)}(hhh]h)}(hsave bit 17 swizzlingh]hsave bit 17 swizzling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM%hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM%ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hXs**Parameters** ``struct drm_i915_gem_object *obj`` i915 GEM buffer object ``struct sg_table *pages`` the scattergather list of physical pages **Description** This function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM)hjubj)}(hhh](j)}(h;``struct drm_i915_gem_object *obj`` i915 GEM buffer object h](j$)}(h#``struct drm_i915_gem_object *obj``h]j*)}(hjh]hstruct drm_i915_gem_object *obj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hjubj@)}(hhh]h)}(hi915 GEM buffer objecth]hi915 GEM buffer object}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hM&hj3ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj2hM&hjubj)}(hD``struct sg_table *pages`` the scattergather list of physical pages h](j$)}(h``struct sg_table *pages``h]j*)}(hjVh]hstruct sg_table *pages}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjTubah}(h]h ]h"]h$]h&]uh1j#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM'hjPubj@)}(hhh]h)}(h(the scattergather list of physical pagesh]h(the scattergather list of physical pages}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhM'hjlubah}(h]h ]h"]h$]h&]uh1j?hjPubeh}(h]h ]h"]h$]h&]uh1jhjkhM'hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM)hjubh)}(hThis function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.h]hThis function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:270: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM(hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubh)}(hhh](h)}(hGlobal GTT Fence Handlingh]hGlobal GTT Fence Handling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hImportant to avoid confusions: "fences" in the i915 driver are not execution fences used to track command completion but hardware detiler objects which wrap a given range of the global GTT. Each platform has only a fairly limited set of these objects.h]hImportant to avoid confusions: “fences” in the i915 driver are not execution fences used to track command completion but hardware detiler objects which wrap a given range of the global GTT. Each platform has only a fairly limited set of these objects.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:276: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chKhjhhubh)}(hXFences are used to detile GTT memory mappings. They're also connected to the hardware frontbuffer render tracking and hence interact with frontbuffer compression. Furthermore on older platforms fences are required for tiled objects used by the display engine. They can also be used by the render engine - they're required for blitter commands and are optional for render commands. But on gen4+ both display (with the exception of fbc) and rendering have their own tiling state bits and don't need fences.h]hXFences are used to detile GTT memory mappings. They’re also connected to the hardware frontbuffer render tracking and hence interact with frontbuffer compression. Furthermore on older platforms fences are required for tiled objects used by the display engine. They can also be used by the render engine - they’re required for blitter commands and are optional for render commands. But on gen4+ both display (with the exception of fbc) and rendering have their own tiling state bits and don’t need fences.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:276: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chKhjhhubh)}(hAlso note that fences only support X and Y tiling and hence can't be used for the fancier new tiling formats like W, Ys and Yf.h]hAlso note that fences only support X and Y tiling and hence can’t be used for the fancier new tiling formats like W, Ys and Yf.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:276: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chK"hjhhubh)}(hXFinally note that because fences are such a restricted resource they're dynamically associated with objects. Furthermore fence state is committed to the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must explicitly call i915_gem_object_get_fence() to synchronize fencing status for cpu access. Also note that some code wants an unfenced view, for those cases the fence can be removed forcefully with i915_gem_object_put_fence().h]hXFinally note that because fences are such a restricted resource they’re dynamically associated with objects. Furthermore fence state is committed to the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must explicitly call i915_gem_object_get_fence() to synchronize fencing status for cpu access. Also note that some code wants an unfenced view, for those cases the fence can be removed forcefully with i915_gem_object_put_fence().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:276: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chK%hjhhubh)}(hInternally these functions will synchronize with userspace access by removing CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.h]hInternally these functions will synchronize with userspace access by removing CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:276: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chK,hjhhubeh}(h]global-gtt-fence-handlingah ]h"]global gtt fence handlingah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h%Hardware Tiling and Swizzling Detailsh]h%Hardware Tiling and Swizzling Details}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhhhMubh)}(hThe idea behind tiling is to increase cache hit rates by rearranging pixel data so that a group of pixel accesses are in the same cacheline. Performance improvement from doing this on the back/depth buffer are on the order of 30%.h]hThe idea behind tiling is to increase cache hit rates by rearranging pixel data so that a group of pixel accesses are in the same cacheline. Performance improvement from doing this on the back/depth buffer are on the order of 30%.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:282: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM hj!hhubh)}(hXMIntel architectures make this somewhat more complicated, though, by adjustments made to addressing of data when the memory is in interleaved mode (matched pairs of DIMMS) to improve memory bandwidth. For interleaved memory, the CPU sends every sequential 64 bytes to an alternate memory channel so it can get the bandwidth from both.h]hXMIntel architectures make this somewhat more complicated, though, by adjustments made to addressing of data when the memory is in interleaved mode (matched pairs of DIMMS) to improve memory bandwidth. For interleaved memory, the CPU sends every sequential 64 bytes to an alternate memory channel so it can get the bandwidth from both.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:282: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj!hhubh)}(hXThe GPU also rearranges its accesses for increased bandwidth to interleaved memory, and it matches what the CPU does for non-tiled. However, when tiled it does it a little differently, since one walks addresses not just in the X direction but also Y. So, along with alternating channels when bit 6 of the address flips, it also alternates when other bits flip -- Bits 9 (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) are common to both the 915 and 965-class hardware.h]hXThe GPU also rearranges its accesses for increased bandwidth to interleaved memory, and it matches what the CPU does for non-tiled. However, when tiled it does it a little differently, since one walks addresses not just in the X direction but also Y. So, along with alternating channels when bit 6 of the address flips, it also alternates when other bits flip -- Bits 9 (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) are common to both the 915 and 965-class hardware.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:282: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj!hhubh)}(hX*The CPU also sometimes XORs in higher bits as well, to improve bandwidth doing strided access like we do so frequently in graphics. This is called "Channel XOR Randomization" in the MCH documentation. The result is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address decode.h]hX.The CPU also sometimes XORs in higher bits as well, to improve bandwidth doing strided access like we do so frequently in graphics. This is called “Channel XOR Randomization” in the MCH documentation. The result is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address decode.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:282: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj!hhubh)}(hAll of this bit 6 XORing has an effect on our memory management, as we need to make sure that the 3d driver can correctly address object contents.h]hAll of this bit 6 XORing has an effect on our memory management, as we need to make sure that the 3d driver can correctly address object contents.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:282: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM"hj!hhubh)}(hUIf we don't have interleaved memory, all tiling is safe and no swizzling is required.h]hWIf we don’t have interleaved memory, all tiling is safe and no swizzling is required.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:282: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hj!hhubh)}(hWhen bit 17 is XORed in, we simply refuse to tile at all. Bit 17 is not just a page offset, so as we page an object out and back in, individual pages in it will have different bit 17 addresses, resulting in each 64 bytes being swapped with its neighbor!h]hWhen bit 17 is XORed in, we simply refuse to tile at all. Bit 17 is not just a page offset, so as we page an object out and back in, individual pages in it will have different bit 17 addresses, resulting in each 64 bytes being swapped with its neighbor!}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:282: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM)hj!hhubh)}(hXOtherwise, if interleaved, we have to tell the 3d driver what the address swizzling it needs to do is, since it's writing with the CPU to the pages (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order to match what the GPU expects.h]hXOtherwise, if interleaved, we have to tell the 3d driver what the address swizzling it needs to do is, since it’s writing with the CPU to the pages (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order to match what the GPU expects.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:282: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM.hj!hhubeh}(h]%hardware-tiling-and-swizzling-detailsah ]h"]%hardware tiling and swizzling detailsah$]h&]uh1hhjhhhhhMubeh}(h]gtt-fences-and-swizzlingah ]h"]gtt fences and swizzlingah$]h&]uh1hhj.bhhhhhM ubh)}(hhh](h)}(hObject Tiling IOCTLsh]hObject Tiling IOCTLs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j i915_gem_fence_size (C function)c.i915_gem_fence_sizehNtauh1jhjhhhNhNubj)}(hhh](j)}(hku32 i915_gem_fence_size (struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h]j)}(hju32 i915_gem_fence_size(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](h)}(hhh]j)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}ji915_gem_fence_sizesbc.i915_gem_fence_sizeasbuh1hhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK-ubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhK-ubj)}(hi915_gem_fence_sizeh]j)}(hjh]hi915_gem_fence_size}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhK-ubj8)}(hS(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hj6hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj2ubj )}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjVmodnameN classnameNjj)}j]jc.i915_gem_fence_sizeasbuh1hhj2ubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(hi915h]hi915}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj.ubj>)}(hu32 sizeh](h)}(hhh]j)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.i915_gem_fence_sizeasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj.ubj>)}(hunsigned int tilingh](jn)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubjn)}(hinth]hint}(hj hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(htilingh]htiling}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj.ubj>)}(hunsigned int strideh](jn)}(hunsignedh]hunsigned}(hj?hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj;ubj )}(h h]h }(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj;ubjn)}(hinth]hint}(hj[hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj;ubj )}(h h]h }(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj;ubj)}(hstrideh]hstride}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj.ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhK-ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhK-ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhK-hjhhubj)}(hhh]h)}(h$required global GTT size for a fenceh]h$required global GTT size for a fence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK-hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhK-ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX=**Parameters** ``struct drm_i915_private *i915`` i915 device ``u32 size`` object size ``unsigned int tiling`` tiling mode ``unsigned int stride`` tiling stride **Description** Return the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK1hjubj)}(hhh](j)}(h.``struct drm_i915_private *i915`` i915 device h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hjh]hstruct drm_i915_private *i915}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK.hjubj@)}(hhh]h)}(h i915 deviceh]h i915 device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK.hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK.hjubj)}(h``u32 size`` object size h](j$)}(h ``u32 size``h]j*)}(hjh]hu32 size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK/hjubj@)}(hhh]h)}(h object sizeh]h object size}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hK/hj1ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj0hK/hjubj)}(h$``unsigned int tiling`` tiling mode h](j$)}(h``unsigned int tiling``h]j*)}(hjTh]hunsigned int tiling}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjRubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK0hjNubj@)}(hhh]h)}(h tiling modeh]h tiling mode}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihK0hjjubah}(h]h ]h"]h$]h&]uh1j?hjNubeh}(h]h ]h"]h$]h&]uh1jhjihK0hjubj)}(h&``unsigned int stride`` tiling stride h](j$)}(h``unsigned int stride``h]j*)}(hjh]hunsigned int stride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK1hjubj@)}(hhh]h)}(h tiling strideh]h tiling stride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK1hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK1hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK3hjubh)}(hReturn the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.h]hReturn the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK2hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%i915_gem_fence_alignment (C function)c.i915_gem_fence_alignmenthNtauh1jhjhhhNhNubj)}(hhh](j)}(hpu32 i915_gem_fence_alignment (struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h]j)}(hou32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](h)}(hhh]j)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}ji915_gem_fence_alignmentsbc.i915_gem_fence_alignmentasbuh1hhj hhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKUubj )}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj hhhj1hKUubj)}(hi915_gem_fence_alignmenth]j)}(hj.h]hi915_gem_fence_alignment}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj hhhj1hKUubj8)}(hS(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hj_hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj[ubj )}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj[ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j,c.i915_gem_fence_alignmentasbuh1hhj[ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj[ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubj)}(hi915h]hi915}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubj>)}(hu32 sizeh](h)}(hhh]j)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j,c.i915_gem_fence_alignmentasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubj>)}(hunsigned int tilingh](jn)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubjn)}(hinth]hint}(hj3hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(htilingh]htiling}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubj>)}(hunsigned int strideh](jn)}(hunsignedh]hunsigned}(hjhhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjdubj )}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjdubjn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjdubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjdubj)}(hstrideh]hstride}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj hhhj1hKUubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhj1hKUubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj1hKUhjhhubj)}(hhh]h)}(h)required global GTT alignment for a fenceh]h)required global GTT alignment for a fence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKUhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj1hKUubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hXD**Parameters** ``struct drm_i915_private *i915`` i915 device ``u32 size`` object size ``unsigned int tiling`` tiling mode ``unsigned int stride`` tiling stride **Description** Return the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKYhjubj)}(hhh](j)}(h.``struct drm_i915_private *i915`` i915 device h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hj h]hstruct drm_i915_private *i915}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKVhjubj@)}(hhh]h)}(h i915 deviceh]h i915 device}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKVhj!ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hKVhjubj)}(h``u32 size`` object size h](j$)}(h ``u32 size``h]j*)}(hjDh]hu32 size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjBubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKWhj>ubj@)}(hhh]h)}(h object sizeh]h object size}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhKWhjZubah}(h]h ]h"]h$]h&]uh1j?hj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhKWhjubj)}(h$``unsigned int tiling`` tiling mode h](j$)}(h``unsigned int tiling``h]j*)}(hj}h]hunsigned int tiling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj{ubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKXhjwubj@)}(hhh]h)}(h tiling modeh]h tiling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKXhjubah}(h]h ]h"]h$]h&]uh1j?hjwubeh}(h]h ]h"]h$]h&]uh1jhjhKXhjubj)}(h&``unsigned int stride`` tiling stride h](j$)}(h``unsigned int stride``h]j*)}(hjh]hunsigned int stride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKYhjubj@)}(hhh]h)}(h tiling strideh]h tiling stride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKYhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKYhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK[hjubh)}(hReturn the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.h]hReturn the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKZhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&i915_gem_set_tiling_ioctl (C function)c.i915_gem_set_tiling_ioctlhNtauh1jhjhhhNhNubj)}(hhh](j)}(hYint i915_gem_set_tiling_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j)}(hXint i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *file)h](jn)}(hinth]hint}(hj6hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj2hhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMIubj )}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2hhhjDhMIubj)}(hi915_gem_set_tiling_ioctlh]j)}(hi915_gem_set_tiling_ioctlh]hi915_gem_set_tiling_ioctl}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj2hhhjDhMIubj8)}(h;(struct drm_device *dev, void *data, struct drm_file *file)h](j>)}(hstruct drm_device *devh](jD)}(hjGh]hstruct}(hjshhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjoubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjoubh)}(hhh]j)}(h drm_deviceh]h drm_device}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjYsbc.i915_gem_set_tiling_ioctlasbuh1hhjoubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjoubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hdevh]hdev}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjkubj>)}(h void *datah](jn)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjkubj>)}(hstruct drm_file *fileh](jD)}(hjGh]hstruct}(hj'hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj#ubj )}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj#ubh)}(hhh]j)}(hdrm_fileh]hdrm_file}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjGmodnameN classnameNjj)}j]jc.i915_gem_set_tiling_ioctlasbuh1hhj#ubj )}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj#ubj)}(hjh]h*}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hfileh]hfile}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjkubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj2hhhjDhMIubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj.hhhjDhMIubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1jhjDhMIhj+hhubj)}(hhh]h)}(h IOCTL handler to set tiling modeh]h IOCTL handler to set tiling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMIhjhhubah}(h]h ]h"]h$]h&]uh1jhj+hhhjDhMIubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hXp**Parameters** ``struct drm_device *dev`` DRM device ``void *data`` data pointer for the ioctl ``struct drm_file *file`` DRM file for the ioctl call **Description** Sets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object. Called by the user via ioctl. **Return** Zero on success, negative errno on failure.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMMhjubj)}(hhh](j)}(h&``struct drm_device *dev`` DRM device h](j$)}(h``struct drm_device *dev``h]j*)}(hjh]hstruct drm_device *dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMJhjubj@)}(hhh]h)}(h DRM deviceh]h DRM device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMJhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMJhjubj)}(h*``void *data`` data pointer for the ioctl h](j$)}(h``void *data``h]j*)}(hj"h]h void *data}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMKhjubj@)}(hhh]h)}(hdata pointer for the ioctlh]hdata pointer for the ioctl}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMKhj8ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj7hMKhjubj)}(h6``struct drm_file *file`` DRM file for the ioctl call h](j$)}(h``struct drm_file *file``h]j*)}(hj[h]hstruct drm_file *file}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjYubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMLhjUubj@)}(hhh]h)}(hDRM file for the ioctl callh]hDRM file for the ioctl call}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphMLhjqubah}(h]h ]h"]h$]h&]uh1j?hjUubeh}(h]h ]h"]h$]h&]uh1jhjphMLhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMNhjubh)}(hhSets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object.h]hhSets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMMhjubh)}(hCalled by the user via ioctl.h]hCalled by the user via ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMPhjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMRhjubh)}(h+Zero on success, negative errno on failure.h]h+Zero on success, negative errno on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMShjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&i915_gem_get_tiling_ioctl (C function)c.i915_gem_get_tiling_ioctlhNtauh1jhjhhhNhNubj)}(hhh](j)}(hYint i915_gem_get_tiling_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j)}(hXint i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *file)h](jn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj hhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj hhhjhMubj)}(hi915_gem_get_tiling_ioctlh]j)}(hi915_gem_get_tiling_ioctlh]hi915_gem_get_tiling_ioctl}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj hhhjhMubj8)}(h;(struct drm_device *dev, void *data, struct drm_file *file)h](j>)}(hstruct drm_device *devh](jD)}(hjGh]hstruct}(hjNhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjJubj )}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjJubh)}(hhh]j)}(h drm_deviceh]h drm_device}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjnmodnameN classnameNjj)}j]j)}jj4sbc.i915_gem_get_tiling_ioctlasbuh1hhjJubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjJubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubj)}(hdevh]hdev}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjFubj>)}(h void *datah](jn)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjFubj>)}(hstruct drm_file *fileh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hdrm_fileh]hdrm_file}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj"modnameN classnameNjj)}j]jc.i915_gem_get_tiling_ioctlasbuh1hhjubj )}(h h]h }(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hfileh]hfile}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjFubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj hhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj hhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h IOCTL handler to get tiling modeh]h IOCTL handler to get tiling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hXT**Parameters** ``struct drm_device *dev`` DRM device ``void *data`` data pointer for the ioctl ``struct drm_file *file`` DRM file for the ioctl call **Description** Returns the current tiling mode and required bit 6 swizzling for the object. Called by the user via ioctl. **Return** Zero on success, negative errno on failure.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubj)}(hhh](j)}(h&``struct drm_device *dev`` DRM device h](j$)}(h``struct drm_device *dev``h]j*)}(hjh]hstruct drm_device *dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubj@)}(hhh]h)}(h DRM deviceh]h DRM device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h*``void *data`` data pointer for the ioctl h](j$)}(h``void *data``h]j*)}(hjh]h void *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubj@)}(hhh]h)}(hdata pointer for the ioctlh]hdata pointer for the ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h6``struct drm_file *file`` DRM file for the ioctl call h](j$)}(h``struct drm_file *file``h]j*)}(hj6h]hstruct drm_file *file}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj4ubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhj0ubj@)}(hhh]h)}(hDRM file for the ioctl callh]hDRM file for the ioctl call}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMhjLubah}(h]h ]h"]h$]h&]uh1j?hj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjqh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubh)}(hLReturns the current tiling mode and required bit 6 swizzling for the object.h]hLReturns the current tiling mode and required bit 6 swizzling for the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubh)}(hCalled by the user via ioctl.h]hCalled by the user via ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubh)}(h+Zero on success, negative errno on failure.h]h+Zero on success, negative errno on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:288: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubh)}(h~i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace interface to declare fence register requirements.h]h~i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace interface to declare fence register requirements.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:291: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjhhubh)}(hIn principle GEM doesn't care at all about the internal data layout of an object, and hence it also doesn't care about tiling or swizzling. There's two exceptions:h]hIn principle GEM doesn’t care at all about the internal data layout of an object, and hence it also doesn’t care about tiling or swizzling. There’s two exceptions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:291: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjhhubj:)}(hhh](j:)}(hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there's only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.h]h)}(hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there's only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.h]hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there’s only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:291: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely. h]h)}(hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely.h]hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:291: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhj ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j;j;uh1j:hjhKhjhhubh)}(hSince neither of this applies for new tiling layouts on modern platforms like W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. Anything else can be handled in userspace entirely without the kernel's involvement.h]hSince neither of this applies for new tiling layouts on modern platforms like W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. Anything else can be handled in userspace entirely without the kernel’s involvement.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:291: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK$hjhhubeh}(h]object-tiling-ioctlsah ]h"]object tiling ioctlsah$]h&]uh1hhj.bhhhhhMubh)}(hhh](h)}(hProtected Objectsh]hProtected Objects}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChhhhhM'ubh)}(hPXP (Protected Xe Path) is a feature available in Gen12 and newer platforms. It allows execution and flip to display of protected (i.e. encrypted) objects. The SW support is enabled via the CONFIG_DRM_I915_PXP kconfig.h]hPXP (Protected Xe Path) is a feature available in Gen12 and newer platforms. It allows execution and flip to display of protected (i.e. encrypted) objects. The SW support is enabled via the CONFIG_DRM_I915_PXP kconfig.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:297: ./drivers/gpu/drm/i915/pxp/intel_pxp.chKhjChhubh)}(hXRObjects can opt-in to PXP encryption at creation time via the I915_GEM_CREATE_EXT_PROTECTED_CONTENT create_ext flag. For objects to be correctly protected they must be used in conjunction with a context created with the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. See the documentation of those two uapi flags for details and restrictions.h]hXRObjects can opt-in to PXP encryption at creation time via the I915_GEM_CREATE_EXT_PROTECTED_CONTENT create_ext flag. For objects to be correctly protected they must be used in conjunction with a context created with the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. See the documentation of those two uapi flags for details and restrictions.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:297: ./drivers/gpu/drm/i915/pxp/intel_pxp.chKhjChhubh)}(hXHProtected objects are tied to a pxp session; currently we only support one session, which i915 manages and whose index is available in the uapi (I915_PROTECTED_CONTENT_DEFAULT_SESSION) for use in instructions targeting protected objects. The session is invalidated by the HW when certain events occur (e.g. suspend/resume). When this happens, all the objects that were used with the session are marked as invalid and all contexts marked as using protected content are banned. Any further attempt at using them in an execbuf call is rejected, while flips are converted to black frames.h]hXHProtected objects are tied to a pxp session; currently we only support one session, which i915 manages and whose index is available in the uapi (I915_PROTECTED_CONTENT_DEFAULT_SESSION) for use in instructions targeting protected objects. The session is invalidated by the HW when certain events occur (e.g. suspend/resume). When this happens, all the objects that were used with the session are marked as invalid and all contexts marked as using protected content are banned. Any further attempt at using them in an execbuf call is rejected, while flips are converted to black frames.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:297: ./drivers/gpu/drm/i915/pxp/intel_pxp.chK#hjChhubh)}(hSome of the PXP setup operations are performed by the Management Engine, which is handled by the mei driver; communication between i915 and mei is performed via the mei_pxp component module.h]hSome of the PXP setup operations are performed by the Management Engine, which is handled by the mei driver; communication between i915 and mei is performed via the mei_pxp component module.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:297: ./drivers/gpu/drm/i915/pxp/intel_pxp.chK-hjChhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_pxp (C struct) c.intel_pxphNtauh1jhjChhhNhNubj)}(hhh](j)}(h intel_pxph]j)}(hstruct intel_pxph](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhKubj)}(h intel_pxph]j)}(hjh]h intel_pxp}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h pxp stateh]h pxp state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jhhhjChNhNubj)}(hX **Definition**:: struct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); }; **Members** ``ctrl_gt`` pointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform) ``platform_cfg_is_bad`` used to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called. ``kcr_base`` base mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile. ``gsccs_res`` resources for request submission for platforms that have a GSC engine. ``pxp_component`` i915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`. ``dev_link`` Enforce module relationship for power management ordering. ``pxp_component_added`` track if the pxp component has been added. Set and cleared in tee init and fini functions respectively. ``ce`` kernel-owned context used for PXP operations ``arb_mutex`` protects arb session start ``arb_is_valid`` tracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW. ``key_instance`` tracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one. ``tee_mutex`` protects the tee channel binding and messaging. ``stream_cmd`` LMEM obj used to send stream PXP commands to the GSC ``hw_state_invalidated`` if the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required. ``irq_enabled`` tracks the status of the kcr irqs ``termination`` tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`. ``session_work`` worker that manages session events. ``session_events`` pending session events, protected with gt->irq_lock.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubjA#)}(hXstruct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); };h]hXstruct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); };}hj(sbah}(h]h ]h"]h$]h&]j5j6uh1j@#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubh)}(h **Members**h]j)}(hj9h]hMembers}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK=hjubj)}(hhh](j)}(h``ctrl_gt`` pointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform) h](j$)}(h ``ctrl_gt``h]j*)}(hjXh]hctrl_gt}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjVubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjRubj@)}(hhh]h)}(hpointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform)h]hpointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform)}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjnubah}(h]h ]h"]h$]h&]uh1j?hjRubeh}(h]h ]h"]h$]h&]uh1jhjmhKhjOubj)}(hXf``platform_cfg_is_bad`` used to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called. h](j$)}(h``platform_cfg_is_bad``h]j*)}(hjh]hplatform_cfg_is_bad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK#hjubj@)}(hhh]h)}(hXMused to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called.h]hXMused to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK#hjOubj)}(h``kcr_base`` base mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile. h](j$)}(h ``kcr_base``h]j*)}(hjh]hkcr_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK)hjubj@)}(hhh]h)}(hbase mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile.h]hbase mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK(hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK)hjOubj)}(hU``gsccs_res`` resources for request submission for platforms that have a GSC engine. h](j$)}(h ``gsccs_res``h]j*)}(hjh]h gsccs_res}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK.hjubj@)}(hhh]h)}(hFresources for request submission for platforms that have a GSC engine.h]hFresources for request submission for platforms that have a GSC engine.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK.hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK.hjOubj)}(h``pxp_component`` i915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`. h](j$)}(h``pxp_component``h]j*)}(hj?h]h pxp_component}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj=ubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK>hj9ubj@)}(hhh]h)}(hi915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`.h](hi915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by }(hjXhhhNhNubh)}(h:c:type:`tee_mutex`h]j*)}(hjbh]h tee_mutex}(hjdhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hj`ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj tee_mutexuh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjOubj)}(hH``dev_link`` Enforce module relationship for power management ordering. h](j$)}(h ``dev_link``h]j*)}(hjh]hdev_link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKChjubj@)}(hhh]h)}(h:Enforce module relationship for power management ordering.h]h:Enforce module relationship for power management ordering.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKChjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKChjOubj)}(h``pxp_component_added`` track if the pxp component has been added. Set and cleared in tee init and fini functions respectively. h](j$)}(h``pxp_component_added``h]j*)}(hjh]hpxp_component_added}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKHhjubj@)}(hhh]h)}(hgtrack if the pxp component has been added. Set and cleared in tee init and fini functions respectively.h]hgtrack if the pxp component has been added. Set and cleared in tee init and fini functions respectively.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKGhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKHhjOubj)}(h4``ce`` kernel-owned context used for PXP operations h](j$)}(h``ce``h]j*)}(hjh]hce}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKLhj ubj@)}(hhh]h)}(h,kernel-owned context used for PXP operationsh]h,kernel-owned context used for PXP operations}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hKLhj%ubah}(h]h ]h"]h$]h&]uh1j?hj ubeh}(h]h ]h"]h$]h&]uh1jhj$hKLhjOubj)}(h)``arb_mutex`` protects arb session start h](j$)}(h ``arb_mutex``h]j*)}(hjHh]h arb_mutex}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjFubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKOhjBubj@)}(hhh]h)}(hprotects arb session starth]hprotects arb session start}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hKOhj^ubah}(h]h ]h"]h$]h&]uh1j?hjBubeh}(h]h ]h"]h$]h&]uh1jhj]hKOhjOubj)}(h``arb_is_valid`` tracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW. h](j$)}(h``arb_is_valid``h]j*)}(hjh]h arb_is_valid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKUhj{ubj@)}(hhh]h)}(htracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW.h]htracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can’t rely on the HW state of the session to know if it’s valid and need to track the status in SW.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKRhjubah}(h]h ]h"]h$]h&]uh1j?hj{ubeh}(h]h ]h"]h$]h&]uh1jhjhKUhjOubj)}(h``key_instance`` tracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one. h](j$)}(h``key_instance``h]j*)}(hjh]h key_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK\hjubj@)}(hhh]h)}(htracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one.h]htracks which key instance we’re on, so we can use it to determine if an object was created using the current key or a previous one.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKZhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK\hjOubj)}(h>``tee_mutex`` protects the tee channel binding and messaging. h](j$)}(h ``tee_mutex``h]j*)}(hjh]h tee_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK`hjubj@)}(hhh]h)}(h/protects the tee channel binding and messaging.h]h/protects the tee channel binding and messaging.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK`hj ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hK`hjOubj)}(hD``stream_cmd`` LMEM obj used to send stream PXP commands to the GSC h](j$)}(h``stream_cmd``h]j*)}(hj.h]h stream_cmd}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj,ubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKchj(ubj@)}(hhh]h)}(h4LMEM obj used to send stream PXP commands to the GSCh]h4LMEM obj used to send stream PXP commands to the GSC}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChKchjDubah}(h]h ]h"]h$]h&]uh1j?hj(ubeh}(h]h ]h"]h$]h&]uh1jhjChKchjOubj)}(h``hw_state_invalidated`` if the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required. h](j$)}(h``hw_state_invalidated``h]j*)}(hjgh]hhw_state_invalidated}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjeubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKmhjaubj@)}(hhh]h)}(hif the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required.h]hif the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKjhj}ubah}(h]h ]h"]h$]h&]uh1j?hjaubeh}(h]h ]h"]h$]h&]uh1jhj|hKmhjOubj)}(h2``irq_enabled`` tracks the status of the kcr irqs h](j$)}(h``irq_enabled``h]j*)}(hjh]h irq_enabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKqhjubj@)}(hhh]h)}(h!tracks the status of the kcr irqsh]h!tracks the status of the kcr irqs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKqhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKqhjOubj)}(h``termination`` tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`. h](j$)}(h``termination``h]j*)}(hjh]h termination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKuhjubj@)}(hhh]h)}(h{tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`.h](hdtracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in }(hjhhhNhNubh)}(h:c:type:`session_work`h]j*)}(hjh]h session_work}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj session_workuh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKthjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKthjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKuhjOubj)}(h5``session_work`` worker that manages session events. h](j$)}(h``session_work``h]j*)}(hj7h]h session_work}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj5ubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKyhj1ubj@)}(hhh]h)}(h#worker that manages session events.h]h#worker that manages session events.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhKyhjMubah}(h]h ]h"]h$]h&]uh1j?hj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhKyhjOubj)}(hG``session_events`` pending session events, protected with gt->irq_lock.h](j$)}(h``session_events``h]j*)}(hjph]hsession_events}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjnubah}(h]h ]h"]h$]h&]uh1j#hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKzhjjubj@)}(hhh]h)}(h4pending session events, protected with gt->irq_lock.h]h4pending session events, protected with gt->irq_lock.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:300: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK{hjubah}(h]h ]h"]h$]h&]uh1j?hjjubeh}(h]h ]h"]h$]h&]uh1jhjhKzhjOubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjChhhNhNubeh}(h]protected-objectsah ]h"]protected objectsah$]h&]uh1hhj.bhhhhhM'ubeh}(h](memory-management-and-command-submissionah ]h"](memory management and command submissionah$]h&]uh1hhhhhhhhKVubh)}(hhh](h)}(hMicrocontrollersh]hMicrocontrollers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM/ubh)}(hXyStarting from gen9, three microcontrollers are available on the HW: the graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the display microcontroller (DMC). The driver is responsible for loading the firmwares on the microcontrollers; the GuC and HuC firmwares are transferred to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.h]hXyStarting from gen9, three microcontrollers are available on the HW: the graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the display microcontroller (DMC). The driver is responsible for loading the firmwares on the microcontrollers; the GuC and HuC firmwares are transferred to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjhhubh)}(hhh](h)}(hWOPCMh]hWOPCM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM8ubh)}(hhh](h)}(h WOPCM Layouth]h WOPCM Layout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM;ubh)}(hThe layout of the WOPCM will be fixed after writing to GuC WOPCM size and offset registers whose values are calculated and determined by HuC/GuC firmware size and set of hardware requirements/restrictions as shown below:h]hThe layout of the WOPCM will be fixed after writing to GuC WOPCM size and offset registers whose values are calculated and determined by HuC/GuC firmware size and set of hardware requirements/restrictions as shown below:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:317: ./drivers/gpu/drm/i915/gt/intel_wopcm.chK hjhhubjA#)}(hX +=========> +====================+ <== WOPCM Top ^ | HW contexts RSVD | | +===> +====================+ <== GuC WOPCM Top | ^ | | | | | | | | | | | GuC | | | WOPCM | | | Size +--------------------+ WOPCM | | GuC FW RSVD | | | +--------------------+ | | | GuC Stack RSVD | | | +------------------- + | v | GuC WOPCM RSVD | | +===> +====================+ <== GuC WOPCM base | | WOPCM RSVD | | +------------------- + <== HuC Firmware Top v | HuC FW | +=========> +====================+ <== WOPCM Baseh]hX +=========> +====================+ <== WOPCM Top ^ | HW contexts RSVD | | +===> +====================+ <== GuC WOPCM Top | ^ | | | | | | | | | | | GuC | | | WOPCM | | | Size +--------------------+ WOPCM | | GuC FW RSVD | | | +--------------------+ | | | GuC Stack RSVD | | | +------------------- + | v | GuC WOPCM RSVD | | +===> +====================+ <== GuC WOPCM base | | WOPCM RSVD | | +------------------- + <== HuC Firmware Top v | HuC FW | +=========> +====================+ <== WOPCM Base}hjsbah}(h]h ]h"]h$]h&]j5j6uh1j@#h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:317: ./drivers/gpu/drm/i915/gt/intel_wopcm.chKhjhhubh)}(hGuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 context).h]hGuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 context).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:317: ./drivers/gpu/drm/i915/gt/intel_wopcm.chK&hjhhubeh}(h] wopcm-layoutah ]h"] wopcm layoutah$]h&]uh1hhjhhhhhM;ubeh}(h]wopcmah ]h"]wopcmah$]h&]uh1hhjhhhhhM8ubh)}(hhh](h)}(hGuCh]hGuC}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhMAubh)}(hThe GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is designed to offload some of the functionality usually performed by the host driver; currently the main operations it can take care of are:h]hThe GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is designed to offload some of the functionality usually performed by the host driver; currently the main operations it can take care of are:}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:323: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhj?hhubj:)}(hhh](j:)}(hGAuthentication of the HuC, which is required to fully enable HuC usage.h]h)}(hjdh]hGAuthentication of the HuC, which is required to fully enable HuC usage.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:323: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhjbubah}(h]h ]h"]h$]h&]uh1j:hj_ubj:)}(h@Low latency graphics context scheduling (a.k.a. GuC submission).h]h)}(hj|h]h@Low latency graphics context scheduling (a.k.a. GuC submission).}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:323: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhjzubah}(h]h ]h"]h$]h&]uh1j:hj_ubj:)}(hGT Power management. h]h)}(hGT Power management.h]hGT Power management.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:323: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhjubah}(h]h ]h"]h$]h&]uh1j:hj_ubeh}(h]h ]h"]h$]h&]j;j;uh1j:hjshKhj?hhubh)}(hThe enable_guc module parameter can be used to select which of those operations to enable within GuC. Note that not all the operations are supported on all gen9+ platforms.h]hThe enable_guc module parameter can be used to select which of those operations to enable within GuC. Note that not all the operations are supported on all gen9+ platforms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:323: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chK hj?hhubh)}(hX Enabling the GuC is not mandatory and therefore the firmware is only loaded if at least one of the operations is selected. However, not loading the GuC might result in the loss of some features that do require the GuC (currently just the HuC, but more are expected to land in the future).h]hX Enabling the GuC is not mandatory and therefore the firmware is only loaded if at least one of the operations is selected. However, not loading the GuC might result in the loss of some features that do require the GuC (currently just the HuC, but more are expected to land in the future).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:323: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chK$hj?hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_guc (C struct) c.intel_guchNtauh1jhj?hhhNhNubj)}(hhh](j)}(h intel_guch]j)}(hstruct intel_guch](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhKubj)}(h intel_guch]j)}(hjh]h intel_guc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hTop level structure of GuC.h]hTop level structure of GuC.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj'hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjBjjBjjjuh1jhhhj?hNhNubj)}(hX **Definition**:: struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; }; **Members** ``fw`` the GuC firmware ``log`` sub-structure containing GuC log related data and objects ``ct`` the command transport communication channel ``slpc`` sub-structure containing SLPC related data and objects ``capture`` the error-state-capture module's data and objects ``dbgfs_node`` debugfs node ``sched_engine`` Global engine used to submit requests to GuC ``stalled_request`` if GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed. ``submission_stall_reason`` reason why submission is stalled ``irq_lock`` protects GuC irq state ``msg_enabled_mask`` mask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message. ``outstanding_submission_g2h`` number of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle ``tlb_lookup`` xarray to store all pending TLB invalidation requests ``serial_slot`` id to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter. ``next_seqno`` the next id (sequence number) to allocate. ``interrupts`` pointers to GuC interrupt-managing functions. ``submission_state`` sub-structure for submission state protected by single lock ``submission_state.lock`` protects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero ``submission_state.guc_ids`` used to allocate new guc_ids, single-lrc ``submission_state.num_guc_ids`` Number of guc_ids, selftest feature to be able to reduce this number while testing. ``submission_state.guc_ids_bitmap`` used to allocate new guc_ids, multi-lrc ``submission_state.guc_id_list`` list of intel_context with valid guc_ids but no refs ``submission_state.guc_ids_in_use`` Number single-lrc guc_ids in use ``submission_state.destroyed_contexts`` list of contexts waiting to be destroyed (deregistered with the GuC) ``submission_state.destroyed_worker`` worker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping) ``submission_state.reset_fail_worker`` worker to trigger a GT reset after an engine reset fails ``submission_state.reset_fail_mask`` mask of engines that failed to reset ``submission_state.sched_disable_delay_ms`` schedule disable delay, in ms, for contexts ``submission_state.sched_disable_gucid_threshold`` threshold of min remaining available guc_ids before we start bypassing the schedule disable delay ``submission_supported`` tracks whether we support GuC submission on the current platform ``submission_selected`` tracks whether the user enabled GuC submission ``submission_initialized`` tracks whether GuC submission has been initialised ``submission_version`` Submission API version of the currently loaded firmware ``rc_supported`` tracks whether we support GuC rc on the current platform ``rc_selected`` tracks whether the user enabled GuC rc ``ads_vma`` object allocated to hold the GuC ADS ``ads_map`` contents of the GuC ADS ``ads_regset_size`` size of the save/restore regsets in the ADS ``ads_regset_count`` number of save/restore registers in the ADS for each engine ``ads_regset`` save/restore regsets in the ADS ``ads_golden_ctxt_size`` size of the golden contexts in the ADS ``ads_waklv_size`` size of workaround KLVs ``ads_capture_size`` size of register lists in the ADS used for error capture ``lrc_desc_pool_v69`` object allocated to hold the GuC LRC descriptor pool ``lrc_desc_pool_vaddr_v69`` contents of the GuC LRC descriptor pool ``context_lookup`` used to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC ``params`` Control params for fw initialization ``send_regs`` GuC's FW specific registers used for sending MMIO H2G ``notify_reg`` register used to send interrupts to the GuC FW ``mmio_msg`` notification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up. ``send_mutex`` used to serialize the intel_guc_send actions ``timestamp`` GT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker. ``timestamp.lock`` Lock protecting the below fields and the engine stats. ``timestamp.gt_stamp`` 64-bit extended value of the GT timestamp. ``timestamp.ping_delay`` Period for polling the GT timestamp for overflow. ``timestamp.work`` Periodic work to adjust GT timestamp, engine and context usage for overflows. ``timestamp.shift`` Right shift value for the gpm timestamp ``timestamp.last_stat_jiffies`` jiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required. ``dead_guc_worker`` Asynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker. ``last_dead_guc_jiffies`` timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC. ``number_guc_id_stolen`` The number of guc_ids that have been stolen ``fast_response_selftest`` Backdoor to CT handler for fast response selftesth](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubh:}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK hjFubjA#)}(hX struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; };h]hX struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; };}hjgsbah}(h]h ]h"]h$]h&]j5j6uh1j@#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK"hjFubh)}(h **Members**h]j)}(hjxh]hMembers}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKuhjFubj)}(hhh](j)}(h``fw`` the GuC firmware h](j$)}(h``fw``h]j*)}(hjh]hfw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK#hjubj@)}(hhh]h)}(hthe GuC firmwareh]hthe GuC firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK#hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK#hjubj)}(hB``log`` sub-structure containing GuC log related data and objects h](j$)}(h``log``h]j*)}(hjh]hlog}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK%hjubj@)}(hhh]h)}(h9sub-structure containing GuC log related data and objectsh]h9sub-structure containing GuC log related data and objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK%hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK%hjubj)}(h3``ct`` the command transport communication channel h](j$)}(h``ct``h]j*)}(hj h]hct}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK'hjubj@)}(hhh]h)}(h+the command transport communication channelh]h+the command transport communication channel}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK'hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK'hjubj)}(h@``slpc`` sub-structure containing SLPC related data and objects h](j$)}(h``slpc``h]j*)}(hjBh]hslpc}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj@ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK)hj<ubj@)}(hhh]h)}(h6sub-structure containing SLPC related data and objectsh]h6sub-structure containing SLPC related data and objects}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhK)hjXubah}(h]h ]h"]h$]h&]uh1j?hj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhK)hjubj)}(h>``capture`` the error-state-capture module's data and objects h](j$)}(h ``capture``h]j*)}(hj{h]hcapture}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjyubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK+hjuubj@)}(hhh]h)}(h1the error-state-capture module's data and objectsh]h3the error-state-capture module’s data and objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK+hjubah}(h]h ]h"]h$]h&]uh1j?hjuubeh}(h]h ]h"]h$]h&]uh1jhjhK+hjubj)}(h``dbgfs_node`` debugfs node h](j$)}(h``dbgfs_node``h]j*)}(hjh]h dbgfs_node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK.hjubj@)}(hhh]h)}(h debugfs nodeh]h debugfs node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK.hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK.hjubj)}(h>``sched_engine`` Global engine used to submit requests to GuC h](j$)}(h``sched_engine``h]j*)}(hjh]h sched_engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK1hjubj@)}(hhh]h)}(h,Global engine used to submit requests to GuCh]h,Global engine used to submit requests to GuC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK1hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK1hjubj)}(h``stalled_request`` if GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed. h](j$)}(h``stalled_request``h]j*)}(hj&h]hstalled_request}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj$ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK6hj ubj@)}(hhh]h)}(hif GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed.h]hif GuC can’t process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK4hj<ubah}(h]h ]h"]h$]h&]uh1j?hj ubeh}(h]h ]h"]h$]h&]uh1jhj;hK6hjubj)}(h=``submission_stall_reason`` reason why submission is stalled h](j$)}(h``submission_stall_reason``h]j*)}(hj`h]hsubmission_stall_reason}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj^ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK:hjZubj@)}(hhh]h)}(h reason why submission is stalledh]h reason why submission is stalled}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhK:hjvubah}(h]h ]h"]h$]h&]uh1j?hjZubeh}(h]h ]h"]h$]h&]uh1jhjuhK:hjubj)}(h$``irq_lock`` protects GuC irq state h](j$)}(h ``irq_lock``h]j*)}(hjh]hirq_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKDhjubj@)}(hhh]h)}(hprotects GuC irq stateh]hprotects GuC irq state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKDhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKDhjubj)}(ho``msg_enabled_mask`` mask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message. h](j$)}(h``msg_enabled_mask``h]j*)}(hjh]hmsg_enabled_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKHhjubj@)}(hhh]h)}(hYmask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message.h]hYmask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKGhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKHhjubj)}(h``outstanding_submission_g2h`` number of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle h](j$)}(h``outstanding_submission_g2h``h]j*)}(hj h]houtstanding_submission_g2h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKOhjubj@)}(hhh]h)}(hjnumber of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idleh]hjnumber of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKMhj"ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj!hKOhjubj)}(hE``tlb_lookup`` xarray to store all pending TLB invalidation requests h](j$)}(h``tlb_lookup``h]j*)}(hjFh]h tlb_lookup}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjDubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKShj@ubj@)}(hhh]h)}(h5xarray to store all pending TLB invalidation requestsh]h5xarray to store all pending TLB invalidation requests}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hKShj\ubah}(h]h ]h"]h$]h&]uh1j?hj@ubeh}(h]h ]h"]h$]h&]uh1jhj[hKShjubj)}(hw``serial_slot`` id to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter. h](j$)}(h``serial_slot``h]j*)}(hjh]h serial_slot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj}ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKXhjyubj@)}(hhh]h)}(hfid to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter.h]hfid to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKWhjubah}(h]h ]h"]h$]h&]uh1j?hjyubeh}(h]h ]h"]h$]h&]uh1jhjhKXhjubj)}(h:``next_seqno`` the next id (sequence number) to allocate. h](j$)}(h``next_seqno``h]j*)}(hjh]h next_seqno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK\hjubj@)}(hhh]h)}(h*the next id (sequence number) to allocate.h]h*the next id (sequence number) to allocate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK\hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK\hjubj)}(h=``interrupts`` pointers to GuC interrupt-managing functions. h](j$)}(h``interrupts``h]j*)}(hjh]h interrupts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK_hjubj@)}(hhh]h)}(h-pointers to GuC interrupt-managing functions.h]h-pointers to GuC interrupt-managing functions.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK_hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK_hjubj)}(hQ``submission_state`` sub-structure for submission state protected by single lock h](j$)}(h``submission_state``h]j*)}(hj+h]hsubmission_state}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj)ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKihj%ubj@)}(hhh]h)}(h;sub-structure for submission state protected by single lockh]h;sub-structure for submission state protected by single lock}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhhjAubah}(h]h ]h"]h$]h&]uh1j?hj%ubeh}(h]h ]h"]h$]h&]uh1jhj@hKihjubj)}(h``submission_state.lock`` protects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero h](j$)}(h``submission_state.lock``h]j*)}(hjeh]hsubmission_state.lock}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjcubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKohj_ubj@)}(hhh]h)}(hpprotects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zeroh]hpprotects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKmhj{ubah}(h]h ]h"]h$]h&]uh1j?hj_ubeh}(h]h ]h"]h$]h&]uh1jhjzhKohjubj)}(hF``submission_state.guc_ids`` used to allocate new guc_ids, single-lrc h](j$)}(h``submission_state.guc_ids``h]j*)}(hjh]hsubmission_state.guc_ids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKthjubj@)}(hhh]h)}(h(used to allocate new guc_ids, single-lrch]h(used to allocate new guc_ids, single-lrc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKshjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKthjubj)}(hu``submission_state.num_guc_ids`` Number of guc_ids, selftest feature to be able to reduce this number while testing. h](j$)}(h ``submission_state.num_guc_ids``h]j*)}(hjh]hsubmission_state.num_guc_ids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKyhjubj@)}(hhh]h)}(hSNumber of guc_ids, selftest feature to be able to reduce this number while testing.h]hSNumber of guc_ids, selftest feature to be able to reduce this number while testing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKxhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKyhjubj)}(hL``submission_state.guc_ids_bitmap`` used to allocate new guc_ids, multi-lrc h](j$)}(h#``submission_state.guc_ids_bitmap``h]j*)}(hjh]hsubmission_state.guc_ids_bitmap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK~hj ubj@)}(hhh]h)}(h'used to allocate new guc_ids, multi-lrch]h'used to allocate new guc_ids, multi-lrc}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK}hj)ubah}(h]h ]h"]h$]h&]uh1j?hj ubeh}(h]h ]h"]h$]h&]uh1jhj(hK~hjubj)}(hV``submission_state.guc_id_list`` list of intel_context with valid guc_ids but no refs h](j$)}(h ``submission_state.guc_id_list``h]j*)}(hjMh]hsubmission_state.guc_id_list}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjKubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjGubj@)}(hhh]h)}(h4list of intel_context with valid guc_ids but no refsh]h4list of intel_context with valid guc_ids but no refs}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjcubah}(h]h ]h"]h$]h&]uh1j?hjGubeh}(h]h ]h"]h$]h&]uh1jhjbhKhjubj)}(hE``submission_state.guc_ids_in_use`` Number single-lrc guc_ids in use h](j$)}(h#``submission_state.guc_ids_in_use``h]j*)}(hjh]hsubmission_state.guc_ids_in_use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h Number single-lrc guc_ids in useh]h Number single-lrc guc_ids in use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hm``submission_state.destroyed_contexts`` list of contexts waiting to be destroyed (deregistered with the GuC) h](j$)}(h'``submission_state.destroyed_contexts``h]j*)}(hjh]h#submission_state.destroyed_contexts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(hDlist of contexts waiting to be destroyed (deregistered with the GuC)h]hDlist of contexts waiting to be destroyed (deregistered with the GuC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``submission_state.destroyed_worker`` worker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping) h](j$)}(h%``submission_state.destroyed_worker``h]j*)}(hjh]h!submission_state.destroyed_worker}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(hworker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping)h]hworker to deregister contexts, need as we need to take a GT PM reference and can’t from destroy function as it might be in an atomic context (no sleeping)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h```submission_state.reset_fail_worker`` worker to trigger a GT reset after an engine reset fails h](j$)}(h&``submission_state.reset_fail_worker``h]j*)}(hj5h]h"submission_state.reset_fail_worker}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj3ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj/ubj@)}(hhh]h)}(h8worker to trigger a GT reset after an engine reset failsh]h8worker to trigger a GT reset after an engine reset fails}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjKubah}(h]h ]h"]h$]h&]uh1j?hj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhKhjubj)}(hJ``submission_state.reset_fail_mask`` mask of engines that failed to reset h](j$)}(h$``submission_state.reset_fail_mask``h]j*)}(hjoh]h submission_state.reset_fail_mask}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjmubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjiubj@)}(hhh]h)}(h$mask of engines that failed to reseth]h$mask of engines that failed to reset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjiubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hX``submission_state.sched_disable_delay_ms`` schedule disable delay, in ms, for contexts h](j$)}(h+``submission_state.sched_disable_delay_ms``h]j*)}(hjh]h'submission_state.sched_disable_delay_ms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h+schedule disable delay, in ms, for contextsh]h+schedule disable delay, in ms, for contexts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``submission_state.sched_disable_gucid_threshold`` threshold of min remaining available guc_ids before we start bypassing the schedule disable delay h](j$)}(h2``submission_state.sched_disable_gucid_threshold``h]j*)}(hjh]h.submission_state.sched_disable_gucid_threshold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(hathreshold of min remaining available guc_ids before we start bypassing the schedule disable delayh]hathreshold of min remaining available guc_ids before we start bypassing the schedule disable delay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hZ``submission_supported`` tracks whether we support GuC submission on the current platform h](j$)}(h``submission_supported``h]j*)}(hjh]hsubmission_supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h@tracks whether we support GuC submission on the current platformh]h@tracks whether we support GuC submission on the current platform}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj3ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj2hKhjubj)}(hG``submission_selected`` tracks whether the user enabled GuC submission h](j$)}(h``submission_selected``h]j*)}(hjWh]hsubmission_selected}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjUubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjQubj@)}(hhh]h)}(h.tracks whether the user enabled GuC submissionh]h.tracks whether the user enabled GuC submission}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhKhjmubah}(h]h ]h"]h$]h&]uh1j?hjQubeh}(h]h ]h"]h$]h&]uh1jhjlhKhjubj)}(hN``submission_initialized`` tracks whether GuC submission has been initialised h](j$)}(h``submission_initialized``h]j*)}(hjh]hsubmission_initialized}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h2tracks whether GuC submission has been initialisedh]h2tracks whether GuC submission has been initialised}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hO``submission_version`` Submission API version of the currently loaded firmware h](j$)}(h``submission_version``h]j*)}(hjh]hsubmission_version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h7Submission API version of the currently loaded firmwareh]h7Submission API version of the currently loaded firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hJ``rc_supported`` tracks whether we support GuC rc on the current platform h](j$)}(h``rc_supported``h]j*)}(hjh]h rc_supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h8tracks whether we support GuC rc on the current platformh]h8tracks whether we support GuC rc on the current platform}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h7``rc_selected`` tracks whether the user enabled GuC rc h](j$)}(h``rc_selected``h]j*)}(hj;h]h rc_selected}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj9ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj5ubj@)}(hhh]h)}(h&tracks whether the user enabled GuC rch]h&tracks whether the user enabled GuC rc}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhKhjQubah}(h]h ]h"]h$]h&]uh1j?hj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhKhjubj)}(h1``ads_vma`` object allocated to hold the GuC ADS h](j$)}(h ``ads_vma``h]j*)}(hjth]hads_vma}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjrubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjnubj@)}(hhh]h)}(h$object allocated to hold the GuC ADSh]h$object allocated to hold the GuC ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjnubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h$``ads_map`` contents of the GuC ADS h](j$)}(h ``ads_map``h]j*)}(hjh]hads_map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(hcontents of the GuC ADSh]hcontents of the GuC ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h@``ads_regset_size`` size of the save/restore regsets in the ADS h](j$)}(h``ads_regset_size``h]j*)}(hjh]hads_regset_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h+size of the save/restore regsets in the ADSh]h+size of the save/restore regsets in the ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hQ``ads_regset_count`` number of save/restore registers in the ADS for each engine h](j$)}(h``ads_regset_count``h]j*)}(hjh]hads_regset_count}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h;number of save/restore registers in the ADS for each engineh]h;number of save/restore registers in the ADS for each engine}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj5ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj4hKhjubj)}(h/``ads_regset`` save/restore regsets in the ADS h](j$)}(h``ads_regset``h]j*)}(hjYh]h ads_regset}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjWubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjSubj@)}(hhh]h)}(hsave/restore regsets in the ADSh]hsave/restore regsets in the ADS}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhKhjoubah}(h]h ]h"]h$]h&]uh1j?hjSubeh}(h]h ]h"]h$]h&]uh1jhjnhKhjubj)}(h@``ads_golden_ctxt_size`` size of the golden contexts in the ADS h](j$)}(h``ads_golden_ctxt_size``h]j*)}(hjh]hads_golden_ctxt_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h&size of the golden contexts in the ADSh]h&size of the golden contexts in the ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h+``ads_waklv_size`` size of workaround KLVs h](j$)}(h``ads_waklv_size``h]j*)}(hjh]hads_waklv_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(hsize of workaround KLVsh]hsize of workaround KLVs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hN``ads_capture_size`` size of register lists in the ADS used for error capture h](j$)}(h``ads_capture_size``h]j*)}(hjh]hads_capture_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h8size of register lists in the ADS used for error captureh]h8size of register lists in the ADS used for error capture}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hK``lrc_desc_pool_v69`` object allocated to hold the GuC LRC descriptor pool h](j$)}(h``lrc_desc_pool_v69``h]j*)}(hj=h]hlrc_desc_pool_v69}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj;ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj7ubj@)}(hhh]h)}(h4object allocated to hold the GuC LRC descriptor poolh]h4object allocated to hold the GuC LRC descriptor pool}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhKhjSubah}(h]h ]h"]h$]h&]uh1j?hj7ubeh}(h]h ]h"]h$]h&]uh1jhjRhKhjubj)}(hD``lrc_desc_pool_vaddr_v69`` contents of the GuC LRC descriptor pool h](j$)}(h``lrc_desc_pool_vaddr_v69``h]j*)}(hjvh]hlrc_desc_pool_vaddr_v69}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjtubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjpubj@)}(hhh]h)}(h'contents of the GuC LRC descriptor poolh]h'contents of the GuC LRC descriptor pool}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjpubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``context_lookup`` used to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC h](j$)}(h``context_lookup``h]j*)}(hjh]hcontext_lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(hrused to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuCh]hrused to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h0``params`` Control params for fw initialization h](j$)}(h ``params``h]j*)}(hjh]hparams}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h$Control params for fw initializationh]h$Control params for fw initialization}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hD``send_regs`` GuC's FW specific registers used for sending MMIO H2G h](j$)}(h ``send_regs``h]j*)}(hj"h]h send_regs}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h5GuC's FW specific registers used for sending MMIO H2Gh]h7GuC’s FW specific registers used for sending MMIO H2G}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hKhj8ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj7hKhjubj)}(h>``notify_reg`` register used to send interrupts to the GuC FW h](j$)}(h``notify_reg``h]j*)}(hj[h]h notify_reg}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjYubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjUubj@)}(hhh]h)}(h.register used to send interrupts to the GuC FWh]h.register used to send interrupts to the GuC FW}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphKhjqubah}(h]h ]h"]h$]h&]uh1j?hjUubeh}(h]h ]h"]h$]h&]uh1jhjphKhjubj)}(h``mmio_msg`` notification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up. h](j$)}(h ``mmio_msg``h]j*)}(hjh]hmmio_msg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(hnotification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up.h]hnotification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h<``send_mutex`` used to serialize the intel_guc_send actions h](j$)}(h``send_mutex``h]j*)}(hjh]h send_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(h,used to serialize the intel_guc_send actionsh]h,used to serialize the intel_guc_send actions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hr``timestamp`` GT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker. h](j$)}(h ``timestamp``h]j*)}(hjh]h timestamp}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj@)}(hhh]h)}(hcGT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker.h]hcGT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hJ``timestamp.lock`` Lock protecting the below fields and the engine stats. h](j$)}(h``timestamp.lock``h]j*)}(hjAh]htimestamp.lock}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj?ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj;ubj@)}(hhh]h)}(h6Lock protecting the below fields and the engine stats.h]h6Lock protecting the below fields and the engine stats.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjWubah}(h]h ]h"]h$]h&]uh1j?hj;ubeh}(h]h ]h"]h$]h&]uh1jhjVhKhjubj)}(hB``timestamp.gt_stamp`` 64-bit extended value of the GT timestamp. h](j$)}(h``timestamp.gt_stamp``h]j*)}(hj{h]htimestamp.gt_stamp}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjyubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjuubj@)}(hhh]h)}(h*64-bit extended value of the GT timestamp.h]h*64-bit extended value of the GT timestamp.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubah}(h]h ]h"]h$]h&]uh1j?hjuubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hK``timestamp.ping_delay`` Period for polling the GT timestamp for overflow. h](j$)}(h``timestamp.ping_delay``h]j*)}(hjh]htimestamp.ping_delay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM hjubj@)}(hhh]h)}(h1Period for polling the GT timestamp for overflow.h]h1Period for polling the GT timestamp for overflow.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(ha``timestamp.work`` Periodic work to adjust GT timestamp, engine and context usage for overflows. h](j$)}(h``timestamp.work``h]j*)}(hjh]htimestamp.work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj@)}(hhh]h)}(hMPeriodic work to adjust GT timestamp, engine and context usage for overflows.h]hMPeriodic work to adjust GT timestamp, engine and context usage for overflows.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h<``timestamp.shift`` Right shift value for the gpm timestamp h](j$)}(h``timestamp.shift``h]j*)}(hj)h]htimestamp.shift}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj'ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj#ubj@)}(hhh]h)}(h'Right shift value for the gpm timestamph]h'Right shift value for the gpm timestamp}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj?ubah}(h]h ]h"]h$]h&]uh1j?hj#ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhjubj)}(h``timestamp.last_stat_jiffies`` jiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required. h](j$)}(h``timestamp.last_stat_jiffies``h]j*)}(hjbh]htimestamp.last_stat_jiffies}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj`ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj\ubj@)}(hhh]h)}(hjiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required.h]hjiffies at last actual stats collection time. We use this timestamp to ensure we don’t oversample the stats because runtime power management events can trigger stats collection at much higher rates than required.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjxubah}(h]h ]h"]h$]h&]uh1j?hj\ubeh}(h]h ]h"]h$]h&]uh1jhjwhMhjubj)}(hX ``dead_guc_worker`` Asynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker. h](j$)}(h``dead_guc_worker``h]j*)}(hjh]hdead_guc_worker}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM'hjubj@)}(hhh]h)}(hAsynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker.h]hAsynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM$hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM'hjubj)}(h``last_dead_guc_jiffies`` timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC. h](j$)}(h``last_dead_guc_jiffies``h]j*)}(hjh]hlast_dead_guc_jiffies}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM-hjubj@)}(hhh]h)}(h~timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC.h]htimestamp of previous ‘dead guc’ occurrence used to prevent a fundamentally broken system from continuously reloading the GuC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM+hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhM-hjubj)}(hE``number_guc_id_stolen`` The number of guc_ids that have been stolen h](j$)}(h``number_guc_id_stolen``h]j*)}(hjh]hnumber_guc_id_stolen}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM3hj ubj@)}(hhh]h)}(h+The number of guc_ids that have been stolenh]h+The number of guc_ids that have been stolen}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hM3hj&ubah}(h]h ]h"]h$]h&]uh1j?hj ubeh}(h]h ]h"]h$]h&]uh1jhj%hM3hjubj)}(hL``fast_response_selftest`` Backdoor to CT handler for fast response selftesth](j$)}(h``fast_response_selftest``h]j*)}(hjIh]hfast_response_selftest}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjGubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM6hjCubj@)}(hhh]h)}(h1Backdoor to CT handler for fast response selftesth]h1Backdoor to CT handler for fast response selftest}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM7hj_ubah}(h]h ]h"]h$]h&]uh1j?hjCubeh}(h]h ]h"]h$]h&]uh1jhj^hM6hjubeh}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj?hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM:hj?hhubh)}(hhIt handles firmware loading and manages client pool. intel_guc owns an i915_sched_engine for submission.h]hhIt handles firmware loading and manages client pool. intel_guc owns an i915_sched_engine for submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj?hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_guc_ggtt_offset (C function)c.intel_guc_ggtt_offsethNtauh1jhj?hhhNhNubj)}(hhh](j)}(hGu32 intel_guc_ggtt_offset (struct intel_guc *guc, struct i915_vma *vma)h]j)}(hFu32 intel_guc_ggtt_offset(struct intel_guc *guc, struct i915_vma *vma)h](h)}(hhh]j)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jintel_guc_ggtt_offsetsbc.intel_guc_ggtt_offsetasbuh1hhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hintel_guc_ggtt_offseth]j)}(hjh]hintel_guc_ggtt_offset}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(h-(struct intel_guc *guc, struct i915_vma *vma)h](j>)}(hstruct intel_guc *guch](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h intel_guch]h intel_guc}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj<modnameN classnameNjj)}j]jc.intel_guc_ggtt_offsetasbuh1hhjubj )}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hguch]hguc}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hstruct i915_vma *vmah](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hi915_vmah]hi915_vma}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.intel_guc_ggtt_offsetasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hvmah]hvma}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h+Get and validate the GGTT offset of **vma**h](h$Get and validate the GGTT offset of }(hj hhhNhNubj)}(h**vma**h]hvma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj3jj3jjjuh1jhhhj?hNhNubj)}(hX**Parameters** ``struct intel_guc *guc`` intel_guc structure. ``struct i915_vma *vma`` i915 graphics virtual memory area. **Description** GuC does not allow any gfx GGTT address that falls into range [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. **Return** GGTT offset of the **vma**.h](h)}(h**Parameters**h]j)}(hj=h]h Parameters}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj7ubj)}(hhh](j)}(h/``struct intel_guc *guc`` intel_guc structure. h](j$)}(h``struct intel_guc *guc``h]j*)}(hj\h]hstruct intel_guc *guc}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjZubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjVubj@)}(hhh]h)}(hintel_guc structure.h]hintel_guc structure.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhMhjrubah}(h]h ]h"]h$]h&]uh1j?hjVubeh}(h]h ]h"]h$]h&]uh1jhjqhMhjSubj)}(h<``struct i915_vma *vma`` i915 graphics virtual memory area. h](j$)}(h``struct i915_vma *vma``h]j*)}(hjh]hstruct i915_vma *vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj@)}(hhh]h)}(h"i915 graphics virtual memory area.h]h"i915 graphics virtual memory area.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjSubeh}(h]h ]h"]h$]h&]uh1jhj7ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj7ubh)}(hX[GuC does not allow any gfx GGTT address that falls into range [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.h]hX[GuC does not allow any gfx GGTT address that falls into range [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj7ubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj7ubh)}(hGGTT offset of the **vma**.h](hGGTT offset of the }(hj hhhNhNubj)}(h**vma**h]hvma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:326: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj?hhhNhNubh)}(hhh](h)}(hGuC Firmware Layouth]hGuC Firmware Layout}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhMIubh)}(h-The GuC/HuC firmware layout looks like this::h]h,The GuC/HuC firmware layout looks like this:}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK hj5hhubjA#)}(hX+======================================================================+ | Firmware blob | +===============+===============+============+============+============+ | CSS header | uCode | RSA key | modulus | exponent | +===============+===============+============+============+============+ <-header size-> <---header size continued -----------> <--- size -----------------------------------------------------------> <-key size-> <-mod size-> <-exp size->h]hX+======================================================================+ | Firmware blob | +===============+===============+============+============+============+ | CSS header | uCode | RSA key | modulus | exponent | +===============+===============+============+============+============+ <-header size-> <---header size continued -----------> <--- size -----------------------------------------------------------> <-key size-> <-mod size-> <-exp size->}hjUsbah}(h]h ]h"]h$]h&]j5j6uh1j@#hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhKhj5hhubh)}(hXbThe firmware may or may not have modulus key and exponent data. The header, uCode and RSA signature are must-have components that will be used by driver. Length of each components, which is all in dwords, can be found in header. In the case that modulus and exponent are not present in fw, a.k.a truncated image, the length value still appears in header.h]hXbThe firmware may or may not have modulus key and exponent data. The header, uCode and RSA signature are must-have components that will be used by driver. Length of each components, which is all in dwords, can be found in header. In the case that modulus and exponent are not present in fw, a.k.a truncated image, the length value still appears in header.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhKhj5hhubh)}(hJDriver will do some basic fw size validation based on the following rules:h]hJDriver will do some basic fw size validation based on the following rules:}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK hj5hhubj;)}(hhh](j:)}(h/Header, uCode and RSA are must-have components.h]h)}(hjh]h/Header, uCode and RSA are must-have components.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK"hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.h]h)}(hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.h]hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK#hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h@Length info of each component can be found in header, in dwords.h]h)}(hjh]h@Length info of each component can be found in header, in dwords.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK%hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case. h]h)}(hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case.h]hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK&hjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j;j;j;hj;j;uh1j;hj5hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhNubh)}(hXStarting from DG2, the HuC is loaded by the GSC instead of i915. The GSC firmware performs all the required integrity checks, we just need to check the version. Note that the header for GSC-managed blobs is different from the CSS used for dma-loaded firmwares.h]hXStarting from DG2, the HuC is loaded by the GSC instead of i915. The GSC firmware performs all the required integrity checks, we just need to check the version. Note that the header for GSC-managed blobs is different from the CSS used for dma-loaded firmwares.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:331: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK)hj5hhubeh}(h]guc-firmware-layoutah ]h"]guc firmware layoutah$]h&]uh1hhj?hhhhhMIjdKubh)}(hhh](h)}(hGuC Memory Managementh]hGuC Memory Management}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMOubh)}(hXGuC can't allocate any memory for its own usage, so all the allocations must be handled by the host driver. GuC accesses the memory via the GGTT, with the exception of the top and bottom parts of the 4GB address space, which are instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM) or other parts of the HW. The driver must take care not to place objects that the GuC is going to access in these reserved ranges. The layout of the GuC address space is shown below:h]hXGuC can’t allocate any memory for its own usage, so all the allocations must be handled by the host driver. GuC accesses the memory via the GGTT, with the exception of the top and bottom parts of the 4GB address space, which are instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM) or other parts of the HW. The driver must take care not to place objects that the GuC is going to access in these reserved ranges. The layout of the GuC address space is shown below:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:337: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjhhubjA#)}(hX +===========> +====================+ <== FFFF_FFFF ^ | Reserved | | +====================+ <== GUC_GGTT_TOP | | | | | DRAM | GuC | | Address +===> +====================+ <== GuC ggtt_pin_bias Space ^ | | | | | | | GuC | GuC | | WOPCM | WOPCM | | Size | | | | | | v v | | +=======+===> +====================+ <== 0000_0000h]hX +===========> +====================+ <== FFFF_FFFF ^ | Reserved | | +====================+ <== GUC_GGTT_TOP | | | | | DRAM | GuC | | Address +===> +====================+ <== GuC ggtt_pin_bias Space ^ | | | | | | | GuC | GuC | | WOPCM | WOPCM | | Size | | | | | | v v | | +=======+===> +====================+ <== 0000_0000}hj%sbah}(h]h ]h"]h$]h&]j5j6uh1j@#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:337: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjhhubh)}(hThe lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.h]hThe lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:337: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#intel_guc_allocate_vma (C function)c.intel_guc_allocate_vmahNtauh1jhjhhhNhNubj)}(hhh](j)}(hJstruct i915_vma * intel_guc_allocate_vma (struct intel_guc *guc, u32 size)h]j)}(hHstruct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)h](jD)}(hjGh]hstruct}(hj\hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjXhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMubj )}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXhhhjihMubh)}(hhh]j)}(hi915_vmah]hi915_vma}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj}modnameN classnameNjj)}j]j)}jintel_guc_allocate_vmasbc.intel_guc_allocate_vmaasbuh1hhjXhhhjihMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXhhhjihMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXhhhjihMubj)}(hintel_guc_allocate_vmah]j)}(hjh]hintel_guc_allocate_vma}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjXhhhjihMubj8)}(h!(struct intel_guc *guc, u32 size)h](j>)}(hstruct intel_guc *guch](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h intel_guch]h intel_guc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.intel_guc_allocate_vmaasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hguch]hguc}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hu32 sizeh](h)}(hhh]j)}(hu32h]hu32}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjKmodnameN classnameNjj)}j]jc.intel_guc_allocate_vmaasbuh1hhjBubj )}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBubj)}(hsizeh]hsize}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjXhhhjihMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjThhhjihMubah}(h]jOah ](jjeh"]h$]h&]jj)jhuh1jhjihMhjQhhubj)}(hhh]h)}(h!Allocate a GGTT VMA for GuC usageh]h!Allocate a GGTT VMA for GuC usage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjQhhhjihMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct intel_guc *guc`` the guc ``u32 size`` size of area to allocate (both virtual space and memory) **Description** This is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC. **Return** A i915_vma if successful, otherwise an ERR_PTR.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubj)}(hhh](j)}(h"``struct intel_guc *guc`` the guc h](j$)}(h``struct intel_guc *guc``h]j*)}(hjh]hstruct intel_guc *guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubj@)}(hhh]h)}(hthe guch]hthe guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hF``u32 size`` size of area to allocate (both virtual space and memory) h](j$)}(h ``u32 size``h]j*)}(hjh]hu32 size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubj@)}(hhh]h)}(h8size of area to allocate (both virtual space and memory)h]h8size of area to allocate (both virtual space and memory)}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj/ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj.hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjTh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubh)}(hXHThis is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC.h]hXHThis is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubh)}(h **Return**h]j)}(hj{h]hReturn}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubh)}(h/A i915_vma if successful, otherwise an ERR_PTR.h]h/A i915_vma if successful, otherwise an ERR_PTR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:339: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h]guc-memory-managementah ]h"]guc memory managementah$]h&]uh1hhj?hhhhhMOubh)}(hhh](h)}(hGuC-specific firmware loaderh]hGuC-specific firmware loader}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMXubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j intel_guc_fw_upload (C function)c.intel_guc_fw_uploadhNtauh1jhjhhhNhNubj)}(hhh](j)}(h/int intel_guc_fw_upload (struct intel_guc *guc)h]j)}(h.int intel_guc_fw_upload(struct intel_guc *guc)h](jn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hintel_guc_fw_uploadh]j)}(hintel_guc_fw_uploadh]hintel_guc_fw_upload}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(h(struct intel_guc *guc)h]j>)}(hstruct intel_guc *guch](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(h intel_guch]h intel_guc}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj6modnameN classnameNjj)}j]j)}jjsbc.intel_guc_fw_uploadasbuh1hhjubj )}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hguch]hguc}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hload GuC uCode to deviceh]hload GuC uCode to device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX_**Parameters** ``struct intel_guc *guc`` intel_guc structure **Description** Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset. The firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w. **Return** non-zero code on errorh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chM"hjubj)}(hhh]j)}(h.``struct intel_guc *guc`` intel_guc structure h](j$)}(h``struct intel_guc *guc``h]j*)}(hjh]hstruct intel_guc *guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjubj@)}(hhh]h)}(hintel_guc structureh]hintel_guc structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chM!hjubh)}(h[Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset.h]h[Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chM hjubh)}(hThe firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w.h]hThe firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chM#hjubh)}(h **Return**h]j)}(hjKh]hReturn}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chM&hjubh)}(hnon-zero code on errorh]hnon-zero code on error}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:346: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chM'hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h]guc-specific-firmware-loaderah ]h"]guc-specific firmware loaderah$]h&]uh1hhj?hhhhhMXubh)}(hhh](h)}(hGuC-based command submissionh]hGuC-based command submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM^ubh)}(hXThe Scratch registers: There are 16 MMIO-based registers start from 0xC180. The kernel driver writes a value to the action register (SOFT_SCRATCH_0) along with any data. It then triggers an interrupt on the GuC via another register write (0xC4C8). Firmware writes a success/fail code back to the action register after processes the request. The kernel driver polls waiting for this update and then proceeds.h]hXThe Scratch registers: There are 16 MMIO-based registers start from 0xC180. The kernel driver writes a value to the action register (SOFT_SCRATCH_0) along with any data. It then triggers an interrupt on the GuC via another register write (0xC4C8). Firmware writes a success/fail code back to the action register after processes the request. The kernel driver polls waiting for this update and then proceeds.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK'hjhhubh)}(hCommand Transport buffers (CTBs): Covered in detail in other sections but CTBs (Host to GuC - H2G, GuC to Host - G2H) are a message interface between the i915 and GuC.h]hCommand Transport buffers (CTBs): Covered in detail in other sections but CTBs (Host to GuC - H2G, GuC to Host - G2H) are a message interface between the i915 and GuC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK/hjhhubh)}(hX#Context registration: Before a context can be submitted it must be registered with the GuC via a H2G. A unique guc_id is associated with each context. The context is either registered at request creation time (normal operation) or at submission time (abnormal operation, e.g. after a reset).h]hX#Context registration: Before a context can be submitted it must be registered with the GuC via a H2G. A unique guc_id is associated with each context. The context is either registered at request creation time (normal operation) or at submission time (abnormal operation, e.g. after a reset).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK3hjhhubh)}(hXContext submission: The i915 updates the LRC tail value in memory. The i915 must enable the scheduling of the context within the GuC for the GuC to actually consider it. Therefore, the first time a disabled context is submitted we use a schedule enable H2G, while follow up submissions are done via the context submit H2G, which informs the GuC that a previously enabled context has new work available.h]hXContext submission: The i915 updates the LRC tail value in memory. The i915 must enable the scheduling of the context within the GuC for the GuC to actually consider it. Therefore, the first time a disabled context is submitted we use a schedule enable H2G, while follow up submissions are done via the context submit H2G, which informs the GuC that a previously enabled context has new work available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK9hjhhubh)}(hX7Context unpin: To unpin a context a H2G is used to disable scheduling. When the corresponding G2H returns indicating the scheduling disable operation has completed it is safe to unpin the context. While a disable is in flight it isn't safe to resubmit the context so a fence is used to stall all future requests of that context until the G2H is returned. Because this interaction with the GuC takes a non-zero amount of time we delay the disabling of scheduling after the pin count goes to zero by a configurable period of time (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a window of time to resubmit something on the context before doing this costly operation. This delay is only done if the context isn't closed and the guc_id usage is less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).h]hX;Context unpin: To unpin a context a H2G is used to disable scheduling. When the corresponding G2H returns indicating the scheduling disable operation has completed it is safe to unpin the context. While a disable is in flight it isn’t safe to resubmit the context so a fence is used to stall all future requests of that context until the G2H is returned. Because this interaction with the GuC takes a non-zero amount of time we delay the disabling of scheduling after the pin count goes to zero by a configurable period of time (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a window of time to resubmit something on the context before doing this costly operation. This delay is only done if the context isn’t closed and the guc_id usage is less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKAhjhhubh)}(hXContext deregistration: Before a context can be destroyed or if we steal its guc_id we must deregister the context with the GuC via H2G. If stealing the guc_id it isn't safe to submit anything to this guc_id until the deregister completes so a fence is used to stall all requests associated with this guc_id until the corresponding G2H returns indicating the guc_id has been deregistered.h]hXContext deregistration: Before a context can be destroyed or if we steal its guc_id we must deregister the context with the GuC via H2G. If stealing the guc_id it isn’t safe to submit anything to this guc_id until the deregister completes so a fence is used to stall all requests associated with this guc_id until the corresponding G2H returns indicating the guc_id has been deregistered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKNhjhhubh)}(hsubmission_state.guc_ids: Unique number associated with private GuC context data passed in during context registration / submission / deregistration. 64k available. Simple ida is used for allocation.h]hsubmission_state.guc_ids: Unique number associated with private GuC context data passed in during context registration / submission / deregistration. 64k available. Simple ida is used for allocation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKUhjhhubh)}(hX Stealing guc_ids: If no guc_ids are available they can be stolen from another context at request creation time if that context is unpinned. If a guc_id can't be found we punt this problem to the user as we believe this is near impossible to hit during normal use cases.h]hXStealing guc_ids: If no guc_ids are available they can be stolen from another context at request creation time if that context is unpinned. If a guc_id can’t be found we punt this problem to the user as we believe this is near impossible to hit during normal use cases.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKZhjhhubh)}(hrLocking: In the GuC submission code we have 3 basic spin locks which protect everything. Details about each below.h]hrLocking: In the GuC submission code we have 3 basic spin locks which protect everything. Details about each below.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK`hjhhubh)}(hX/sched_engine->lock This is the submission lock for all contexts that share an i915 schedule engine (sched_engine), thus only one of the contexts which share a sched_engine can be submitting at a time. Currently only one sched_engine is used for all of GuC submission but that could change in the future.h]hX/sched_engine->lock This is the submission lock for all contexts that share an i915 schedule engine (sched_engine), thus only one of the contexts which share a sched_engine can be submitting at a time. Currently only one sched_engine is used for all of GuC submission but that could change in the future.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKdhjhhubh)}(hnguc->submission_state.lock Global lock for GuC submission state. Protects guc_ids and destroyed contexts list.h]hnguc->submission_state.lock Global lock for GuC submission state. Protects guc_ids and destroyed contexts list.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKjhjhhubh)}(hXce->guc_state.lock Protects everything under ce->guc_state. Ensures that a context is in the correct state before issuing a H2G. e.g. We don't issue a schedule disable on a disabled context (bad idea), we don't issue a schedule enable when a schedule disable is in flight, etc... Also protects list of inflight requests on the context and the priority management state. Lock is individual to each context.h]hXce->guc_state.lock Protects everything under ce->guc_state. Ensures that a context is in the correct state before issuing a H2G. e.g. We don’t issue a schedule disable on a disabled context (bad idea), we don’t issue a schedule enable when a schedule disable is in flight, etc... Also protects list of inflight requests on the context and the priority management state. Lock is individual to each context.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKnhjhhubh)}(hnLock ordering rules: sched_engine->lock -> ce->guc_state.lock guc->submission_state.lock -> ce->guc_state.lockh]hnLock ordering rules: sched_engine->lock -> ce->guc_state.lock guc->submission_state.lock -> ce->guc_state.lock}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKvhjhhubh)}(hXReset races: When a full GT reset is triggered it is assumed that some G2H responses to H2Gs can be lost as the GuC is also reset. Losing these G2H can prove to be fatal as we do certain operations upon receiving a G2H (e.g. destroy contexts, release guc_ids, etc...). When this occurs we can scrub the context state and cleanup appropriately, however this is quite racey. To avoid races, the reset code must disable submission before scrubbing for the missing G2H, while the submission code must check for submission being disabled and skip sending H2Gs and updating context states when it is. Both sides must also make sure to hold the relevant locks.h]hXReset races: When a full GT reset is triggered it is assumed that some G2H responses to H2Gs can be lost as the GuC is also reset. Losing these G2H can prove to be fatal as we do certain operations upon receiving a G2H (e.g. destroy contexts, release guc_ids, etc...). When this occurs we can scrub the context state and cleanup appropriately, however this is quite racey. To avoid races, the reset code must disable submission before scrubbing for the missing G2H, while the submission code must check for submission being disabled and skip sending H2Gs and updating context states when it is. Both sides must also make sure to hold the relevant locks.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:352: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKzhjhhubeh}(h]guc-based-command-submissionah ]h"]guc-based command submissionah$]h&]uh1hhj?hhhhhM^ubh)}(hhh](h)}(hGuC ABIh]hGuC ABI}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhhhhhMdubh)}(h.. _HXG Message:h]h}(h]h ]h"]h$]h&]h hxg-messageuh1hhKhjjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hjdKubh)}(h**HXG Message**h]j)}(hjh]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"] hxg messageah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhexpect_referenced_by_name}jj{sexpect_referenced_by_id}jj{sjdKubh)}(hAll messages exchanged with GuC are defined using 32 bit dwords. First dword is treated as a message header. Remaining dwords are optional.h]hAll messages exchanged with GuC are defined using 32 bit dwords. First dword is treated as a message header. Remaining dwords are optional.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK hjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | | | | | 0 | 31 | **ORIGIN** - originator of the message | | | | - _`GUC_HXG_ORIGIN_HOST` = 0 | | | | - _`GUC_HXG_ORIGIN_GUC` = 1 | | | | | | +-------+--------------------------------------------------------------+ | | 30:28 | **TYPE** - message type | | | | - _`GUC_HXG_TYPE_REQUEST` = 0 | | | | - _`GUC_HXG_TYPE_EVENT` = 1 | | | | - _`GUC_HXG_TYPE_FAST_REQUEST` = 2 | | | | - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3 | | | | - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5 | | | | - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6 | | | | - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7 | | +-------+--------------------------------------------------------------+ | | 27:0 | **AUX** - auxiliary data (depends on TYPE) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **PAYLOAD** - optional payload (depends on TYPE) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubhtbody)}(hhh](j)}(hhh](j)}(hhh]h)}(h0h]h0}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj9ubah}(h]h ]h"]h$]h&]morerowsKuh1jhj6ubj)}(hhh]h)}(h31h]h31}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhKhjRubah}(h]h ]h"]h$]h&]uh1jhj6ubj)}(hhh]j)}(hhh]j)}(h`**ORIGIN** - originator of the message - _`GUC_HXG_ORIGIN_HOST` = 0 - _`GUC_HXG_ORIGIN_GUC` = 1 h](j$)}(h&**ORIGIN** - originator of the messageh](j)}(h **ORIGIN**h]hORIGIN}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubh - originator of the message}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjoubj@)}(hhh]j:)}(hhh](j:)}(h_`GUC_HXG_ORIGIN_HOST` = 0h]h)}(hjh](h)}(h_`GUC_HXG_ORIGIN_HOST`h]hGUC_HXG_ORIGIN_HOST}(hjhhhNhNubah}(h]guc-hxg-origin-hostah ]h"]guc_hxg_origin_hostah$]h&]uh1hhjjdKubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h_`GUC_HXG_ORIGIN_GUC` = 1 h]h)}(h_`GUC_HXG_ORIGIN_GUC` = 1h](h)}(h_`GUC_HXG_ORIGIN_GUC`h]hGUC_HXG_ORIGIN_GUC}(hjhhhNhNubah}(h]guc-hxg-origin-gucah ]h"]guc_hxg_origin_gucah$]h&]uh1hhjjdKubh = 1}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j;j;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjoubeh}(h]h ]h"]h$]h&]uh1jhjhKhjlubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]j)}(hhh]j)}(hX**TYPE** - message type - _`GUC_HXG_TYPE_REQUEST` = 0 - _`GUC_HXG_TYPE_EVENT` = 1 - _`GUC_HXG_TYPE_FAST_REQUEST` = 2 - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3 - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5 - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6 - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7h](j$)}(h**TYPE** - message typeh](j)}(h**TYPE**h]hTYPE}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubh - message type}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj+ubj@)}(hhh]j:)}(hhh](j:)}(h_`GUC_HXG_TYPE_REQUEST` = 0h]h)}(hjTh](h)}(h_`GUC_HXG_TYPE_REQUEST`h]hGUC_HXG_TYPE_REQUEST}(hjYhhhNhNubah}(h]guc-hxg-type-requestah ]h"]guc_hxg_type_requestah$]h&]uh1hhjVjdKubh = 0}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjRubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h_`GUC_HXG_TYPE_EVENT` = 1h]h)}(hj|h](h)}(h_`GUC_HXG_TYPE_EVENT`h]hGUC_HXG_TYPE_EVENT}(hjhhhNhNubah}(h]guc-hxg-type-eventah ]h"]guc_hxg_type_eventah$]h&]uh1hhj~jdKubh = 1}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjzubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h _`GUC_HXG_TYPE_FAST_REQUEST` = 2h]h)}(hjh](h)}(h_`GUC_HXG_TYPE_FAST_REQUEST`h]hGUC_HXG_TYPE_FAST_REQUEST}(hjhhhNhNubah}(h]guc-hxg-type-fast-requestah ]h"]guc_hxg_type_fast_requestah$]h&]uh1hhjjdKubh = 2}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h$_`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3h]h)}(hjh](h)}(h _`GUC_HXG_TYPE_NO_RESPONSE_BUSY`h]hGUC_HXG_TYPE_NO_RESPONSE_BUSY}(hjhhhNhNubah}(h]guc-hxg-type-no-response-busyah ]h"]guc_hxg_type_no_response_busyah$]h&]uh1hhjjdKubh = 3}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h%_`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5h]h)}(hjh](h)}(h!_`GUC_HXG_TYPE_NO_RESPONSE_RETRY`h]hGUC_HXG_TYPE_NO_RESPONSE_RETRY}(hjhhhNhNubah}(h]guc-hxg-type-no-response-retryah ]h"]guc_hxg_type_no_response_retryah$]h&]uh1hhjjdKubh = 5}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h$_`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6h]h)}(hjh](h)}(h _`GUC_HXG_TYPE_RESPONSE_FAILURE`h]hGUC_HXG_TYPE_RESPONSE_FAILURE}(hj!hhhNhNubah}(h]guc-hxg-type-response-failureah ]h"]guc_hxg_type_response_failureah$]h&]uh1hhjjdKubh = 6}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjKhKhjubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h$_`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7h]h)}(hjCh](h)}(h _`GUC_HXG_TYPE_RESPONSE_SUCCESS`h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjHhhhNhNubah}(h]guc-hxg-type-response-successah ]h"]guc_hxg_type_response_successah$]h&]uh1hhjEjdKubh = 7}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjAubah}(h]h ]h"]h$]h&]uh1j:hjOubeh}(h]h ]h"]h$]h&]j;j;uh1j:hjshKhjLubah}(h]h ]h"]h$]h&]uh1j?hj+ubeh}(h]h ]h"]h$]h&]uh1jhjKhKhj(ubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h***AUX** - auxiliary data (depends on TYPE)h](j)}(h**AUX**h]hAUX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh# - auxiliary data (depends on TYPE)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh](j)}(hhh]h)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h0**PAYLOAD** - optional payload (depends on TYPE)h](j)}(h **PAYLOAD**h]hPAYLOAD}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh% - optional payload (depends on TYPE)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK#hjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hK#hj5ubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh](j)}(hhh]h)}(hjh]hn}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK%hj^ubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(h31:0h]h31:0}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhK%hjuubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jfdhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK hjjhhubh)}(h.. _HXG Request:h]h}(h]h ]h"]h$]h&]h hxg-requestuh1hhK$hjjhhhjjdKubh)}(h**HXG Request**h]j)}(hjh]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"] hxg requestah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK+hjjhhj}jjsj}jjsjdKubh)}(h}The `HXG Request`_ message should be used to initiate synchronous activity for which confirmation or return data is expected.h](hThe }(hjhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjj7;Kubhk message should be used to initiate synchronous activity for which confirmation or return data is expected.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK;hjjhhubh)}(hThe recipient of this message shall use `HXG Response`_, `HXG Failure`_ or `HXG Retry`_ message as a definite reply, and may use `HXG Busy`_ message as a intermediate reply.h](h(The recipient of this message shall use }(hjhhhNhNubj5)}(h`HXG Response`_h]h HXG Response}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Responseh hxg-responseuh1j5hjj7;Kubh, }(hjhhhNhNubj5)}(h`HXG Failure`_h]h HXG Failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Failureh hxg-failureuh1j5hjj7;Kubh or }(hjhhhNhNubj5)}(h `HXG Retry`_h]h HXG Retry}(hj'hhhNhNubah}(h]h ]h"]h$]h&]name HXG Retryh hxg-retryuh1j5hjj7;Kubh* message as a definite reply, and may use }(hjhhhNhNubj5)}(h `HXG Busy`_h]hHXG Busy}(hj<hhhNhNubah}(h]h ]h"]h$]h&]nameHXG Busyhhxg-busyuh1j5hjj7;Kubh! message as a intermediate reply.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK>hjjhhubh)}(hLFormat of **DATA0** and all **DATAn** fields depends on the **ACTION** code.h](h Format of }(hjXhhhNhNubj)}(h **DATA0**h]hDATA0}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh and all }(hjXhhhNhNubj)}(h **DATAn**h]hDATAn}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh fields depends on the }(hjXhhhNhNubj)}(h **ACTION**h]hACTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh code.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKBhjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **DATA0** - request data (depends on ACTION) | | +-------+--------------------------------------------------------------+ | | 15:0 | **ACTION** - requested action code | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - optional data (depends on ACTION) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKEhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKEhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKGhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hKGhj-ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hKGhjDubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKIhjdubah}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hjhhhNhNubj5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESThjcuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjuhKIhj|ubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h,**DATA0** - request data (depends on ACTION)h](j)}(h **DATA0**h]hDATA0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh# - request data (depends on ACTION)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h"**ACTION** - requested action codeh](j)}(h **ACTION**h]hACTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh - requested action code}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKOhj8ubah}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh]h)}(h31:0h]h31:0}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhKOhjOubah}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh]h)}(h-**DATAn** - optional data (depends on ACTION)h](j)}(h **DATAn**h]hDATAn}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubh$ - optional data (depends on ACTION)}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKQhjfubah}(h]h ]h"]h$]h&]morerowsKuh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKShjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKShjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jfdhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKDhjjhhubh)}(h.. _HXG Fast Request:h]h}(h]h ]h"]h$]h&]hhxg-fast-requestuh1hhKDhjjhhhjjdKubh)}(h**HXG Fast Request**h]j)}(hjh]hHXG Fast Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"]hxg fast requestah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKYhjjhhj}j-j sj}jj sjdKubh)}(hThe `HXG Request`_ message should be used to initiate asynchronous activity for which confirmation or return data is not expected.h](hThe }(hj3hhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hj;hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hj3j7;Kubhp message should be used to initiate asynchronous activity for which confirmation or return data is not expected.}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK_hjjhhubh)}(hFIf confirmation is required then `HXG Request`_ shall be used instead.h](h!If confirmation is required then }(hjVhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hj^hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjVj7;Kubh shall be used instead.}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKbhjjhhubh)}(h~The recipient of this message may only use `HXG Failure`_ message if it was unable to accept this request (like invalid data).h](h+The recipient of this message may only use }(hjyhhhNhNubj5)}(h`HXG Failure`_h]h HXG Failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Failurehj"uh1j5hjyj7;KubhE message if it was unable to accept this request (like invalid data).}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKdhjjhhubh)}(hPFormat of `HXG Fast Request`_ message is same as `HXG Request`_ except **TYPE**.h](h Format of }(hjhhhNhNubj5)}(h`HXG Fast Request`_h]hHXG Fast Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameHXG Fast Requesthjuh1j5hjj7;Kubh message is same as }(hjhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjj7;Kubh except }(hjhhhNhNubj)}(h**TYPE**h]hTYPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKghjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN - see `HXG Message`_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = `GUC_HXG_TYPE_FAST_REQUEST`_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 - see `HXG Request`_ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION - see `HXG Request`_ | +---+-------+--------------------------------------------------------------+ |...| | DATAn - see `HXG Request`_ | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKjhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hKjhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKlhj]ubah}(h]h ]h"]h$]h&]morerowsKuh1jhjZubj)}(hhh]h)}(h31h]h31}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhKlhjuubah}(h]h ]h"]h$]h&]uh1jhjZubj)}(hhh]h)}(hORIGIN - see `HXG Message`_h](h ORIGIN - see }(hjhhhNhNubj5)}(h`HXG Message`_h]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagehjuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjmhKlhjubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjWubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKnhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h#TYPE = `GUC_HXG_TYPE_FAST_REQUEST`_h](hTYPE = }(hjhhhNhNubj5)}(h`GUC_HXG_TYPE_FAST_REQUEST`_h]hGUC_HXG_TYPE_FAST_REQUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_FAST_REQUESThjuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjhKnhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjWubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKphjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hDATA0 - see `HXG Request`_h](h DATA0 - see }(hjhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hj'hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjhKphjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjWubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKrhjLubah}(h]h ]h"]h$]h&]uh1jhjIubj)}(hhh]h)}(hACTION - see `HXG Request`_h](h ACTION - see }(hjghhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hjohhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjgj7;Kubeh}(h]h ]h"]h$]h&]uh1hhj]hKrhjdubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhjWubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKthjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hDATAn - see `HXG Request`_h](h DATAn - see }(hjhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjhKthjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jfdhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKihjjhhubh)}(h.. _HXG Event:h]h}(h]h ]h"]h$]h&]h hxg-eventuh1hhKahjjhhhjjdKubh)}(h **HXG Event**h]j)}(hj h]h HXG Event}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"] hxg eventah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKzhjjhhj}jjsj}jjsjdKubh)}(hThe `HXG Event`_ message should be used to initiate asynchronous activity that does not involves immediate confirmation nor data.h](hThe }(hj"hhhNhNubj5)}(h `HXG Event`_h]h HXG Event}(hj*hhhNhNubah}(h]h ]h"]h$]h&]name HXG Eventhjuh1j5hj"j7;Kubhq message should be used to initiate asynchronous activity that does not involves immediate confirmation nor data.}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK{hjjhhubh)}(hLFormat of **DATA0** and all **DATAn** fields depends on the **ACTION** code.h](h Format of }(hjEhhhNhNubj)}(h **DATA0**h]hDATA0}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubh and all }(hjEhhhNhNubj)}(h **DATAn**h]hDATAn}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubh fields depends on the }(hjEhhhNhNubj)}(h **ACTION**h]hACTION}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubh code.}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK~hjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_EVENT_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **DATA0** - event data (depends on ACTION) | | +-------+--------------------------------------------------------------+ | | 15:0 | **ACTION** - event action code | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - optional event data (depends on ACTION) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjQubah}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_EVENT_h](hTYPE = }(hjlhhhNhNubj5)}(hGUC_HXG_TYPE_EVENT_h]hGUC_HXG_TYPE_EVENT}(hjthhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_EVENThjuh1j5hjlj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjbhKhjiubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h***DATA0** - event data (depends on ACTION)h](j)}(h **DATA0**h]hDATA0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh! - event data (depends on ACTION)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h**ACTION** - event action codeh](j)}(h **ACTION**h]hACTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - event action code}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj%ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh]h)}(h31:0h]h31:0}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hKhj<ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh]h)}(h4**DATAn** - optional event data (depends on ACTION)h](j)}(h **DATAn**h]hDATAn}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh+ - optional event data (depends on ACTION)}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjSubah}(h]h ]h"]h$]h&]morerowsKuh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jfdhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubh)}(h .. _HXG Busy:h]h}(h]h ]h"]h$]h&]hjLuh1hhK}hjjhhhjjdKubh)}(h **HXG Busy**h]j)}(hjh]hHXG Busy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jLah ]h"]hxg busyah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhj}jjsj}jLjsjdKubh)}(hThe `HXG Busy`_ message may be used to acknowledge reception of the `HXG Request`_ message if the recipient expects that it processing will be longer than default timeout.h](hThe }(hjhhhNhNubj5)}(h `HXG Busy`_h]hHXG Busy}(hj'hhhNhNubah}(h]h ]h"]h$]h&]nameHXG BusyhjLuh1j5hjj7;Kubh5 message may be used to acknowledge reception of the }(hjhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hj;hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjj7;KubhY message if the recipient expects that it processing will be longer than default timeout.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubh)}(h:The **COUNTER** field may be used as a progress indicator.h](hThe }(hjVhhhNhNubj)}(h **COUNTER**h]hCOUNTER}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh+ field may be used as a progress indicator.}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_NO_RESPONSE_BUSY_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **COUNTER** - progress indicator | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj~ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj~ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj~ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj~ubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj>ubah}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_NO_RESPONSE_BUSY_h](hTYPE = }(hjYhhhNhNubj5)}(hGUC_HXG_TYPE_NO_RESPONSE_BUSY_h]hGUC_HXG_TYPE_NO_RESPONSE_BUSY}(hjahhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_NO_RESPONSE_BUSYhjuh1j5hjYj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjOhKhjVubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h **COUNTER** - progress indicatorh](j)}(h **COUNTER**h]hCOUNTER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - progress indicator}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hj~ubeh}(h]h ]h"]h$]h&]colsKuh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jfdhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubh)}(h.. _HXG Retry:h]h}(h]h ]h"]h$]h&]hj7uh1hhKhjjhhhjjdKubh)}(h **HXG Retry**h]j)}(hjh]h HXG Retry}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]j7ah ]h"] hxg retryah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhj}jjsj}j7jsjdKubh)}(hThe `HXG Retry`_ message should be used by recipient to indicate that the `HXG Request`_ message was dropped and it should be resent again.h](hThe }(hjhhhNhNubj5)}(h `HXG Retry`_h]h HXG Retry}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Retryhj7uh1j5hjj7;Kubh: message should be used by recipient to indicate that the }(hjhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hj$hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjj7;Kubh3 message was dropped and it should be resent again.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubh)}(hCThe **REASON** field may be used to provide additional information.h](hThe }(hj?hhhNhNubj)}(h **REASON**h]hREASON}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh5 field may be used to provide additional information.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_NO_RESPONSE_RETRY_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **REASON** - reason for retry | | | | - _`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0 | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjgubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjgubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjgubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjgubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj'ubah}(h]h ]h"]h$]h&]uh1jhj$ubj)}(hhh]h)}(h&TYPE = GUC_HXG_TYPE_NO_RESPONSE_RETRY_h](hTYPE = }(hjBhhhNhNubj5)}(hGUC_HXG_TYPE_NO_RESPONSE_RETRY_h]hGUC_HXG_TYPE_NO_RESPONSE_RETRY}(hjJhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_NO_RESPONSE_RETRYhjuh1j5hjBj7;Kubeh}(h]h ]h"]h$]h&]uh1hhj8hKhj?ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjoubah}(h]h ]h"]h$]h&]uh1jhjlubj)}(hhh]j)}(hhh]j)}(hG**REASON** - reason for retry - _`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0h](j$)}(h**REASON** - reason for retryh](j)}(h **REASON**h]hREASON}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - reason for retry}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hjhKhjubj@)}(hhh]j:)}(hhh]j:)}(h'_`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0h]h)}(hjh](h)}(h#_`GUC_HXG_RETRY_REASON_UNSPECIFIED`h]h GUC_HXG_RETRY_REASON_UNSPECIFIED}(hjhhhNhNubah}(h] guc-hxg-retry-reason-unspecifiedah ]h"] guc_hxg_retry_reason_unspecifiedah$]h&]uh1hhjubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&]j;j;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hjgubeh}(h]h ]h"]h$]h&]colsKuh1jhjdubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jfdhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubh)}(h.. _HXG Failure:h]h}(h]h ]h"]h$]h&]hj"uh1hhKhjjhhhjjdKubh)}(h**HXG Failure**h]j)}(hj%h]h HXG Failure}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]j"ah ]h"] hxg failureah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhj}j8jsj}j"jsjdKubh)}(h~The `HXG Failure`_ message shall be used as a reply to the `HXG Request`_ message that could not be processed due to an error.h](hThe }(hj>hhhNhNubj5)}(h`HXG Failure`_h]h HXG Failure}(hjFhhhNhNubah}(h]h ]h"]h$]h&]name HXG Failurehj"uh1j5hj>j7;Kubh) message shall be used as a reply to the }(hj>hhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hjZhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hj>j7;Kubh5 message that could not be processed due to an error.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubjgd)}(hXP+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_FAILURE_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **HINT** - additional error hint | | +-------+--------------------------------------------------------------+ | | 15:0 | **ERROR** - error/result code | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj|ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj|ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj|ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj|ubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj<ubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_FAILURE_h](hTYPE = }(hjWhhhNhNubj5)}(hGUC_HXG_TYPE_RESPONSE_FAILURE_h]hGUC_HXG_TYPE_RESPONSE_FAILURE}(hj_hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_FAILUREhj+uh1j5hjWj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjMhKhjTubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h **HINT** - additional error hinth](j)}(h**HINT**h]hHINT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - additional error hint}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h**ERROR** - error/result codeh](j)}(h **ERROR**h]hERROR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - error/result code}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hj|ubeh}(h]h ]h"]h$]h&]colsKuh1jhjyubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jfdhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubh)}(h.. _HXG Response:h]h}(h]h ]h"]h$]h&]hj uh1hhKhjjhhhjjdKubh)}(h**HXG Response**h]j)}(hj3h]h HXG Response}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]j ah ]h"] hxg responseah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhj}jFj'sj}j j'sjdKubh)}(hThe `HXG Response`_ message shall be used as a reply to the `HXG Request`_ message that was successfully processed without an error.h](hThe }(hjLhhhNhNubj5)}(h`HXG Response`_h]h HXG Response}(hjThhhNhNubah}(h]h ]h"]h$]h&]name HXG Responsehj uh1j5hjLj7;Kubh) message shall be used as a reply to the }(hjLhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hjhhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjLj7;Kubh: message that was successfully processed without an error.}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **DATA0** - data (depends on ACTION from `HXG Request`_) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - data (depends on ACTION from `HXG Request`_) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjJubah}(h]h ]h"]h$]h&]uh1jhjGubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hjehhhNhNubj5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjmhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESShjRuh1j5hjej7;Kubeh}(h]h ]h"]h$]h&]uh1hhj[hKhjbubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h8**DATA0** - data (depends on ACTION from `HXG Request`_)h](j)}(h **DATA0**h]hDATA0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - data (depends on ACTION from }(hjhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjj7;Kubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h8**DATAn** - data (depends on ACTION from `HXG Request`_)h](j)}(h **DATAn**h]hDATAn}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - data (depends on ACTION from }(hjhhhNhNubj5)}(h`HXG Request`_h]h HXG Request}(hj3hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requesthjuh1j5hjj7;Kubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhKhj^ubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jfdhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjjhhubh)}(h!.. _GuC MMIO based communication:h]h}(h]h ]h"]h$]h&]hguc-mmio-based-communicationuh1hhKhjjhhhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hubh)}(h **GuC MMIO based communication**h]j)}(hjh]hGuC MMIO based communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"]guc mmio based communicationah$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjjhhj}jjsj}jjsubh)}(hThe MMIO based communication between Host and GuC relies on special hardware registers which format could be defined by the software (so called scratch registers).h]hThe MMIO based communication between Host and GuC relies on special hardware registers which format could be defined by the software (so called scratch registers).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK hjjhhubh)}(hEach MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) messages, which maximum length depends on number of available scratch registers, is directly written into those scratch registers.h]hEach MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) messages, which maximum length depends on number of available scratch registers, is directly written into those scratch registers.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjjhhubh)}(hFor Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, but no H2G command takes more than 4 parameters and the GuC firmware itself uses an 4-element array to store the H2G message.h]hFor Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, but no H2G command takes more than 4 parameters and the GuC firmware itself uses an 4-element array to store the H2G message.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjjhhubh)}(hFor Gen11+, there are additional 4 registers 0x190240-0x19024C, which are, regardless on lower count, preferred over legacy ones.h]hFor Gen11+, there are additional 4 registers 0x190240-0x19024C, which are, regardless on lower count, preferred over legacy ones.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjjhhubh)}(hThe MMIO based communication is mainly used during driver initialization phase to setup the `CTB based communication`_ that will be used afterwards.h](h\The MMIO based communication is mainly used during driver initialization phase to setup the }(hj8hhhNhNubj5)}(h`CTB based communication`_h]hCTB based communication}(hj@hhhNhNubah}(h]h ]h"]h$]h&]nameCTB based communicationhctb-based-communicationuh1j5hj8j7;Kubh that will be used afterwards.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjjhhubh)}(h.. _MMIO HXG Message:h]h}(h]h ]h"]h$]h&]hmmio-hxg-messageuh1hhKhjjhhhjjdKubh)}(h**MMIO HXG Message**h]j)}(hjih]hMMIO HXG Message}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]jfah ]h"]mmio hxg messageah$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjjhhj}j|j\sj}jfj\sjdKubh)}(hBFormat of the MMIO messages follows definitions of `HXG Message`_.h](h3Format of the MMIO messages follows definitions of }(hjhhhNhNubj5)}(h`HXG Message`_h]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagehjuh1j5hjj7;Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK"hjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:0 | | +---+-------+ | |...| | [Embedded `HXG Message`_] | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK%hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hK'hj4ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[Embedded `HXG Message`_]h](h [Embedded }(hjNhhhNhNubj5)}(h`HXG Message`_h]h HXG Message}(hjVhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagehjuh1j5hjNj7;Kubh]}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK)hjKubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphK)hjubah}(h]h ]h"]h$]h&]uh1jhj~ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK+hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK+hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jfdhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK$hjjhhubh)}(h.. _CT Buffer:h]h}(h]h ]h"]h$]h&]h ct-bufferuh1hhKhjjhhhNjdKubh)}(h **CT Buffer**h]j)}(hjh]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"] ct bufferah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjjhhj}jjsj}jjsjdKubh)}(h+Circular buffer used to send `CTB Message`_h](hCircular buffer used to send }(hjhhhNhNubj5)}(h`CTB Message`_h]h CTB Message}(hj&hhhNhNubah}(h]h ]h"]h$]h&]name CTB Messageh ctb-messageuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjjhhubh)}(h.. _CTB Descriptor:h]h}(h]h ]h"]h$]h&]hctb-descriptoruh1hhKhjjhhhNjdKubh)}(h**CTB Descriptor**h]j)}(hjKh]hCTB Descriptor}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]jHah ]h"]ctb descriptorah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjjhhj}j^j>sj}jHj>sjdKubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:0 | **HEAD** - offset (in dwords) to the last dword that was | | | | read from the `CT Buffer`_. | | | | It can only be updated by the receiver. | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **TAIL** - offset (in dwords) to the last dword that was | | | | written to the `CT Buffer`_. | | | | It can only be updated by the sender. | +---+-------+--------------------------------------------------------------+ | 2 | 31:0 | **STATUS** - status of the CTB | | | | | | | | - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation) | | | | - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large) | | | | - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message) | | | | - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified) | | | | - _`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use) | +---+-------+--------------------------------------------------------------+ |...| | RESERVED = MBZ | +---+-------+--------------------------------------------------------------+ | 15| 31:0 | RESERVED = MBZ | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjkubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjkubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjkubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjkubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h|**HEAD** - offset (in dwords) to the last dword that was read from the `CT Buffer`_. It can only be updated by the receiver.h](j)}(h**HEAD**h]hHEAD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh? - offset (in dwords) to the last dword that was read from the }(hj hhhNhNubj5)}(h `CT Buffer`_h]h CT Buffer}(hj#hhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferhjuh1j5hj j7;Kubh). It can only be updated by the receiver.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjLubah}(h]h ]h"]h$]h&]uh1jhjIubj)}(hhh]h)}(h31:0h]h31:0}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hKhjcubah}(h]h ]h"]h$]h&]uh1jhjIubj)}(hhh]h)}(h{**TAIL** - offset (in dwords) to the last dword that was written to the `CT Buffer`_. It can only be updated by the sender.h](j)}(h**TAIL**h]hTAIL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubh@ - offset (in dwords) to the last dword that was written to the }(hj}hhhNhNubj5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferhjuh1j5hj}j7;Kubh'. It can only be updated by the sender.}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj\hKhjzubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h2h]h2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h**STATUS** - status of the CTBh](j)}(h **STATUS**h]hSTATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - status of the CTB}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK hjubjgd)}(hX - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation) - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large) - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message) - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified) - _`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use)h]j:)}(hhh](j:)}(h1_`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation)h]h)}(hj h](h)}(h_`GUC_CTB_STATUS_NO_ERROR`h]hGUC_CTB_STATUS_NO_ERROR}(hj hhhNhNubah}(h]guc-ctb-status-no-errorah ]h"]guc_ctb_status_no_errorah$]h&]uh1hhj ubh = 0 (normal operation)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK"hj ubah}(h]h ]h"]h$]h&]uh1j:hj ubj:)}(h4_`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large)h]h)}(hj; h](h)}(h_`GUC_CTB_STATUS_OVERFLOW`h]hGUC_CTB_STATUS_OVERFLOW}(hj@ hhhNhNubah}(h]guc-ctb-status-overflowah ]h"]guc_ctb_status_overflowah$]h&]uh1hhj= ubh = 1 (head/tail too large)}(hj= hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK#hj9 ubah}(h]h ]h"]h$]h&]uh1j:hj ubj:)}(h3_`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)h]h)}(hjc h](h)}(h_`GUC_CTB_STATUS_UNDERFLOW`h]hGUC_CTB_STATUS_UNDERFLOW}(hjh hhhNhNubah}(h]guc-ctb-status-underflowah ]h"]guc_ctb_status_underflowah$]h&]uh1hhje ubh = 2 (truncated message)}(hje hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK$hja ubah}(h]h ]h"]h$]h&]uh1j:hj ubj:)}(h3_`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)h]h)}(hj h](h)}(h_`GUC_CTB_STATUS_MISMATCH`h]hGUC_CTB_STATUS_MISMATCH}(hj hhhNhNubah}(h]guc-ctb-status-mismatchah ]h"]guc_ctb_status_mismatchah$]h&]uh1hhj ubh = 4 (head/tail modified)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK%hj ubah}(h]h ]h"]h$]h&]uh1j:hj ubj:)}(h0_`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use)h]h)}(hj h](h)}(h_`GUC_CTB_STATUS_UNUSED`h]hGUC_CTB_STATUS_UNUSED}(hj hhhNhNubah}(h]guc-ctb-status-unusedah ]h"]guc_ctb_status_unusedah$]h&]uh1hhj ubh = 8 (CTB is not in use)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK&hj ubah}(h]h ]h"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]j;j;uh1j:hj2 hK"hj ubah}(h]h ]h"]h$]h&]uh1jfdhj2 hK"hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK(hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK(hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15h]h15}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK*hj5 ubah}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh]h)}(h31:0h]h31:0}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF hK*hjM ubah}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF hK*hjd ubah}(h]h ]h"]h$]h&]uh1jhj2 ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hjkubeh}(h]h ]h"]h$]h&]colsKuh1jhjhubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jfdht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjjhhubh)}(h.. _CTB Message:h]h}(h]h ]h"]h$]h&]hj6uh1hhK%hjjhhhNjdKubh)}(h**CTB Message**h]j)}(hj h]h CTB Message}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]j6ah ]h"] ctb messageah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK0hjjhhj}j j sj}j6j sjdKubjgd)}(hXk+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | **FENCE** - message identifier | | +-------+--------------------------------------------------------------+ | | 15:12 | **FORMAT** - format of the CTB message | | | | - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_ | | +-------+--------------------------------------------------------------+ | | 11:8 | **RESERVED** | | +-------+--------------------------------------------------------------+ | | 7:0 | **NUM_DWORDS** - length of the CTB message (w/o header) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | optional (depends on FORMAT) | +---+-------+ | |...| | | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hBitsh]hBits}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK?hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Descriptionh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK?hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKAhj8 ubah}(h]h ]h"]h$]h&]morerowsKuh1jhj5 ubj)}(hhh]h)}(h31:16h]h31:16}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjH hKAhjP ubah}(h]h ]h"]h$]h&]uh1jhj5 ubj)}(hhh]h)}(h**FENCE** - message identifierh](j)}(h **FENCE**h]hFENCE}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj ubh - message identifier}(hjj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjH hKAhjg ubah}(h]h ]h"]h$]h&]uh1jhj5 ubeh}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh](j)}(hhh]h)}(h15:12h]h15:12}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKChj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]j)}(hhh]j)}(h[**FORMAT** - format of the CTB message - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_h](j$)}(h&**FORMAT** - format of the CTB messageh](j)}(h **FORMAT**h]hFORMAT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh - format of the CTB message}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hj hKChj ubj@)}(hhh]j:)}(hhh]j:)}(h2_`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_h]h)}(hj h](h)}(h_`GUC_CTB_FORMAT_HXG`h]hGUC_CTB_FORMAT_HXG}(hj hhhNhNubah}(h]guc-ctb-format-hxgah ]h"]guc_ctb_format_hxgah$]h&]uh1hhj jdKubh = 0 - see }(hj hhhNhNubj5)}(h`CTB HXG Message`_h]hCTB HXG Message}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameCTB HXG Messagehctb-hxg-messageuh1j5hj j7;Kubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKDhj ubah}(h]h ]h"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&]j;j;uh1j:hj hKDhj ubah}(h]h ]h"]h$]h&]uh1j?hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKChj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh](j)}(hhh]h)}(h11:8h]h11:8}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKFhj9 ubah}(h]h ]h"]h$]h&]uh1jhj6 ubj)}(hhh]h)}(h **RESERVED**h]j)}(hjV h]hRESERVED}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT ubah}(h]h ]h"]h$]h&]uh1hhjJ hKFhjQ ubah}(h]h ]h"]h$]h&]uh1jhj6 ubeh}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh](j)}(hhh]h)}(h7:0h]h7:0}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKHhjz ubah}(h]h ]h"]h$]h&]uh1jhjw ubj)}(hhh]h)}(h7**NUM_DWORDS** - length of the CTB message (w/o header)h](j)}(h**NUM_DWORDS**h]h NUM_DWORDS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh) - length of the CTB message (w/o header)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj hKHhj ubah}(h]h ]h"]h$]h&]uh1jhjw ubeh}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKJhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h31:0h]h31:0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKJhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hoptional (depends on FORMAT)h]hoptional (depends on FORMAT)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKJhj ubah}(h]h ]h"]h$]h&]morerowsKuh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKLhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh](j)}(hhh]h)}(hjh]hn}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKNhj9 ubah}(h]h ]h"]h$]h&]uh1jhj6 ubj)}(hhh]h)}(h31:0h]h31:0}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI hKNhjP ubah}(h]h ]h"]h$]h&]uh1jhj6 ubeh}(h]h ]h"]h$]h&]uh1jhj2 ubeh}(h]h ]h"]h$]h&]uh1j1hj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jfdht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK>hjjhhubh)}(h.. _CTB HXG Message:h]h}(h]h ]h"]h$]h&]hj uh1hhK=hjjhhhNjdKubh)}(h**CTB HXG Message**h]j)}(hj h]hCTB HXG Message}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]j ah ]h"]ctb hxg messageah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKThjjhhj}j j sj}j j sjdKubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | FENCE | | +-------+--------------------------------------------------------------+ | | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_ | | +-------+--------------------------------------------------------------+ | | 11:8 | RESERVED = MBZ | | +-------+--------------------------------------------------------------+ | | 7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | [Embedded `HXG Message`_] | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hBitsh]hBits}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK_hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Descriptionh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK_hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKahj$ubah}(h]h ]h"]h$]h&]morerowsKuh1jhj!ubj)}(hhh]h)}(h31:16h]h31:16}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hKahj<ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(hFENCEh]hFENCE}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hKahjSubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:12h]h15:12}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKchjsubah}(h]h ]h"]h$]h&]uh1jhjpubj)}(hhh]h)}(hFORMAT = GUC_CTB_FORMAT_HXG_h](h FORMAT = }(hjhhhNhNubj5)}(hGUC_CTB_FORMAT_HXG_h]hGUC_CTB_FORMAT_HXG}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_CTB_FORMAT_HXGhj uh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjhKchjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h11:8h]h11:8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKehjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKehjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h7:0h]h7:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKghjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h;NUM_DWORDS = length (in dwords) of the embedded HXG messageh]h;NUM_DWORDS = length (in dwords) of the embedded HXG message}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKghj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKihj+ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]h)}(h31:0h]h31:0}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hKihjBubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]h)}(h[Embedded `HXG Message`_]h](h [Embedded }(hj\hhhNhNubj5)}(h`HXG Message`_h]h HXG Message}(hjdhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagehjuh1j5hj\j7;Kubh]}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKkhjYubah}(h]h ]h"]h$]h&]morerowsKuh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKkhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKmhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKmhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jfdht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK^hjjhhubh)}(h.. _CTB based communication:h]h}(h]h ]h"]h$]h&]hjPuh1hhKThjjhhhNjdKubh)}(h**CTB based communication**h]j)}(hjh]hCTB based communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jPah ]h"]ctb based communicationah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKshjjhhj}j%jsj}jPjsjdKubh)}(hThe CTB (command transport buffer) communication between Host and GuC is based on u32 data stream written to the shared buffer. One buffer can be used to transmit data only in one direction (one-directional channel).h]hThe CTB (command transport buffer) communication between Host and GuC is based on u32 data stream written to the shared buffer. One buffer can be used to transmit data only in one direction (one-directional channel).}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKwhjjhhubh)}(hX Current status of the each buffer is stored in the buffer descriptor. Buffer descriptor holds tail and head fields that represents active data stream. The tail field is updated by the data producer (sender), and head field is updated by the data consumer (receiver)::h]hX Current status of the each buffer is stored in the buffer descriptor. Buffer descriptor holds tail and head fields that represents active data stream. The tail field is updated by the data producer (sender), and head field is updated by the data consumer (receiver):}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK{hjjhhubjA#)}(hX+------------+ | DESCRIPTOR | +=================+============+========+ +============+ | | MESSAGE(s) | | | address |--------->+=================+============+========+ +------------+ | head | ^-----head--------^ +------------+ | tail | ^---------tail-----------------^ +------------+ | size | ^---------------size--------------------^ +------------+h]hX+------------+ | DESCRIPTOR | +=================+============+========+ +============+ | | MESSAGE(s) | | | address |--------->+=================+============+========+ +------------+ | head | ^-----head--------^ +------------+ | tail | ^---------tail-----------------^ +------------+ | size | ^---------------size--------------------^ +------------+}hjIsbah}(h]h ]h"]h$]h&]j5j6uh1j@#ht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjjhhubh)}(hEach message in data stream starts with the single u32 treated as a header, followed by optional set of u32 data that makes message specific payload::h]hEach message in data stream starts with the single u32 treated as a header, followed by optional set of u32 data that makes message specific payload:}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjjhhubjA#)}(hX+------------+---------+---------+---------+ | MESSAGE | +------------+---------+---------+---------+ | msg[0] | [1] | ... | [n-1] | +------------+---------+---------+---------+ | MESSAGE | MESSAGE PAYLOAD | + HEADER +---------+---------+---------+ | | 0 | ... | n | +======+=====+=========+=========+=========+ | 31:16| code| | | | +------+-----+ | | | | 15:5|flags| | | | +------+-----+ | | | | 4:0| len| | | | +------+-----+---------+---------+---------+ ^-------------len-------------^h]hX+------------+---------+---------+---------+ | MESSAGE | +------------+---------+---------+---------+ | msg[0] | [1] | ... | [n-1] | +------------+---------+---------+---------+ | MESSAGE | MESSAGE PAYLOAD | + HEADER +---------+---------+---------+ | | 0 | ... | n | +======+=====+=========+=========+=========+ | 31:16| code| | | | +------+-----+ | | | | 15:5|flags| | | | +------+-----+ | | | | 4:0| len| | | | +------+-----+---------+---------+---------+ ^-------------len-------------^}hjgsbah}(h]h ]h"]h$]h&]j5j6uh1j@#ht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjjhhubh)}(hThe message header consists of:h]hThe message header consists of:}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjjhhubj:)}(hhh](j:)}(h9**len**, indicates length of the message payload (in u32)h]h)}(hjh](j)}(h**len**h]hlen}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh2, indicates length of the message payload (in u32)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h **code**, indicates message codeh]h)}(hjh](j)}(h**code**h]hcode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, indicates message code}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h;**flags**, holds various bits to control message handling h]h)}(h9**flags**, holds various bits to control message handlingh](j)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh0, holds various bits to control message handling}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j;j;uh1j:hjhKhjjhhubh)}(h.. _HOST2GUC_SELF_CFG:h]h}(h]h ]h"]h$]h&]hhost2guc-self-cfguh1hhKhjjhhhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hjdKubh)}(h**HOST2GUC_SELF_CFG**h]j)}(hjh]hHOST2GUC_SELF_CFG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]j ah ]h"]host2guc_self_cfgah$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjjhhj}j"jsj}j jsjdKubh)}(hIThis message is used by Host KMD to setup of the `GuC Self Config KLVs`_.h](h1This message is used by Host KMD to setup of the }(hj(hhhNhNubj5)}(h`GuC Self Config KLVs`_h]hGuC Self Config KLVs}(hj0hhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVshguc-self-config-klvsuh1j5hj(j7;Kubh.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjjhhubh)}(h1This message must be sent as `MMIO HXG Message`_.h](hThis message must be sent as }(hjLhhhNhNubj5)}(h`MMIO HXG Message`_h]hMMIO HXG Message}(hjThhhNhNubah}(h]h ]h"]h$]h&]nameMMIO HXG Messagehjfuh1j5hjLj7;Kubh.}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjjhhubjgd)}(hXU +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 = MBZ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508 | +---+-------+--------------------------------------------------------------+ | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_ | | +-------+--------------------------------------------------------------+ | | 15:0 | **KLV_LEN** - KLV length | | | | | | | | - 32 bit KLV = 1 | | | | - 64 bit KLV = 2 | +---+-------+--------------------------------------------------------------+ | 2 | 31:0 | **VALUE32** - Bits 31-0 of the KLV value | +---+-------+--------------------------------------------------------------+ | 3 | 31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2) | +---+-------+--------------------------------------------------------------+ +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized | +---+-------+--------------------------------------------------------------+ h](j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjvubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjvubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjvubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjvubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_HOST_h](h ORIGIN = }(hjhhhNhNubj5)}(hGUC_HXG_ORIGIN_HOST_h]hGUC_HXG_ORIGIN_HOST}(hj!hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_HOSThjuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjFubah}(h]h ]h"]h$]h&]uh1jhjCubj)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hjahhhNhNubj5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hjihhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESThjcuh1j5hjaj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjWhKhj^ubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h1ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508h](h ACTION = }(hjhhhNhNubh)}(h_`GUC_ACTION_HOST2GUC_SELF_CFG`h]hGUC_ACTION_HOST2GUC_SELF_CFG}(hjhhhNhNubah}(h]guc-action-host2guc-self-cfgah ]h"]guc_action_host2guc_self_cfgah$]h&]uh1hhjubh = 0x0508}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31:16h]h31:16}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hKhj*ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h2**KLV_KEY** - KLV key, see `GuC Self Config KLVs`_h](j)}(h **KLV_KEY**h]hKLV_KEY}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubh - KLV key, see }(hjDhhhNhNubj5)}(h`GuC Self Config KLVs`_h]hGuC Self Config KLVs}(hjZhhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVshj@uh1j5hjDj7;Kubeh}(h]h ]h"]h$]h&]uh1hhj"hKhjAubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh](h)}(h**KLV_LEN** - KLV lengthh](j)}(h **KLV_LEN**h]hKLV_LEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - KLV length}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubjgd)}(h!- 32 bit KLV = 1 - 64 bit KLV = 2h]j:)}(hhh](j:)}(h32 bit KLV = 1h]h)}(hjh]h32 bit KLV = 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h64 bit KLV = 2h]h)}(hjh]h64 bit KLV = 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j;j;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1jfdhjhKhjubeh}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h2}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h(**VALUE32** - Bits 31-0 of the KLV valueh](j)}(h **VALUE32**h]hVALUE32}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubh - Bits 31-0 of the KLV value}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK hj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h3h]h3}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK"hjdubah}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhK"hj|ubah}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(h;**VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2)h](j)}(h **VALUE64**h]hVALUE64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Bits 63-32 of the KLV value (}(hjhhhNhNubj)}(h **KLV_LEN**h]hKLV_LEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = 2)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjuhK"hjubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hjvubeh}(h]h ]h"]h$]h&]colsKuh1jhjsubah}(h]h ]h"]h$]h&]uh1jhjoubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK&hjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Descriptionh]h Description}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hK&hj.ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK(hjWubah}(h]h ]h"]h$]h&]morerowsKuh1jhjTubj)}(hhh]h)}(h31h]h31}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghK(hjoubah}(h]h ]h"]h$]h&]uh1jhjTubj)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_GUC_h](h ORIGIN = }(hjhhhNhNubj5)}(hGUC_HXG_ORIGIN_GUC_h]hGUC_HXG_ORIGIN_GUC}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_GUChjuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjghK(hjubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hjhhhNhNubj5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESShjRuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h:DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognizedh](hDATA0 = }(hjhhhNhNubj)}(h**NUM**h]hNUM}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh+ - 1 if KLV was parsed, 0 if not recognized}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jfdhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjjhhubh)}(h.. _HOST2GUC_CONTROL_CTB:h]h}(h]h ]h"]h$]h&]hhost2guc-control-ctbuh1hhK+hjjhhhj ubh)}(h**HOST2GUC_CONTROL_CTB**h]j)}(hjlh]hHOST2GUC_CONTROL_CTB}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]jiah ]h"]host2guc_control_ctbah$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK2hjjhhj}jj_sj}jij_subh)}(hMThis H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_.h](h@This H2G action allows Vf Host to enable or disable H2G and G2H }(hjhhhNhNubj5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferhjuh1j5hjj7;Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK>hjjhhubh)}(h1This message must be sent as `MMIO HXG Message`_.h](hThis message must be sent as }(hjhhhNhNubj5)}(h`MMIO HXG Message`_h]hMMIO HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameMMIO HXG Messagehjfuh1j5hjj7;Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK@hjjhhubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 = MBZ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509 | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **CONTROL** - control `CTB based communication`_ | | | | | | | | - _`GUC_CTB_CONTROL_DISABLE` = 0 | | | | - _`GUC_CTB_CONTROL_ENABLE` = 1 | +---+-------+--------------------------------------------------------------+ +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | DATA0 = MBZ | +---+-------+--------------------------------------------------------------+ h](j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKChjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKChjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKEhjCubah}(h]h ]h"]h$]h&]morerowsKuh1jhj@ubj)}(hhh]h)}(h31h]h31}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShKEhj[ubah}(h]h ]h"]h$]h&]uh1jhj@ubj)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_HOST_h](h ORIGIN = }(hjuhhhNhNubj5)}(hGUC_HXG_ORIGIN_HOST_h]hGUC_HXG_ORIGIN_HOST}(hj}hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_HOSThjuh1j5hjuj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjShKEhjrubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKGhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hjhhhNhNubj5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESThjcuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjhKGhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKKhj"ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h4ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509h](h ACTION = }(hj=hhhNhNubh)}(h"_`GUC_ACTION_HOST2GUC_CONTROL_CTB`h]hGUC_ACTION_HOST2GUC_CONTROL_CTB}(hjEhhhNhNubah}(h]guc-action-host2guc-control-ctbah ]h"]guc_action_host2guc_control_ctbah$]h&]uh1hhj=ubh = 0x4509}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj3hKKhj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKMhjnubah}(h]h ]h"]h$]h&]uh1jhjkubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKMhjubah}(h]h ]h"]h$]h&]uh1jhjkubj)}(hhh](h)}(h0**CONTROL** - control `CTB based communication`_h](j)}(h **CONTROL**h]hCONTROL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - control }(hjhhhNhNubj5)}(h`CTB based communication`_h]hCTB based communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameCTB based communicationhjPuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhj~hKMhjubjgd)}(h@- _`GUC_CTB_CONTROL_DISABLE` = 0 - _`GUC_CTB_CONTROL_ENABLE` = 1h]j:)}(hhh](j:)}(h_`GUC_CTB_CONTROL_DISABLE` = 0h]h)}(hjh](h)}(h_`GUC_CTB_CONTROL_DISABLE`h]hGUC_CTB_CONTROL_DISABLE}(hjhhhNhNubah}(h]guc-ctb-control-disableah ]h"]guc_ctb_control_disableah$]h&]uh1hhjubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKOhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h_`GUC_CTB_CONTROL_ENABLE` = 1h]h)}(hjh](h)}(h_`GUC_CTB_CONTROL_ENABLE`h]hGUC_CTB_CONTROL_ENABLE}(hjhhhNhNubah}(h]guc-ctb-control-enableah ]h"]guc_ctb_control_enableah$]h&]uh1hhjubh = 1}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKPhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j;j;uh1j:hjhKOhjubah}(h]h ]h"]h$]h&]uh1jfdhjhKOhjubeh}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjPubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjPubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjPubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjtubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKThjubah}(h]h ]h"]h$]h&]uh1jhjtubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKThjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhjPubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKVhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKVhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_GUC_h](h ORIGIN = }(hjhhhNhNubj5)}(hGUC_HXG_ORIGIN_GUC_h]hGUC_HXG_ORIGIN_GUC}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_GUChjuh1j5hjj7;Kubeh}(h]h ]h"]h$]h&]uh1hhjhKVhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKXhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hj;hhhNhNubj5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjChhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESShjRuh1j5hj;j7;Kubeh}(h]h ]h"]h$]h&]uh1hhj1hKXhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKZhjhubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhKZhjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j1hjPubeh}(h]h ]h"]h$]h&]colsKuh1jhjMubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfdhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:361: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKBhjjhhubh)}(h .. _GuC KLV:h]h}(h]h ]h"]h$]h&]hguc-klvuh1hhKhjjhhhNjdKubh)}(h **GuC KLV**h]j)}(hjh]hGuC KLV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"]guc klvah$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjjhhj}jjsj}jjsjdKubjgd)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | **KEY** - KLV key identifier | | | | - `GuC Self Config KLVs`_ | | | | | | +-------+--------------------------------------------------------------+ | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) | +---+-------+ | |...| | | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hK hj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj2)}(hhh](j)}(hhh](j)}(hhh]h)}(hj>h]h0}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjUubah}(h]h ]h"]h$]h&]morerowsKuh1jhjRubj)}(hhh]h)}(h31:16h]h31:16}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehKhjmubah}(h]h ]h"]h$]h&]uh1jhjRubj)}(hhh]j)}(hhh]j)}(h7**KEY** - KLV key identifier - `GuC Self Config KLVs`_ h](j$)}(h**KEY** - KLV key identifierh](j)}(h**KEY**h]hKEY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - KLV key identifier}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubj@)}(hhh]j:)}(hhh]j:)}(h`GuC Self Config KLVs`_ h]h)}(h`GuC Self Config KLVs`_h]j5)}(hjh]hGuC Self Config KLVs}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVshj@uh1j5hjj7;Kubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&]j;j;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h+**LEN** - length of VALUE (in 32bit dwords)h](j)}(h**LEN**h]hLEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh$ - length of VALUE (in 32bit dwords)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj hKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjAubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh]h)}(h31:0h]h31:0}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhKhjXubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh]h)}(h;**VALUE** - actual value of the KLV (format depends on KEY)h](j)}(h **VALUE**h]hVALUE}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubh2 - actual value of the KLV (format depends on KEY)}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjQhKhjoubah}(h]h ]h"]h$]h&]morerowsKuh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh](j)}(hhh]h)}(hjh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j1hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jfdhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK hjjhhubh)}(h.. _GuC Self Config KLVs:h]h}(h]h ]h"]h$]h&]hj@uh1hhKhjjhhhNjdKubh)}(h**GuC Self Config KLVs**h]j)}(hj"h]hGuC Self Config KLVs}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]j@ah ]h"]guc self config klvsah$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjjhhj}j5jsj}j@jsjdKubh)}(h:`GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.h](j5)}(h `GuC KLV`_h]hGuC KLV}(hj?hhhNhNubah}(h]h ]h"]h$]h&]nameGuC KLVhjuh1j5hj;j7;Kubh keys available for use with }(hj;hhhNhNubj5)}(hHOST2GUC_SELF_CFG_h]hHOST2GUC_SELF_CFG}(hjShhhNhNubah}(h]h ]h"]h$]h&]nameHOST2GUC_SELF_CFGhj uh1j5hj;j7;Kubh.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK%hjjhhubj)}(hhh](j)}(h_`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902 Refers to 64 bit Global Gfx address of H2G `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode. h](j$)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR`h](h)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR`h]hGUC_KLV_SELF_CFG_H2G_CTB_ADDR}(hjyhhhNhNubah}(h]guc-klv-self-cfg-h2g-ctb-addrah ]h"]guc_klv_self_cfg_h2g_ctb_addrah$]h&]uh1hhjuubhh}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK)hjqubh classifier)}(h0x0902h]h0x0902}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqhjubj@)}(hhh]h)}(hRefers to 64 bit Global Gfx address of H2G `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of H2G }(hjhhhNhNubj5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferhjuh1j5hjj7;KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK(hjubah}(h]h ]h"]h$]h&]uh1j?hjqubeh}(h]h ]h"]h$]h&]uh1jhjhK)hjnubj)}(h_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR` : 0x0903 Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode. h](j$)}(h+_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR`h](h)}(h+_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR`h]h(GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR}(hjhhhNhNubah}(h](guc-klv-self-cfg-h2g-ctb-descriptor-addrah ]h"](guc_klv_self_cfg_h2g_ctb_descriptor_addrah$]h&]uh1hhjubhh}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK-hjubj)}(h0x0903h]h0x0903}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhjubj@)}(hhh]h)}(hRefers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of H2G }(hjhhhNhNubj5)}(h`CTB Descriptor`_h]hCTB Descriptor}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameCTB DescriptorhjHuh1j5hjj7;KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK,hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK-hjnubj)}(hs_`GUC_KLV_SELF_CFG_H2G_CTB_SIZE` : 0x0904 Refers to size of H2G `CT Buffer`_ in bytes. Should be a multiple of 4K. h](j$)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE`h](h)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE`h]hGUC_KLV_SELF_CFG_H2G_CTB_SIZE}(hj?hhhNhNubah}(h]guc-klv-self-cfg-h2g-ctb-sizeah ]h"]guc_klv_self_cfg_h2g_ctb_sizeah$]h&]uh1hhj;ubhh}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK1hj7ubj)}(h0x0904h]h0x0904}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7hjXubj@)}(hhh]h)}(hHRefers to size of H2G `CT Buffer`_ in bytes. Should be a multiple of 4K.h](hRefers to size of H2G }(hjjhhhNhNubj5)}(h `CT Buffer`_h]h CT Buffer}(hjrhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferhjuh1j5hjjj7;Kubh& in bytes. Should be a multiple of 4K.}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK0hjgubah}(h]h ]h"]h$]h&]uh1j?hj7ubeh}(h]h ]h"]h$]h&]uh1jhjXhK1hjnubj)}(h_`GUC_KLV_SELF_CFG_G2H_CTB_ADDR` : 0x0905 Refers to 64 bit Global Gfx address of G2H `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode. h](j$)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR`h](h)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR`h]hGUC_KLV_SELF_CFG_G2H_CTB_ADDR}(hjhhhNhNubah}(h]guc-klv-self-cfg-g2h-ctb-addrah ]h"]guc_klv_self_cfg_g2h_ctb_addrah$]h&]uh1hhjubhh}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK5hjubj)}(h0x0905h]h0x0905}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhjubj@)}(hhh]h)}(hRefers to 64 bit Global Gfx address of G2H `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of G2H }(hjhhhNhNubj5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferhjuh1j5hjj7;KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK4hjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK5hjnubj)}(h_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR` : 0x0906 Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode. h](j$)}(h+_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR`h](h)}(h+_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR`h]h(GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR}(hjhhhNhNubah}(h](guc-klv-self-cfg-g2h-ctb-descriptor-addrah ]h"](guc_klv_self_cfg_g2h_ctb_descriptor_addrah$]h&]uh1hhjubhh}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK9hjubj)}(h0x0906h]h0x0906}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhjubj@)}(hhh]h)}(hRefers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of G2H }(hj.hhhNhNubj5)}(h`CTB Descriptor`_h]hCTB Descriptor}(hj6hhhNhNubah}(h]h ]h"]h$]h&]nameCTB DescriptorhjHuh1j5hj.j7;KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK8hj+ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhK9hjnubj)}(ht_`GUC_KLV_SELF_CFG_G2H_CTB_SIZE` : 0x0907 Refers to size of G2H `CT Buffer`_ in bytes. Should be a multiple of 4K. h](j$)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE`h](h)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE`h]hGUC_KLV_SELF_CFG_G2H_CTB_SIZE}(hjehhhNhNubah}(h]guc-klv-self-cfg-g2h-ctb-sizeah ]h"]guc_klv_self_cfg_g2h_ctb_sizeah$]h&]uh1hhjaubhh}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1j#hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK>hj]ubj)}(h0x0907h]h0x0907}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]hj~ubj@)}(hhh]h)}(hHRefers to size of G2H `CT Buffer`_ in bytes. Should be a multiple of 4K.h](hRefers to size of G2H }(hjhhhNhNubj5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferhjuh1j5hjj7;Kubh& in bytes. Should be a multiple of 4K.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjnubeh}(h]h ]h"]h$]h&]uh1jhjjhhhNhNubeh}(h]guc-abiah ]h"]guc abiah$]h&]uh1hhj?hhhhhMdubeh}(h]gucah ]h"]gucah$]h&]uh1hhjhhhhhMAubh)}(hhh](h)}(hHuCh]hHuC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMmubh)}(hThe HuC is a dedicated microcontroller for usage in media HEVC (High Efficiency Video Coding) operations. Userspace can directly use the firmware capabilities by adding HuC specific commands to batch buffers.h]hThe HuC is a dedicated microcontroller for usage in media HEVC (High Efficiency Video Coding) operations. Userspace can directly use the firmware capabilities by adding HuC specific commands to batch buffers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:366: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chKhjhhubh)}(hThe kernel driver is only responsible for loading the HuC firmware and triggering its security authentication. This is done differently depending on the platform:h]hThe kernel driver is only responsible for loading the HuC firmware and triggering its security authentication. This is done differently depending on the platform:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:366: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chKhjhhubj:)}(hhh](j:)}(hholder platforms (from Gen9 to most Gen12s): the load is performed via DMA and the authentication via GuCh]h)}(hholder platforms (from Gen9 to most Gen12s): the load is performed via DMA and the authentication via GuCh]hholder platforms (from Gen9 to most Gen12s): the load is performed via DMA and the authentication via GuC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:366: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chKhj ubah}(h]h ]h"]h$]h&]uh1j:hj ubj:)}(h8DG2: load and authentication are both performed via GSC.h]h)}(hj" h]h8DG2: load and authentication are both performed via GSC.}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:366: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chKhj ubah}(h]h ]h"]h$]h&]uh1j:hj ubj:)}(hMTL and newer platforms: the load is performed via DMA (same as with not-DG2 older platforms), while the authentication is done in 2-steps, a first auth for clear-media workloads via GuC and a second one for all workloads via GSC. h]h)}(hMTL and newer platforms: the load is performed via DMA (same as with not-DG2 older platforms), while the authentication is done in 2-steps, a first auth for clear-media workloads via GuC and a second one for all workloads via GSC.h]hMTL and newer platforms: the load is performed via DMA (same as with not-DG2 older platforms), while the authentication is done in 2-steps, a first auth for clear-media workloads via GuC and a second one for all workloads via GSC.}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:366: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chK hj8 ubah}(h]h ]h"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]j;j;uh1j:hj hKhjhhubh)}(hXOn platforms where the GuC does the authentication, to correctly do so the HuC binary must be loaded before the GuC one. Loading the HuC is optional; however, not using the HuC might negatively impact power usage and/or performance of media workloads, depending on the use-cases. HuC must be reloaded on events that cause the WOPCM to lose its contents (S3/S4, FLR); on older platforms the HuC must also be reloaded on GuC/GT reset, while on newer ones it will survive that.h]hXOn platforms where the GuC does the authentication, to correctly do so the HuC binary must be loaded before the GuC one. Loading the HuC is optional; however, not using the HuC might negatively impact power usage and/or performance of media workloads, depending on the use-cases. HuC must be reloaded on events that cause the WOPCM to lose its contents (S3/S4, FLR); on older platforms the HuC must also be reloaded on GuC/GT reset, while on newer ones it will survive that.}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:366: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chK%hjhhubh)}(hVSee https://github.com/intel/media-driver for the latest details on HuC functionality.h](hSee }(hjf hhhNhNubj5)}(h%https://github.com/intel/media-driverh]h%https://github.com/intel/media-driver}(hjn hhhNhNubah}(h]h ]h"]h$]h&]refurijp uh1j5hjf ubh- for the latest details on HuC functionality.}(hjf hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:366: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chK.hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jintel_huc_auth (C function)c.intel_huc_authhNtauh1jhjhhhNhNubj)}(hhh](j)}(hSint intel_huc_auth (struct intel_huc *huc, enum intel_huc_authentication_type type)h]j)}(hRint intel_huc_auth(struct intel_huc *huc, enum intel_huc_authentication_type type)h](jn)}(hinth]hint}(hj hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:368: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chMubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj hhhj hMubj)}(hintel_huc_authh]j)}(hintel_huc_authh]hintel_huc_auth}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj hhhj hMubj8)}(h@(struct intel_huc *huc, enum intel_huc_authentication_type type)h](j>)}(hstruct intel_huc *huch](jD)}(hjGh]hstruct}(hj hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj ubj )}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubh)}(hhh]j)}(h intel_huch]h intel_huc}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jj sbc.intel_huc_authasbuh1hhj ubj )}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj)}(hjh]h*}(hj*!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hhuch]hhuc}(hj7!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj ubj>)}(h'enum intel_huc_authentication_type typeh](jD)}(hjh]henum}(hjP!hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjL!ubj )}(h h]h }(hj]!hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjL!ubh)}(hhh]j)}(hintel_huc_authentication_typeh]hintel_huc_authentication_type}(hjn!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjk!ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjp!modnameN classnameNjj)}j]j!c.intel_huc_authasbuh1hhjL!ubj )}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjL!ubj)}(htypeh]htype}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL!ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj hhhj hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj hhhj hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hMhj hhubj)}(hhh]h)}(hAuthenticate HuC uCodeh]hAuthenticate HuC uCode}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:368: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chMhj!hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj!jj!jjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct intel_huc *huc`` intel_huc structure ``enum intel_huc_authentication_type type`` authentication type (via GuC or via GSC) **Description** Called after HuC and GuC firmware loading during intel_uc_init_hw(). This function invokes the GuC action to authenticate the HuC firmware, passing the offset of the RSA signature to intel_guc_auth_huc(). It then waits for up to 50ms for firmware verification ACK.h](h)}(h**Parameters**h]j)}(hj!h]h Parameters}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:368: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chM hj!ubj)}(hhh](j)}(h.``struct intel_huc *huc`` intel_huc structure h](j$)}(h``struct intel_huc *huc``h]j*)}(hj"h]hstruct intel_huc *huc}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj"ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:368: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chMhj!ubj@)}(hhh]h)}(hintel_huc structureh]hintel_huc structure}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMhj"ubah}(h]h ]h"]h$]h&]uh1j?hj!ubeh}(h]h ]h"]h$]h&]uh1jhj"hMhj!ubj)}(hU``enum intel_huc_authentication_type type`` authentication type (via GuC or via GSC) h](j$)}(h+``enum intel_huc_authentication_type type``h]j*)}(hj>"h]h'enum intel_huc_authentication_type type}(hj@"hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj<"ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:368: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chMhj8"ubj@)}(hhh]h)}(h(authentication type (via GuC or via GSC)h]h(authentication type (via GuC or via GSC)}(hjW"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjS"hMhjT"ubah}(h]h ]h"]h$]h&]uh1j?hj8"ubeh}(h]h ]h"]h$]h&]uh1jhjS"hMhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!ubh)}(h**Description**h]j)}(hjy"h]h Description}(hj{"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjw"ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:368: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chM hj!ubh)}(hDCalled after HuC and GuC firmware loading during intel_uc_init_hw().h]hDCalled after HuC and GuC firmware loading during intel_uc_init_hw().}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:368: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chM hj!ubh)}(hThis function invokes the GuC action to authenticate the HuC firmware, passing the offset of the RSA signature to intel_guc_auth_huc(). It then waits for up to 50ms for firmware verification ACK.h]hThis function invokes the GuC action to authenticate the HuC firmware, passing the offset of the RSA signature to intel_guc_auth_huc(). It then waits for up to 50ms for firmware verification ACK.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:368: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chM hj!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubh)}(hhh](h)}(hHuC Memory Managementh]hHuC Memory Management}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhMtubh)}(hX?Similarly to the GuC, the HuC can't do any memory allocations on its own, with the difference being that the allocations for HuC usage are handled by the userspace driver instead of the kernel one. The HuC accesses the memory via the PPGTT belonging to the context loaded on the VCS executing the HuC-specific commands.h]hXASimilarly to the GuC, the HuC can’t do any memory allocations on its own, with the difference being that the allocations for HuC usage are handled by the userspace driver instead of the kernel one. The HuC accesses the memory via the PPGTT belonging to the context loaded on the VCS executing the HuC-specific commands.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:374: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chK5hj"hhubeh}(h]huc-memory-managementah ]h"]huc memory managementah$]h&]uh1hhjhhhhhMtubh)}(hhh](h)}(hHuC Firmware Layouth]hHuC Firmware Layout}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhMzubh)}(hHThe HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_h](h2The HuC FW layout is the same as the GuC one, see }(hj"hhhNhNubj5)}(h`GuC Firmware Layout`_h]hGuC Firmware Layout}(hj"hhhNhNubah}(h]h ]h"]h$]h&]nameGuC Firmware Layouthjuh1j5hj"j7;Kubeh}(h]h ]h"]h$]h&]uh1hhhhM{hj"hhubeh}(h]huc-firmware-layoutah ]h"]huc firmware layoutah$]h&]uh1hhjhhhhhMzubeh}(h]hucah ]h"]hucah$]h&]uh1hhjhhhhhMmubh)}(hhh](h)}(hDMCh]hDMC}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhM~ubh)}(h!See :ref:`drm/intel-display/dmc`.h](hSee }(hj,#hhhNhNubh)}(h:ref:`drm/intel-display/dmc`h]h)}(hj6#h]hdrm/intel-display/dmc}(hj8#hhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1hhj4#ubah}(h]h ]h"]h$]h&]refdocj refdomainjB#reftyperef refexplicitrefwarnjdrm/intel-display/dmcuh1hhhhMhj,#ubh.}(hj,#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj#hhubeh}(h]dmcah ]h"]dmcah$]h&]uh1hhjhhhhhM~ubeh}(h]microcontrollersah ]h"]microcontrollersah$]h&]uh1hhhhhhhhM/ubh)}(hhh](h)}(hTracingh]hTracing}(hjq#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn#hhhhhMubh)}(hZThis sections covers all things related to the tracepoints implemented in the i915 driver.h]hZThis sections covers all things related to the tracepoints implemented in the i915 driver.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjn#hhubh)}(hhh](h)}(h(i915_ppgtt_create and i915_ppgtt_releaseh]h(i915_ppgtt_create and i915_ppgtt_release}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMubh)}(hXWith full ppgtt enabled each process using drm will allocate at least one translation table. With these traces it is possible to keep track of the allocation and of the lifetime of the tables; this can be used during testing/debug to verify that we are not leaking ppgtts. These traces identify the ppgtt through the vm pointer, which is also printed by the i915_vma_bind and i915_vma_unbind tracepoints.h]hXWith full ppgtt enabled each process using drm will allocate at least one translation table. With these traces it is possible to keep track of the allocation and of the lifetime of the tables; this can be used during testing/debug to verify that we are not leaking ppgtts. These traces identify the ppgtt through the vm pointer, which is also printed by the i915_vma_bind and i915_vma_unbind tracepoints.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/i915:394: ./drivers/gpu/drm/i915/i915_trace.hhMhj#hhubeh}(h](i915-ppgtt-create-and-i915-ppgtt-releaseah ]h"](i915_ppgtt_create and i915_ppgtt_releaseah$]h&]uh1hhjn#hhhhhMubh)}(hhh](h)}(h)i915_context_create and i915_context_freeh]h)i915_context_create and i915_context_free}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMubh)}(hThese tracepoints are used to track creation and deletion of contexts. If full ppgtt is enabled, they also print the address of the vm assigned to the context.h]hThese tracepoints are used to track creation and deletion of contexts. If full ppgtt is enabled, they also print the address of the vm assigned to the context.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/i915:400: ./drivers/gpu/drm/i915/i915_trace.hhMhj#hhubeh}(h])i915-context-create-and-i915-context-freeah ]h"])i915_context_create and i915_context_freeah$]h&]uh1hhjn#hhhhhMubeh}(h]tracingah ]h"]tracingah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hPerfh]hPerf}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMubh)}(hhh](h)}(hOverviewh]hOverview}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMubh)}(hGen graphics supports a large number of performance counters that can help driver and application developers understand and optimize their use of the GPU.h]hGen graphics supports a large number of performance counters that can help driver and application developers understand and optimize their use of the GPU.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:408: ./drivers/gpu/drm/i915/i915_perf.chKhj#hhubh)}(hThis i915 perf interface enables userspace to configure and open a file descriptor representing a stream of GPU metrics which can then be read() as a stream of sample records.h]hThis i915 perf interface enables userspace to configure and open a file descriptor representing a stream of GPU metrics which can then be read() as a stream of sample records.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:408: ./drivers/gpu/drm/i915/i915_perf.chK!hj#hhubh)}(hThe interface is particularly suited to exposing buffered metrics that are captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.h]hThe interface is particularly suited to exposing buffered metrics that are captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.}(hj%$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:408: ./drivers/gpu/drm/i915/i915_perf.chK%hj#hhubh)}(hX7Streams representing a single context are accessible to applications with a corresponding drm file descriptor, such that OpenGL can use the interface without special privileges. Access to system-wide metrics requires root privileges by default, unless changed via the dev.i915.perf_event_paranoid sysctl option.h]hX7Streams representing a single context are accessible to applications with a corresponding drm file descriptor, such that OpenGL can use the interface without special privileges. Access to system-wide metrics requires root privileges by default, unless changed via the dev.i915.perf_event_paranoid sysctl option.}(hj4$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:408: ./drivers/gpu/drm/i915/i915_perf.chK(hj#hhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhj#hhhhhMubh)}(hhh](h)}(hComparison with Core Perfh]hComparison with Core Perf}(hjN$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjK$hhhhhMubh)}(hfThe interface was initially inspired by the core Perf infrastructure but some notable differences are:h]hfThe interface was initially inspired by the core Perf infrastructure but some notable differences are:}(hj\$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chK3hjK$hhubh)}(hXi915 perf file descriptors represent a "stream" instead of an "event"; where a perf event primarily corresponds to a single 64bit value, while a stream might sample sets of tightly-coupled counters, depending on the configuration. For example the Gen OA unit isn't designed to support orthogonal configurations of individual counters; it's configured for a set of related counters. Samples for an i915 perf stream capturing OA metrics will include a set of counter values packed in a compact HW specific format. The OA unit supports a number of different packing formats which can be selected by the user opening the stream. Perf has support for grouping events, but each event in the group is configured, validated and authenticated individually with separate system calls.h]hXi915 perf file descriptors represent a “stream” instead of an “event”; where a perf event primarily corresponds to a single 64bit value, while a stream might sample sets of tightly-coupled counters, depending on the configuration. For example the Gen OA unit isn’t designed to support orthogonal configurations of individual counters; it’s configured for a set of related counters. Samples for an i915 perf stream capturing OA metrics will include a set of counter values packed in a compact HW specific format. The OA unit supports a number of different packing formats which can be selected by the user opening the stream. Perf has support for grouping events, but each event in the group is configured, validated and authenticated individually with separate system calls.}(hjk$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chK6hjK$hhubh)}(hi915 perf stream configurations are provided as an array of u64 (key,value) pairs, instead of a fixed struct with multiple miscellaneous config members, interleaved with event-type specific members.h]hi915 perf stream configurations are provided as an array of u64 (key,value) pairs, instead of a fixed struct with multiple miscellaneous config members, interleaved with event-type specific members.}(hjz$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKBhjK$hhubh)}(hXLi915 perf doesn't support exposing metrics via an mmap'd circular buffer. The supported metrics are being written to memory by the GPU unsynchronized with the CPU, using HW specific packing formats for counter sets. Sometimes the constraints on HW configuration require reports to be filtered before it would be acceptable to expose them to unprivileged applications - to hide the metrics of other processes/contexts. For these use cases a read() based interface is a good fit, and provides an opportunity to filter data as it gets copied from the GPU mapped buffers to userspace buffers.h]hXPi915 perf doesn’t support exposing metrics via an mmap’d circular buffer. The supported metrics are being written to memory by the GPU unsynchronized with the CPU, using HW specific packing formats for counter sets. Sometimes the constraints on HW configuration require reports to be filtered before it would be acceptable to expose them to unprivileged applications - to hide the metrics of other processes/contexts. For these use cases a read() based interface is a good fit, and provides an opportunity to filter data as it gets copied from the GPU mapped buffers to userspace buffers.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKFhjK$hhubh)}(hhh](h)}(h2Issues hit with first prototype based on Core Perfh]h2Issues hit with first prototype based on Core Perf}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hNhNubh)}(hXThe first prototype of this driver was based on the core perf infrastructure, and while we did make that mostly work, with some changes to perf, we found we were breaking or working around too many assumptions baked into perf's currently cpu centric design.h]hXThe first prototype of this driver was based on the core perf infrastructure, and while we did make that mostly work, with some changes to perf, we found we were breaking or working around too many assumptions baked into perf’s currently cpu centric design.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKShj$ubh)}(hIn the end we didn't see a clear benefit to making perf's implementation and interface more complex by changing design assumptions while we knew we still wouldn't be able to use any existing perf based userspace tools.h]hIn the end we didn’t see a clear benefit to making perf’s implementation and interface more complex by changing design assumptions while we knew we still wouldn’t be able to use any existing perf based userspace tools.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKXhj$ubh)}(hXAlso considering the Gen specific nature of the Observability hardware and how userspace will sometimes need to combine i915 perf OA metrics with side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're expecting the interface to be used by a platform specific userspace such as OpenGL or tools. This is to say; we aren't inherently missing out on having a standard vendor/architecture agnostic interface by not using perf.h]hXAlso considering the Gen specific nature of the Observability hardware and how userspace will sometimes need to combine i915 perf OA metrics with side-band OA data captured via MI_REPORT_PERF_COUNT commands; we’re expecting the interface to be used by a platform specific userspace such as OpenGL or tools. This is to say; we aren’t inherently missing out on having a standard vendor/architecture agnostic interface by not using perf.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chK\hj$ubh)}(hFor posterity, in case we might re-visit trying to adapt core perf to be better suited to exposing i915 metrics these were the main pain points we hit:h]hFor posterity, in case we might re-visit trying to adapt core perf to be better suited to exposing i915 metrics these were the main pain points we hit:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKdhj$ubj:)}(hhh](j:)}(hXQThe perf based OA PMU driver broke some significant design assumptions: Existing perf pmus are used for profiling work on a cpu and we were introducing the idea of _IS_DEVICE pmus with different security implications, the need to fake cpu-related data (such as user/kernel registers) to fit with perf's current design, and adding _DEVICE records as a way to forward device-specific status records. The OA unit writes reports of counters into a circular buffer, without involvement from the CPU, making our PMU driver the first of a kind. Given the way we were periodically forward data from the GPU-mapped, OA buffer to perf's buffer, those bursts of sample writes looked to perf like we were sampling too fast and so we had to subvert its throttling checks. Perf supports groups of counters and allows those to be read via transactions internally but transactions currently seem designed to be explicitly initiated from the cpu (say in response to a userspace read()) and while we could pull a report out of the OA buffer we can't trigger a report from the cpu on demand. Related to being report based; the OA counters are configured in HW as a set while perf generally expects counter configurations to be orthogonal. Although counters can be associated with a group leader as they are opened, there's no clear precedent for being able to provide group-wide configuration attributes (for example we want to let userspace choose the OA unit report format used to capture all counters in a set, or specify a GPU context to filter metrics on). We avoided using perf's grouping feature and forwarded OA reports to userspace via perf's 'raw' sample field. This suited our userspace well considering how coupled the counters are when dealing with normalizing. It would be inconvenient to split counters up into separate events, only to require userspace to recombine them. For Mesa it's also convenient to be forwarded raw, periodic reports for combining with the side-band raw reports it captures using MI_REPORT_PERF_COUNT commands. - As a side note on perf's grouping feature; there was also some concern that using PERF_FORMAT_GROUP as a way to pack together counter values would quite drastically inflate our sample sizes, which would likely lower the effective sampling resolutions we could use when the available memory bandwidth is limited. With the OA unit's report formats, counters are packed together as 32 or 40bit values, with the largest report size being 256 bytes. PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a documented ordering to the values, implying PERF_FORMAT_ID must also be used to add a 64bit ID before each value; giving 16 bytes per counter. Related to counter orthogonality; we can't time share the OA unit, while event scheduling is a central design idea within perf for allowing userspace to open + enable more events than can be configured in HW at any one time. The OA unit is not designed to allow re-configuration while in use. We can't reconfigure the OA unit without losing internal OA unit state which we can't access explicitly to save and restore. Reconfiguring the OA unit is also relatively slow, involving ~100 register writes. From userspace Mesa also depends on a stable OA configuration when emitting MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be disabled while there are outstanding MI_RPC commands lest we hang the command streamer. The contents of sample records aren't extensible by device drivers (i.e. the sample_type bits). As an example; Sourab Gupta had been looking to attach GPU timestamps to our OA samples. We were shoehorning OA reports into sample records by using the 'raw' field, but it's tricky to pack more than one thing into this field because events/core.c currently only lets a pmu give a single raw data pointer plus len which will be copied into the ring buffer. To include more than the OA report we'd have to copy the report into an intermediate larger buffer. I'd been considering allowing a vector of data+len values to be specified for copying the raw data, but it felt like a kludge to being using the raw field for this purpose. h](h)}(hGThe perf based OA PMU driver broke some significant design assumptions:h]hGThe perf based OA PMU driver broke some significant design assumptions:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKhhj$ubh)}(hXEExisting perf pmus are used for profiling work on a cpu and we were introducing the idea of _IS_DEVICE pmus with different security implications, the need to fake cpu-related data (such as user/kernel registers) to fit with perf's current design, and adding _DEVICE records as a way to forward device-specific status records.h]hXGExisting perf pmus are used for profiling work on a cpu and we were introducing the idea of _IS_DEVICE pmus with different security implications, the need to fake cpu-related data (such as user/kernel registers) to fit with perf’s current design, and adding _DEVICE records as a way to forward device-specific status records.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKjhj$ubh)}(hThe OA unit writes reports of counters into a circular buffer, without involvement from the CPU, making our PMU driver the first of a kind.h]hThe OA unit writes reports of counters into a circular buffer, without involvement from the CPU, making our PMU driver the first of a kind.}(hj %hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKphj$ubh)}(hGiven the way we were periodically forward data from the GPU-mapped, OA buffer to perf's buffer, those bursts of sample writes looked to perf like we were sampling too fast and so we had to subvert its throttling checks.h]hGiven the way we were periodically forward data from the GPU-mapped, OA buffer to perf’s buffer, those bursts of sample writes looked to perf like we were sampling too fast and so we had to subvert its throttling checks.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKshj$ubh)}(hX9Perf supports groups of counters and allows those to be read via transactions internally but transactions currently seem designed to be explicitly initiated from the cpu (say in response to a userspace read()) and while we could pull a report out of the OA buffer we can't trigger a report from the cpu on demand.h]hX;Perf supports groups of counters and allows those to be read via transactions internally but transactions currently seem designed to be explicitly initiated from the cpu (say in response to a userspace read()) and while we could pull a report out of the OA buffer we can’t trigger a report from the cpu on demand.}(hj(%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKwhj$ubh)}(hXRelated to being report based; the OA counters are configured in HW as a set while perf generally expects counter configurations to be orthogonal. Although counters can be associated with a group leader as they are opened, there's no clear precedent for being able to provide group-wide configuration attributes (for example we want to let userspace choose the OA unit report format used to capture all counters in a set, or specify a GPU context to filter metrics on). We avoided using perf's grouping feature and forwarded OA reports to userspace via perf's 'raw' sample field. This suited our userspace well considering how coupled the counters are when dealing with normalizing. It would be inconvenient to split counters up into separate events, only to require userspace to recombine them. For Mesa it's also convenient to be forwarded raw, periodic reports for combining with the side-band raw reports it captures using MI_REPORT_PERF_COUNT commands.h]hXRelated to being report based; the OA counters are configured in HW as a set while perf generally expects counter configurations to be orthogonal. Although counters can be associated with a group leader as they are opened, there’s no clear precedent for being able to provide group-wide configuration attributes (for example we want to let userspace choose the OA unit report format used to capture all counters in a set, or specify a GPU context to filter metrics on). We avoided using perf’s grouping feature and forwarded OA reports to userspace via perf’s ‘raw’ sample field. This suited our userspace well considering how coupled the counters are when dealing with normalizing. It would be inconvenient to split counters up into separate events, only to require userspace to recombine them. For Mesa it’s also convenient to be forwarded raw, periodic reports for combining with the side-band raw reports it captures using MI_REPORT_PERF_COUNT commands.}(hj7%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chK}hj$ubj:)}(hhh]j:)}(hXAs a side note on perf's grouping feature; there was also some concern that using PERF_FORMAT_GROUP as a way to pack together counter values would quite drastically inflate our sample sizes, which would likely lower the effective sampling resolutions we could use when the available memory bandwidth is limited. With the OA unit's report formats, counters are packed together as 32 or 40bit values, with the largest report size being 256 bytes. PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a documented ordering to the values, implying PERF_FORMAT_ID must also be used to add a 64bit ID before each value; giving 16 bytes per counter. h](h)}(hX7As a side note on perf's grouping feature; there was also some concern that using PERF_FORMAT_GROUP as a way to pack together counter values would quite drastically inflate our sample sizes, which would likely lower the effective sampling resolutions we could use when the available memory bandwidth is limited.h]hX9As a side note on perf’s grouping feature; there was also some concern that using PERF_FORMAT_GROUP as a way to pack together counter values would quite drastically inflate our sample sizes, which would likely lower the effective sampling resolutions we could use when the available memory bandwidth is limited.}(hjM%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKhjI%ubh)}(hWith the OA unit's report formats, counters are packed together as 32 or 40bit values, with the largest report size being 256 bytes.h]hWith the OA unit’s report formats, counters are packed together as 32 or 40bit values, with the largest report size being 256 bytes.}(hj\%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKhjI%ubh)}(hPERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a documented ordering to the values, implying PERF_FORMAT_ID must also be used to add a 64bit ID before each value; giving 16 bytes per counter.h]hPERF_FORMAT_GROUP values are 64bit, but there doesn’t appear to be a documented ordering to the values, implying PERF_FORMAT_ID must also be used to add a 64bit ID before each value; giving 16 bytes per counter.}(hjk%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKhjI%ubeh}(h]h ]h"]h$]h&]uh1j:hjF%ubah}(h]h ]h"]h$]h&]j;j;uh1j:hj[%hKhj$ubh)}(hXRelated to counter orthogonality; we can't time share the OA unit, while event scheduling is a central design idea within perf for allowing userspace to open + enable more events than can be configured in HW at any one time. The OA unit is not designed to allow re-configuration while in use. We can't reconfigure the OA unit without losing internal OA unit state which we can't access explicitly to save and restore. Reconfiguring the OA unit is also relatively slow, involving ~100 register writes. From userspace Mesa also depends on a stable OA configuration when emitting MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be disabled while there are outstanding MI_RPC commands lest we hang the command streamer.h]hXRelated to counter orthogonality; we can’t time share the OA unit, while event scheduling is a central design idea within perf for allowing userspace to open + enable more events than can be configured in HW at any one time. The OA unit is not designed to allow re-configuration while in use. We can’t reconfigure the OA unit without losing internal OA unit state which we can’t access explicitly to save and restore. Reconfiguring the OA unit is also relatively slow, involving ~100 register writes. From userspace Mesa also depends on a stable OA configuration when emitting MI_REPORT_PERF_COUNT commands and importantly the OA unit can’t be disabled while there are outstanding MI_RPC commands lest we hang the command streamer.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKhj$ubh)}(hXThe contents of sample records aren't extensible by device drivers (i.e. the sample_type bits). As an example; Sourab Gupta had been looking to attach GPU timestamps to our OA samples. We were shoehorning OA reports into sample records by using the 'raw' field, but it's tricky to pack more than one thing into this field because events/core.c currently only lets a pmu give a single raw data pointer plus len which will be copied into the ring buffer. To include more than the OA report we'd have to copy the report into an intermediate larger buffer. I'd been considering allowing a vector of data+len values to be specified for copying the raw data, but it felt like a kludge to being using the raw field for this purpose.h]hXThe contents of sample records aren’t extensible by device drivers (i.e. the sample_type bits). As an example; Sourab Gupta had been looking to attach GPU timestamps to our OA samples. We were shoehorning OA reports into sample records by using the ‘raw’ field, but it’s tricky to pack more than one thing into this field because events/core.c currently only lets a pmu give a single raw data pointer plus len which will be copied into the ring buffer. To include more than the OA report we’d have to copy the report into an intermediate larger buffer. I’d been considering allowing a vector of data+len values to be specified for copying the raw data, but it felt like a kludge to being using the raw field for this purpose.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKhj$ubeh}(h]h ]h"]h$]h&]uh1j:hj$ubj:)}(hX\It felt like our perf based PMU was making some technical compromises just for the sake of using perf: perf_event_open() requires events to either relate to a pid or a specific cpu core, while our device pmu related to neither. Events opened with a pid will be automatically enabled/disabled according to the scheduling of that process - so not appropriate for us. When an event is related to a cpu id, perf ensures pmu methods will be invoked via an inter process interrupt on that core. To avoid invasive changes our userspace opened OA perf events for a specific cpu. This was workable but it meant the majority of the OA driver ran in atomic context, including all OA report forwarding, which wasn't really necessary in our case and seems to make our locking requirements somewhat complex as we handled the interaction with the rest of the i915 driver. h](h)}(hfIt felt like our perf based PMU was making some technical compromises just for the sake of using perf:h]hfIt felt like our perf based PMU was making some technical compromises just for the sake of using perf:}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKhj%ubh)}(hXperf_event_open() requires events to either relate to a pid or a specific cpu core, while our device pmu related to neither. Events opened with a pid will be automatically enabled/disabled according to the scheduling of that process - so not appropriate for us. When an event is related to a cpu id, perf ensures pmu methods will be invoked via an inter process interrupt on that core. To avoid invasive changes our userspace opened OA perf events for a specific cpu. This was workable but it meant the majority of the OA driver ran in atomic context, including all OA report forwarding, which wasn't really necessary in our case and seems to make our locking requirements somewhat complex as we handled the interaction with the rest of the i915 driver.h]hXperf_event_open() requires events to either relate to a pid or a specific cpu core, while our device pmu related to neither. Events opened with a pid will be automatically enabled/disabled according to the scheduling of that process - so not appropriate for us. When an event is related to a cpu id, perf ensures pmu methods will be invoked via an inter process interrupt on that core. To avoid invasive changes our userspace opened OA perf events for a specific cpu. This was workable but it meant the majority of the OA driver ran in atomic context, including all OA report forwarding, which wasn’t really necessary in our case and seems to make our locking requirements somewhat complex as we handled the interaction with the rest of the i915 driver.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:413: ./drivers/gpu/drm/i915/i915_perf.chKhj%ubeh}(h]h ]h"]h$]h&]uh1j:hj$ubeh}(h]h ]h"]h$]h&]j;j;uh1j:hj$hKhhj$ubeh}(h]2issues-hit-with-first-prototype-based-on-core-perfah ]h"]2issues hit with first prototype based on core perfah$]h&]uh1hhjK$hhhNhNubeh}(h]comparison-with-core-perfah ]h"]comparison with core perfah$]h&]uh1hhj#hhhhhMubh)}(hhh](h)}(hi915 Driver Entry Pointsh]hi915 Driver Entry Points}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhhhMubh)}(hThis section covers the entrypoints exported outside of i915_perf.c to integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.h](hqThis section covers the entrypoints exported outside of i915_perf.c to integrate with drm/i915 and to handle the }(hj%hhhNhNubjc)}(h`DRM_I915_PERF_OPEN`h]hDRM_I915_PERF_OPEN}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j chj%ubh ioctl.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_perf_init (C function)c.i915_perf_inithNtauh1jhj%hhhNhNubj)}(hhh](j)}(h2int i915_perf_init (struct drm_i915_private *i915)h]j)}(h1int i915_perf_init(struct drm_i915_private *i915)h](jn)}(hinth]hint}(hj2&hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj.&hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjA&hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj.&hhhj@&hMubj)}(hi915_perf_inith]j)}(hi915_perf_inith]hi915_perf_init}(hjS&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO&ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj.&hhhj@&hMubj8)}(h(struct drm_i915_private *i915)h]j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hjo&hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjk&ubj )}(h h]h }(hj|&hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjk&ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj&modnameN classnameNjj)}j]j)}jjU&sbc.i915_perf_initasbuh1hhjk&ubj )}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjk&ubj)}(hjh]h*}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjk&ubj)}(hi915h]hi915}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjk&ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjg&ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj.&hhhj@&hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj*&hhhj@&hMubah}(h]j%&ah ](jjeh"]h$]h&]jj)jhuh1jhj@&hMhj'&hhubj)}(hhh]h)}(h)initialize i915-perf state on module bindh]h)initialize i915-perf state on module bind}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_perf.chMhj&hhubah}(h]h ]h"]h$]h&]uh1jhj'&hhhj@&hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj 'jj 'jjjuh1jhhhj%hNhNubj)}(hX***Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** Initializes i915-perf state without exposing anything to userspace. **Note** i915-perf initialization is split into an 'init' and 'register' phase with the i915_perf_register() exposing state to userspace.h](h)}(h**Parameters**h]j)}(hj'h]h Parameters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_perf.chMhj'ubj)}(hhh]j)}(h7``struct drm_i915_private *i915`` i915 device instance h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hj3'h]hstruct drm_i915_private *i915}(hj5'hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj1'ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_perf.chMhj-'ubj@)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hjL'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjH'hMhjI'ubah}(h]h ]h"]h$]h&]uh1j?hj-'ubeh}(h]h ]h"]h$]h&]uh1jhjH'hMhj*'ubah}(h]h ]h"]h$]h&]uh1jhj'ubh)}(h**Description**h]j)}(hjn'h]h Description}(hjp'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl'ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_perf.chMhj'ubh)}(hCInitializes i915-perf state without exposing anything to userspace.h]hCInitializes i915-perf state without exposing anything to userspace.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_perf.chMhj'ubh)}(h**Note**h]j)}(hj'h]hNote}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_perf.chMhj'ubh)}(hi915-perf initialization is split into an 'init' and 'register' phase with the i915_perf_register() exposing state to userspace.h]hi915-perf initialization is split into an ‘init’ and ‘register’ phase with the i915_perf_register() exposing state to userspace.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_perf.chMhj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_perf_fini (C function)c.i915_perf_finihNtauh1jhj%hhhNhNubj)}(hhh](j)}(h3void i915_perf_fini (struct drm_i915_private *i915)h]j)}(h2void i915_perf_fini(struct drm_i915_private *i915)h](jn)}(hvoidh]hvoid}(hj'hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj'hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:424: ./drivers/gpu/drm/i915/i915_perf.chMHubj )}(h h]h }(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj'hhhj'hMHubj)}(hi915_perf_finih]j)}(hi915_perf_finih]hi915_perf_fini}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj'hhhj'hMHubj8)}(h(struct drm_i915_private *i915)h]j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hj(hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj(ubj )}(h h]h }(hj$(hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj(ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj5(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2(ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj7(modnameN classnameNjj)}j]j)}jj'sbc.i915_perf_finiasbuh1hhj(ubj )}(h h]h }(hjU(hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj(ubj)}(hjh]h*}(hjc(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubj)}(hi915h]hi915}(hjp(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj(ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj'hhhj'hMHubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj'hhhj'hMHubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1jhj'hMHhj'hhubj)}(hhh]h)}(h Counter part to i915_perf_init()h]h Counter part to i915_perf_init()}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:424: ./drivers/gpu/drm/i915/i915_perf.chMHhj(hhubah}(h]h ]h"]h$]h&]uh1jhj'hhhj'hMHubeh}(h]h ](jfunctioneh"]h$]h&]jjjj(jj(jjjuh1jhhhj%hNhNubj)}(hH**Parameters** ``struct drm_i915_private *i915`` i915 device instanceh](h)}(h**Parameters**h]j)}(hj(h]h Parameters}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:424: ./drivers/gpu/drm/i915/i915_perf.chMLhj(ubj)}(hhh]j)}(h6``struct drm_i915_private *i915`` i915 device instanceh](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hj(h]hstruct drm_i915_private *i915}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj(ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:424: ./drivers/gpu/drm/i915/i915_perf.chMNhj(ubj@)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:424: ./drivers/gpu/drm/i915/i915_perf.chMIhj(ubah}(h]h ]h"]h$]h&]uh1j?hj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMNhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_perf_register (C function)c.i915_perf_registerhNtauh1jhj%hhhNhNubj)}(hhh](j)}(h7void i915_perf_register (struct drm_i915_private *i915)h]j)}(h6void i915_perf_register(struct drm_i915_private *i915)h](jn)}(hvoidh]hvoid}(hj5)hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj1)hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:426: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjD)hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj1)hhhjC)hMubj)}(hi915_perf_registerh]j)}(hi915_perf_registerh]hi915_perf_register}(hjV)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjR)ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj1)hhhjC)hMubj8)}(h(struct drm_i915_private *i915)h]j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hjr)hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjn)ubj )}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjn)ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj)modnameN classnameNjj)}j]j)}jjX)sbc.i915_perf_registerasbuh1hhjn)ubj )}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjn)ubj)}(hjh]h*}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn)ubj)}(hi915h]hi915}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn)ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjj)ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj1)hhhjC)hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj-)hhhjC)hMubah}(h]j()ah ](jjeh"]h$]h&]jj)jhuh1jhjC)hMhj*)hhubj)}(hhh]h)}(hexposes i915-perf to userspaceh]hexposes i915-perf to userspace}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:426: ./drivers/gpu/drm/i915/i915_perf.chMhj)hhubah}(h]h ]h"]h$]h&]uh1jhj*)hhhjC)hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj *jj *jjjuh1jhhhj%hNhNubj)}(h**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** In particular OA metric sets are advertised under a sysfs metrics/ directory allowing userspace to enumerate valid IDs that can be used to open an i915-perf stream.h](h)}(h**Parameters**h]j)}(hj*h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:426: ./drivers/gpu/drm/i915/i915_perf.chMhj*ubj)}(hhh]j)}(h7``struct drm_i915_private *i915`` i915 device instance h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hj6*h]hstruct drm_i915_private *i915}(hj8*hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj4*ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:426: ./drivers/gpu/drm/i915/i915_perf.chMhj0*ubj@)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hjO*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjK*hMhjL*ubah}(h]h ]h"]h$]h&]uh1j?hj0*ubeh}(h]h ]h"]h$]h&]uh1jhjK*hMhj-*ubah}(h]h ]h"]h$]h&]uh1jhj*ubh)}(h**Description**h]j)}(hjq*h]h Description}(hjs*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo*ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:426: ./drivers/gpu/drm/i915/i915_perf.chMhj*ubh)}(hIn particular OA metric sets are advertised under a sysfs metrics/ directory allowing userspace to enumerate valid IDs that can be used to open an i915-perf stream.h]hIn particular OA metric sets are advertised under a sysfs metrics/ directory allowing userspace to enumerate valid IDs that can be used to open an i915-perf stream.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:426: ./drivers/gpu/drm/i915/i915_perf.chMhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!i915_perf_unregister (C function)c.i915_perf_unregisterhNtauh1jhj%hhhNhNubj)}(hhh](j)}(h9void i915_perf_unregister (struct drm_i915_private *i915)h]j)}(h8void i915_perf_unregister(struct drm_i915_private *i915)h](jn)}(hvoidh]hvoid}(hj*hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj*hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:428: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj*hhhj*hMubj)}(hi915_perf_unregisterh]j)}(hi915_perf_unregisterh]hi915_perf_unregister}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj*hhhj*hMubj8)}(h(struct drm_i915_private *i915)h]j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hj*hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj*ubj )}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj*ubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj+modnameN classnameNjj)}j]j)}jj*sbc.i915_perf_unregisterasbuh1hhj*ubj )}(h h]h }(hj1+hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj*ubj)}(hjh]h*}(hj?+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj)}(hi915h]hi915}(hjL+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj*ubah}(h]h ]h"]h$]h&]j5j6uh1j7hj*hhhj*hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj*hhhj*hMubah}(h]j*ah ](jjeh"]h$]h&]jj)jhuh1jhj*hMhj*hhubj)}(hhh]h)}(hhide i915-perf from userspaceh]hhide i915-perf from userspace}(hjv+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:428: ./drivers/gpu/drm/i915/i915_perf.chMhjs+hhubah}(h]h ]h"]h$]h&]uh1jhj*hhhj*hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj+jj+jjjuh1jhhhj%hNhNubj)}(hX+**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** i915-perf state cleanup is split up into an 'unregister' and 'deinit' phase where the interface is first hidden from userspace by i915_perf_unregister() before cleaning up remaining state in i915_perf_fini().h](h)}(h**Parameters**h]j)}(hj+h]h Parameters}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:428: ./drivers/gpu/drm/i915/i915_perf.chMhj+ubj)}(hhh]j)}(h7``struct drm_i915_private *i915`` i915 device instance h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hj+h]hstruct drm_i915_private *i915}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj+ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:428: ./drivers/gpu/drm/i915/i915_perf.chMhj+ubj@)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hMhj+ubah}(h]h ]h"]h$]h&]uh1j?hj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubh)}(h**Description**h]j)}(hj+h]h Description}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:428: ./drivers/gpu/drm/i915/i915_perf.chMhj+ubh)}(hi915-perf state cleanup is split up into an 'unregister' and 'deinit' phase where the interface is first hidden from userspace by i915_perf_unregister() before cleaning up remaining state in i915_perf_fini().h]hi915-perf state cleanup is split up into an ‘unregister’ and ‘deinit’ phase where the interface is first hidden from userspace by i915_perf_unregister() before cleaning up remaining state in i915_perf_fini().}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:428: ./drivers/gpu/drm/i915/i915_perf.chMhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!i915_perf_open_ioctl (C function)c.i915_perf_open_ioctlhNtauh1jhj%hhhNhNubj)}(hhh](j)}(hTint i915_perf_open_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j)}(hSint i915_perf_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file)h](jn)}(hinth]hint}(hj7,hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj3,hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMbubj )}(h h]h }(hjF,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj3,hhhjE,hMbubj)}(hi915_perf_open_ioctlh]j)}(hi915_perf_open_ioctlh]hi915_perf_open_ioctl}(hjX,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjT,ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj3,hhhjE,hMbubj8)}(h;(struct drm_device *dev, void *data, struct drm_file *file)h](j>)}(hstruct drm_device *devh](jD)}(hjGh]hstruct}(hjt,hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjp,ubj )}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjp,ubh)}(hhh]j)}(h drm_deviceh]h drm_device}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj,modnameN classnameNjj)}j]j)}jjZ,sbc.i915_perf_open_ioctlasbuh1hhjp,ubj )}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjp,ubj)}(hjh]h*}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp,ubj)}(hdevh]hdev}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp,ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjl,ubj>)}(h void *datah](jn)}(hvoidh]hvoid}(hj,hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj,ubj )}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj,ubj)}(hjh]h*}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj)}(hdatah]hdata}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjl,ubj>)}(hstruct drm_file *fileh](jD)}(hjGh]hstruct}(hj(-hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj$-ubj )}(h h]h }(hj5-hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj$-ubh)}(hhh]j)}(hdrm_fileh]hdrm_file}(hjF-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjC-ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjH-modnameN classnameNjj)}j]j,c.i915_perf_open_ioctlasbuh1hhj$-ubj )}(h h]h }(hjd-hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj$-ubj)}(hjh]h*}(hjr-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$-ubj)}(hfileh]hfile}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$-ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjl,ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj3,hhhjE,hMbubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj/,hhhjE,hMbubah}(h]j*,ah ](jjeh"]h$]h&]jj)jhuh1jhjE,hMbhj,,hhubj)}(hhh]h)}(h-DRM ioctl() for userspace to open a stream FDh]h-DRM ioctl() for userspace to open a stream FD}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMbhj-hhubah}(h]h ]h"]h$]h&]uh1jhj,,hhhjE,hMbubeh}(h]h ](jfunctioneh"]h$]h&]jjjj-jj-jjjuh1jhhhj%hNhNubj)}(hX**Parameters** ``struct drm_device *dev`` drm device ``void *data`` ioctl data copied from userspace (unvalidated) ``struct drm_file *file`` drm file **Description** Validates the stream open parameters given by userspace including flags and an array of u64 key, value pair properties. Very little is assumed up front about the nature of the stream being opened (for instance we don't assume it's for periodic OA unit metrics). An i915-perf stream is expected to be a suitable interface for other forms of buffered data written by the GPU besides periodic OA metrics. Note we copy the properties from userspace outside of the i915 perf mutex to avoid an awkward lockdep with mmap_lock. Most of the implementation details are handled by i915_perf_open_ioctl_locked() after taking the :c:type:`gt->perf `.lock mutex for serializing with any non-file-operation driver hooks. **Return** A newly opened i915 Perf stream file descriptor or negative error code on failure.h](h)}(h**Parameters**h]j)}(hj-h]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMfhj-ubj)}(hhh](j)}(h&``struct drm_device *dev`` drm device h](j$)}(h``struct drm_device *dev``h]j*)}(hj-h]hstruct drm_device *dev}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj-ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMchj-ubj@)}(hhh]h)}(h drm deviceh]h drm device}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMchj.ubah}(h]h ]h"]h$]h&]uh1j?hj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hMchj-ubj)}(h>``void *data`` ioctl data copied from userspace (unvalidated) h](j$)}(h``void *data``h]j*)}(hj#.h]h void *data}(hj%.hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!.ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMdhj.ubj@)}(hhh]h)}(h.ioctl data copied from userspace (unvalidated)h]h.ioctl data copied from userspace (unvalidated)}(hj<.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8.hMdhj9.ubah}(h]h ]h"]h$]h&]uh1j?hj.ubeh}(h]h ]h"]h$]h&]uh1jhj8.hMdhj-ubj)}(h#``struct drm_file *file`` drm file h](j$)}(h``struct drm_file *file``h]j*)}(hj\.h]hstruct drm_file *file}(hj^.hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjZ.ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMehjV.ubj@)}(hhh]h)}(hdrm fileh]hdrm file}(hju.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjq.hMehjr.ubah}(h]h ]h"]h$]h&]uh1j?hjV.ubeh}(h]h ]h"]h$]h&]uh1jhjq.hMehj-ubeh}(h]h ]h"]h$]h&]uh1jhj-ubh)}(h**Description**h]j)}(hj.h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMghj-ubh)}(hwValidates the stream open parameters given by userspace including flags and an array of u64 key, value pair properties.h]hwValidates the stream open parameters given by userspace including flags and an array of u64 key, value pair properties.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMfhj-ubh)}(hXVery little is assumed up front about the nature of the stream being opened (for instance we don't assume it's for periodic OA unit metrics). An i915-perf stream is expected to be a suitable interface for other forms of buffered data written by the GPU besides periodic OA metrics.h]hXVery little is assumed up front about the nature of the stream being opened (for instance we don’t assume it’s for periodic OA unit metrics). An i915-perf stream is expected to be a suitable interface for other forms of buffered data written by the GPU besides periodic OA metrics.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMihj-ubh)}(huNote we copy the properties from userspace outside of the i915 perf mutex to avoid an awkward lockdep with mmap_lock.h]huNote we copy the properties from userspace outside of the i915 perf mutex to avoid an awkward lockdep with mmap_lock.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMnhj-ubh)}(hMost of the implementation details are handled by i915_perf_open_ioctl_locked() after taking the :c:type:`gt->perf `.lock mutex for serializing with any non-file-operation driver hooks.h](haMost of the implementation details are handled by i915_perf_open_ioctl_locked() after taking the }(hj.hhhNhNubh)}(h:c:type:`gt->perf `h]j*)}(hj.h]hgt->perf}(hj.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hj.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjgtuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMqhj.ubhE.lock mutex for serializing with any non-file-operation driver hooks.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/hMqhj-ubh)}(h **Return**h]j)}(hj/h]hReturn}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj /ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMuhj-ubh)}(hRA newly opened i915 Perf stream file descriptor or negative error code on failure.h]hRA newly opened i915 Perf stream file descriptor or negative error code on failure.}(hj$/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:430: ./drivers/gpu/drm/i915/i915_perf.chMvhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_perf_release (C function)c.i915_perf_releasehNtauh1jhj%hhhNhNubj)}(hhh](j)}(h>int i915_perf_release (struct inode *inode, struct file *file)h]j)}(h=int i915_perf_release(struct inode *inode, struct file *file)h](jn)}(hinth]hint}(hjS/hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjO/hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjb/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjO/hhhja/hMubj)}(hi915_perf_releaseh]j)}(hi915_perf_releaseh]hi915_perf_release}(hjt/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp/ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjO/hhhja/hMubj8)}(h((struct inode *inode, struct file *file)h](j>)}(hstruct inode *inodeh](jD)}(hjGh]hstruct}(hj/hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj/ubj )}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/ubh)}(hhh]j)}(hinodeh]hinode}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj/modnameN classnameNjj)}j]j)}jjv/sbc.i915_perf_releaseasbuh1hhj/ubj )}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/ubj)}(hjh]h*}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj)}(hinodeh]hinode}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj/ubj>)}(hstruct file *fileh](jD)}(hjGh]hstruct}(hj0hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj/ubj )}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/ubh)}(hhh]j)}(hfileh]hfile}(hj 0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj"0modnameN classnameNjj)}j]j/c.i915_perf_releaseasbuh1hhj/ubj )}(h h]h }(hj>0hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/ubj)}(hjh]h*}(hjL0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj)}(hfileh]hfile}(hjY0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj/ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjO/hhhja/hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjK/hhhja/hMubah}(h]jF/ah ](jjeh"]h$]h&]jj)jhuh1jhja/hMhjH/hhubj)}(hhh]h)}(h*handles userspace close() of a stream fileh]h*handles userspace close() of a stream file}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0hhubah}(h]h ]h"]h$]h&]uh1jhjH/hhhja/hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj0jj0jjjuh1jhhhj%hNhNubj)}(hXQ**Parameters** ``struct inode *inode`` anonymous inode associated with file ``struct file *file`` An i915 perf stream file **Description** Cleans up any resources associated with an open i915 perf stream file. NB: close() can't really fail from the userspace point of view. **Return** zero on success or a negative error code.h](h)}(h**Parameters**h]j)}(hj0h]h Parameters}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0ubj)}(hhh](j)}(h=``struct inode *inode`` anonymous inode associated with file h](j$)}(h``struct inode *inode``h]j*)}(hj0h]hstruct inode *inode}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj0ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0ubj@)}(hhh]h)}(h$anonymous inode associated with fileh]h$anonymous inode associated with file}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj0ubah}(h]h ]h"]h$]h&]uh1j?hj0ubeh}(h]h ]h"]h$]h&]uh1jhj0hMhj0ubj)}(h/``struct file *file`` An i915 perf stream file h](j$)}(h``struct file *file``h]j*)}(hj0h]hstruct file *file}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj0ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0ubj@)}(hhh]h)}(hAn i915 perf stream fileh]hAn i915 perf stream file}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj1ubah}(h]h ]h"]h$]h&]uh1j?hj0ubeh}(h]h ]h"]h$]h&]uh1jhj1hMhj0ubeh}(h]h ]h"]h$]h&]uh1jhj0ubh)}(h**Description**h]j)}(hj81h]h Description}(hj:1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj61ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0ubh)}(hFCleans up any resources associated with an open i915 perf stream file.h]hFCleans up any resources associated with an open i915 perf stream file.}(hjN1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0ubh)}(h?NB: close() can't really fail from the userspace point of view.h]hANB: close() can’t really fail from the userspace point of view.}(hj]1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0ubh)}(h **Return**h]j)}(hjn1h]hReturn}(hjp1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl1ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0ubh)}(h)zero on success or a negative error code.h]h)zero on success or a negative error code.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:432: ./drivers/gpu/drm/i915/i915_perf.chMhj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'i915_perf_add_config_ioctl (C function)c.i915_perf_add_config_ioctlhNtauh1jhj%hhhNhNubj)}(hhh](j)}(hZint i915_perf_add_config_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j)}(hYint i915_perf_add_config_ioctl(struct drm_device *dev, void *data, struct drm_file *file)h](jn)}(hinth]hint}(hj1hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj1hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj1hhhj1hMubj)}(hi915_perf_add_config_ioctlh]j)}(hi915_perf_add_config_ioctlh]hi915_perf_add_config_ioctl}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj1hhhj1hMubj8)}(h;(struct drm_device *dev, void *data, struct drm_file *file)h](j>)}(hstruct drm_device *devh](jD)}(hjGh]hstruct}(hj1hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj1ubj )}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj1ubh)}(hhh]j)}(h drm_deviceh]h drm_device}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 2ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj2modnameN classnameNjj)}j]j)}jj1sbc.i915_perf_add_config_ioctlasbuh1hhj1ubj )}(h h]h }(hj.2hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj1ubj)}(hjh]h*}(hj<2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj)}(hdevh]hdev}(hjI2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj1ubj>)}(h void *datah](jn)}(hvoidh]hvoid}(hjb2hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj^2ubj )}(h h]h }(hjp2hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^2ubj)}(hjh]h*}(hj~2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^2ubj)}(hdatah]hdata}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^2ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj1ubj>)}(hstruct drm_file *fileh](jD)}(hjGh]hstruct}(hj2hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj2ubj )}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2ubh)}(hhh]j)}(hdrm_fileh]hdrm_file}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj2modnameN classnameNjj)}j]j*2c.i915_perf_add_config_ioctlasbuh1hhj2ubj )}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2ubj)}(hjh]h*}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(hfileh]hfile}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj1ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj1hhhj1hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj1hhhj1hMubah}(h]j1ah ](jjeh"]h$]h&]jj)jhuh1jhj1hMhj1hhubj)}(hhh]h)}(h0DRM ioctl() for userspace to add a new OA configh]h0DRM ioctl() for userspace to add a new OA config}(hj%3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhj"3hhubah}(h]h ]h"]h$]h&]uh1jhj1hhhj1hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj=3jj=3jjjuh1jhhhj%hNhNubj)}(hX**Parameters** ``struct drm_device *dev`` drm device ``void *data`` ioctl data (pointer to struct drm_i915_perf_oa_config) copied from userspace (unvalidated) ``struct drm_file *file`` drm file **Description** Validates the submitted OA register to be saved into a new OA config that can then be used for programming the OA unit and its NOA network. **Return** A new allocated config number to be used with the perf open ioctl or a negative error code on failure.h](h)}(h**Parameters**h]j)}(hjG3h]h Parameters}(hjI3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE3ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhjA3ubj)}(hhh](j)}(h&``struct drm_device *dev`` drm device h](j$)}(h``struct drm_device *dev``h]j*)}(hjf3h]hstruct drm_device *dev}(hjh3hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjd3ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhj`3ubj@)}(hhh]h)}(h drm deviceh]h drm device}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{3hMhj|3ubah}(h]h ]h"]h$]h&]uh1j?hj`3ubeh}(h]h ]h"]h$]h&]uh1jhj{3hMhj]3ubj)}(hj``void *data`` ioctl data (pointer to struct drm_i915_perf_oa_config) copied from userspace (unvalidated) h](j$)}(h``void *data``h]j*)}(hj3h]h void *data}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj3ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhj3ubj@)}(hhh]h)}(hZioctl data (pointer to struct drm_i915_perf_oa_config) copied from userspace (unvalidated)h]hZioctl data (pointer to struct drm_i915_perf_oa_config) copied from userspace (unvalidated)}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhj3ubah}(h]h ]h"]h$]h&]uh1j?hj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhj]3ubj)}(h#``struct drm_file *file`` drm file h](j$)}(h``struct drm_file *file``h]j*)}(hj3h]hstruct drm_file *file}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj3ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhj3ubj@)}(hhh]h)}(hdrm fileh]hdrm file}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1j?hj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhj]3ubeh}(h]h ]h"]h$]h&]uh1jhjA3ubh)}(h**Description**h]j)}(hj4h]h Description}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhjA3ubh)}(hValidates the submitted OA register to be saved into a new OA config that can then be used for programming the OA unit and its NOA network.h]hValidates the submitted OA register to be saved into a new OA config that can then be used for programming the OA unit and its NOA network.}(hj*4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhjA3ubh)}(h **Return**h]j)}(hj;4h]hReturn}(hj=4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj94ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhjA3ubh)}(hfA new allocated config number to be used with the perf open ioctl or a negative error code on failure.h]hfA new allocated config number to be used with the perf open ioctl or a negative error code on failure.}(hjQ4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:434: ./drivers/gpu/drm/i915/i915_perf.chMhjA3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*i915_perf_remove_config_ioctl (C function)c.i915_perf_remove_config_ioctlhNtauh1jhj%hhhNhNubj)}(hhh](j)}(h]int i915_perf_remove_config_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j)}(h\int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, struct drm_file *file)h](jn)}(hinth]hint}(hj4hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj|4hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj|4hhhj4hMubj)}(hi915_perf_remove_config_ioctlh]j)}(hi915_perf_remove_config_ioctlh]hi915_perf_remove_config_ioctl}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj|4hhhj4hMubj8)}(h;(struct drm_device *dev, void *data, struct drm_file *file)h](j>)}(hstruct drm_device *devh](jD)}(hjGh]hstruct}(hj4hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj4ubj )}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj4ubh)}(hhh]j)}(h drm_deviceh]h drm_device}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj4modnameN classnameNjj)}j]j)}jj4sbc.i915_perf_remove_config_ioctlasbuh1hhj4ubj )}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj4ubj)}(hjh]h*}(hj 5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj)}(hdevh]hdev}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj4ubj>)}(h void *datah](jn)}(hvoidh]hvoid}(hj/5hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj+5ubj )}(h h]h }(hj=5hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj+5ubj)}(hjh]h*}(hjK5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+5ubj)}(hdatah]hdata}(hjX5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+5ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj4ubj>)}(hstruct drm_file *fileh](jD)}(hjGh]hstruct}(hjq5hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjm5ubj )}(h h]h }(hj~5hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjm5ubh)}(hhh]j)}(hdrm_fileh]hdrm_file}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj5modnameN classnameNjj)}j]j4c.i915_perf_remove_config_ioctlasbuh1hhjm5ubj )}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjm5ubj)}(hjh]h*}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm5ubj)}(hfileh]hfile}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm5ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj4ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj|4hhhj4hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjx4hhhj4hMubah}(h]js4ah ](jjeh"]h$]h&]jj)jhuh1jhj4hMhju4hhubj)}(hhh]h)}(h0DRM ioctl() for userspace to remove an OA configh]h0DRM ioctl() for userspace to remove an OA config}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhj5hhubah}(h]h ]h"]h$]h&]uh1jhju4hhhj4hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj 6jj 6jjjuh1jhhhj%hNhNubj)}(hX**Parameters** ``struct drm_device *dev`` drm device ``void *data`` ioctl data (pointer to u64 integer) copied from userspace ``struct drm_file *file`` drm file **Description** Configs can be removed while being used, the will stop appearing in sysfs and their content will be freed when the stream using the config is closed. **Return** 0 on success or a negative error code on failure.h](h)}(h**Parameters**h]j)}(hj6h]h Parameters}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhj6ubj)}(hhh](j)}(h&``struct drm_device *dev`` drm device h](j$)}(h``struct drm_device *dev``h]j*)}(hj36h]hstruct drm_device *dev}(hj56hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj16ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhj-6ubj@)}(hhh]h)}(h drm deviceh]h drm device}(hjL6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjH6hMhjI6ubah}(h]h ]h"]h$]h&]uh1j?hj-6ubeh}(h]h ]h"]h$]h&]uh1jhjH6hMhj*6ubj)}(hI``void *data`` ioctl data (pointer to u64 integer) copied from userspace h](j$)}(h``void *data``h]j*)}(hjl6h]h void *data}(hjn6hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjj6ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhjf6ubj@)}(hhh]h)}(h9ioctl data (pointer to u64 integer) copied from userspaceh]h9ioctl data (pointer to u64 integer) copied from userspace}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1j?hjf6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj*6ubj)}(h#``struct drm_file *file`` drm file h](j$)}(h``struct drm_file *file``h]j*)}(hj6h]hstruct drm_file *file}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj6ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhj6ubj@)}(hhh]h)}(hdrm fileh]hdrm file}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1j?hj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj*6ubeh}(h]h ]h"]h$]h&]uh1jhj6ubh)}(h**Description**h]j)}(hj6h]h Description}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhj6ubh)}(hConfigs can be removed while being used, the will stop appearing in sysfs and their content will be freed when the stream using the config is closed.h]hConfigs can be removed while being used, the will stop appearing in sysfs and their content will be freed when the stream using the config is closed.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhj6ubh)}(h **Return**h]j)}(hj7h]hReturn}(hj 7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhj6ubh)}(h10 on success or a negative error code on failure.h]h10 on success or a negative error code on failure.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:436: ./drivers/gpu/drm/i915/i915_perf.chMhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj%hhhNhNubeh}(h]i915-driver-entry-pointsah ]h"]i915 driver entry pointsah$]h&]uh1hhj#hhhhhMubh)}(hhh](h)}(hi915 Perf Streamh]hi915 Perf Stream}(hj>7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;7hhhhhMubh)}(hThis section covers the stream-semantics-agnostic structures and functions for representing an i915 perf stream FD and associated file operations.h]hThis section covers the stream-semantics-agnostic structures and functions for representing an i915 perf stream FD and associated file operations.}(hjL7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;7hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_perf_stream (C struct)c.i915_perf_streamhNtauh1jhj;7hhhNhNubj)}(hhh](j)}(hi915_perf_streamh]j)}(hstruct i915_perf_streamh](jD)}(hjGh]hstruct}(hjs7hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjo7hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKubj )}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjo7hhhj7hKubj)}(hi915_perf_streamh]j)}(hjm7h]hi915_perf_stream}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjo7hhhj7hKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjk7hhhj7hKubah}(h]jf7ah ](jjeh"]h$]h&]jj)jhuh1jhj7hKhjh7hhubj)}(hhh]h)}(h!state for a single open stream FDh]h!state for a single open stream FD}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj7hhubah}(h]h ]h"]h$]h&]uh1jhjh7hhhj7hKubeh}(h]h ](jstructeh"]h$]h&]jjjj7jj7jjjuh1jhhhj;7hNhNubj)}(hX**Definition**:: struct i915_perf_stream { struct i915_perf *perf; struct intel_uncore *uncore; struct intel_engine_cs *engine; struct mutex lock; u32 sample_flags; int sample_size; struct i915_gem_context *ctx; bool enabled; bool hold_preemption; const struct i915_perf_stream_ops *ops; struct i915_oa_config *oa_config; struct llist_head oa_config_bos; struct intel_context *pinned_ctx; u32 specific_ctx_id; u32 specific_ctx_id_mask; struct hrtimer poll_check_timer; wait_queue_head_t poll_wq; bool pollin; bool periodic; int period_exponent; struct { const struct i915_oa_format *format; struct i915_vma *vma; u8 *vaddr; u32 last_ctx_id; spinlock_t ptr_lock; u32 head; u32 tail; } oa_buffer; struct i915_vma *noa_wait; u64 poll_oa_period; }; **Members** ``perf`` i915_perf backpointer ``uncore`` mmio access path ``engine`` Engine associated with this performance stream. ``lock`` Lock associated with operations on stream ``sample_flags`` Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` properties given when opening a stream, representing the contents of a single sample as read() by userspace. ``sample_size`` Considering the configured contents of a sample combined with the required header size, this is the total size of a single sample record. ``ctx`` ``NULL`` if measuring system-wide across all contexts or a specific context that is being monitored. ``enabled`` Whether the stream is currently enabled, considering whether the stream was opened in a disabled state and based on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. ``hold_preemption`` Whether preemption is put on hold for command submissions done on the **ctx**. This is useful for some drivers that cannot easily post process the OA buffer context to subtract delta of performance counters not associated with **ctx**. ``ops`` The callbacks providing the implementation of this specific type of configured stream. ``oa_config`` The OA configuration used by the stream. ``oa_config_bos`` A list of struct i915_oa_config_bo allocated lazily each time **oa_config** changes. ``pinned_ctx`` The OA context specific information. ``specific_ctx_id`` The id of the specific context. ``specific_ctx_id_mask`` The mask used to masking specific_ctx_id bits. ``poll_check_timer`` High resolution timer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()). ``poll_wq`` The wait queue that hrtimer callback wakes when it sees data ready to read in the circular OA buffer. ``pollin`` Whether there is data available to read. ``periodic`` Whether periodic sampling is currently enabled. ``period_exponent`` The OA unit sampling frequency is derived from this. ``oa_buffer`` State of the OA buffer. ``oa_buffer.ptr_lock`` Locks reads and writes to all head/tail state Consider: the head and tail pointer state needs to be read consistently from a hrtimer callback (atomic context) and read() fop (user context) with tail pointer updates happening in atomic context and head updates in user context and the (unlikely) possibility of read() errors needing to reset all head/tail state. Note: Contention/performance aren't currently a significant concern here considering the relatively low frequency of hrtimer callbacks (5ms period) and that reads typically only happen in response to a hrtimer event and likely complete before the next callback. Note: This lock is not held *while* reading and copying data to userspace so the value of head observed in htrimer callbacks won't represent any partial consumption of data. ``oa_buffer.head`` Although we can always read back the head pointer register, we prefer to avoid trusting the HW state, just to avoid any risk that some hardware condition could * somehow bump the head pointer unpredictably and cause us to forward the wrong OA buffer data to userspace. ``oa_buffer.tail`` The last verified tail that can be read by userspace. ``noa_wait`` A batch buffer doing a wait on the GPU for the NOA logic to be reprogrammed. ``poll_oa_period`` The period in nanoseconds at which the OA buffer should be checked for available data.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubh:}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj7ubjA#)}(hXostruct i915_perf_stream { struct i915_perf *perf; struct intel_uncore *uncore; struct intel_engine_cs *engine; struct mutex lock; u32 sample_flags; int sample_size; struct i915_gem_context *ctx; bool enabled; bool hold_preemption; const struct i915_perf_stream_ops *ops; struct i915_oa_config *oa_config; struct llist_head oa_config_bos; struct intel_context *pinned_ctx; u32 specific_ctx_id; u32 specific_ctx_id_mask; struct hrtimer poll_check_timer; wait_queue_head_t poll_wq; bool pollin; bool periodic; int period_exponent; struct { const struct i915_oa_format *format; struct i915_vma *vma; u8 *vaddr; u32 last_ctx_id; spinlock_t ptr_lock; u32 head; u32 tail; } oa_buffer; struct i915_vma *noa_wait; u64 poll_oa_period; };h]hXostruct i915_perf_stream { struct i915_perf *perf; struct intel_uncore *uncore; struct intel_engine_cs *engine; struct mutex lock; u32 sample_flags; int sample_size; struct i915_gem_context *ctx; bool enabled; bool hold_preemption; const struct i915_perf_stream_ops *ops; struct i915_oa_config *oa_config; struct llist_head oa_config_bos; struct intel_context *pinned_ctx; u32 specific_ctx_id; u32 specific_ctx_id_mask; struct hrtimer poll_check_timer; wait_queue_head_t poll_wq; bool pollin; bool periodic; int period_exponent; struct { const struct i915_oa_format *format; struct i915_vma *vma; u8 *vaddr; u32 last_ctx_id; spinlock_t ptr_lock; u32 head; u32 tail; } oa_buffer; struct i915_vma *noa_wait; u64 poll_oa_period; };}hj7sbah}(h]h ]h"]h$]h&]j5j6uh1j@#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj7ubh)}(h **Members**h]j)}(hj8h]hMembers}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj7ubj)}(hhh](j)}(h``perf`` i915_perf backpointer h](j$)}(h``perf``h]j*)}(hj"8h]hperf}(hj$8hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj 8ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj8ubj@)}(hhh]h)}(hi915_perf backpointerh]hi915_perf backpointer}(hj;8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj78hKhj88ubah}(h]h ]h"]h$]h&]uh1j?hj8ubeh}(h]h ]h"]h$]h&]uh1jhj78hKhj8ubj)}(h``uncore`` mmio access path h](j$)}(h ``uncore``h]j*)}(hj[8h]huncore}(hj]8hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjY8ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhjU8ubj@)}(hhh]h)}(hmmio access pathh]hmmio access path}(hjt8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp8hKhjq8ubah}(h]h ]h"]h$]h&]uh1j?hjU8ubeh}(h]h ]h"]h$]h&]uh1jhjp8hKhj8ubj)}(h;``engine`` Engine associated with this performance stream. h](j$)}(h ``engine``h]j*)}(hj8h]hengine}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj8ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj8ubj@)}(hhh]h)}(h/Engine associated with this performance stream.h]h/Engine associated with this performance stream.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hKhj8ubah}(h]h ]h"]h$]h&]uh1j?hj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hKhj8ubj)}(h3``lock`` Lock associated with operations on stream h](j$)}(h``lock``h]j*)}(hj8h]hlock}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj8ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj8ubj@)}(hhh]h)}(h)Lock associated with operations on streamh]h)Lock associated with operations on stream}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hKhj8ubah}(h]h ]h"]h$]h&]uh1j?hj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hKhj8ubj)}(h``sample_flags`` Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` properties given when opening a stream, representing the contents of a single sample as read() by userspace. h](j$)}(h``sample_flags``h]j*)}(hj9h]h sample_flags}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj9ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj9ubj@)}(hhh]h)}(hFlags representing the `DRM_I915_PERF_PROP_SAMPLE_*` properties given when opening a stream, representing the contents of a single sample as read() by userspace.h](hFlags representing the }(hj9hhhNhNubjc)}(h`DRM_I915_PERF_PROP_SAMPLE_*`h]hDRM_I915_PERF_PROP_SAMPLE_*}(hj'9hhhNhNubah}(h]h ]h"]h$]h&]uh1j chj9ubhm properties given when opening a stream, representing the contents of a single sample as read() by userspace.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj9ubah}(h]h ]h"]h$]h&]uh1j?hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hKhj8ubj)}(h``sample_size`` Considering the configured contents of a sample combined with the required header size, this is the total size of a single sample record. h](j$)}(h``sample_size``h]j*)}(hjR9h]h sample_size}(hjT9hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjP9ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhjL9ubj@)}(hhh]h)}(hConsidering the configured contents of a sample combined with the required header size, this is the total size of a single sample record.h]hConsidering the configured contents of a sample combined with the required header size, this is the total size of a single sample record.}(hjk9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhjh9ubah}(h]h ]h"]h$]h&]uh1j?hjL9ubeh}(h]h ]h"]h$]h&]uh1jhjg9hKhj8ubj)}(hm``ctx`` ``NULL`` if measuring system-wide across all contexts or a specific context that is being monitored. h](j$)}(h``ctx``h]j*)}(hj9h]hctx}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj9ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj9ubj@)}(hhh]h)}(hd``NULL`` if measuring system-wide across all contexts or a specific context that is being monitored.h](j*)}(h``NULL``h]hNULL}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj9ubh\ if measuring system-wide across all contexts or a specific context that is being monitored.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj9ubah}(h]h ]h"]h$]h&]uh1j?hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hKhj8ubj)}(h``enabled`` Whether the stream is currently enabled, considering whether the stream was opened in a disabled state and based on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. h](j$)}(h ``enabled``h]j*)}(hj9h]henabled}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj9ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj9ubj@)}(hhh]h)}(hWhether the stream is currently enabled, considering whether the stream was opened in a disabled state and based on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.h](htWhether the stream is currently enabled, considering whether the stream was opened in a disabled state and based on }(hj9hhhNhNubjc)}(h`I915_PERF_IOCTL_ENABLE`h]hI915_PERF_IOCTL_ENABLE}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j chj9ubh and }(hj9hhhNhNubjc)}(h`I915_PERF_IOCTL_DISABLE`h]hI915_PERF_IOCTL_DISABLE}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j chj9ubh calls.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj9ubah}(h]h ]h"]h$]h&]uh1j?hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hKhj8ubj)}(hX``hold_preemption`` Whether preemption is put on hold for command submissions done on the **ctx**. This is useful for some drivers that cannot easily post process the OA buffer context to subtract delta of performance counters not associated with **ctx**. h](j$)}(h``hold_preemption``h]j*)}(hj2:h]hhold_preemption}(hj4:hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj0:ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj,:ubj@)}(hhh]h)}(hWhether preemption is put on hold for command submissions done on the **ctx**. This is useful for some drivers that cannot easily post process the OA buffer context to subtract delta of performance counters not associated with **ctx**.h](hFWhether preemption is put on hold for command submissions done on the }(hjK:hhhNhNubj)}(h**ctx**h]hctx}(hjS:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK:ubh. This is useful for some drivers that cannot easily post process the OA buffer context to subtract delta of performance counters not associated with }(hjK:hhhNhNubj)}(h**ctx**h]hctx}(hje:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK:ubh.}(hjK:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhjH:ubah}(h]h ]h"]h$]h&]uh1j?hj,:ubeh}(h]h ]h"]h$]h&]uh1jhjG:hKhj8ubj)}(h_``ops`` The callbacks providing the implementation of this specific type of configured stream. h](j$)}(h``ops``h]j*)}(hj:h]hops}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj:ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj:ubj@)}(hhh]h)}(hVThe callbacks providing the implementation of this specific type of configured stream.h]hVThe callbacks providing the implementation of this specific type of configured stream.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj:ubah}(h]h ]h"]h$]h&]uh1j?hj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hKhj8ubj)}(h7``oa_config`` The OA configuration used by the stream. h](j$)}(h ``oa_config``h]j*)}(hj:h]h oa_config}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj:ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj:ubj@)}(hhh]h)}(h(The OA configuration used by the stream.h]h(The OA configuration used by the stream.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj:ubah}(h]h ]h"]h$]h&]uh1j?hj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hKhj8ubj)}(hg``oa_config_bos`` A list of struct i915_oa_config_bo allocated lazily each time **oa_config** changes. h](j$)}(h``oa_config_bos``h]j*)}(hj;h]h oa_config_bos}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj;ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj:ubj@)}(hhh]h)}(hTA list of struct i915_oa_config_bo allocated lazily each time **oa_config** changes.h](h>A list of struct i915_oa_config_bo allocated lazily each time }(hj;hhhNhNubj)}(h **oa_config**h]h oa_config}(hj$;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubh changes.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj;ubah}(h]h ]h"]h$]h&]uh1j?hj:ubeh}(h]h ]h"]h$]h&]uh1jhj;hKhj8ubj)}(h4``pinned_ctx`` The OA context specific information. h](j$)}(h``pinned_ctx``h]j*)}(hjO;h]h pinned_ctx}(hjQ;hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjM;ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhjI;ubj@)}(hhh]h)}(h$The OA context specific information.h]h$The OA context specific information.}(hjh;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjd;hKhje;ubah}(h]h ]h"]h$]h&]uh1j?hjI;ubeh}(h]h ]h"]h$]h&]uh1jhjd;hKhj8ubj)}(h4``specific_ctx_id`` The id of the specific context. h](j$)}(h``specific_ctx_id``h]j*)}(hj;h]hspecific_ctx_id}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj;ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj;ubj@)}(hhh]h)}(hThe id of the specific context.h]hThe id of the specific context.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hKhj;ubah}(h]h ]h"]h$]h&]uh1j?hj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hKhj8ubj)}(hH``specific_ctx_id_mask`` The mask used to masking specific_ctx_id bits. h](j$)}(h``specific_ctx_id_mask``h]j*)}(hj;h]hspecific_ctx_id_mask}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj;ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj;ubj@)}(hhh]h)}(h.The mask used to masking specific_ctx_id bits.h]h.The mask used to masking specific_ctx_id bits.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hKhj;ubah}(h]h ]h"]h$]h&]uh1j?hj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hKhj8ubj)}(h``poll_check_timer`` High resolution timer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()). h](j$)}(h``poll_check_timer``h]j*)}(hj;h]hpoll_check_timer}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj;ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj;ubj@)}(hhh]h)}(hHigh resolution timer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()).h]hHigh resolution timer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()).}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj<ubah}(h]h ]h"]h$]h&]uh1j?hj;ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj8ubj)}(hr``poll_wq`` The wait queue that hrtimer callback wakes when it sees data ready to read in the circular OA buffer. h](j$)}(h ``poll_wq``h]j*)}(hj4<h]hpoll_wq}(hj6<hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj2<ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhM hj.<ubj@)}(hhh]h)}(heThe wait queue that hrtimer callback wakes when it sees data ready to read in the circular OA buffer.h]heThe wait queue that hrtimer callback wakes when it sees data ready to read in the circular OA buffer.}(hjM<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMhjJ<ubah}(h]h ]h"]h$]h&]uh1j?hj.<ubeh}(h]h ]h"]h$]h&]uh1jhjI<hM hj8ubj)}(h4``pollin`` Whether there is data available to read. h](j$)}(h ``pollin``h]j*)}(hjn<h]hpollin}(hjp<hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjl<ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMhjh<ubj@)}(hhh]h)}(h(Whether there is data available to read.h]h(Whether there is data available to read.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1j?hjh<ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj8ubj)}(h=``periodic`` Whether periodic sampling is currently enabled. h](j$)}(h ``periodic``h]j*)}(hj<h]hperiodic}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj<ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj<ubj@)}(hhh]h)}(h/Whether periodic sampling is currently enabled.h]h/Whether periodic sampling is currently enabled.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1j?hj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj8ubj)}(hI``period_exponent`` The OA unit sampling frequency is derived from this. h](j$)}(h``period_exponent``h]j*)}(hj<h]hperiod_exponent}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj<ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj<ubj@)}(hhh]h)}(h4The OA unit sampling frequency is derived from this.h]h4The OA unit sampling frequency is derived from this.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1j?hj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj8ubj)}(h&``oa_buffer`` State of the OA buffer. h](j$)}(h ``oa_buffer``h]j*)}(hj=h]h oa_buffer}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj=ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj=ubj@)}(hhh]h)}(hState of the OA buffer.h]hState of the OA buffer.}(hj2=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.=hMhj/=ubah}(h]h ]h"]h$]h&]uh1j?hj=ubeh}(h]h ]h"]h$]h&]uh1jhj.=hMhj8ubj)}(hX8``oa_buffer.ptr_lock`` Locks reads and writes to all head/tail state Consider: the head and tail pointer state needs to be read consistently from a hrtimer callback (atomic context) and read() fop (user context) with tail pointer updates happening in atomic context and head updates in user context and the (unlikely) possibility of read() errors needing to reset all head/tail state. Note: Contention/performance aren't currently a significant concern here considering the relatively low frequency of hrtimer callbacks (5ms period) and that reads typically only happen in response to a hrtimer event and likely complete before the next callback. Note: This lock is not held *while* reading and copying data to userspace so the value of head observed in htrimer callbacks won't represent any partial consumption of data. h](j$)}(h``oa_buffer.ptr_lock``h]j*)}(hjR=h]hoa_buffer.ptr_lock}(hjT=hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjP=ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhM8hjL=ubj@)}(hhh](h)}(h-Locks reads and writes to all head/tail stateh]h-Locks reads and writes to all head/tail state}(hjk=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhM&hjh=ubh)}(hX;Consider: the head and tail pointer state needs to be read consistently from a hrtimer callback (atomic context) and read() fop (user context) with tail pointer updates happening in atomic context and head updates in user context and the (unlikely) possibility of read() errors needing to reset all head/tail state.h]hX;Consider: the head and tail pointer state needs to be read consistently from a hrtimer callback (atomic context) and read() fop (user context) with tail pointer updates happening in atomic context and head updates in user context and the (unlikely) possibility of read() errors needing to reset all head/tail state.}(hjz=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhM)hjh=ubh)}(hXNote: Contention/performance aren't currently a significant concern here considering the relatively low frequency of hrtimer callbacks (5ms period) and that reads typically only happen in response to a hrtimer event and likely complete before the next callback.h]hXNote: Contention/performance aren’t currently a significant concern here considering the relatively low frequency of hrtimer callbacks (5ms period) and that reads typically only happen in response to a hrtimer event and likely complete before the next callback.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhM0hjh=ubh)}(hNote: This lock is not held *while* reading and copying data to userspace so the value of head observed in htrimer callbacks won't represent any partial consumption of data.h](hNote: This lock is not held }(hj=hhhNhNubj>)}(h*while*h]hwhile}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j>hj=ubh reading and copying data to userspace so the value of head observed in htrimer callbacks won’t represent any partial consumption of data.}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhM6hjh=ubeh}(h]h ]h"]h$]h&]uh1j?hjL=ubeh}(h]h ]h"]h$]h&]uh1jhjg=hM8hj8ubj)}(hX ``oa_buffer.head`` Although we can always read back the head pointer register, we prefer to avoid trusting the HW state, just to avoid any risk that some hardware condition could * somehow bump the head pointer unpredictably and cause us to forward the wrong OA buffer data to userspace. h](j$)}(h``oa_buffer.head``h]j*)}(hj=h]hoa_buffer.head}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj=ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMBhj=ubj@)}(hhh]h)}(hX Although we can always read back the head pointer register, we prefer to avoid trusting the HW state, just to avoid any risk that some hardware condition could * somehow bump the head pointer unpredictably and cause us to forward the wrong OA buffer data to userspace.h]hX Although we can always read back the head pointer register, we prefer to avoid trusting the HW state, just to avoid any risk that some hardware condition could * somehow bump the head pointer unpredictably and cause us to forward the wrong OA buffer data to userspace.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhM=hj=ubah}(h]h ]h"]h$]h&]uh1j?hj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMBhj8ubj)}(hI``oa_buffer.tail`` The last verified tail that can be read by userspace. h](j$)}(h``oa_buffer.tail``h]j*)}(hj>h]hoa_buffer.tail}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj>ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMHhj=ubj@)}(hhh]h)}(h5The last verified tail that can be read by userspace.h]h5The last verified tail that can be read by userspace.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMGhj>ubah}(h]h ]h"]h$]h&]uh1j?hj=ubeh}(h]h ]h"]h$]h&]uh1jhj>hMHhj8ubj)}(hZ``noa_wait`` A batch buffer doing a wait on the GPU for the NOA logic to be reprogrammed. h](j$)}(h ``noa_wait``h]j*)}(hj?>h]hnoa_wait}(hjA>hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj=>ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMOhj9>ubj@)}(hhh]h)}(hLA batch buffer doing a wait on the GPU for the NOA logic to be reprogrammed.h]hLA batch buffer doing a wait on the GPU for the NOA logic to be reprogrammed.}(hjX>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMNhjU>ubah}(h]h ]h"]h$]h&]uh1j?hj9>ubeh}(h]h ]h"]h$]h&]uh1jhjT>hMOhj8ubj)}(hi``poll_oa_period`` The period in nanoseconds at which the OA buffer should be checked for available data.h](j$)}(h``poll_oa_period``h]j*)}(hjy>h]hpoll_oa_period}(hj{>hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjw>ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:445: ./drivers/gpu/drm/i915/i915_perf_types.hhMThjs>ubj@)}(hhh]h)}(hVThe period in nanoseconds at which the OA buffer should be checked for available data.h]hVThe period in nanoseconds at which the OA buffer should be checked for available data.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMThj>ubah}(h]h ]h"]h$]h&]uh1j?hjs>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMThj8ubeh}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_perf_stream_ops (C struct)c.i915_perf_stream_opshNtauh1jhj;7hhhNhNubj)}(hhh](j)}(hi915_perf_stream_opsh]j)}(hstruct i915_perf_stream_opsh](jD)}(hjGh]hstruct}(hj>hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj>hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:447: ./drivers/gpu/drm/i915/i915_perf_types.hhKubj )}(h h]h }(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj>hhhj>hKubj)}(hi915_perf_stream_opsh]j)}(hj>h]hi915_perf_stream_ops}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj>hhhj>hKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj>hhhj>hKubah}(h]j>ah ](jjeh"]h$]h&]jj)jhuh1jhj>hKhj>hhubj)}(hhh]h)}(h)the OPs to support a specific stream typeh]h)the OPs to support a specific stream type}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:447: ./drivers/gpu/drm/i915/i915_perf_types.hhKehj?hhubah}(h]h ]h"]h$]h&]uh1jhj>hhhj>hKubeh}(h]h ](jstructeh"]h$]h&]jjjj,?jj,?jjjuh1jhhhj;7hNhNubj)}(hX**Definition**:: struct i915_perf_stream_ops { void (*enable)(struct i915_perf_stream *stream); void (*disable)(struct i915_perf_stream *stream); void (*poll_wait)(struct i915_perf_stream *stream, struct file *file, poll_table *wait); int (*wait_unlocked)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset); void (*destroy)(struct i915_perf_stream *stream); }; **Members** ``enable`` Enables the collection of HW samples, either in response to `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened without `I915_PERF_FLAG_DISABLED`. ``disable`` Disables the collection of HW samples, either in response to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying the stream. ``poll_wait`` Call poll_wait, passing a wait queue that will be woken once there is something ready to read() for the stream ``wait_unlocked`` For handling a blocking read, wait until there is something to ready to read() for the stream. E.g. wait on the same wait queue that would be passed to poll_wait(). ``read`` Copy buffered metrics as records to userspace **buf**: the userspace, destination buffer **count**: the number of bytes to copy, requested by userspace **offset**: zero at the start of the read, updated as the read proceeds, it represents how many bytes have been copied so far and the buffer offset for copying the next record. Copy as many buffered i915 perf samples and records for this stream to userspace as will fit in the given buffer. Only write complete records; returning -``ENOSPC`` if there isn't room for a complete record. Return any error condition that results in a short read such as -``ENOSPC`` or -``EFAULT``, even though these may be squashed before returning to userspace. ``destroy`` Cleanup any stream specific resources. The stream will always be disabled before this is called.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj8?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4?ubh:}(hj4?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:447: ./drivers/gpu/drm/i915/i915_perf_types.hhKihj0?ubjA#)}(hXstruct i915_perf_stream_ops { void (*enable)(struct i915_perf_stream *stream); void (*disable)(struct i915_perf_stream *stream); void (*poll_wait)(struct i915_perf_stream *stream, struct file *file, poll_table *wait); int (*wait_unlocked)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset); void (*destroy)(struct i915_perf_stream *stream); };h]hXstruct i915_perf_stream_ops { void (*enable)(struct i915_perf_stream *stream); void (*disable)(struct i915_perf_stream *stream); void (*poll_wait)(struct i915_perf_stream *stream, struct file *file, poll_table *wait); int (*wait_unlocked)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset); void (*destroy)(struct i915_perf_stream *stream); };}hjQ?sbah}(h]h ]h"]h$]h&]j5j6uh1j@#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:447: ./drivers/gpu/drm/i915/i915_perf_types.hhKkhj0?ubh)}(h **Members**h]j)}(hjb?h]hMembers}(hjd?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`?ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:447: ./drivers/gpu/drm/i915/i915_perf_types.hhKthj0?ubj)}(hhh](j)}(h``enable`` Enables the collection of HW samples, either in response to `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened without `I915_PERF_FLAG_DISABLED`. h](j$)}(h ``enable``h]j*)}(hj?h]henable}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj?ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:447: ./drivers/gpu/drm/i915/i915_perf_types.hhKlhj{?ubj@)}(hhh]h)}(hEnables the collection of HW samples, either in response to `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened without `I915_PERF_FLAG_DISABLED`.h](h)}(hstruct i915_perf *perfh](jD)}(hjGh]hstruct}(hjBhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjBubj )}(h h]h }(hj%BhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBubh)}(hhh]j)}(h i915_perfh]h i915_perf}(hj6BhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3Bubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj8BmodnameN classnameNjj)}j]j)}jjAsbc.read_properties_unlockedasbuh1hhjBubj )}(h h]h }(hjVBhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBubj)}(hjh]h*}(hjdBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(hperfh]hperf}(hjqBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjBubj>)}(hu64 __user *upropsh](h)}(hhh]j)}(hu64h]hu64}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjBmodnameN classnameNjj)}j]jRBc.read_properties_unlockedasbuh1hhjBubj )}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBubh__user}(hjBhhhNhNubj )}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBubj)}(hjh]h*}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj)}(hupropsh]huprops}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjBubj>)}(h u32 n_propsh](h)}(hhh]j)}(hu32h]hu32}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjBmodnameN classnameNjj)}j]jRBc.read_properties_unlockedasbuh1hhjBubj )}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBubj)}(hn_propsh]hn_props}(hj ChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjBubj>)}(h"struct perf_open_properties *propsh](jD)}(hjGh]hstruct}(hj9ChhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj5Cubj )}(h h]h }(hjFChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj5Cubh)}(hhh]j)}(hperf_open_propertiesh]hperf_open_properties}(hjWChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTCubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjYCmodnameN classnameNjj)}j]jRBc.read_properties_unlockedasbuh1hhj5Cubj )}(h h]h }(hjuChhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj5Cubj)}(hjh]h*}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5Cubj)}(hpropsh]hprops}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5Cubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjBubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjAhhhjAhMpubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjAhhhjAhMpubah}(h]jAah ](jjeh"]h$]h&]jj)jhuh1jhjAhMphjAhhubj)}(hhh]h)}(h0validate + copy userspace stream open propertiesh]h0validate + copy userspace stream open properties}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMphjChhubah}(h]h ]h"]h$]h&]uh1jhjAhhhjAhMpubeh}(h]h ](jfunctioneh"]h$]h&]jjjjCjjCjjjuh1jhhhj;7hNhNubj)}(hX**Parameters** ``struct i915_perf *perf`` i915 perf instance ``u64 __user *uprops`` The array of u64 key value pairs given by userspace ``u32 n_props`` The number of key value pairs expected in **uprops** ``struct perf_open_properties *props`` The stream configuration built up while validating properties **Description** Note this function only validates properties in isolation it doesn't validate that the combination of properties makes sense or that all properties necessary for a particular kind of stream have been set. Note that there currently aren't any ordering requirements for properties so we shouldn't validate or assume anything about ordering here. This doesn't rule out defining new properties with ordering requirements in the future.h](h)}(h**Parameters**h]j)}(hjCh]h Parameters}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMthjCubj)}(hhh](j)}(h.``struct i915_perf *perf`` i915 perf instance h](j$)}(h``struct i915_perf *perf``h]j*)}(hjCh]hstruct i915_perf *perf}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjCubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMqhjCubj@)}(hhh]h)}(hi915 perf instanceh]hi915 perf instance}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMqhjDubah}(h]h ]h"]h$]h&]uh1j?hjCubeh}(h]h ]h"]h$]h&]uh1jhjDhMqhjCubj)}(hK``u64 __user *uprops`` The array of u64 key value pairs given by userspace h](j$)}(h``u64 __user *uprops``h]j*)}(hj4Dh]hu64 __user *uprops}(hj6DhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj2Dubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMrhj.Dubj@)}(hhh]h)}(h3The array of u64 key value pairs given by userspaceh]h3The array of u64 key value pairs given by userspace}(hjMDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIDhMrhjJDubah}(h]h ]h"]h$]h&]uh1j?hj.Dubeh}(h]h ]h"]h$]h&]uh1jhjIDhMrhjCubj)}(hE``u32 n_props`` The number of key value pairs expected in **uprops** h](j$)}(h``u32 n_props``h]j*)}(hjmDh]h u32 n_props}(hjoDhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjkDubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMshjgDubj@)}(hhh]h)}(h4The number of key value pairs expected in **uprops**h](h*The number of key value pairs expected in }(hjDhhhNhNubj)}(h **uprops**h]huprops}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1hhjDhMshjDubah}(h]h ]h"]h$]h&]uh1j?hjgDubeh}(h]h ]h"]h$]h&]uh1jhjDhMshjCubj)}(he``struct perf_open_properties *props`` The stream configuration built up while validating properties h](j$)}(h&``struct perf_open_properties *props``h]j*)}(hjDh]h"struct perf_open_properties *props}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjDubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMthjDubj@)}(hhh]h)}(h=The stream configuration built up while validating propertiesh]h=The stream configuration built up while validating properties}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMthjDubah}(h]h ]h"]h$]h&]uh1j?hjDubeh}(h]h ]h"]h$]h&]uh1jhjDhMthjCubeh}(h]h ]h"]h$]h&]uh1jhjCubh)}(h**Description**h]j)}(hjDh]h Description}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMvhjCubh)}(hNote this function only validates properties in isolation it doesn't validate that the combination of properties makes sense or that all properties necessary for a particular kind of stream have been set.h]hNote this function only validates properties in isolation it doesn’t validate that the combination of properties makes sense or that all properties necessary for a particular kind of stream have been set.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMuhjCubh)}(hNote that there currently aren't any ordering requirements for properties so we shouldn't validate or assume anything about ordering here. This doesn't rule out defining new properties with ordering requirements in the future.h]hNote that there currently aren’t any ordering requirements for properties so we shouldn’t validate or assume anything about ordering here. This doesn’t rule out defining new properties with ordering requirements in the future.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_perf.chMyhjCubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(i915_perf_open_ioctl_locked (C function)c.i915_perf_open_ioctl_lockedhNtauh1jhj;7hhhNhNubj)}(hhh](j)}(hint i915_perf_open_ioctl_locked (struct i915_perf *perf, struct drm_i915_perf_open_param *param, struct perf_open_properties *props, struct drm_file *file)h]j)}(hint i915_perf_open_ioctl_locked(struct i915_perf *perf, struct drm_i915_perf_open_param *param, struct perf_open_properties *props, struct drm_file *file)h](jn)}(hinth]hint}(hjCEhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj?EhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjREhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj?EhhhjQEhMubj)}(hi915_perf_open_ioctl_lockedh]j)}(hi915_perf_open_ioctl_lockedh]hi915_perf_open_ioctl_locked}(hjdEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`Eubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj?EhhhjQEhMubj8)}(h{(struct i915_perf *perf, struct drm_i915_perf_open_param *param, struct perf_open_properties *props, struct drm_file *file)h](j>)}(hstruct i915_perf *perfh](jD)}(hjGh]hstruct}(hjEhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj|Eubj )}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj|Eubh)}(hhh]j)}(h i915_perfh]h i915_perf}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjEmodnameN classnameNjj)}j]j)}jjfEsbc.i915_perf_open_ioctl_lockedasbuh1hhj|Eubj )}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj|Eubj)}(hjh]h*}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|Eubj)}(hperfh]hperf}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|Eubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjxEubj>)}(h&struct drm_i915_perf_open_param *paramh](jD)}(hjGh]hstruct}(hjEhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjEubj )}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjEubh)}(hhh]j)}(hdrm_i915_perf_open_paramh]hdrm_i915_perf_open_param}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Fubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjFmodnameN classnameNjj)}j]jEc.i915_perf_open_ioctl_lockedasbuh1hhjEubj )}(h h]h }(hj.FhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjEubj)}(hjh]h*}(hj)}(h"struct perf_open_properties *propsh](jD)}(hjGh]hstruct}(hjbFhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj^Fubj )}(h h]h }(hjoFhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^Fubh)}(hhh]j)}(hperf_open_propertiesh]hperf_open_properties}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}Fubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjFmodnameN classnameNjj)}j]jEc.i915_perf_open_ioctl_lockedasbuh1hhj^Fubj )}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^Fubj)}(hjh]h*}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^Fubj)}(hpropsh]hprops}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^Fubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjxEubj>)}(hstruct drm_file *fileh](jD)}(hjGh]hstruct}(hjFhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjFubj )}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjFubh)}(hhh]j)}(hdrm_fileh]hdrm_file}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjFmodnameN classnameNjj)}j]jEc.i915_perf_open_ioctl_lockedasbuh1hhjFubj )}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjFubj)}(hjh]h*}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubj)}(hfileh]hfile}(hj)GhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjxEubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj?EhhhjQEhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj;EhhhjQEhMubah}(h]j6Eah ](jjeh"]h$]h&]jj)jhuh1jhjQEhMhj8Ehhubj)}(hhh]h)}(h-DRM ioctl() for userspace to open a stream FDh]h-DRM ioctl() for userspace to open a stream FD}(hjSGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjPGhhubah}(h]h ]h"]h$]h&]uh1jhj8EhhhjQEhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjkGjjkGjjjuh1jhhhj;7hNhNubj)}(hX **Parameters** ``struct i915_perf *perf`` i915 perf instance ``struct drm_i915_perf_open_param *param`` The open parameters passed to 'DRM_I915_PERF_OPEN` ``struct perf_open_properties *props`` individually validated u64 property value pairs ``struct drm_file *file`` drm file **Description** See i915_perf_ioctl_open() for interface details. Implements further stream config validation and stream initialization on behalf of i915_perf_open_ioctl() with the :c:type:`gt->perf `.lock mutex taken to serialize with any non-file-operation driver hooks. **Note** at this point the **props** have only been validated in isolation and it's still necessary to validate that the combination of properties makes sense. In the case where userspace is interested in OA unit metrics then further config validation and stream initialization details will be handled by i915_oa_stream_init(). The code here should only validate config state that will be relevant to all stream types / backends. **Return** zero on success or a negative error code.h](h)}(h**Parameters**h]j)}(hjuGh]h Parameters}(hjwGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsGubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjoGubj)}(hhh](j)}(h.``struct i915_perf *perf`` i915 perf instance h](j$)}(h``struct i915_perf *perf``h]j*)}(hjGh]hstruct i915_perf *perf}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjGubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjGubj@)}(hhh]h)}(hi915 perf instanceh]hi915 perf instance}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjGubah}(h]h ]h"]h$]h&]uh1j?hjGubeh}(h]h ]h"]h$]h&]uh1jhjGhMhjGubj)}(h^``struct drm_i915_perf_open_param *param`` The open parameters passed to 'DRM_I915_PERF_OPEN` h](j$)}(h*``struct drm_i915_perf_open_param *param``h]j*)}(hjGh]h&struct drm_i915_perf_open_param *param}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjGubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjGubj@)}(hhh]h)}(h2The open parameters passed to 'DRM_I915_PERF_OPEN`h]h4The open parameters passed to ‘DRM_I915_PERF_OPEN`}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjGubah}(h]h ]h"]h$]h&]uh1j?hjGubeh}(h]h ]h"]h$]h&]uh1jhjGhMhjGubj)}(hW``struct perf_open_properties *props`` individually validated u64 property value pairs h](j$)}(h&``struct perf_open_properties *props``h]j*)}(hjHh]h"struct perf_open_properties *props}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjHubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjHubj@)}(hhh]h)}(h/individually validated u64 property value pairsh]h/individually validated u64 property value pairs}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMhjHubah}(h]h ]h"]h$]h&]uh1j?hjHubeh}(h]h ]h"]h$]h&]uh1jhjHhMhjGubj)}(h#``struct drm_file *file`` drm file h](j$)}(h``struct drm_file *file``h]j*)}(hj?Hh]hstruct drm_file *file}(hjAHhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj=Hubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhj9Hubj@)}(hhh]h)}(hdrm fileh]hdrm file}(hjXHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTHhMhjUHubah}(h]h ]h"]h$]h&]uh1j?hj9Hubeh}(h]h ]h"]h$]h&]uh1jhjTHhMhjGubeh}(h]h ]h"]h$]h&]uh1jhjoGubh)}(h**Description**h]j)}(hjzHh]h Description}(hj|HhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxHubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjoGubh)}(h1See i915_perf_ioctl_open() for interface details.h]h1See i915_perf_ioctl_open() for interface details.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjoGubh)}(hImplements further stream config validation and stream initialization on behalf of i915_perf_open_ioctl() with the :c:type:`gt->perf `.lock mutex taken to serialize with any non-file-operation driver hooks.h](hsImplements further stream config validation and stream initialization on behalf of i915_perf_open_ioctl() with the }(hjHhhhNhNubh)}(h:c:type:`gt->perf `h]j*)}(hjHh]hgt->perf}(hjHhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjHubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjgtuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjHubhH.lock mutex taken to serialize with any non-file-operation driver hooks.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjHhMhjoGubh)}(h**Note**h]j)}(hjHh]hNote}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjoGubh)}(hat this point the **props** have only been validated in isolation and it's still necessary to validate that the combination of properties makes sense.h](hat this point the }(hjHhhhNhNubj)}(h **props**h]hprops}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh} have only been validated in isolation and it’s still necessary to validate that the combination of properties makes sense.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjoGubh)}(hX In the case where userspace is interested in OA unit metrics then further config validation and stream initialization details will be handled by i915_oa_stream_init(). The code here should only validate config state that will be relevant to all stream types / backends.h]hX In the case where userspace is interested in OA unit metrics then further config validation and stream initialization details will be handled by i915_oa_stream_init(). The code here should only validate config state that will be relevant to all stream types / backends.}(hj IhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjoGubh)}(h **Return**h]j)}(hjIh]hReturn}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjoGubh)}(h)zero on success or a negative error code.h]h)zero on success or a negative error code.}(hj1IhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:452: ./drivers/gpu/drm/i915/i915_perf.chMhjoGubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%i915_perf_destroy_locked (C function)c.i915_perf_destroy_lockedhNtauh1jhj;7hhhNhNubj)}(hhh](j)}(h?void i915_perf_destroy_locked (struct i915_perf_stream *stream)h]j)}(h>void i915_perf_destroy_locked(struct i915_perf_stream *stream)h](jn)}(hvoidh]hvoid}(hj`IhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj\IhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:454: ./drivers/gpu/drm/i915/i915_perf.chMsubj )}(h h]h }(hjoIhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj\IhhhjnIhMsubj)}(hi915_perf_destroy_lockedh]j)}(hi915_perf_destroy_lockedh]hi915_perf_destroy_locked}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}Iubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj\IhhhjnIhMsubj8)}(h!(struct i915_perf_stream *stream)h]j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjIhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjIubj )}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjIubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjImodnameN classnameNjj)}j]j)}jjIsbc.i915_perf_destroy_lockedasbuh1hhjIubj )}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjIubj)}(hjh]h*}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(hstreamh]hstream}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjIubah}(h]h ]h"]h$]h&]j5j6uh1j7hj\IhhhjnIhMsubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjXIhhhjnIhMsubah}(h]jSIah ](jjeh"]h$]h&]jj)jhuh1jhjnIhMshjUIhhubj)}(hhh]h)}(hdestroy an i915 perf streamh]hdestroy an i915 perf stream}(hj JhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:454: ./drivers/gpu/drm/i915/i915_perf.chMshjJhhubah}(h]h ]h"]h$]h&]uh1jhjUIhhhjnIhMsubeh}(h]h ](jfunctioneh"]h$]h&]jjjj8Jjj8Jjjjuh1jhhhj;7hNhNubj)}(hXM**Parameters** ``struct i915_perf_stream *stream`` An i915 perf stream **Description** Frees all resources associated with the given i915 perf **stream**, disabling any associated data capture in the process. **Note** The :c:type:`gt->perf `.lock mutex has been taken to serialize with any non-file-operation driver hooks.h](h)}(h**Parameters**h]j)}(hjBJh]h Parameters}(hjDJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@Jubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:454: ./drivers/gpu/drm/i915/i915_perf.chMwhjperf `.lock mutex has been taken to serialize with any non-file-operation driver hooks.h](hThe }(hjJhhhNhNubh)}(h:c:type:`gt->perf `h]j*)}(hjJh]hgt->perf}(hjJhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjJubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjgtuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:454: ./drivers/gpu/drm/i915/i915_perf.chMyhjJubhQ.lock mutex has been taken to serialize with any non-file-operation driver hooks.}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjKhMyhj)}(hstruct file *fileh](jD)}(hjGh]hstruct}(hjKhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjKubj )}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjKubh)}(hhh]j)}(hfileh]hfile}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjKmodnameN classnameNjj)}j]j\Kc.i915_perf_readasbuh1hhjKubj )}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjKubj)}(hjh]h*}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubj)}(hfileh]hfile}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjKubj>)}(hchar __user *bufh](jn)}(hcharh]hchar}(hjKhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjKubj )}(h h]h }(hj LhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjKubh__user}(hjKhhhNhNubj )}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjKubj)}(hjh]h*}(hj-LhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubj)}(hbufh]hbuf}(hj:LhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjKubj>)}(h size_t counth](h)}(hhh]j)}(hsize_th]hsize_t}(hjVLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSLubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjXLmodnameN classnameNjj)}j]j\Kc.i915_perf_readasbuh1hhjOLubj )}(h h]h }(hjtLhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjOLubj)}(hcounth]hcount}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOLubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjKubj>)}(h loff_t *pposh](h)}(hhh]j)}(hloff_th]hloff_t}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjLmodnameN classnameNjj)}j]j\Kc.i915_perf_readasbuh1hhjLubj )}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjLubj)}(hjh]h*}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(hpposh]hppos}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjKubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj9KhhhjaKhMS ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj5KhhhjaKhMS ubah}(h]j0Kah ](jjeh"]h$]h&]jj)jhuh1jhjaKhMS hj2Khhubj)}(hhh]h)}(h+handles read() FOP for i915 perf stream FDsh]h+handles read() FOP for i915 perf stream FDs}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:456: ./drivers/gpu/drm/i915/i915_perf.chMS hjLhhubah}(h]h ]h"]h$]h&]uh1jhj2KhhhjaKhMS ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjMjjMjjjuh1jhhhj;7hNhNubj)}(hX'**Parameters** ``struct file *file`` An i915 perf stream file ``char __user *buf`` destination buffer given by userspace ``size_t count`` the number of bytes userspace wants to read ``loff_t *ppos`` (inout) file seek position (unused) **Description** The entry point for handling a read() on a stream file descriptor from userspace. Most of the work is left to the i915_perf_read_locked() and :c:type:`i915_perf_stream_ops->read ` but to save having stream implementations (of which we might have multiple later) we handle blocking read here. We can also consistently treat trying to read from a disabled stream as an IO error so implementations can assume the stream is enabled while reading. **Return** The number of bytes copied or a negative error code on failure.h](h)}(h**Parameters**h]j)}(hj#Mh]h Parameters}(hj%MhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!Mubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:456: ./drivers/gpu/drm/i915/i915_perf.chMW hjMubj)}(hhh](j)}(h/``struct file *file`` An i915 perf stream file h](j$)}(h``struct file *file``h]j*)}(hjBMh]hstruct file *file}(hjDMhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj@Mubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:456: ./drivers/gpu/drm/i915/i915_perf.chMT hjread ` but to save having stream implementations (of which we might have multiple later) we handle blocking read here.h](hThe entry point for handling a read() on a stream file descriptor from userspace. Most of the work is left to the i915_perf_read_locked() and }(hj>NhhhNhNubh)}(h;:c:type:`i915_perf_stream_ops->read `h]j*)}(hjHNh]hi915_perf_stream_ops->read}(hjJNhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjFNubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_perf_stream_opsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:456: ./drivers/gpu/drm/i915/i915_perf.chMX hj>Nubhp but to save having stream implementations (of which we might have multiple later) we handle blocking read here.}(hj>NhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjeNhMX hjMubh)}(hWe can also consistently treat trying to read from a disabled stream as an IO error so implementations can assume the stream is enabled while reading.h]hWe can also consistently treat trying to read from a disabled stream as an IO error so implementations can assume the stream is enabled while reading.}(hjpNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:456: ./drivers/gpu/drm/i915/i915_perf.chM] hjMubh)}(h **Return**h]j)}(hjNh]hReturn}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:456: ./drivers/gpu/drm/i915/i915_perf.chMa hjMubh)}(h?The number of bytes copied or a negative error code on failure.h]h?The number of bytes copied or a negative error code on failure.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:456: ./drivers/gpu/drm/i915/i915_perf.chMb hjMubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_perf_ioctl (C function)c.i915_perf_ioctlhNtauh1jhj;7hhhNhNubj)}(hhh](j)}(hMlong i915_perf_ioctl (struct file *file, unsigned int cmd, unsigned long arg)h]j)}(hLlong i915_perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg)h](jn)}(hlongh]hlong}(hjNhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjNhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chMZubj )}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjNhhhjNhMZubj)}(hi915_perf_ioctlh]j)}(hi915_perf_ioctlh]hi915_perf_ioctl}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjNhhhjNhMZubj8)}(h8(struct file *file, unsigned int cmd, unsigned long arg)h](j>)}(hstruct file *fileh](jD)}(hjGh]hstruct}(hjOhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjNubj )}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjNubh)}(hhh]j)}(hfileh]hfile}(hj!OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj#OmodnameN classnameNjj)}j]j)}jjNsbc.i915_perf_ioctlasbuh1hhjNubj )}(h h]h }(hjAOhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjNubj)}(hjh]h*}(hjOOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubj)}(hfileh]hfile}(hj\OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjNubj>)}(hunsigned int cmdh](jn)}(hunsignedh]hunsigned}(hjuOhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjqOubj )}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjqOubjn)}(hinth]hint}(hjOhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjqOubj )}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjqOubj)}(hcmdh]hcmd}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqOubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjNubj>)}(hunsigned long argh](jn)}(hunsignedh]hunsigned}(hjOhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjOubj )}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjOubjn)}(hlongh]hlong}(hjOhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjOubj )}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjOubj)}(hargh]harg}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjNubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjNhhhjNhMZubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjNhhhjNhMZubah}(h]jNah ](jjeh"]h$]h&]jj)jhuh1jhjNhMZhjNhhubj)}(hhh]h)}(h/support ioctl() usage with i915 perf stream FDsh]h/support ioctl() usage with i915 perf stream FDs}(hj(PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chMZhj%Phhubah}(h]h ]h"]h$]h&]uh1jhjNhhhjNhMZubeh}(h]h ](jfunctioneh"]h$]h&]jjjj@Pjj@Pjjjuh1jhhhj;7hNhNubj)}(hX>**Parameters** ``struct file *file`` An i915 perf stream file ``unsigned int cmd`` the ioctl request ``unsigned long arg`` the ioctl data **Description** Implementation deferred to i915_perf_ioctl_locked(). **Return** zero on success or a negative error code. Returns -EINVAL for an unknown ioctl request.h](h)}(h**Parameters**h]j)}(hjJPh]h Parameters}(hjLPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHPubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chM^hjDPubj)}(hhh](j)}(h/``struct file *file`` An i915 perf stream file h](j$)}(h``struct file *file``h]j*)}(hjiPh]hstruct file *file}(hjkPhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjgPubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chM[hjcPubj@)}(hhh]h)}(hAn i915 perf stream fileh]hAn i915 perf stream file}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~PhM[hjPubah}(h]h ]h"]h$]h&]uh1j?hjcPubeh}(h]h ]h"]h$]h&]uh1jhj~PhM[hj`Pubj)}(h'``unsigned int cmd`` the ioctl request h](j$)}(h``unsigned int cmd``h]j*)}(hjPh]hunsigned int cmd}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjPubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chM\hjPubj@)}(hhh]h)}(hthe ioctl requesth]hthe ioctl request}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM\hjPubah}(h]h ]h"]h$]h&]uh1j?hjPubeh}(h]h ]h"]h$]h&]uh1jhjPhM\hj`Pubj)}(h%``unsigned long arg`` the ioctl data h](j$)}(h``unsigned long arg``h]j*)}(hjPh]hunsigned long arg}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjPubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chM]hjPubj@)}(hhh]h)}(hthe ioctl datah]hthe ioctl data}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM]hjPubah}(h]h ]h"]h$]h&]uh1j?hjPubeh}(h]h ]h"]h$]h&]uh1jhjPhM]hj`Pubeh}(h]h ]h"]h$]h&]uh1jhjDPubh)}(h**Description**h]j)}(hjQh]h Description}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chM_hjDPubh)}(h4Implementation deferred to i915_perf_ioctl_locked().h]h4Implementation deferred to i915_perf_ioctl_locked().}(hj,QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chM^hjDPubh)}(h **Return**h]j)}(hj=Qh]hReturn}(hj?QhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;Qubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chM`hjDPubh)}(hWzero on success or a negative error code. Returns -EINVAL for an unknown ioctl request.h]hWzero on success or a negative error code. Returns -EINVAL for an unknown ioctl request.}(hjSQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:458: ./drivers/gpu/drm/i915/i915_perf.chMahjDPubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$i915_perf_enable_locked (C function)c.i915_perf_enable_lockedhNtauh1jhj;7hhhNhNubj)}(hhh](j)}(h>void i915_perf_enable_locked (struct i915_perf_stream *stream)h]j)}(h=void i915_perf_enable_locked(struct i915_perf_stream *stream)h](jn)}(hvoidh]hvoid}(hjQhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj~QhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:460: ./drivers/gpu/drm/i915/i915_perf.chM ubj )}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj~QhhhjQhM ubj)}(hi915_perf_enable_lockedh]j)}(hi915_perf_enable_lockedh]hi915_perf_enable_locked}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj~QhhhjQhM ubj8)}(h!(struct i915_perf_stream *stream)h]j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjQhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjQubj )}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjQubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjQmodnameN classnameNjj)}j]j)}jjQsbc.i915_perf_enable_lockedasbuh1hhjQubj )}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjQubj)}(hjh]h*}(hj RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj)}(hstreamh]hstream}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjQubah}(h]h ]h"]h$]h&]j5j6uh1j7hj~QhhhjQhM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjzQhhhjQhM ubah}(h]juQah ](jjeh"]h$]h&]jj)jhuh1jhjQhM hjwQhhubj)}(hhh]h)}(h%handle `I915_PERF_IOCTL_ENABLE` ioctlh](hhandle }(hjBRhhhNhNubjc)}(h`I915_PERF_IOCTL_ENABLE`h]hI915_PERF_IOCTL_ENABLE}(hjJRhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjBRubh ioctl}(hjBRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:460: ./drivers/gpu/drm/i915/i915_perf.chM hj?Rhhubah}(h]h ]h"]h$]h&]uh1jhjwQhhhjQhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjlRjjlRjjjuh1jhhhj;7hNhNubj)}(hX>**Parameters** ``struct i915_perf_stream *stream`` A disabled i915 perf stream **Description** [Re]enables the associated capture of data for this stream. If a stream was previously enabled then there's currently no intention to provide userspace any guarantee about the preservation of previously buffered data.h](h)}(h**Parameters**h]j)}(hjvRh]h Parameters}(hjxRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtRubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:460: ./drivers/gpu/drm/i915/i915_perf.chM hjpRubj)}(hhh]j)}(h@``struct i915_perf_stream *stream`` A disabled i915 perf stream h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjRh]hstruct i915_perf_stream *stream}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjRubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:460: ./drivers/gpu/drm/i915/i915_perf.chM hjRubj@)}(hhh]h)}(hA disabled i915 perf streamh]hA disabled i915 perf stream}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhM hjRubah}(h]h ]h"]h$]h&]uh1j?hjRubeh}(h]h ]h"]h$]h&]uh1jhjRhM hjRubah}(h]h ]h"]h$]h&]uh1jhjpRubh)}(h**Description**h]j)}(hjRh]h Description}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:460: ./drivers/gpu/drm/i915/i915_perf.chM hjpRubh)}(h;[Re]enables the associated capture of data for this stream.h]h;[Re]enables the associated capture of data for this stream.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:460: ./drivers/gpu/drm/i915/i915_perf.chM hjpRubh)}(hIf a stream was previously enabled then there's currently no intention to provide userspace any guarantee about the preservation of previously buffered data.h]hIf a stream was previously enabled then there’s currently no intention to provide userspace any guarantee about the preservation of previously buffered data.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:460: ./drivers/gpu/drm/i915/i915_perf.chM hjpRubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%i915_perf_disable_locked (C function)c.i915_perf_disable_lockedhNtauh1jhj;7hhhNhNubj)}(hhh](j)}(h?void i915_perf_disable_locked (struct i915_perf_stream *stream)h]j)}(h>void i915_perf_disable_locked(struct i915_perf_stream *stream)h](jn)}(hvoidh]hvoid}(hj$ShhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj ShhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hj3ShhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj Shhhj2ShMubj)}(hi915_perf_disable_lockedh]j)}(hi915_perf_disable_lockedh]hi915_perf_disable_locked}(hjEShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjASubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj Shhhj2ShMubj8)}(h!(struct i915_perf_stream *stream)h]j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjaShhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj]Subj )}(h h]h }(hjnShhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj]Subh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|Subah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjSmodnameN classnameNjj)}j]j)}jjGSsbc.i915_perf_disable_lockedasbuh1hhj]Subj )}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj]Subj)}(hjh]h*}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]Subj)}(hstreamh]hstream}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]Subeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjYSubah}(h]h ]h"]h$]h&]j5j6uh1j7hj Shhhj2ShMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjShhhj2ShMubah}(h]jSah ](jjeh"]h$]h&]jj)jhuh1jhj2ShMhjShhubj)}(hhh]h)}(h&handle `I915_PERF_IOCTL_DISABLE` ioctlh](hhandle }(hjShhhNhNubjc)}(h`I915_PERF_IOCTL_DISABLE`h]hI915_PERF_IOCTL_DISABLE}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j chjSubh ioctl}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chMhjShhubah}(h]h ]h"]h$]h&]uh1jhjShhhj2ShMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjTjjTjjjuh1jhhhj;7hNhNubj)}(hX/**Parameters** ``struct i915_perf_stream *stream`` An enabled i915 perf stream **Description** Disables the associated capture of data for this stream. The intention is that disabling an re-enabling a stream will ideally be cheaper than destroying and re-opening a stream with the same configuration, though there are no formal guarantees about what state or buffered data must be retained between disabling and re-enabling a stream. **Note** while a stream is disabled it's considered an error for userspace to attempt to read from the stream (-EIO).h](h)}(h**Parameters**h]j)}(hjTh]h Parameters}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chMhjTubj)}(hhh]j)}(h@``struct i915_perf_stream *stream`` An enabled i915 perf stream h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hj7Th]hstruct i915_perf_stream *stream}(hj9ThhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj5Tubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chMhj1Tubj@)}(hhh]h)}(hAn enabled i915 perf streamh]hAn enabled i915 perf stream}(hjPThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLThMhjMTubah}(h]h ]h"]h$]h&]uh1j?hj1Tubeh}(h]h ]h"]h$]h&]uh1jhjLThMhj.Tubah}(h]h ]h"]h$]h&]uh1jhjTubh)}(h**Description**h]j)}(hjrTh]h Description}(hjtThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpTubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chMhjTubh)}(h8Disables the associated capture of data for this stream.h]h8Disables the associated capture of data for this stream.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chMhjTubh)}(hXThe intention is that disabling an re-enabling a stream will ideally be cheaper than destroying and re-opening a stream with the same configuration, though there are no formal guarantees about what state or buffered data must be retained between disabling and re-enabling a stream.h]hXThe intention is that disabling an re-enabling a stream will ideally be cheaper than destroying and re-opening a stream with the same configuration, though there are no formal guarantees about what state or buffered data must be retained between disabling and re-enabling a stream.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chMhjTubh)}(h**Note**h]j)}(hjTh]hNote}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chM hjTubh)}(hlwhile a stream is disabled it's considered an error for userspace to attempt to read from the stream (-EIO).h]hnwhile a stream is disabled it’s considered an error for userspace to attempt to read from the stream (-EIO).}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:462: ./drivers/gpu/drm/i915/i915_perf.chM hjTubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_perf_poll (C function)c.i915_perf_pollhNtauh1jhj;7hhhNhNubj)}(hhh](j)}(h=__poll_t i915_perf_poll (struct file *file, poll_table *wait)h]j)}(h<__poll_t i915_perf_poll(struct file *file, poll_table *wait)h](h)}(hhh]j)}(h__poll_th]h__poll_t}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjTmodnameN classnameNjj)}j]j)}ji915_perf_pollsbc.i915_perf_pollasbuh1hhjThhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM ubj )}(h h]h }(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjThhhjUhM ubj)}(hi915_perf_pollh]j)}(hjUh]hi915_perf_poll}(hj$UhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Uubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjThhhjUhM ubj8)}(h%(struct file *file, poll_table *wait)h](j>)}(hstruct file *fileh](jD)}(hjGh]hstruct}(hj?UhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj;Uubj )}(h h]h }(hjLUhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj;Uubh)}(hhh]j)}(hfileh]hfile}(hj]UhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj_UmodnameN classnameNjj)}j]j Uc.i915_perf_pollasbuh1hhj;Uubj )}(h h]h }(hj{UhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj;Uubj)}(hjh]h*}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;Uubj)}(hfileh]hfile}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;Uubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj7Uubj>)}(hpoll_table *waith](h)}(hhh]j)}(h poll_tableh]h poll_table}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]j Uc.i915_perf_pollasbuh1hhjUubj )}(h h]h }(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjUubj)}(hjh]h*}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubj)}(hwaith]hwait}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj7Uubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjThhhjUhM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjThhhjUhM ubah}(h]jTah ](jjeh"]h$]h&]jj)jhuh1jhjUhM hjThhubj)}(hhh]h)}(h6call poll_wait() with a suitable wait queue for streamh]h6call poll_wait() with a suitable wait queue for stream}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hjVhhubah}(h]h ]h"]h$]h&]uh1jhjThhhjUhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj-Vjj-Vjjjuh1jhhhj;7hNhNubj)}(hX**Parameters** ``struct file *file`` An i915 perf stream file ``poll_table *wait`` poll() state table **Description** For handling userspace polling on an i915 perf stream, this ensures poll_wait() gets called with a wait queue that will be woken for new stream data. **Note** Implementation deferred to i915_perf_poll_locked() **Return** any poll events that are ready without sleepingh](h)}(h**Parameters**h]j)}(hj7Vh]h Parameters}(hj9VhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5Vubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hj1Vubj)}(hhh](j)}(h/``struct file *file`` An i915 perf stream file h](j$)}(h``struct file *file``h]j*)}(hjVVh]hstruct file *file}(hjXVhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjTVubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hjPVubj@)}(hhh]h)}(hAn i915 perf stream fileh]hAn i915 perf stream file}(hjoVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkVhM hjlVubah}(h]h ]h"]h$]h&]uh1j?hjPVubeh}(h]h ]h"]h$]h&]uh1jhjkVhM hjMVubj)}(h(``poll_table *wait`` poll() state table h](j$)}(h``poll_table *wait``h]j*)}(hjVh]hpoll_table *wait}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjVubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hjVubj@)}(hhh]h)}(hpoll() state tableh]hpoll() state table}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhM hjVubah}(h]h ]h"]h$]h&]uh1j?hjVubeh}(h]h ]h"]h$]h&]uh1jhjVhM hjMVubeh}(h]h ]h"]h$]h&]uh1jhj1Vubh)}(h**Description**h]j)}(hjVh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hj1Vubh)}(hFor handling userspace polling on an i915 perf stream, this ensures poll_wait() gets called with a wait queue that will be woken for new stream data.h]hFor handling userspace polling on an i915 perf stream, this ensures poll_wait() gets called with a wait queue that will be woken for new stream data.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hj1Vubh)}(h**Note**h]j)}(hjVh]hNote}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hj1Vubh)}(h2Implementation deferred to i915_perf_poll_locked()h]h2Implementation deferred to i915_perf_poll_locked()}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hj1Vubh)}(h **Return**h]j)}(hjWh]hReturn}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hj1Vubh)}(h/any poll events that are ready without sleepingh]h/any poll events that are ready without sleeping}(hj.WhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:464: ./drivers/gpu/drm/i915/i915_perf.chM hj1Vubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_perf_poll_locked (C function)c.i915_perf_poll_lockedhNtauh1jhj;7hhhNhNubj)}(hhh](j)}(he__poll_t i915_perf_poll_locked (struct i915_perf_stream *stream, struct file *file, poll_table *wait)h]j)}(hd__poll_t i915_perf_poll_locked(struct i915_perf_stream *stream, struct file *file, poll_table *wait)h](h)}(hhh]j)}(h__poll_th]h__poll_t}(hj`WhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]Wubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjbWmodnameN classnameNjj)}j]j)}ji915_perf_poll_lockedsbc.i915_perf_poll_lockedasbuh1hhjYWhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM ubj )}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjYWhhhjWhM ubj)}(hi915_perf_poll_lockedh]j)}(hj~Wh]hi915_perf_poll_locked}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjYWhhhjWhM ubj8)}(hF(struct i915_perf_stream *stream, struct file *file, poll_table *wait)h](j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjWhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjWubj )}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjWubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjWmodnameN classnameNjj)}j]j|Wc.i915_perf_poll_lockedasbuh1hhjWubj )}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjWubj)}(hjh]h*}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj)}(hstreamh]hstream}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubj>)}(hstruct file *fileh](jD)}(hjGh]hstruct}(hjXhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjXubj )}(h h]h }(hj,XhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXubh)}(hhh]j)}(hfileh]hfile}(hj=XhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:Xubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj?XmodnameN classnameNjj)}j]j|Wc.i915_perf_poll_lockedasbuh1hhjXubj )}(h h]h }(hj[XhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXubj)}(hjh]h*}(hjiXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj)}(hfileh]hfile}(hjvXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubj>)}(hpoll_table *waith](h)}(hhh]j)}(h poll_tableh]h poll_table}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjXmodnameN classnameNjj)}j]j|Wc.i915_perf_poll_lockedasbuh1hhjXubj )}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXubj)}(hjh]h*}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj)}(hwaith]hwait}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjWubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjYWhhhjWhM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjUWhhhjWhM ubah}(h]jPWah ](jjeh"]h$]h&]jj)jhuh1jhjWhM hjRWhhubj)}(hhh]h)}(h1poll_wait() with a suitable wait queue for streamh]h1poll_wait() with a suitable wait queue for stream}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hjXhhubah}(h]h ]h"]h$]h&]uh1jhjRWhhhjWhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj Yjj Yjjjuh1jhhhj;7hNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915 perf stream ``struct file *file`` An i915 perf stream file ``poll_table *wait`` poll() state table **Description** For handling userspace polling on an i915 perf stream, this calls through to :c:type:`i915_perf_stream_ops->poll_wait ` to call poll_wait() with a wait queue that will be woken for new stream data. **Return** any poll events that are ready without sleepingh](h)}(h**Parameters**h]j)}(hjYh]h Parameters}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hjYubj)}(hhh](j)}(h8``struct i915_perf_stream *stream`` An i915 perf stream h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hj6Yh]hstruct i915_perf_stream *stream}(hj8YhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj4Yubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hj0Yubj@)}(hhh]h)}(hAn i915 perf streamh]hAn i915 perf stream}(hjOYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKYhM hjLYubah}(h]h ]h"]h$]h&]uh1j?hj0Yubeh}(h]h ]h"]h$]h&]uh1jhjKYhM hj-Yubj)}(h/``struct file *file`` An i915 perf stream file h](j$)}(h``struct file *file``h]j*)}(hjoYh]hstruct file *file}(hjqYhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjmYubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hjiYubj@)}(hhh]h)}(hAn i915 perf stream fileh]hAn i915 perf stream file}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhM hjYubah}(h]h ]h"]h$]h&]uh1j?hjiYubeh}(h]h ]h"]h$]h&]uh1jhjYhM hj-Yubj)}(h(``poll_table *wait`` poll() state table h](j$)}(h``poll_table *wait``h]j*)}(hjYh]hpoll_table *wait}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjYubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hjYubj@)}(hhh]h)}(hpoll() state tableh]hpoll() state table}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhM hjYubah}(h]h ]h"]h$]h&]uh1j?hjYubeh}(h]h ]h"]h$]h&]uh1jhjYhM hj-Yubeh}(h]h ]h"]h$]h&]uh1jhjYubh)}(h**Description**h]j)}(hjYh]h Description}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hjYubh)}(hFor handling userspace polling on an i915 perf stream, this calls through to :c:type:`i915_perf_stream_ops->poll_wait ` to call poll_wait() with a wait queue that will be woken for new stream data.h](hMFor handling userspace polling on an i915 perf stream, this calls through to }(hjYhhhNhNubh)}(h@:c:type:`i915_perf_stream_ops->poll_wait `h]j*)}(hjZh]hi915_perf_stream_ops->poll_wait}(hjZhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjZubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_perf_stream_opsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hjYubhN to call poll_wait() with a wait queue that will be woken for new stream data.}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj ZhM hjYubh)}(h **Return**h]j)}(hj-Zh]hReturn}(hj/ZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+Zubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hjYubh)}(h/any poll events that are ready without sleepingh]h/any poll events that are ready without sleeping}(hjCZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:466: ./drivers/gpu/drm/i915/i915_perf.chM hjYubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj;7hhhNhNubeh}(h]i915-perf-streamah ]h"]i915 perf streamah$]h&]uh1hhj#hhhhhMubh)}(hhh](h)}(h)i915 Perf Observation Architecture Streamh]h)i915 Perf Observation Architecture Stream}(hjdZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaZhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_oa_ops (C struct) c.i915_oa_opshNtauh1jhjaZhhhNhNubj)}(hhh](j)}(h i915_oa_opsh]j)}(hstruct i915_oa_opsh](jD)}(hjGh]hstruct}(hjZhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjZhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhKubj )}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjZhhhjZhKubj)}(h i915_oa_opsh]j)}(hjZh]h i915_oa_ops}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjZhhhjZhKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjZhhhjZhKubah}(h]j~Zah ](jjeh"]h$]h&]jj)jhuh1jhjZhKhjZhhubj)}(hhh]h)}(h0Gen specific implementation of an OA unit streamh]h0Gen specific implementation of an OA unit stream}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhMZhjZhhubah}(h]h ]h"]h$]h&]uh1jhjZhhhjZhKubeh}(h]h ](jstructeh"]h$]h&]jjjjZjjZjjjuh1jhhhjaZhNhNubj)}(hX**Definition**:: struct i915_oa_ops { bool (*is_valid_b_counter_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_mux_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_flex_reg)(struct i915_perf *perf, u32 addr); int (*enable_metric_set)(struct i915_perf_stream *stream, struct i915_active *active); void (*disable_metric_set)(struct i915_perf_stream *stream); void (*oa_enable)(struct i915_perf_stream *stream); void (*oa_disable)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset); u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream); }; **Members** ``is_valid_b_counter_reg`` Validates register's address for programming boolean counters for a particular platform. ``is_valid_mux_reg`` Validates register's address for programming mux for a particular platform. ``is_valid_flex_reg`` Validates register's address for programming flex EU filtering for a particular platform. ``enable_metric_set`` Selects and applies any MUX configuration to set up the Boolean and Custom (B/C) counters that are part of the counter reports being sampled. May apply system constraints such as disabling EU clock gating as required. ``disable_metric_set`` Remove system constraints associated with using the OA unit. ``oa_enable`` Enable periodic sampling ``oa_disable`` Disable periodic sampling ``read`` Copy data from the circular OA buffer into a given userspace buffer. ``oa_hw_tail_read`` read the OA tail pointer register In particular this enables us to share all the fiddly code for handling the OA unit tail pointer race that affects multiple generations.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubh:}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhM^hjZubjA#)}(hXstruct i915_oa_ops { bool (*is_valid_b_counter_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_mux_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_flex_reg)(struct i915_perf *perf, u32 addr); int (*enable_metric_set)(struct i915_perf_stream *stream, struct i915_active *active); void (*disable_metric_set)(struct i915_perf_stream *stream); void (*oa_enable)(struct i915_perf_stream *stream); void (*oa_disable)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset); u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream); };h]hXstruct i915_oa_ops { bool (*is_valid_b_counter_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_mux_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_flex_reg)(struct i915_perf *perf, u32 addr); int (*enable_metric_set)(struct i915_perf_stream *stream, struct i915_active *active); void (*disable_metric_set)(struct i915_perf_stream *stream); void (*oa_enable)(struct i915_perf_stream *stream); void (*oa_disable)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset); u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream); };}hj [sbah}(h]h ]h"]h$]h&]j5j6uh1j@#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhM`hjZubh)}(h **Members**h]j)}(hj[h]hMembers}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhMlhjZubj)}(hhh](j)}(ht``is_valid_b_counter_reg`` Validates register's address for programming boolean counters for a particular platform. h](j$)}(h``is_valid_b_counter_reg``h]j*)}(hj:[h]his_valid_b_counter_reg}(hj<[hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj8[ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhM`hj4[ubj@)}(hhh]h)}(hXValidates register's address for programming boolean counters for a particular platform.h]hZValidates register’s address for programming boolean counters for a particular platform.}(hjS[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhM_hjP[ubah}(h]h ]h"]h$]h&]uh1j?hj4[ubeh}(h]h ]h"]h$]h&]uh1jhjO[hM`hj1[ubj)}(ha``is_valid_mux_reg`` Validates register's address for programming mux for a particular platform. h](j$)}(h``is_valid_mux_reg``h]j*)}(hjt[h]his_valid_mux_reg}(hjv[hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjr[ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhMfhjn[ubj@)}(hhh]h)}(hKValidates register's address for programming mux for a particular platform.h]hMValidates register’s address for programming mux for a particular platform.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhMehj[ubah}(h]h ]h"]h$]h&]uh1j?hjn[ubeh}(h]h ]h"]h$]h&]uh1jhj[hMfhj1[ubj)}(hp``is_valid_flex_reg`` Validates register's address for programming flex EU filtering for a particular platform. h](j$)}(h``is_valid_flex_reg``h]j*)}(hj[h]his_valid_flex_reg}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj[ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhMlhj[ubj@)}(hhh]h)}(hYValidates register's address for programming flex EU filtering for a particular platform.h]h[Validates register’s address for programming flex EU filtering for a particular platform.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhMkhj[ubah}(h]h ]h"]h$]h&]uh1j?hj[ubeh}(h]h ]h"]h$]h&]uh1jhj[hMlhj1[ubj)}(h``enable_metric_set`` Selects and applies any MUX configuration to set up the Boolean and Custom (B/C) counters that are part of the counter reports being sampled. May apply system constraints such as disabling EU clock gating as required. h](j$)}(h``enable_metric_set``h]j*)}(hj[h]henable_metric_set}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj[ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhMthj[ubj@)}(hhh]h)}(hSelects and applies any MUX configuration to set up the Boolean and Custom (B/C) counters that are part of the counter reports being sampled. May apply system constraints such as disabling EU clock gating as required.h]hSelects and applies any MUX configuration to set up the Boolean and Custom (B/C) counters that are part of the counter reports being sampled. May apply system constraints such as disabling EU clock gating as required.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhMqhj[ubah}(h]h ]h"]h$]h&]uh1j?hj[ubeh}(h]h ]h"]h$]h&]uh1jhj[hMthj1[ubj)}(hT``disable_metric_set`` Remove system constraints associated with using the OA unit. h](j$)}(h``disable_metric_set``h]j*)}(hj"\h]hdisable_metric_set}(hj$\hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj \ubah}(h]h ]h"]h$]h&]uh1j#h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:472: ./drivers/gpu/drm/i915/i915_perf_types.hhM{hj\ubj@)}(hhh]h)}(h)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hj]hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj]ubj )}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj]ubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj]modnameN classnameNjj)}j]j)}jj]sbc.i915_oa_stream_initasbuh1hhj]ubj )}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj]ubj)}(hjh]h*}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj)}(hstreamh]hstream}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj]ubj>)}(h&struct drm_i915_perf_open_param *paramh](jD)}(hjGh]hstruct}(hj ^hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj^ubj )}(h h]h }(hj-^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubh)}(hhh]j)}(hdrm_i915_perf_open_paramh]hdrm_i915_perf_open_param}(hj>^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;^ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj@^modnameN classnameNjj)}j]j]c.i915_oa_stream_initasbuh1hhj^ubj )}(h h]h }(hj\^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubj)}(hjh]h*}(hjj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj)}(hparamh]hparam}(hjw^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj]ubj>)}(h"struct perf_open_properties *propsh](jD)}(hjGh]hstruct}(hj^hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj^ubj )}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubh)}(hhh]j)}(hperf_open_propertiesh]hperf_open_properties}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj^modnameN classnameNjj)}j]j]c.i915_oa_stream_initasbuh1hhj^ubj )}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj^ubj)}(hjh]h*}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj)}(hpropsh]hprops}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj]ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjm]hhhj]hM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhji]hhhj]hM ubah}(h]jd]ah ](jjeh"]h$]h&]jj)jhuh1jhj]hM hjf]hhubj)}(hhh]h)}(h.validate combined props for OA stream and inith]h.validate combined props for OA stream and init}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj_hhubah}(h]h ]h"]h$]h&]uh1jhjf]hhhj]hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj)_jj)_jjjuh1jhhhjaZhNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915 perf stream ``struct drm_i915_perf_open_param *param`` The open parameters passed to `DRM_I915_PERF_OPEN` ``struct perf_open_properties *props`` The property state that configures stream (individually validated) **Description** While read_properties_unlocked() validates properties in isolation it doesn't ensure that the combination necessarily makes sense. At this point it has been determined that userspace wants a stream of OA metrics, but still we need to further validate the combined properties are OK. If the configuration makes sense then we can allocate memory for a circular OA buffer and apply the requested metric set configuration. **Return** zero on success or a negative error code.h](h)}(h**Parameters**h]j)}(hj3_h]h Parameters}(hj5_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1_ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj-_ubj)}(hhh](j)}(h8``struct i915_perf_stream *stream`` An i915 perf stream h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjR_h]hstruct i915_perf_stream *stream}(hjT_hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjP_ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hjL_ubj@)}(hhh]h)}(hAn i915 perf streamh]hAn i915 perf stream}(hjk_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjg_hM hjh_ubah}(h]h ]h"]h$]h&]uh1j?hjL_ubeh}(h]h ]h"]h$]h&]uh1jhjg_hM hjI_ubj)}(h^``struct drm_i915_perf_open_param *param`` The open parameters passed to `DRM_I915_PERF_OPEN` h](j$)}(h*``struct drm_i915_perf_open_param *param``h]j*)}(hj_h]h&struct drm_i915_perf_open_param *param}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj_ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj_ubj@)}(hhh]h)}(h2The open parameters passed to `DRM_I915_PERF_OPEN`h](hThe open parameters passed to }(hj_hhhNhNubjc)}(h`DRM_I915_PERF_OPEN`h]hDRM_I915_PERF_OPEN}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j chj_ubeh}(h]h ]h"]h$]h&]uh1hhj_hM hj_ubah}(h]h ]h"]h$]h&]uh1j?hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM hjI_ubj)}(hj``struct perf_open_properties *props`` The property state that configures stream (individually validated) h](j$)}(h&``struct perf_open_properties *props``h]j*)}(hj_h]h"struct perf_open_properties *props}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj_ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj_ubj@)}(hhh]h)}(hBThe property state that configures stream (individually validated)h]hBThe property state that configures stream (individually validated)}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM hj_ubah}(h]h ]h"]h$]h&]uh1j?hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM hjI_ubeh}(h]h ]h"]h$]h&]uh1jhj-_ubh)}(h**Description**h]j)}(hj `h]h Description}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj `ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj-_ubh)}(hWhile read_properties_unlocked() validates properties in isolation it doesn't ensure that the combination necessarily makes sense.h]hWhile read_properties_unlocked() validates properties in isolation it doesn’t ensure that the combination necessarily makes sense.}(hj#`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj-_ubh)}(hAt this point it has been determined that userspace wants a stream of OA metrics, but still we need to further validate the combined properties are OK.h]hAt this point it has been determined that userspace wants a stream of OA metrics, but still we need to further validate the combined properties are OK.}(hj2`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj-_ubh)}(hIf the configuration makes sense then we can allocate memory for a circular OA buffer and apply the requested metric set configuration.h]hIf the configuration makes sense then we can allocate memory for a circular OA buffer and apply the requested metric set configuration.}(hjA`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj-_ubh)}(h **Return**h]j)}(hjR`h]hReturn}(hjT`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjP`ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj-_ubh)}(h)zero on success or a negative error code.h]h)zero on success or a negative error code.}(hjh`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:475: ./drivers/gpu/drm/i915/i915_perf.chM hj-_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjaZhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_oa_read (C function)c.i915_oa_readhNtauh1jhjaZhhhNhNubj)}(hhh](j)}(hbint i915_oa_read (struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h]j)}(haint i915_oa_read(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h](jn)}(hinth]hint}(hj`hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj`hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj`hhhj`hMubj)}(h i915_oa_readh]j)}(h i915_oa_readh]h i915_oa_read}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj`hhhj`hMubj8)}(hQ(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h](j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hj`hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj`ubj )}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj`ubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj`modnameN classnameNjj)}j]j)}jj`sbc.i915_oa_readasbuh1hhj`ubj )}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj`ubj)}(hjh]h*}(hj ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubj)}(hstreamh]hstream}(hj-ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj`ubj>)}(hchar __user *bufh](jn)}(hcharh]hchar}(hjFahhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjBaubj )}(h h]h }(hjTahhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBaubh__user}(hjBahhhNhNubj )}(h h]h }(hjfahhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjBaubj)}(hjh]h*}(hjtahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBaubj)}(hbufh]hbuf}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBaubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj`ubj>)}(h size_t counth](h)}(hhh]j)}(hsize_th]hsize_t}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjamodnameN classnameNjj)}j]jac.i915_oa_readasbuh1hhjaubj )}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjaubj)}(hcounth]hcount}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj`ubj>)}(hsize_t *offseth](h)}(hhh]j)}(hsize_th]hsize_t}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjamodnameN classnameNjj)}j]jac.i915_oa_readasbuh1hhjaubj )}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjaubj)}(hjh]h*}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj)}(hoffseth]hoffset}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj`ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj`hhhj`hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj`hhhj`hMubah}(h]j`ah ](jjeh"]h$]h&]jj)jhuh1jhj`hMhj`hhubj)}(hhh]h)}(h?just calls through to :c:type:`i915_oa_ops->read `h](hjust calls through to }(hjHbhhhNhNubh)}(h):c:type:`i915_oa_ops->read `h]j*)}(hjRbh]hi915_oa_ops->read}(hjTbhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1j)hjPbubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]jac.i915_oa_readasbj i915_oa_opsuh1hhj`hMhjHbubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjEbhhubah}(h]h ]h"]h$]h&]uh1jhj`hhhj`hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjbjjbjjjuh1jhhhjaZhNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics ``char __user *buf`` destination buffer given by userspace ``size_t count`` the number of bytes userspace wants to read ``size_t *offset`` (inout): the current position for writing into **buf** **Description** Updates **offset** according to the number of bytes successfully copied into the userspace buffer. **Return** zero on success or a negative error codeh](h)}(h**Parameters**h]j)}(hjbh]h Parameters}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjbubj)}(hhh](j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjbh]hstruct i915_perf_stream *stream}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjbubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjbubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMhjbubah}(h]h ]h"]h$]h&]uh1j?hjbubeh}(h]h ]h"]h$]h&]uh1jhjbhMhjbubj)}(h;``char __user *buf`` destination buffer given by userspace h](j$)}(h``char __user *buf``h]j*)}(hjbh]hchar __user *buf}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjbubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjbubj@)}(hhh]h)}(h%destination buffer given by userspaceh]h%destination buffer given by userspace}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMhjbubah}(h]h ]h"]h$]h&]uh1j?hjbubeh}(h]h ]h"]h$]h&]uh1jhjbhMhjbubj)}(h=``size_t count`` the number of bytes userspace wants to read h](j$)}(h``size_t count``h]j*)}(hjch]h size_t count}(hj!chhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjcubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjcubj@)}(hhh]h)}(h+the number of bytes userspace wants to readh]h+the number of bytes userspace wants to read}(hj8chhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4chMhj5cubah}(h]h ]h"]h$]h&]uh1j?hjcubeh}(h]h ]h"]h$]h&]uh1jhj4chMhjbubj)}(hJ``size_t *offset`` (inout): the current position for writing into **buf** h](j$)}(h``size_t *offset``h]j*)}(hjXch]hsize_t *offset}(hjZchhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjVcubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjRcubj@)}(hhh]h)}(h6(inout): the current position for writing into **buf**h](h/(inout): the current position for writing into }(hjqchhhNhNubj)}(h**buf**h]hbuf}(hjychhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqcubeh}(h]h ]h"]h$]h&]uh1hhjmchMhjncubah}(h]h ]h"]h$]h&]uh1j?hjRcubeh}(h]h ]h"]h$]h&]uh1jhjmchMhjbubeh}(h]h ]h"]h$]h&]uh1jhjbubh)}(h**Description**h]j)}(hjch]h Description}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjbubh)}(hbUpdates **offset** according to the number of bytes successfully copied into the userspace buffer.h](hUpdates }(hjchhhNhNubj)}(h **offset**h]hoffset}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubhP according to the number of bytes successfully copied into the userspace buffer.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjbubh)}(h **Return**h]j)}(hjch]hReturn}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjbubh)}(h(zero on success or a negative error codeh]h(zero on success or a negative error code}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/i915_perf.chMhjbubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjaZhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_oa_stream_enable (C function)c.i915_oa_stream_enablehNtauh1jhjaZhhhNhNubj)}(hhh](j)}(h)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hj\dhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjXdubj )}(h h]h }(hjidhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXdubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjzdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwdubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj|dmodnameN classnameNjj)}j]j)}jjBdsbc.i915_oa_stream_enableasbuh1hhjXdubj )}(h h]h }(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjXdubj)}(hjh]h*}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXdubj)}(hstreamh]hstream}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXdubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjTdubah}(h]h ]h"]h$]h&]j5j6uh1j7hjdhhhj-dhM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjdhhhj-dhM ubah}(h]jdah ](jjeh"]h$]h&]jj)jhuh1jhj-dhM hjdhhubj)}(hhh]h)}(h-handle `I915_PERF_IOCTL_ENABLE` for OA streamh](hhandle }(hjdhhhNhNubjc)}(h`I915_PERF_IOCTL_ENABLE`h]hI915_PERF_IOCTL_ENABLE}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjdubh for OA stream}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:479: ./drivers/gpu/drm/i915/i915_perf.chM hjdhhubah}(h]h ]h"]h$]h&]uh1jhjdhhhj-dhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj ejj ejjjuh1jhhhjaZhNhNubj)}(hXi**Parameters** ``struct i915_perf_stream *stream`` An i915 perf stream opened for OA metrics **Description** [Re]enables hardware periodic sampling according to the period configured when opening the stream. This also starts a hrtimer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()).h](h)}(h**Parameters**h]j)}(hjeh]h Parameters}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:479: ./drivers/gpu/drm/i915/i915_perf.chM hj eubj)}(hhh]j)}(hN``struct i915_perf_stream *stream`` An i915 perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hj2eh]hstruct i915_perf_stream *stream}(hj4ehhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj0eubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:479: ./drivers/gpu/drm/i915/i915_perf.chM hj,eubj@)}(hhh]h)}(h)An i915 perf stream opened for OA metricsh]h)An i915 perf stream opened for OA metrics}(hjKehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGehM hjHeubah}(h]h ]h"]h$]h&]uh1j?hj,eubeh}(h]h ]h"]h$]h&]uh1jhjGehM hj)eubah}(h]h ]h"]h$]h&]uh1jhj eubh)}(h**Description**h]j)}(hjmeh]h Description}(hjoehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkeubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:479: ./drivers/gpu/drm/i915/i915_perf.chM hj eubh)}(h[Re]enables hardware periodic sampling according to the period configured when opening the stream. This also starts a hrtimer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()).h]h[Re]enables hardware periodic sampling according to the period configured when opening the stream. This also starts a hrtimer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()).}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:479: ./drivers/gpu/drm/i915/i915_perf.chM hj eubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjaZhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#i915_oa_stream_disable (C function)c.i915_oa_stream_disablehNtauh1jhjaZhhhNhNubj)}(hhh](j)}(h=void i915_oa_stream_disable (struct i915_perf_stream *stream)h]j)}(h)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjehhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjeubj )}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjeubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hj fhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj fubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjfmodnameN classnameNjj)}j]j)}jjesbc.i915_oa_stream_disableasbuh1hhjeubj )}(h h]h }(hj-fhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjeubj)}(hjh]h*}(hj;fhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj)}(hstreamh]hstream}(hjHfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjeubah}(h]h ]h"]h$]h&]j5j6uh1j7hjehhhjehM+ ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjehhhjehM+ ubah}(h]jeah ](jjeh"]h$]h&]jj)jhuh1jhjehM+ hjehhubj)}(hhh]h)}(h.handle `I915_PERF_IOCTL_DISABLE` for OA streamh](hhandle }(hjrfhhhNhNubjc)}(h`I915_PERF_IOCTL_DISABLE`h]hI915_PERF_IOCTL_DISABLE}(hjzfhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjrfubh for OA stream}(hjrfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:481: ./drivers/gpu/drm/i915/i915_perf.chM+ hjofhhubah}(h]h ]h"]h$]h&]uh1jhjehhhjehM+ ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjfjjfjjjuh1jhhhjaZhNhNubj)}(hX<**Parameters** ``struct i915_perf_stream *stream`` An i915 perf stream opened for OA metrics **Description** Stops the OA unit from periodically writing counter reports into the circular OA buffer. This also stops the hrtimer that periodically checks for data in the circular OA buffer, for notifying userspace.h](h)}(h**Parameters**h]j)}(hjfh]h Parameters}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:481: ./drivers/gpu/drm/i915/i915_perf.chM/ hjfubj)}(hhh]j)}(hN``struct i915_perf_stream *stream`` An i915 perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjfh]hstruct i915_perf_stream *stream}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjfubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:481: ./drivers/gpu/drm/i915/i915_perf.chM, hjfubj@)}(hhh]h)}(h)An i915 perf stream opened for OA metricsh]h)An i915 perf stream opened for OA metrics}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhM, hjfubah}(h]h ]h"]h$]h&]uh1j?hjfubeh}(h]h ]h"]h$]h&]uh1jhjfhM, hjfubah}(h]h ]h"]h$]h&]uh1jhjfubh)}(h**Description**h]j)}(hjgh]h Description}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:481: ./drivers/gpu/drm/i915/i915_perf.chM. hjfubh)}(hStops the OA unit from periodically writing counter reports into the circular OA buffer. This also stops the hrtimer that periodically checks for data in the circular OA buffer, for notifying userspace.h]hStops the OA unit from periodically writing counter reports into the circular OA buffer. This also stops the hrtimer that periodically checks for data in the circular OA buffer, for notifying userspace.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:481: ./drivers/gpu/drm/i915/i915_perf.chM- hjfubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjaZhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_oa_wait_unlocked (C function)c.i915_oa_wait_unlockedhNtauh1jhjaZhhhNhNubj)}(hhh](j)}(h;int i915_oa_wait_unlocked (struct i915_perf_stream *stream)h]j)}(h:int i915_oa_wait_unlocked(struct i915_perf_stream *stream)h](jn)}(hinth]hint}(hjEghhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjAghhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjTghhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjAghhhjSghMubj)}(hi915_oa_wait_unlockedh]j)}(hi915_oa_wait_unlockedh]hi915_oa_wait_unlocked}(hjfghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbgubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjAghhhjSghMubj8)}(h!(struct i915_perf_stream *stream)h]j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjghhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj~gubj )}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj~gubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjgmodnameN classnameNjj)}j]j)}jjhgsbc.i915_oa_wait_unlockedasbuh1hhj~gubj )}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj~gubj)}(hjh]h*}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~gubj)}(hstreamh]hstream}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~gubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjzgubah}(h]h ]h"]h$]h&]j5j6uh1j7hjAghhhjSghMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj=ghhhjSghMubah}(h]j8gah ](jjeh"]h$]h&]jj)jhuh1jhjSghMhj:ghhubj)}(hhh]h)}(h+handles blocking IO until OA data availableh]h+handles blocking IO until OA data available}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhjhhhubah}(h]h ]h"]h$]h&]uh1jhj:ghhhjSghMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjhjjhjjjuh1jhhhjaZhNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics **Description** Called when userspace tries to read() from a blocking stream FD opened for OA metrics. It waits until the hrtimer callback finds a non-empty OA buffer and wakes us. **Note** it's acceptable to have this return with some false positives since any subsequent read handling will return -EAGAIN if there isn't really data ready for userspace yet. **Return** zero on success or a negative error codeh](h)}(h**Parameters**h]j)}(hj'hh]h Parameters}(hj)hhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%hubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhj!hubj)}(hhh]j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjFhh]hstruct i915_perf_stream *stream}(hjHhhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjDhubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhj@hubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hj_hhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hhMhj\hubah}(h]h ]h"]h$]h&]uh1j?hj@hubeh}(h]h ]h"]h$]h&]uh1jhj[hhMhj=hubah}(h]h ]h"]h$]h&]uh1jhj!hubh)}(h**Description**h]j)}(hjhh]h Description}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhj!hubh)}(hCalled when userspace tries to read() from a blocking stream FD opened for OA metrics. It waits until the hrtimer callback finds a non-empty OA buffer and wakes us.h]hCalled when userspace tries to read() from a blocking stream FD opened for OA metrics. It waits until the hrtimer callback finds a non-empty OA buffer and wakes us.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhj!hubh)}(h**Note**h]j)}(hjhh]hNote}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhj!hubh)}(hit's acceptable to have this return with some false positives since any subsequent read handling will return -EAGAIN if there isn't really data ready for userspace yet.h]hit’s acceptable to have this return with some false positives since any subsequent read handling will return -EAGAIN if there isn’t really data ready for userspace yet.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhj!hubh)}(h **Return**h]j)}(hjhh]hReturn}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhj!hubh)}(h(zero on success or a negative error codeh]h(zero on success or a negative error code}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:483: ./drivers/gpu/drm/i915/i915_perf.chMhj!hubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjaZhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](ji915_oa_poll_wait (C function)c.i915_oa_poll_waithNtauh1jhjaZhhhNhNubj)}(hhh](j)}(h]void i915_oa_poll_wait (struct i915_perf_stream *stream, struct file *file, poll_table *wait)h]j)}(h\void i915_oa_poll_wait(struct i915_perf_stream *stream, struct file *file, poll_table *wait)h](jn)}(hvoidh]hvoid}(hjihhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjihhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:485: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hj#ihhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjihhhj"ihMubj)}(hi915_oa_poll_waith]j)}(hi915_oa_poll_waith]hi915_oa_poll_wait}(hj5ihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1iubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjihhhj"ihMubj8)}(hF(struct i915_perf_stream *stream, struct file *file, poll_table *wait)h](j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjQihhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjMiubj )}(h h]h }(hj^ihhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjMiubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjoihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjliubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjqimodnameN classnameNjj)}j]j)}jj7isbc.i915_oa_poll_waitasbuh1hhjMiubj )}(h h]h }(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjMiubj)}(hjh]h*}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMiubj)}(hstreamh]hstream}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMiubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjIiubj>)}(hstruct file *fileh](jD)}(hjGh]hstruct}(hjihhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjiubj )}(h h]h }(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjiubh)}(hhh]j)}(hfileh]hfile}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjimodnameN classnameNjj)}j]jic.i915_oa_poll_waitasbuh1hhjiubj )}(h h]h }(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjiubj)}(hjh]h*}(hj jhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubj)}(hfileh]hfile}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjIiubj>)}(hpoll_table *waith](h)}(hhh]j)}(h poll_tableh]h poll_table}(hj6jhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3jubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj8jmodnameN classnameNjj)}j]jic.i915_oa_poll_waitasbuh1hhj/jubj )}(h h]h }(hjTjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj/jubj)}(hjh]h*}(hjbjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/jubj)}(hwaith]hwait}(hjojhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/jubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjIiubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjihhhj"ihMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj ihhhj"ihMubah}(h]jiah ](jjeh"]h$]h&]jj)jhuh1jhj"ihMhj ihhubj)}(hhh]h)}(h(call poll_wait() for an OA stream poll()h]h(call poll_wait() for an OA stream poll()}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:485: ./drivers/gpu/drm/i915/i915_perf.chMhjjhhubah}(h]h ]h"]h$]h&]uh1jhj ihhhj"ihMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjjjuh1jhhhjaZhNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics ``struct file *file`` An i915 perf stream file ``poll_table *wait`` poll() state table **Description** For handling userspace polling on an i915 perf stream opened for OA metrics, this starts a poll_wait with the wait queue that our hrtimer callback wakes when it sees data ready to read in the circular OA buffer.h](h)}(h**Parameters**h]j)}(hjjh]h Parameters}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:485: ./drivers/gpu/drm/i915/i915_perf.chMhjjubj)}(hhh](j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjjh]hstruct i915_perf_stream *stream}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjjubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:485: ./drivers/gpu/drm/i915/i915_perf.chMhjjubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMhjjubah}(h]h ]h"]h$]h&]uh1j?hjjubeh}(h]h ]h"]h$]h&]uh1jhjjhMhjjubj)}(h/``struct file *file`` An i915 perf stream file h](j$)}(h``struct file *file``h]j*)}(hjkh]hstruct file *file}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjkubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:485: ./drivers/gpu/drm/i915/i915_perf.chMhj kubj@)}(hhh]h)}(hAn i915 perf stream fileh]hAn i915 perf stream file}(hj,khhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(khMhj)kubah}(h]h ]h"]h$]h&]uh1j?hj kubeh}(h]h ]h"]h$]h&]uh1jhj(khMhjjubj)}(h(``poll_table *wait`` poll() state table h](j$)}(h``poll_table *wait``h]j*)}(hjLkh]hpoll_table *wait}(hjNkhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjJkubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:485: ./drivers/gpu/drm/i915/i915_perf.chMhjFkubj@)}(hhh]h)}(hpoll() state tableh]hpoll() state table}(hjekhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjakhMhjbkubah}(h]h ]h"]h$]h&]uh1j?hjFkubeh}(h]h ]h"]h$]h&]uh1jhjakhMhjjubeh}(h]h ]h"]h$]h&]uh1jhjjubh)}(h**Description**h]j)}(hjkh]h Description}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:485: ./drivers/gpu/drm/i915/i915_perf.chMhjjubh)}(hFor handling userspace polling on an i915 perf stream opened for OA metrics, this starts a poll_wait with the wait queue that our hrtimer callback wakes when it sees data ready to read in the circular OA buffer.h]hFor handling userspace polling on an i915 perf stream opened for OA metrics, this starts a poll_wait with the wait queue that our hrtimer callback wakes when it sees data ready to read in the circular OA buffer.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:485: ./drivers/gpu/drm/i915/i915_perf.chMhjjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjaZhhhNhNubeh}(h])i915-perf-observation-architecture-streamah ]h"])i915 perf observation architecture streamah$]h&]uh1hhj#hhhhhMubh)}(hhh](h)}(hOther i915 Perf Internalsh]hOther i915 Perf Internals}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubh)}(hThis section simply includes all other currently documented i915 perf internals, in no particular order, but may include some more minor utilities or platform specific details than found in the more high-level sections.h]hThis section simply includes all other currently documented i915 perf internals, in no particular order, but may include some more minor utilities or platform specific details than found in the more high-level sections.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjkhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jperf_open_properties (C struct)c.perf_open_propertieshNtauh1jhjkhhhNhNubj)}(hhh](j)}(hperf_open_propertiesh]j)}(hstruct perf_open_propertiesh](jD)}(hjGh]hstruct}(hjkhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjkhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chKubj )}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjkhhhjlhKubj)}(hperf_open_propertiesh]j)}(hjkh]hperf_open_properties}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjkhhhjlhKubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjkhhhjlhKubah}(h]jkah ](jjeh"]h$]h&]jj)jhuh1jhjlhKhjkhhubj)}(hhh]h)}(h/for validated properties given to open a streamh]h/for validated properties given to open a stream}(hj5lhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMXhj2lhhubah}(h]h ]h"]h$]h&]uh1jhjkhhhjlhKubeh}(h]h ](jstructeh"]h$]h&]jjjjMljjMljjjuh1jhhhjkhNhNubj)}(hXW**Definition**:: struct perf_open_properties { u32 sample_flags; u64 single_context:1; u64 hold_preemption:1; u64 ctx_handle; int metrics_set; int oa_format; bool oa_periodic; int oa_period_exponent; struct intel_engine_cs *engine; bool has_sseu; struct intel_sseu sseu; u64 poll_oa_period; }; **Members** ``sample_flags`` `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags ``single_context`` Whether a single or all gpu contexts should be monitored ``hold_preemption`` Whether the preemption is disabled for the filtered context ``ctx_handle`` A gem ctx handle for use with **single_context** ``metrics_set`` An ID for an OA unit metric set advertised via sysfs ``oa_format`` An OA unit HW report format ``oa_periodic`` Whether to enable periodic OA unit sampling ``oa_period_exponent`` The OA unit sampling period is derived from this ``engine`` The engine (typically rcs0) being monitored by the OA unit ``has_sseu`` Whether **sseu** was specified by userspace ``sseu`` internal SSEU configuration computed either from the userspace specified configuration in the opening parameters or a default value (see get_default_sseu_config()) ``poll_oa_period`` The period in nanoseconds at which the CPU will check for OA data availabilityh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjYlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUlubh:}(hjUlhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM\hjQlubjA#)}(hXDstruct perf_open_properties { u32 sample_flags; u64 single_context:1; u64 hold_preemption:1; u64 ctx_handle; int metrics_set; int oa_format; bool oa_periodic; int oa_period_exponent; struct intel_engine_cs *engine; bool has_sseu; struct intel_sseu sseu; u64 poll_oa_period; };h]hXDstruct perf_open_properties { u32 sample_flags; u64 single_context:1; u64 hold_preemption:1; u64 ctx_handle; int metrics_set; int oa_format; bool oa_periodic; int oa_period_exponent; struct intel_engine_cs *engine; bool has_sseu; struct intel_sseu sseu; u64 poll_oa_period; };}hjrlsbah}(h]h ]h"]h$]h&]j5j6uh1j@#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM^hjQlubh)}(h **Members**h]j)}(hjlh]hMembers}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMmhjQlubj)}(hhh](j)}(hO``sample_flags`` `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags h](j$)}(h``sample_flags``h]j*)}(hjlh]h sample_flags}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjlubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMZhjlubj@)}(hhh]h)}(h=`DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flagsh](jc)}(h`DRM_I915_PERF_PROP_SAMPLE_*`h]hDRM_I915_PERF_PROP_SAMPLE_*}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjlubh properties are tracked as flags}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjlhMZhjlubah}(h]h ]h"]h$]h&]uh1j?hjlubeh}(h]h ]h"]h$]h&]uh1jhjlhMZhjlubj)}(hL``single_context`` Whether a single or all gpu contexts should be monitored h](j$)}(h``single_context``h]j*)}(hjlh]hsingle_context}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjlubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM[hjlubj@)}(hhh]h)}(h8Whether a single or all gpu contexts should be monitoredh]h8Whether a single or all gpu contexts should be monitored}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhM[hjlubah}(h]h ]h"]h$]h&]uh1j?hjlubeh}(h]h ]h"]h$]h&]uh1jhjlhM[hjlubj)}(hP``hold_preemption`` Whether the preemption is disabled for the filtered context h](j$)}(h``hold_preemption``h]j*)}(hj"mh]hhold_preemption}(hj$mhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj mubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM]hjmubj@)}(hhh]h)}(h;Whether the preemption is disabled for the filtered contexth]h;Whether the preemption is disabled for the filtered context}(hj;mhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM\hj8mubah}(h]h ]h"]h$]h&]uh1j?hjmubeh}(h]h ]h"]h$]h&]uh1jhj7mhM]hjlubj)}(h@``ctx_handle`` A gem ctx handle for use with **single_context** h](j$)}(h``ctx_handle``h]j*)}(hj\mh]h ctx_handle}(hj^mhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjZmubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM^hjVmubj@)}(hhh]h)}(h0A gem ctx handle for use with **single_context**h](hA gem ctx handle for use with }(hjumhhhNhNubj)}(h**single_context**h]hsingle_context}(hj}mhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjumubeh}(h]h ]h"]h$]h&]uh1hhjqmhM^hjrmubah}(h]h ]h"]h$]h&]uh1j?hjVmubeh}(h]h ]h"]h$]h&]uh1jhjqmhM^hjlubj)}(hE``metrics_set`` An ID for an OA unit metric set advertised via sysfs h](j$)}(h``metrics_set``h]j*)}(hjmh]h metrics_set}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjmubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM_hjmubj@)}(hhh]h)}(h4An ID for an OA unit metric set advertised via sysfsh]h4An ID for an OA unit metric set advertised via sysfs}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhM_hjmubah}(h]h ]h"]h$]h&]uh1j?hjmubeh}(h]h ]h"]h$]h&]uh1jhjmhM_hjlubj)}(h*``oa_format`` An OA unit HW report format h](j$)}(h ``oa_format``h]j*)}(hjmh]h oa_format}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjmubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM`hjmubj@)}(hhh]h)}(hAn OA unit HW report formath]hAn OA unit HW report format}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhM`hjmubah}(h]h ]h"]h$]h&]uh1j?hjmubeh}(h]h ]h"]h$]h&]uh1jhjmhM`hjlubj)}(h<``oa_periodic`` Whether to enable periodic OA unit sampling h](j$)}(h``oa_periodic``h]j*)}(hjnh]h oa_periodic}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjnubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMahjnubj@)}(hhh]h)}(h+Whether to enable periodic OA unit samplingh]h+Whether to enable periodic OA unit sampling}(hj.nhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*nhMahj+nubah}(h]h ]h"]h$]h&]uh1j?hjnubeh}(h]h ]h"]h$]h&]uh1jhj*nhMahjlubj)}(hH``oa_period_exponent`` The OA unit sampling period is derived from this h](j$)}(h``oa_period_exponent``h]j*)}(hjNnh]hoa_period_exponent}(hjPnhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjLnubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMbhjHnubj@)}(hhh]h)}(h0The OA unit sampling period is derived from thish]h0The OA unit sampling period is derived from this}(hjgnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjcnhMbhjdnubah}(h]h ]h"]h$]h&]uh1j?hjHnubeh}(h]h ]h"]h$]h&]uh1jhjcnhMbhjlubj)}(hF``engine`` The engine (typically rcs0) being monitored by the OA unit h](j$)}(h ``engine``h]j*)}(hjnh]hengine}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjnubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMchjnubj@)}(hhh]h)}(h:The engine (typically rcs0) being monitored by the OA unith]h:The engine (typically rcs0) being monitored by the OA unit}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMchjnubah}(h]h ]h"]h$]h&]uh1j?hjnubeh}(h]h ]h"]h$]h&]uh1jhjnhMchjlubj)}(h9``has_sseu`` Whether **sseu** was specified by userspace h](j$)}(h ``has_sseu``h]j*)}(hjnh]hhas_sseu}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjnubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMdhjnubj@)}(hhh]h)}(h+Whether **sseu** was specified by userspaceh](hWhether }(hjnhhhNhNubj)}(h**sseu**h]hsseu}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubh was specified by userspace}(hjnhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjnhMdhjnubah}(h]h ]h"]h$]h&]uh1j?hjnubeh}(h]h ]h"]h$]h&]uh1jhjnhMdhjlubj)}(h``sseu`` internal SSEU configuration computed either from the userspace specified configuration in the opening parameters or a default value (see get_default_sseu_config()) h](j$)}(h``sseu``h]j*)}(hj oh]hsseu}(hj ohhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj oubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMghjoubj@)}(hhh]h)}(hinternal SSEU configuration computed either from the userspace specified configuration in the opening parameters or a default value (see get_default_sseu_config())h]hinternal SSEU configuration computed either from the userspace specified configuration in the opening parameters or a default value (see get_default_sseu_config())}(hj$ohhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMehj!oubah}(h]h ]h"]h$]h&]uh1j?hjoubeh}(h]h ]h"]h$]h&]uh1jhj ohMghjlubj)}(ha``poll_oa_period`` The period in nanoseconds at which the CPU will check for OA data availabilityh](j$)}(h``poll_oa_period``h]j*)}(hjEoh]hpoll_oa_period}(hjGohhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjCoubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhhj?oubj@)}(hhh]h)}(hNThe period in nanoseconds at which the CPU will check for OA data availabilityh]hNThe period in nanoseconds at which the CPU will check for OA data availability}(hj^ohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZohMhhj[oubah}(h]h ]h"]h$]h&]uh1j?hj?oubeh}(h]h ]h"]h$]h&]uh1jhjZohMhhjlubeh}(h]h ]h"]h$]h&]uh1jhjQlubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubh)}(h**Description**h]j)}(hjoh]h Description}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMlhjkhhubh)}(hAs read_properties_unlocked() enumerates and validates the properties given to open a stream of metrics the configuration is built up in the structure which starts out zero initialized.h]hAs read_properties_unlocked() enumerates and validates the properties given to open a stream of metrics the configuration is built up in the structure which starts out zero initialized.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMihjkhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%oa_buffer_check_unlocked (C function)c.oa_buffer_check_unlockedhNtauh1jhjkhhhNhNubj)}(hhh](j)}(h?bool oa_buffer_check_unlocked (struct i915_perf_stream *stream)h]j)}(h>bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)h](jn)}(hjqh]hbool}(hjohhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjohhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM ubj )}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjohhhjohM ubj)}(hoa_buffer_check_unlockedh]j)}(hoa_buffer_check_unlockedh]hoa_buffer_check_unlocked}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjohhhjohM ubj8)}(h!(struct i915_perf_stream *stream)h]j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjphhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjoubj )}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjoubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj!pmodnameN classnameNjj)}j]j)}jjosbc.oa_buffer_check_unlockedasbuh1hhjoubj )}(h h]h }(hj?phhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjoubj)}(hjh]h*}(hjMphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hstreamh]hstream}(hjZphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjoubah}(h]h ]h"]h$]h&]j5j6uh1j7hjohhhjohM ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjohhhjohM ubah}(h]joah ](jjeh"]h$]h&]jj)jhuh1jhjohM hjohhubj)}(hhh]h)}(h(check for data and update tail ptr stateh]h(check for data and update tail ptr state}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM hjphhubah}(h]h ]h"]h$]h&]uh1jhjohhhjohM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjpjjpjjjuh1jhhhjkhNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` i915 stream instance **Description** This is either called via fops (for blocking reads in user ctx) or the poll check hrtimer (atomic ctx) to check the OA buffer tail pointer and check if there is data available for userspace to read. This function is central to providing a workaround for the OA unit tail pointer having a race with respect to what data is visible to the CPU. It is responsible for reading tail pointers from the hardware and giving the pointers time to 'age' before they are made available for reading. (See description of OA_TAIL_MARGIN_NSEC above for further details.) Besides returning true when there is data available to read() this function also updates the tail in the oa_buffer object. **Note** It's safe to read OA config state here unlocked, assuming that this is only called while the stream is enabled, while the global OA configuration can't be modified. **Return** ``true`` if the OA buffer contains data, else ``false``h](h)}(h**Parameters**h]j)}(hjph]h Parameters}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM hjpubj)}(hhh]j)}(h9``struct i915_perf_stream *stream`` i915 stream instance h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjph]hstruct i915_perf_stream *stream}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjpubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM hjpubj@)}(hhh]h)}(hi915 stream instanceh]hi915 stream instance}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphM hjpubah}(h]h ]h"]h$]h&]uh1j?hjpubeh}(h]h ]h"]h$]h&]uh1jhjphM hjpubah}(h]h ]h"]h$]h&]uh1jhjpubh)}(h**Description**h]j)}(hjqh]h Description}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM hjpubh)}(hThis is either called via fops (for blocking reads in user ctx) or the poll check hrtimer (atomic ctx) to check the OA buffer tail pointer and check if there is data available for userspace to read.h]hThis is either called via fops (for blocking reads in user ctx) or the poll check hrtimer (atomic ctx) to check the OA buffer tail pointer and check if there is data available for userspace to read.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM hjpubh)}(hXbThis function is central to providing a workaround for the OA unit tail pointer having a race with respect to what data is visible to the CPU. It is responsible for reading tail pointers from the hardware and giving the pointers time to 'age' before they are made available for reading. (See description of OA_TAIL_MARGIN_NSEC above for further details.)h]hXfThis function is central to providing a workaround for the OA unit tail pointer having a race with respect to what data is visible to the CPU. It is responsible for reading tail pointers from the hardware and giving the pointers time to ‘age’ before they are made available for reading. (See description of OA_TAIL_MARGIN_NSEC above for further details.)}(hj%qhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjpubh)}(hzBesides returning true when there is data available to read() this function also updates the tail in the oa_buffer object.h]hzBesides returning true when there is data available to read() this function also updates the tail in the oa_buffer object.}(hj4qhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjpubh)}(h**Note**h]j)}(hjEqh]hNote}(hjGqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCqubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjpubh)}(hIt's safe to read OA config state here unlocked, assuming that this is only called while the stream is enabled, while the global OA configuration can't be modified.h]hIt’s safe to read OA config state here unlocked, assuming that this is only called while the stream is enabled, while the global OA configuration can’t be modified.}(hj[qhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjpubh)}(h **Return**h]j)}(hjlqh]hReturn}(hjnqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjqubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjpubh)}(h7``true`` if the OA buffer contains data, else ``false``h](j*)}(h``true``h]htrue}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjqubh& if the OA buffer contains data, else }(hjqhhhNhNubj*)}(h ``false``h]hfalse}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjqubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjpubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jappend_oa_status (C function)c.append_oa_statushNtauh1jhjkhhhNhNubj)}(hhh](j)}(hint append_oa_status (struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset, enum drm_i915_perf_record_type type)h]j)}(hint append_oa_status(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset, enum drm_i915_perf_record_type type)h](jn)}(hinth]hint}(hjqhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjqhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMfubj )}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjqhhhjqhMfubj)}(happend_oa_statush]j)}(happend_oa_statush]happend_oa_status}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjqhhhjqhMfubj8)}(hv(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset, enum drm_i915_perf_record_type type)h](j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hj rhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjrubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjrubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hj(rhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%rubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj*rmodnameN classnameNjj)}j]j)}jjqsbc.append_oa_statusasbuh1hhjrubj )}(h h]h }(hjHrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjrubj)}(hjh]h*}(hjVrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(hstreamh]hstream}(hjcrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(hchar __user *bufh](jn)}(hcharh]hchar}(hj|rhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjxrubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjxrubh__user}(hjxrhhhNhNubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjxrubj)}(hjh]h*}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxrubj)}(hbufh]hbuf}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxrubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(h size_t counth](h)}(hhh]j)}(hsize_th]hsize_t}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjrmodnameN classnameNjj)}j]jDrc.append_oa_statusasbuh1hhjrubj )}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjrubj)}(hcounth]hcount}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(hsize_t *offseth](h)}(hhh]j)}(hsize_th]hsize_t}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjsmodnameN classnameNjj)}j]jDrc.append_oa_statusasbuh1hhjsubj )}(h h]h }(hj9shhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjsubj)}(hjh]h*}(hjGshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj)}(hoffseth]hoffset}(hjTshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubj>)}(h#enum drm_i915_perf_record_type typeh](jD)}(hjh]henum}(hjmshhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjisubj )}(h h]h }(hjzshhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjisubh)}(hhh]j)}(hdrm_i915_perf_record_typeh]hdrm_i915_perf_record_type}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjsmodnameN classnameNjj)}j]jDrc.append_oa_statusasbuh1hhjisubj )}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjisubj)}(htypeh]htype}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjisubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjrubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjqhhhjqhMfubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjqhhhjqhMfubah}(h]jqah ](jjeh"]h$]h&]jj)jhuh1jhjqhMfhjqhhubj)}(hhh]h)}(h5Appends a status record to a userspace read() buffer.h]h5Appends a status record to a userspace read() buffer.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMfhjshhubah}(h]h ]h"]h$]h&]uh1jhjqhhhjqhMfubeh}(h]h ](jfunctioneh"]h$]h&]jjjjsjjsjjjuh1jhhhjkhNhNubj)}(hXn**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics ``char __user *buf`` destination buffer given by userspace ``size_t count`` the number of bytes userspace wants to read ``size_t *offset`` (inout): the current position for writing into **buf** ``enum drm_i915_perf_record_type type`` The kind of status to report to userspace **Description** Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`) into the userspace read() buffer. The **buf** **offset** will only be updated on success. **Return** 0 on success, negative error code on failure.h](h)}(h**Parameters**h]j)}(hjth]h Parameters}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMjhjsubj)}(hhh](j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hj"th]hstruct i915_perf_stream *stream}(hj$thhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj tubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMghjtubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hj;thhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7thMghj8tubah}(h]h ]h"]h$]h&]uh1j?hjtubeh}(h]h ]h"]h$]h&]uh1jhj7thMghjtubj)}(h;``char __user *buf`` destination buffer given by userspace h](j$)}(h``char __user *buf``h]j*)}(hj[th]hchar __user *buf}(hj]thhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjYtubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhhjUtubj@)}(hhh]h)}(h%destination buffer given by userspaceh]h%destination buffer given by userspace}(hjtthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpthMhhjqtubah}(h]h ]h"]h$]h&]uh1j?hjUtubeh}(h]h ]h"]h$]h&]uh1jhjpthMhhjtubj)}(h=``size_t count`` the number of bytes userspace wants to read h](j$)}(h``size_t count``h]j*)}(hjth]h size_t count}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjtubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMihjtubj@)}(hhh]h)}(h+the number of bytes userspace wants to readh]h+the number of bytes userspace wants to read}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMihjtubah}(h]h ]h"]h$]h&]uh1j?hjtubeh}(h]h ]h"]h$]h&]uh1jhjthMihjtubj)}(hJ``size_t *offset`` (inout): the current position for writing into **buf** h](j$)}(h``size_t *offset``h]j*)}(hjth]hsize_t *offset}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjtubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMjhjtubj@)}(hhh]h)}(h6(inout): the current position for writing into **buf**h](h/(inout): the current position for writing into }(hjthhhNhNubj)}(h**buf**h]hbuf}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1hhjthMjhjtubah}(h]h ]h"]h$]h&]uh1j?hjtubeh}(h]h ]h"]h$]h&]uh1jhjthMjhjtubj)}(hR``enum drm_i915_perf_record_type type`` The kind of status to report to userspace h](j$)}(h'``enum drm_i915_perf_record_type type``h]j*)}(hjuh]h#enum drm_i915_perf_record_type type}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjuubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMkhjuubj@)}(hhh]h)}(h)The kind of status to report to userspaceh]h)The kind of status to report to userspace}(hj-uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)uhMkhj*uubah}(h]h ]h"]h$]h&]uh1j?hjuubeh}(h]h ]h"]h$]h&]uh1jhj)uhMkhjtubeh}(h]h ]h"]h$]h&]uh1jhjsubh)}(h**Description**h]j)}(hjOuh]h Description}(hjQuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMuubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMmhjsubh)}(hhWrites a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`) into the userspace read() buffer.h](h Writes a status record (such as }(hjeuhhhNhNubjc)}(h%`DRM_I915_PERF_RECORD_OA_REPORT_LOST`h]h#DRM_I915_PERF_RECORD_OA_REPORT_LOST}(hjmuhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjeuubh#) into the userspace read() buffer.}(hjeuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMlhjsubh)}(h7The **buf** **offset** will only be updated on success.h](hThe }(hjuhhhNhNubj)}(h**buf**h]hbuf}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubh }(hjuhhhNhNubj)}(h **offset**h]hoffset}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubh! will only be updated on success.}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMohjsubh)}(h **Return**h]j)}(hjuh]hReturn}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMqhjsubh)}(h-0 on success, negative error code on failure.h]h-0 on success, negative error code on failure.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMrhjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jappend_oa_sample (C function)c.append_oa_samplehNtauh1jhjkhhhNhNubj)}(hhh](j)}(hxint append_oa_sample (struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset, const u8 *report)h]j)}(hwint append_oa_sample(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset, const u8 *report)h](jn)}(hinth]hint}(hjvhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjuhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjuhhhjvhMubj)}(happend_oa_sampleh]j)}(happend_oa_sampleh]happend_oa_sample}(hj!vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjuhhhjvhMubj8)}(hc(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset, const u8 *report)h](j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hj=vhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj9vubj )}(h h]h }(hjJvhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj9vubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hj[vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXvubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj]vmodnameN classnameNjj)}j]j)}jj#vsbc.append_oa_sampleasbuh1hhj9vubj )}(h h]h }(hj{vhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj9vubj)}(hjh]h*}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9vubj)}(hstreamh]hstream}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9vubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj5vubj>)}(hchar __user *bufh](jn)}(hcharh]hchar}(hjvhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjvubj )}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjvubh__user}(hjvhhhNhNubj )}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjvubj)}(hjh]h*}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(hbufh]hbuf}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj5vubj>)}(h size_t counth](h)}(hhh]j)}(hsize_th]hsize_t}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjwmodnameN classnameNjj)}j]jwvc.append_oa_sampleasbuh1hhjvubj )}(h h]h }(hj$whhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjvubj)}(hcounth]hcount}(hj2whhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj5vubj>)}(hsize_t *offseth](h)}(hhh]j)}(hsize_th]hsize_t}(hjNwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjPwmodnameN classnameNjj)}j]jwvc.append_oa_sampleasbuh1hhjGwubj )}(h h]h }(hjlwhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjGwubj)}(hjh]h*}(hjzwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGwubj)}(hoffseth]hoffset}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGwubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj5vubj>)}(hconst u8 *reporth](jD)}(hconsth]hconst}(hjwhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjwubj )}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjwubh)}(hhh]j)}(hu8h]hu8}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjwmodnameN classnameNjj)}j]jwvc.append_oa_sampleasbuh1hhjwubj )}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjwubj)}(hjh]h*}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubj)}(hreporth]hreport}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj5vubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjuhhhjvhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjuhhhjvhMubah}(h]juah ](jjeh"]h$]h&]jj)jhuh1jhjvhMhjuhhubj)}(hhh]h)}(h5Copies single OA report into userspace read() buffer.h]h5Copies single OA report into userspace read() buffer.}(hj"xhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjxhhubah}(h]h ]h"]h$]h&]uh1jhjuhhhjvhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj:xjj:xjjjuh1jhhhjkhNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics ``char __user *buf`` destination buffer given by userspace ``size_t count`` the number of bytes userspace wants to read ``size_t *offset`` (inout): the current position for writing into **buf** ``const u8 *report`` A single OA report to (optionally) include as part of the sample **Description** The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*` properties when opening a stream, tracked as `stream->sample_flags`. This function copies the requested components of a single sample to the given read() **buf**. The **buf** **offset** will only be updated on success. **Return** 0 on success, negative error code on failure.h](h)}(h**Parameters**h]j)}(hjDxh]h Parameters}(hjFxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBxubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj>xubj)}(hhh](j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjcxh]hstruct i915_perf_stream *stream}(hjexhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjaxubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj]xubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hj|xhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxxhMhjyxubah}(h]h ]h"]h$]h&]uh1j?hj]xubeh}(h]h ]h"]h$]h&]uh1jhjxxhMhjZxubj)}(h;``char __user *buf`` destination buffer given by userspace h](j$)}(h``char __user *buf``h]j*)}(hjxh]hchar __user *buf}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjxubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjxubj@)}(hhh]h)}(h%destination buffer given by userspaceh]h%destination buffer given by userspace}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMhjxubah}(h]h ]h"]h$]h&]uh1j?hjxubeh}(h]h ]h"]h$]h&]uh1jhjxhMhjZxubj)}(h=``size_t count`` the number of bytes userspace wants to read h](j$)}(h``size_t count``h]j*)}(hjxh]h size_t count}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjxubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjxubj@)}(hhh]h)}(h+the number of bytes userspace wants to readh]h+the number of bytes userspace wants to read}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMhjxubah}(h]h ]h"]h$]h&]uh1j?hjxubeh}(h]h ]h"]h$]h&]uh1jhjxhMhjZxubj)}(hJ``size_t *offset`` (inout): the current position for writing into **buf** h](j$)}(h``size_t *offset``h]j*)}(hjyh]hsize_t *offset}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj yubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjyubj@)}(hhh]h)}(h6(inout): the current position for writing into **buf**h](h/(inout): the current position for writing into }(hj'yhhhNhNubj)}(h**buf**h]hbuf}(hj/yhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'yubeh}(h]h ]h"]h$]h&]uh1hhj#yhMhj$yubah}(h]h ]h"]h$]h&]uh1j?hjyubeh}(h]h ]h"]h$]h&]uh1jhj#yhMhjZxubj)}(hV``const u8 *report`` A single OA report to (optionally) include as part of the sample h](j$)}(h``const u8 *report``h]j*)}(hjUyh]hconst u8 *report}(hjWyhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjSyubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjOyubj@)}(hhh]h)}(h@A single OA report to (optionally) include as part of the sampleh]h@A single OA report to (optionally) include as part of the sample}(hjnyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjyhMhjkyubah}(h]h ]h"]h$]h&]uh1j?hjOyubeh}(h]h ]h"]h$]h&]uh1jhjjyhMhjZxubeh}(h]h ]h"]h$]h&]uh1jhj>xubh)}(h**Description**h]j)}(hjyh]h Description}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj>xubh)}(hThe contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*` properties when opening a stream, tracked as `stream->sample_flags`. This function copies the requested components of a single sample to the given read() **buf**.h](h0The contents of a sample are configured through }(hjyhhhNhNubjc)}(h`DRM_I915_PERF_PROP_SAMPLE_*`h]hDRM_I915_PERF_PROP_SAMPLE_*}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjyubh. properties when opening a stream, tracked as }(hjyhhhNhNubjc)}(h`stream->sample_flags`h]hstream->sample_flags}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjyubhW. This function copies the requested components of a single sample to the given read() }(hjyhhhNhNubj)}(h**buf**h]hbuf}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubh.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj>xubh)}(h7The **buf** **offset** will only be updated on success.h](hThe }(hjyhhhNhNubj)}(h**buf**h]hbuf}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubh }(hjyhhhNhNubj)}(h **offset**h]hoffset}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubh! will only be updated on success.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj>xubh)}(h **Return**h]j)}(hj zh]hReturn}(hj"zhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj>xubh)}(h-0 on success, negative error code on failure.h]h-0 on success, negative error code on failure.}(hj6zhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj>xubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#gen8_append_oa_reports (C function)c.gen8_append_oa_reportshNtauh1jhjkhhhNhNubj)}(hhh](j)}(hlint gen8_append_oa_reports (struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h]j)}(hkint gen8_append_oa_reports(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h](jn)}(hinth]hint}(hjezhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjazhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjtzhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjazhhhjszhMubj)}(hgen8_append_oa_reportsh]j)}(hgen8_append_oa_reportsh]hgen8_append_oa_reports}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjazhhhjszhMubj8)}(hQ(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h](j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjzhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjzubj )}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjzubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjzmodnameN classnameNjj)}j]j)}jjzsbc.gen8_append_oa_reportsasbuh1hhjzubj )}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjzubj)}(hjh]h*}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(hstreamh]hstream}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjzubj>)}(hchar __user *bufh](jn)}(hcharh]hchar}(hj{hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj{ubj )}(h h]h }(hj"{hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj{ubh__user}(hj{hhhNhNubj )}(h h]h }(hj4{hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj{ubj)}(hjh]h*}(hjB{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj)}(hbufh]hbuf}(hjO{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjzubj>)}(h size_t counth](h)}(hhh]j)}(hsize_th]hsize_t}(hjk{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjh{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjm{modnameN classnameNjj)}j]jzc.gen8_append_oa_reportsasbuh1hhjd{ubj )}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjd{ubj)}(hcounth]hcount}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjd{ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjzubj>)}(hsize_t *offseth](h)}(hhh]j)}(hsize_th]hsize_t}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj{modnameN classnameNjj)}j]jzc.gen8_append_oa_reportsasbuh1hhj{ubj )}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj{ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj)}(hoffseth]hoffset}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjzubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjazhhhjszhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj]zhhhjszhMubah}(h]jXzah ](jjeh"]h$]h&]jj)jhuh1jhjszhMhjZzhhubj)}(hhh]h)}(h)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hj?~hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj;~ubj )}(h h]h }(hjL~hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj;~ubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hj]~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZ~ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj_~modnameN classnameNjj)}j]j)}jj%~sbc.gen8_oa_readasbuh1hhj;~ubj )}(h h]h }(hj}~hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj;~ubj)}(hjh]h*}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;~ubj)}(hstreamh]hstream}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;~ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj7~ubj>)}(hchar __user *bufh](jn)}(hcharh]hchar}(hj~hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj~ubj )}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj~ubh__user}(hj~hhhNhNubj )}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj~ubj)}(hjh]h*}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(hbufh]hbuf}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj7~ubj>)}(h size_t counth](h)}(hhh]j)}(hsize_th]hsize_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jy~c.gen8_oa_readasbuh1hhjubj )}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hcounth]hcount}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj7~ubj>)}(hsize_t *offseth](h)}(hhh]j)}(hsize_th]hsize_t}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjRmodnameN classnameNjj)}j]jy~c.gen8_oa_readasbuh1hhjIubj )}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjIubj)}(hjh]h*}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj)}(hoffseth]hoffset}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hj7~ubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj}hhhj~hMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj}hhhj~hMubah}(h]j}ah ](jjeh"]h$]h&]jj)jhuh1jhj~hMhj}hhubj)}(hhh]h)}(h,copy status records then buffered OA reportsh]h,copy status records then buffered OA reports}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj}hhhj~hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjkhNhNubj)}(hX&**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics ``char __user *buf`` destination buffer given by userspace ``size_t count`` the number of bytes userspace wants to read ``size_t *offset`` (inout): the current position for writing into **buf** **Description** Checks OA unit status registers and if necessary appends corresponding status records for userspace (such as for a buffer full condition) and then initiate appending any buffered OA reports. Updates **offset** according to the number of bytes successfully copied into the userspace buffer. NB: some data may be successfully copied to the userspace buffer even if an error is returned, and this is reflected in the updated **offset**. **Return** zero on success or a negative error codeh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubj)}(hhh](j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjh]hstruct i915_perf_stream *stream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(h;``char __user *buf`` destination buffer given by userspace h](j$)}(h``char __user *buf``h]j*)}(hj-h]hchar __user *buf}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj+ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj'ubj@)}(hhh]h)}(h%destination buffer given by userspaceh]h%destination buffer given by userspace}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMhjCubah}(h]h ]h"]h$]h&]uh1j?hj'ubeh}(h]h ]h"]h$]h&]uh1jhjBhMhjubj)}(h=``size_t count`` the number of bytes userspace wants to read h](j$)}(h``size_t count``h]j*)}(hjfh]h size_t count}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjdubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhj`ubj@)}(hhh]h)}(h+the number of bytes userspace wants to readh]h+the number of bytes userspace wants to read}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hMhj|ubah}(h]h ]h"]h$]h&]uh1j?hj`ubeh}(h]h ]h"]h$]h&]uh1jhj{hMhjubj)}(hJ``size_t *offset`` (inout): the current position for writing into **buf** h](j$)}(h``size_t *offset``h]j*)}(hjh]hsize_t *offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubj@)}(hhh]h)}(h6(inout): the current position for writing into **buf**h](h/(inout): the current position for writing into }(hjhhhNhNubj)}(h**buf**h]hbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubh)}(hChecks OA unit status registers and if necessary appends corresponding status records for userspace (such as for a buffer full condition) and then initiate appending any buffered OA reports.h]hChecks OA unit status registers and if necessary appends corresponding status records for userspace (such as for a buffer full condition) and then initiate appending any buffered OA reports.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubh)}(hbUpdates **offset** according to the number of bytes successfully copied into the userspace buffer.h](hUpdates }(hj hhhNhNubj)}(h **offset**h]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhP according to the number of bytes successfully copied into the userspace buffer.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubh)}(hNB: some data may be successfully copied to the userspace buffer even if an error is returned, and this is reflected in the updated **offset**.h](hNB: some data may be successfully copied to the userspace buffer even if an error is returned, and this is reflected in the updated }(hj.hhhNhNubj)}(h **offset**h]hoffset}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubh)}(h **Return**h]j)}(hjQh]hReturn}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubh)}(h(zero on success or a negative error codeh]h(zero on success or a negative error code}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#gen7_append_oa_reports (C function)c.gen7_append_oa_reportshNtauh1jhjkhhhNhNubj)}(hhh](j)}(hlint gen7_append_oa_reports (struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h]j)}(hkint gen7_append_oa_reports(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h](jn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hgen7_append_oa_reportsh]j)}(hgen7_append_oa_reportsh]hgen7_append_oa_reports}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(hQ(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h](j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjӁhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjρubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjρubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.gen7_append_oa_reportsasbuh1hhjρubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjρubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjρubj)}(hstreamh]hstream}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjρubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjˁubj>)}(hchar __user *bufh](jn)}(hcharh]hchar}(hjEhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjAubj )}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjAubh__user}(hjAhhhNhNubj )}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjAubj)}(hjh]h*}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubj)}(hbufh]hbuf}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjˁubj>)}(h size_t counth](h)}(hhh]j)}(hsize_th]hsize_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j c.gen7_append_oa_reportsasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hcounth]hcount}(hjȂhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjˁubj>)}(hsize_t *offseth](h)}(hhh]j)}(hsize_th]hsize_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j c.gen7_append_oa_reportsasbuh1hhj݂ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj݂ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj݂ubj)}(hoffseth]hoffset}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj݂ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjˁubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjphhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjlubj )}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjlubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjVsbc.gen7_oa_readasbuh1hhjlubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjlubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubj)}(hstreamh]hstream}(hjɅhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjhubj>)}(hchar __user *bufh](jn)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjޅubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjޅubh__user}(hjޅhhhNhNubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjޅubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޅubj)}(hbufh]hbuf}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޅubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjhubj>)}(h size_t counth](h)}(hhh]j)}(hsize_th]hsize_t}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj;modnameN classnameNjj)}j]jc.gen7_oa_readasbuh1hhj2ubj )}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2ubj)}(hcounth]hcount}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjhubj>)}(hsize_t *offseth](h)}(hhh]j)}(hsize_th]hsize_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.gen7_oa_readasbuh1hhjzubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjzubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj)}(hoffseth]hoffset}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjhubeh}(h]h ]h"]h$]h&]j5j6uh1j7hj/hhhjAhMqubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj+hhhjAhMqubah}(h]j&ah ](jjeh"]h$]h&]jj)jhuh1jhjAhMqhj(hhubj)}(hhh]h)}(h,copy status records then buffered OA reportsh]h,copy status records then buffered OA reports}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMqhjhhubah}(h]h ]h"]h$]h&]uh1jhj(hhhjAhMqubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjkhNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics ``char __user *buf`` destination buffer given by userspace ``size_t count`` the number of bytes userspace wants to read ``size_t *offset`` (inout): the current position for writing into **buf** **Description** Checks Gen 7 specific OA unit status registers and if necessary appends corresponding status records for userspace (such as for a buffer full condition) and then initiate appending any buffered OA reports. Updates **offset** according to the number of bytes successfully copied into the userspace buffer. **Return** zero on success or a negative error codeh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMuhjubj)}(hhh](j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hj%h]hstruct i915_perf_stream *stream}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj#ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMrhjubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMrhj;ubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhj:hMrhjubj)}(h;``char __user *buf`` destination buffer given by userspace h](j$)}(h``char __user *buf``h]j*)}(hj^h]hchar __user *buf}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj\ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMshjXubj@)}(hhh]h)}(h%destination buffer given by userspaceh]h%destination buffer given by userspace}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMshjtubah}(h]h ]h"]h$]h&]uh1j?hjXubeh}(h]h ]h"]h$]h&]uh1jhjshMshjubj)}(h=``size_t count`` the number of bytes userspace wants to read h](j$)}(h``size_t count``h]j*)}(hjh]h size_t count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMthjubj@)}(hhh]h)}(h+the number of bytes userspace wants to readh]h+the number of bytes userspace wants to read}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMthjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMthjubj)}(hJ``size_t *offset`` (inout): the current position for writing into **buf** h](j$)}(h``size_t *offset``h]j*)}(hjЇh]hsize_t *offset}(hj҇hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj·ubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMuhjʇubj@)}(hhh]h)}(h6(inout): the current position for writing into **buf**h](h/(inout): the current position for writing into }(hjhhhNhNubj)}(h**buf**h]hbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMuhjubah}(h]h ]h"]h$]h&]uh1j?hjʇubeh}(h]h ]h"]h$]h&]uh1jhjhMuhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMwhjubh)}(hChecks Gen 7 specific OA unit status registers and if necessary appends corresponding status records for userspace (such as for a buffer full condition) and then initiate appending any buffered OA reports.h]hChecks Gen 7 specific OA unit status registers and if necessary appends corresponding status records for userspace (such as for a buffer full condition) and then initiate appending any buffered OA reports.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMvhjubh)}(hbUpdates **offset** according to the number of bytes successfully copied into the userspace buffer.h](hUpdates }(hj>hhhNhNubj)}(h **offset**h]hoffset}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubhP according to the number of bytes successfully copied into the userspace buffer.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMzhjubh)}(h **Return**h]j)}(hjah]hReturn}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM}hjubh)}(h(zero on success or a negative error codeh]h(zero on success or a negative error code}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM~hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!oa_get_render_ctx_id (C function)c.oa_get_render_ctx_idhNtauh1jhjkhhhNhNubj)}(hhh](j)}(h:int oa_get_render_ctx_id (struct i915_perf_stream *stream)h]j)}(h9int oa_get_render_ctx_id(struct i915_perf_stream *stream)h](jn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjhhhjhMubj)}(hoa_get_render_ctx_idh]j)}(hoa_get_render_ctx_idh]hoa_get_render_ctx_id}(hjLjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjÈubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjhhhjhMubj8)}(h!(struct i915_perf_stream *stream)h]j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChj߈ubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj߈ubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjɈsbc.oa_get_render_ctx_idasbuh1hhj߈ubj )}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj߈ubj)}(hjh]h*}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj߈ubj)}(hstreamh]hstream}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj߈ubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjۈubah}(h]h ]h"]h$]h&]j5j6uh1j7hjhhhjhMubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hdetermine and hold ctx hw idh]hdetermine and hold ctx hw id}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjchhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj~jj~jjjuh1jhhhjkhNhNubj)}(hXg**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics **Description** Determine the render context hw id, and ensure it remains fixed for the lifetime of the stream. This ensures that we don't have to worry about updating the context ID in OACONTROL on the fly. **Return** zero on success or a negative error codeh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubj)}(hhh]j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjh]hstruct i915_perf_stream *stream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubh)}(hDetermine the render context hw id, and ensure it remains fixed for the lifetime of the stream. This ensures that we don't have to worry about updating the context ID in OACONTROL on the fly.h]hDetermine the render context hw id, and ensure it remains fixed for the lifetime of the stream. This ensures that we don’t have to worry about updating the context ID in OACONTROL on the fly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubh)}(h **Return**h]j)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubh)}(h(zero on success or a negative error codeh]h(zero on success or a negative error code}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!oa_put_render_ctx_id (C function)c.oa_put_render_ctx_idhNtauh1jhjkhhhNhNubj)}(hhh](j)}(h;void oa_put_render_ctx_id (struct i915_perf_stream *stream)h]j)}(h:void oa_put_render_ctx_id(struct i915_perf_stream *stream)h](jn)}(hvoidh]hvoid}(hjNhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjJhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMJubj )}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjJhhhj\hMJubj)}(hoa_put_render_ctx_idh]j)}(hoa_put_render_ctx_idh]hoa_put_render_ctx_id}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjJhhhj\hMJubj8)}(h!(struct i915_perf_stream *stream)h]j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjqsbc.oa_put_render_ctx_idasbuh1hhjubj )}(h h]h }(hjɊhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hj׊hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hstreamh]hstream}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hjJhhhj\hMJubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjFhhhj\hMJubah}(h]jAah ](jjeh"]h$]h&]jj)jhuh1jhj\hMJhjChhubj)}(hhh]h)}(h1counterpart to oa_get_render_ctx_id releases holdh]h1counterpart to oa_get_render_ctx_id releases hold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMJhj hhubah}(h]h ]h"]h$]h&]uh1jhjChhhj\hMJubeh}(h]h ](jfunctioneh"]h$]h&]jjjj&jj&jjjuh1jhhhjkhNhNubj)}(h**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics **Description** In case anything needed doing to ensure the context HW ID would remain valid for the lifetime of the stream, then that can be undone here.h](h)}(h**Parameters**h]j)}(hj0h]h Parameters}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMNhj*ubj)}(hhh]j)}(hN``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjOh]hstruct i915_perf_stream *stream}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjMubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMKhjIubj@)}(hhh]h)}(h)An i915-perf stream opened for OA metricsh]h)An i915-perf stream opened for OA metrics}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMKhjeubah}(h]h ]h"]h$]h&]uh1j?hjIubeh}(h]h ]h"]h$]h&]uh1jhjdhMKhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMMhj*ubh)}(hIn case anything needed doing to ensure the context HW ID would remain valid for the lifetime of the stream, then that can be undone here.h]hIn case anything needed doing to ensure the context HW ID would remain valid for the lifetime of the stream, then that can be undone here.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMLhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#i915_perf_ioctl_locked (C function)c.i915_perf_ioctl_lockedhNtauh1jhjkhhhNhNubj)}(hhh](j)}(hblong i915_perf_ioctl_locked (struct i915_perf_stream *stream, unsigned int cmd, unsigned long arg)h]j)}(halong i915_perf_ioctl_locked(struct i915_perf_stream *stream, unsigned int cmd, unsigned long arg)h](jn)}(hlongh]hlong}(hjϋhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjˋhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM?ubj )}(h h]h }(hjދhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjˋhhhj݋hM?ubj)}(hi915_perf_ioctl_lockedh]j)}(hi915_perf_ioctl_lockedh]hi915_perf_ioctl_locked}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhjˋhhhj݋hM?ubj8)}(hF(struct i915_perf_stream *stream, unsigned int cmd, unsigned long arg)h](j>)}(hstruct i915_perf_stream *streamh](jD)}(hjGh]hstruct}(hj hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hi915_perf_streamh]hi915_perf_stream}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj,modnameN classnameNjj)}j]j)}jjsbc.i915_perf_ioctl_lockedasbuh1hhjubj )}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hstreamh]hstream}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hunsigned int cmdh](jn)}(hunsignedh]hunsigned}(hj~hhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjzubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjzubjn)}(hinth]hint}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjzubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjzubj)}(hcmdh]hcmd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubj>)}(hunsigned long argh](jn)}(hunsignedh]hunsigned}(hjόhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjˌubj )}(h h]h }(hj݌hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjˌubjn)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhjˌubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjˌubj)}(hargh]harg}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjˌubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubeh}(h]h ]h"]h$]h&]j5j6uh1j7hjˋhhhj݋hM?ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhjNjhhhj݋hM?ubah}(h]j‹ah ](jjeh"]h$]h&]jj)jhuh1jhj݋hM?hjċhhubj)}(hhh]h)}(h/support ioctl() usage with i915 perf stream FDsh]h/support ioctl() usage with i915 perf stream FDs}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM?hj.hhubah}(h]h ]h"]h$]h&]uh1jhjċhhhj݋hM?ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjIjjIjjjuh1jhhhjkhNhNubj)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915 perf stream ``unsigned int cmd`` the ioctl request ``unsigned long arg`` the ioctl data **Return** zero on success or a negative error code. Returns -EINVAL for an unknown ioctl request.h](h)}(h**Parameters**h]j)}(hjSh]h Parameters}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMChjMubj)}(hhh](j)}(h8``struct i915_perf_stream *stream`` An i915 perf stream h](j$)}(h#``struct i915_perf_stream *stream``h]j*)}(hjrh]hstruct i915_perf_stream *stream}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjpubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM@hjlubj@)}(hhh]h)}(hAn i915 perf streamh]hAn i915 perf stream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM@hjubah}(h]h ]h"]h$]h&]uh1j?hjlubeh}(h]h ]h"]h$]h&]uh1jhjhM@hjiubj)}(h'``unsigned int cmd`` the ioctl request h](j$)}(h``unsigned int cmd``h]j*)}(hjh]hunsigned int cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMAhjubj@)}(hhh]h)}(hthe ioctl requesth]hthe ioctl request}(hjčhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMAhjubah}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjhMAhjiubj)}(h%``unsigned long arg`` the ioctl data h](j$)}(h``unsigned long arg``h]j*)}(hjh]hunsigned long arg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMBhjލubj@)}(hhh]h)}(hthe ioctl datah]hthe ioctl data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMBhjubah}(h]h ]h"]h$]h&]uh1j?hjލubeh}(h]h ]h"]h$]h&]uh1jhjhMBhjiubeh}(h]h ]h"]h$]h&]uh1jhjMubh)}(h **Return**h]j)}(hjh]hReturn}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMDhjMubh)}(hWzero on success or a negative error code. Returns -EINVAL for an unknown ioctl request.h]hWzero on success or a negative error code. Returns -EINVAL for an unknown ioctl request.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMDhjMubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$i915_perf_ioctl_version (C function)c.i915_perf_ioctl_versionhNtauh1jhjkhhhNhNubj)}(hhh](j)}(h;int i915_perf_ioctl_version (struct drm_i915_private *i915)h]j)}(h:int i915_perf_ioctl_version(struct drm_i915_private *i915)h](jn)}(hinth]hint}(hjdhhhNhNubah}(h]h ]jzah"]h$]h&]uh1jmhj`hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM_ubj )}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj`hhhjrhM_ubj)}(hi915_perf_ioctl_versionh]j)}(hi915_perf_ioctl_versionh]hi915_perf_ioctl_version}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j0j1eh"]h$]h&]j5j6uh1jhj`hhhjrhM_ubj8)}(h(struct drm_i915_private *i915)h]j>)}(hstruct drm_i915_private *i915h](jD)}(hjGh]hstruct}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jChjubj )}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubh)}(hhh]j)}(hdrm_i915_privateh]hdrm_i915_private}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.i915_perf_ioctl_versionasbuh1hhjubj )}(h h]h }(hjߎhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hi915h]hi915}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj5j6uh1j=hjubah}(h]h ]h"]h$]h&]j5j6uh1j7hj`hhhjrhM_ubeh}(h]h ]h"]h$]h&]j5j6juh1jjjhj\hhhjrhM_ubah}(h]jWah ](jjeh"]h$]h&]jj)jhuh1jhjrhM_hjYhhubj)}(hhh]h)}(h"Version of the i915-perf subsystemh]h"Version of the i915-perf subsystem}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM_hj!hhubah}(h]h ]h"]h$]h&]uh1jhjYhhhjrhM_ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj<jj<jjjuh1jhhhjkhNhNubj)}(h**Parameters** ``struct drm_i915_private *i915`` The i915 device **Description** This version number is used by userspace to detect available features.h](h)}(h**Parameters**h]j)}(hjFh]h Parameters}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMchj@ubj)}(hhh]j)}(h2``struct drm_i915_private *i915`` The i915 device h](j$)}(h!``struct drm_i915_private *i915``h]j*)}(hjeh]hstruct drm_i915_private *i915}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjcubah}(h]h ]h"]h$]h&]uh1j#hZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chM`hj_ubj@)}(hhh]h)}(hThe i915 deviceh]hThe i915 device}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhM`hj{ubah}(h]h ]h"]h$]h&]uh1j?hj_ubeh}(h]h ]h"]h$]h&]uh1jhjzhM`hj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMbhj@ubh)}(hFThis version number is used by userspace to detect available features.h]hFThis version number is used by userspace to detect available features.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:495: ./drivers/gpu/drm/i915/i915_perf.chMahj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjkhhhNhNubeh}(h]other-i915-perf-internalsah ]h"]other i915 perf internalsah$]h&]uh1hhj#hhhhhMubeh}(h]perfah ]h"]perfah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hStyleh]hStyle}(hjߏhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj܏hhhhhMubh)}(h~The drm/i915 driver codebase has some style rules in addition to (and, in some cases, deviating from) the kernel coding style.h]h~The drm/i915 driver codebase has some style rules in addition to (and, in some cases, deviating from) the kernel coding style.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj܏hhubh)}(hhh](h)}(hRegister macro definition styleh]hRegister macro definition style}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h#The style guide for ``i915_reg.h``.h](hThe style guide for }(hj hhhNhNubj*)}(h``i915_reg.h``h]h i915_reg.h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hFollow the style described here for new macros, and while changing existing macros. Do **not** mass change existing definitions just to update the style.h](hWFollow the style described here for new macros, and while changing existing macros. Do }(hj,hhhNhNubj)}(h**not**h]hnot}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubh; mass change existing definitions just to update the style.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK hjhhubh)}(hhh](h)}(h File Layouth]h File Layout}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhNhNubh)}(hBKeep helper macros near the top. For example, _PIPE() and friends.h]hBKeep helper macros near the top. For example, _PIPE() and friends.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK&hjMubh)}(hPrefix macros that generally should not be used outside of this file with underscore '_'. For example, _PIPE() and friends, single instances of registers that are defined solely for the use by function-like macros.h]hPrefix macros that generally should not be used outside of this file with underscore ‘_’. For example, _PIPE() and friends, single instances of registers that are defined solely for the use by function-like macros.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK(hjMubh)}(hrAvoid using the underscore prefixed macros outside of this file. There are exceptions, but keep them to a minimum.h]hrAvoid using the underscore prefixed macros outside of this file. There are exceptions, but keep them to a minimum.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK,hjMubh)}(hXThere are two basic types of register definitions: Single registers and register groups. Register groups are registers which have two or more instances, for example one per pipe, port, transcoder, etc. Register groups should be defined using function-like macros.h]hXThere are two basic types of register definitions: Single registers and register groups. Register groups are registers which have two or more instances, for example one per pipe, port, transcoder, etc. Register groups should be defined using function-like macros.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK/hjMubh)}(hVFor single registers, define the register offset first, followed by register contents.h]hVFor single registers, define the register offset first, followed by register contents.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK4hjMubh)}(hFor register groups, define the register instance offsets first, prefixed with underscore, followed by a function-like macro choosing the right instance based on the parameter, followed by register contents.h]hFor register groups, define the register instance offsets first, prefixed with underscore, followed by a function-like macro choosing the right instance based on the parameter, followed by register contents.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK7hjMubh)}(hDefine the register contents (i.e. bit and bit field macros) from most significant to least significant bit. Indent the register content macros using two extra spaces between ``#define`` and the macro name.h](hDefine the register contents (i.e. bit and bit field macros) from most significant to least significant bit. Indent the register content macros using two extra spaces between }(hjhhhNhNubj*)}(h ``#define``h]h#define}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubh and the macro name.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK;hjMubh)}(hXnDefine bit fields using ``REG_GENMASK(h, l)``. Define bit field contents using ``REG_FIELD_PREP(mask, value)``. This will define the values already shifted in place, so they can be directly OR'd together. For convenience, function-like macros may be used to define bit fields, but do note that the macros may be needed to read as well as write the register contents.h](hDefine bit fields using }(hjِhhhNhNubj*)}(h``REG_GENMASK(h, l)``h]hREG_GENMASK(h, l)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjِubh". Define bit field contents using }(hjِhhhNhNubj*)}(h``REG_FIELD_PREP(mask, value)``h]hREG_FIELD_PREP(mask, value)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjِubhX. This will define the values already shifted in place, so they can be directly OR’d together. For convenience, function-like macros may be used to define bit fields, but do note that the macros may be needed to read as well as write the register contents.}(hjِhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK?hjMubh)}(hMDefine bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.h](hDefine bits using }(hj hhhNhNubj*)}(h``REG_BIT(N)``h]h REG_BIT(N)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubh. Do }(hj hhhNhNubj)}(h**not**h]hnot}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh add }(hj hhhNhNubj*)}(h``_BIT``h]h_BIT}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubh suffix to the name.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhKEhjMubh)}(hGroup the register and its contents together without blank lines, separate from other registers and their contents with one blank line.h]hGroup the register and its contents together without blank lines, separate from other registers and their contents with one blank line.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhKGhjMubh)}(hX Indent macro values from macro names using TABs. Align values vertically. Use braces in macro values as needed to avoid unintended precedence after macro substitution. Use spaces in macro values according to kernel coding style. Use lower case in hexadecimal values.h]hX Indent macro values from macro names using TABs. Align values vertically. Use braces in macro values as needed to avoid unintended precedence after macro substitution. Use spaces in macro values according to kernel coding style. Use lower case in hexadecimal values.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhKJhjMubeh}(h] file-layoutah ]h"] file layoutah$]h&]uh1hhjhhhNhNubh)}(hhh](h)}(hNamingh]hNaming}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhNhNubh)}(hTry to name registers according to the specs. If the register name changes in the specs from platform to another, stick to the original name.h]hTry to name registers according to the specs. If the register name changes in the specs from platform to another, stick to the original name.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhKRhjwubh)}(hTry to reuse existing register macro definitions. Only add new macros for new register offsets, or when the register contents have changed enough to warrant a full redefinition.h]hTry to reuse existing register macro definitions. Only add new macros for new register offsets, or when the register contents have changed enough to warrant a full redefinition.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhKUhjwubh)}(hWhen a register macro changes for a new platform, prefix the new macro using the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The prefix signifies the start platform/generation using the register.h](h~When a register macro changes for a new platform, prefix the new macro using the platform acronym or generation. For example, }(hjhhhNhNubj*)}(h``SKL_``h]hSKL_}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubh or }(hjhhhNhNubj*)}(h ``GEN8_``h]hGEN8_}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubhH. The prefix signifies the start platform/generation using the register.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhKYhjwubh)}(hWhen a bit (field) macro changes or gets added for a new platform, while retaining the existing register macro, add a platform acronym or generation suffix to the name. For example, ``_SKL`` or ``_GEN8``.Zh](hWhen a bit (field) macro changes or gets added for a new platform, while retaining the existing register macro, add a platform acronym or generation suffix to the name. For example, }(hjّhhhNhNubj*)}(h``_SKL``h]h_SKL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjّubh or }(hjّhhhNhNubj*)}(h ``_GEN8``h]h_GEN8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjّubh.}(hjّhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhK]hjwubeh}(h]namingah ]h"]namingah$]h&]uh1hhjhhhNhNubh)}(hhh](h)}(hExamplesh]hExamples}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhNhNubh)}(h(Note that the values in the example are indented using spaces instead of TABs to avoid misalignment in generated documentation. Use TABs in the definitions.)::h]h(Note that the values in the example are indented using spaces instead of TABs to avoid misalignment in generated documentation. Use TABs in the definitions.):}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhKdhjubjA#)}(hX6#define _FOO_A 0xf000 #define _FOO_B 0xf001 #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) #define FOO_ENABLE REG_BIT(31) #define FOO_MODE_MASK REG_GENMASK(19, 16) #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) #define BAR _MMIO(0xb000) #define GEN8_BAR _MMIO(0xb888)h]hX6#define _FOO_A 0xf000 #define _FOO_B 0xf001 #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) #define FOO_ENABLE REG_BIT(31) #define FOO_MODE_MASK REG_GENMASK(19, 16) #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) #define BAR _MMIO(0xb000) #define GEN8_BAR _MMIO(0xb888)}hj4sbah}(h]h ]h"]h$]h&]j5j6uh1j@#hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:530: ./drivers/gpu/drm/i915/i915_reg.hhKhhjubeh}(h]examplesah ]h"]examplesah$]h&]uh1hhjhhhNhNubh)}(h.. _i915-usage-stats:h]h}(h]h ]h"]h$]h&]hi915-usage-statsuh1hhMhjhhhhubeh}(h]register-macro-definition-styleah ]h"]register macro definition styleah$]h&]uh1hhj܏hhhhhMubeh}(h]styleah ]h"]styleah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h*i915 DRM client usage stats implementationh]h*i915 DRM client usage stats implementation}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhhhhhMubh)}(hwThe drm/i915 driver implements the DRM client usage stats specification as documented in :ref:`drm-client-usage-stats`.h](hYThe drm/i915 driver implements the DRM client usage stats specification as documented in }(hjwhhhNhNubh)}(h:ref:`drm-client-usage-stats`h]h)}(hjh]hdrm-client-usage-stats}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjdrm-client-usage-statsuh1hhhhMhjwubh.}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjfhhubh)}(htExample of the output showing the implemented key value pairs and entirety of the currently possible format options:h]htExample of the output showing the implemented key value pairs and entirety of the currently possible format options:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfhhubjA#)}(hXpos: 0 flags: 0100002 mnt_id: 21 drm-driver: i915 drm-pdev: 0000:00:02.0 drm-client-id: 7 drm-engine-render: 9288864723 ns drm-engine-copy: 2035071108 ns drm-engine-video: 0 ns drm-engine-capacity-video: 2 drm-engine-video-enhance: 0 nsh]hXpos: 0 flags: 0100002 mnt_id: 21 drm-driver: i915 drm-pdev: 0000:00:02.0 drm-client-id: 7 drm-engine-render: 9288864723 ns drm-engine-copy: 2035071108 ns drm-engine-video: 0 ns drm-engine-capacity-video: 2 drm-engine-video-enhance: 0 ns}hjsbah}(h]h ]h"]h$]h&]j5j6uh1j@#hhhM"hjfhhubh)}(hTPossible `drm-engine-` key names are: `render`, `copy`, `video` and `video-enhance`.h](h Possible }(hjŒhhhNhNubjc)}(h `drm-engine-`h]h drm-engine-}(hj͒hhhNhNubah}(h]h ]h"]h$]h&]uh1j chjŒubh key names are: }(hjŒhhhNhNubjc)}(h`render`h]hrender}(hjߒhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjŒubh, }(hjŒhhhNhNubjc)}(h`copy`h]hcopy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjŒubh, }hjŒsbjc)}(h`video`h]hvideo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjŒubh and }(hjŒhhhNhNubjc)}(h`video-enhance`h]h video-enhance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j chjŒubh.}(hjŒhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM.hjfhhubeh}(h](*i915-drm-client-usage-stats-implementationjUeh ]h"](*i915 drm client usage stats implementationi915-usage-statseh$]h&]uh1hhhhhhhhMj}j3jKsj}jUjKsubeh}(h](drm-i915-intel-gfx-driverheh ]h"](drm/i915 intel gfx driverdrm/i915eh$]h&]uh1hhhhhhhhKj}j>hsj}hhsubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjeerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehÌ _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}(1]j&;a(gem bo management implementation details]jEca hxg request](jj;j^jj'jojj;j$jZjhjj3e hxg response](jjTe hxg failure](jjjFe hxg retry](j'jehxg busy](j<j'eguc_hxg_type_request](jjijehxg fast request]ja hxg message](jjjVjdeguc_hxg_type_fast_request]ja hxg event]j*aguc_hxg_type_event]jtaguc_hxg_type_no_response_busy]jaaguc_hxg_type_no_response_retry]jJaguc_hxg_type_response_failure]j_aguc_hxg_type_response_success](jmjjCectb based communication](j@je ctb message]j&a ct buffer](j#jjjjrjjectb hxg message]j aguc_ctb_format_hxg]jaguc self config klvs](j0jZjemmio hxg message](jTjeguc_hxg_origin_host](j!j}eguc_hxg_origin_guc](jjeguc klv]j?ahost2guc_self_cfg]jSactb descriptor](jj6eguc firmware layout]j"aurefids}(h]haj]j{aj]jaj]j aj]jajL]jaj7]jaj"]jaj ]j'aj]jajf]j\aj]jajH]j>aj6]j aj ]j ajP]jaj ]jaji]j_aj]jaj@]jajU]jKaunameids}(j>hj=j:j5<j2<j+j+j0j0j5j5j:j:j-<j*<j%<j5;j+bj(bj#bj bjjjcjcjdjdjdjUcjpjpj~j~jňjˆjbj_j3j0jȦjŦjjjjjjjjj@j=jjjk#jh#j<j9j4j1jjjjjjj|jyjgjdjjjjjjjjjfjcjjjjjjjjj.j+jUjRjjj-jjjjjLjj7jjj8j"jFj jjj|jfjjj^jHj% j" jM jJ ju jr j j j j j j6j j j j j%jPj"j jjjjijRjOjjjj jjj5j@jjjjjLjIjjjj jrjoj#j#j"j"j#j #jc#j`#j#j#j#j#j#j#jُj֏jH$jE$j%j%j%j%j87j57j^Zj[ZjkjkjяjΏjcj`j[jXjtjqjjjHjEj3jUj2j/u nametypes}(j>j=j5<j+j0j5j:j-<j%<j+bj#bjjcjdjdjpj~jňjbj3jȦjjjjj@jjk#j<j4jjjj|jgjjjjjfjjjjj.jUjj-jjjjj8jFjj|jj^j% jM ju j j j j j j%j"jjjRjjjj5jjjLjjjrj#j"j#jc#j#j#j#jُjH$j%j%j87j^Zjkjяjcj[jtjjHj3j2uh}(hhj:hj2<jhj+jjjjjjjjjj j j j je jj jgjljjj'j,jjj)j.jFjKjcjhjZj_jwj|j#j#j)j)j0j+j,j ,j-j-j/j"/j5j0j0j0jV2j[2j3j3j:j5j5j5j7j7j9j9j*<j:j0;j&;j5;j;j(bj8<j bjI<j<j<j>j>jAjAjBjBjEjEj7Ijj>jAjAj6Ej;EjSIjXIj0Kj5KjNjNjuQjzQjSjSjTjTjPWjUWjkjaZj~ZjZjd]ji]j`j`jdjdjejej8gj=gjij ijΏjkjkjkjojojqjqjujujXzj]zj}j}jjj&j+jjjAjFj‹jNjjWj\j`j܏jXjjqjMjjwjEjjUjfj/jfu footnote_refs}j]j&;as citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes]j;a citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}jsKsRparse_messages](hsystem_message)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypeINFOlineK$sourcek/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.huh1jhj5ubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8ubah}(h]h ]h"]h$]h&]levelKtypej4lineKRsourcek/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.huh1jhjubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubah}(h]h ]h"]h$]h&]levelKtypej4lineKusourcek/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.huh1jhjubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpubah}(h]h ]h"]h$]h&]levelKtypej4lineKsourcek/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.huh1jhjubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4lineKsourcek/var/lib/git/docbuild/linux/Documentation/gpu/i915:358: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.huh1jhj^ubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4lineK*sourceu/var/lib/git/docbuild/linux/Documentation/gpu/i915:359: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.huh1jhjubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjǔhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjĔubah}(h]h ]h"]h$]h&]levelKtypej4lineK)sourcet/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.huh1jhj ubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4lineKMsourcet/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.huh1jhj ubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4lineKlsourcet/var/lib/git/docbuild/linux/Documentation/gpu/i915:360: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.huh1jhjubj)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4lineKsourceg/var/lib/git/docbuild/linux/Documentation/gpu/i915:362: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.huh1jhjubetransform_messages](j)}(hhh]h)}(hhh]h.Hyperlink target "drm-i915" is not referenced.}hj9sbah}(h]h ]h"]h$]h&]uh1hhj6ubah}(h]h ]h"]h$]h&]levelKtypej4sourcehÌlineKuh1jubj)}(hhh]h)}(hhh]hFHyperlink target "guc_hxg_retry_reason_unspecified" is not referenced.}hjSsbah}(h]h ]h"]h$]h&]uh1hhjPubah}(h]h ]h"]h$]h&]levelKtypej4sourcejlineKuh1jubj)}(hhh]h)}(hhh]hBHyperlink target "guc-mmio-based-communication" is not referenced.}hjmsbah}(h]h ]h"]h$]h&]uh1hhjjubah}(h]h ]h"]h$]h&]levelKtypej4sourcejlineKuh1jubj)}(hhh]h)}(hhh]h=Hyperlink target "guc_ctb_status_no_error" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcej2 lineK"uh1jubj)}(hhh]h)}(hhh]h=Hyperlink target "guc_ctb_status_overflow" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcejZ lineK#uh1jubj)}(hhh]h)}(hhh]h>Hyperlink target "guc_ctb_status_underflow" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcej lineK$uh1jubj)}(hhh]h)}(hhh]h=Hyperlink target "guc_ctb_status_mismatch" is not referenced.}hjՕsbah}(h]h ]h"]h$]h&]uh1hhjҕubah}(h]h ]h"]h$]h&]levelKtypej4sourcej lineK%uh1jubj)}(hhh]h)}(hhh]h;Hyperlink target "guc_ctb_status_unused" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcej lineK&uh1jubj)}(hhh]h)}(hhh]hBHyperlink target "guc_action_host2guc_self_cfg" is not referenced.}hj sbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcejlineKuh1jubj)}(hhh]h)}(hhh]h:Hyperlink target "host2guc-control-ctb" is not referenced.}hj#sbah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]levelKtypej4sourcej lineK+uh1jubj)}(hhh]h)}(hhh]hEHyperlink target "guc_action_host2guc_control_ctb" is not referenced.}hj=sbah}(h]h ]h"]h$]h&]uh1hhj:ubah}(h]h ]h"]h$]h&]levelKtypej4sourcej3lineKKuh1jubj)}(hhh]h)}(hhh]h=Hyperlink target "guc_ctb_control_disable" is not referenced.}hjWsbah}(h]h ]h"]h$]h&]uh1hhjTubah}(h]h ]h"]h$]h&]levelKtypej4sourcejlineKOuh1jubj)}(hhh]h)}(hhh]huh1jubj)}(hhh]h)}(hhh]h6Hyperlink target "i915-usage-stats" is not referenced.}hj'sbah}(h]h ]h"]h$]h&]uh1hhj$ubah}(h]h ]h"]h$]h&]levelKtypej4sourcehÌlineMuh1jube transformerN include_log] decorationNhhub.