.sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/gpu/i915modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/gpu/i915modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hdrm/i915 Intel GFX Driverh]hdrm/i915 Intel GFX Driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh6/var/lib/git/docbuild/linux/Documentation/gpu/i915.rsthKubh paragraph)}(hXThe drm/i915 driver supports all (with the exception of some very early models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver.h]hXThe drm/i915 driver supports all (with the exception of some very early models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hCore Driver Infrastructureh]hCore Driver Infrastructure}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hhThis section covers core driver infrastructure used by both the display and the GEM parts of the driver.h]hhThis section covers core driver infrastructure used by both the display and the GEM parts of the driver.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hRuntime Power Managementh]hRuntime Power Management}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hXrThe i915 driver supports dynamic enabling and disabling of entire hardware blocks at runtime. This is especially important on the display side where software is supposed to control many power gates manually on recent hardware, since on the GT side a lot of the power management is done by the hardware. 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Raw references are not considered during wakelock assert checks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjYubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put_raw() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put_raw() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjYubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjYubh)}(h|the wakeref cookie to pass to intel_runtime_pm_put_raw(), evaluates as True if the wakeref was acquired, or False otherwise.h]h|the wakeref cookie to pass to intel_runtime_pm_put_raw(), evaluates as True if the wakeref was acquired, or False otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjYubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_runtime_pm_get (C function)c.intel_runtime_pm_gethNtauh1jhhhhhNhNubj')}(hhh](j,)}(hCintel_wakeref_t intel_runtime_pm_get (struct intel_runtime_pm *rpm)h]j2)}(hBintel_wakeref_t intel_runtime_pm_get(struct intel_runtime_pm *rpm)h](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hjChhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjEmodnameN classnameNjXj[)}j^]ja)}jTintel_runtime_pm_getsbc.intel_runtime_pm_getasbuh1hhj<hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKubji)}(h h]h }(hjehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj<hhhjdhKubjz)}(hintel_runtime_pm_geth]j;)}(hjah]hintel_runtime_pm_get}(hjwhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj<hhhjdhKubj)}(h(struct intel_runtime_pm *rpm)h]j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j_c.intel_runtime_pm_getasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj<hhhjdhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj8hhhjdhKubah}(h]j3ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjdhKhj5hhubj1)}(hhh]h)}(hgrab a runtime pm referenceh]hgrab a runtime pm reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hj5hhhjdhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj+jSj+jTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up. 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Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubh)}(hThis function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up.h]hThis function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubh)}(h4the wakeref cookie to pass to intel_runtime_pm_put()h]h4the wakeref cookie to pass to intel_runtime_pm_put()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"-__intel_runtime_pm_get_if_active (C function)"c.__intel_runtime_pm_get_if_activehNtauh1jhhhhhNhNubj')}(hhh](j,)}(heintel_wakeref_t __intel_runtime_pm_get_if_active (struct intel_runtime_pm *rpm, bool ignore_usecount)h]j2)}(hdintel_wakeref_t __intel_runtime_pm_get_if_active(struct intel_runtime_pm *rpm, bool ignore_usecount)h](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jT __intel_runtime_pm_get_if_activesb"c.__intel_runtime_pm_get_if_activeasbuh1hhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj.hKubjz)}(h __intel_runtime_pm_get_if_activeh]j;)}(hj+h]h __intel_runtime_pm_get_if_active}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj=ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj.hKubj)}(h4(struct intel_runtime_pm *rpm, bool ignore_usecount)h](j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubji)}(h h]h }(hjihhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjXubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hjzhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjwubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj|modnameN classnameNjXj[)}j^]j)"c.__intel_runtime_pm_get_if_activeasbuh1hhjXubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjXubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj;)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjXubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubj)}(hbool ignore_usecounth](hdesc_sig_keyword_type)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hignore_usecounth]hignore_usecount}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj.hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj.hKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj.hKhjhhubj1)}(hhh]h)}(h/grab a runtime pm reference if device is activeh]h/grab a runtime pm reference if device is active}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj.hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj-jSj-jTjUjVuh1j&hhhhhNhNubjX)}(hX-**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``bool ignore_usecount`` get a ref even if dev->power.usage_count is 0 **Description** This function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure. If **ignore_usecount** is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it's guaranteed that the device's runtime suspend hook has been called already or that it will be called (and hence it's also guaranteed that the device's runtime resume hook will be called eventually). Any runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again. **Return** the wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.h](h)}(h**Parameters**h]jb)}(hj7h]h Parameters}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj5ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubjx)}(hhh](j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjVh]hstruct intel_runtime_pm *rpm}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjPubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhKhjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j|hjkhKhjMubj})}(hG``bool ignore_usecount`` get a ref even if dev->power.usage_count is 0 h](j)}(h``bool ignore_usecount``h]j)}(hjh]hbool ignore_usecount}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjubj)}(hhh]h)}(h-get a ref even if dev->power.usage_count is 0h]h-get a ref even if dev->power.usage_count is 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjMubeh}(h]h ]h"]h$]h&]uh1jwhj1ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(hThis function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure.h]hThis function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(hXIf **ignore_usecount** is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it's guaranteed that the device's runtime suspend hook has been called already or that it will be called (and hence it's also guaranteed that the device's runtime resume hook will be called eventually).h](hIf }(hjhhhNhNubjb)}(h**ignore_usecount**h]hignore_usecount}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubhX is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it’s guaranteed that the device’s runtime suspend hook has been called already or that it will be called (and hence it’s also guaranteed that the device’s runtime resume hook will be called eventually).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(h **Return**h]jb)}(hj!h]hReturn}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(hxthe wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.h]hxthe wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"*intel_runtime_pm_get_noresume (C function)c.intel_runtime_pm_get_noresumehNtauh1jhhhhhNhNubj')}(hhh](j,)}(hLintel_wakeref_t intel_runtime_pm_get_noresume (struct intel_runtime_pm *rpm)h]j2)}(hKintel_wakeref_t intel_runtime_pm_get_noresume(struct intel_runtime_pm *rpm)h](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjkmodnameN classnameNjXj[)}j^]ja)}jTintel_runtime_pm_get_noresumesbc.intel_runtime_pm_get_noresumeasbuh1hhjbhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbhhhjhMubjz)}(hintel_runtime_pm_get_noresumeh]j;)}(hjh]hintel_runtime_pm_get_noresume}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjbhhhjhMubj)}(h(struct intel_runtime_pm *rpm)h]j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_runtime_pm_get_noresumeasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjbhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj^hhhjhMubah}(h]jYah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhj[hhubj1)}(hhh]h)}(hgrab a runtime pm referenceh]hgrab a runtime pm reference}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj6hhubah}(h]h ]h"]h$]h&]uh1j0hj[hhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjQjSjQjTjUjVuh1j&hhhhhNhNubjX)}(hX@**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function grabs a device-level runtime pm reference. It will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold. Any runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again. **Return** the wakeref cookie to pass to intel_runtime_pm_put()h](h)}(h**Parameters**h]jb)}(hj[h]h Parameters}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjYubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubjx)}(hhh]j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjzh]hstruct intel_runtime_pm *rpm}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjtubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjqubah}(h]h ]h"]h$]h&]uh1jwhjUubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(h8This function grabs a device-level runtime pm reference.h]h8This function grabs a device-level runtime pm reference.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(hIt will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold.h]hIt will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(h4the wakeref cookie to pass to intel_runtime_pm_put()h]h4the wakeref cookie to pass to intel_runtime_pm_put()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_runtime_pm_put_raw (C function)c.intel_runtime_pm_put_rawhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hRvoid intel_runtime_pm_put_raw (struct intel_runtime_pm *rpm, intel_wakeref_t wref)h]j2)}(hQvoid intel_runtime_pm_put_raw(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j)}(hvoidh]hvoid}(hj? hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj; hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM?ubji)}(h h]h }(hjN hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj; hhhjM hM?ubjz)}(hintel_runtime_pm_put_rawh]j;)}(hintel_runtime_pm_put_rawh]hintel_runtime_pm_put_raw}(hj` hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj; hhhjM hM?ubj)}(h4(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hj| hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjx ubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjb sbc.intel_runtime_pm_put_rawasbuh1hhjx ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjx ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx ubj;)}(hrpmh]hrpm}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjx ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjt ubj)}(hintel_wakeref_t wrefh](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]j c.intel_runtime_pm_put_rawasbuh1hhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj;)}(hwrefh]hwref}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjt ubeh}(h]h ]h"]h$]h&]jjuh1jhj; hhhjM hM?ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj7 hhhjM hM?ubah}(h]j2 ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjM hM?hj4 hhubj1)}(hhh]h)}(h"release a raw runtime pm referenceh]h"release a raw runtime pm reference}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM7hjD hhubah}(h]h ]h"]h$]h&]uh1j0hj4 hhhjM hM?ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj_ jSj_ jTjUjVuh1j&hhhhhNhNubjX)}(hXz**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``intel_wakeref_t wref`` wakeref acquired for the reference that is being released **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.h](h)}(h**Parameters**h]jb)}(hji h]h Parameters}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjg ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM;hjc ubjx)}(hhh](j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hj h]hstruct intel_runtime_pm *rpm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM8hj ubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM8hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hM8hj ubj})}(hS``intel_wakeref_t wref`` wakeref acquired for the reference that is being released h](j)}(h``intel_wakeref_t wref``h]j)}(hj h]hintel_wakeref_t wref}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM9hj ubj)}(hhh]h)}(h9wakeref acquired for the reference that is being releasedh]h9wakeref acquired for the reference that is being released}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM9hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hM9hj ubeh}(h]h ]h"]h$]h&]uh1jwhjc ubh)}(h**Description**h]jb)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM;hjc ubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM;hjc ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+intel_runtime_pm_put_unchecked (C function) c.intel_runtime_pm_put_uncheckedhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hBvoid intel_runtime_pm_put_unchecked (struct intel_runtime_pm *rpm)h]j2)}(hAvoid intel_runtime_pm_put_unchecked(struct intel_runtime_pm *rpm)h](j)}(hvoidh]hvoid}(hjA hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj= hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMQubji)}(h h]h }(hjP hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj= hhhjO hMQubjz)}(hintel_runtime_pm_put_uncheckedh]j;)}(hintel_runtime_pm_put_uncheckedh]hintel_runtime_pm_put_unchecked}(hjb hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj^ ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj= hhhjO hMQubj)}(h(struct intel_runtime_pm *rpm)h]j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hj~ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz ubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjd sb c.intel_runtime_pm_put_uncheckedasbuh1hhjz ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz ubj;)}(hrpmh]hrpm}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjz ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjv ubah}(h]h ]h"]h$]h&]jjuh1jhj= hhhjO hMQubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj9 hhhjO hMQubah}(h]j4 ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjO hMQhj6 hhubj1)}(hhh]h)}(h)release an unchecked runtime pm referenceh]h)release an unchecked runtime pm reference}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMFhj hhubah}(h]h ]h"]h$]h&]uh1j0hj6 hhhjO hMQubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference. This function exists only for historical reasons and should be avoided in new code, as the correctness of its use cannot be checked. Always use intel_runtime_pm_put() instead.h](h)}(h**Parameters**h]jb)}(hj# h]h Parameters}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj! ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMJhj ubjx)}(hhh]j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjB h]hstruct intel_runtime_pm *rpm}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMGhj< ubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjW hMGhjX ubah}(h]h ]h"]h$]h&]uh1jhj< ubeh}(h]h ]h"]h$]h&]uh1j|hjW hMGhj9 ubah}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hj} h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj{ ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMIhj ubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMIhj ubh)}(hThis function exists only for historical reasons and should be avoided in new code, as the correctness of its use cannot be checked. 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Always use intel_runtime_pm_put() instead.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_runtime_pm_put (C function)c.intel_runtime_pm_puthNtauh1jhhhhhNhNubj')}(hhh](j,)}(hNvoid intel_runtime_pm_put (struct intel_runtime_pm *rpm, intel_wakeref_t wref)h]j2)}(hMvoid intel_runtime_pm_put(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM`ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj hhhj hM`ubjz)}(hintel_runtime_pm_puth]j;)}(hintel_runtime_pm_puth]hintel_runtime_pm_put}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj hhhj hM`ubj)}(h4(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hj, hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj) ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj. modnameN classnameNjXj[)}j^]ja)}jTj sbc.intel_runtime_pm_putasbuh1hhj ubji)}(h h]h }(hjL hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hjZ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hrpmh]hrpm}(hjg hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(hintel_wakeref_t wrefh](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jH c.intel_runtime_pm_putasbuh1hhj| ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj| ubj;)}(hwrefh]hwref}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj| ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubeh}(h]h ]h"]h$]h&]jjuh1jhj hhhj hM`ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhj hM`ubah}(h]j ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj hM`hj hhubj1)}(hhh]h)}(hrelease a runtime pm referenceh]hrelease a runtime pm reference}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMXhj hhubah}(h]h ]h"]h$]h&]uh1j0hj hhhj hM`ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhhhNhNubjX)}(hXv**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``intel_wakeref_t wref`` wakeref acquired for the reference that is being released **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM\hj ubjx)}(hhh](j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjh]hstruct intel_runtime_pm *rpm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMYhjubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMYhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj/hMYhjubj})}(hS``intel_wakeref_t wref`` wakeref acquired for the reference that is being released h](j)}(h``intel_wakeref_t wref``h]j)}(hjSh]hintel_wakeref_t wref}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMZhjMubj)}(hhh]h)}(h9wakeref acquired for the reference that is being releasedh]h9wakeref acquired for the reference that is being released}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMZhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j|hjhhMZhjubeh}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM\hj ubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM\hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_runtime_pm_enable (C function)c.intel_runtime_pm_enablehNtauh1jhhhhhNhNubj')}(hhh](j,)}(h;void intel_runtime_pm_enable (struct intel_runtime_pm *rpm)h]j2)}(h:void intel_runtime_pm_enable(struct intel_runtime_pm *rpm)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMpubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMpubjz)}(hintel_runtime_pm_enableh]j;)}(hintel_runtime_pm_enableh]hintel_runtime_pm_enable}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMpubj)}(h(struct intel_runtime_pm *rpm)h]j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_runtime_pm_enableasbuh1hhj ubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hrpmh]hrpm}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMpubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMpubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMphjhhubj1)}(hhh]h)}(henable runtime pmh]henable runtime pm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMghjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMpubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hXC**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function enables runtime pm at the end of the driver load sequence. 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That is done by intel_power_domains_enable().h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMkhjubjx)}(hhh]j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjh]hstruct intel_runtime_pm *rpm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhhjubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMjhjubh)}(hHThis function enables runtime pm at the end of the driver load sequence.h]hHThis function enables runtime pm at the end of the driver load sequence.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMjhjubh)}(hNote that this function does currently not enable runtime pm for the subordinate display power domains. That is done by intel_power_domains_enable().h]hNote that this function does currently not enable runtime pm for the subordinate display power domains. That is done by intel_power_domains_enable().}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMlhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_uncore_forcewake_get (C function)c.intel_uncore_forcewake_gethNtauh1jhhhhhNhNubj')}(hhh](j,)}(h`void intel_uncore_forcewake_get (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(h_void intel_uncore_forcewake_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj_hhhjqhMubjz)}(hintel_uncore_forcewake_geth]j;)}(hintel_uncore_forcewake_geth]hintel_uncore_forcewake_get}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj_hhhjqhMubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_uncore_forcewake_getasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(henumh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hj1hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj3modnameN classnameNjXj[)}j^]jc.intel_uncore_forcewake_getasbuh1hhjubji)}(h h]h }(hjOhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h fw_domainsh]h fw_domains}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhj_hhhjqhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj[hhhjqhMubah}(h]jVah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjqhMhjXhhubj1)}(hhh]h)}(h grab forcewake domain referencesh]h grab forcewake domain references}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjXhhhjqhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to get reference on **Description** This function can be used get GT's forcewake domain references. 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Usually caller wants all the domains to be kept awake so the **fw_domains** would be then FORCEWAKE_ALL.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hL``enum forcewake_domains fw_domains`` forcewake domains to get reference on h](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hjh]h!enum forcewake_domains fw_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(h%forcewake domains to get reference onh]h%forcewake domains to get reference on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj<h]h Description}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj:ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.c-hMhjubh)}(hXThis function can be used get GT's forcewake domain references. Normal register access will handle the forcewake domains automatically. However if some sequence requires the GT to not power down a particular forcewake domains this function should be called at the beginning of the sequence. And subsequently the reference should be dropped by symmetric call to intel_unforce_forcewake_put(). Usually caller wants all the domains to be kept awake so the **fw_domains** would be then FORCEWAKE_ALL.h](hXThis function can be used get GT’s forcewake domain references. Normal register access will handle the forcewake domains automatically. However if some sequence requires the GT to not power down a particular forcewake domains this function should be called at the beginning of the sequence. And subsequently the reference should be dropped by symmetric call to intel_unforce_forcewake_put(). Usually caller wants all the domains to be kept awake so the }(hjRhhhNhNubjb)}(h**fw_domains**h]h fw_domains}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjRubh would be then FORCEWAKE_ALL.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_uncore_forcewake_user_get (C function)!c.intel_uncore_forcewake_user_gethNtauh1jhhhhhNhNubj')}(hhh](j,)}(hBvoid intel_uncore_forcewake_user_get (struct intel_uncore *uncore)h]j2)}(hAvoid intel_uncore_forcewake_user_get(struct intel_uncore *uncore)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_uncore_forcewake_user_geth]j;)}(hintel_uncore_forcewake_user_geth]hintel_uncore_forcewake_user_get}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct intel_uncore *uncore)h]j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb!c.intel_uncore_forcewake_user_getasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hj)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h&claim forcewake on behalf of userspaceh]h&claim forcewake on behalf of userspace}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjPhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjkjSjkjTjUjVuh1j&hhhhhNhNubjX)}(hX **Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure **Description** This function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace's bypass.h](h)}(h**Parameters**h]jb)}(hjuh]h Parameters}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjsubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjoubjx)}(hhh]j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjoubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjoubh)}(hThis function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace's bypass.h]hThis function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace’s bypass.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjoubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_uncore_forcewake_user_put (C function)!c.intel_uncore_forcewake_user_puthNtauh1jhhhhhNhNubj')}(hhh](j,)}(hBvoid intel_uncore_forcewake_user_put (struct intel_uncore *uncore)h]j2)}(hAvoid intel_uncore_forcewake_user_put(struct intel_uncore *uncore)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hj#hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj"hMubjz)}(hintel_uncore_forcewake_user_puth]j;)}(hintel_uncore_forcewake_user_puth]hintel_uncore_forcewake_user_put}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj1ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj"hMubj)}(h(struct intel_uncore *uncore)h]j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjMubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hjohhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjlubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjqmodnameN classnameNjXj[)}j^]ja)}jTj7sb!c.intel_uncore_forcewake_user_putasbuh1hhjMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubj;)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjMubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjIubah}(h]h ]h"]h$]h&]jjuh1jhjhhhj"hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhj"hMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj"hMhj hhubj1)}(hhh]h)}(h(release forcewake on behalf of userspaceh]h(release forcewake on behalf of userspace}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj hhhj"hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(h**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure **Description** This function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubjx)}(hhh]j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj*hMhj ubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjPh]h Description}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubh)}(hThis function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.h]hThis function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"/intel_uncore_forcewake_get__locked (C function)$c.intel_uncore_forcewake_get__lockedhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hhvoid intel_uncore_forcewake_get__locked (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(hgvoid intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(h"intel_uncore_forcewake_get__lockedh]j;)}(h"intel_uncore_forcewake_get__lockedh]h"intel_uncore_forcewake_get__locked}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb$c.intel_uncore_forcewake_get__lockedasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(hjh]henum}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@ubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hjbhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjdmodnameN classnameNjXj[)}j^]j $c.intel_uncore_forcewake_get__lockedasbuh1hhj@ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@ubj;)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h grab forcewake domain referencesh]h grab forcewake domain references}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hX3**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to get reference on **Description** See intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hL``enum forcewake_domains fw_domains`` forcewake domains to get reference on h](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hj2h]h!enum forcewake_domains fw_domains}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhj,ubj)}(hhh]h)}(h%forcewake domains to get reference onh]h%forcewake domains to get reference on}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjHubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1j|hjGhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjmh]h Description}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jahjkubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubh)}(hSee intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h]hSee intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_uncore_forcewake_put (C function)c.intel_uncore_forcewake_puthNtauh1jhhhhhNhNubj')}(hhh](j,)}(h`void intel_uncore_forcewake_put (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(h_void intel_uncore_forcewake_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_uncore_forcewake_puth]j;)}(hintel_uncore_forcewake_puth]hintel_uncore_forcewake_put}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_uncore_forcewake_putasbuh1hhjubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hjHhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(hjh]henum}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubji)}(h h]h }(hjnhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]ubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j)c.intel_uncore_forcewake_putasbuh1hhj]ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]ubj;)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj]ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h$release a forcewake domain referenceh]h$release a forcewake domain reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to put references **Description** This function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hMhj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj+hMhj ubj})}(hJ``enum forcewake_domains fw_domains`` forcewake domains to put references h](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hjOh]h!enum forcewake_domains fw_domains}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjIubj)}(hhh]h)}(h#forcewake domains to put referencesh]h#forcewake domains to put references}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjeubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1j|hjdhMhj ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubh)}(hoThis function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().h]hoThis function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_uncore_forcewake_flush (C function)c.intel_uncore_forcewake_flushhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hbvoid intel_uncore_forcewake_flush (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(havoid intel_uncore_forcewake_flush(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM7ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM7ubjz)}(hintel_uncore_forcewake_flushh]j;)}(hintel_uncore_forcewake_flushh]hintel_uncore_forcewake_flush}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM7ubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj*hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj,modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_uncore_forcewake_flushasbuh1hhjubji)}(h h]h }(hjJhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hjehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(hjh]henum}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jFc.intel_uncore_forcewake_flushasbuh1hhjzubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzubj;)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM7ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM7ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM7hjhhubj1)}(hhh]h)}(hflush the delayed releaseh]hflush the delayed release}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM3hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM7ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhhhNhNubjX)}(h**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to flushh](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM7hjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hj3h]hstruct intel_uncore *uncore}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM4hj-ubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhM4hjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1j|hjHhM4hj*ubj})}(h@``enum forcewake_domains fw_domains`` forcewake domains to flushh](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hjlh]h!enum forcewake_domains fw_domains}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM6hjfubj)}(hhh]h)}(hforcewake domains to flushh]hforcewake domains to flush}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM5hjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1j|hjhM6hj*ubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"/intel_uncore_forcewake_put__locked (C function)$c.intel_uncore_forcewake_put__lockedhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hhvoid intel_uncore_forcewake_put__locked (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(hgvoid intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMPubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMPubjz)}(h"intel_uncore_forcewake_put__lockedh]j;)}(h"intel_uncore_forcewake_put__lockedh]h"intel_uncore_forcewake_put__locked}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMPubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj#modnameN classnameNjXj[)}j^]ja)}jTjsb$c.intel_uncore_forcewake_put__lockedasbuh1hhjubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hj\hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(hjh]henum}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j=$c.intel_uncore_forcewake_put__lockedasbuh1hhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubj;)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjqubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMPubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMPubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMPhjhhubj1)}(hhh]h)}(h#release forcewake domain referencesh]h#release forcewake domain references}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMIhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMPubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hX1**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to put references **Description** See intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMMhjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hj*h]hstruct intel_uncore *uncore}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMJhj$ubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMJhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1j|hj?hMJhj!ubj})}(hJ``enum forcewake_domains fw_domains`` forcewake domains to put references h](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hjch]h!enum forcewake_domains fw_domains}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMKhj]ubj)}(hhh]h)}(h#forcewake domains to put referencesh]h#forcewake domains to put references}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMKhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1j|hjxhMKhj!ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMMhjubh)}(hSee intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h]hSee intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")__intel_wait_for_register_fw (C function)c.__intel_wait_for_register_fwhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hint __intel_wait_for_register_fw (struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h]j2)}(hint __intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(h__intel_wait_for_register_fwh]j;)}(h__intel_wait_for_register_fwh]h__intel_wait_for_register_fw}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj@modnameN classnameNjXj[)}j^]ja)}jTjsbc.__intel_wait_for_register_fwasbuh1hhjubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hi915_reg_t regh](h)}(hhh]j;)}(h i915_reg_th]h i915_reg_t}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jZc.__intel_wait_for_register_fwasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hregh]hreg}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu32 maskh](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jZc.__intel_wait_for_register_fwasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hmaskh]hmask}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj'modnameN classnameNjXj[)}j^]jZc.__intel_wait_for_register_fwasbuh1hhjubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hvalueh]hvalue}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int fast_timeout_ush](j)}(hunsignedh]hunsigned}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubji)}(h h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubj;)}(hfast_timeout_ush]hfast_timeout_us}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int slow_timeout_msh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hslow_timeout_msh]hslow_timeout_ms}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu32 *out_valueh](h)}(hhh]j;)}(hu32h]hu32}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jZc.__intel_wait_for_register_fwasbuh1hhj ubji)}(h h]h }(hj- hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj; hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(h out_valueh]h out_value}(hjH hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h*wait until register matches expected stateh]h*wait until register matches expected state}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hjo hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhhhNhNubjX)}(hXr**Parameters** ``struct intel_uncore *uncore`` the struct intel_uncore ``i915_reg_t reg`` the register to read ``u32 mask`` mask to apply to register value ``u32 value`` expected value ``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait ``unsigned int slow_timeout_ms`` slow timeout in millisecond ``u32 *out_value`` optional placeholder to hold registry value **Description** This routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until :: (intel_uncore_read_fw(uncore, reg) & mask) == value Otherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds. Note that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow). **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubjx)}(hhh](j})}(h8``struct intel_uncore *uncore`` the struct intel_uncore h](j)}(h``struct intel_uncore *uncore``h]j)}(hj h]hstruct intel_uncore *uncore}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubj)}(hhh]h)}(hthe struct intel_uncoreh]hthe struct intel_uncore}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hM hj ubj})}(h(``i915_reg_t reg`` the register to read h](j)}(h``i915_reg_t reg``h]j)}(hj h]hi915_reg_t reg}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubj)}(hhh]h)}(hthe register to readh]hthe register to read}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj!hM hj ubj})}(h-``u32 mask`` mask to apply to register value h](j)}(h ``u32 mask``h]j)}(hj%!h]hu32 mask}(hj'!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hj>!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:!hM hj;!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j|hj:!hM hj ubj})}(h``u32 value`` expected value h](j)}(h ``u32 value``h]j)}(hj^!h]h u32 value}(hj`!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hjX!ubj)}(hhh]h)}(hexpected valueh]hexpected value}(hjw!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs!hM hjt!ubah}(h]h ]h"]h$]h&]uh1jhjX!ubeh}(h]h ]h"]h$]h&]uh1j|hjs!hM hj ubj})}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j)}(h ``unsigned int fast_timeout_us``h]j)}(hj!h]hunsigned int fast_timeout_us}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j|hj!hM hj ubj})}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j)}(h ``unsigned int slow_timeout_ms``h]j)}(hj!h]hunsigned int slow_timeout_ms}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j|hj!hM hj ubj})}(h?``u32 *out_value`` optional placeholder to hold registry value h](j)}(h``u32 *out_value``h]j)}(hj "h]hu32 *out_value}(hj "hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj"ubj)}(hhh]h)}(h+optional placeholder to hold registry valueh]h+optional placeholder to hold registry value}(hj""hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj"hM hj ubeh}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjD"h]h Description}(hjF"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjB"ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hjZ"hhhNhNubjb)}(h**reg**h]hreg}(hjb"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZ"ubh contains the expected }(hjZ"hhhNhNubjb)}(h **value**h]hvalue}(hjt"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZ"ubh after applying the }(hjZ"hhhNhNubjb)}(h**mask**h]hmask}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZ"ubh, i.e. it waits until}(hjZ"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh literal_block)}(h3(intel_uncore_read_fw(uncore, reg) & mask) == valueh]h3(intel_uncore_read_fw(uncore, reg) & mask) == value}hj"sbah}(h]h ]h"]h$]h&]jjuh1j"h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(hOtherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds.h](h'Otherwise, the wait will timeout after }(hj"hhhNhNubjb)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubh" milliseconds. For atomic context }(hj"hhhNhNubjb)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubh must be zero and }(hj"hhhNhNubjb)}(h**fast_timeout_us**h]hfast_timeout_us}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubh. must be not larger than 20,0000 microseconds.}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(hNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow).h]hNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow).}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(h **Return**h]jb)}(hj#h]hReturn}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&__intel_wait_for_register (C function)c.__intel_wait_for_registerhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hint __intel_wait_for_register (struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h]j2)}(hint __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j)}(hinth]hint}(hjK#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG#hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM ubji)}(h h]h }(hjZ#hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjG#hhhjY#hM ubjz)}(h__intel_wait_for_registerh]j;)}(h__intel_wait_for_registerh]h__intel_wait_for_register}(hjl#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjh#ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjG#hhhjY#hM ubj)}(h(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubji)}(h h]h }(hj#hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj#ubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj#modnameN classnameNjXj[)}j^]ja)}jTjn#sbc.__intel_wait_for_registerasbuh1hhj#ubji)}(h h]h }(hj#hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj#ubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj;)}(huncoreh]huncore}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hi915_reg_t regh](h)}(hhh]j;)}(h i915_reg_th]h i915_reg_t}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj#modnameN classnameNjXj[)}j^]j#c.__intel_wait_for_registerasbuh1hhj#ubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj#ubj;)}(hregh]hreg}(hj)$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hu32 maskh](h)}(hhh]j;)}(hu32h]hu32}(hjE$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjB$ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjG$modnameN classnameNjXj[)}j^]j#c.__intel_wait_for_registerasbuh1hhj>$ubji)}(h h]h }(hjc$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>$ubj;)}(hmaskh]hmask}(hjq$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>$ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj$modnameN classnameNjXj[)}j^]j#c.__intel_wait_for_registerasbuh1hhj$ubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubj;)}(hvalueh]hvalue}(hj$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hunsigned int fast_timeout_ush](j)}(hunsignedh]hunsigned}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubj)}(hinth]hint}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubj;)}(hfast_timeout_ush]hfast_timeout_us}(hj %hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hunsigned int slow_timeout_msh](j)}(hunsignedh]hunsigned}(hj#%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubji)}(h h]h }(hj1%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj%ubj)}(hinth]hint}(hj?%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubji)}(h h]h }(hjM%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj%ubj;)}(hslow_timeout_msh]hslow_timeout_ms}(hj[%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hu32 *out_valueh](h)}(hhh]j;)}(hu32h]hu32}(hjw%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjt%ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjy%modnameN classnameNjXj[)}j^]j#c.__intel_wait_for_registerasbuh1hhjp%ubji)}(h h]h }(hj%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjp%ubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp%ubj;)}(h out_valueh]h out_value}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjp%ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubeh}(h]h ]h"]h$]h&]jjuh1jhjG#hhhjY#hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjC#hhhjY#hM ubah}(h]j>#ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjY#hM hj@#hhubj1)}(hhh]h)}(h*wait until register matches expected stateh]h*wait until register matches expected state}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%hhubah}(h]h ]h"]h$]h&]uh1j0hj@#hhhjY#hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj%jSj%jTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_uncore *uncore`` the struct intel_uncore ``i915_reg_t reg`` the register to read ``u32 mask`` mask to apply to register value ``u32 value`` expected value ``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait ``unsigned int slow_timeout_ms`` slow timeout in millisecond ``u32 *out_value`` optional placeholder to hold registry value **Description** This routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until :: (intel_uncore_read(uncore, reg) & mask) == value Otherwise, the wait will timeout after **timeout_ms** milliseconds. **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]jb)}(hj%h]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj%ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubjx)}(hhh](j})}(h8``struct intel_uncore *uncore`` the struct intel_uncore h](j)}(h``struct intel_uncore *uncore``h]j)}(hj&h]hstruct intel_uncore *uncore}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh]h)}(hthe struct intel_uncoreh]hthe struct intel_uncore}(hj4&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0&hM hj1&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hj0&hM hj&ubj})}(h(``i915_reg_t reg`` the register to read h](j)}(h``i915_reg_t reg``h]j)}(hjT&h]hi915_reg_t reg}(hjV&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hjN&ubj)}(hhh]h)}(hthe register to readh]hthe register to read}(hjm&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji&hM hjj&ubah}(h]h ]h"]h$]h&]uh1jhjN&ubeh}(h]h ]h"]h$]h&]uh1j|hji&hM hj&ubj})}(h-``u32 mask`` mask to apply to register value h](j)}(h ``u32 mask``h]j)}(hj&h]hu32 mask}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hM hj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hj&hM hj&ubj})}(h``u32 value`` expected value h](j)}(h ``u32 value``h]j)}(hj&h]h u32 value}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh]h)}(hexpected valueh]hexpected value}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hM hj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hj&hM hj&ubj})}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j)}(h ``unsigned int fast_timeout_us``h]j)}(hj&h]hunsigned int fast_timeout_us}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM hj'ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hj'hM hj&ubj})}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j)}(h ``unsigned int slow_timeout_ms``h]j)}(hj8'h]hunsigned int slow_timeout_ms}(hj:'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6'ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj2'ubj)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hjQ'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM'hM hjN'ubah}(h]h ]h"]h$]h&]uh1jhj2'ubeh}(h]h ]h"]h$]h&]uh1j|hjM'hM hj&ubj})}(h?``u32 *out_value`` optional placeholder to hold registry value h](j)}(h``u32 *out_value``h]j)}(hjq'h]hu32 *out_value}(hjs'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo'ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hjk'ubj)}(hhh]h)}(h+optional placeholder to hold registry valueh]h+optional placeholder to hold registry value }(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM hj'ubah}(h]h ]h"]h$]h&]uh1jhjk'ubeh}(h]h ]h"]h$]h&]uh1j|hj'hM hj&ubeh}(h]h ]h"]h$]h&]uh1jwhj%ubh)}(h**Description**h]jb)}(hj'h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hj'hhhNhNubjb)}(h**reg**h]hreg}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubh contains the expected }(hj'hhhNhNubjb)}(h **value**h]hvalue}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubh after applying the }(hj'hhhNhNubjb)}(h**mask**h]hmask}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubh, i.e. it waits until}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubj")}(h0(intel_uncore_read(uncore, reg) & mask) == valueh]h0(intel_uncore_read(uncore, reg) & mask) == value}hj(sbah}(h]h ]h"]h$]h&]jjuh1j"h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubh)}(hCOtherwise, the wait will timeout after **timeout_ms** milliseconds.h](h'Otherwise, the wait will timeout after }(hj(hhhNhNubjb)}(h**timeout_ms**h]h timeout_ms}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj(ubh milliseconds.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubh)}(h **Return**h]jb)}(hj9(h]hReturn}(hj;(hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj7(ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hjO(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+intel_uncore_forcewake_for_reg (C function) c.intel_uncore_forcewake_for_reghNtauh1jhhhhhNhNubj')}(hhh](j,)}(htenum forcewake_domains intel_uncore_forcewake_for_reg (struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h]j2)}(hsenum forcewake_domains intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h](j)}(hjh]henum}(hj~(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz(hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM7 ubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz(hhhj(hM7 ubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj(modnameN classnameNjXj[)}j^]ja)}jTintel_uncore_forcewake_for_regsb c.intel_uncore_forcewake_for_regasbuh1hhjz(hhhj(hM7 ubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz(hhhj(hM7 ubjz)}(hintel_uncore_forcewake_for_regh]j;)}(hj(h]hintel_uncore_forcewake_for_reg}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjz(hhhj(hM7 ubj)}(h>(struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj(ubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj )hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj )modnameN classnameNjXj[)}j^]j( c.intel_uncore_forcewake_for_regasbuh1hhj(ubji)}(h h]h }(hj')hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj(ubj)}(hjh]h*}(hj5)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubj;)}(huncoreh]huncore}(hjB)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(ubj)}(hi915_reg_t regh](h)}(hhh]j;)}(h i915_reg_th]h i915_reg_t}(hj^)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj[)ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj`)modnameN classnameNjXj[)}j^]j( c.intel_uncore_forcewake_for_regasbuh1hhjW)ubji)}(h h]h }(hj|)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjW)ubj;)}(hregh]hreg}(hj)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjW)ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(ubj)}(hunsigned int oph](j)}(hunsignedh]hunsigned}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)ubj)}(hinth]hint}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)ubj;)}(hoph]hop}(hj)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(ubeh}(h]h ]h"]h$]h&]jjuh1jhjz(hhhj(hM7 ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjv(hhhj(hM7 ubah}(h]jq(ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj(hM7 hjs(hhubj1)}(hhh]h)}(h7which forcewake domains are needed to access a registerh]h7which forcewake domains are needed to access a register}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM* hj*hhubah}(h]h ]h"]h$]h&]uh1j0hjs(hhhj(hM7 ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj*jSj*jTjUjVuh1j&hhhhhNhNubjX)}(hXI**Parameters** ``struct intel_uncore *uncore`` pointer to struct intel_uncore ``i915_reg_t reg`` register in question ``unsigned int op`` operation bitmask of FW_REG_READ and/or FW_REG_WRITE **Description** Returns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors. **NOTE** On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.h](h)}(h**Parameters**h]jb)}(hj'*h]h Parameters}(hj)*hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj%*ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM. hj!*ubjx)}(hhh](j})}(h?``struct intel_uncore *uncore`` pointer to struct intel_uncore h](j)}(h``struct intel_uncore *uncore``h]j)}(hjF*h]hstruct intel_uncore *uncore}(hjH*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD*ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM, hj@*ubj)}(hhh]h)}(hpointer to struct intel_uncoreh]hpointer to struct intel_uncore}(hj_*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[*hM, hj\*ubah}(h]h ]h"]h$]h&]uh1jhj@*ubeh}(h]h ]h"]h$]h&]uh1j|hj[*hM, hj=*ubj})}(h(``i915_reg_t reg`` register in question h](j)}(h``i915_reg_t reg``h]j)}(hj*h]hi915_reg_t reg}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}*ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM- hjy*ubj)}(hhh]h)}(hregister in questionh]hregister in question}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM- hj*ubah}(h]h ]h"]h$]h&]uh1jhjy*ubeh}(h]h ]h"]h$]h&]uh1j|hj*hM- hj=*ubj})}(hI``unsigned int op`` operation bitmask of FW_REG_READ and/or FW_REG_WRITE h](j)}(h``unsigned int op``h]j)}(hj*h]hunsigned int op}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM. hj*ubj)}(hhh]h)}(h4operation bitmask of FW_REG_READ and/or FW_REG_WRITEh]h4operation bitmask of FW_REG_READ and/or FW_REG_WRITE}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM. hj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1j|hj*hM. hj=*ubeh}(h]h ]h"]h$]h&]uh1jwhj!*ubh)}(h**Description**h]jb)}(hj*h]h Description}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj*ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM0 hj!*ubh)}(hReturns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors.h]hReturns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors.}(hj +hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM0 hj!*ubh)}(h**NOTE**h]jb)}(hj+h]hNOTE}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj+ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM4 hj!*ubh)}(hOn Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.h]hOn Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.}(hj0+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM4 hj!*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubeh}(h]runtime-power-managementah ]h"]runtime power managementah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hInterrupt Handlingh]hInterrupt Handling}(hjQ+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjN+hhhhhKubh)}(hThese functions provide the basic support for enabling and disabling the interrupt handling support. There's a lot more functionality in i915_irq.c and related files, but that will be described in separate chapters.h]hThese functions provide the basic support for enabling and disabling the interrupt handling support. There’s a lot more functionality in i915_irq.c and related files, but that will be described in separate chapters.}(hj_+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/i915_irq.chK7hjN+hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_irq_init (C function)c.intel_irq_inithNtauh1jhjN+hhhNhNubj')}(hhh](j,)}(h7void intel_irq_init (struct drm_i915_private *dev_priv)h]j2)}(h6void intel_irq_init(struct drm_i915_private *dev_priv)h](j)}(hvoidh]hvoid}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMuubji)}(h h]h }(hj+hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+hhhj+hMuubjz)}(hintel_irq_inith]j;)}(hintel_irq_inith]hintel_irq_init}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj+hhhj+hMuubj)}(h#(struct drm_i915_private *dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubji)}(h h]h }(hj+hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj+modnameN classnameNjXj[)}j^]ja)}jTj+sbc.intel_irq_initasbuh1hhj+ubji)}(h h]h }(hj,hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+ubj)}(hjh]h*}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubj;)}(hdev_privh]hdev_priv}(hj,hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+ubah}(h]h ]h"]h$]h&]jjuh1jhj+hhhj+hMuubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj+hhhj+hMuubah}(h]jz+ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj+hMuhj|+hhubj1)}(hhh]h)}(hinitializes irq supporth]hinitializes irq support}(hjG,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMohjD,hhubah}(h]h ]h"]h$]h&]uh1j0hj|+hhhj+hMuubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj_,jSj_,jTjUjVuh1j&hhhjN+hNhNubjX)}(h**Parameters** ``struct drm_i915_private *dev_priv`` i915 device instance **Description** This function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.h](h)}(h**Parameters**h]jb)}(hji,h]h Parameters}(hjk,hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjg,ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMshjc,ubjx)}(hhh]j})}(h;``struct drm_i915_private *dev_priv`` i915 device instance h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hj,h]h!struct drm_i915_private *dev_priv}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMphj,ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMphj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1j|hj,hMphj,ubah}(h]h ]h"]h$]h&]uh1jwhjc,ubh)}(h**Description**h]jb)}(hj,h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMrhjc,ubh)}(hThis function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.h]hThis function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMrhjc,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjN+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_irq_suspend (C function)c.intel_irq_suspendhNtauh1jhjN+hhhNhNubj')}(hhh](j,)}(h6void intel_irq_suspend (struct drm_i915_private *i915)h]j2)}(h5void intel_irq_suspend(struct drm_i915_private *i915)h](j)}(hvoidh]hvoid}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj-hhhj-hMubjz)}(hintel_irq_suspendh]j;)}(hintel_irq_suspendh]hintel_irq_suspend}(hj)-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%-ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj-hhhj-hMubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjE-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA-ubji)}(h h]h }(hjR-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjA-ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjc-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`-ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetje-modnameN classnameNjXj[)}j^]ja)}jTj+-sbc.intel_irq_suspendasbuh1hhjA-ubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjA-ubj)}(hjh]h*}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA-ubj;)}(hi915h]hi915}(hj-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjA-ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=-ubah}(h]h ]h"]h$]h&]jjuh1jhj-hhhj-hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj-hhhj-hMubah}(h]j,ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj-hMhj,hhubj1)}(hhh]h)}(hSuspend interruptsh]hSuspend interrupts}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj-hhubah}(h]h ]h"]h$]h&]uh1j0hj,hhhj-hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj-jSj-jTjUjVuh1j&hhhjN+hNhNubjX)}(h**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** This function is used to disable interrupts at runtime.h](h)}(h**Parameters**h]jb)}(hj-h]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubjx)}(hhh]j})}(h7``struct drm_i915_private *i915`` i915 device instance h](j)}(h!``struct drm_i915_private *i915``h]j)}(hj .h]hstruct drm_i915_private *i915}(hj .hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj.ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj".hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hj.hMhj.ubah}(h]h ]h"]h$]h&]uh1jwhj-ubh)}(h**Description**h]jb)}(hjD.h]h Description}(hjF.hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjB.ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubh)}(h7This function is used to disable interrupts at runtime.h]h7This function is used to disable interrupts at runtime.}(hjZ.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjN+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_irq_resume (C function)c.intel_irq_resumehNtauh1jhjN+hhhNhNubj')}(hhh](j,)}(h5void intel_irq_resume (struct drm_i915_private *i915)h]j2)}(h4void intel_irq_resume(struct drm_i915_private *i915)h](j)}(hvoidh]hvoid}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chM#ubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.hhhj.hM#ubjz)}(hintel_irq_resumeh]j;)}(hintel_irq_resumeh]hintel_irq_resume}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj.hhhj.hM#ubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj.modnameN classnameNjXj[)}j^]ja)}jTj.sbc.intel_irq_resumeasbuh1hhj.ubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubj)}(hjh]h*}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubj;)}(hi915h]hi915}(hj/hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj.ubah}(h]h ]h"]h$]h&]jjuh1jhj.hhhj.hM#ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj.hhhj.hM#ubah}(h]j|.ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj.hM#hj~.hhubj1)}(hhh]h)}(hResume interruptsh]hResume interrupts}(hjI/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhjF/hhubah}(h]h ]h"]h$]h&]uh1j0hj~.hhhj.hM#ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRja/jSja/jTjUjVuh1j&hhhjN+hNhNubjX)}(h**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** This function is used to enable interrupts at runtime.h](h)}(h**Parameters**h]jb)}(hjk/h]h Parameters}(hjm/hhhNhNubah}(h]h ]h"]h$]h&]uh1jahji/ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chM"hje/ubjx)}(hhh]j})}(h7``struct drm_i915_private *i915`` i915 device instance h](j)}(h!``struct drm_i915_private *i915``h]j)}(hj/h]hstruct drm_i915_private *i915}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhj/ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1j|hj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jwhje/ubh)}(h**Description**h]jb)}(hj/h]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj/ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chM!hje/ubh)}(h6This function is used to enable interrupts at runtime.h]h6This function is used to enable interrupts at runtime.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chM!hje/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjN+hhhNhNubeh}(h]interrupt-handlingah ]h"]interrupt handlingah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hIntel GVT-g Guest Support(vGPU)h]hIntel GVT-g Guest Support(vGPU)}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhK,ubh)}(hXIntel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine. This file provides vGPU specific optimizations when running in a virtual machine, to reduce the complexity of vGPU emulation and to improve the overall performance.h]hXIntel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine. This file provides vGPU specific optimizations when running in a virtual machine, to reduce the complexity of vGPU emulation and to improve the overall performance.}(hj 0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:46: ./drivers/gpu/drm/i915/i915_vgpu.chKhj/hhubh)}(hXA primary function introduced here is so-called "address space ballooning" technique. Intel GVT-g partitions global graphics memory among multiple VMs, so each VM can directly access a portion of the memory without hypervisor's intervention, e.g. filling textures or queuing commands. However with the partitioning an unmodified i915 driver would assume a smaller graphics memory starting from address ZERO, then requires vGPU emulation module to translate the graphics address between 'guest view' and 'host view', for all registers and command opcodes which contain a graphics memory address. To reduce the complexity, Intel GVT-g introduces "address space ballooning", by telling the exact partitioning knowledge to each guest i915 driver, which then reserves and prevents non-allocated portions from allocation. Thus vGPU emulation module only needs to scan and validate graphics addresses without complexity of address translation.h]hXA primary function introduced here is so-called “address space ballooning” technique. Intel GVT-g partitions global graphics memory among multiple VMs, so each VM can directly access a portion of the memory without hypervisor’s intervention, e.g. filling textures or queuing commands. However with the partitioning an unmodified i915 driver would assume a smaller graphics memory starting from address ZERO, then requires vGPU emulation module to translate the graphics address between ‘guest view’ and ‘host view’, for all registers and command opcodes which contain a graphics memory address. To reduce the complexity, Intel GVT-g introduces “address space ballooning”, by telling the exact partitioning knowledge to each guest i915 driver, which then reserves and prevents non-allocated portions from allocation. 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The ballooning related knowledge(starting address and size of the mappable/unmappable graphic memory) is described in the vgt_if structure in a reserved mmio range.h]hXAThis function is called at the initialization stage, to balloon out the graphic address space allocated to other vGPUs, by marking these spaces as reserved. The ballooning related knowledge(starting address and size of the mappable/unmappable graphic memory) is described in the vgt_if structure in a reserved mmio range.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(hX(To give an example, the drawing below depicts one typical scenario after ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned out each for the mappable and the non-mappable part. From the vGPU1 point of view, the total size is the same as the physical one, with the start address of its graphic space being zero. Yet there are some portions ballooned out( the shadow part, which are marked as reserved by drm allocator). From the host point of view, the graphic address space is partitioned by multiple vGPUs in different VMs. ::h]hX%To give an example, the drawing below depicts one typical scenario after ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned out each for the mappable and the non-mappable part. From the vGPU1 point of view, the total size is the same as the physical one, with the start address of its graphic space being zero. Yet there are some portions ballooned out( the shadow part, which are marked as reserved by drm allocator). From the host point of view, the graphic address space is partitioned by multiple vGPUs in different VMs.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubj")}(hXk vGPU1 view Host view 0 ------> +-----------+ +-----------+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ mappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | v |###########| | Host | +=======+===========+ +===========+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ unmappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | | |###########| | Host | v |###########| | | total GM size ------> +-----------+ +-----------+h]hXk vGPU1 view Host view 0 ------> +-----------+ +-----------+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ mappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | v |###########| | Host | +=======+===========+ +===========+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ unmappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | | |###########| | Host | v |###########| | | total GM size ------> +-----------+ +-----------+}hj4sbah}(h]h ]h"]h$]h&]jjuh1j"hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(h **Return**h]jb)}(hj4h]hReturn}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj4ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(hGzero on success, non-zero if configuration invalid or ballooning failedh]hGzero on success, non-zero if configuration invalid or ballooning failed}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj/hhhNhNubeh}(h]intel-gvt-g-guest-support-vgpuah ]h"]intel gvt-g guest support(vgpu)ah$]h&]uh1hhhhhhhhK,ubh)}(hhh](h)}(h+Intel GVT-g Host Support(vGPU device model)h]h+Intel GVT-g Host Support(vGPU device model)}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhK5ubh)}(hX6Intel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. 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*dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj5ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj5ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj5modnameN classnameNjXj[)}j^]ja)}jTjx5sbc.intel_gvt_initasbuh1hhj5ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj5ubj)}(hjh]h*}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubj;)}(hdev_privh]hdev_priv}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj5ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj5ubah}(h]h ]h"]h$]h&]jjuh1jhjQ5hhhjc5hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjM5hhhjc5hKubah}(h]jH5ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjc5hKhjJ5hhubj1)}(hhh]h)}(hinitialize GVT componentsh]hinitialize GVT components}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj6hhubah}(h]h ]h"]h$]h&]uh1j0hjJ5hhhjc5hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj-6jSj-6jTjUjVuh1j&hhhj4hNhNubjX)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private data **Description** This function is called at the initialization stage to create a GVT device. **Return** Zero on success, negative error code if failed.h](h)}(h**Parameters**h]jb)}(hj76h]h Parameters}(hj96hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj56ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubjx)}(hhh]j})}(h<``struct drm_i915_private *dev_priv`` drm i915 private data h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hjV6h]h!struct drm_i915_private *dev_priv}(hjX6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhjP6ubj)}(hhh]h)}(hdrm i915 private datah]hdrm i915 private data}(hjo6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk6hKhjl6ubah}(h]h ]h"]h$]h&]uh1jhjP6ubeh}(h]h ]h"]h$]h&]uh1j|hjk6hKhjM6ubah}(h]h ]h"]h$]h&]uh1jwhj16ubh)}(h**Description**h]jb)}(hj6h]h Description}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj6ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubh)}(hKThis function is called at the initialization stage to create a GVT device.h]hKThis function is called at the initialization stage to create a GVT device.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubh)}(h **Return**h]jb)}(hj6h]hReturn}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj6ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubh)}(h/Zero on success, negative error code if failed.h]h/Zero on success, negative error code if failed.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj4hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_gvt_driver_remove (C function)c.intel_gvt_driver_removehNtauh1jhj4hhhNhNubj')}(hhh](j,)}(h@void intel_gvt_driver_remove (struct drm_i915_private *dev_priv)h]j2)}(h?void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)h](j)}(hvoidh]hvoid}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMubji)}(h h]h }(hj 7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj6hhhj 7hMubjz)}(hintel_gvt_driver_removeh]j;)}(hintel_gvt_driver_removeh]hintel_gvt_driver_remove}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj6hhhj 7hMubj)}(h#(struct drm_i915_private *dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hj:7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj67ubji)}(h h]h }(hjG7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj67ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjX7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjU7ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjZ7modnameN classnameNjXj[)}j^]ja)}jTj 7sbc.intel_gvt_driver_removeasbuh1hhj67ubji)}(h h]h }(hjx7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj67ubj)}(hjh]h*}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj67ubj;)}(hdev_privh]hdev_priv}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj67ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj27ubah}(h]h ]h"]h$]h&]jjuh1jhj6hhhj 7hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj6hhhj 7hMubah}(h]j6ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj 7hMhj6hhubj1)}(hhh]h)}(h4cleanup GVT components when i915 driver is unbindingh]h4cleanup GVT components when i915 driver is unbinding}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj7hhubah}(h]h ]h"]h$]h&]uh1j0hj6hhhj 7hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj7jSj7jTjUjVuh1j&hhhj4hNhNubjX)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private * **Description** This function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.h](h)}(h**Parameters**h]jb)}(hj7h]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj7ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhj7ubjx)}(hhh]j})}(h9``struct drm_i915_private *dev_priv`` drm i915 private * h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hj7h]h!struct drm_i915_private *dev_priv}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj7ubj)}(hhh]h)}(hdrm i915 private *h]hdrm i915 private *}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hKhj8ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1j|hj8hKhj7ubah}(h]h ]h"]h$]h&]uh1jwhj7ubh)}(h**Description**h]jb)}(hj98h]h Description}(hj;8hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj78ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhj7ubh)}(hyThis function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.h]hyThis function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.}(hjO8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj4hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_gvt_resume (C function)c.intel_gvt_resumehNtauh1jhj4hhhNhNubj')}(hhh](j,)}(h9void intel_gvt_resume (struct drm_i915_private *dev_priv)h]j2)}(h8void intel_gvt_resume(struct drm_i915_private *dev_priv)h](j)}(hvoidh]hvoid}(hj~8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz8hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz8hhhj8hMubjz)}(hintel_gvt_resumeh]j;)}(hintel_gvt_resumeh]hintel_gvt_resume}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjz8hhhj8hMubj)}(h#(struct drm_i915_private *dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj8ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj8modnameN classnameNjXj[)}j^]ja)}jTj8sbc.intel_gvt_resumeasbuh1hhj8ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj8ubj)}(hjh]h*}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj;)}(hdev_privh]hdev_priv}(hj9hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj8ubah}(h]h ]h"]h$]h&]jjuh1jhjz8hhhj8hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjv8hhhj8hMubah}(h]jq8ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj8hMhjs8hhubj1)}(hhh]h)}(hGVT resume routine wrapperh]hGVT resume routine wrapper}(hj>9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chM hj;9hhubah}(h]h ]h"]h$]h&]uh1j0hjs8hhhj8hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjV9jSjV9jTjUjVuh1j&hhhj4hNhNubjX)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private * **Description** This function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.h](h)}(h**Parameters**h]jb)}(hj`9h]h Parameters}(hjb9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj^9ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhjZ9ubjx)}(hhh]j})}(h9``struct drm_i915_private *dev_priv`` drm i915 private * Ih](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hj9h]h!struct drm_i915_private *dev_priv}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhjy9ubj)}(hhh]h)}(hdrm i915 private *h]hdrm i915 private *}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhjy9ubeh}(h]h ]h"]h$]h&]uh1j|hj9hMhjv9ubah}(h]h ]h"]h$]h&]uh1jwhjZ9ubh)}(h**Description**h]jb)}(hj9h]h Description}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj9ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhjZ9ubh)}(hThis function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.h]hThis function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhjZ9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj4hhhNhNubeh}(h]*intel-gvt-g-host-support-vgpu-device-modelah ]h"]+intel gvt-g host support(vgpu device model)ah$]h&]uh1hhhhhhhhK5ubh)}(hhh](h)}(h Workaroundsh]h Workarounds}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhK>ubh)}(hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:h]hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKhj9hhubh bullet_list)}(hhh](h list_item)}(hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers. Context workarounds should be implemented in the \*_ctx_workarounds_init() variants respective to the targeted platforms. h](h)}(hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers.h]hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a “primed golden context”, i.e. a context image that already contains the changes needed to all the registers.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKhj:ubh)}(hyContext workarounds should be implemented in the \*_ctx_workarounds_init() variants respective to the targeted platforms.h]hyContext workarounds should be implemented in the *_ctx_workarounds_init() variants respective to the targeted platforms.}(hj(:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK#hj:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hX Engine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. Workarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine's MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode(). h](h)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference.h](hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It’s also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See }(hjA:hhhNhNubj)}(h.``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c``h]h*drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c}(hjI:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA:ubh for reference.}(hjA:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK&hj=:ubh)}(hXWorkarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine's MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode().h]hXWorkarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine’s MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode().}(hjb:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK2hj=:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hXGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc. GT workarounds should be implemented in the \*_gt_workarounds_init() variants respective to the targeted platforms. h](h)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc.h](hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume }(hj{:hhhNhNubhfootnote_reference)}(h[1]_h]h1}(hj:hhhNhNubah}(h]id1ah ]h"]h$]h&]refidid2docnamegpu/i915uh1j:hj{:resolvedKubh, etc.}(hj{:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK:hjw:ubh)}(hsGT workarounds should be implemented in the \*_gt_workarounds_init() variants respective to the targeted platforms.h]hsGT workarounds should be implemented in the *_gt_workarounds_init() variants respective to the targeted platforms.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK=hjw:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hXRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers). Register whitelisting should be done in the \*_whitelist_build() variants respective to the targeted platforms. h](h)}(hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).h]hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK@hj:ubh)}(hoRegister whitelisting should be done in the \*_whitelist_build() variants respective to the targeted platforms.h]hoRegister whitelisting should be done in the *_whitelist_build() variants respective to the targeted platforms.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKFhj:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hX`Workaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms: #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms. #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver. h](h)}(hXRWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms:h]hXRWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms:}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKIhj:ubhenumerated_list)}(hhh](j:)}(hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms. h]h)}(hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms.h]hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKOhj:ubah}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver. h]h)}(hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver.h]hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKThj;ubah}(h]h ]h"]h$]h&]uh1j:hj:ubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j:hj:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example. h]h)}(hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example.h]hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example.}(hj@;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKYhj<;ubah}(h]h ]h"]h$]h&]uh1j:hj:ubeh}(h]h ]h"]h$]h&]bullet-uh1j:hj':hKhj9hhubhfootnote)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver. h](hlabel)}(h1h]h1}(hje;hhhNhNubah}(h]h ]h"]h$]h&]uh1jc;hj_;ubh)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver.h]hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it’s the approach taken in the driver.}(hjs;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK]hj_;ubeh}(h]j:ah ]h"]1ah$]h&]j:aj:j:uh1j];hj;hK]hj9hhj:Kubeh}(h] workaroundsah ]h"] workaroundsah$]h&]uh1hhhhhhhhK>ubeh}(h]core-driver-infrastructureah ]h"]core driver infrastructureah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hDisplay Hardware Handlingh]hDisplay Hardware Handling}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhKDubh)}(hThis section covers everything related to the display hardware including the mode setting infrastructure, plane, sprite and cursor handling and display, output probing and related topics.h]hThis section covers everything related to the display hardware including the mode setting infrastructure, plane, sprite and cursor handling and display, output probing and related topics.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhj;hhubh)}(hhh](h)}(hMode Setting Infrastructureh]hMode Setting Infrastructure}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhKKubh)}(hThe i915 driver is thus far the only DRM driver which doesn't use the common DRM helper code to implement mode setting sequences. Thus it has its own tailor-made infrastructure for executing a display configuration change.h]hThe i915 driver is thus far the only DRM driver which doesn’t use the common DRM helper code to implement mode setting sequences. Thus it has its own tailor-made infrastructure for executing a display configuration change.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhj;hhubeh}(h]mode-setting-infrastructureah ]h"]mode setting infrastructureah$]h&]uh1hhj;hhhhhKKubh)}(hhh](h)}(hFrontbuffer Trackingh]hFrontbuffer Tracking}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhKSubh)}(hMany features require us to track changes to the currently active frontbuffer, especially rendering targeted at the frontbuffer.h]hMany features require us to track changes to the currently active frontbuffer, especially rendering targeted at the frontbuffer.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:85: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj;hhubh)}(hX To be able to do so we track frontbuffers using a bitmask for all possible frontbuffer slots through intel_frontbuffer_track(). The functions in this file are then called when the contents of the frontbuffer are invalidated, when frontbuffer rendering has stopped again to flush out all the changes and when the frontbuffer is exchanged with a flip. Subsystems interested in frontbuffer changes (e.g. PSR, FBC, DRRS) should directly put their callbacks into the relevant places and filter for the frontbuffer slots that they are interested int.h]hX To be able to do so we track frontbuffers using a bitmask for all possible frontbuffer slots through intel_frontbuffer_track(). The functions in this file are then called when the contents of the frontbuffer are invalidated, when frontbuffer rendering has stopped again to flush out all the changes and when the frontbuffer is exchanged with a flip. Subsystems interested in frontbuffer changes (e.g. PSR, FBC, DRRS) should directly put their callbacks into the relevant places and filter for the frontbuffer slots that they are interested int.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:85: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj;hhubh)}(hX&On a high level there are two types of powersaving features. The first one work like a special cache (FBC and PSR) and are interested when they should stop caching and when to restart caching. This is done by placing callbacks into the invalidate and the flush functions: At invalidate the caching must be stopped and at flush time it can be restarted. And maybe they need to know when the frontbuffer changes (e.g. when the hw doesn't initiate an invalidate and flush on its own) which can be achieved with placing callbacks into the flip functions.h]hX(On a high level there are two types of powersaving features. The first one work like a special cache (FBC and PSR) and are interested when they should stop caching and when to restart caching. This is done by placing callbacks into the invalidate and the flush functions: At invalidate the caching must be stopped and at flush time it can be restarted. And maybe they need to know when the frontbuffer changes (e.g. when the hw doesn’t initiate an invalidate and flush on its own) which can be achieved with placing callbacks into the flip functions.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:85: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chK(hj;hhubh)}(hXRThe other type of display power saving feature only cares about busyness (e.g. DRRS). In that case all three (invalidate, flush and flip) indicate busyness. There is no direct way to detect idleness. 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?ubh)}(hhh]j;)}(h fb_op_originh]h fb_op_origin}(hj.?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+?ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0?modnameN classnameNjXj[)}j^]j>c.intel_frontbuffer_flushasbuh1hhj ?ubji)}(h h]h }(hjL?hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ?ubj;)}(horiginh]horigin}(hjZ?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ?ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubeh}(h]h ]h"]h$]h&]jjuh1jhj]>hhhjo>hK~ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjY>hhhjo>hK~ubah}(h]jT>ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjo>hK~hjV>hhubj1)}(hhh]h)}(hflush frontbuffer objecth]hflush frontbuffer object}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:88: ./drivers/gpu/drm/i915/display/intel_frontbuffer.hhKwhj?hhubah}(h]h ]h"]h$]h&]uh1j0hjV>hhhjo>hK~ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj?jSj?jTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_frontbuffer *front`` GEM object to flush ``enum fb_op_origin origin`` which operation caused the flush **Description** This function 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originh](j)}(hjh]henum}(hj~AhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzAubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzAubh)}(hhh]j;)}(h fb_op_originh]h fb_op_origin}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjAmodnameN classnameNjXj[)}j^]j@c.frontbuffer_flushasbuh1hhjzAubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzAubj;)}(horiginh]horigin}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzAubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj@ubeh}(h]h ]h"]h$]h&]jjuh1jhjz@hhhj@hKUubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjv@hhhj@hKUubah}(h]jq@ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj@hKUhjs@hhubj1)}(hhh]h)}(hflush frontbufferh]hflush frontbuffer}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKJhjAhhubah}(h]h ]h"]h$]h&]uh1j0hjs@hhhj@hKUubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj BjSj BjTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct drm_i915_private *i915`` i915 device ``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the flush **Description** This function gets called every time rendering on the given planes has completed and frontbuffer caching can be started again. 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Can be called without any locks held.h](h)}(h**Parameters**h]jb)}(hjKDh]h Parameters}(hjMDhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjIDubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKqhjEDubjx)}(hhh](j})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjjDh]hstruct drm_i915_private *i915}(hjlDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhDubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKnhjdDubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhKnhjDubah}(h]h ]h"]h$]h&]uh1jhjdDubeh}(h]h ]h"]h$]h&]uh1j|hjDhKnhjaDubj})}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h``unsigned frontbuffer_bits``h]j)}(hjDh]hunsigned frontbuffer_bits}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKohjDubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhKohjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j|hjDhKohjaDubeh}(h]h ]h"]h$]h&]uh1jwhjEDubh)}(h**Description**h]jb)}(hjDh]h Description}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjDubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKqhjEDubh)}(hThis function gets called after scheduling a flip on **obj**. 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]h"]h$]h&]jjj"uh1j1j#j$hjJIhhhj`IhKubah}(h]jEIah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj`IhKhjGIhhubj1)}(hhh]h)}(h!queue flushing frontbuffer objecth]h!queue flushing frontbuffer object}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhjJhhubah}(h]h ]h"]h$]h&]uh1j0hjGIhhhj`IhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj*JjSj*JjTjUjVuh1j&hhhj;hNhNubjX)}(h**Parameters** ``struct intel_frontbuffer *front`` GEM object to flush **Description** This function is targeted for our dirty callback for queueing flush when dma fence is signalsh](h)}(h**Parameters**h]jb)}(hj4Jh]h Parameters}(hj6JhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj2Jubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj.Jubjx)}(hhh]j})}(h8``struct intel_frontbuffer *front`` GEM object to flush h](j)}(h#``struct intel_frontbuffer *front``h]j)}(hjSJh]hstruct intel_frontbuffer *front}(hjUJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQJubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhjMJubj)}(hhh]h)}(hGEM object to flushh]hGEM object to flush}(hjlJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhJhKhjiJubah}(h]h ]h"]h$]h&]uh1jhjMJubeh}(h]h ]h"]h$]h&]uh1j|hjhJhKhjJJubah}(h]h ]h"]h$]h&]uh1jwhj.Jubh)}(h**Description**h]jb)}(hjJh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjJubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj.Jubh)}(h]This function is targeted for our dirty callback for queueing flush when dma fence is signalsh]h]This function is targeted for our dirty callback for queueing flush when dma fence is signals}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj.Jubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_frontbuffer_track (C function)c.intel_frontbuffer_trackhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hzvoid intel_frontbuffer_track (struct intel_frontbuffer *old, struct intel_frontbuffer *new, unsigned int frontbuffer_bits)h]j2)}(hyvoid intel_frontbuffer_track(struct intel_frontbuffer *old, struct intel_frontbuffer *new, unsigned int frontbuffer_bits)h](j)}(hvoidh]hvoid}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJhhhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chMGubji)}(h h]h }(hjJhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJhhhjJhMGubjz)}(hintel_frontbuffer_trackh]j;)}(hintel_frontbuffer_trackh]hintel_frontbuffer_track}(hjJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjJubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjJhhhjJhMGubj)}(h](struct intel_frontbuffer *old, struct intel_frontbuffer *new, unsigned int frontbuffer_bits)h](j)}(hstruct intel_frontbuffer *oldh](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Kubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj Kubh)}(hhh]j;)}(hintel_frontbufferh]hintel_frontbuffer}(hj.KhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+Kubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0KmodnameN classnameNjXj[)}j^]ja)}jTjJsbc.intel_frontbuffer_trackasbuh1hhj Kubji)}(h h]h }(hjNKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj Kubj)}(hjh]h*}(hj\KhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Kubj;)}(holdh]hold}(hjiKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj Kubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubj)}(hstruct intel_frontbuffer *newh](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Kubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~Kubh)}(hhh]j;)}(hintel_frontbufferh]hintel_frontbuffer}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjKmodnameN classnameNjXj[)}j^]jJKc.intel_frontbuffer_trackasbuh1hhj~Kubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~Kubj)}(hjh]h*}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Kubj;)}(hnewh]hnew}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~Kubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubj)}(hunsigned int frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hjLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj)}(hinth]hint}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hjLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hj*LhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubeh}(h]h ]h"]h$]h&]jjuh1jhjJhhhjJhMGubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjJhhhjJhMGubah}(h]jJah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjJhMGhjJhhubj1)}(hhh]h)}(hupdate frontbuffer trackingh]hupdate frontbuffer tracking}(hjTLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM?hjQLhhubah}(h]h ]h"]h$]h&]uh1j0hjJhhhjJhMGubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjlLjSjlLjTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_frontbuffer *old`` current buffer for the frontbuffer slots ``struct intel_frontbuffer *new`` new buffer for the frontbuffer slots ``unsigned int frontbuffer_bits`` bitmask of frontbuffer slots **Description** This updates the frontbuffer tracking bits **frontbuffer_bits** by clearing them from **old** and setting them in **new**. Both **old** and **new** can be NULL.h](h)}(h**Parameters**h]jb)}(hjvLh]h Parameters}(hjxLhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtLubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chMChjpLubjx)}(hhh](j})}(hK``struct intel_frontbuffer *old`` current buffer for the frontbuffer slots h](j)}(h!``struct intel_frontbuffer *old``h]j)}(hjLh]hstruct intel_frontbuffer *old}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM@hjLubj)}(hhh]h)}(h(current buffer for the frontbuffer slotsh]h(current buffer for the frontbuffer slots}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM@hjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjLhM@hjLubj})}(hG``struct intel_frontbuffer *new`` new buffer for the frontbuffer slots h](j)}(h!``struct intel_frontbuffer *new``h]j)}(hjLh]hstruct intel_frontbuffer *new}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chMAhjLubj)}(hhh]h)}(h$new buffer for the frontbuffer slotsh]h$new buffer for the frontbuffer slots}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhMAhjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjLhMAhjLubj})}(h?``unsigned int frontbuffer_bits`` bitmask of frontbuffer slots h](j)}(h!``unsigned int frontbuffer_bits``h]j)}(hjMh]hunsigned int frontbuffer_bits}(hj MhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chMBhjMubj)}(hhh]h)}(hbitmask of frontbuffer slotsh]hbitmask of frontbuffer slots}(hj MhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhMBhjMubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j|hjMhMBhjLubeh}(h]h ]h"]h$]h&]uh1jwhjpLubh)}(h**Description**h]jb)}(hjBMh]h Description}(hjDMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj@Mubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chMDhjpLubh)}(hThis updates the frontbuffer tracking bits **frontbuffer_bits** by clearing them from **old** and setting them in **new**. Both **old** and **new** can be NULL.h](h+This updates the frontbuffer tracking bits }(hjXMhhhNhNubjb)}(h**frontbuffer_bits**h]hfrontbuffer_bits}(hj`MhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh by clearing them from }(hjXMhhhNhNubjb)}(h**old**h]hold}(hjrMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh and setting them in }(hjXMhhhNhNubjb)}(h**new**h]hnew}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh. Both }(hjXMhhhNhNubjb)}(h**old**h]hold}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh and }(hjXMhhhNhNubjb)}(h**new**h]hnew}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh can be NULL.}(hjXMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chMDhjpLubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubeh}(h]frontbuffer-trackingah ]h"]frontbuffer trackingah$]h&]uh1hhj;hhhhhKSubh)}(hhh](h)}(hDisplay FIFO Underrun Reportingh]hDisplay FIFO Underrun Reporting}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhK_ubh)}(hThe i915 driver checks for display fifo underruns using the interrupt signals provided by the hardware. This is enabled by default and fairly useful to debug display issues, especially watermark settings.h]hThe i915 driver checks for display fifo underruns using the interrupt signals provided by the hardware. This is enabled by default and fairly useful to debug display issues, especially watermark settings.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:97: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK'hjMhhubh)}(hIf an underrun is detected this is logged into dmesg. To avoid flooding logs and occupying the cpu underrun interrupts are disabled after the first occurrence until the next modeset on a given pipe.h]hIf an underrun is detected this is logged into dmesg. To avoid flooding logs and occupying the cpu underrun interrupts are disabled after the first occurrence until the next modeset on a given pipe.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:97: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK+hjMhhubh)}(hXFNote that underrun detection on gmch platforms is a bit more ugly since there is no interrupt (despite that the signalling bit is in the PIPESTAT pipe interrupt register). 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Also on some other platforms underrun interrupts are shared, which means that if we detect an underrun we need to disable underrun reporting on all pipes.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:97: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK/hjMhhubh)}(h@The code also supports underrun detection on the PCH transcoder.h]h@The code also supports underrun detection on the PCH transcoder.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:97: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK5hjMhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"2intel_set_cpu_fifo_underrun_reporting (C function)'c.intel_set_cpu_fifo_underrun_reportinghNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hgbool intel_set_cpu_fifo_underrun_reporting (struct intel_display *display, enum pipe pipe, bool enable)h]j2)}(hfbool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable)h](j)}(hjh]hbool}(hj6NhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2Nhhhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM1ubji)}(h h]h }(hjDNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2NhhhjCNhM1ubjz)}(h%intel_set_cpu_fifo_underrun_reportingh]j;)}(h%intel_set_cpu_fifo_underrun_reportingh]h%intel_set_cpu_fifo_underrun_reporting}(hjVNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRNubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj2NhhhjCNhM1ubj)}(h<(struct intel_display *display, enum pipe pipe, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjrNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnNubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnNubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjNmodnameN classnameNjXj[)}j^]ja)}jTjXNsb'c.intel_set_cpu_fifo_underrun_reportingasbuh1hhjnNubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnNubj)}(hjh]h*}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnNubj;)}(hdisplayh]hdisplay}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnNubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjNubj)}(henum pipe pipeh](j)}(hjh]henum}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjNubh)}(hhh]j;)}(hpipeh]hpipe}(hjOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjOmodnameN classnameNjXj[)}j^]jN'c.intel_set_cpu_fifo_underrun_reportingasbuh1hhjNubji)}(h h]h }(hj OhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjNubj;)}(hpipeh]hpipe}(hj.OhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjNubj)}(h bool enableh](j)}(hjh]hbool}(hjGOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCOubji)}(h h]h }(hjTOhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjCOubj;)}(henableh]henable}(hjbOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCOubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjNubeh}(h]h ]h"]h$]h&]jjuh1jhj2NhhhjCNhM1ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj.NhhhjCNhM1ubah}(h]j)Nah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjCNhM1hj+Nhhubj1)}(hhh]h)}(h%set cpu fifo underrun reporting stateh]h%set cpu fifo underrun reporting state}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM"hjOhhubah}(h]h ]h"]h$]h&]uh1j0hj+NhhhjCNhM1ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjOjSjOjTjUjVuh1j&hhhjMhNhNubjX)}(hXc**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pipe`` (CPU) pipe to set state for ``bool enable`` whether underruns should be reported or not **Description** This function sets the fifo underrun state for **pipe**. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe. Notice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though. Returns the previous state of underrun reporting.h](h)}(h**Parameters**h]jb)}(hjOh]h Parameters}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjOubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM&hjOubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjOh]hstruct intel_display *display}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM#hjOubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhM#hjOubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j|hjOhM#hjOubj})}(h/``enum pipe pipe`` (CPU) pipe to set state for h](j)}(h``enum pipe pipe``h]j)}(hjPh]henum pipe pipe}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM$hjPubj)}(hhh]h)}(h(CPU) pipe to set state forh]h(CPU) pipe to set state for}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM$hjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j|hjPhM$hjOubj})}(h<``bool enable`` whether underruns should be reported or not h](j)}(h``bool enable``h]j)}(hj?Ph]h bool enable}(hjAPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=Pubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM%hj9Pubj)}(hhh]h)}(h+whether underruns should be reported or noth]h+whether underruns should be reported or not}(hjXPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTPhM%hjUPubah}(h]h ]h"]h$]h&]uh1jhj9Pubeh}(h]h ]h"]h$]h&]uh1j|hjTPhM%hjOubeh}(h]h ]h"]h$]h&]uh1jwhjOubh)}(h**Description**h]jb)}(hjzPh]h Description}(hj|PhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjxPubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM'hjOubh)}(hThis function sets the fifo underrun state for **pipe**. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe.h](h/This function sets the fifo underrun state for }(hjPhhhNhNubjb)}(h**pipe**h]hpipe}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjPubh. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM'hjOubh)}(hNotice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though.h]hNotice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM+hjOubh)}(h1Returns the previous state of underrun reporting.h]h1Returns the previous state of underrun reporting.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM/hjOubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"2intel_set_pch_fifo_underrun_reporting (C function)'c.intel_set_pch_fifo_underrun_reportinghNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hqbool intel_set_pch_fifo_underrun_reporting (struct intel_display *display, enum pipe pch_transcoder, bool enable)h]j2)}(hpbool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable)h](j)}(hjh]hbool}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMMubji)}(h h]h }(hjPhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjPhhhjPhMMubjz)}(h%intel_set_pch_fifo_underrun_reportingh]j;)}(h%intel_set_pch_fifo_underrun_reportingh]h%intel_set_pch_fifo_underrun_reporting}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj Qubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjPhhhjPhMMubj)}(hF(struct intel_display *display, enum pipe pch_transcoder, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj+QhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'Qubji)}(h h]h }(hj8QhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'Qubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjIQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFQubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjKQmodnameN classnameNjXj[)}j^]ja)}jTjQsb'c.intel_set_pch_fifo_underrun_reportingasbuh1hhj'Qubji)}(h h]h }(hjiQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'Qubj)}(hjh]h*}(hjwQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'Qubj;)}(hdisplayh]hdisplay}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'Qubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#Qubj)}(henum pipe pch_transcoderh](j)}(hjh]henum}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubh)}(hhh]j;)}(hpipeh]hpipe}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjQmodnameN classnameNjXj[)}j^]jeQ'c.intel_set_pch_fifo_underrun_reportingasbuh1hhjQubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj;)}(hpch_transcoderh]hpch_transcoder}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#Qubj)}(h bool enableh](j)}(hjh]hbool}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hj RhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj;)}(henableh]henable}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#Qubeh}(h]h ]h"]h$]h&]jjuh1jhjPhhhjPhMMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjPhhhjPhMMubah}(h]jPah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjPhMMhjPhhubj1)}(hhh]h)}(h%set PCH fifo underrun reporting stateh]h%set PCH fifo underrun reporting state}(hjERhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM@hjBRhhubah}(h]h ]h"]h$]h&]uh1j0hjPhhhjPhMMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj]RjSj]RjTjUjVuh1j&hhhjMhNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) ``bool enable`` whether underruns should be reported or not **Description** This function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there's just one interrupt mask/enable bit for all the transcoders. Returns the previous state of underrun reporting.h](h)}(h**Parameters**h]jb)}(hjgRh]h Parameters}(hjiRhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjeRubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMDhjaRubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjRh]hstruct intel_display *display}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMAhjRubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhMAhjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j|hjRhMAhj}Rubj})}(hP``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) h](j)}(h``enum pipe pch_transcoder``h]j)}(hjRh]henum pipe pch_transcoder}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMBhjRubj)}(hhh]h)}(h2the PCH transcoder (same as pipe on IVB and older)h]h2the PCH transcoder (same as pipe on IVB and older)}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhMBhjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j|hjRhMBhj}Rubj})}(h<``bool enable`` whether underruns should be reported or not h](j)}(h``bool enable``h]j)}(hjRh]h bool enable}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMChjRubj)}(hhh]h)}(h+whether underruns should be reported or noth]h+whether underruns should be reported or not}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ShMChjSubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j|hj ShMChj}Rubeh}(h]h ]h"]h$]h&]uh1jwhjaRubh)}(h**Description**h]jb)}(hj3Sh]h Description}(hj5ShhhNhNubah}(h]h ]h"]h$]h&]uh1jahj1Subah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMEhjaRubh)}(hX_This function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there's just one interrupt mask/enable bit for all the transcoders.h]hXaThis function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there’s just one interrupt mask/enable bit for all the transcoders.}(hjIShhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMEhjaRubh)}(h1Returns the previous state of underrun reporting.h]h1Returns the previous state of underrun reporting.}(hjXShhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMKhjaRubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"0intel_cpu_fifo_underrun_irq_handler (C function)%c.intel_cpu_fifo_underrun_irq_handlerhNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hXvoid intel_cpu_fifo_underrun_irq_handler (struct intel_display *display, enum pipe pipe)h]j2)}(hWvoid intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pipe)h](j)}(hvoidh]hvoid}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjShhhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMzubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjShhhjShMzubjz)}(h#intel_cpu_fifo_underrun_irq_handlerh]j;)}(h#intel_cpu_fifo_underrun_irq_handlerh]h#intel_cpu_fifo_underrun_irq_handler}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjShhhjShMzubj)}(h/(struct intel_display *display, enum pipe pipe)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjSmodnameN classnameNjXj[)}j^]ja)}jTjSsb%c.intel_cpu_fifo_underrun_irq_handlerasbuh1hhjSubji)}(h h]h }(hjThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubj)}(hjh]h*}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubj;)}(hdisplayh]hdisplay}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjSubj)}(henum pipe pipeh](j)}(hjh]henum}(hj6ThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2Tubji)}(h h]h }(hjCThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2Tubh)}(hhh]j;)}(hpipeh]hpipe}(hjTThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQTubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjVTmodnameN classnameNjXj[)}j^]jS%c.intel_cpu_fifo_underrun_irq_handlerasbuh1hhj2Tubji)}(h h]h }(hjrThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2Tubj;)}(hpipeh]hpipe}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2Tubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjSubeh}(h]h ]h"]h$]h&]jjuh1jhjShhhjShMzubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjShhhjShMzubah}(h]jzSah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjShMzhj|Shhubj1)}(hhh]h)}(h"handle CPU fifo underrun interrupth]h"handle CPU fifo underrun interrupt}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMrhjThhubah}(h]h ]h"]h$]h&]uh1j0hj|ShhhjShMzubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjTjSjTjTjUjVuh1j&hhhjMhNhNubjX)}(hXF**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pipe`` (CPU) pipe to set state for **Description** This handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h](h)}(h**Parameters**h]jb)}(hjTh]h Parameters}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jahjTubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMvhjTubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjTh]hstruct intel_display *display}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMshjTubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMshjUubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j|hjUhMshjTubj})}(h/``enum pipe pipe`` (CPU) pipe to set state for h](j)}(h``enum pipe pipe``h]j)}(hj$Uh]henum pipe pipe}(hj&UhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"Uubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMthjUubj)}(hhh]h)}(h(CPU) pipe to set state forh]h(CPU) pipe to set state for}(hj=UhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9UhMthj:Uubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j|hj9UhMthjTubeh}(h]h ]h"]h$]h&]uh1jwhjTubh)}(h**Description**h]jb)}(hj_Uh]h Description}(hjaUhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj]Uubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMvhjTubh)}(hThis handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h]hThis handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.}(hjuUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMvhjTubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"0intel_pch_fifo_underrun_irq_handler (C function)%c.intel_pch_fifo_underrun_irq_handlerhNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hbvoid intel_pch_fifo_underrun_irq_handler (struct intel_display *display, enum pipe pch_transcoder)h]j2)}(havoid intel_pch_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pch_transcoder)h](j)}(hvoidh]hvoid}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUhhhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMubji)}(h h]h }(hjUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjUhhhjUhMubjz)}(h#intel_pch_fifo_underrun_irq_handlerh]j;)}(h#intel_pch_fifo_underrun_irq_handlerh]h#intel_pch_fifo_underrun_irq_handler}(hjUhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjUubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjUhhhjUhMubj)}(h9(struct intel_display *display, enum pipe pch_transcoder)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubji)}(h h]h }(hjUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjUubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjUhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjUubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjVmodnameN classnameNjXj[)}j^]ja)}jTjUsb%c.intel_pch_fifo_underrun_irq_handlerasbuh1hhjUubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjUubj)}(hjh]h*}(hj-VhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubj;)}(hdisplayh]hdisplay}(hj:VhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjUubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjUubj)}(henum pipe pch_transcoderh](j)}(hjh]henum}(hjSVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOVubji)}(h h]h }(hj`VhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjOVubh)}(hhh]j;)}(hpipeh]hpipe}(hjqVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnVubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjsVmodnameN classnameNjXj[)}j^]jV%c.intel_pch_fifo_underrun_irq_handlerasbuh1hhjOVubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjOVubj;)}(hpch_transcoderh]hpch_transcoder}(hjVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjOVubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjUubeh}(h]h ]h"]h$]h&]jjuh1jhjUhhhjUhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjUhhhjUhMubah}(h]jUah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjUhMhjUhhubj1)}(hhh]h)}(h"handle PCH fifo underrun interrupth]h"handle PCH fifo underrun interrupt}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjVhhubah}(h]h ]h"]h$]h&]uh1j0hjUhhhjUhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjVjSjVjTjUjVuh1j&hhhjMhNhNubjX)}(hXg**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) **Description** This handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h](h)}(h**Parameters**h]jb)}(hjVh]h Parameters}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjVubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjVubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjWh]hstruct intel_display *display}(hj WhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjWubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj!WhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhMhjWubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1j|hjWhMhjVubj})}(hP``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) h](j)}(h``enum pipe pch_transcoder``h]j)}(hjAWh]henum pipe pch_transcoder}(hjCWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?Wubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj;Wubj)}(hhh]h)}(h2the PCH transcoder (same as pipe on IVB and older)h]h2the PCH transcoder (same as pipe on IVB and older)}(hjZWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVWhMhjWWubah}(h]h ]h"]h$]h&]uh1jhj;Wubeh}(h]h ]h"]h$]h&]uh1j|hjVWhMhjVubeh}(h]h ]h"]h$]h&]uh1jwhjVubh)}(h**Description**h]jb)}(hj|Wh]h Description}(hj~WhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjzWubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjVubh)}(hThis handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h]hThis handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjVubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+intel_check_cpu_fifo_underruns (C function) c.intel_check_cpu_fifo_underrunshNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hCvoid intel_check_cpu_fifo_underruns (struct intel_display *display)h]j2)}(hBvoid intel_check_cpu_fifo_underruns(struct intel_display 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}(hjQYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>YhhhjPYhMubjz)}(hintel_check_pch_fifo_underrunsh]j;)}(hintel_check_pch_fifo_underrunsh]hintel_check_pch_fifo_underruns}(hjcYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_Yubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj>YhhhjPYhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{Yubji)}(h h]h }(hjYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{Yubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjYubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjYmodnameN classnameNjXj[)}j^]ja)}jTjeYsb c.intel_check_pch_fifo_underrunsasbuh1hhj{Yubji)}(h h]h }(hjYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{Yubj)}(hjh]h*}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{Yubj;)}(hdisplayh]hdisplay}(hjYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{Yubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjwYubah}(h]h ]h"]h$]h&]jjuh1jhj>YhhhjPYhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj:YhhhjPYhMubah}(h]j5Yah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjPYhMhj7Yhhubj1)}(hhh]h)}(h(check for PCH fifo underruns immediatelyh]h(check for PCH fifo underruns immediately}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjYhhubah}(h]h ]h"]h$]h&]uh1j0hj7YhhhjPYhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjZjSjZjTjUjVuh1j&hhhjMhNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device instance **Description** Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won't necessarily raise an interrupt.h](h)}(h**Parameters**h]jb)}(hj$Zh]h Parameters}(hj&ZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"Zubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjZubjx)}(hhh]j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjCZh]hstruct intel_display *display}(hjEZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAZubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj=Zubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj\ZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXZhMhjYZubah}(h]h ]h"]h$]h&]uh1jhj=Zubeh}(h]h ]h"]h$]h&]uh1j|hjXZhMhj:Zubah}(h]h ]h"]h$]h&]uh1jwhjZubh)}(h**Description**h]jb)}(hj~Zh]h Description}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj|Zubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjZubh)}(hCheck for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won't necessarily raise an interrupt.h]hCheck for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won’t necessarily raise an interrupt.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjZubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubeh}(h]display-fifo-underrun-reportingah ]h"]display fifo underrun reportingah$]h&]uh1hhj;hhhhhK_ubh)}(hhh](h)}(hPlane Configurationh]hPlane Configuration}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhKhubh)}(hX5This section covers plane configuration and composition with the primary plane, sprites, cursors and overlays. This includes the infrastructure to do atomic vsync'ed updates of all this state and also tightly coupled topics like watermark setup and computation, framebuffer compression and panel self refresh.h]hX7This section covers plane configuration and composition with the primary plane, sprites, cursors and overlays. This includes the infrastructure to do atomic vsync’ed updates of all this state and also tightly coupled topics like watermark setup and computation, framebuffer compression and panel self refresh.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjZhhubeh}(h]plane-configurationah ]h"]plane configurationah$]h&]uh1hhj;hhhhhKhubh)}(hhh](h)}(hAtomic Plane Helpersh]hAtomic Plane Helpers}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhKqubh)}(hX0The functions here are used by the atomic plane helper functions to implement legacy plane updates (i.e., drm_plane->update_plane() and drm_plane->disable_plane()). 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This allows plane updates to use the atomic state infrastructure and perform plane updates as separate prepare/check/commit/cleanup steps.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:115: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhjZhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_plane_destroy (C function)c.intel_plane_destroyhNtauh1jhjZhhhNhNubj')}(hhh](j,)}(h2void intel_plane_destroy (struct drm_plane *plane)h]j2)}(h1void intel_plane_destroy(struct drm_plane *plane)h](j)}(hvoidh]hvoid}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[hhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKjubji)}(h h]h }(hj![hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj[hhhj [hKjubjz)}(hintel_plane_destroyh]j;)}(hintel_plane_destroyh]hintel_plane_destroy}(hj3[hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/[ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj[hhhj [hKjubj)}(h(struct drm_plane *plane)h]j)}(hstruct drm_plane *planeh](j)}(hjh]hstruct}(hjO[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjK[ubji)}(h h]h }(hj\[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjK[ubh)}(hhh]j;)}(h drm_planeh]h drm_plane}(hjm[hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjj[ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjo[modnameN classnameNjXj[)}j^]ja)}jTj5[sbc.intel_plane_destroyasbuh1hhjK[ubji)}(h h]h }(hj[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjK[ubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjK[ubj;)}(hplaneh]hplane}(hj[hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjK[ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjG[ubah}(h]h ]h"]h$]h&]jjuh1jhj[hhhj [hKjubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj [hhhj [hKjubah}(h]j[ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj [hKjhj[hhubj1)}(hhh]h)}(hdestroy a planeh]hdestroy a plane}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKdhj[hhubah}(h]h ]h"]h$]h&]uh1j0hj[hhhj [hKjubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj[jSj[jTjUjVuh1j&hhhjZhNhNubjX)}(h**Parameters** ``struct drm_plane *plane`` plane to destroy **Description** Common destruction function for all types of planes (primary, cursor, sprite).h](h)}(h**Parameters**h]jb)}(hj[h]h Parameters}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj[ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhhj[ubjx)}(hhh]j})}(h-``struct drm_plane *plane`` plane to destroy h](j)}(h``struct drm_plane *plane``h]j)}(hj\h]hstruct drm_plane *plane}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKehj \ubj)}(hhh]h)}(hplane to destroyh]hplane to destroy}(hj,\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(\hKehj)\ubah}(h]h ]h"]h$]h&]uh1jhj \ubeh}(h]h ]h"]h$]h&]uh1j|hj(\hKehj \ubah}(h]h ]h"]h$]h&]uh1jwhj[ubh)}(h**Description**h]jb)}(hjN\h]h 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./drivers/gpu/drm/i915/display/intel_atomic_plane.chKyubji)}(h h]h }(hj\hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\hhhj\hKyubh)}(hhh]j;)}(hdrm_plane_stateh]hdrm_plane_state}(hj\hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj\modnameN classnameNjXj[)}j^]ja)}jTintel_plane_duplicate_statesbc.intel_plane_duplicate_stateasbuh1hhj\hhhj\hKyubji)}(h h]h }(hj\hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\hhhj\hKyubj)}(hjh]h*}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\hhhj\hKyubjz)}(hintel_plane_duplicate_stateh]j;)}(hj\h]hintel_plane_duplicate_state}(hj\hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj\hhhj\hKyubj)}(h(struct drm_plane *plane)h]j)}(hstruct drm_plane *planeh](j)}(hjh]hstruct}(hj ]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ]ubji)}(h h]h }(hj]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ]ubh)}(hhh]j;)}(h drm_planeh]h drm_plane}(hj+]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(]ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj-]modnameN classnameNjXj[)}j^]j\c.intel_plane_duplicate_stateasbuh1hhj ]ubji)}(h h]h }(hjI]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ]ubj)}(hjh]h*}(hjW]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ]ubj;)}(hplaneh]hplane}(hjd]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ]ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj]ubah}(h]h ]h"]h$]h&]jjuh1jhj\hhhj\hKyubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj\hhhj\hKyubah}(h]j\ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj\hKyhj\hhubj1)}(hhh]h)}(hduplicate plane stateh]hduplicate plane state}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKqhj]hhubah}(h]h ]h"]h$]h&]uh1j0hj\hhhj\hKyubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj]jSj]jTjUjVuh1j&hhhjZhNhNubjX)}(h**Parameters** ``struct drm_plane *plane`` drm plane **Description** Allocates and returns a copy of the plane state (both common and Intel-specific) for the specified plane. **Return** The newly allocated plane state, or NULL on failure.h](h)}(h**Parameters**h]jb)}(hj]h]h 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]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj_hhubah}(h]h ]h"]h$]h&]uh1j0hjk^hhhj^hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj_jSj_jTjUjVuh1j&hhhjZhNhNubjX)}(h**Parameters** ``struct drm_plane *plane`` drm plane ``struct drm_plane_state *state`` state object to destroy **Description** Destroys the plane state (both common and Intel-specific) for the specified plane.h](h)}(h**Parameters**h]jb)}(hj_h]h Parameters}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj_ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj_ubjx)}(hhh](j})}(h&``struct drm_plane *plane`` drm plane h](j)}(h``struct drm_plane *plane``h]j)}(hj_h]hstruct drm_plane *plane}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj_ubj)}(hhh]h)}(h drm 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drm_plane *_plane, struct drm_plane_state *_new_plane_state)h](j)}(hstruct drm_plane *_planeh](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubji)}(h h]h }(hj`hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubh)}(hhh]j;)}(h drm_planeh]h drm_plane}(hj`hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj`modnameN classnameNjXj[)}j^]ja)}jTj`sbc.intel_prepare_plane_fbasbuh1hhj`ubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubj)}(hjh]h*}(hj)ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubj;)}(h_planeh]h_plane}(hj6ahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj`ubj)}(h(struct drm_plane_state *_new_plane_stateh](j)}(hjh]hstruct}(hjOahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKaubji)}(h h]h }(hj\ahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKaubh)}(hhh]j;)}(hdrm_plane_stateh]hdrm_plane_state}(hjmahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjaubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjoamodnameN classnameNjXj[)}j^]jac.intel_prepare_plane_fbasbuh1hhjKaubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKaubj)}(hjh]h*}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKaubj;)}(h_new_plane_stateh]h_new_plane_state}(hjahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKaubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj`ubeh}(h]h ]h"]h$]h&]jjuh1jhj`hhhj`hM~ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj`hhhj`hM~ubah}(h]j`ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj`hM~hj`hhubj1)}(hhh]h)}(hPrepare fb for usage on planeh]hPrepare fb for usage on plane}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMshjahhubah}(h]h ]h"]h$]h&]uh1j0hj`hhhj`hM~ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjajSjajTjUjVuh1j&hhhjZhNhNubjX)}(hX**Parameters** ``struct drm_plane *_plane`` drm plane to prepare for ``struct drm_plane_state *_new_plane_state`` the plane state being prepared **Description** Prepares a framebuffer for usage on a display plane. Generally this involves pinning the underlying object and updating the frontbuffer tracking bits. Some older platforms need special physical address handling for cursor planes. Returns 0 on success, negative error code on failure.h](h)}(h**Parameters**h]jb)}(hjah]h Parameters}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jahjaubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMwhjaubjx)}(hhh](j})}(h6``struct drm_plane *_plane`` drm plane to prepare for h](j)}(h``struct drm_plane *_plane``h]j)}(hjbh]hstruct drm_plane *_plane}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMthj bubj)}(hhh]h)}(hdrm plane to prepare forh]hdrm plane to prepare for}(hj*bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&bhMthj'bubah}(h]h ]h"]h$]h&]uh1jhj bubeh}(h]h ]h"]h$]h&]uh1j|hj&bhMthjbubj})}(hL``struct drm_plane_state *_new_plane_state`` the plane state being prepared h](j)}(h,``struct drm_plane_state *_new_plane_state``h]j)}(hjJbh]h(struct drm_plane_state *_new_plane_state}(hjLbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHbubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMuhjDbubj)}(hhh]h)}(hthe plane state being preparedh]hthe plane state being prepared}(hjcbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_bhMuhj`bubah}(h]h ]h"]h$]h&]uh1jhjDbubeh}(h]h ]h"]h$]h&]uh1j|hj_bhMuhjbubeh}(h]h ]h"]h$]h&]uh1jwhjaubh)}(h**Description**h]jb)}(hjbh]h Description}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjbubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMwhjaubh)}(hPrepares a framebuffer for usage on a display plane. Generally this involves pinning the underlying object and updating the frontbuffer tracking bits. Some older platforms need special physical address handling for cursor planes.h]hPrepares a framebuffer for usage on a display plane. Generally this involves pinning the underlying object and updating the frontbuffer tracking bits. Some older platforms need special physical address handling for cursor planes.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMwhjaubh)}(h5Returns 0 on success, negative error code on failure.h]h5Returns 0 on success, negative error code on failure.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chM|hjaubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjZhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_cleanup_plane_fb (C function)c.intel_cleanup_plane_fbhNtauh1jhjZhhhNhNubj')}(hhh](j,)}(h_void intel_cleanup_plane_fb (struct drm_plane *plane, struct drm_plane_state *_old_plane_state)h]j2)}(h^void intel_cleanup_plane_fb(struct drm_plane *plane, struct drm_plane_state *_old_plane_state)h](j)}(hvoidh]hvoid}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMubji)}(h h]h }(hjbhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbhhhjbhMubjz)}(hintel_cleanup_plane_fbh]j;)}(hintel_cleanup_plane_fbh]hintel_cleanup_plane_fb}(hjbhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjbubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjbhhhjbhMubj)}(hC(struct drm_plane *plane, struct drm_plane_state *_old_plane_state)h](j)}(hstruct drm_plane *planeh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubji)}(h h]h }(hj#chhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubh)}(hhh]j;)}(h drm_planeh]h drm_plane}(hj4chhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj1cubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj6cmodnameN classnameNjXj[)}j^]ja)}jTjbsbc.intel_cleanup_plane_fbasbuh1hhjcubji)}(h h]h }(hjTchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubj)}(hjh]h*}(hjbchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj;)}(hplaneh]hplane}(hjochhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjcubj)}(h(struct drm_plane_state *_old_plane_stateh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubh)}(hhh]j;)}(hdrm_plane_stateh]hdrm_plane_state}(hjchhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjcmodnameN classnameNjXj[)}j^]jPcc.intel_cleanup_plane_fbasbuh1hhjcubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubj)}(hjh]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj;)}(h_old_plane_stateh]h_old_plane_state}(hjchhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjcubeh}(h]h ]h"]h$]h&]jjuh1jhjbhhhjbhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjbhhhjbhMubah}(h]jbah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjbhMhjbhhubj1)}(hhh]h)}(hCleans up an fb after plane useh]hCleans up an fb after plane use}(hj dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjdhhubah}(h]h ]h"]h$]h&]uh1j0hjbhhhjbhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj!djSj!djTjUjVuh1j&hhhjZhNhNubjX)}(h**Parameters** ``struct drm_plane *plane`` drm plane to clean up for ``struct drm_plane_state *_old_plane_state`` the state from the previous modeset **Description** Cleans up a framebuffer that has just been removed from a plane.h](h)}(h**Parameters**h]jb)}(hj+dh]h Parameters}(hj-dhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj)dubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj%dubjx)}(hhh](j})}(h6``struct drm_plane *plane`` drm plane to clean up for h](j)}(h``struct drm_plane *plane``h]j)}(hjJdh]hstruct drm_plane *plane}(hjLdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHdubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjDdubj)}(hhh]h)}(hdrm plane to clean up forh]hdrm plane to clean up for}(hjcdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_dhMhj`dubah}(h]h ]h"]h$]h&]uh1jhjDdubeh}(h]h ]h"]h$]h&]uh1j|hj_dhMhjAdubj})}(hQ``struct drm_plane_state *_old_plane_state`` the state from the previous modeset h](j)}(h,``struct drm_plane_state *_old_plane_state``h]j)}(hjdh]h(struct drm_plane_state *_old_plane_state}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj}dubj)}(hhh]h)}(h#the state from the previous modeseth]h#the state from the previous modeset}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjdubah}(h]h ]h"]h$]h&]uh1jhj}dubeh}(h]h ]h"]h$]h&]uh1j|hjdhMhjAdubeh}(h]h ]h"]h$]h&]uh1jwhj%dubh)}(h**Description**h]jb)}(hjdh]h Description}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjdubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj%dubh)}(h@Cleans up a framebuffer that has just been removed from a plane.h]h@Cleans up a framebuffer that has just been removed from a plane.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj%dubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjZhhhNhNubeh}(h]atomic-plane-helpersah ]h"]atomic plane helpersah$]h&]uh1hhj;hhhhhKqubh)}(hhh](h)}(hAsynchronous Page Fliph]hAsynchronous Page Flip}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhhhhhKzubh)}(hAsynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC flag. Currently async flip is only supported via the drmModePageFlip IOCTL. Correspondingly, support is currently added for primary plane only.h]hAsynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC flag. Currently async flip is only supported via the drmModePageFlip IOCTL. Correspondingly, support is currently added for primary plane only.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:124: ./drivers/gpu/drm/i915/display/intel_display.chMhjdhhubh)}(hAsync flip can only change the plane surface address, so anything else changing is rejected from the intel_async_flip_check_hw() function. Once this check is cleared, flip done interrupt is enabled using the intel_crtc_enable_flip_done() function.h]hAsync flip can only change the plane surface address, so anything else changing is rejected from the intel_async_flip_check_hw() function. Once this check is cleared, flip done interrupt is enabled using the intel_crtc_enable_flip_done() function.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:124: ./drivers/gpu/drm/i915/display/intel_display.chMhjdhhubh)}(hXLAs soon as the surface address register is written, flip done interrupt is generated and the requested events are sent to the userspace in the interrupt handler itself. The timestamp and sequence sent during the flip done event correspond to the last vblank and have no relation to the actual time when the flip done event was sent.h]hXLAs soon as the surface address register is written, flip done interrupt is generated and the requested events are sent to the userspace in the interrupt handler itself. The timestamp and sequence sent during the flip done event correspond to the last vblank and have no relation to the actual time when the flip done event was sent.}(hj!ehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:124: ./drivers/gpu/drm/i915/display/intel_display.chMhjdhhubeh}(h]asynchronous-page-flipah ]h"]asynchronous page flipah$]h&]uh1hhj;hhhhhKzubh)}(hhh](h)}(hOutput Probingh]hOutput Probing}(hj;ehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8ehhhhhKubh)}(hThis section covers output probing and related infrastructure like the hotplug interrupt storm detection and mitigation code. Note that the i915 driver still uses most of the common DRM helper code for output probing, so those sections fully apply.h]hThis section covers output probing and related infrastructure like the hotplug interrupt storm detection and mitigation code. Note that the i915 driver still uses most of the common DRM helper code for output probing, so those sections fully apply.}(hjIehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj8ehhubeh}(h]output-probingah ]h"]output probingah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hHotplugh]hHotplug}(hjbehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_ehhhhhKubh)}(hSimply put, hotplug occurs when a display is connected to or disconnected from the system. However, there may be adapters and docking stations and Display Port short pulses and MST devices involved, complicating matters.h]hSimply put, hotplug occurs when a display is connected to or disconnected from the system. However, there may be adapters and docking stations and Display Port short pulses and MST devices involved, complicating matters.}(hjpehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK'hj_ehhubh)}(hCHotplug in i915 is handled in many different levels of abstraction.h]hCHotplug in i915 is handled in many different levels of abstraction.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK+hj_ehhubh)}(hXThe platform dependent interrupt handling code in i915_irq.c enables, disables, and does preliminary handling of the interrupts. The interrupt handlers gather the hotplug detect (HPD) information from relevant registers into a platform independent mask of hotplug pins that have fired.h]hXThe platform dependent interrupt handling code in i915_irq.c enables, disables, and does preliminary handling of the interrupts. The interrupt handlers gather the hotplug detect (HPD) information from relevant registers into a platform independent mask of hotplug pins that have fired.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK-hj_ehhubh)}(hThe platform independent interrupt handler intel_hpd_irq_handler() in intel_hotplug.c does hotplug irq storm detection and mitigation, and passes further processing to appropriate bottom halves (Display Port specific and regular hotplug).h]hThe platform independent interrupt handler intel_hpd_irq_handler() in intel_hotplug.c does hotplug irq storm detection and mitigation, and passes further processing to appropriate bottom halves (Display Port specific and regular hotplug).}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK2hj_ehhubh)}(hThe Display Port work function i915_digport_work_func() calls into intel_dp_hpd_pulse() via hooks, which handles DP short pulses and DP MST long pulses, with failures and non-MST long pulses triggering regular hotplug processing on the connector.h]hThe Display Port work function i915_digport_work_func() calls into intel_dp_hpd_pulse() via hooks, which handles DP short pulses and DP MST long pulses, with failures and non-MST long pulses triggering regular hotplug processing on the connector.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK7hj_ehhubh)}(hThe regular hotplug work function i915_hotplug_work_func() calls connector detect hooks, and, if connector status changes, triggers sending of hotplug uevent to userspace via drm_kms_helper_hotplug_event().h]hThe regular hotplug work function i915_hotplug_work_func() calls connector detect hooks, and, if connector status changes, triggers sending of hotplug uevent to userspace via drm_kms_helper_hotplug_event().}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chKdisplay.hotplug.hpd_storm_threshold** which defaults to **HPD_STORM_DEFAULT_THRESHOLD**. Long IRQs count as +10 to this threshold, and short IRQs count as +1. If this threshold is exceeded, it's considered an IRQ storm and the IRQ state is set to **HPD_MARK_DISABLED**. By default, most systems will only count long IRQs towards :c:type:`dev_priv->display `.hotplug.hpd_storm_threshold. However, some older systems also suffer from short IRQ storms and must also track these. Because short IRQ storms are naturally caused by sideband interactions with DP MST devices, short IRQ detection is only enabled for systems without DP MST support. Systems which are new enough to support DP MST are far less likely to suffer from IRQ storms at all, so this is fine. The HPD threshold can be controlled through i915_hpd_storm_ctl in debugfs, and should only be adjusted for automated hotplug testing. Return true if an IRQ storm was detected on **pin**.h](h)}(h**Parameters**h]jb)}(hjKih]h Parameters}(hjMihhhNhNubah}(h]h ]h"]h$]h&]uh1jahjIiubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK|hjEiubjx)}(hhh](j})}(hB``struct drm_i915_private *dev_priv`` private driver data pointer h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hjjih]h!struct drm_i915_private *dev_priv}(hjlihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhiubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKyhjdiubj)}(hhh]h)}(hprivate driver data pointerh]hprivate driver data pointer}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKyhjiubah}(h]h ]h"]h$]h&]uh1jhjdiubeh}(h]h ]h"]h$]h&]uh1j|hjihKyhjaiubj})}(h0``enum hpd_pin pin`` the pin to gather stats on h](j)}(h``enum hpd_pin pin``h]j)}(hjih]henum hpd_pin pin}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKzhjiubj)}(hhh]h)}(hthe pin to gather stats onh]hthe pin to gather stats on}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKzhjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1j|hjihKzhjaiubj})}(h8``bool long_hpd`` whether the HPD IRQ was long or short h](j)}(h``bool long_hpd``h]j)}(hjih]h bool long_hpd}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK{hjiubj)}(hhh]h)}(h%whether the HPD IRQ was long or shorth]h%whether the HPD IRQ was long or short}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihK{hjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1j|hjihK{hjaiubeh}(h]h ]h"]h$]h&]uh1jwhjEiubh)}(h**Description**h]jb)}(hjjh]h Description}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK}hjEiubh)}(hGather stats about HPD IRQs from the specified **pin**, and detect IRQ storms. Only the pin specific stats and state are changed, the caller is responsible for further action.h](h/Gather stats about HPD IRQs from the specified }(hj-jhhhNhNubjb)}(h**pin**h]hpin}(hj5jhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-jubhy, and detect IRQ storms. Only the pin specific stats and state are changed, the caller is responsible for further action.}(hj-jhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK}hjEiubh)}(hXmThe number of IRQs that are allowed within **HPD_STORM_DETECT_PERIOD** is stored in **dev_priv->display.hotplug.hpd_storm_threshold** which defaults to **HPD_STORM_DEFAULT_THRESHOLD**. Long IRQs count as +10 to this threshold, and short IRQs count as +1. If this threshold is exceeded, it's considered an IRQ storm and the IRQ state is set to **HPD_MARK_DISABLED**.h](h+The number of IRQs that are allowed within }(hjNjhhhNhNubjb)}(h**HPD_STORM_DETECT_PERIOD**h]hHPD_STORM_DETECT_PERIOD}(hjVjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNjubh is stored in }(hjNjhhhNhNubjb)}(h1**dev_priv->display.hotplug.hpd_storm_threshold**h]h-dev_priv->display.hotplug.hpd_storm_threshold}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNjubh which defaults to }(hjNjhhhNhNubjb)}(h**HPD_STORM_DEFAULT_THRESHOLD**h]hHPD_STORM_DEFAULT_THRESHOLD}(hjzjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNjubh. Long IRQs count as +10 to this threshold, and short IRQs count as +1. If this threshold is exceeded, it’s considered an IRQ storm and the IRQ state is set to }(hjNjhhhNhNubjb)}(h**HPD_MARK_DISABLED**h]hHPD_MARK_DISABLED}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNjubh.}(hjNjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKhjEiubh)}(hXBy default, most systems will only count long IRQs towards :c:type:`dev_priv->display `.hotplug.hpd_storm_threshold. However, some older systems also suffer from short IRQ storms and must also track these. Because short IRQ storms are naturally caused by sideband interactions with DP MST devices, short IRQ detection is only enabled for systems without DP MST support. Systems which are new enough to support DP MST are far less likely to suffer from IRQ storms at all, so this is fine.h](h;By default, most systems will only count long IRQs towards }(hjjhhhNhNubh)}(h&:c:type:`dev_priv->display `h]j)}(hjjh]hdev_priv->display}(hjjhhhNhNubah}(h]h ](xrefjRc-typeeh"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXj[)}j^]sb reftargetdev_privuh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKhjjubhX.hotplug.hpd_storm_threshold. However, some older systems also suffer from short IRQ storms and must also track these. Because short IRQ storms are naturally caused by sideband interactions with DP MST devices, short IRQ detection is only enabled for systems without DP MST support. Systems which are new enough to support DP MST are far less likely to suffer from IRQ storms at all, so this is fine.}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjjhKhjEiubh)}(hThe HPD threshold can be controlled through i915_hpd_storm_ctl in debugfs, and should only be adjusted for automated hotplug testing.h]hThe HPD threshold can be controlled through i915_hpd_storm_ctl in debugfs, and should only be adjusted for automated hotplug testing.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKhjEiubh)}(h4Return true if an IRQ storm was detected on **pin**.h](h,Return true if an IRQ storm was detected on }(hjjhhhNhNubjb)}(h**pin**h]hpin}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjjubh.}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKhjEiubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_hpd_trigger_irq (C function)c.intel_hpd_trigger_irqhNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(h@void intel_hpd_trigger_irq (struct intel_digital_port *dig_port)h]j2)}(h?void intel_hpd_trigger_irq(struct intel_digital_port *dig_port)h](j)}(hvoidh]hvoid}(hj,khhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(khhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMubji)}(h h]h }(hj;khhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj(khhhj:khMubjz)}(hintel_hpd_trigger_irqh]j;)}(hintel_hpd_trigger_irqh]hintel_hpd_trigger_irq}(hjMkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIkubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj(khhhj:khMubj)}(h%(struct intel_digital_port *dig_port)h]j)}(h#struct intel_digital_port *dig_porth](j)}(hjh]hstruct}(hjikhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjekubji)}(h h]h }(hjvkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjekubh)}(hhh]j;)}(hintel_digital_porth]hintel_digital_port}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjkubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjkmodnameN classnameNjXj[)}j^]ja)}jTjOksbc.intel_hpd_trigger_irqasbuh1hhjekubji)}(h h]h }(hjkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjekubj)}(hjh]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjekubj;)}(hdig_porth]hdig_port}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjekubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjakubah}(h]h ]h"]h$]h&]jjuh1jhj(khhhj:khMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj$khhhj:khMubah}(h]jkah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj:khMhj!khhubj1)}(hhh]h)}(h#trigger an hpd irq event for a porth]h#trigger an hpd irq event for a port}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjkhhubah}(h]h ]h"]h$]h&]uh1j0hj!khhhj:khMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjljSjljTjUjVuh1j&hhhj_ehNhNubjX)}(h**Parameters** ``struct intel_digital_port *dig_port`` digital port **Description** Trigger an HPD interrupt event for the given port, emulating a short pulse generated by the sink, and schedule the dig port work to handle it.h](h)}(h**Parameters**h]jb)}(hjlh]h Parameters}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj lubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjlubjx)}(hhh]j})}(h5``struct intel_digital_port *dig_port`` digital port h](j)}(h'``struct intel_digital_port *dig_port``h]j)}(hj-lh]h#struct intel_digital_port *dig_port}(hj/lhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+lubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhj'lubj)}(hhh]h)}(h digital porth]h digital port}(hjFlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBlhMhjClubah}(h]h ]h"]h$]h&]uh1jhj'lubeh}(h]h ]h"]h$]h&]uh1j|hjBlhMhj$lubah}(h]h ]h"]h$]h&]uh1jwhjlubh)}(h**Description**h]jb)}(hjhlh]h Description}(hjjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjflubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjlubh)}(hTrigger an HPD interrupt event for the given port, emulating a short pulse generated by the sink, and schedule the dig port work to handle it.h]hTrigger an HPD interrupt event for the given port, emulating a short pulse generated by the sink, and schedule the dig port work to handle it.}(hj~lhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjlubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_hpd_irq_handler (C function)c.intel_hpd_irq_handlerhNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(h[void intel_hpd_irq_handler (struct drm_i915_private *dev_priv, u32 pin_mask, u32 long_mask)h]j2)}(hZvoid intel_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 pin_mask, u32 long_mask)h](j)}(hvoidh]hvoid}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMubji)}(h h]h }(hjlhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjlhhhjlhMubjz)}(hintel_hpd_irq_handlerh]j;)}(hintel_hpd_irq_handlerh]hintel_hpd_irq_handler}(hjlhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjlubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjlhhhjlhMubj)}(h@(struct drm_i915_private *dev_priv, u32 pin_mask, u32 long_mask)h](j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubji)}(h h]h }(hjlhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjlubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj mmodnameN classnameNjXj[)}j^]ja)}jTjlsbc.intel_hpd_irq_handlerasbuh1hhjlubji)}(h h]h }(hj(mhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjlubj)}(hjh]h*}(hj6mhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubj;)}(hdev_privh]hdev_priv}(hjCmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjlubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjlubj)}(h u32 pin_maskh](h)}(hhh]j;)}(hu32h]hu32}(hj_mhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\mubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjammodnameN classnameNjXj[)}j^]j$mc.intel_hpd_irq_handlerasbuh1hhjXmubji)}(h h]h }(hj}mhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjXmubj;)}(hpin_maskh]hpin_mask}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjXmubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjlubj)}(h u32 long_maskh](h)}(hhh]j;)}(hu32h]hu32}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmmodnameN classnameNjXj[)}j^]j$mc.intel_hpd_irq_handlerasbuh1hhjmubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjmubj;)}(h long_maskh]h long_mask}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjlubeh}(h]h ]h"]h$]h&]jjuh1jhjlhhhjlhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjlhhhjlhMubah}(h]jlah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjlhMhjlhhubj1)}(hhh]h)}(hmain hotplug irq handlerh]hmain hotplug irq handler}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM hjmhhubah}(h]h ]h"]h$]h&]uh1j0hjlhhhjlhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjnjSjnjTjUjVuh1j&hhhj_ehNhNubjX)}(hX**Parameters** ``struct drm_i915_private *dev_priv`` drm_i915_private ``u32 pin_mask`` a mask of hpd pins that have triggered the irq ``u32 long_mask`` a mask of hpd pins that may be long hpd pulses **Description** This is the main hotplug irq handler for all platforms. The platform specific irq handlers call the platform specific hotplug irq handlers, which read and decode the appropriate registers into bitmasks about hpd pins that have triggered (**pin_mask**), and which of those pins may be long pulses (**long_mask**). The **long_mask** is ignored if the port corresponding to the pin is not a digital port. Here, we do hotplug irq storm detection and mitigation, and pass further processing to appropriate bottom halves.h](h)}(h**Parameters**h]jb)}(hjnh]h Parameters}(hj!nhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjnubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjnubjx)}(hhh](j})}(h7``struct drm_i915_private *dev_priv`` drm_i915_private h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hj>nh]h!struct drm_i915_private *dev_priv}(hj@nhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvoid intel_hpd_poll_enable (struct drm_i915_private *dev_priv)h]j2)}(h=void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)h](j)}(hvoidh]hvoid}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM/ubji)}(h h]h }(hj#qhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqhhhj"qhM/ubjz)}(hintel_hpd_poll_enableh]j;)}(hintel_hpd_poll_enableh]hintel_hpd_poll_enable}(hj5qhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj1qubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjqhhhj"qhM/ubj)}(h#(struct drm_i915_private *dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hjQqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMqubji)}(h h]h }(hj^qhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjMqubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjoqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjlqubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjqqmodnameN classnameNjXj[)}j^]ja)}jTj7qsbc.intel_hpd_poll_enableasbuh1hhjMqubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjMqubj)}(hjh]h*}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMqubj;)}(hdev_privh]hdev_priv}(hjqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjMqubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjIqubah}(h]h ]h"]h$]h&]jjuh1jhjqhhhj"qhM/ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj qhhhj"qhM/ubah}(h]jqah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj"qhM/hj qhhubj1)}(hhh]h)}(h&enable polling for connectors with hpdh]h&enable polling for connectors with hpd}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM hjqhhubah}(h]h ]h"]h$]h&]uh1j0hj qhhhj"qhM/ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjqjSjqjTjUjVuh1j&hhhj_ehNhNubjX)}(hXL**Parameters** ``struct drm_i915_private *dev_priv`` i915 device instance **Description** This function enables polling for all connectors which support HPD. Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. On Valleyview and Cherryview systems, this also happens when we shut off all of the powerwells. Since this function can get called in contexts where we're already holding dev->mode_config.mutex, we do the actual hotplug enabling in a separate worker. Also see: intel_hpd_init() and intel_hpd_poll_disable().h](h)}(h**Parameters**h]jb)}(hjqh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjqubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM$hjqubjx)}(hhh]j})}(h;``struct drm_i915_private *dev_priv`` i915 device instance h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hjrh]h!struct drm_i915_private *dev_priv}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM!hjrubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj.rhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*rhM!hj+rubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1j|hj*rhM!hj rubah}(h]h ]h"]h$]h&]uh1jwhjqubh)}(h**Description**h]jb)}(hjPrh]h Description}(hjRrhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNrubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM#hjqubh)}(hXThis function enables polling for all connectors which support HPD. Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. On Valleyview and Cherryview systems, this also happens when we shut off all of the powerwells.h]hXThis function enables polling for all connectors which support HPD. Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. On Valleyview and Cherryview systems, this also happens when we shut off all of the powerwells.}(hjfrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM#hjqubh)}(hSince this function can get called in contexts where we're already holding dev->mode_config.mutex, we do the actual hotplug enabling in a separate worker.h]hSince this function can get called in contexts where we’re already holding dev->mode_config.mutex, we do the actual hotplug enabling in a separate worker.}(hjurhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM)hjqubh)}(h8Also see: intel_hpd_init() and intel_hpd_poll_disable().h]h8Also see: intel_hpd_init() and intel_hpd_poll_disable().}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM-hjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_hpd_poll_disable (C function)c.intel_hpd_poll_disablehNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(h?void intel_hpd_poll_disable (struct drm_i915_private *dev_priv)h]j2)}(h>void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)h](j)}(hvoidh]hvoid}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMXubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrhhhjrhMXubjz)}(hintel_hpd_poll_disableh]j;)}(hintel_hpd_poll_disableh]hintel_hpd_poll_disable}(hjrhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjrubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjrhhhjrhMXubj)}(h#(struct drm_i915_private *dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjshhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj subah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjsmodnameN classnameNjXj[)}j^]ja)}jTjrsbc.intel_hpd_poll_disableasbuh1hhjrubji)}(h h]h }(hj.shhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrubj)}(hjh]h*}(hjmode_config.mutex, we do the actual hotplug enabling in a separate worker. Also used during driver init to initialize connector->polled appropriately for all connectors. Also see: intel_hpd_init() and intel_hpd_poll_enable().h](h)}(h**Parameters**h]jb)}(hjsh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jahjsubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMJhjsubjx)}(hhh]j})}(h;``struct drm_i915_private *dev_priv`` i915 device instance h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hjsh]h!struct drm_i915_private *dev_priv}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMGhjsubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMGhjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1j|hjshMGhjsubah}(h]h ]h"]h$]h&]uh1jwhjsubh)}(h**Description**h]jb)}(hjsh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jahjsubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMIhjsubh)}(hXThis function disables polling for all connectors which support HPD. Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. On Valleyview and Cherryview systems, this also happens when we shut off all of the powerwells.h]hXThis function disables polling for all connectors which support HPD. Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. On Valleyview and Cherryview systems, this also happens when we shut off all of the powerwells.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMIhjsubh)}(hSince this function can get called in contexts where we're already holding dev->mode_config.mutex, we do the actual hotplug enabling in a separate worker.h]hSince this function can get called in contexts where we’re already holding dev->mode_config.mutex, we do the actual hotplug enabling in a separate worker.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMOhjsubh)}(h^Also used during driver init to initialize connector->polled appropriately for all connectors.h]h^Also used during driver init to initialize connector->polled appropriately for all connectors.}(hj#thhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMShjsubh)}(h7Also see: intel_hpd_init() and intel_hpd_poll_enable().h]h7Also see: intel_hpd_init() and intel_hpd_poll_enable().}(hj2thhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMVhjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubeh}(h]hotplugah ]h"]hotplugah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hHigh Definition Audioh]hHigh Definition Audio}(hjSthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPthhhhhKubh)}(hXAThe graphics and audio drivers together support High Definition Audio over HDMI and Display Port. The audio programming sequences are divided into audio codec and controller enable and disable sequences. The graphics driver handles the audio codec sequences, while the audio driver handles the audio controller sequences.h]hXAThe graphics and audio drivers together support High Definition Audio over HDMI and Display Port. The audio programming sequences are divided into audio codec and controller enable and disable sequences. The graphics driver handles the audio codec sequences, while the audio driver handles the audio controller sequences.}(hjathhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:147: ./drivers/gpu/drm/i915/display/intel_audio.chK+hjPthhubh)}(hXThe disable sequences must be performed before disabling the transcoder or port. The enable sequences may only be performed after enabling the transcoder and port, and after completed link training. Therefore the audio enable/disable sequences are part of the modeset sequence.h]hXThe disable sequences must be performed before disabling the transcoder or port. The enable sequences may only be performed after enabling the transcoder and port, and after completed link training. Therefore the audio enable/disable sequences are part of the modeset sequence.}(hjpthhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:147: ./drivers/gpu/drm/i915/display/intel_audio.chK1hjPthhubh)}(hX~The codec and controller sequences could be done either parallel or serial, but generally the ELDV/PD change in the codec sequence indicates to the audio driver that the controller sequence should start. Indeed, most of the co-operation between the graphics and audio drivers is handled via audio related registers. (The notable exception is the power management, not covered here.)h]hX~The codec and controller sequences could be done either parallel or serial, but generally the ELDV/PD change in the codec sequence indicates to the audio driver that the controller sequence should start. Indeed, most of the co-operation between the graphics and audio drivers is handled via audio related registers. (The notable exception is the power management, not covered here.)}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:147: ./drivers/gpu/drm/i915/display/intel_audio.chK6hjPthhubh)}(hX9The struct :c:type:`i915_audio_component` is used to interact between the graphics and audio drivers. The struct :c:type:`i915_audio_component_ops` **ops** in it is defined in graphics driver and called in audio driver. The struct :c:type:`i915_audio_component_audio_ops` **audio_ops** is called from i915 driver.h](h The struct }(hjthhhNhNubh)}(h:c:type:`i915_audio_component`h]j)}(hjth]hi915_audio_component}(hjthhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_audio_componentuh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:147: ./drivers/gpu/drm/i915/display/intel_audio.chK=hjtubhH is used to interact between the graphics and audio drivers. The struct }(hjthhhNhNubh)}(h":c:type:`i915_audio_component_ops`h]j)}(hjth]hi915_audio_component_ops}(hjthhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_audio_component_opsuh1hhjthK=hjtubh }(hjthhhNhNubjb)}(h**ops**h]hops}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubhL in it is defined in graphics driver and called in audio driver. The struct }(hjthhhNhNubh)}(h(:c:type:`i915_audio_component_audio_ops`h]j)}(hjth]hi915_audio_component_audio_ops}(hjthhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_audio_component_audio_opsuh1hhjthK=hjtubh }hjtsbjb)}(h **audio_ops**h]h audio_ops}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubh is called from i915 driver.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjthK=hjPthhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_audio_codec_enable (C function)c.intel_audio_codec_enablehNtauh1jhjPthhhNhNubj')}(hhh](j,)}(hvoid intel_audio_codec_enable (struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state)h]j2)}(hvoid intel_audio_codec_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state)h](j)}(hvoidh]hvoid}(hjCuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?uhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMubji)}(h h]h }(hjRuhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?uhhhjQuhMubjz)}(hintel_audio_codec_enableh]j;)}(hintel_audio_codec_enableh]hintel_audio_codec_enable}(hjduhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`uubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj?uhhhjQuhMubj)}(hx(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state)h](j)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|uubji)}(h h]h }(hjuhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|uubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hjuhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjuubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjumodnameN classnameNjXj[)}j^]ja)}jTjfusbc.intel_audio_codec_enableasbuh1hhj|uubji)}(h h]h }(hjuhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|uubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|uubj;)}(hencoderh]hencoder}(hjuhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|uubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxuubj)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hconsth]hconst}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubji)}(h h]h }(hjvhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuubj)}(hjh]hstruct}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubji)}(h h]h }(hjvhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hj,vhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)vubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj.vmodnameN classnameNjXj[)}j^]juc.intel_audio_codec_enableasbuh1hhjuubji)}(h h]h }(hjJvhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuubj)}(hjh]h*}(hjXvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubj;)}(h crtc_stateh]h crtc_state}(hjevhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjuubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxuubj)}(h,const struct drm_connector_state *conn_stateh](j)}(hjuh]hconst}(hj~vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzvubji)}(h h]h }(hjvhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzvubj)}(hjh]hstruct}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzvubji)}(h h]h }(hjvhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzvubh)}(hhh]j;)}(hdrm_connector_stateh]hdrm_connector_state}(hjvhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjvubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjvmodnameN classnameNjXj[)}j^]juc.intel_audio_codec_enableasbuh1hhjzvubji)}(h h]h }(hjvhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzvubj)}(hjh]h*}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzvubj;)}(h conn_stateh]h conn_state}(hjvhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzvubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxuubeh}(h]h ]h"]h$]h&]jjuh1jhj?uhhhjQuhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj;uhhhjQuhMubah}(h]j6uah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjQuhMhj8uhhubj1)}(hhh]h)}(h#Enable the audio codec for HD audioh]h#Enable the audio codec for HD audio}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjwhhubah}(h]h ]h"]h$]h&]uh1j0hj8uhhhjQuhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj2wjSj2wjTjUjVuh1j&hhhjPthNhNubjX)}(hX**Parameters** ``struct intel_encoder *encoder`` encoder on which to enable audio ``const struct intel_crtc_state *crtc_state`` pointer to the current crtc state. ``const struct drm_connector_state *conn_state`` pointer to the current connector state. **Description** The enable sequences may only be performed after enabling the transcoder and port, and after completed link training.h](h)}(h**Parameters**h]jb)}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj:wubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj6wubjx)}(hhh](j})}(hC``struct intel_encoder *encoder`` encoder on which to enable audio h](j)}(h!``struct intel_encoder *encoder``h]j)}(hj[wh]hstruct intel_encoder *encoder}(hj]whhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYwubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjUwubj)}(hhh]h)}(h encoder on which to enable audioh]h encoder on which to enable audio}(hjtwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpwhMhjqwubah}(h]h ]h"]h$]h&]uh1jhjUwubeh}(h]h ]h"]h$]h&]uh1j|hjpwhMhjRwubj})}(hQ``const struct intel_crtc_state *crtc_state`` pointer to the current crtc state. h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjwh]h)const struct intel_crtc_state *crtc_state}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjwubj)}(hhh]h)}(h"pointer to the current crtc state.h]h"pointer to the current crtc state.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMhjwubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1j|hjwhMhjRwubj})}(hY``const struct drm_connector_state *conn_state`` pointer to the current connector state. h](j)}(h0``const struct drm_connector_state *conn_state``h]j)}(hjwh]h,const struct drm_connector_state *conn_state}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjwubj)}(hhh]h)}(h'pointer to the current connector state.h]h'pointer to the current connector state.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMhjwubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1j|hjwhMhjRwubeh}(h]h ]h"]h$]h&]uh1jwhj6wubh)}(h**Description**h]jb)}(hjxh]h Description}(hj xhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjxubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj6wubh)}(huThe enable sequences may only be performed after enabling the transcoder and port, and after completed link training.h]huThe enable sequences may only be performed after enabling the transcoder and port, and after completed link training.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj6wubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjPthhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_audio_codec_disable (C function)c.intel_audio_codec_disablehNtauh1jhjPthhhNhNubj')}(hhh](j,)}(hvoid intel_audio_codec_disable (struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state)h]j2)}(hvoid intel_audio_codec_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state)h](j)}(hvoidh]hvoid}(hjMxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIxhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMubji)}(h h]h }(hj\xhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIxhhhj[xhMubjz)}(hintel_audio_codec_disableh]j;)}(hintel_audio_codec_disableh]hintel_audio_codec_disable}(hjnxhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjxubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjIxhhhj[xhMubj)}(h(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state)h](j)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubji)}(h h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hjxhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjxubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjxmodnameN classnameNjXj[)}j^]ja)}jTjpxsbc.intel_audio_codec_disableasbuh1hhjxubji)}(h h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxubj)}(hjh]h*}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj;)}(hencoderh]hencoder}(hjxhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjxubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxubj)}(h-const struct intel_crtc_state *old_crtc_stateh](j)}(hjuh]hconst}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubji)}(h h]h }(hj yhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxubj)}(hjh]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubji)}(h h]h }(hj$yhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hj5yhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2yubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj7ymodnameN classnameNjXj[)}j^]jxc.intel_audio_codec_disableasbuh1hhjxubji)}(h h]h }(hjSyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxubj)}(hjh]h*}(hjayhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj;)}(hold_crtc_stateh]hold_crtc_state}(hjnyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjxubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxubj)}(h0const struct drm_connector_state *old_conn_stateh](j)}(hjuh]hconst}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubji)}(h h]h }(hjyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjyubj)}(hjh]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubji)}(h h]h }(hjyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjyubh)}(hhh]j;)}(hdrm_connector_stateh]hdrm_connector_state}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjyubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjymodnameN classnameNjXj[)}j^]jxc.intel_audio_codec_disableasbuh1hhjyubji)}(h h]h }(hjyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjyubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubj;)}(hold_conn_stateh]hold_conn_state}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjyubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxubeh}(h]h ]h"]h$]h&]jjuh1jhjIxhhhj[xhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjExhhhj[xhMubah}(h]j@xah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj[xhMhjBxhhubj1)}(hhh]h)}(h$Disable the audio codec for HD audioh]h$Disable the audio codec for HD audio}(hj#zhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj zhhubah}(h]h ]h"]h$]h&]uh1j0hjBxhhhj[xhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj;zjSj;zjTjUjVuh1j&hhhjPthNhNubjX)}(hXh**Parameters** ``struct intel_encoder *encoder`` encoder on which to disable audio ``const struct intel_crtc_state *old_crtc_state`` pointer to the old crtc state. ``const struct drm_connector_state *old_conn_state`` pointer to the old connector state. **Description** The disable sequences must be performed before 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register the audio componenth]h+initialize and register the audio component}(hjq}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chM#hjn}hhubah}(h]h ]h"]h$]h&]uh1j0hj|hhhj|hM2ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj}jSj}jTjUjVuh1j&hhhjPthNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device **Description** This will register with the component framework a child component which will bind dynamically to the snd_hda_intel driver's corresponding master component when the latter is registered. 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}(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj=ubh)}(hhh]j;)}(h transcoderh]h transcoder}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjamodnameN classnameNjXj[)}j^]j c.intel_lpe_audio_notifyasbuh1hhj=ubji)}(h h]h }(hj}hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj=ubj;)}(hcpu_transcoderh]hcpu_transcoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj=ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjLjubj)}(henum port porth](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hporth]hport}(hj‰hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjĉmodnameN classnameNjXj[)}j^]j c.intel_lpe_audio_notifyasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hporth]hport}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjLjubj)}(hconst void *eldh](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hvoidh]hvoid}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj0hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(heldh]held}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjLjubj)}(h int ls_clockh](j)}(hinth]hint}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubj;)}(hls_clockh]hls_clock}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjLjubj)}(hbool dp_outputh](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h dp_outputh]h dp_output}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjLjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMHubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMHubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMHhjhhubj1)}(hhh]h)}(h,notify lpe audio event audio driver and i915h]h,notify lpe audio event audio driver and i915}(hjފhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chM=hjۊhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMHubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXC**Parameters** ``struct intel_display *display`` display device ``enum transcoder cpu_transcoder`` CPU transcoder ``enum port port`` port ``const void *eld`` ELD data ``int ls_clock`` Link symbol clock in kHz ``bool dp_output`` Driving a DP output? **Description** Notify lpe audio driver of eld change.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMAhjubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h 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kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]intel-hdmi-lpe-audio-supportah ]h"]intel hdmi lpe audio supportah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(h Panel Self Refresh PSR (PSR/SRD)h]h Panel Self Refresh PSR (PSR/SRD)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXSince Haswell Display controller supports Panel Self-Refresh on display panels witch have a remote frame buffer (RFB) implemented according to PSR spec in eDP1.3. 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PSR feature allows the display to go to lower standby states when system is idle but display is on as it eliminates display refresh request to DDR memory completely as long as the frame buffer for that display is unchanged.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chK3hjhhubh)}(hPPanel Self Refresh must be supported by both Hardware (source) and Panel (sink).h]hPPanel Self Refresh must be supported by both Hardware (source) and Panel (sink).}(hjˌhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chK:hjhhubh)}(hPSR saves power by caching the framebuffer in the panel RFB, which allows us to power down the link and memory controller. For DSI panels the same idea is called "manual mode".h]hPSR saves power by caching the framebuffer in the panel RFB, which allows us to power down the link and memory controller. For DSI panels the same idea is called “manual mode”.}(hjڌhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chK=hjhhubh)}(hXThe implementation uses the hardware-based PSR support which automatically enters/exits self-refresh mode. The hardware takes care of sending the required DP aux message and could even retrain the link (that part isn't enabled yet though). The hardware also keeps track of any frontbuffer changes to know when to exit self-refresh mode again. Unfortunately that part doesn't work too well, hence why the i915 PSR support uses the software frontbuffer tracking to make sure it doesn't miss a screen update. For this integration intel_psr_invalidate() and intel_psr_flush() get called by the frontbuffer tracking code. Note that because of locking issues the self-refresh re-enable code is done from a work queue, which must be correctly synchronized/cancelled when shutting down the pipe."h]hXThe implementation uses the hardware-based PSR support which automatically enters/exits self-refresh mode. The hardware takes care of sending the required DP aux message and could even retrain the link (that part isn’t enabled yet though). The hardware also keeps track of any frontbuffer changes to know when to exit self-refresh mode again. Unfortunately that part doesn’t work too well, hence why the i915 PSR support uses the software frontbuffer tracking to make sure it doesn’t miss a screen update. For this integration intel_psr_invalidate() and intel_psr_flush() get called by the frontbuffer tracking code. Note that because of locking issues the self-refresh re-enable code is done from a work queue, which must be correctly synchronized/cancelled when shutting down the pipe.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKAhjhhubh)}(hDC3CO (DC3 clock off)h]hDC3CO (DC3 clock off)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKMhjhhubh)}(hXNOn top of PSR2, GEN12 adds a intermediate power savings state that turns clock off automatically during PSR2 idle state. The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep entry/exit allows the HW to enter a low-power state even when page flipping periodically (for instance a 30fps video playback scenario).h]hXNOn top of PSR2, GEN12 adds a intermediate power savings state that turns clock off automatically during PSR2 idle state. The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep entry/exit allows the HW to enter a low-power state even when page flipping periodically (for instance a 30fps video playback scenario).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKOhjhhubh)}(hXEvery time a flips occurs PSR2 will get out of deep sleep state(if it was), so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 frames, if no other flip occurs and the function above is executed, DC3CO is disabled and PSR2 is configured to enter deep sleep, resetting again in case of another flip. Front buffer modifications do not trigger DC3CO activation on purpose as it would bring a lot of complexity and most of the moderns systems will only use page flips.h]hXEvery time a flips occurs PSR2 will get out of deep sleep state(if it was), so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 frames, if no other flip occurs and the function above is executed, DC3CO is disabled and PSR2 is configured to enter deep sleep, resetting again in case of another flip. Front buffer modifications do not trigger DC3CO activation on purpose as it would bring a lot of complexity and most of the moderns systems will only use page flips.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKUhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_disable (C function)c.intel_psr_disablehNtauh1jhjhhhNhNubj')}(hhh](j,)}(havoid intel_psr_disable (struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h]j2)}(h`void intel_psr_disable(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h](j)}(hvoidh]hvoid}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjMhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj:hhhjLhMubjz)}(hintel_psr_disableh]j;)}(hintel_psr_disableh]hintel_psr_disable}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj[ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj:hhhjLhMubj)}(hJ(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h](j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjwubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjasbc.intel_psr_disableasbuh1hhjwubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjwubj)}(hjh]h*}(hjǍhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubj;)}(hintel_dph]hintel_dp}(hjԍhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjwubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjsubj)}(h-const struct intel_crtc_state *old_crtc_stateh](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hj&hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj(modnameN classnameNjXj[)}j^]jc.intel_psr_disableasbuh1hhjubji)}(h h]h }(hjDhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hold_crtc_stateh]hold_crtc_state}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjsubeh}(h]h ]h"]h$]h&]jjuh1jhj:hhhjLhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj6hhhjLhMubah}(h]j1ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjLhMhj3hhubj1)}(hhh]h)}(h Disable PSRh]h Disable PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj3hhhjLhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_dp *intel_dp`` Intel DP ``const struct intel_crtc_state *old_crtc_state`` old CRTC state **Description** This function needs to be called before disabling pipe.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjx)}(hhh](j})}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjʎh]hstruct intel_dp *intel_dp}(hj̎hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȎubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjĎubj)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjߎhMhjubah}(h]h ]h"]h$]h&]uh1jhjĎubeh}(h]h ]h"]h$]h&]uh1j|hjߎhMhjubj})}(hA``const struct intel_crtc_state *old_crtc_state`` old CRTC state h](j)}(h1``const struct intel_crtc_state *old_crtc_state``h]j)}(hjh]h-const struct intel_crtc_state *old_crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(hold CRTC stateh]hold CRTC state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj>h]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj<ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(h7This function needs to be called before disabling pipe.h]h7This function needs to be called before disabling pipe.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_pause (C function)c.intel_psr_pausehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h0void intel_psr_pause (struct intel_dp *intel_dp)h]j2)}(h/void intel_psr_pause(struct intel_dp *intel_dp)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_psr_pauseh]j;)}(hintel_psr_pauseh]hintel_psr_pause}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj͏hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hjޏhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjۏubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_pauseasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj{hhhjhMubah}(h]jvah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjxhhubj1)}(hhh]h)}(h Pause PSRh]h Pause PSR}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj@hhubah}(h]h ]h"]h$]h&]uh1j0hjxhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj[jSj[jTjUjVuh1j&hhhjhNhNubjX)}(h~**Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function need to be called after enabling psr.h](h)}(h**Parameters**h]jb)}(hjeh]h Parameters}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjcubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj_ubjx)}(hhh]j})}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj~ubj)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj{ubah}(h]h ]h"]h$]h&]uh1jwhj_ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj_ubh)}(h3This function need to be called after enabling psr.h]h3This function need to be called after enabling psr.}(hjՐhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_resume (C function)c.intel_psr_resumehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h1void intel_psr_resume (struct intel_dp *intel_dp)h]j2)}(h0void intel_psr_resume(struct intel_dp *intel_dp)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_psr_resumeh]j;)}(hintel_psr_resumeh]hintel_psr_resume}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj!ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj=ubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjamodnameN classnameNjXj[)}j^]ja)}jTj'sbc.intel_psr_resumeasbuh1hhj=ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj=ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubj;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj=ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj9ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h Resume PSRh]h Resume PSR}(hjđhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjܑjSjܑjTjUjVuh1j&hhhjhNhNubjX)}(h}**Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function need to be called after pausing psr.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjx)}(hhh]j})}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj@h]h Description}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj>ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(h2This function need to be called after pausing psr.h]h2This function need to be called after pausing psr.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_psr_needs_block_dc_vblank (C function)!c.intel_psr_needs_block_dc_vblankhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hPbool intel_psr_needs_block_dc_vblank (const struct intel_crtc_state *crtc_state)h]j2)}(hObool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_psr_needs_block_dc_vblankh]j;)}(hintel_psr_needs_block_dc_vblankh]hintel_psr_needs_block_dc_vblank}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjΒhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjܒhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb!c.intel_psr_needs_block_dc_vblankasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj}hhhjhMubah}(h]jxah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjzhhubj1)}(hhh]h)}(h!Check if block dc entry is neededh]h!Check if block dc entry is needed}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj\hhubah}(h]h ]h"]h$]h&]uh1j0hjzhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjwjSjwjTjUjVuh1j&hhhjhNhNubjX)}(hXe**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC status **Description** We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj{ubjx)}(hhh]j})}(h:``const struct intel_crtc_state *crtc_state`` CRTC status h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(h CRTC statush]h CRTC status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhj{ubh)}(h**Description**h]jb)}(hjۓh]h Description}(hjݓhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjٓubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj{ubh)}(hXWe need to block DC6 entry in case of Panel Replay as enabling VBI doesn't prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events.h]hX We need to block DC6 entry in case of Panel Replay as enabling VBI doesn’t prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"1intel_psr_trigger_frame_change_event (C function)&c.intel_psr_trigger_frame_change_eventhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h|void intel_psr_trigger_frame_change_event (struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h]j2)}(h{void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj.hMubjz)}(h$intel_psr_trigger_frame_change_eventh]j;)}(h$intel_psr_trigger_frame_change_eventh]h$intel_psr_trigger_frame_change_event}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj=ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj.hMubj)}(hR(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubji)}(h h]h }(hjjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYubh)}(hhh]j;)}(h intel_dsbh]h intel_dsb}(hj{hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjxubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj}modnameN classnameNjXj[)}j^]ja)}jTjCsb&c.intel_psr_trigger_frame_change_eventasbuh1hhjYubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubj;)}(hdsbh]hdsb}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjYubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjUubj)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjϔhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj˔ubji)}(h h]h }(hjܔhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj˔ubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j&c.intel_psr_trigger_frame_change_eventasbuh1hhj˔ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj˔ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj˔ubj;)}(hstateh]hstate}(hj&hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj˔ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjUubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubji)}(h h]h }(hjLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj;ubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjZubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj_modnameN classnameNjXj[)}j^]j&c.intel_psr_trigger_frame_change_eventasbuh1hhj;ubji)}(h h]h }(hj{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj;ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjUubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj.hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj.hMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj.hMhjhhubj1)}(hhh]h)}(hTrigger "Frame Change" eventh]h Trigger “Frame Change” event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj.hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjؕjSjؕjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_dsb *dsb`` DSB context ``struct intel_atomic_state *state`` the atomic state ``struct intel_crtc *crtc`` the CRTC **Description** Generate PSR "Frame Change" event.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjܕubjx)}(hhh](j})}(h&``struct intel_dsb *dsb`` DSB context h](j)}(h``struct intel_dsb *dsb``h]j)}(hjh]hstruct intel_dsb *dsb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(h DSB contexth]h DSB context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(h6``struct intel_atomic_state *state`` the atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hj:h]h struct intel_atomic_state *state}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj4ubj)}(hhh]h)}(hthe atomic stateh]hthe atomic state}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhMhjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1j|hjOhMhjubj})}(h%``struct intel_crtc *crtc`` the CRTC h](j)}(h``struct intel_crtc *crtc``h]j)}(hjsh]hstruct intel_crtc *crtc}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjmubj)}(hhh]h)}(hthe CRTCh]hthe CRTC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjܕubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjܕubh)}(h"Generate PSR "Frame Change" event.h]h&Generate PSR “Frame Change” event.}(hjĖhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjܕubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+intel_psr_wait_for_idle_locked (C function) c.intel_psr_wait_for_idle_lockedhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hSvoid intel_psr_wait_for_idle_locked (const struct intel_crtc_state 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reftargetjkmodnameN classnameNjXj[)}j^]ja)}jTjsb c.intel_psr_wait_for_idle_lockedasbuh1hhj,ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj,ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj;)}(hnew_crtc_stateh]hnew_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj,ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM| ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM| ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM| hjhhubj1)}(hhh]h)}(h'wait for PSR be ready for a pipe updateh]h'wait for PSR be ready for a pipe update}(hjΗhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMv hj˗hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM| ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *new_crtc_state`` new CRTC state **Description** This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMz hjubjx)}(hhh]j})}(hA``const struct intel_crtc_state *new_crtc_state`` new CRTC state h](j)}(h1``const struct intel_crtc_state *new_crtc_state``h]j)}(hjh]h-const struct intel_crtc_state *new_crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMw hj ubj)}(hhh]h)}(hnew CRTC stateh]hnew CRTC state}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMw hj%ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj$hMw hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjJh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjHubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMy hjubh)}(h|This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.h]h|This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMy hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_psr_invalidate (C function)c.intel_psr_invalidatehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hnvoid intel_psr_invalidate (struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h]j2)}(hmvoid intel_psr_invalidate(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_psr_invalidateh]j;)}(hintel_psr_invalidateh]hintel_psr_invalidate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(hT(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj̘hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȘubji)}(h h]h }(hj٘hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjȘubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_invalidateasbuh1hhjȘubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjȘubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȘubj;)}(hdisplayh]hdisplay}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjȘubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjĘubj)}(hunsigned frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubji)}(h h]h }(hjLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj:ubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj:ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjĘubj)}(henum fb_op_origin originh](j)}(hjh]henum}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjoubh)}(hhh]j;)}(h fb_op_originh]h fb_op_origin}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_psr_invalidateasbuh1hhjoubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjoubj;)}(horiginh]horigin}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjoubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjĘubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(hInvalidate PSRh]hInvalidate PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMs hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXA**Parameters** ``struct intel_display *display`` display device ``unsigned frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the invalidate **Description** Since the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering starts and a buffer gets dirtied. PSR must be disabled if the frontbuffer mask contains a buffer relevant to PSR. Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMw hjubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hj(h]hstruct intel_display *display}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMt hj"ubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMt hj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj=hMt hjubj})}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h``unsigned frontbuffer_bits``h]j)}(hjah]hunsigned frontbuffer_bits}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMu hj[ubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMu hjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hjvhMu hjubj})}(hC``enum fb_op_origin origin`` which operation caused the invalidate h](j)}(h``enum fb_op_origin origin``h]j)}(hjh]henum fb_op_origin origin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMv hjubj)}(hhh]h)}(h%which operation caused the invalidateh]h%which operation caused the invalidate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMv hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMv hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj՚h]h Description}(hjךhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjӚubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMx hjubh)}(hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. 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PSR must be disabled if the frontbuffer mask contains a buffer relevant to PSR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMx hjubh)}(hIDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."h]hKDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM} hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_flush (C function)c.intel_psr_flushhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hivoid intel_psr_flush (struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h]j2)}(hhvoid intel_psr_flush(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hvoidh]hvoid}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj%hhhj7hM ubjz)}(hintel_psr_flushh]j;)}(hintel_psr_flushh]hintel_psr_flush}(hjJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj%hhhj7hM ubj)}(hT(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubji)}(h h]h }(hjshhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjLsbc.intel_psr_flushasbuh1hhjbubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjbubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj^ubj)}(hunsigned frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hj؛hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjԛubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjԛubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjԛubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj^ubj)}(henum fb_op_origin originh](j)}(hjh]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(h fb_op_originh]h fb_op_origin}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj-modnameN classnameNjXj[)}j^]jc.intel_psr_flushasbuh1hhj ubji)}(h h]h }(hjIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj;)}(horiginh]horigin}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj^ubeh}(h]h ]h"]h$]h&]jjuh1jhj%hhhj7hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj!hhhj7hM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj7hM hjhhubj1)}(hhh]h)}(h Flush PSRh]h Flush PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hj~hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj7hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX=**Parameters** ``struct intel_display *display`` display device ``unsigned frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the flush **Description** Since the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. 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Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjœh]hstruct intel_display *display}(hjĜhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjۜhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjלhM hj؜ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjלhM hjubj})}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h``unsigned frontbuffer_bits``h]j)}(hjh]hunsigned frontbuffer_bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubj})}(h>``enum fb_op_origin origin`` which operation caused the flush h](j)}(h``enum fb_op_origin origin``h]j)}(hj4h]henum fb_op_origin origin}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hj.ubj)}(hhh]h)}(h which operation caused the flushh]h which operation caused the flush}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhM hjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hjIhM hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjoh]h Description}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjmubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty.h]hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hHDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.h]hHDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_init (C function)c.intel_psr_inithNtauh1jhjhhhNhNubj')}(hhh](j,)}(h/void intel_psr_init (struct intel_dp *intel_dp)h]j2)}(h.void intel_psr_init(struct intel_dp *intel_dp)h](j)}(hvoidh]hvoid}(hjÝhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM ubji)}(h h]h }(hjҝhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjѝhM ubjz)}(hintel_psr_inith]j;)}(hintel_psr_inith]hintel_psr_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjѝhM ubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_initasbuh1hhjubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hintel_dph]hintel_dp}(hjYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjѝhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjѝhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjѝhM hjhhubj1)}(hhh]h)}(hInit basic PSR work and mutex.h]hInit basic PSR work and mutex.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjѝhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX **Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubjx)}(hhh]j})}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjĞh]hstruct intel_dp *intel_dp}(hjƞhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjžubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj)}(hhh]h)}(hIntel DPh]hIntel DP}(hjݞhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjٞhM hjڞubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjٞhM hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hThis function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.h]hThis function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_link_ok (C function)c.intel_psr_link_okhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h2bool intel_psr_link_ok (struct intel_dp *intel_dp)h]j2)}(h1bool intel_psr_link_ok(struct intel_dp *intel_dp)h](j)}(hjh]hbool}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM ubji)}(h h]h }(hjRhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@hhhjQhM ubjz)}(hintel_psr_link_okh]j;)}(hintel_psr_link_okh]hintel_psr_link_ok}(hjdhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj@hhhjQhM ubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|ubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjfsbc.intel_psr_link_okasbuh1hhj|ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|ubj)}(hjh]h*}(hj̟hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubj;)}(hintel_dph]hintel_dp}(hjٟhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxubah}(h]h ]h"]h$]h&]jjuh1jhj@hhhjQhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj<hhhjQhM ubah}(h]j7ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjQhM hj9hhubj1)}(hhh]h)}(hreturn psr->link_okh]hreturn psr->link_ok}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hj9hhhjQhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_dp *intel_dp`` struct intel_dp **Description** We are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter. Return value of link_okh](h)}(h**Parameters**h]jb)}(hj%h]h Parameters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubjx)}(hhh]j})}(h.``struct intel_dp *intel_dp`` struct intel_dp h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjDh]hstruct intel_dp *intel_dp}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hj>ubj)}(hhh]h)}(hstruct intel_dph]hstruct intel_dp}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhM hjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1j|hjYhM hj;ubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj}ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hXRWe are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter.h]hXRWe are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hReturn value of link_okh]hReturn value of link_ok}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_lock (C function)c.intel_psr_lockhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h?void intel_psr_lock (const struct intel_crtc_state *crtc_state)h]j2)}(h>void intel_psr_lock(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjӠhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjϠhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjϠhhhjhMubjz)}(hintel_psr_lockh]j;)}(hintel_psr_lockh]hintel_psr_lock}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjϠhhhjhMubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]hstruct}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjKmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_lockasbuh1hhj ubji)}(h h]h }(hjihhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjϠhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjˠhhhjhMubah}(h]jƠah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjȠhhubj1)}(hhh]h)}(h grab PSR lockh]h grab PSR lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjȠhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjơjSjơjTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** This is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.h](h)}(h**Parameters**h]jb)}(hjСh]h Parameters}(hjҡhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjΡubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjʡubjx)}(hhh]j})}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubah}(h]h ]h"]h$]h&]uh1jwhjʡubh)}(h**Description**h]jb)}(hj*h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj(ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjʡubh)}(hThis is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.h]hThis is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjʡubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_unlock (C function)c.intel_psr_unlockhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hAvoid intel_psr_unlock (const struct intel_crtc_state *crtc_state)h]j2)}(h@void intel_psr_unlock(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hj~hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjkhhhj}hMubjz)}(hintel_psr_unlockh]j;)}(hintel_psr_unlockh]hintel_psr_unlock}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjkhhhj}hMubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjǢhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjԢhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_unlockasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjkhhhj}hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjghhhj}hMubah}(h]jbah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj}hMhjdhhubj1)}(hhh]h)}(hrelease PSR lockh]hrelease PSR lock}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjGhhubah}(h]h ]h"]h$]h&]uh1j0hjdhhhj}hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjbjSjbjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Release the PSR lock that was held during pipe update.h](h)}(h**Parameters**h]jb)}(hjlh]h Parameters}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjfubjx)}(hhh]j})}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjfubh)}(h**Description**h]jb)}(hjƣh]h Description}(hjȣhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjģubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjfubh)}(h6Release the PSR lock that was held during pipe update.h]h6Release the PSR lock that was held during pipe update.}(hjܣhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjfubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]panel-self-refresh-psr-psr-srdah ]h"] panel self refresh psr (psr/srd)ah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hFrame Buffer Compression (FBC)h]hFrame Buffer Compression (FBC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hFBC tries to save memory bandwidth (and so power consumption) by compressing the amount of memory used by the display. It is total transparent to user space and completely handled in the kernel.h]hFBC tries to save memory bandwidth (and so power consumption) by compressing the amount of memory used by the display. It is total transparent to user space and completely handled in the kernel.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:177: ./drivers/gpu/drm/i915/display/intel_fbc.chKhjhhubh)}(hThe benefits of FBC are mostly visible with solid backgrounds and variation-less patterns. It comes from keeping the memory footprint small and having fewer memory pages opened and accessed for refreshing the display.h]hThe benefits of FBC are mostly visible with solid backgrounds and variation-less patterns. It comes from keeping the memory footprint small and having fewer memory pages opened and accessed for refreshing the display.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:177: ./drivers/gpu/drm/i915/display/intel_fbc.chKhjhhubh)}(hi915 is responsible to reserve stolen memory for FBC and configure its offset on proper registers. The hardware takes care of all compress/decompress. However there are many known cases where we have to forcibly disable it to allow proper screen updates.h]hi915 is responsible to reserve stolen memory for FBC and configure its offset on proper registers. The hardware takes care of all compress/decompress. However there are many known cases where we have to forcibly disable it to allow proper screen updates.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:177: ./drivers/gpu/drm/i915/display/intel_fbc.chK!hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_fbc_disable (C function)c.intel_fbc_disablehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h0void intel_fbc_disable (struct intel_crtc *crtc)h]j2)}(h/void intel_fbc_disable(struct intel_crtc *crtc)h](j)}(hvoidh]hvoid}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMXubji)}(h h]h }(hj`hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjMhhhj_hMXubjz)}(hintel_fbc_disableh]j;)}(hintel_fbc_disableh]hintel_fbc_disable}(hjrhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjMhhhj_hMXubj)}(h(struct intel_crtc *crtc)h]j)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjtsbc.intel_fbc_disableasbuh1hhjubji)}(h h]h }(hj̤hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjڤhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjMhhhj_hMXubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjIhhhj_hMXubah}(h]jDah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj_hMXhjFhhubj1)}(hhh]h)}(h(disable FBC if it's associated with crtch]h*disable FBC if it’s associated with crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMShjhhubah}(h]h ]h"]h$]h&]uh1j0hjFhhhj_hMXubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj)jSj)jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_crtc *crtc`` the CRTC **Description** This function disables FBC if it's associated with the provided CRTC.h](h)}(h**Parameters**h]jb)}(hj3h]h Parameters}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj1ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMWhj-ubjx)}(hhh]j})}(h%``struct intel_crtc *crtc`` the CRTC h](j)}(h``struct intel_crtc *crtc``h]j)}(hjRh]hstruct intel_crtc *crtc}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMThjLubj)}(hhh]h)}(hthe CRTCh]hthe CRTC}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMThjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjghMThjIubah}(h]h ]h"]h$]h&]uh1jwhj-ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMVhj-ubh)}(hEThis function disables FBC if it's associated with the provided CRTC.h]hGThis function disables FBC if it’s associated with the provided CRTC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMVhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"/intel_fbc_handle_fifo_underrun_irq (C function)$c.intel_fbc_handle_fifo_underrun_irqhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hGvoid intel_fbc_handle_fifo_underrun_irq (struct intel_display *display)h]j2)}(hFvoid intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjҥhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΥhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjΥhhhjhMubjz)}(h"intel_fbc_handle_fifo_underrun_irqh]j;)}(h"intel_fbc_handle_fifo_underrun_irqh]h"intel_fbc_handle_fifo_underrun_irq}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjΥhhhjhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj*ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj/modnameN classnameNjXj[)}j^]ja)}jTjsb$c.intel_fbc_handle_fifo_underrun_irqasbuh1hhj ubji)}(h h]h }(hjMhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hdisplayh]hdisplay}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjΥhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjʥhhhjhMubah}(h]jťah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjǥhhubj1)}(hhh]h)}(h'disable FBC when we get a FIFO underrunh]h'disable FBC when we get a FIFO underrun}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjǥhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX=**Parameters** ``struct intel_display *display`` display **Description** Without FBC, most underruns are harmless and don't really cause too many problems, except for an annoying message on dmesg. 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This function is called from the IRQ handler.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubjx)}(hhh]j})}(h*``struct intel_display *display`` display h](j)}(h!``struct intel_display *display``h]j)}(hjӦh]hstruct intel_display *display}(hjզhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjѦubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjͦubj)}(hhh]h)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjͦubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjʦubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubh)}(hXWithout FBC, most underruns are harmless and don't really cause too many problems, except for an annoying message on dmesg. With FBC, underruns can become black screens or even worse, especially when paired with bad watermarks. So in order for us to be on the safe side, completely disable FBC in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe already suggests that watermarks may be bad, so try to be as safe as possible.h]hXWithout FBC, most underruns are harmless and don’t really cause too many problems, except for an annoying message on dmesg. With FBC, underruns can become black screens or even worse, especially when paired with bad watermarks. So in order for us to be on the safe side, completely disable FBC in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe already suggests that watermarks may be bad, so try to be as safe as possible.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubh)}(h-This function is called from the IRQ handler.h]h-This function is called from the IRQ handler.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_fbc_init (C function)c.intel_fbc_inithNtauh1jhjhhhNhNubj')}(hhh](j,)}(h3void intel_fbc_init (struct intel_display *display)h]j2)}(h2void intel_fbc_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM(ubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj^hhhjphM(ubjz)}(hintel_fbc_inith]j;)}(hintel_fbc_inith]hintel_fbc_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj^hhhjphM(ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_fbc_initasbuh1hhjubji)}(h h]h }(hjݧhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj^hhhjphM(ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjZhhhjphM(ubah}(h]jUah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjphM(hjWhhubj1)}(hhh]h)}(hInitialize FBCh]hInitialize FBC}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM#hjhhubah}(h]h ]h"]h$]h&]uh1j0hjWhhhjphM(ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj:jSj:jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display **Description** This function might be called during PM init process.h](h)}(h**Parameters**h]jb)}(hjDh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjBubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM'hj>ubjx)}(hhh]j})}(h*``struct intel_display *display`` display h](j)}(h!``struct intel_display *display``h]j)}(hjch]hstruct intel_display *display}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM$hj]ubj)}(hhh]h)}(hdisplayh]hdisplay}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhM$hjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1j|hjxhM$hjZubah}(h]h ]h"]h$]h&]uh1jwhj>ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM&hj>ubh)}(h5This function might be called during PM init process.h]h5This function might be called during PM init process.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM&hj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_fbc_sanitize (C function)c.intel_fbc_sanitizehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h7void intel_fbc_sanitize (struct intel_display *display)h]j2)}(h6void intel_fbc_sanitize(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjߨhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM<ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjߨhhhjhM<ubjz)}(hintel_fbc_sanitizeh]j;)}(hintel_fbc_sanitizeh]hintel_fbc_sanitize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjߨhhhjhM<ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj@modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_fbc_sanitizeasbuh1hhjubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjߨhhhjhM<ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjۨhhhjhM<ubah}(h]j֨ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM<hjبhhubj1)}(hhh]h)}(h Sanitize FBCh]h Sanitize FBC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM5hjhhubah}(h]h ]h"]h$]h&]uh1j0hjبhhhjhM<ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display **Description** Make sure FBC is initially disabled since we have no idea eg. into which parts of stolen it might be scribbling into.h](h)}(h**Parameters**h]jb)}(hjũh]h Parameters}(hjǩhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjéubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM9hjubjx)}(hhh]j})}(h*``struct intel_display *display`` display h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM6hjީubj)}(hhh]h)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM6hjubah}(h]h ]h"]h$]h&]uh1jhjީubeh}(h]h ]h"]h$]h&]uh1j|hjhM6hj۩ubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM8hjubh)}(huMake sure FBC is initially disabled since we have no idea eg. into which parts of stolen it might be scribbling into.h]huMake sure FBC is initially disabled since we have no idea eg. into which parts of stolen it might be scribbling into.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM8hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]frame-buffer-compression-fbcah ]h"]frame buffer compression (fbc)ah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(h%Display Refresh Rate Switching (DRRS)h]h%Display Refresh Rate Switching (DRRS)}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShhhhhKubh)}(hDisplay Refresh Rate Switching (DRRS) is a power conservation feature which enables swtching between low and high refresh rates, dynamically, based on the usage scenario. This feature is applicable for internal panels.h]hDisplay Refresh Rate Switching (DRRS) is a power conservation feature which enables swtching between low and high refresh rates, dynamically, based on the usage scenario. This feature is applicable for internal panels.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjShhubh)}(hIndication that the panel supports DRRS is given by the panel EDID, which would list multiple refresh rates for one resolution.h]hIndication that the panel supports DRRS is given by the panel EDID, which would list multiple refresh rates for one resolution.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjShhubh)}(hX\DRRS is of 2 types - static and seamless. Static DRRS involves changing refresh rate (RR) by doing a full modeset (may appear as a blink on screen) and is used in dock-undock scenario. Seamless DRRS involves changing RR without any visual effect to the user and can be used during normal system usage. This is done by programming certain registers.h]hX\DRRS is of 2 types - static and seamless. Static DRRS involves changing refresh rate (RR) by doing a full modeset (may appear as a blink on screen) and is used in dock-undock scenario. Seamless DRRS involves changing RR without any visual effect to the user and can be used during normal system usage. This is done by programming certain registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjShhubh)}(haSupport for static/seamless DRRS may be indicated in the VBT based on inputs from the panel spec.h]haSupport for static/seamless DRRS may be indicated in the VBT based on inputs from the panel spec.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK!hjShhubh)}(hADRRS saves power by switching to low RR based on usage scenarios.h]hADRRS saves power by switching to low RR based on usage scenarios.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK$hjShhubh)}(hX4The implementation is based on frontbuffer tracking implementation. When there is a disturbance on the screen triggered by user activity or a periodic system activity, DRRS is disabled (RR is changed to high RR). When there is no movement on screen, after a timeout of 1 second, a switch to low RR is made.h]hX4The implementation is based on frontbuffer tracking implementation. When there is a disturbance on the screen triggered by user activity or a periodic system activity, DRRS is disabled (RR is changed to high RR). When there is no movement on screen, after a timeout of 1 second, a switch to low RR is made.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK&hjShhubh)}(hjFor integration with frontbuffer tracking code, intel_drrs_invalidate() and intel_drrs_flush() are called.h]hjFor integration with frontbuffer tracking code, intel_drrs_invalidate() and intel_drrs_flush() are called.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK,hjShhubh)}(hDRRS can be further extended to support other internal panels and also the scenario of video playback wherein RR is set based on the rate requested by userspace.h]hDRRS can be further extended to support other internal panels and also the scenario of video playback wherein RR is set based on the rate requested by userspace.}(hjͪhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK/hjShhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_drrs_activate (C function)c.intel_drrs_activatehNtauh1jhjShhhNhNubj')}(hhh](j,)}(hDvoid intel_drrs_activate (const struct intel_crtc_state *crtc_state)h]j2)}(hCvoid intel_drrs_activate(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(hintel_drrs_activateh]j;)}(hintel_drrs_activateh]hintel_drrs_activate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjuh]hconst}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubji)}(h h]h }(hj?hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubj)}(hjh]hstruct}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_drrs_activateasbuh1hhj.ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj*ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(h activate DRRSh]h activate DRRS}(hjЫhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjͫhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjShNhNubjX)}(h|**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Activates DRRS on the crtc.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjubjx)}(hhh]j})}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhj ubj)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj&hKhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjLh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjJubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjubh)}(hActivates DRRS on the crtc.h]hActivates DRRS on the crtc.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjShhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_drrs_deactivate (C function)c.intel_drrs_deactivatehNtauh1jhjShhhNhNubj')}(hhh](j,)}(hJvoid intel_drrs_deactivate (const struct intel_crtc_state *old_crtc_state)h]j2)}(hIvoid intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(hintel_drrs_deactivateh]j;)}(hintel_drrs_deactivateh]hintel_drrs_deactivate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubj)}(h/(const struct intel_crtc_state *old_crtc_state)h]j)}(h-const struct intel_crtc_state *old_crtc_stateh](j)}(hjuh]hconst}(hjάhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʬubji)}(h h]h }(hj۬hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjʬubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʬubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjʬubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_drrs_deactivateasbuh1hhjʬubji)}(h h]h }(hj'hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjʬubj)}(hjh]h*}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʬubj;)}(hold_crtc_stateh]hold_crtc_state}(hjBhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjʬubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjƬubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(hdeactivate DRRSh]hdeactivate DRRS}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjihhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjShNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *old_crtc_state`` the old crtc state **Description** Deactivates DRRS on the crtc.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjubjx)}(hhh]j})}(hE``const struct intel_crtc_state *old_crtc_state`` the old crtc state h](j)}(h1``const struct intel_crtc_state *old_crtc_state``h]j)}(hjh]h-const struct intel_crtc_state *old_crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjubj)}(hhh]h)}(hthe old crtc stateh]hthe old crtc state}(hjƭhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj­hKhjíubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj­hKhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjubh)}(hDeactivates DRRS on the crtc.h]hDeactivates DRRS on the crtc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjShhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_drrs_invalidate (C function)c.intel_drrs_invalidatehNtauh1jhjShhhNhNubj')}(hhh](j,)}(hYvoid intel_drrs_invalidate (struct intel_display *display, unsigned int frontbuffer_bits)h]j2)}(hXvoid intel_drrs_invalidate(struct intel_display *display, unsigned int frontbuffer_bits)h](j)}(hvoidh]hvoid}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)hhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMubji)}(h h]h }(hj<hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)hhhj;hMubjz)}(hintel_drrs_invalidateh]j;)}(hintel_drrs_invalidateh]hintel_drrs_invalidate}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjJubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj)hhhj;hMubj)}(h>(struct intel_display *display, unsigned int frontbuffer_bits)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubji)}(h h]h }(hjwhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjPsbc.intel_drrs_invalidateasbuh1hhjfubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubj;)}(hdisplayh]hdisplay}(hjîhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjbubj)}(hunsigned int frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hjܮhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjخubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjخubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjخubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjخubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjخubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjbubeh}(h]h ]h"]h$]h&]jjuh1jhj)hhhj;hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj%hhhj;hMubah}(h]j ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj;hMhj"hhubj1)}(hhh]h)}(hDisable Idleness DRRSh]hDisable Idleness DRRS}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhj;hhubah}(h]h ]h"]h$]h&]uh1j0hj"hhhj;hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjVjSjVjTjUjVuh1j&hhhjShNhNubjX)}(hXi**Parameters** ``struct intel_display *display`` display device ``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits **Description** This function gets called everytime rendering on the given planes start. Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.h](h)}(h**Parameters**h]jb)}(hj`h]h Parameters}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj^ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM hjZubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjyubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjvubj})}(hB``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h!``unsigned int frontbuffer_bits``h]j)}(hjh]hunsigned int frontbuffer_bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjѯhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjͯhMhjίubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjͯhMhjvubeh}(h]h ]h"]h$]h&]uh1jwhjZubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM hjZubh)}(hThis function gets called everytime rendering on the given planes start. Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).h]hThis function gets called everytime rendering on the given planes start. Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM hjZubh)}(hIDirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.h]hIDirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM hjZubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjShhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_drrs_flush (C function)c.intel_drrs_flushhNtauh1jhjShhhNhNubj')}(hhh](j,)}(hTvoid intel_drrs_flush (struct intel_display *display, unsigned int frontbuffer_bits)h]j2)}(hSvoid intel_drrs_flush(struct intel_display *display, unsigned int frontbuffer_bits)h](j)}(hvoidh]hvoid}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjChhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM!ubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjChhhjUhM!ubjz)}(hintel_drrs_flushh]j;)}(hintel_drrs_flushh]hintel_drrs_flush}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjdubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjChhhjUhM!ubj)}(h>(struct intel_display *display, unsigned int frontbuffer_bits)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjjsbc.intel_drrs_flushasbuh1hhjubji)}(h h]h }(hj°hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjаhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjݰhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj|ubj)}(hunsigned int frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj|ubeh}(h]h ]h"]h$]h&]jjuh1jhjChhhjUhM!ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj?hhhjUhM!ubah}(h]j:ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjUhM!hj<hhubj1)}(hhh]h)}(hRestart Idleness DRRSh]hRestart Idleness DRRS}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjUhhubah}(h]h ]h"]h$]h&]uh1j0hj<hhhjUhM!ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjpjSjpjTjUjVuh1j&hhhjShNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device ``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits **Description** This function gets called every time rendering on the given planes has completed or flip on a crtc is completed. So DRRS should be upclocked (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, if no other planes are dirty. Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.h](h)}(h**Parameters**h]jb)}(hjzh]h Parameters}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjxubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjtubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hB``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h!``unsigned int frontbuffer_bits``h]j)}(hjұh]hunsigned int frontbuffer_bits}(hjԱhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjбubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhj̱ubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj̱ubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjtubh)}(h**Description**h]jb)}(hj h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjtubh)}(hThis function gets called every time rendering on the given planes has completed or flip on a crtc is completed. So DRRS should be upclocked (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, if no other planes are dirty.h]hThis function gets called every time rendering on the given planes has completed or flip on a crtc is completed. So DRRS should be upclocked (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, if no other planes are dirty.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjtubh)}(hIDirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.h]hIDirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjtubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjShhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_drrs_crtc_init (C function)c.intel_drrs_crtc_inithNtauh1jhjShhhNhNubj')}(hhh](j,)}(h3void intel_drrs_crtc_init (struct intel_crtc *crtc)h]j2)}(h2void intel_drrs_crtc_init(struct intel_crtc *crtc)h](j)}(hvoidh]hvoid}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM/ubji)}(h h]h }(hjphhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]hhhjohM/ubjz)}(hintel_drrs_crtc_inith]j;)}(hintel_drrs_crtc_inith]hintel_drrs_crtc_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj]hhhjohM/ubj)}(h(struct intel_crtc *crtc)h]j)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_drrs_crtc_initasbuh1hhjubji)}(h h]h }(hjܲhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj]hhhjohM/ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjYhhhjohM/ubah}(h]jTah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjohM/hjVhhubj1)}(hhh]h)}(hInit DRRS for CRTCh]hInit DRRS for CRTC}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM(hjhhubah}(h]h ]h"]h$]h&]uh1j0hjVhhhjohM/ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj9jSj9jTjUjVuh1j&hhhjShNhNubjX)}(h**Parameters** ``struct intel_crtc *crtc`` crtc **Description** This function is called only once at driver load to initialize basic DRRS stuff.h](h)}(h**Parameters**h]jb)}(hjCh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjAubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM,hj=ubjx)}(hhh]j})}(h!``struct intel_crtc *crtc`` crtc h](j)}(h``struct intel_crtc *crtc``h]j)}(hjbh]hstruct intel_crtc *crtc}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM)hj\ubj)}(hhh]h)}(hcrtch]hcrtc}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhM)hjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1j|hjwhM)hjYubah}(h]h ]h"]h$]h&]uh1jwhj=ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM+hj=ubh)}(hPThis function is called only once at driver load to initialize basic DRRS stuff.h]hPThis function is called only once at driver load to initialize basic DRRS stuff.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM+hj=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjShhhNhNubeh}(h]#display-refresh-rate-switching-drrsah ]h"]%display refresh rate switching (drrs)ah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hDPIOh]hDPIO}(hjԳhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjѳhhhhhKubh)}(hXVLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI ports. DPIO is the name given to such a display PHY. These PHYs don't follow the standard programming model using direct MMIO registers, and instead their registers must be accessed through IOSF sideband. VLV has one such PHY for driving ports B and C, and CHV adds another PHY for driving port D. Each PHY responds to specific IOSF-SB port.h]hXVLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI ports. DPIO is the name given to such a display PHY. These PHYs don’t follow the standard programming model using direct MMIO registers, and instead their registers must be accessed through IOSF sideband. VLV has one such PHY for driving ports B and C, and CHV adds another PHY for driving port D. Each PHY responds to specific IOSF-SB port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK&hjѳhhubh)}(hX9Each display PHY is made up of one or two channels. Each channel houses a common lane part which contains the PLL and other common logic. CH0 common lane also contains the IOSF-SB logic for the Common Register Interface (CRI) ie. the DPIO registers. CRI clock must be running when any DPIO registers are accessed.h]hX9Each display PHY is made up of one or two channels. Each channel houses a common lane part which contains the PLL and other common logic. CH0 common lane also contains the IOSF-SB logic for the Common Register Interface (CRI) ie. the DPIO registers. CRI clock must be running when any DPIO registers are accessed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK.hjѳhhubh)}(hIn addition to having their own registers, the PHYs are also controlled through some dedicated signals from the display controller. These include PLL reference clock enable, PLL enable, and CRI clock selection, for example.h]hIn addition to having their own registers, the PHYs are also controlled through some dedicated signals from the display controller. These include PLL reference clock enable, PLL enable, and CRI clock selection, for example.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK4hjѳhhubh)}(hX,Eeach channel also has two splines (also called data lanes), and each spline is made up of one Physical Access Coding Sub-Layer (PCS) block and two TX lanes. So each channel has two PCS blocks and four TX lanes. The TX lanes are used as DP lanes or TMDS data/clock pairs depending on the output type.h]hX,Eeach channel also has two splines (also called data lanes), and each spline is made up of one Physical Access Coding Sub-Layer (PCS) block and two TX lanes. So each channel has two PCS blocks and four TX lanes. The TX lanes are used as DP lanes or TMDS data/clock pairs depending on the output type.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK9hjѳhhubh)}(hX$Additionally the PHY also contains an AUX lane with AUX blocks for each channel. This is used for DP AUX communication, but this fact isn't really relevant for the driver since AUX is controlled from the display controller side. No DPIO registers need to be accessed during AUX communication,h]hX&Additionally the PHY also contains an AUX lane with AUX blocks for each channel. This is used for DP AUX communication, but this fact isn’t really relevant for the driver since AUX is controlled from the display controller side. No DPIO registers need to be accessed during AUX communication,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK?hjѳhhubh)}(hmGenerally on VLV/CHV the common lane corresponds to the pipe and the spline (PCS/TX) corresponds to the port.h]hmGenerally on VLV/CHV the common lane corresponds to the pipe and the spline (PCS/TX) corresponds to the port.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKEhjѳhhubh)}(hFor dual channel PHY (VLV/CHV):h]hFor dual channel PHY (VLV/CHV):}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKHhjѳhhubh block_quote)}(hapipe A == CMN/PLL/REF CH0 pipe B == CMN/PLL/REF CH1 port B == PCS/TX CH0 port C == PCS/TX CH1 h](h)}(hpipe A == CMN/PLL/REF CH0h]hpipe A == CMN/PLL/REF CH0}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKJhjMubh)}(hpipe B == CMN/PLL/REF CH1h]hpipe B == CMN/PLL/REF CH1}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKLhjMubh)}(hport B == PCS/TX CH0h]hport B == PCS/TX CH0}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKNhjMubh)}(hport C == PCS/TX CH1h]hport C == PCS/TX CH1}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKPhjMubeh}(h]h ]h"]h$]h&]uh1jKhj_hKJhjѳhhubh)}(hkThis is especially important when we cross the streams ie. drive port B with pipe B, or port C with pipe A.h]hkThis is especially important when we cross the streams ie. drive port B with pipe B, or port C with pipe A.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKRhjѳhhubh)}(hFor single channel PHY (CHV):h]hFor single channel PHY (CHV):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKUhjѳhhubjL)}(h0pipe C == CMN/PLL/REF CH0 port D == PCS/TX CH0 h](h)}(hpipe C == CMN/PLL/REF CH0h]hpipe C == CMN/PLL/REF CH0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKWhjubh)}(hport D == PCS/TX CH0h]hport D == PCS/TX CH0}(hjĴhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKYhjubeh}(h]h ]h"]h$]h&]uh1jKhjôhKWhjѳhhubh)}(hX3On BXT the entire PHY channel corresponds to the port. That means the PLL is also now associated with the port rather than the pipe, and so the clock needs to be routed to the appropriate transcoder. Port A PLL is directly connected to transcoder EDP and port B/C PLLs can be routed to any transcoder A/B/C.h]hX3On BXT the entire PHY channel corresponds to the port. That means the PLL is also now associated with the port rather than the pipe, and so the clock needs to be routed to the appropriate transcoder. Port A PLL is directly connected to transcoder EDP and port B/C PLLs can be routed to any transcoder A/B/C.}(hjٴhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK[hjѳhhubh)}(hiNote: DDI0 is digital port B, DD1 is digital port C, and DDI2 is digital port D (CHV) or port A (BXT). ::h]hfNote: DDI0 is digital port B, DD1 is digital port C, and DDI2 is digital port D (CHV) or port A (BXT).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKahjѳhhubj")}(hXwDual channel PHY (VLV/CHV/BXT) --------------------------------- | CH0 | CH1 | | CMN/PLL/REF | CMN/PLL/REF | |---------------|---------------| Display PHY | PCS01 | PCS23 | PCS01 | PCS23 | |-------|-------|-------|-------| |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| --------------------------------- | DDI0 | DDI1 | DP/HDMI ports --------------------------------- Single channel PHY (CHV/BXT) ----------------- | CH0 | | CMN/PLL/REF | |---------------| Display PHY | PCS01 | PCS23 | |-------|-------| |TX0|TX1|TX2|TX3| ----------------- | DDI2 | DP/HDMI port -----------------h]hXwDual channel PHY (VLV/CHV/BXT) --------------------------------- | CH0 | CH1 | | CMN/PLL/REF | CMN/PLL/REF | |---------------|---------------| Display PHY | PCS01 | PCS23 | PCS01 | PCS23 | |-------|-------|-------|-------| |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| --------------------------------- | DDI0 | DDI1 | DP/HDMI ports --------------------------------- Single channel PHY (CHV/BXT) ----------------- | CH0 | | CMN/PLL/REF | |---------------| Display PHY | PCS01 | PCS23 | |-------|-------| |TX0|TX1|TX2|TX3| ----------------- | DDI2 | DP/HDMI port -----------------}hjsbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKehjѳhhubeh}(h]dpioah ]h"]dpioah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hDMC Firmware Supporth]hDMC Firmware Support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hFrom gen9 onwards we have newly added DMC (Display microcontroller) in display engine to save and restore the state of display engine when it enter into low-power state and comes back to normal.h]hFrom gen9 onwards we have newly added DMC (Display microcontroller) in display engine to save and restore the state of display engine when it enter into low-power state and comes back to normal.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:201: ./drivers/gpu/drm/i915/display/intel_dmc.chK$hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_dmc_load_program (C function)c.intel_dmc_load_programhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h;void intel_dmc_load_program (struct intel_display *display)h]j2)}(h:void intel_dmc_load_program(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjChhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMGubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjChhhjUhMGubjz)}(hintel_dmc_load_programh]j;)}(hintel_dmc_load_programh]hintel_dmc_load_program}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjdubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjChhhjUhMGubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjjsbc.intel_dmc_load_programasbuh1hhjubji)}(h h]h }(hjµhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjеhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjݵhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj|ubah}(h]h ]h"]h$]h&]jjuh1jhjChhhjUhMGubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj?hhhjUhMGubah}(h]j:ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjUhMGhj<hhubj1)}(hhh]h)}(h+write the firmware from memory to register.h]h+write the firmware from memory to register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM@hjhhubah}(h]h ]h"]h$]h&]uh1j0hj<hhhjUhMGubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX$**Parameters** ``struct intel_display *display`` display instance **Description** DMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.h](h)}(h**Parameters**h]jb)}(hj)h]h Parameters}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMDhj#ubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjHh]hstruct intel_display *display}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMAhjBubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hMAhj^ubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1j|hj]hMAhj?ubah}(h]h ]h"]h$]h&]uh1jwhj#ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMChj#ubh)}(hDMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.h]hDMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMChj#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_dmc_disable_program (C function)c.intel_dmc_disable_programhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h>void intel_dmc_disable_program (struct intel_display *display)h]j2)}(h=void intel_dmc_disable_program(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjȶhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjĶhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMyubji)}(h h]h }(hj׶hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjĶhhhjֶhMyubjz)}(hintel_dmc_disable_programh]j;)}(hintel_dmc_disable_programh]hintel_dmc_disable_program}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjĶhhhjֶhMyubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj%modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_disable_programasbuh1hhjubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj^hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjĶhhhjֶhMyubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjֶhMyubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjֶhMyhjhhubj1)}(hhh]h)}(hdisable the firmwareh]hdisable the firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMshjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjֶhMyubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Disable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMwhjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjɷh]hstruct intel_display *display}(hj˷hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjǷubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMthj÷ubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj޷hMthj߷ubah}(h]h ]h"]h$]h&]uh1jhj÷ubeh}(h]h ]h"]h$]h&]uh1j|hj޷hMthjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMvhjubh)}(htDisable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.h]htDisable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMvhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dmc_init (C function)c.intel_dmc_inithNtauh1jhjhhhNhNubj')}(hhh](j,)}(h3void intel_dmc_init (struct intel_display *display)h]j2)}(h2void intel_dmc_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM1ubji)}(h h]h }(hjXhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEhhhjWhM1ubjz)}(hintel_dmc_inith]j;)}(hintel_dmc_inith]hintel_dmc_init}(hjjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjEhhhjWhM1ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjlsbc.intel_dmc_initasbuh1hhjubji)}(h h]h }(hjĸhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjҸhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj߸hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj~ubah}(h]h ]h"]h$]h&]jjuh1jhjEhhhjWhM1ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjAhhhjWhM1ubah}(h]j<ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjWhM1hj>hhubj1)}(hhh]h)}(h initialize the firmware loading.h]h initialize the firmware loading.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM+hjhhubah}(h]h ]h"]h$]h&]uh1j0hj>hhhjWhM1ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj!jSj!jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** This function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.h](h)}(h**Parameters**h]jb)}(hj+h]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj)ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM/hj%ubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjJh]hstruct intel_display *display}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM,hjDubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM,hj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j|hj_hM,hjAubah}(h]h ]h"]h$]h&]uh1jwhj%ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM.hj%ubh)}(hThis function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.h]hThis function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM.hj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dmc_suspend (C function)c.intel_dmc_suspendhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h6void intel_dmc_suspend (struct intel_display *display)h]j2)}(h5void intel_dmc_suspend(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjʹhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƹhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMnubji)}(h h]h }(hjٹhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjƹhhhjعhMnubjz)}(hintel_dmc_suspendh]j;)}(hintel_dmc_suspendh]hintel_dmc_suspend}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjƹhhhjعhMnubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj'modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_suspendasbuh1hhjubji)}(h h]h }(hjEhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj`hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjƹhhhjعhMnubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj¹hhhjعhMnubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjعhMnhjhhubj1)}(hhh]h)}(h*prepare DMC firmware before system suspendh]h*prepare DMC firmware before system suspend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMghjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjعhMnubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Prepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMkhjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj˺h]hstruct intel_display *display}(hjͺhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjɺubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhhjźubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhhjubah}(h]h ]h"]h$]h&]uh1jhjźubeh}(h]h ]h"]h$]h&]uh1j|hjhMhhjºubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMjhjubh)}(hPrepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.h]hPrepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMjhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dmc_resume (C function)c.intel_dmc_resumehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h5void intel_dmc_resume (struct intel_display *display)h]j2)}(h4void intel_dmc_resume(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjGhhhjYhMubjz)}(hintel_dmc_resumeh]j;)}(hintel_dmc_resumeh]hintel_dmc_resume}(hjlhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjGhhhjYhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjnsbc.intel_dmc_resumeasbuh1hhjubji)}(h h]h }(hjƻhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjԻhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjGhhhjYhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjChhhjYhMubah}(h]j>ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjYhMhj@hhubj1)}(hhh]h)}(h&init DMC firmware during system resumeh]h&init DMC firmware during system resume}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM~hjhhubah}(h]h ]h"]h$]h&]uh1j0hj@hhhjYhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj#jSj#jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Reinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().h](h)}(h**Parameters**h]jb)}(hj-h]h Parameters}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj+ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj'ubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjLh]hstruct intel_display *display}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjFubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahMhjbubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1j|hjahMhjCubah}(h]h ]h"]h$]h&]uh1jwhj'ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj'ubh)}(hnReinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().h]hnReinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dmc_fini (C function)c.intel_dmc_finihNtauh1jhjhhhNhNubj')}(hhh](j,)}(h3void intel_dmc_fini (struct intel_display *display)h]j2)}(h2void intel_dmc_fini(struct intel_display *display)h](j)}(hvoidh]hvoid}(hj̼hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȼhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMubji)}(h h]h }(hjۼhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjȼhhhjڼhMubjz)}(hintel_dmc_finih]j;)}(hintel_dmc_finih]hintel_dmc_fini}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjȼhhhjڼhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj'hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj)modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_finiasbuh1hhjubji)}(h h]h }(hjGhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjbhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjȼhhhjڼhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjļhhhjڼhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjڼhMhjhhubj1)}(hhh]h)}(hunload the DMC firmware.h]hunload the DMC firmware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjڼhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Firmmware unloading includes freeing the internal memory and reset the firmware loading status.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjͽh]hstruct intel_display *display}(hjϽhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj˽ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjǽubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjǽubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjĽubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubh)}(h_Firmmware unloading includes freeing the internal memory and reset the firmware loading status.h]h_Firmmware unloading includes freeing the internal memory and reset the firmware loading status.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]dmc-firmware-supportah ]h"]dmc firmware supportah$]h&]uh1hhj;hhhhhKnj referencedKubh)}(hhh](h)}(hDMC wakelock supporth]hDMC wakelock support}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhhhKubh)}(hXWake lock is the mechanism to cause display engine to exit DC states to allow programming to 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Wake lock is only required when DC5, DC6, or DC6v have been enabled in DC_STATE_EN and the wake lock mode of operation has been enabled.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:210: ./drivers/gpu/drm/i915/display/intel_dmc_wl.chKhj=hhubh)}(hXThe wakelock mechanism in DMC allows the display engine to exit DC states explicitly before programming registers that may be powered down. In earlier hardware, this was done automatically and implicitly when the display engine accessed a register. With the wakelock implementation, the driver asserts a wakelock in DMC, which forces it to exit the DC state until the wakelock is deasserted.h]hXThe wakelock mechanism in DMC allows the display engine to exit DC states explicitly before programming registers that may be powered down. In earlier hardware, this was done automatically and implicitly when the display engine accessed a register. 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The other definitions are here for potential future use.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:210: ./drivers/gpu/drm/i915/display/intel_dmc_wl.chK#hj=hhubeh}(h]dmc-wakelock-supportah ]h"]dmc wakelock supportah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hVideo BIOS Table (VBT)h]hVideo BIOS Table (VBT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX/The Video BIOS Table, or VBT, provides platform and board specific configuration information to the driver that is not discoverable or available through other means. The configuration is mostly related to display hardware. The VBT is available via the ACPI OpRegion or, on older systems, in the PCI ROM.h]hX/The Video BIOS Table, or VBT, provides platform and board specific configuration information to the driver that is not discoverable or available through other means. The configuration is mostly related to display hardware. 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The data blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of data. (Block 53, the MIPI Sequence Block is an exception.)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjʾhK5hjhhubh)}(hThe driver parses the VBT during load. The relevant information is stored in driver private data for ease of use, and the actual VBT is not read after that.h]hThe driver parses the VBT during load. The relevant information is stored in driver private data for ease of use, and the actual VBT is not read after that.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:216: ./drivers/gpu/drm/i915/display/intel_bios.chK=hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_bios_is_valid_vbt (C function)c.intel_bios_is_valid_vbthNtauh1jhjhhhNhNubj')}(hhh](j,)}(hZbool intel_bios_is_valid_vbt (struct intel_display *display, const void *buf, size_t size)h]j2)}(hYbool intel_bios_is_valid_vbt(struct intel_display *display, const void *buf, size_t size)h](j)}(hjh]hbool}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM ubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj-hM ubjz)}(hintel_bios_is_valid_vbth]j;)}(hintel_bios_is_valid_vbth]hintel_bios_is_valid_vbt}(hj@hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj<ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj-hM ubj)}(h=(struct intel_display *display, const void *buf, size_t size)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubji)}(h h]h }(hjihhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjXubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjzhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjwubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj|modnameN classnameNjXj[)}j^]ja)}jTjBsbc.intel_bios_is_valid_vbtasbuh1hhjXubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjXubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjXubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubj)}(hconst void *bufh](j)}(hjuh]hconst}(hjοhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʿubji)}(h h]h }(hjۿhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjʿubj)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʿubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjʿubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʿubj;)}(hbufh]hbuf}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjʿubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubj)}(h size_t sizeh](h)}(hhh]j;)}(hsize_th]hsize_t}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0modnameN classnameNjXj[)}j^]jc.intel_bios_is_valid_vbtasbuh1hhj'ubji)}(h h]h }(hjLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'ubj;)}(hsizeh]hsize}(hjZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj-hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj-hM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj-hM hjhhubj1)}(hhh]h)}(h)does the given buffer contain a valid VBTh]h)does the given buffer contain a valid VBT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj-hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display device ``const void *buf`` pointer to a buffer to validate ``size_t size`` size of the buffer **Description** Returns true on valid VBT.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubj})}(h4``const void *buf`` pointer to a buffer to validate h](j)}(h``const void *buf``h]j)}(hjh]hconst void *buf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubj)}(hhh]h)}(hpointer to a buffer to validateh]hpointer to a buffer to validate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubj})}(h#``size_t size`` size of the buffer h](j)}(h``size_t size``h]j)}(hj7h]h size_t size}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hj1ubj)}(hhh]h)}(hsize of the bufferh]hsize of the buffer}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM hjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1j|hjLhM hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjrh]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjpubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubh)}(hReturns true on valid VBT.h]hReturns true on valid VBT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_bios_init (C function)c.intel_bios_inithNtauh1jhjhhhNhNubj')}(hhh](j,)}(h4void intel_bios_init (struct intel_display *display)h]j2)}(h3void intel_bios_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chML ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhML ubjz)}(hintel_bios_inith]j;)}(hintel_bios_inith]hintel_bios_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhML ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_bios_initasbuh1hhjubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjMhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhML ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhML ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhML hjhhubj1)}(hhh]h)}(h.find VBT and initialize settings from the BIOSh]h.find VBT and initialize settings from the BIOS}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chME hjthhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhML ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX)**Parameters** ``struct intel_display *display`` display device instance **Description** Parse and initialize settings from the Video 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Also initialize some defaults if the VBT is not present at all.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMI hjubjx)}(hhh]j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMF hjubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMF hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMF hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMH hjubh)}(hParse and initialize settings from the Video BIOS Tables (VBT). If the VBT was not found in ACPI OpRegion, try to find it in PCI ROM first. Also initialize some defaults if the VBT is not present at all.h]hParse and initialize settings from the Video BIOS Tables (VBT). If the VBT was not found in ACPI OpRegion, try to find it in PCI ROM first. Also initialize some defaults if the VBT is not present at all.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMH hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_bios_driver_remove (C function)c.intel_bios_driver_removehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h=void intel_bios_driver_remove (struct intel_display *display)h]j2)}(h` from beginning of VBT ``aim_offset`` Offsets of add-in data blocks from beginning of VBTh](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhK[hjubj")}(hstruct vbt_header { u8 signature[20]; u16 version; u16 header_size; u16 vbt_size; u8 vbt_checksum; u8 reserved0; u32 bdb_offset; u32 aim_offset[4]; };h]hstruct vbt_header { u8 signature[20]; u16 version; u16 header_size; u16 vbt_size; u8 vbt_checksum; u8 reserved0; u32 bdb_offset; u32 aim_offset[4]; };}hj sbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhK]hjubh)}(h **Members**h]jb)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhKhhjubjx)}(hhh](j})}(h7``signature`` VBT signature, always starts with "$VBT" h](j)}(h ``signature``h]j)}(hj9h]h signature}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhKYhj3ubj)}(hhh]h)}(h(VBT signature, always starts with "$VBT"h]h,VBT signature, always starts with “$VBT”}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhKYhjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j|hjNhKYhj0ubj})}(h&``version`` Version of this structure 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./drivers/gpu/drm/i915/display/intel_vbt_defs.hhK^hjPubj)}(hhh]h)}(hReservedh]hReserved}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhK^hjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j|hjkhK^hj0ubj})}(hX``bdb_offset`` Offset of :c:type:`struct bdb_header ` from beginning of VBT h](j)}(h``bdb_offset``h]j)}(hjh]h bdb_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhK_hjubj)}(hhh]h)}(hHOffset of :c:type:`struct bdb_header ` from beginning of VBTh](h Offset of }(hjhhhNhNubh)}(h(:c:type:`struct bdb_header `h]j)}(hjh]hstruct bdb_header}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjj bdb_headeruh1hhjhK_hjubh from beginning of VBT}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK_hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK_hj0ubj})}(hB``aim_offset`` Offsets of add-in data blocks from beginning of VBTh](j)}(h``aim_offset``h]j)}(hjh]h aim_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhK_hjubj)}(hhh]h)}(h3Offsets of add-in data blocks from beginning of VBTh]h3Offsets of add-in data blocks from beginning of VBT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhK`hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK_hj0ubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"bdb_header (C struct) c.bdb_headerhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h bdb_headerh]j2)}(hstruct bdb_headerh](j)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhKfubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAhhhjRhKfubjz)}(h bdb_headerh]j;)}(hj?h]h bdb_header}(hjehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjaubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjAhhhjRhKfubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj=hhhjRhKfubah}(h]j8ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjRhKfhj:hhubj1)}(hhh]h)}(hBDB Header structureh]hBDB Header structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhKmhjhhubah}(h]h ]h"]h$]h&]uh1j0hj:hhhjRhKfubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXX**Definition**:: struct bdb_header { u8 signature[16]; u16 version; u16 header_size; u16 bdb_size; }; **Members** ``signature`` BDB signature "BIOS_DATA_BLOCK" ``version`` Version of the data block definitions ``header_size`` Size of this structure ``bdb_size`` Size of BDB (BDB Header and data blocks)h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:}(hjhhhNhNubeh}(h]h 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“BIOS_DATA_BLOCK”}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKohj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hKohjubj})}(h2``version`` Version of the data block definitions h](j)}(h ``version``h]j)}(hj-h]hversion}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhKphj'ubj)}(hhh]h)}(h%Version of the data block definitionsh]h%Version of the data block definitions}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhKphjCubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1j|hjBhKphjubj})}(h'``header_size`` Size of this structure h](j)}(h``header_size``h]j)}(hjfh]h header_size}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhKqhj`ubj)}(hhh]h)}(hSize of this structureh]hSize of this structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hKqhj|ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1j|hj{hKqhjubj})}(h5``bdb_size`` Size of BDB (BDB Header and data blocks)h](j)}(h ``bdb_size``h]j)}(hjh]hbdb_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhKqhjubj)}(hhh]h)}(h(Size of BDB (BDB Header and data blocks)h]h(Size of BDB (BDB Header and data blocks)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_vbt_defs.hhKrhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKqhjubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]video-bios-table-vbtah ]h"]video bios table (vbt)ah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hDisplay clocksh]hDisplay clocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXThe display engine uses several different clocks to do its work. There are two main clocks involved that aren't directly related to the actual pixel clock or any symbol/bit clock of the actual output port. These are the core display clock (CDCLK) and RAWCLK.h]hXThe display engine uses several different clocks to do its work. There are two main clocks involved that aren’t directly related to the actual pixel clock or any symbol/bit clock of the actual output port. These are the core display clock (CDCLK) and RAWCLK.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chK5hjhhubh)}(hCDCLK clocks most of the display pipe logic, and thus its frequency must be high enough to support the rate at which pixels are flowing through the pipes. Downscaling must also be accounted as that increases the effective pixel rate.h]hCDCLK clocks most of the display pipe logic, and thus its frequency must be high enough to support the rate at which pixels are flowing through the pipes. Downscaling must also be accounted as that increases the effective pixel rate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chK:hjhhubh)}(hXOn several platforms the CDCLK frequency can be changed dynamically to minimize power consumption for a given display configuration. Typically changes to the CDCLK frequency require all the display pipes to be shut down while the frequency is being changed.h]hXOn several platforms the CDCLK frequency can be changed dynamically to minimize power consumption for a given display configuration. Typically changes to the CDCLK frequency require all the display pipes to be shut down while the frequency is being changed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chK?hjhhubh)}(hOn SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. DMC will not change the active CDCLK frequency however, so that part will still be performed by the driver directly.h]hOn SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. DMC will not change the active CDCLK frequency however, so that part will still be performed by the driver directly.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKDhjhhubh)}(hPThere are multiple components involved in the generation of the CDCLK frequency:h]hPThere are multiple components involved in the generation of the CDCLK frequency:}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKHhjhhubj:)}(hhh](j:)}(hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.h]h)}(hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.h]hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKKhjGubah}(h]h ]h"]h$]h&]uh1j:hjDubj:)}(htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.h]h)}(htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.h]htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKMhj`ubah}(h]h ]h"]h$]h&]uh1j:hjDubj:)}(hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero "squashes out" a clock cycle.h]h)}(hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero "squashes out" a clock cycle.h]hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero “squashes out” a clock cycle.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKOhjyubah}(h]h ]h"]h$]h&]uh1j:hjDubj:)}(hFAnd, finally, a fixed divider that divides the output frequency by 2. h]h)}(hEAnd, finally, a fixed divider that divides the output frequency by 2.h]hEAnd, finally, a fixed divider that divides the output frequency by 2.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKRhjubah}(h]h ]h"]h$]h&]uh1j:hjDubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjYhKKhjhhubh)}(hTAs such, the resulting CDCLK frequency can be calculated with the following formula:h]hTAs such, the resulting CDCLK frequency can be calculated with the following formula:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKThjhhubjL)}(h/cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 h]h)}(h.cdclk = vco / cd2x_div / (sq_len / sq_div) / 2h]h.cdclk = vco / cd2x_div / (sq_len / sq_div) / 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKWhjubah}(h]h ]h"]h$]h&]uh1jKhjhKWhjhhubh)}(h, where vco is the frequency generated by the PLL; cd2x_div represents the CD2X Divider; sq_len and sq_div are the bit length and the number of high bits for the CD2X Squasher waveform, respectively; and 2 represents the fixed divider.h]h, where vco is the frequency generated by the PLL; cd2x_div represents the CD2X Divider; sq_len and sq_div are the bit length and the number of high bits for the CD2X Squasher waveform, respectively; and 2 represents the fixed divider.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKYhjhhubh)}(hNote that some older platforms do not contain the CD2X Divider and/or CD2X Squasher, in which case we can ignore their respective factors in the formula above.h]hNote that some older platforms do not contain the CD2X Divider and/or CD2X Squasher, in which case we can ignore their respective factors in the formula above.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chK^hjhhubh)}(hfSeveral methods exist to change the CDCLK frequency, which ones are supported depends on the platform:h]hfSeveral methods exist to change the CDCLK frequency, which ones are supported depends on the platform:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKbhjhhubj:)}(hhh](j:)}(hLFull PLL disable + re-enable with new VCO frequency. Pipes must be inactive.h]h)}(hj h]hLFull PLL disable + re-enable with new VCO frequency. Pipes must be inactive.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKehj ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hyCD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe's start of vblank.h]h)}(hyCD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe's start of vblank.h]h{CD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe’s start of vblank.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKfhj!ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hECrawl the PLL smoothly to the new VCO frequency. Pipes can be active.h]h)}(hj<h]hECrawl the PLL smoothly to the new VCO frequency. Pipes can be active.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKhhj:ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h,Squash waveform update. Pipes can be active.h]h)}(hjTh]h,Squash waveform update. Pipes can be active.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKihjRubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hECrawl and squash can also be done back to back. Pipes can be active. h]h)}(hDCrawl and squash can also be done back to back. Pipes can be active.h]hDCrawl and squash can also be done back to back. Pipes can be active.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKjhjjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKehjhhubh)}(hRAWCLK is a fixed frequency clock, often used by various auxiliary blocks such as AUX CH or backlight PWM. Hence the only thing we really need to know about RAWCLK is its frequency so that various dividers can be programmed correctly.h]hRAWCLK is a fixed frequency clock, often used by various auxiliary blocks such as AUX CH or backlight PWM. Hence the only thing we really need to know about RAWCLK is its frequency so that various dividers can be programmed correctly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKlhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_cdclk_init_hw (C function)c.intel_cdclk_init_hwhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h8void intel_cdclk_init_hw (struct intel_display *display)h]j2)}(h7void intel_cdclk_init_hw(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_cdclk_init_hwh]j;)}(hintel_cdclk_init_hwh]hintel_cdclk_init_hw}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_cdclk_init_hwasbuh1hhjubji)}(h h]h }(hj,hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjGhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(hInitialize CDCLK hardwareh]hInitialize CDCLK hardware}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjnhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXf**Parameters** ``struct intel_display *display`` display instance **Description** Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh)}(hXInitialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.h]hXInitialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_cdclk_uninit_hw (C function)c.intel_cdclk_uninit_hwhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h:void intel_cdclk_uninit_hw (struct intel_display *display)h]j2)}(h9void intel_cdclk_uninit_hw(struct intel_display *display)h](j)}(hvoidh]hvoid}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.hhhj@hM ubjz)}(hintel_cdclk_uninit_hwh]j;)}(hintel_cdclk_uninit_hwh]hintel_cdclk_uninit_hw}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjOubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj.hhhj@hM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubji)}(h h]h }(hj|hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjkubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjUsbc.intel_cdclk_uninit_hwasbuh1hhjkubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjkubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjkubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjgubah}(h]h ]h"]h$]h&]jjuh1jhj.hhhj@hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj*hhhj@hM ubah}(h]j%ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj@hM hj'hhubj1)}(hhh]h)}(hUninitialize CDCLK hardwareh]hUninitialize CDCLK hardware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hj'hhhj@hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Uninitialize CDCLK. This is done only during the display core uninitialization sequence.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj3h]hstruct intel_display *display}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj-ubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhM hjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1j|hjHhM hj*ubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjnh]h Description}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jahjlubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh)}(hXUninitialize CDCLK. This is done only during the display core uninitialization sequence.h]hXUninitialize CDCLK. This is done only during the display core uninitialization sequence.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_cdclk_clock_changed (C function)c.intel_cdclk_clock_changedhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hgbool intel_cdclk_clock_changed (const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j2)}(hfbool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMh ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMh ubjz)}(hintel_cdclk_clock_changedh]j;)}(hintel_cdclk_clock_changedh]hintel_cdclk_clock_changed}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMh ubj)}(hH(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(h"const struct intel_cdclk_config *ah](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj*modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_cdclk_clock_changedasbuh1hhjubji)}(h h]h }(hjHhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hah]ha}(hjchhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h"const struct intel_cdclk_config *bh](j)}(hjuh]hconst}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jDc.intel_cdclk_clock_changedasbuh1hhjxubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj;)}(hbh]hb}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjxubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMh ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMh ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMh hjhhubj1)}(hhh]h)}(hCheck whether the clock changedh]hCheck whether the clock changed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM` hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMh ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj0jSj0jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if CDCLK changed in a way that requires re-programming and False otherwise.h](h)}(h**Parameters**h]jb)}(hj:h]h Parameters}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj8ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMd hj4ubjx)}(hhh](j})}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hjYh]h"const struct intel_cdclk_config *a}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMa hjSubj)}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMa hjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1j|hjnhMa hjPubj})}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hjh]h"const struct intel_cdclk_config *b}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMb hjubj)}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMb hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMb hjPubeh}(h]h ]h"]h$]h&]uh1jwhj4ubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMd hj4ubh)}(hPTrue if CDCLK changed in a way that requires re-programming and False otherwise.h]hPTrue if CDCLK changed in a way that requires re-programming and False otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMd hj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"(intel_cdclk_can_cd2x_update (C function)c.intel_cdclk_can_cd2x_updatehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hbool intel_cdclk_can_cd2x_update (struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j2)}(hbool intel_cdclk_can_cd2x_update(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM{ ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM{ ubjz)}(hintel_cdclk_can_cd2x_updateh]j;)}(hintel_cdclk_can_cd2x_updateh]hintel_cdclk_can_cd2x_update}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM{ ubj)}(hg(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubji)}(h h]h }(hj[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjlhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjiubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjnmodnameN classnameNjXj[)}j^]ja)}jTj4sbc.intel_cdclk_can_cd2x_updateasbuh1hhjJubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjJubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjFubj)}(h"const struct intel_cdclk_config *ah](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_cdclk_can_cd2x_updateasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hjeh]ha}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjFubj)}(h"const struct intel_cdclk_config *bh](j)}(hjuh]hconst}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjFubj)}(hjh]hstruct}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjFubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_cdclk_can_cd2x_updateasbuh1hhjFubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjFubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubj;)}(hjh]hb}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjFubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM{ ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhjhM{ ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM{ hjhhubj1)}(hhh]h)}(h^Determine if changing between the two CDCLK configurations requires only a cd2x divider updateh]h^Determine if changing between the two CDCLK configurations requires only a cd2x divider update}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMq hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM{ ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXK**Parameters** ``struct intel_display *display`` display instance ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMu hjubjx)}(hhh](j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj&h]hstruct intel_display *display}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMs hj ubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMs hj<ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj;hMs hjubj})}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hj_h]h"const struct intel_cdclk_config *a}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMt hjYubj)}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMt hjuubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1j|hjthMt hjubj})}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hjh]h"const struct intel_cdclk_config *b}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMu hjubj)}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMu hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMu hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMw hjubh)}(hpTrue if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.h]hpTrue if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMw hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_cdclk_changed (C function)c.intel_cdclk_changedhNtauh1jhjhhhNhNubj')}(hhh](j,)}(habool intel_cdclk_changed (const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j2)}(h`bool intel_cdclk_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hj&hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj%hM ubjz)}(hintel_cdclk_changedh]j;)}(hintel_cdclk_changedh]hintel_cdclk_changed}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj4ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj%hM ubj)}(hH(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(h"const struct intel_cdclk_config *ah](j)}(hjuh]hconst}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjPubj)}(hjh]hstruct}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubji)}(h h]h }(hj|hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjPubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTj:sbc.intel_cdclk_changedasbuh1hhjPubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjPubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubj;)}(hjeh]ha}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjPubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjLubj)}(h"const struct intel_cdclk_config *bh](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_cdclk_changedasbuh1hhjubji)}(h h]h }(hj7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hjh]hb}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjLubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj%hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj%hM ubah}(h]j ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj%hM hj hhubj1)}(hhh]h)}(h3Determine if two CDCLK configurations are differenth]h3Determine if two CDCLK configurations are different}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjxhhubah}(h]h ]h"]h$]h&]uh1j0hj hhhj%hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if the CDCLK configurations don't match, false if they do.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubjx)}(hhh](j})}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hjh]h"const struct intel_cdclk_config *a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubj})}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hjh]h"const struct intel_cdclk_config *b}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hM hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h **Return**h]jb)}(hj0h]hReturn}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj.ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh)}(h?True if the CDCLK configurations don't match, false if they do.h]hATrue if the CDCLK configurations don’t match, false if they do.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"-intel_set_cdclk_pre_plane_update (C function)"c.intel_set_cdclk_pre_plane_updatehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hHvoid intel_set_cdclk_pre_plane_update (struct intel_atomic_state *state)h]j2)}(hGvoid intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)h](j)}(hvoidh]hvoid}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMl ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqhhhjhMl ubjz)}(h intel_set_cdclk_pre_plane_updateh]j;)}(h intel_set_cdclk_pre_plane_updateh]h intel_set_cdclk_pre_plane_update}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjqhhhjhMl ubj)}(h"(struct intel_atomic_state *state)h]j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb"c.intel_set_cdclk_pre_plane_updateasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hstateh]hstate}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjqhhhjhMl ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjmhhhjhMl ubah}(h]jhah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMl hjjhhubj1)}(hhh]h)}(h$Push the CDCLK state to the hardwareh]h$Push the CDCLK state to the hardware}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMf hj2hhubah}(h]h ]h"]h$]h&]uh1j0hjjhhhjhMl ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjMjSjMjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_atomic_state *state`` intel atomic state **Description** Program the hardware before updating the HW plane state based on the new CDCLK state, if necessary.h](h)}(h**Parameters**h]jb)}(hjWh]h Parameters}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjUubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMj hjQubjx)}(hhh]j})}(h8``struct intel_atomic_state *state`` intel atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjvh]h struct intel_atomic_state *state}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMg hjpubj)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMg hjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1j|hjhMg hjmubah}(h]h ]h"]h$]h&]uh1jwhjQubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMi hjQubh)}(hcProgram the hardware before updating the HW plane state based on the new CDCLK state, if necessary.h]hcProgram the hardware before updating the HW plane state based on the new CDCLK state, if necessary.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMi hjQubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j".intel_set_cdclk_post_plane_update (C function)#c.intel_set_cdclk_post_plane_updatehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hIvoid intel_set_cdclk_post_plane_update (struct intel_atomic_state *state)h]j2)}(hHvoid intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(h!intel_set_cdclk_post_plane_updateh]j;)}(h!intel_set_cdclk_post_plane_updateh]h!intel_set_cdclk_post_plane_update}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h"(struct intel_atomic_state *state)h]j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubji)}(h h]h }(hj@hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/ubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjSmodnameN classnameNjXj[)}j^]ja)}jTjsb#c.intel_set_cdclk_post_plane_updateasbuh1hhj/ubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj;)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h$Push the CDCLK state to the hardwareh]h$Push the CDCLK state to the hardware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_atomic_state *state`` intel atomic state **Description** Program the hardware after updating the HW plane state based on the new CDCLK state, if necessary.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubjx)}(hhh]j})}(h8``struct intel_atomic_state *state`` intel atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hM hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj2h]h Description}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj0ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh)}(hbProgram the hardware after updating the HW plane state based on the new CDCLK state, if necessary.h]hbProgram the hardware after updating the HW plane state based on the new CDCLK state, if necessary.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_update_max_cdclk (C function)c.intel_update_max_cdclkhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h;void intel_update_max_cdclk (struct intel_display *display)h]j2)}(h:void intel_update_max_cdclk(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjshhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM< ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjshhhjhM< ubjz)}(hintel_update_max_cdclkh]j;)}(hintel_update_max_cdclkh]hintel_update_max_cdclk}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjshhhjhM< ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_update_max_cdclkasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjshhhjhM< ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjohhhjhM< ubah}(h]jjah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM< hjlhhubj1)}(hhh]h)}(h-Determine the maximum support CDCLK frequencyh]h-Determine the maximum support CDCLK frequency}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM5 hj4hhubah}(h]h ]h"]h$]h&]uh1j0hjlhhhjhM< ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjOjSjOjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Determine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.h](h)}(h**Parameters**h]jb)}(hjYh]h Parameters}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjWubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM9 hjSubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjxh]hstruct intel_display *display}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM6 hjrubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM6 hjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1j|hjhM6 hjoubah}(h]h ]h"]h$]h&]uh1jwhjSubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM8 hjSubh)}(hDetermine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.h]hDetermine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM8 hjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_update_cdclk (C function)c.intel_update_cdclkhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h7void intel_update_cdclk (struct intel_display *display)h]j2)}(h6void intel_update_cdclk(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_update_cdclkh]j;)}(hintel_update_cdclkh]hintel_update_cdclk}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubji)}(h h]h }(hjBhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj1ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjPubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjUmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_update_cdclkasbuh1hhj1ubji)}(h h]h }(hjshhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj1ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj1ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj-ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h%Determine the current CDCLK frequencyh]h%Determine the current CDCLK frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h}**Parameters** ``struct intel_display *display`` display instance **Description** Determine the current CDCLK frequency.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjuba h}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj4h]h Description}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj2ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh)}(h&Determine the current CDCLK frequency.h]h&Determine the current CDCLK frequency.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_read_rawclk (C function)c.intel_read_rawclkhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h5u32 intel_read_rawclk (struct intel_display *display)h]j2)}(h4u32 intel_read_rawclk(struct intel_display *display)h](h)}(hhh]j;)}(hu32h]hu32}(hj|hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjyubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj~modnameN classnameNjXj[)}j^]ja)}jTintel_read_rawclksbc.intel_read_rawclkasbuh1hhjuhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuhhhjhM ubjz)}(hintel_read_rawclkh]j;)}(hjh]hintel_read_rawclk}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjuhhhjhM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_read_rawclkasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj"hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjuhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjqhhhjhM ubah}(h]jlah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjnhhubj1)}(hhh]h)}(h&Determine the current RAWCLK frequencyh]h&Determine the current RAWCLK frequency}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjIhhubah}(h]h ]h"]h$]h&]uh1j0hjnhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjdjSjdjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Determine the current RAWCLK frequency. RAWCLK is a fixed frequency clock so this needs to done only once.h](h)}(h**Parameters**h]jb)}(hjnh]h Parameters}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jahjlubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjhubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubah}(h]h ]h"]h$]h&]uh1jwhjhubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjhubh)}(hjDetermine the current RAWCLK frequency. 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While some have per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL from a pool. In the latter scenario, it is possible that multiple pipes share a PLL if their configurations match.h]hXDisplay PLLs used for driving outputs vary by platform. While some have per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL from a pool. In the latter scenario, it is possible that multiple pipes share a PLL if their configurations match.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:237: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chK,hjWhhubh)}(hXcThis file provides an abstraction over display PLLs. The function intel_shared_dpll_init() initializes the PLLs for the given platform. The users of a PLL are tracked and that tracking is integrated with the atomic modset interface. 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Changes to the users are first staged in the atomic state, and then made effective by calling intel_shared_dpll_swap_state() during the atomic commit phase.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:237: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chK1hjWhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"(intel_get_shared_dpll_by_id (C function)c.intel_get_shared_dpll_by_idhNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hmstruct intel_shared_dpll * intel_get_shared_dpll_by_id (struct intel_display *display, enum intel_dpll_id id)h]j2)}(hkstruct intel_shared_dpll *intel_get_shared_dpll_by_id(struct intel_display *display, enum intel_dpll_id id)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTintel_get_shared_dpll_by_idsbc.intel_get_shared_dpll_by_idasbuh1hhjhhhjhKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubjz)}(hintel_get_shared_dpll_by_idh]j;)}(hjh]hintel_get_shared_dpll_by_id}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubj)}(h6(struct intel_display *display, enum intel_dpll_id id)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj&hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj4ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj9modnameN classnameNjXj[)}j^]jc.intel_get_shared_dpll_by_idasbuh1hhjubji)}(h h]h }(hjUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjphhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(henum intel_dpll_id idh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_dpll_idh]h intel_dpll_id}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_get_shared_dpll_by_idasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hidh]hid}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(hget a DPLL given its idh]hget a DPLL given its id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(h**Parameters** ``struct intel_display *display`` intel_display device instance ``enum intel_dpll_id id`` pll id **Return** A pointer to the DPLL with **id**h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubjx)}(hhh](j})}(h@``struct intel_display *display`` intel_display device instance h](j)}(h!``struct intel_display *display``h]j)}(hj>h]hstruct intel_display *display}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhj8ubj)}(hhh]h)}(hintel_display device instanceh]hintel_display device instance}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShKhjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1j|hjShKhj5ubj})}(h!``enum intel_dpll_id id`` pll id h](j)}(h``enum intel_dpll_id id``h]j)}(hjwh]henum intel_dpll_id id}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjqubj)}(hhh]h)}(hpll idh]hpll id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj5ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubh)}(h!A pointer to the DPLL with **id**h](hA pointer to the DPLL with }(hjhhhNhNubjb)}(h**id**h]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_enable_shared_dpll (C function)c.intel_enable_shared_dpllhNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hIvoid intel_enable_shared_dpll (const struct intel_crtc_state *crtc_state)h]j2)}(hHvoid intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(hintel_enable_shared_dpllh]j;)}(hintel_enable_shared_dpllh]hintel_enable_shared_dpll}(hj&hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjuh]hconst}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubji)}(h h]h }(hjOhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>ubj)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubji)}(h h]h }(hjjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>ubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hj{hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjxubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj}modnameN classnameNjXj[)}j^]ja)}jTj(sbc.intel_enable_shared_dpllasbuh1hhj>ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj:ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(henable a CRTC's shared DPLLh]henable a CRTC’s shared DPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL **Description** Enable the shared DPLL used by **crtc**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubjx)}(hhh]j})}(h[``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hj!h]h)const struct intel_crtc_state *crtc_state}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubj)}(hhh]h)}(h,CRTC, and its state, which has a shared DPLLh]h,CRTC, and its state, which has a shared DPLL}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hKhj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj6hKhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj\h]h Description}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubh)}(h(Enable the shared DPLL used by **crtc**.h](hEnable the shared DPLL used by }(hjrhhhNhNubjb)}(h**crtc**h]hcrtc}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjrubh.}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_disable_shared_dpll (C function)c.intel_disable_shared_dpllhNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hJvoid intel_disable_shared_dpll (const struct intel_crtc_state *crtc_state)h]j2)}(hIvoid intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM-ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM-ubjz)}(hintel_disable_shared_dpllh]j;)}(hintel_disable_shared_dpllh]hintel_disable_shared_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM-ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hj)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj&ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj+modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_disable_shared_dpllasbuh1hhjubji)}(h h]h }(hjIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hjdhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM-ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM-ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM-hjhhubj1)}(hhh]h)}(hdisable a CRTC's shared DPLLh]hdisable a CRTC’s shared DPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM(hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM-ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL **Description** Disable the shared DPLL used by **crtc**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM,hjubjx)}(hhh]j})}(h[``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM)hjubj)}(hhh]h)}(h,CRTC, and its state, which has a shared DPLLh]h,CRTC, and its state, which has a shared DPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM)hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM+hjubh)}(h)Disable the shared DPLL used by **crtc**.h](h Disable the shared DPLL used by }(hj hhhNhNubjb)}(h**crtc**h]hcrtc}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM+hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"-intel_reference_shared_dpll_crtc (C function)"c.intel_reference_shared_dpll_crtchNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hvoid intel_reference_shared_dpll_crtc (const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h]j2)}(hvoid intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h](j)}(hvoidh]hvoid}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjphhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]hhhjohMubjz)}(h intel_reference_shared_dpll_crtch]j;)}(h intel_reference_shared_dpll_crtch]h intel_reference_shared_dpll_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj]hhhjohMubj)}(hw(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h](j)}(hconst struct intel_crtc *crtch](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb"c.intel_reference_shared_dpll_crtcasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h#const struct intel_shared_dpll *pllh](j)}(hjuh]hconst}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'ubj)}(hjh]hstruct}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'ubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hjdhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjaubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjfmodnameN classnameNjXj[)}j^]j"c.intel_reference_shared_dpll_crtcasbuh1hhj'ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj;)}(hpllh]hpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h1struct intel_shared_dpll_state *shared_dpll_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_shared_dpll_stateh]hintel_shared_dpll_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j"c.intel_reference_shared_dpll_crtcasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hshared_dpll_stateh]hshared_dpll_state}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhj]hhhjohMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjYhhhjohMubah}(h]jTah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjohMhjVhhubj1)}(hhh]h)}(hGet a DPLL reference for a CRTCh]hGet a DPLL reference for a CRTC}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj4hhubah}(h]h ]h"]h$]h&]uh1j0hjVhhhjohMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjOjSjOjTjUjVuh1j&hhhjWhNhNubjX)}(hXt**Parameters** ``const struct intel_crtc *crtc`` CRTC on which behalf the reference is taken ``const struct intel_shared_dpll *pll`` DPLL for which the reference is taken ``struct intel_shared_dpll_state *shared_dpll_state`` the DPLL atomic state in which the reference is tracked **Description** Take a reference for **pll** tracking the use of it by **crtc**.h](h)}(h**Parameters**h]jb)}(hjYh]h Parameters}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjWubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjSubjx)}(hhh](j})}(hN``const struct intel_crtc *crtc`` CRTC on which behalf the reference is taken h](j)}(h!``const struct intel_crtc *crtc``h]j)}(hjxh]hconst struct intel_crtc *crtc}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjrubj)}(hhh]h)}(h+CRTC on which behalf the reference is takenh]h+CRTC on which behalf the reference is taken}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjoubj})}(hN``const struct intel_shared_dpll *pll`` DPLL for which the reference is taken h](j)}(h'``const struct intel_shared_dpll *pll``h]j)}(hjh]h#const struct intel_shared_dpll *pll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h%DPLL for which the reference is takenh]h%DPLL for which the reference is taken}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjoubj})}(hn``struct intel_shared_dpll_state *shared_dpll_state`` the DPLL atomic state in which the reference is tracked h](j)}(h5``struct intel_shared_dpll_state *shared_dpll_state``h]j)}(hjh]h1struct intel_shared_dpll_state *shared_dpll_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h7the DPLL atomic state in which the reference is trackedh]h7the DPLL atomic state in which the reference is tracked}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjoubeh}(h]h ]h"]h$]h&]uh1jwhjSubh)}(h**Description**h]jb)}(hj%h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjSubh)}(h@Take a reference for **pll** tracking the use of it by **crtc**.h](hTake a reference for }(hj;hhhNhNubjb)}(h**pll**h]hpll}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jahj;ubh tracking the use of it by }(hj;hhhNhNubjb)}(h**crtc**h]hcrtc}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj;ubh.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"/intel_unreference_shared_dpll_crtc (C function)$c.intel_unreference_shared_dpll_crtchNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hvoid intel_unreference_shared_dpll_crtc (const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h]j2)}(hvoid intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(h"intel_unreference_shared_dpll_crtch]j;)}(h"intel_unreference_shared_dpll_crtch]h"intel_unreference_shared_dpll_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(hw(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h](j)}(hconst struct intel_crtc *crtch](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb$c.intel_unreference_shared_dpll_crtcasbuh1hhjubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hj?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h#const struct intel_shared_dpll *pllh](j)}(hjuh]hconst}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubji)}(h h]h }(hjehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubj)}(hjh]hstruct}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j $c.intel_unreference_shared_dpll_crtcasbuh1hhjTubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubj;)}(hpllh]hpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjTubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h1struct intel_shared_dpll_state *shared_dpll_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_shared_dpll_stateh]hintel_shared_dpll_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j $c.intel_unreference_shared_dpll_crtcasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hshared_dpll_stateh]hshared_dpll_state}(hj:hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h Drop a DPLL reference for a CRTCh]h Drop a DPLL reference for a CRTC}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjahhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj|jSj|jTjUjVuh1j&hhhjWhNhNubjX)}(hX**Parameters** ``const struct intel_crtc *crtc`` CRTC on which behalf the reference is dropped ``const struct intel_shared_dpll *pll`` DPLL for which the reference is dropped ``struct intel_shared_dpll_state *shared_dpll_state`` the DPLL atomic state in which the reference is tracked **Description** Drop a reference for **pll** tracking the end of use of it by **crtc**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(hP``const struct intel_crtc *crtc`` CRTC on which behalf the reference is dropped h](j)}(h!``const struct intel_crtc *crtc``h]j)}(hjh]hconst struct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h-CRTC on which behalf the reference is droppedh]h-CRTC on which behalf the reference is dropped}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hP``const struct intel_shared_dpll *pll`` DPLL for which the reference is dropped h](j)}(h'``const struct intel_shared_dpll *pll``h]j)}(hjh]h#const struct intel_shared_dpll *pll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h'DPLL for which the reference is droppedh]h'DPLL for which the reference is dropped}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hn``struct intel_shared_dpll_state *shared_dpll_state`` the DPLL atomic state in which the reference is tracked h](j)}(h5``struct intel_shared_dpll_state *shared_dpll_state``h]j)}(hjh]h1struct intel_shared_dpll_state *shared_dpll_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h7the DPLL atomic state in which the reference is trackedh]h7the DPLL atomic state in which the reference is tracked}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj,hMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjRh]h Description}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jahjPubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hGDrop a reference for **pll** tracking the end of use of it by **crtc**.h](hDrop a reference for }(hjhhhhNhNubjb)}(h**pll**h]hpll}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jahjhubh" tracking the end of use of it by }(hjhhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjhubh.}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_shared_dpll_swap_state (C function)c.intel_shared_dpll_swap_statehNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hDvoid intel_shared_dpll_swap_state (struct intel_atomic_state *state)h]j2)}(hCvoid intel_shared_dpll_swap_state(struct intel_atomic_state *state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_shared_dpll_swap_stateh]j;)}(hintel_shared_dpll_swap_stateh]hintel_shared_dpll_swap_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h"(struct intel_atomic_state *state)h]j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_shared_dpll_swap_stateasbuh1hhjubji)}(h h]h }(hj6hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hstateh]hstate}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h(make atomic DPLL configuration effectiveh]h(make atomic DPLL configuration effective}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjxhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state **Description** This is the dpll version of drm_atomic_helper_swap_state() since the helper does not handle driver-specific global state. For consistency with atomic helpers this function does a complete swap, i.e. it also puts the current state into **state**, even though there is no need for that at this moment.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh]j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hyThis is the dpll version of drm_atomic_helper_swap_state() since the helper does not handle driver-specific global state.h]hyThis is the dpll version of drm_atomic_helper_swap_state() since the helper does not handle driver-specific global state.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hFor consistency with atomic helpers this function does a complete swap, i.e. it also puts the current state into **state**, even though there is no need for that at this moment.h](hqFor consistency with atomic helpers this function does a complete swap, i.e. it also puts the current state into }(hjhhhNhNubjb)}(h **state**h]hstate}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh7, even though there is no need for that at this moment.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%icl_set_active_port_dpll (C function)c.icl_set_active_port_dpllhNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hgvoid icl_set_active_port_dpll (struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id)h]j2)}(hfvoid icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id)h](j)}(hvoidh]hvoid}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM ubji)}(h h]h }(hjlhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYhhhjkhM ubjz)}(hicl_set_active_port_dpllh]j;)}(hicl_set_active_port_dpllh]hicl_set_active_port_dpll}(hj~hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjYhhhjkhM ubj)}(hI(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id)h](j)}(h#struct intel_crtc_state *crtc_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.icl_set_active_port_dpllasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h"enum icl_port_dpll_id port_dpll_idh](j)}(hjh]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hicl_port_dpll_idh]hicl_port_dpll_id}(hj*hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj,modnameN classnameNjXj[)}j^]jc.icl_set_active_port_dpllasbuh1hhjubji)}(h h]h }(hjHhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h port_dpll_idh]h port_dpll_id}(hjVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjYhhhjkhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjUhhhjkhM ubah}(h]jPah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjkhM hjRhhubj1)}(hhh]h)}(h,select the active port DPLL for a given CRTCh]h,select the active port DPLL for a given CRTC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hj}hhubah}(h]h ]h"]h$]h&]uh1j0hjRhhhjkhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hX**Parameters** ``struct intel_crtc_state *crtc_state`` state for the CRTC to select the DPLL for ``enum icl_port_dpll_id port_dpll_id`` the active **port_dpll_id** to select **Description** Select the given **port_dpll_id** instance from the DPLLs reserved for the CRTC.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubjx)}(hhh](j})}(hR``struct intel_crtc_state *crtc_state`` state for the CRTC to select the DPLL for h](j)}(h'``struct intel_crtc_state *crtc_state``h]j)}(hjh]h#struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubj)}(hhh]h)}(h)state for the CRTC to select the DPLL forh]h)state for the CRTC to select the DPLL for}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubj})}(hM``enum icl_port_dpll_id port_dpll_id`` the active **port_dpll_id** to select h](j)}(h&``enum icl_port_dpll_id port_dpll_id``h]j)}(hjh]h"enum icl_port_dpll_id port_dpll_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubj)}(hhh]h)}(h%the active **port_dpll_id** to selecth](h the active }(hjhhhNhNubjb)}(h**port_dpll_id**h]h port_dpll_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh to select}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjGh]h Description}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjEubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubh)}(hPSelect the given **port_dpll_id** instance from the DPLLs reserved for the CRTC.h](hSelect the given }(hj]hhhNhNubjb)}(h**port_dpll_id**h]h port_dpll_id}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jahj]ubh/ instance from the DPLLs reserved for the CRTC.}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_shared_dpll_init (C function)c.intel_shared_dpll_inithNtauh1jhjWhhhNhNubj')}(hhh](j,)}(h;void intel_shared_dpll_init (struct intel_display *display)h]j2)}(h:void intel_shared_dpll_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_shared_dpll_inith]j;)}(hintel_shared_dpll_inith]hintel_shared_dpll_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_shared_dpll_initasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj4hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hInitialize shared DPLLsh]hInitialize shared DPLLs}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj[hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjvjSjvjTjUjVuh1j&hhhjWhNhNubjX)}(h**Parameters** ``struct intel_display *display`` intel_display device **Description** Initialize shared DPLLs for **display**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj~ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjzubjx)}(hhh]j})}(h7``struct intel_display *display`` intel_display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(hintel_display deviceh]hintel_display device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjzubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjzubh)}(h(Initialize shared DPLLs for **display**.h](hInitialize shared DPLLs for }(hjhhhNhNubjb)}(h **display**h]hdisplay}(hjhhhNhNubah}(h]h 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classnameNjXj[)}j^]jc.intel_compute_shared_dpllsasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjfubj)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubji)}(h h]h }(hj]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjLubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hjnhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjkubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjpmodnameN classnameNjXj[)}j^]jc.intel_compute_shared_dpllsasbuh1hhjLubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjLubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj;)}(hencoderh]hencoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjLubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjfubeh}(h]h ]h"]h$]h&]jjuh1jhj-hhhj?hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj)hhhj?hMubah}(h]j$ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj?hMhj&hhubj1)}(hhh]h)}(h/compute DPLL state CRTC and encoder combinationh]h/compute DPLL state CRTC and encoder combination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj&hhhj?hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` CRTC to compute DPLLs for ``struct intel_encoder *encoder`` encoder **Description** This function computes the DPLL state for the given CRTC and encoder. The new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state(). **Return** 0 on success, negative error code on failure.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(h atomic stateh]h atomic state}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hMhj(ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj'hMhj ubj})}(h6``struct intel_crtc *crtc`` CRTC to compute DPLLs for h](j)}(h``struct intel_crtc *crtc``h]j)}(hjKh]hstruct intel_crtc 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]juah"]h$]h&]uh1jhhjHhhhjZhM>ubjz)}(hintel_reserve_shared_dpllsh]j;)}(hintel_reserve_shared_dpllsh]hintel_reserve_shared_dplls}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjiubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjHhhhjZhM>ubj)}(hZ(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjosbc.intel_reserve_shared_dpllsasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_reserve_shared_dpllsasbuh1hhjubji)}(h h]h }(hj7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubji)}(h h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjgubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_reserve_shared_dpllsasbuh1hhjgubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjgubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubj;)}(hencoderh]hencoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjgubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjHhhhjZhM>ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjDhhhjZhM>ubah}(h]j?ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjZhM>hjAhhubj1)}(hhh]h)}(h.reserve DPLLs for CRTC and encoder combinationh]h.reserve DPLLs for CRTC and encoder combination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM+hjhhubah}(h]h ]h"]h$]h&]uh1j0hjAhhhjZhM>ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hX}**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` CRTC to reserve DPLLs for ``struct intel_encoder *encoder`` encoder **Description** This function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit **state** and the new **crtc** atomic state. The new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state(). The reserved DPLLs should be released by calling intel_release_shared_dplls(). **Return** 0 if all required DPLLs were successfully reserved, negative error code otherwise.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM/hjubjx)}(hhh](j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hj-h]h struct intel_atomic_state *state}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM,hj'ubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhM,hjCubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1j|hjBhM,hj$ubj})}(h6``struct intel_crtc *crtc`` CRTC to reserve DPLLs for h](j)}(h``struct intel_crtc *crtc``h]j)}(hjfh]hstruct intel_crtc *crtc}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM-hj`ubj)}(hhh]h)}(hCRTC to reserve DPLLs forh]hCRTC to reserve DPLLs for}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hM-hj|ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1j|hj{hM-hj$ubj})}(h*``struct intel_encoder *encoder`` encoder h](j)}(h!``struct intel_encoder *encoder``h]j)}(hjh]hstruct intel_encoder *encoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM.hjubj)}(hhh]h)}(hencoderh]hencoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM.hj$ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM0hjubh)}(hThis function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit **state** and the new **crtc** atomic state.h](hrThis function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit }(hjhhhNhNubjb)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and the new }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh atomic state.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM0hjubh)}(hqThe new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state().h](h+The new configuration in the atomic commit }(hj#hhhNhNubjb)}(h **state**h]hstate}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubh= is made effective by calling intel_shared_dpll_swap_state().}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM4hjubh)}(hNThe reserved DPLLs should be released by calling intel_release_shared_dplls().h]hNThe reserved DPLLs should be released by calling intel_release_shared_dplls().}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM7hjubh)}(h **Return**h]jb)}(hjUh]hReturn}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjSubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM:hjubh)}(hR0 if all required DPLLs were successfully reserved, negative error code otherwise.h]hR0 if all required DPLLs were successfully reserved, negative error code otherwise.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM:hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_release_shared_dplls (C function)c.intel_release_shared_dpllshNtauh1jhjWhhhNhNubj')}(hhh](j,)}(h[void intel_release_shared_dplls (struct intel_atomic_state *state, struct intel_crtc *crtc)h]j2)}(hZvoid intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMVubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMVubjz)}(hintel_release_shared_dpllsh]j;)}(hintel_release_shared_dpllsh]hintel_release_shared_dplls}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMVubj)}(h;(struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_release_shared_dpllsasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hstateh]hstate}(hj0hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjghhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjdubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjimodnameN classnameNjXj[)}j^]jc.intel_release_shared_dpllsasbuh1hhjEubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMVubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMVubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMVhjhhubj1)}(hhh]h)}(h(end use of DPLLs by CRTC in atomic stateh]h(end use of DPLLs by CRTC in atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMLhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMVubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` crtc from which the DPLLs are to be released **Description** This function releases all DPLLs reserved by intel_reserve_shared_dplls() from the current atomic commit **state** and the old **crtc** atomic state. The new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state().h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMPhjubjx)}(hhh](j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hj h]h struct intel_atomic_state *state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMMhjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMMhj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hMMhjubj})}(hI``struct intel_crtc *crtc`` crtc from which the DPLLs are to be released h](j)}(h``struct intel_crtc *crtc``h]j)}(hjDh]hstruct intel_crtc *crtc}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMNhj>ubj)}(hhh]h)}(h,crtc from which the DPLLs are to be releasedh]h,crtc from which the DPLLs are to be released}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMNhjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1j|hjYhMNhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj}ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMPhjubh)}(hThis function releases all DPLLs reserved by intel_reserve_shared_dplls() from the current atomic commit **state** and the old **crtc** atomic state.h](hiThis function releases all DPLLs reserved by intel_reserve_shared_dplls() from the current atomic commit }(hjhhhNhNubjb)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and the old }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh atomic state.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMPhjubh)}(hqThe new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state().h](h+The new configuration in the atomic commit }(hjhhhNhNubjb)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh= is made effective by calling intel_shared_dpll_swap_state().}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMShjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_update_active_dpll (C function)c.intel_update_active_dpllhNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hxvoid intel_update_active_dpll (struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h]j2)}(hwvoid intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMrubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMrubjz)}(hintel_update_active_dpllh]j;)}(hintel_update_active_dpllh]hintel_update_active_dpll}(hj*hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj&ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMrubj)}(hZ(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjBubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjdhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjaubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjfmodnameN classnameNjXj[)}j^]ja)}jTj,sbc.intel_update_active_dpllasbuh1hhjBubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjBubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubj;)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjBubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_update_active_dpllasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubj)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjHmodnameN classnameNjXj[)}j^]jc.intel_update_active_dpllasbuh1hhj$ubji)}(h h]h }(hjdhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubj)}(hjh]h*}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj;)}(hencoderh]hencoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMrubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMrubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMrhjhhubj1)}(hhh]h)}(h)update the active DPLL for a CRTC/encoderh]h)update the active DPLL for a CRTC/encoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMihjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMrubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` the CRTC for which to update the active DPLL ``struct intel_encoder *encoder`` encoder determining the type of port DPLL **Description** Update the active DPLL for the given **crtc**/**encoder** in **crtc**'s atomic state, from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The DPLL selected will be based on the current mode of the encoder's port.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMmhjubjx)}(hhh](j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMjhjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMjhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMjhjubj})}(hI``struct intel_crtc *crtc`` the CRTC for which to update the active DPLL h](j)}(h``struct intel_crtc *crtc``h]j)}(hj#h]hstruct intel_crtc *crtc}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMkhjubj)}(hhh]h)}(h,the CRTC for which to update the active DPLLh]h,the CRTC for which to update the active DPLL}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMkhj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj8hMkhjubj})}(hL``struct intel_encoder *encoder`` encoder determining the type of port DPLL h](j)}(h!``struct intel_encoder *encoder``h]j)}(hj\h]hstruct intel_encoder *encoder}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMlhjVubj)}(hhh]h)}(h)encoder determining the type of port DPLLh]h)encoder determining the type of port DPLL}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhMlhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j|hjqhMlhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMnhjubh)}(hUpdate the active DPLL for the given **crtc**/**encoder** in **crtc**'s atomic state, from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The DPLL selected will be based on the current mode of the encoder's port.h](h%Update the active DPLL for the given }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh/}(hjhhhNhNubjb)}(h **encoder**h]hencoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh in }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh’s atomic state, from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The DPLL selected will be based on the current mode of the encoder’s port.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_dpll_get_freq (C function)c.intel_dpll_get_freqhNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hint intel_dpll_get_freq (struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h]j2)}(hint intel_dpll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hj!hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj hMubjz)}(hintel_dpll_get_freqh]j;)}(hintel_dpll_get_freqh]hintel_dpll_get_freq}(hj3hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj hMubj)}(hu(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hj\hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjomodnameN classnameNjXj[)}j^]ja)}jTj5sbc.intel_dpll_get_freqasbuh1hhjKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjGubj)}(h#const struct intel_shared_dpll *pllh](j)}(hjuh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_dpll_get_freqasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hpllh]hpll}(hj3hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjGubj)}(h/const struct intel_dpll_hw_state *dpll_hw_stateh](j)}(hjuh]hconst}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubji)}(h h]h }(hjYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHubj)}(hjh]hstruct}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubji)}(h h]h }(hjthhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_dpll_get_freqasbuh1hhjHubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubj;)}(h dpll_hw_stateh]h dpll_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjHubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjGubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhj hMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj hMhjhhubj1)}(hhh]h)}(h%calculate the DPLL's output frequencyh]h'calculate the DPLL’s output frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hXy**Parameters** ``struct intel_display *display`` intel_display device ``const struct intel_shared_dpll *pll`` DPLL for which to calculate the output frequency ``const struct intel_dpll_hw_state *dpll_hw_state`` DPLL state from which to calculate the output frequency **Description** Return the output frequency corresponding to **pll**'s passed in **dpll_hw_state**.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(h7``struct intel_display *display`` intel_display device h](j)}(h!``struct intel_display *display``h]j)}(hj)h]hstruct intel_display *display}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj#ubj)}(hhh]h)}(hintel_display deviceh]hintel_display device}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1j|hj>hMhj ubj})}(hY``const struct intel_shared_dpll *pll`` DPLL for which to calculate the output frequency h](j)}(h'``const struct intel_shared_dpll *pll``h]j)}(hjbh]h#const struct intel_shared_dpll *pll}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj\ubj)}(hhh]h)}(h0DPLL for which to calculate the output frequencyh]h0DPLL for which to calculate the output frequency}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMhjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1j|hjwhMhj ubj})}(hl``const struct intel_dpll_hw_state *dpll_hw_state`` DPLL state from which to calculate the output frequency h](j)}(h3``const struct intel_dpll_hw_state *dpll_hw_state``h]j)}(hjh]h/const struct intel_dpll_hw_state *dpll_hw_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h7DPLL state from which to calculate the output frequencyh]h7DPLL state from which to calculate the output frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hSReturn the output frequency corresponding to **pll**'s passed in **dpll_hw_state**.h](h-Return the output frequency corresponding to }(hjhhhNhNubjb)}(h**pll**h]hpll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh’s passed in }(hjhhhNhNubjb)}(h**dpll_hw_state**h]h dpll_hw_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_dpll_get_hw_state (C function)c.intel_dpll_get_hw_statehNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hbool intel_dpll_get_hw_state (struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h]j2)}(hbool intel_dpll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hjh]hbool}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjMhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj;hhhjLhMubjz)}(hintel_dpll_get_hw_stateh]j;)}(hintel_dpll_get_hw_stateh]hintel_dpll_get_hw_state}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj[ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj;hhhjLhMubj)}(hi(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjwubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjasbc.intel_dpll_get_hw_stateasbuh1hhjwubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjwubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjwubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjsubj)}(hstruct intel_shared_dpll *pllh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jc.intel_dpll_get_hw_stateasbuh1hhjubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hpllh]hpll}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjsubj)}(h)struct intel_dpll_hw_state *dpll_hw_stateh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubji)}(h h]h }(hjjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hj{hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjxubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj}modnameN classnameNjXj[)}j^]jc.intel_dpll_get_hw_stateasbuh1hhjYubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubj;)}(h dpll_hw_stateh]h dpll_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjYubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjsubeh}(h]h ]h"]h$]h&]jjuh1jhj;hhhjLhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj7hhhjLhMubah}(h]j2ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjLhMhj4hhubj1)}(hhh]h)}(h!readout the DPLL's hardware stateh]h#readout the DPLL’s hardware state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj4hhhjLhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hX:**Parameters** ``struct intel_display *display`` intel_display device instance ``struct intel_shared_dpll *pll`` DPLL for which to calculate the output frequency ``struct intel_dpll_hw_state *dpll_hw_state`` DPLL's hardware state **Description** Read out **pll**'s hardware state into **dpll_hw_state**.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(h@``struct intel_display *display`` intel_display device instance h](j)}(h!``struct intel_display *display``h]j)}(hj h]hstruct intel_display *display}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(hintel_display device instanceh]hintel_display device instance}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4 hMhj5 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj4 hMhj ubj})}(hS``struct intel_shared_dpll *pll`` DPLL for which to calculate the output frequency h](j)}(h!``struct intel_shared_dpll *pll``h]j)}(hjX h]hstruct intel_shared_dpll *pll}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjV ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjR ubj)}(hhh]h)}(h0DPLL for which to calculate the output frequencyh]h0DPLL for which to calculate the output frequency}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjm hMhjn ubah}(h]h ]h"]h$]h&]uh1jhjR ubeh}(h]h ]h"]h$]h&]uh1j|hjm hMhj ubj})}(hD``struct intel_dpll_hw_state *dpll_hw_state`` DPLL's hardware state h](j)}(h-``struct intel_dpll_hw_state *dpll_hw_state``h]j)}(hj h]h)struct intel_dpll_hw_state *dpll_hw_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(hDPLL's hardware stateh]hDPLL’s hardware state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hMhj ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(h9Read out **pll**'s hardware state into **dpll_hw_state**.h](h Read out }(hj hhhNhNubjb)}(h**pll**h]hpll}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh’s hardware state into }(hj hhhNhNubjb)}(h**dpll_hw_state**h]h dpll_hw_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_dpll_dump_hw_state (C function)c.intel_dpll_dump_hw_statehNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hvoid intel_dpll_dump_hw_state (struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h]j2)}(hvoid intel_dpll_dump_hw_state(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hvoidh]hvoid}(hj5 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1 hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjD hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj1 hhhjC hMubjz)}(hintel_dpll_dump_hw_stateh]j;)}(hintel_dpll_dump_hw_stateh]hintel_dpll_dump_hw_state}(hjV hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjR ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj1 hhhjC hMubj)}(hg(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjr hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjn ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjX sbc.intel_dpll_dump_hw_stateasbuh1hhjn ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjn ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjn ubj;)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjn ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjj ubj)}(hstruct drm_printer *ph](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(h drm_printerh]h drm_printer}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]j c.intel_dpll_dump_hw_stateasbuh1hhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj. hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hjh]hp}(hj; hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjj ubj)}(h/const struct intel_dpll_hw_state *dpll_hw_stateh](j)}(hjuh]hconst}(hjS hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO ubji)}(h h]h }(hj` hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjO ubj)}(hjh]hstruct}(hjn hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO ubji)}(h h]h }(hj{ hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjO ubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]j c.intel_dpll_dump_hw_stateasbuh1hhjO ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjO ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO ubj;)}(h dpll_hw_stateh]h dpll_hw_state}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjO ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjj ubeh}(h]h ]h"]h$]h&]jjuh1jhj1 hhhjC hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj- hhhjC hMubah}(h]j( ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjC hMhj* hhubj1)}(hhh]h)}(h dump hw_stateh]h dump hw_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj hhubah}(h]h ]h"]h$]h&]uh1j0hj* hhhjC hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhjWhNhNubjX)}(hX**Parameters** ``struct intel_display *display`` intel_display structure ``struct drm_printer *p`` where to print the state to ``const struct intel_dpll_hw_state *dpll_hw_state`` hw state to be dumped **Description** Dumo out the relevant values in **dpll_hw_state**.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubjx)}(hhh](j})}(h:``struct intel_display *display`` intel_display structure h](j)}(h!``struct intel_display *display``h]j)}(hj0 h]hstruct intel_display *display}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj. ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj* ubj)}(hhh]h)}(hintel_display structureh]hintel_display structure}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE hMhjF ubah}(h]h ]h"]h$]h&]uh1jhj* ubeh}(h]h ]h"]h$]h&]uh1j|hjE hMhj' ubj})}(h6``struct drm_printer *p`` where to print the state to h](j)}(h``struct drm_printer *p``h]j)}(hji h]hstruct drm_printer *p}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjg ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjc ubj)}(hhh]h)}(hwhere to print the state toh]hwhere to print the state to}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~ hMhj ubah}(h]h ]h"]h$]h&]uh1jhjc ubeh}(h]h ]h"]h$]h&]uh1j|hj~ hMhj' ubj})}(hJ``const struct intel_dpll_hw_state *dpll_hw_state`` hw state to be dumped h](j)}(h3``const struct intel_dpll_hw_state *dpll_hw_state``h]j)}(hj h]h/const struct intel_dpll_hw_state *dpll_hw_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(hhw state to be dumpedh]hhw state to be dumped}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hMhj' ubeh}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubh)}(h2Dumo out the relevant values in **dpll_hw_state**.h](h Dumo out the relevant values in }(hj hhhNhNubjb)}(h**dpll_hw_state**h]h dpll_hw_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"(intel_dpll_compare_hw_state (C function)c.intel_dpll_compare_hw_statehNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hbool intel_dpll_compare_hw_state (struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h]j2)}(hbool intel_dpll_compare_hw_state(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h](j)}(hjh]hbool}(hj4 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0 hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjB hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj0 hhhjA hMubjz)}(hintel_dpll_compare_hw_stateh]j;)}(hintel_dpll_compare_hw_stateh]hintel_dpll_compare_hw_state}(hjT hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjP ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj0 hhhjA hMubj)}(hi(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjp hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl ubji)}(h h]h }(hj} hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjl ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjV sbc.intel_dpll_compare_hw_stateasbuh1hhjl ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjl ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl ubj;)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjl ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjh ubj)}(h#const struct intel_dpll_hw_state *ah](j)}(hjuh]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j c.intel_dpll_compare_hw_stateasbuh1hhj ubji)}(h h]h }(hj9hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hjeh]ha}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjh ubj)}(h#const struct intel_dpll_hw_state *bh](j)}(hjuh]hconst}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubji)}(h h]h }(hjyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j c.intel_dpll_compare_hw_stateasbuh1hhjhubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj;)}(hjh]hb}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjh ubeh}(h]h ]h"]h$]h&]jjuh1jhj0 hhhjA hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj, hhhjA hMubah}(h]j' ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjA hMhj) hhubj1)}(hhh]h)}(hcompare the two statesh]hcompare the two states}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj) hhhjA hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hXC**Parameters** ``struct intel_display *display`` intel_display structure ``const struct intel_dpll_hw_state *a`` first DPLL hw state ``const struct intel_dpll_hw_state *b`` second DPLL hw state **Description** Compare DPLL hw states **a** and **b**. **Return** true if the states are equal, false if the differh](h)}(h**Parameters**h]jb)}(hj)h]h Parameters}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj#ubjx)}(hhh](j})}(h:``struct intel_display *display`` intel_display structure h](j)}(h!``struct intel_display *display``h]j)}(hjHh]hstruct intel_display *display}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjBubj)}(hhh]h)}(hintel_display structureh]hintel_display structure}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hMhj^ubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1j|hj]hMhj?ubj})}(h<``const struct intel_dpll_hw_state *a`` first DPLL hw state h](j)}(h'``const struct intel_dpll_hw_state *a``h]j)}(hjh]h#const struct intel_dpll_hw_state *a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj{ubj)}(hhh]h)}(hfirst DPLL hw stateh]hfirst DPLL hw state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj?ubj})}(h=``const struct intel_dpll_hw_state *b`` second DPLL hw state h](j)}(h'``const struct intel_dpll_hw_state *b``h]j)}(hjh]h#const struct intel_dpll_hw_state *b}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(hsecond DPLL hw stateh]hsecond DPLL hw state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj?ubeh}(h]h ]h"]h$]h&]uh1jwhj#ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj#ubh)}(h'Compare DPLL hw states **a** and **b**.h](hCompare DPLL hw states }(hj hhhNhNubjb)}(h**a**h]ha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh and }(hj hhhNhNubjb)}(h**b**h]hb}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj#ubh)}(h **Return**h]jb)}(hj@h]hReturn}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj>ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj#ubh)}(h1true if the states are equal, false if the differh]h1true if the states are equal, false if the differ}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dpll_id (C enum)c.intel_dpll_idhNtauh1jhjWhhhNhNubj')}(hhh](j,)}(h intel_dpll_idh]j2)}(henum intel_dpll_idh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(h intel_dpll_idh]j;)}(hjh]h intel_dpll_id}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj}hhhjhKubah}(h]jxah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjzhhubj1)}(hhh]h)}(hpossible DPLL idsh]hpossible DPLL ids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK/hjhhubah}(h]h ]h"]h$]h&]uh1j0hjzhhhjhKubeh}(h]h ](jRenumeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjWhNhNubjX)}(hX**Constants** ``DPLL_ID_PRIVATE`` non-shared dpll in use ``DPLL_ID_PCH_PLL_A`` DPLL A in ILK, SNB and IVB ``DPLL_ID_PCH_PLL_B`` DPLL B in ILK, SNB and IVB ``DPLL_ID_WRPLL1`` HSW and BDW WRPLL1 ``DPLL_ID_WRPLL2`` HSW and BDW WRPLL2 ``DPLL_ID_SPLL`` HSW and BDW SPLL ``DPLL_ID_LCPLL_810`` HSW and BDW 0.81 GHz LCPLL ``DPLL_ID_LCPLL_1350`` HSW and BDW 1.35 GHz LCPLL ``DPLL_ID_LCPLL_2700`` HSW and BDW 2.7 GHz LCPLL ``DPLL_ID_SKL_DPLL0`` SKL and later DPLL0 ``DPLL_ID_SKL_DPLL1`` SKL and later DPLL1 ``DPLL_ID_SKL_DPLL2`` SKL and later DPLL2 ``DPLL_ID_SKL_DPLL3`` SKL and later DPLL3 ``DPLL_ID_ICL_DPLL0`` ICL/TGL combo PHY DPLL0 ``DPLL_ID_ICL_DPLL1`` ICL/TGL combo PHY DPLL1 ``DPLL_ID_EHL_DPLL4`` EHL combo PHY DPLL4 ``DPLL_ID_ICL_TBTPLL`` ICL/TGL TBT PLL ``DPLL_ID_ICL_MGPLL1`` ICL MG PLL 1 port 1 (C), TGL TC PLL 1 port 1 (TC1) ``DPLL_ID_ICL_MGPLL2`` ICL MG PLL 1 port 2 (D) TGL TC PLL 1 port 2 (TC2) ``DPLL_ID_ICL_MGPLL3`` ICL MG PLL 1 port 3 (E) TGL TC PLL 1 port 3 (TC3) ``DPLL_ID_ICL_MGPLL4`` ICL MG PLL 1 port 4 (F) TGL TC PLL 1 port 4 (TC4) ``DPLL_ID_TGL_MGPLL5`` TGL TC PLL port 5 (TC5) ``DPLL_ID_TGL_MGPLL6`` TGL TC PLL port 6 (TC6) ``DPLL_ID_DG1_DPLL0`` DG1 combo PHY DPLL0 ``DPLL_ID_DG1_DPLL1`` DG1 combo PHY DPLL1 ``DPLL_ID_DG1_DPLL2`` DG1 combo PHY DPLL2 ``DPLL_ID_DG1_DPLL3`` DG1 combo PHY DPLL3h](h)}(h **Constants**h]jb)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK3hjubjx)}(hhh](j})}(h+``DPLL_ID_PRIVATE`` non-shared dpll in use h](j)}(h``DPLL_ID_PRIVATE``h]j)}(hjh]hDPLL_ID_PRIVATE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK6hjubj)}(hhh]h)}(hnon-shared dpll in useh]hnon-shared dpll in use}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK6hjubj})}(h1``DPLL_ID_PCH_PLL_A`` DPLL A in ILK, SNB and IVB h](j)}(h``DPLL_ID_PCH_PLL_A``h]j)}(hjAh]hDPLL_ID_PCH_PLL_A}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK9hj;ubj)}(hhh]h)}(hDPLL A in ILK, SNB and IVBh]hDPLL A in ILK, SNB and IVB}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhK9hjWubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j|hjVhK9hjubj})}(h1``DPLL_ID_PCH_PLL_B`` DPLL B in ILK, SNB and IVB h](j)}(h``DPLL_ID_PCH_PLL_B``h]j)}(hjzh]hDPLL_ID_PCH_PLL_B}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKEhj;ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj:hKEhjubj})}(h1``DPLL_ID_LCPLL_810`` HSW and BDW 0.81 GHz LCPLL h](j)}(h``DPLL_ID_LCPLL_810``h]j)}(hj^h]hDPLL_ID_LCPLL_810}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKHhjXubj)}(hhh]h)}(hHSW and BDW 0.81 GHz LCPLLh]hHSW and BDW 0.81 GHz LCPLL}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshKHhjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1j|hjshKHhjubj})}(h2``DPLL_ID_LCPLL_1350`` HSW and BDW 1.35 GHz LCPLL h](j)}(h``DPLL_ID_LCPLL_1350``h]j)}(hjh]hDPLL_ID_LCPLL_1350}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKKhjubj)}(hhh]h)}(hHSW and BDW 1.35 GHz LCPLLh]hHSW and BDW 1.35 GHz LCPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKKhjubj})}(h1``DPLL_ID_LCPLL_2700`` HSW and BDW 2.7 GHz LCPLL h](j)}(h``DPLL_ID_LCPLL_2700``h]j)}(hjh]hDPLL_ID_LCPLL_2700}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKNhjubj)}(hhh]h)}(hHSW and BDW 2.7 GHz LCPLLh]hHSW and BDW 2.7 GHz LCPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKNhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKNhjubj})}(h*``DPLL_ID_SKL_DPLL0`` SKL and later DPLL0 h](j)}(h``DPLL_ID_SKL_DPLL0``h]j)}(hj h]hDPLL_ID_SKL_DPLL0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKQhjubj)}(hhh]h)}(hSKL and later DPLL0h]hSKL and later DPLL0}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKQhjubj})}(h*``DPLL_ID_SKL_DPLL1`` SKL and later DPLL1 h](j)}(h``DPLL_ID_SKL_DPLL1``h]j)}(hjBh]hDPLL_ID_SKL_DPLL1}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKThj<ubj)}(hhh]h)}(hSKL and later DPLL1h]hSKL and later DPLL1}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhKThjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1j|hjWhKThjubj})}(h*``DPLL_ID_SKL_DPLL2`` SKL and later DPLL2 h](j)}(h``DPLL_ID_SKL_DPLL2``h]j)}(hj{h]hDPLL_ID_SKL_DPLL2}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKWhjuubj)}(hhh]h)}(hSKL and later DPLL2h]hSKL and later DPLL2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKWhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1j|hjhKWhjubj})}(h*``DPLL_ID_SKL_DPLL3`` SKL and later DPLL3 h](j)}(h``DPLL_ID_SKL_DPLL3``h]j)}(hjh]hDPLL_ID_SKL_DPLL3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKZhjubj)}(hhh]h)}(hSKL and later DPLL3h]hSKL and later DPLL3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKZhjubj})}(h.``DPLL_ID_ICL_DPLL0`` ICL/TGL combo PHY DPLL0 h](j)}(h``DPLL_ID_ICL_DPLL0``h]j)}(hjh]hDPLL_ID_ICL_DPLL0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK]hjubj)}(hhh]h)}(hICL/TGL combo PHY DPLL0h]hICL/TGL combo PHY DPLL0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK]hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK]hjubj})}(h.``DPLL_ID_ICL_DPLL1`` ICL/TGL combo PHY DPLL1 h](j)}(h``DPLL_ID_ICL_DPLL1``h]j)}(hj&h]hDPLL_ID_ICL_DPLL1}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK`hj ubj)}(hhh]h)}(hICL/TGL combo PHY DPLL1h]hICL/TGL combo PHY DPLL1}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hK`hj<ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj;hK`hjubj})}(h*``DPLL_ID_EHL_DPLL4`` EHL combo PHY DPLL4 h](j)}(h``DPLL_ID_EHL_DPLL4``h]j)}(hj_h]hDPLL_ID_EHL_DPLL4}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKchjYubj)}(hhh]h)}(hEHL combo PHY DPLL4h]hEHL combo PHY DPLL4}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthKchjuubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1j|hjthKchjubj})}(h'``DPLL_ID_ICL_TBTPLL`` ICL/TGL TBT PLL h](j)}(h``DPLL_ID_ICL_TBTPLL``h]j)}(hjh]hDPLL_ID_ICL_TBTPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKfhjubj)}(hhh]h)}(hICL/TGL TBT PLLh]hICL/TGL TBT PLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKfhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKfhjubj})}(h_``DPLL_ID_ICL_MGPLL1`` ICL MG PLL 1 port 1 (C), TGL TC PLL 1 port 1 (TC1) h](j)}(h``DPLL_ID_ICL_MGPLL1``h]j)}(hjh]hDPLL_ID_ICL_MGPLL1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKjhjubj)}(hhh]jx)}(hhh]j})}(h3ICL MG PLL 1 port 1 (C), TGL TC PLL 1 port 1 (TC1) h](j)}(hICL MG PLL 1 port 1 (C),h]hICL MG PLL 1 port 1 (C),}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKjhjubj)}(hhh]h)}(hTGL TC PLL 1 port 1 (TC1)h]hTGL TC PLL 1 port 1 (TC1)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKjhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKjhjubah}(h]h ]h"]h$]h&]uh1jwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKjhjubj})}(h^``DPLL_ID_ICL_MGPLL2`` ICL MG PLL 1 port 2 (D) TGL TC PLL 1 port 2 (TC2) h](j)}(h``DPLL_ID_ICL_MGPLL2``h]j)}(hj4h]hDPLL_ID_ICL_MGPLL2}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKnhj.ubj)}(hhh]jx)}(hhh]j})}(h2ICL MG PLL 1 port 2 (D) TGL TC PLL 1 port 2 (TC2) h](j)}(hICL MG PLL 1 port 2 (D)h]hICL MG PLL 1 port 2 (D)}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIhKnhjPubj)}(hhh]h)}(hTGL TC PLL 1 port 2 (TC2)h]hTGL TC PLL 1 port 2 (TC2)}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhKnhjbubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j|hjIhKnhjMubah}(h]h ]h"]h$]h&]uh1jwhjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hjIhKnhjubj})}(h^``DPLL_ID_ICL_MGPLL3`` ICL MG PLL 1 port 3 (E) TGL TC PLL 1 port 3 (TC3) h](j)}(h``DPLL_ID_ICL_MGPLL3``h]j)}(hjh]hDPLL_ID_ICL_MGPLL3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKrhjubj)}(hhh]jx)}(hhh]j})}(h2ICL MG PLL 1 port 3 (E) TGL TC PLL 1 port 3 (TC3) h](j)}(hICL MG PLL 1 port 3 (E)h]hICL MG PLL 1 port 3 (E)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKrhjubj)}(hhh]h)}(hTGL TC PLL 1 port 3 (TC3)h]hTGL TC PLL 1 port 3 (TC3)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKrhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKrhjubah}(h]h ]h"]h$]h&]uh1jwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKrhjubj})}(h^``DPLL_ID_ICL_MGPLL4`` ICL MG PLL 1 port 4 (F) TGL TC PLL 1 port 4 (TC4) h](j)}(h``DPLL_ID_ICL_MGPLL4``h]j)}(hjh]hDPLL_ID_ICL_MGPLL4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKvhjubj)}(hhh]jx)}(hhh]j})}(h2ICL MG PLL 1 port 4 (F) TGL TC PLL 1 port 4 (TC4) h](j)}(hICL MG PLL 1 port 4 (F)h]hICL MG PLL 1 port 4 (F)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKvhjubj)}(hhh]h)}(hTGL TC PLL 1 port 4 (TC4)h]hTGL TC PLL 1 port 4 (TC4)}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKvhj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKvhjubah}(h]h ]h"]h$]h&]uh1jwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKvhjubj})}(h/``DPLL_ID_TGL_MGPLL5`` TGL TC PLL port 5 (TC5) h](j)}(h``DPLL_ID_TGL_MGPLL5``h]j)}(hj]h]hDPLL_ID_TGL_MGPLL5}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKyhjWubj)}(hhh]h)}(hTGL TC PLL port 5 (TC5)h]hTGL TC PLL port 5 (TC5)}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhKyhjsubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1j|hjrhKyhjubj})}(h/``DPLL_ID_TGL_MGPLL6`` TGL TC PLL port 6 (TC6) h](j)}(h``DPLL_ID_TGL_MGPLL6``h]j)}(hjh]hDPLL_ID_TGL_MGPLL6}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK|hjubj)}(hhh]h)}(hTGL TC PLL port 6 (TC6)h]hTGL TC PLL port 6 (TC6)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK|hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK|hjubj})}(h*``DPLL_ID_DG1_DPLL0`` DG1 combo PHY DPLL0 h](j)}(h``DPLL_ID_DG1_DPLL0``h]j)}(hjh]hDPLL_ID_DG1_DPLL0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKhjubj)}(hhh]h)}(hDG1 combo PHY DPLL0h]hDG1 combo PHY DPLL0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h*``DPLL_ID_DG1_DPLL1`` DG1 combo PHY DPLL1 h](j)}(h``DPLL_ID_DG1_DPLL1``h]j)}(hjh]hDPLL_ID_DG1_DPLL1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKhjubj)}(hhh]h)}(hDG1 combo PHY DPLL1h]hDG1 combo PHY DPLL1}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h*``DPLL_ID_DG1_DPLL2`` DG1 combo PHY DPLL2 h](j)}(h``DPLL_ID_DG1_DPLL2``h]j)}(hjAh]hDPLL_ID_DG1_DPLL2}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKhj;ubj)}(hhh]h)}(hDG1 combo PHY DPLL2h]hDG1 combo PHY DPLL2}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhKhjWubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j|hjVhKhjubj})}(h)``DPLL_ID_DG1_DPLL3`` DG1 combo PHY DPLL3h](j)}(h``DPLL_ID_DG1_DPLL3``h]j)}(hjzh]hDPLL_ID_DG1_DPLL3}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKhjtubj)}(hhh]h)}(hDG1 combo PHY DPLL3h]hDG1 combo PHY DPLL3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKhjWhhubh)}(hJEnumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.h]hJEnumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK0hjWhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_shared_dpll_state (C struct)c.intel_shared_dpll_statehNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hintel_shared_dpll_stateh]j2)}(hstruct intel_shared_dpll_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK5ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhK5ubjz)}(hintel_shared_dpll_stateh]j;)}(hjh]hintel_shared_dpll_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhK5ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhK5ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhK5hjhhubj1)}(hhh]h)}(hhold the DPLL atomic stateh]hhold the DPLL atomic state}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhj:hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhK5ubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjUjSjUjTjUjVuh1j&hhhjWhNhNubjX)}(hX)**Definition**:: struct intel_shared_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; }; **Members** ``pipe_mask`` mask of pipes using this DPLL, active or not ``hw_state`` hardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jahj]ubh:}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhjYubj")}(h^struct intel_shared_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; };h]h^struct intel_shared_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; };}hjzsbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM!hjYubh)}(h **Members**h]jb)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM&hjYubjx)}(hhh](j})}(h;``pipe_mask`` mask of pipes using this DPLL, active or not h](j)}(h ``pipe_mask``h]j)}(hjh]h pipe_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM'hjubj)}(hhh]h)}(h,mask of pipes using this DPLL, active or noth]h,mask of pipes using this DPLL, active or not}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM'hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM'hjubj})}(h```hw_state`` hardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](j)}(h ``hw_state``h]j)}(hjh]hhw_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM,hjubj)}(hhh]h)}(hShardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](h5hardware configuration for the DPLL stored in struct }(hjhhhNhNubh)}(h:c:type:`intel_dpll_hw_state`h]j)}(hjh]hintel_dpll_hw_state}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjintel_dpll_hw_stateuh1hhjhM,hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM,hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM,hjubeh}(h]h ]h"]h$]h&]uh1jwhjYubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubh)}(h**Description**h]jb)}(hjHh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM0hjWhhubh)}(hXThis structure holds an atomic state for the DPLL, that can represent either its current state (in struct :c:type:`intel_shared_dpll`) or a desired future state which would be applied by an atomic mode set (stored in a struct :c:type:`intel_atomic_state`).h](hjThis structure holds an atomic state for the DPLL, that can represent either its current state (in struct }(hj^hhhNhNubh)}(h:c:type:`intel_shared_dpll`h]j)}(hjhh]hintel_shared_dpll}(hjjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjintel_shared_dplluh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhj^ubh]) or a desired future state which would be applied by an atomic mode set (stored in a struct }(hj^hhhNhNubh)}(h:c:type:`intel_atomic_state`h]j)}(hjh]hintel_atomic_state}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjintel_atomic_stateuh1hhjhMhj^ubh).}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjWhhubh)}(hGSee also intel_reserve_shared_dplls() and intel_release_shared_dplls().h]hGSee also intel_reserve_shared_dplls() and intel_release_shared_dplls().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM!hjWhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"dpll_info (C struct) c.dpll_infohNtauh1jhjWhhhNhNubj')}(hhh](j,)}(h dpll_infoh]j2)}(hstruct dpll_infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM&ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM&ubjz)}(h dpll_infoh]j;)}(hjh]h dpll_info}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM&ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM&ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM&hjhhubj1)}(hhh]h)}(h"display PLL platform specific infoh]h"display PLL platform specific info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM2hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM&ubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRj5jSj5jTjUjVuh1j&hhhjWhNhNubjX)}(hX**Definition**:: struct dpll_info { const char *name; const struct intel_shared_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; }; **Members** ``name`` DPLL name; used for logging ``funcs`` platform specific hooks ``id`` unique identifier for this DPLL ``power_domain`` extra power domain required by the DPLL ``always_on`` Inform the state checker that the DPLL is kept enabled even if not in use by any CRTC. ``is_alt_port_dpll`` Inform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj=ubh:}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM6hj9ubj")}(hstruct dpll_info { const char *name; const struct intel_shared_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; };h]hstruct dpll_info { const char *name; const struct intel_shared_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; };}hjZsbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM8hj9ubh)}(h **Members**h]jb)}(hjkh]hMembers}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjiubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMAhj9ubjx)}(hhh](j})}(h%``name`` DPLL name; used for logging h](j)}(h``name``h]j)}(hjh]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM7hjubj)}(hhh]h)}(hDPLL name; used for loggingh]hDPLL name; used for logging}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM7hjubj})}(h"``funcs`` platform specific hooks h](j)}(h ``funcs``h]j)}(hjh]hfuncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM<hjubj)}(hhh]h)}(hplatform specific hooksh]hplatform specific hooks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM<hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM<hjubj})}(h'``id`` unique identifier for this DPLL h](j)}(h``id``h]j)}(hjh]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMAhjubj)}(hhh]h)}(hunique identifier for this DPLLh]hunique identifier for this DPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMAhjubj})}(h9``power_domain`` extra power domain required by the DPLL h](j)}(h``power_domain``h]j)}(hj5h]h power_domain}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMFhj/ubj)}(hhh]h)}(h'extra power domain required by the DPLLh]h'extra power domain required by the DPLL}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMFhjKubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1j|hjJhMFhjubj})}(he``always_on`` Inform the state checker that the DPLL is kept enabled even if not in use by any CRTC. h](j)}(h ``always_on``h]j)}(hjnh]h always_on}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMLhjhubj)}(hhh]h)}(hVInform the state checker that the DPLL is kept enabled even if not in use by any CRTC.h]hVInform the state checker that the DPLL is kept enabled even if not in use by any CRTC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMKhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1j|hjhMLhjubj})}(hm``is_alt_port_dpll`` Inform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h](j)}(h``is_alt_port_dpll``h]j)}(hjh]his_alt_port_dpll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMShjubj)}(hhh]h)}(hXInform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h]hXInform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMShjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMShjubeh}(h]h ]h"]h$]h&]uh1jwhj9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjWhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_shared_dpll (C struct)c.intel_shared_dpllhNtauh1jhjWhhhNhNubj')}(hhh](j,)}(hintel_shared_dpllh]j2)}(hstruct intel_shared_dpllh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMZubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMZubjz)}(hintel_shared_dpllh]j;)}(hjh]hintel_shared_dpll}(hj!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMZubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMZubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMZhjhhubj1)}(hhh]h)}(h(display PLL with tracked state and usersh]h(display PLL with tracked state and users}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM[hj@hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMZubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRj[jSj[jTjUjVuh1j&hhhjWhNhNubjX)}(hX**Definition**:: struct intel_shared_dpll { struct intel_shared_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; intel_wakeref_t wakeref; }; **Members** ``state`` Store the state for the pll, including its hw state and CRTCs using it. ``index`` index for atomic state ``active_mask`` mask of active pipes (i.e. DPMS on) using this DPLL ``on`` is the PLL actually active? Disabled during modeset ``info`` platform specific info ``wakeref`` In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabledh](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjcubh:}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM_hj_ubj")}(hstruct intel_shared_dpll { struct intel_shared_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; intel_wakeref_t wakeref; };h]hstruct intel_shared_dpll { struct intel_shared_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; intel_wakeref_t wakeref; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMahj_ubh)}(h **Members**h]jb)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMjhj_ubjx)}(hhh](j})}(hR``state`` Store the state for the pll, including its hw state and CRTCs using it. h](j)}(h ``state``h]j)}(hjh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMahjubj)}(hhh]h)}(hGStore the state for the pll, including its hw state and CRTCs using it.h]hGStore the state for the pll, including its hw state and CRTCs using it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM`hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMahjubj})}(h!``index`` index for atomic state h](j)}(h ``index``h]j)}(hjh]hindex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhhjubj)}(hhh]h)}(hindex for atomic stateh]hindex for atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhhjubj})}(hD``active_mask`` mask of active pipes (i.e. DPMS on) using this DPLL h](j)}(h``active_mask``h]j)}(hj#h]h active_mask}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMmhjubj)}(hhh]h)}(h3mask of active pipes (i.e. DPMS on) using this DPLLh]h3mask of active pipes (i.e. DPMS on) using this DPLL}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMmhj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj8hMmhjubj})}(h;``on`` is the PLL actually active? Disabled during modeset h](j)}(h``on``h]j)}(hj\h]hon}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMrhjVubj)}(hhh]h)}(h3is the PLL actually active? Disabled during modeseth]h3is the PLL actually active? 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DSB Support added from Gen12 Intel graphics based platform.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/display/intel_dsb.chKmcr_lock. uncore->lock should *not* be held when this function is called, although it may be acquired after this function call.h](h)}(h**Parameters**h]jb)}(hj)h]h Parameters}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj)ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM=hj)ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj)h]hstruct intel_gt *gt}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM:hj)ubj)}(hhh]h)}(h GT structureh]h GT structure}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hM:hj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1j|hj)hM:hj)ubj})}(h6``unsigned long *flags`` storage to save IRQ flags to h](j)}(h``unsigned long *flags``h]j)}(hj*h]hunsigned long *flags}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM;hj*ubj)}(hhh]h)}(hstorage to save IRQ flags toh]hstorage to save IRQ flags to}(hj0*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,*hM;hj-*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1j|hj,*hM;hj)ubeh}(h]h ]h"]h$]h&]uh1jwhj)ubh)}(h**Description**h]jb)}(hjR*h]h Description}(hjT*hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjP*ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM=hj)ubh)}(hPerforms locking to protect the steering for the duration of an MCR operation. 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lock}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj-hhubah}(h]h ]h"]h$]h&]uh1j0hj,hhhj-hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj-jSj-jTjUjVuh1j&hhhj((hNhNubjX)}(hXE**Parameters** ``struct intel_gt *gt`` GT structure **Description** This will be used to sanitize the initial status of the hardware lock during driver load and resume since there won't be any concurrent access from other agents at those times, but it's possible that boot firmware may have left the lock in a bad state.h](h)}(h**Parameters**h]jb)}(hj-h]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj-ubjx)}(hhh]j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj.h]hstruct intel_gt *gt}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h 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the lock in a bad state.}(hjV.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_gt_mcr_read (C function)c.intel_gt_mcr_readhNtauh1jhj((hhhNhNubj')}(hhh](j,)}(hXu32 intel_gt_mcr_read (struct intel_gt *gt, i915_mcr_reg_t reg, int group, int instance)h]j2)}(hWu32 intel_gt_mcr_read(struct intel_gt *gt, i915_mcr_reg_t reg, int group, int instance)h](h)}(hhh]j;)}(hu32h]hu32}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj.modnameN classnameNjXj[)}j^]ja)}jTintel_gt_mcr_readsbc.intel_gt_mcr_readasbuh1hhj.hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.hhhj.hMubjz)}(hintel_gt_mcr_readh]j;)}(hj.h]hintel_gt_mcr_read}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h 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]h"]h$]h&]noemphjjuh1jhj.ubj)}(h int grouph](j)}(hinth]hint}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/ubj;)}(hgrouph]hgroup}(hj/hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj.ubj)}(h int instanceh](j)}(hinth]hint}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/ubj;)}(hinstanceh]hinstance}(hj/hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj.ubeh}(h]h ]h"]h$]h&]jjuh1jhj.hhhj.hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj}.hhhj.hMubah}(h]jx.ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj.hMhjz.hhubj1)}(hhh]h)}(h+read a specific instance of an MCR registerh]h+read a specific instance of an MCR register}(hj 0hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj0hhubah}(h]h ]h"]h$]h&]uh1j0hjz.hhhj.hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj"0jSj"0jTjUjVuh1j&hhhj((hNhNubjX)}(hXJ**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to read ``int group`` the MCR group ``int instance`` the MCR instance **Context** Takes and releases gt->mcr_lock **Description** Returns the value read from an MCR register after steering toward a specific group/instance.h](h)}(h**Parameters**h]jb)}(hj,0h]h Parameters}(hj.0hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj*0ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj&0ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjK0h]hstruct intel_gt *gt}(hjM0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI0ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjE0ubj)}(hhh]h)}(h GT structureh]h GT structure}(hjd0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`0hMhja0ubah}(h]h ]h"]h$]h&]uh1jhjE0ubeh}(h]h ]h"]h$]h&]uh1j|hj`0hMhjB0ubj})}(h0``i915_mcr_reg_t reg`` the MCR register to read h](j)}(h``i915_mcr_reg_t reg``h]j)}(hj0h]hi915_mcr_reg_t reg}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj~0ubj)}(hhh]h)}(hthe MCR register to readh]hthe MCR register to read}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj~0ubeh}(h]h ]h"]h$]h&]uh1j|hj0hMhjB0ubj})}(h``int group`` the MCR group h](j)}(h ``int group``h]j)}(hj0h]h int group}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj0ubj)}(hhh]h)}(h the MCR grouph]h the MCR group}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1j|hj0hMhjB0ubj})}(h"``int instance`` the MCR instance h](j)}(h``int instance``h]j)}(hj0h]h int instance}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj0ubj)}(hhh]h)}(hthe MCR instanceh]hthe MCR instance}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 1hMhj 1ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1j|hj 1hMhjB0ubeh}(h]h ]h"]h$]h&]uh1jwhj&0ubh)}(h **Context**h]jb)}(hj11h]hContext}(hj31hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj/1ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj&0ubh)}(hTakes and releases gt->mcr_lockh]hTakes and releases gt->mcr_lock}(hjG1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj&0ubh)}(h**Description**h]jb)}(hjX1h]h Description}(hjZ1hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjV1ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj&0ubh)}(h\Returns the value read from an MCR register after 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reftargetjQ2modnameN classnameNjXj[)}j^]j2c.intel_gt_mcr_unicast_writeasbuh1hhjH2ubji)}(h h]h }(hjm2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjH2ubj;)}(hregh]hreg}(hj{2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjH2ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj1ubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj2modnameN classnameNjXj[)}j^]j2c.intel_gt_mcr_unicast_writeasbuh1hhj2ubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2ubj;)}(hvalueh]hvalue}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj1ubj)}(h int grouph](j)}(hinth]hint}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2ubj;)}(hgrouph]hgroup}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj1ubj)}(h int instanceh](j)}(hinth]hint}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 3ubji)}(h h]h }(hj3hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj 3ubj;)}(hinstanceh]hinstance}(hj-3hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj 3ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj1ubeh}(h]h ]h"]h$]h&]jjuh1jhj1hhhj1hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj1hhhj1hMubah}(h]j1ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj1hMhj1hhubj1)}(hhh]h)}(h,write a specific instance of an MCR registerh]h,write a specific instance of an MCR register}(hjW3hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjT3hhubah}(h]h ]h"]h$]h&]uh1j0hj1hhhj1hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjo3jSjo3jTjUjVuh1j&hhhj((hNhNubjX)}(hX{**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to write ``u32 value`` value to write ``int group`` the MCR group ``int instance`` the MCR instance **Description** Write an MCR register in unicast mode after steering toward a specific group/instance. **Context** Calls a function that takes and releases gt->mcr_lockh](h)}(h**Parameters**h]jb)}(hjy3h]h Parameters}(hj{3hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjw3ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjs3ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj3h]hstruct intel_gt *gt}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj3ubj)}(hhh]h)}(h GT structureh]h GT structure}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j|hj3hMhj3ubj})}(h1``i915_mcr_reg_t reg`` the MCR register to write h](j)}(h``i915_mcr_reg_t reg``h]j)}(hj3h]hi915_mcr_reg_t reg}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj3ubj)}(hhh]h)}(hthe MCR register to writeh]hthe MCR register to write}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j|hj3hMhj3ubj})}(h``u32 value`` value to write h](j)}(h ``u32 value``h]j)}(hj 4h]h u32 value}(hj 4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj4ubj)}(hhh]h)}(hvalue to writeh]hvalue to write}(hj#4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMhj 4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1j|hj4hMhj3ubj})}(h``int group`` the MCR group h](j)}(h ``int group``h]j)}(hjC4h]h int group}(hjE4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA4ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj=4ubj)}(hhh]h)}(h the MCR grouph]h the MCR group}(hj\4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjX4hMhjY4ubah}(h]h ]h"]h$]h&]uh1jhj=4ubeh}(h]h ]h"]h$]h&]uh1j|hjX4hMhj3ubj})}(h"``int instance`` the MCR instance h](j)}(h``int instance``h]j)}(hj|4h]h int instance}(hj~4hhhNhNubah}(h]h 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]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjs3ubh)}(h5Calls a function that takes and releases gt->mcr_lockh]h5Calls a function that takes and releases gt->mcr_lock}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjs3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_gt_mcr_multicast_write (C function)c.intel_gt_mcr_multicast_writehNtauh1jhj((hhhNhNubj')}(hhh](j,)}(hVvoid intel_gt_mcr_multicast_write (struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h]j2)}(hUvoid intel_gt_mcr_multicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j)}(hvoidh]hvoid}(hj#5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hj25hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj5hhhj15hMubjz)}(hintel_gt_mcr_multicast_writeh]j;)}(hintel_gt_mcr_multicast_writeh]hintel_gt_mcr_multicast_write}(hjD5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@5ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj5hhhj15hMubj)}(h4(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hj`5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\5ubji)}(h h]h }(hjm5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\5ubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hj~5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{5ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj5modnameN classnameNjXj[)}j^]ja)}jTjF5sbc.intel_gt_mcr_multicast_writeasbuh1hhj\5ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\5ubj)}(hjh]h*}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\5ubj;)}(hgth]hgt}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\5ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjX5ubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj5ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj5modnameN classnameNjXj[)}j^]j5c.intel_gt_mcr_multicast_writeasbuh1hhj5ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj5ubj;)}(hregh]hreg}(hj6hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj5ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjX5ubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj6hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj6ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj6modnameN classnameNjXj[)}j^]j5c.intel_gt_mcr_multicast_writeasbuh1hhj6ubji)}(h h]h }(hj;6hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj6ubj;)}(hvalueh]hvalue}(hjI6hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj6ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjX5ubeh}(h]h ]h"]h$]h&]jjuh1jhj5hhhj15hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj5hhhj15hMubah}(h]j5ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj15hMhj5hhubj1)}(hhh]h)}(h1write a value to all instances of an MCR registerh]h1write a value to all instances of an MCR register}(hjs6hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjp6hhubah}(h]h ]h"]h$]h&]uh1j0hj5hhhj15hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj6jSj6jTjUjVuh1j&hhhj((hNhNubjX)}(hX **Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to write ``u32 value`` value to write **Description** Write an MCR register in multicast mode to update all instances. **Context** Takes and releases gt->mcr_lockh](h)}(h**Parameters**h]jb)}(hj6h]h Parameters}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj6ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj6h]hstruct intel_gt *gt}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6ubj)}(hhh]h)}(h GT structureh]h GT structure}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h 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]h"]h$]h&]uh1jahj_7ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6ubh)}(h@Write an MCR register in multicast mode to update all instances.h]h@Write an MCR register in multicast mode to update all instances.}(hjw7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6ubh)}(h **Context**h]jb)}(hj7h]hContext}(hj7hhhNhNubah}(h]h ]h"]h$] h&]uh1jahj7ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6ubh)}(hTakes and releases gt->mcr_lockh]hTakes and releases gt->mcr_lock}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_gt_mcr_multicast_write_fw (C function)!c.intel_gt_mcr_multicast_write_fwhNtauh1jhj((hhhNhNubj')}(hhh](j,)}(hYvoid intel_gt_mcr_multicast_write_fw (struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h]j2)}(hXvoid intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j)}(hvoidh]hvoid}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hj7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj7hhhj7hMubjz)}(hintel_gt_mcr_multicast_write_fwh]j;)}(hintel_gt_mcr_multicast_write_fwh]hintel_gt_mcr_multicast_write_fw}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj7hhhj7hMubj)}(h4(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hj 8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj8ubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hj(8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%8ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj*8modnameN classnameNjXj[)}j^]ja)}jTj7sb!c.intel_gt_mcr_multicast_write_fwasbuh1hhj8ubji)}(h h]h }(hjH8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj8ubj)}(hjh]h*}(hjV8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj;)}(hgth]hgt}(hjc8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj8ubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|8ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj8modnameN classnameNjXj[)}j^]jD8!c.intel_gt_mcr_multicast_write_fwasbuh1hhjx8ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjx8ubj;)}(hregh]hreg}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjx8ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj8ubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj8modnameN classnameNjXj[)}j^]jD8!c.intel_gt_mcr_multicast_write_fwasbuh1hhj8ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj8ubj;)}(hvalueh]hvalue}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj8ubeh}(h]h ]h"]h$]h&]jjuh1jhj7hhhj7hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj7hhhj7hMubah}(h]j7ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj7hMhj7hhubj1)}(hhh]h)}(h1write a value to all instances of an MCR registerh]h1write a value to all instances of an MCR register}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj9hhubah}(h]h ]h"]h$]h&]uh1j0hj7hhhj7hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj59jSj59jTjUjVuh1j&hhhj((hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to write ``u32 value`` value to write **Description** Write an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically. **Context** The caller must hold gt->mcr_lock.h](h)}(h**Parameters**h]jb)}(hj?9h]h Parameters}(hjA9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj=9ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj99ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj^9h]hstruct intel_gt *gt}(hj`9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\9ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjX9ubj)}(hhh]h)}(h GT structureh]h GT structure}(hjw9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs9hMhjt9ubah}(h]h ]h"]h$]h&]uh1jhjX9ubeh}(h]h ]h"]h$]h&]uh1j|hjs9hMhjU9ubj})}(h1``i915_mcr_reg_t reg`` the MCR register to write h](j)}(h``i915_mcr_reg_t reg``h]j)}(hj9h]hi915_mcr_reg_t reg}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj9ubj)}(hhh]h)}(hthe MCR register to writeh]hthe MCR register to write}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j|hj9hMhjU9ubj})}(h``u32 value`` value to write h](j)}(h ``u32 value``h]j)}(hj9h]h u32 value}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj9ubj)}(hhh]h)}(hvalue to writeh]hvalue to write}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j|hj9hMhjU9ubeh}(h]h ]h"]h$]h&]uh1jwhj99ubh)}(h**Description**h]jb)}(hj :h]h Description}(hj :hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj :ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj99ubh)}(hWrite an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically.h]hWrite an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically.}(hj!:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj99ubh)}(h **Context**h]jb)}(hj2:h]hContext}(hj4:hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj0:ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj99ubh)}(h"The caller must hold gt->mcr_lock.h]h"The caller must hold gt->mcr_lock.}(hjH:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj99ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_gt_mcr_multicast_rmw (C function)c.intel_gt_mcr_multicast_rmwhNtauh1jhj((hhhNhNubj')}(hhh](j,)}(h\u32 intel_gt_mcr_multicast_rmw (struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h]j2)}(h[u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h](h)}(hhh]j;)}(hu32h]hu32}(hjz:hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjw:ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj|:modnameN classnameNjXj[)}j^]ja)}jTintel_gt_mcr_multicast_rmwsbc.intel_gt_mcr_multicast_rmwasbuh1hhjs:hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hj:hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjs:hhhj:hMubjz)}(hintel_gt_mcr_multicast_rmwh]j;)}(hj:h]hintel_gt_mcr_multicast_rmw}(hj:hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj:ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjs:hhhj:hMubj)}(h=(struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubji)}(h h]h }(hj:hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj:ubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hj:hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj:ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj:modnameN classnameNjXj[)}j^]j:c.intel_gt_mcr_multicast_rmwasbuh1hhj:ubji)}(h h]h }(hj;hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj:ubj)}(hjh]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj;)}(hgth]hgt}(hj ;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj:ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj:ubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hj<;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj9;ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj>;modnameN classnameNjXj[)}j^]j:c.intel_gt_mcr_multicast_rmwasbuh1hhj5;ubji)}(h h]h }(hjZ;hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj5;ubj;)}(hregh]hreg}(hjh;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj5;ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj:ubj)}(h u32 clearh](h)}(hhh]j;)}(hu32h]hu32}(hj;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj;modnameN classnameNjXj[)}j^]j:c.intel_gt_mcr_multicast_rmwasbuh1hhj};ubji)}(h h]h }(hj;hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj};ubj;)}(hclearh]hclear}(hj;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj};ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj:ubj)}(hu32 seth](h)}(hhh]j;)}(hu32h]hu32}(hj;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj;modnameN classnameNjXj[)}j^]j:c.intel_gt_mcr_multicast_rmwasbuh1hhj;ubji)}(h h]h }(hj;hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj;ubj;)}(hseth]hset}(hj;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj:ubeh}(h]h ]h"]h$]h&]jjuh1jhjs:hhhj:hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjo:hhhj:hMubah}(h]jj:ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj:hMhjl:hhubj1)}(hhh]h)}(h#Performs a multicast RMW operationsh]h#Performs a multicast RMW operations}(hj"<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj<hhubah}(h]h ]h"]h$]h&]uh1j0hjl:hhhj:hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj:<jSj:<jTjUjVuh1j&hhhj((hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to read and write ``u32 clear`` bits to clear during RMW ``u32 set`` bits to set during RMW **Description** Performs a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically. Returns the old (unmodified) value read. **Context** Calls functions that take and release gt->mcr_lockh](h)}(h**Parameters**h]jb)}(hjD<h]h Parameters}(hjF<hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjB<ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj><ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjc<h]hstruct intel_gt *gt}(hje<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja<ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj]<ubj)}(hhh]h)}(h GT structureh]h GT structure}(hj|<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx<hMhjy<ubah}(h]h ]h"]h$]h&]uh1jhj]<ubeh}(h]h ]h"]h$]h&]uh1j|hjx<hMhjZ<ubj})}(h:``i915_mcr_reg_t reg`` the MCR register to read and write h](j)}(h``i915_mcr_reg_t reg``h]j)}(hj<h]hi915_mcr_reg_t reg}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj<ubj)}(hhh]h)}(h"the MCR register to read and writeh]h"the MCR register to read and write}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1j|hj<hMhjZ<ubj})}(h'``u32 clear`` bits to clear during RMW h](j)}(h ``u32 clear``h]j)}(hj<h]h u32 clear}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj<ubj)}(hhh]h)}(hbits to clear during RMWh]hbits to clear during RMW}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM hj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1j|hj<hM hjZ<ubj})}(h#``u32 set`` bits to set during RMW h](j)}(h ``u32 set``h]j)}(hj=h]hu32 set}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj =ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj=ubj)}(hhh]h)}(hbits to set during RMWh]hbits to set during RMW}(hj'=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#=hM hj$=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1j|hj#=hM hjZ<ubeh}(h]h ]h"]h$]h&]uh1jwhj><ubh)}(h**Description**h]jb)}(hjI=h]h Description}(hjK=hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjG=ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj><ubh)}(hXPerforms a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances.h]hXPerforms a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances.}(hj_=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hj><ubh)}(hThis function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically.h]hThis function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically.}(hjn=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj><ubh)}(h(Returns the old (unmodified) value read.h]h(Returns the old (unmodified) value read.}(hj}=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj><ubh)}(h **Context**h]jb)}(hj=h]hContext}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj=ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj><ubh)}(h2Calls functions that take and release gt->mcr_lockh]h2Calls functions that take and release gt->mcr_lock}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj><ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"4intel_gt_mcr_get_nonterminated_steering (C function))c.intel_gt_mcr_get_nonterminated_steeringhNtauh1jhj((hhhNhNubj')}(hhh](j,)}(hovoid intel_gt_mcr_get_nonterminated_steering (struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h]j2)}(hnvoid intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h](j)}(hvoidh]hvoid}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hj=hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj=hhhj=hMubjz)}(h'intel_gt_mcr_get_nonterminated_steeringh]j;)}(h'intel_gt_mcr_get_nonterminated_steeringh]h'intel_gt_mcr_get_nonterminated_steering}(hj=hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj=ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj=hhhj=hMubj)}(hB(struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj >ubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj >ubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hj.>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+>ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0>modnameN classnameNjXj[)}j^]ja)}jTj=sb)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhj >ubji)}(h h]h }(hjN>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj >ubj)}(hjh]h*}(hj\>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj >ubj;)}(hgth]hgt}(hji>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj >ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj>modnameN classnameNjXj[)}j^]jJ>)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhj~>ubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~>ubj;)}(hregh]hreg}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~>ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubj)}(h u8 *grouph](h)}(hhh]j;)}(hu8h]hu8}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj>modnameN classnameNjXj[)}j^]jJ>)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhj>ubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>ubj)}(hjh]h*}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubj;)}(hgrouph]hgroup}(hj?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubj)}(h u8 *instanceh](h)}(hhh]j;)}(hu8h]hu8}(hj"?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj?ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj$?modnameN classnameNjXj[)}j^]jJ>)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhj?ubji)}(h h]h }(hj@?hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?ubj)}(hjh]h*}(hjN?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj;)}(hinstanceh]hinstance}(hj[?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj?ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubeh}(h]h ]h"]h$]h&]jjuh1jhj=hhhj=hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj=hhhj=hMubah}(h]j=ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj=hMhj=hhubj1)}(hhh]h)}(hRfind group/instance values that will steer a register to a non-terminated instanceh]hRfind group/instance values that will steer a register to a non-terminated instance}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj?hhubah}(h]h ]h"]h$]h&]uh1j0hj=hhhj=hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj?jSj?jTjUjVuh1j&hhhj((hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` register for which the steering is required ``u8 *group`` return variable for group steering ``u8 *instance`` return variable for instance steering **Description** This function returns a group/instance pair that is guaranteed to work for read steering of the given register. Note that a value will be returned even if the register is not replicated and therefore does not actually require steering.h](h)}(h**Parameters**h]jb)}(hj?h]h Parameters}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj?ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj?h]hstruct intel_gt *gt}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj?ubj)}(hhh]h)}(h GT structureh]h GT structure}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j|hj?hMhj?ubj})}(hC``i915_mcr_reg_t reg`` register for which the steering is required h](j)}(h``i915_mcr_reg_t reg``h]j)}(hj?h]hi915_mcr_reg_t reg}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj?ubj)}(hhh]h)}(h+register for which the steering is requiredh]h+register for which the steering is required}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j|hj@hMhj?ubj})}(h1``u8 *group`` return variable for group steering h](j)}(h ``u8 *group``h]j)}(hj8@h]h u8 *group}(hj:@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6@ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj2@ubj)}(hhh]h)}(h"return variable for group steeringh]h"return variable for group steering}(hjQ@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM@hMhjN@ubah}(h]h ]h"]h$]h&]uh1jhj2@ubeh}(h]h ]h"]h$]h&]uh1j|hjM@hMhj?ubj})}(h7``u8 *instance`` return variable for instance steering h](j)}(h``u8 *instance``h]j)}(hjq@h]h u8 *instance}(hjs@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo@ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjk@ubj)}(hhh]h)}(h%return variable for instance steeringh]h%return variable for instance steering}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhjk@ubeh}(h]h ]h"]h$]h&]uh1j|hj@hMhj?ubeh}(h]h ]h"]h$]h&]uh1jwhj?ubh)}(h**Description**h]jb)}(hj@h]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj@ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj?ubh)}(hThis function returns a group/instance pair that is guaranteed to work for read steering of the given register. Note that a value will be returned even if the register is not replicated and therefore does not actually require steering.h]hThis function returns a group/instance pair that is guaranteed to work for read steering of the given register. Note that a value will be returned even if the register is not replicated and therefore does not actually require steering.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_gt_mcr_read_any_fw (C function)c.intel_gt_mcr_read_any_fwhNtauh1jhj((hhhNhNubj')}(hhh](j,)}(hFu32 intel_gt_mcr_read_any_fw (struct intel_gt *gt, i915_mcr_reg_t reg)h]j2)}(hEu32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg)h](h)}(hhh]j;)}(hu32h]hu32}(hj@hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj@modnameN classnameNjXj[)}j^]ja)}jTintel_gt_mcr_read_any_fwsbc.intel_gt_mcr_read_any_fwasbuh1hhj@hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@hhhjAhMubjz)}(hintel_gt_mcr_read_any_fwh]j;)}(hjAh]hintel_gt_mcr_read_any_fw}(hj(AhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$Aubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj@hhhjAhMubj)}(h)(struct intel_gt *gt, i915_mcr_reg_t reg)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hjCAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?Aubji)}(h h]h }(hjPAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?Aubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjaAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj^Aubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjcAmodnameN classnameNjXj[)}j^]jAc.intel_gt_mcr_read_any_fwasbuh1hhj?Aubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?Aubj)}(hjh]h*}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?Aubj;)}(hgth]hgt}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj?Aubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj;Aubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjAmodnameN classnameNjXj[)}j^]jAc.intel_gt_mcr_read_any_fwasbuh1hhjAubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAubj;)}(hregh]hreg}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj;Aubeh}(h]h ]h"]h$]h&]jjuh1jhj@hhhjAhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj@hhhjAhMubah}(h]j@ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjAhMhj@hhubj1)}(hhh]h)}(h%reads one instance of an MCR registerh]h%reads one instance of an MCR register}(hj BhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj Bhhubah}(h]h ]h"]h$]h&]uh1j0hj@hhhjAhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj$BjSj$BjTjUjVuh1j&hhhj((hNhNubjX)}(hX **Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` register to read **Description** Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically. Returns the value from a non-terminated instance of **reg**. **Context** The caller must hold gt->mcr_lock.h](h)}(h**Parameters**h]jb)}(hj.Bh]h Parameters}(hj0BhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,Bubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj(Bubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjMBh]hstruct intel_gt *gt}(hjOBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKBubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGBubj)}(hhh]h)}(h GT structureh]h GT structure}(hjfBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbBhMhjcBubah}(h]h ]h"]h$]h&]uh1jhjGBubeh}(h]h ]h"]h$]h&]uh1j|hjbBhMhjDBubj})}(h(``i915_mcr_reg_t reg`` register to read h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjBh]hi915_mcr_reg_t reg}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjBubj)}(hhh]h)}(hregister to readh]hregister to read}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1j|hjBhMhjDBubeh}(h]h ]h"]h$]h&]uh1jwhj(Bubh)}(h**Description**h]jb)}(hjBh]h Description}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjBubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj(Bubh)}(hX=Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically.h]hX?Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn’t fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj(Bubh)}(hmcr_lock.h]h"The caller must hold gt->mcr_lock.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj(Bubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_gt_mcr_read_any (C function)c.intel_gt_mcr_read_anyhNtauh1jhj((hhhNhNubj')}(hhh](j,)}(hCu32 intel_gt_mcr_read_any (struct intel_gt *gt, i915_mcr_reg_t reg)h]j2)}(hBu32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg)h](h)}(hhh]j;)}(hu32h]hu32}(hjQChhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNCubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjSCmodnameN classnameNjXj[)}j^]ja)}jTintel_gt_mcr_read_anysbc.intel_gt_mcr_read_anyasbuh1hhjJChhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hjsChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJChhhjrChMubjz)}(hintel_gt_mcr_read_anyh]j;)}(hjoCh]hintel_gt_mcr_read_any}(hjChhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjJChhhjrChMubj)}(h)(struct intel_gt *gt, i915_mcr_reg_t reg)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjCubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjChhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjCmodnameN classnameNjXj[)}j^]jmCc.intel_gt_mcr_read_anyasbuh1hhjCubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjCubj)}(hjh]h*}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubj;)}(hgth]hgt}(hjChhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjCubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjDubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjDmodnameN classnameNjXj[)}j^]jmCc.intel_gt_mcr_read_anyasbuh1hhj Dubji)}(h h]h }(hj1DhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj Dubj;)}(hregh]hreg}(hj?DhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj Dubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjCubeh}(h]h ]h"]h$]h&]jjuh1jhjJChhhjrChMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjFChhhjrChMubah}(h]jACah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjrChMhjCChhubj1)}(hhh]h)}(h%reads one instance of an MCR registerh]h%reads one instance of an MCR register}(hjiDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjfDhhubah}(h]h ]h"]h$]h&]uh1j0hjCChhhjrChMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjDjSjDjTjUjVuh1j&hhhj((hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` register to read **Description** Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). Returns the value from a non-terminated instance of **reg**. **Context** Calls a function that takes and releases gt->mcr_lock.h](h)}(h**Parameters**h]jb)}(hjDh]h Parameters}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjDubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjDh]hstruct intel_gt *gt}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubj)}(hhh]h)}(h GT structureh]h GT structure}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j|hjDhMhjDubj})}(h(``i915_mcr_reg_t reg`` register to read h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjDh]hi915_mcr_reg_t reg}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubj)}(hhh]h)}(hregister to readh]hregister to read}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j|hjDhMhjDubeh}(h]h ]h"]h$]h&]uh1jwhjDubh)}(h**Description**h]jb)}(hjEh]h Description}(hj EhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjEubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubh)}(hReads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating).h]hReads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn’t fused off or powered down by power gating).}(hj4EhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubh)}(hmcr_lock.h]h6Calls a function that takes and releases gt->mcr_lock.}(hj|EhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_gt_mcr_get_ss_steering (C function)c.intel_gt_mcr_get_ss_steeringhNtauh1jhj((hhhNhNubj')}(hhh](j,)}(hvvoid intel_gt_mcr_get_ss_steering (struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance)h]j2)}(huvoid intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance)h](j)}(hvoidh]hvoid}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM ubji)}(h h]h }(hjEhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEhhhjEhM ubjz)}(hintel_gt_mcr_get_ss_steeringh]j;)}(hintel_gt_mcr_get_ss_steeringh]hintel_gt_mcr_get_ss_steering}(hjEhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjEhhhjEhM ubj)}(hT(struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubji)}(h h]h }(hjEhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjFmodnameN classnameNjXj[)}j^]ja)}jTjEsbc.intel_gt_mcr_get_ss_steeringasbuh1hhjEubji)}(h h]h }(hj&FhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubj)}(hjh]h*}(hj4FhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj;)}(hgth]hgt}(hjAFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjEubj)}(hunsigned int dssh](j)}(hunsignedh]hunsigned}(hjZFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVFubji)}(h h]h }(hjhFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVFubj)}(hinth]hint}(hjvFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVFubji)}(h h]h }(hjFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVFubj;)}(hdssh]hdss}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVFubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjEubj)}(hunsigned int *grouph](j)}(hunsignedh]hunsigned}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubji)}(h h]h }(hjFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjFubj)}(hinth]hint}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubji)}(h h]h }(hjFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjFubj)}(hjh]h*}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubj;)}(hgrouph]hgroup}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjEubj)}(hunsigned int *instanceh](j)}(hunsignedh]hunsigned}(hj GhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubji)}(h h]h }(hjGhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjGubj)}(hinth]hint}(hj%GhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubji)}(h h]h }(hj3GhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjGubj)}(hjh]h*}(hjAGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj;)}(hinstanceh]hinstance}(hjNGhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjGubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjEubeh}(h]h ]h"]h$]h&]jjuh1jhjEhhhjEhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjEhhhjEhM ubah}(h]jEah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjEhM hjEhhubj1)}(hhh]h)}(h,returns the group/instance steering for a SSh]h,returns the group/instance steering for a SS}(hjxGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjuGhhubah}(h]h ]h"]h$]h&]uh1j0hjEhhhjEhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjGjSjGjTjUjVuh1j&hhhj((hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``unsigned int dss`` DSS ID to obtain steering for ``unsigned int *group`` pointer to storage for steering group ID ``unsigned int *instance`` pointer to storage for steering instance ID **Description** Returns the steering IDs (via the **group** and **instance** parameters) that correspond to a specific subslice/DSS ID.h](h)}(h**Parameters**h]jb)}(hjGh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjGubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjGh]hstruct intel_gt *gt}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubj)}(hhh]h)}(h GT structureh]h GT structure}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1j|hjGhMhjGubj})}(h3``unsigned int dss`` DSS ID to obtain steering for h](j)}(h``unsigned int dss``h]j)}(hjGh]hunsigned int dss}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubj)}(hhh]h)}(hDSS ID to obtain steering forh]hDSS ID to obtain steering for}(hj HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMhjHubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1j|hjHhMhjGubj})}(hA``unsigned int *group`` pointer to storage for steering group ID h](j)}(h``unsigned int *group``h]j)}(hj+Hh]hunsigned int *group}(hj-HhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)Hubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj%Hubj)}(hhh]h)}(h(pointer to storage for steering group IDh]h(pointer to storage for steering group ID}(hjDHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@HhMhjAHubah}(h]h ]h"]h$]h&]uh1jhj%Hubeh}(h]h ]h"]h$]h&]uh1j|hj@HhMhjGubj})}(hG``unsigned int *instance`` pointer to storage for steering instance ID h](j)}(h``unsigned int *instance``h]j)}(hjdHh]hunsigned int *instance}(hjfHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbHubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj^Hubj)}(hhh]h)}(h+pointer to storage for steering instance IDh]h+pointer to storage for steering instance ID}(hj}HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyHhMhjzHubah}(h]h ]h"]h$]h&]uh1jhj^Hubeh}(h]h ]h"]h$]h&]uh1j|hjyHhMhjGubeh}(h]h ]h"]h$]h&]uh1jwhjGubh)}(h**Description**h]jb)}(hjHh]h Description}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjHubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubh)}(hwReturns the steering IDs (via the **group** and **instance** parameters) that correspond to a specific subslice/DSS ID.h](h"Returns the steering IDs (via the }(hjHhhhNhNubjb)}(h **group**h]hgroup}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjHubh and }(hjHhhhNhNubjb)}(h **instance**h]hinstance}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjHubh; parameters) that correspond to a specific subslice/DSS ID.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_gt_mcr_wait_for_reg (C function)c.intel_gt_mcr_wait_for_reghNtauh1jhj((hhhNhNubj')}(hhh](j,)}(hint intel_gt_mcr_wait_for_reg (struct intel_gt *gt, i915_mcr_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms)h]j2)}(hint intel_gt_mcr_wait_for_reg(struct intel_gt *gt, i915_mcr_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms)h](j)}(hinth]hint}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMKubji)}(h h]h }(hjIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIhhhjIhMKubjz)}(hintel_gt_mcr_wait_for_regh]j;)}(hintel_gt_mcr_wait_for_regh]hintel_gt_mcr_wait_for_reg}(hj)IhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%Iubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjIhhhjIhMKubj)}(hz(struct intel_gt *gt, i915_mcr_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hjEIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAIubji)}(h h]h }(hjRIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAIubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjcIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`Iubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjeImodnameN classnameNjXj[)}j^]ja)}jTj+Isbc.intel_gt_mcr_wait_for_regasbuh1hhjAIubji)}(h h]h }(hjIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAIubj)}(hjh]h*}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAIubj;)}(hgth]hgt}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAIubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Iubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjImodnameN classnameNjXj[)}j^]jIc.intel_gt_mcr_wait_for_regasbuh1hhjIubji)}(h h]h }(hjIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIubj;)}(hregh]hreg}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Iubj)}(hu32 maskh](h)}(hhh]j;)}(hu32h]hu32}(hjJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjJmodnameN classnameNjXj[)}j^]jIc.intel_gt_mcr_wait_for_regasbuh1hhjIubji)}(h h]h }(hj JhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIubj;)}(hmaskh]hmask}(hj.JhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Iubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hjJJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjGJubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjLJmodnameN classnameNjXj[)}j^]jIc.intel_gt_mcr_wait_for_regasbuh1hhjCJubji)}(h h]h }(hjhJhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjCJubj;)}(hvalueh]hvalue}(hjvJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCJubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Iubj)}(hunsigned int fast_timeout_ush](j)}(hunsignedh]hunsigned}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubji)}(h h]h }(hjJhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJubj)}(hinth]hint}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubji)}(h h]h }(hjJhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJubj;)}(hfast_timeout_ush]hfast_timeout_us}(hjJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjJubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Iubj)}(hunsigned int slow_timeout_msh](j)}(hunsignedh]hunsigned}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubji)}(h h]h }(hjJhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJubj)}(hinth]hint}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubji)}(h h]h }(hj KhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJubj;)}(hslow_timeout_msh]hslow_timeout_ms}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjJubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Iubeh}(h]h ]h"]h$]h&]jjuh1jhjIhhhjIhMKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjIhhhjIhMKubah}(h]jHah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjIhMKhjHhhubj1)}(hhh]h)}(h.wait until MCR register matches expected stateh]h.wait until MCR register matches expected state}(hjBKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM.hj?Khhubah}(h]h ]h"]h$]h&]uh1j0hjHhhhjIhMKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjZKjSjZKjTjUjVuh1j&hhhj((hNhNubjX)}(hX **Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the register to read ``u32 mask`` mask to apply to register value ``u32 value`` value to wait for ``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait ``unsigned int slow_timeout_ms`` slow timeout in millisecond **Description** This routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until :: (intel_gt_mcr_read_any_fw(gt, reg) & mask) == value Otherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds. This function is basically an MCR-friendly version of __intel_wait_for_register_fw(). Generally this function will only be used on GAM registers which are a bit special --- although they're MCR registers, reads (e.g., waiting for status updates) are always directed to the primary instance. Note that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. **Context** Calls a function that takes and releases gt->mcr_lock **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]jb)}(hjdKh]h Parameters}(hjfKhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjbKubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM2hj^Kubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjKh]hstruct intel_gt *gt}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM/hj}Kubj)}(hhh]h)}(h GT structureh]h GT structure}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM/hjKubah}(h]h ]h"]h$]h&]uh1jhj}Kubeh}(h]h ]h"]h$]h&]uh1j|hjKhM/hjzKubj})}(h,``i915_mcr_reg_t reg`` the register to read h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjKh]hi915_mcr_reg_t reg}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM0hjKubj)}(hhh]h)}(hthe register to readh]hthe register to read}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM0hjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1j|hjKhM0hjzKubj})}(h-``u32 mask`` mask to apply to register value h](j)}(h ``u32 mask``h]j)}(hjKh]hu32 mask}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM1hjKubj)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj LhM1hj Lubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1j|hj LhM1hjzKubj})}(h ``u32 value`` value to wait for h](j)}(h ``u32 value``h]j)}(hj.Lh]h u32 value}(hj0LhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,Lubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM2hj(Lubj)}(hhh]h)}(hvalue to wait forh]hvalue to wait for}(hjGLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCLhM2hjDLubah}(h]h ]h"]h$]h&]uh1jhj(Lubeh}(h]h ]h"]h$]h&]uh1j|hjCLhM2hjzKubj})}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j)}(h ``unsigned int fast_timeout_us``h]j)}(hjgLh]hunsigned int fast_timeout_us}(hjiLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeLubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM3hjaLubj)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|LhM3hj}Lubah}(h]h ]h"]h$]h&]uh1jhjaLubeh}(h]h ]h"]h$]h&]uh1j|hj|LhM3hjzKubj})}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j)}(h ``unsigned int slow_timeout_ms``h]j)}(hjLh]hunsigned int slow_timeout_ms}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM4hjLubj)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM4hjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjLhM4hjzKubeh}(h]h ]h"]h$]h&]uh1jwhj^Kubh)}(h**Description**h]jb)}(hjLh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjLubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM6hj^Kubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hjLhhhNhNubjb)}(h**reg**h]hreg}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjLubh contains the expected }(hjLhhhNhNubjb)}(h **value**h]hvalue}(hj MhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjLubh after applying the }(hjLhhhNhNubjb)}(h**mask**h]hmask}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjLubh, i.e. it waits until}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM6hj^Kubj")}(h3(intel_gt_mcr_read_any_fw(gt, reg) & mask) == valueh]h3(intel_gt_mcr_read_any_fw(gt, reg) & mask) == value}hj6Msbah}(h]h ]h"]h$]h&]jjuh1j"h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM9hj^Kubh)}(hOtherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds.h](h'Otherwise, the wait will timeout after }(hjEMhhhNhNubjb)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hjMMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjEMubh" milliseconds. For atomic context }(hjEMhhhNhNubjb)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hj_MhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjEMubh must be zero and }(hjEMhhhNhNubjb)}(h**fast_timeout_us**h]hfast_timeout_us}(hjqMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjEMubh. must be not larger than 20,0000 microseconds.}(hjEMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM;hj^Kubh)}(hX#This function is basically an MCR-friendly version of __intel_wait_for_register_fw(). Generally this function will only be used on GAM registers which are a bit special --- although they're MCR registers, reads (e.g., waiting for status updates) are always directed to the primary instance.h]hX%This function is basically an MCR-friendly version of __intel_wait_for_register_fw(). Generally this function will only be used on GAM registers which are a bit special --- although they’re MCR registers, reads (e.g., waiting for status updates) are always directed to the primary instance.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM?hj^Kubh)}(hkNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits.h]hkNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMEhj^Kubh)}(h **Context**h]jb)}(hjMh]hContext}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjMubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMHhj^Kubh)}(h5Calls a function that takes and releases gt->mcr_lockh]h5Calls a function that takes and releases gt->mcr_lock}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMHhj^Kubh)}(h **Return**h]jb)}(hjMh]hReturn}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjMubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMJhj^Kubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMIhj^Kubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj((hhhNhNubeh}(h]"multicast-replicated-mcr-registersah ]h"]$multicast/replicated (mcr) registersah$]h&]uh1hhj(hhhhhMubeh}(h]gt-programmingah ]h"]gt programmingah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h(Memory Management and Command Submissionh]h(Memory Management and Command Submission}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj NhhhhhM ubh)}(hUThis sections covers all things related to the GEM implementation in the i915 driver.h]hUThis sections covers all things related to the GEM implementation in the i915 driver.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj Nhhubh)}(hhh](h)}(hIntel GPU Basicsh]hIntel GPU Basics}(hj/NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,NhhhhhMubh)}(hBAn Intel GPU has multiple engines. There are several engine types:h]hBAn Intel GPU has multiple engines. There are several engine types:}(hj=NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,Nhhubj:)}(hhh](j:)}(hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.h]h)}(hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.h]hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.}(hjRNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNNubah}(h]h ]h"]h$]h&]uh1j:hjKNhhhhhNubj:)}(h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.h]h)}(h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.h]h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.}(hjjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfNubah}(h]h ]h"]h$]h&]uh1j:hjKNhhhhhNubj:)}(h~Video Command Streamer. An engine used for video encoding and decoding. Also sometimes called 'BSD' in hardware documentation.h]h)}(h~Video Command Streamer. An engine used for video encoding and decoding. Also sometimes called 'BSD' in hardware documentation.h]hVideo Command Streamer. An engine used for video encoding and decoding. Also sometimes called ‘BSD’ in hardware documentation.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj~Nubah}(h]h ]h"]h$]h&]uh1j:hjKNhhhhhNubj:)}(hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called 'VEBOX' in hardware documentation.h]h)}(hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called 'VEBOX' in hardware documentation.h]hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called ‘VEBOX’ in hardware documentation.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNubah}(h]h ]h"]h$]h&]uh1j:hjKNhhhhhNubj:)}(htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.h]h)}(htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.h]htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNubah}(h]h ]h"]h$]h&]uh1j:hjKNhhhhhNubj:)}(hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication. h]h)}(hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication.h]hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjNubah}(h]h ]h"]h$]h&]uh1j:hjKNhhhhhNubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hhhMhj,Nhhubh)}(hXThe Intel GPU family is a family of integrated GPU's using Unified Memory Access. For having the GPU "do work", user space will feed the GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will instruct the GPU to perform work (for example rendering) and that work needs memory from which to read and memory to which to write. All memory is encapsulated within GEM buffer objects (usually created with the ioctl `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU to create will also list all GEM buffer objects that the batchbuffer reads and/or writes. For implementation details of memory management see `GEM BO Management Implementation Details`_.h](hThe Intel GPU family is a family of integrated GPU’s using Unified Memory Access. For having the GPU “do work”, user space will feed the GPU batch buffers via one of the ioctls }(hjNhhhNhNubhtitle_reference)}(h `DRM_IOCTL_I915_GEM_EXECBUFFER2`h]hDRM_IOCTL_I915_GEM_EXECBUFFER2}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jNhjNubh or }(hjNhhhNhNubjN)}(h#`DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`h]h!DRM_IOCTL_I915_GEM_EXECBUFFER2_WR}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jNhjNubh. Most such batchbuffers will instruct the GPU to perform work (for example rendering) and that work needs memory from which to read and memory to which to write. All memory is encapsulated within GEM buffer objects (usually created with the ioctl }(hjNhhhNhNubjN)}(h`DRM_IOCTL_I915_GEM_CREATE`h]hDRM_IOCTL_I915_GEM_CREATE}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jNhjNubh). An ioctl providing a batchbuffer for the GPU to create will also list all GEM buffer objects that the batchbuffer reads and/or writes. For implementation details of memory management see }(hjNhhhNhNubj!5)}(h+`GEM BO Management Implementation Details`_h]h(GEM BO Management Implementation Details}(hj$OhhhNhNubah}(h]h ]h"]h$]h&]name(GEM BO Management Implementation Detailsj:(gem-bo-management-implementation-detailsuh1j 5hjNj:Kubh.}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM%hj,Nhhubh)}(hXThe i915 driver allows user space to create a context via the ioctl `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit integer. Such a context should be viewed by user-space as -loosely- analogous to the idea of a CPU process of an operating system. The i915 driver guarantees that commands issued to a fixed context are to be executed so that writes of a previously issued command are seen by reads of following commands. Actions issued between different contexts (even if from the same file descriptor) are NOT given that guarantee and the only way to synchronize across contexts (even from the same file descriptor) is through the use of fences. At least as far back as Gen4, also have that a context carries with it a GPU HW context; the HW context is essentially (most of at least) the state of a GPU. In addition to the ordering guarantees, the kernel will restore GPU state via HW context when commands are issued to a context, this saves user space the need to restore (most of at least) the GPU state at the start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use with the command.h](hDThe i915 driver allows user space to create a context via the ioctl }(hj?OhhhNhNubjN)}(h#`DRM_IOCTL_I915_GEM_CONTEXT_CREATE`h]h!DRM_IOCTL_I915_GEM_CONTEXT_CREATE}(hjGOhhhNhNubah}(h]h ]h"]h$]h&]uh1jNhj?OubhXl which is identified by a 32-bit integer. Such a context should be viewed by user-space as -loosely- analogous to the idea of a CPU process of an operating system. The i915 driver guarantees that commands issued to a fixed context are to be executed so that writes of a previously issued command are seen by reads of following commands. Actions issued between different contexts (even if from the same file descriptor) are NOT given that guarantee and the only way to synchronize across contexts (even from the same file descriptor) is through the use of fences. At least as far back as Gen4, also have that a context carries with it a GPU HW context; the HW context is essentially (most of at least) the state of a GPU. In addition to the ordering guarantees, the kernel will restore GPU state via HW context when commands are issued to a context, this saves user space the need to restore (most of at least) the GPU state at the start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use with the command.}(hj?OhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM1hj,Nhhubh)}(hXThe GPU has its own memory management and address space. The kernel driver maintains the memory translation table for the GPU. For older GPUs (i.e. those before Gen8), there is a single global such translation table, a global Graphics Translation Table (GTT). For newer generation GPUs each context has its own translation table, called Per-Process Graphics Translation Table (PPGTT). Of important note, is that although PPGTT is named per-process it is actually per context. When user space submits a batchbuffer, the kernel walks the list of GEM buffer objects used by the batchbuffer and guarantees that not only is the memory of each such GEM buffer object resident but it is also present in the (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, then it is given an address. Two consequences of this are: the kernel needs to edit the batchbuffer submitted to write the correct value of the GPU address when a GEM BO is assigned a GPU address and the kernel might evict a different GEM BO from the (PP)GTT to make address room for another GEM BO. Consequently, the ioctls submitting a batchbuffer for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation.h]hXThe GPU has its own memory management and address space. The kernel driver maintains the memory translation table for the GPU. For older GPUs (i.e. those before Gen8), there is a single global such translation table, a global Graphics Translation Table (GTT). For newer generation GPUs each context has its own translation table, called Per-Process Graphics Translation Table (PPGTT). Of important note, is that although PPGTT is named per-process it is actually per context. When user space submits a batchbuffer, the kernel walks the list of GEM buffer objects used by the batchbuffer and guarantees that not only is the memory of each such GEM buffer object resident but it is also present in the (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, then it is given an address. Two consequences of this are: the kernel needs to edit the batchbuffer submitted to write the correct value of the GPU address when a GEM BO is assigned a GPU address and the kernel might evict a different GEM BO from the (PP)GTT to make address room for another GEM BO. Consequently, the ioctls submitting a batchbuffer for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation.}(hj_OhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhj,Nhhubeh}(h]intel-gpu-basicsah ]h"]intel gpu basicsah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(hLocking Guidelinesh]hLocking Guidelines}(hjxOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuOhhhhhMYubhnote)}(hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.h]h)}(hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.h]hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hjOubah}(h]h ]h"]h$]h&]uh1jOhjuOhhhhhNubj:)}(hhh](j:)}(hqAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed. h]h)}(hpAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed.h]hpAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjOubah}(h]h ]h"]h$]h&]uh1j:hjOhhhhhNubj:)}(h%No struct_mutex anywhere in the code h]h)}(h$No struct_mutex anywhere in the codeh]h$No struct_mutex anywhere in the code}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchjOubah}(h]h ]h"]h$]h&]uh1j:hjOhhhhhNubj:)}(hdma_resv will be the outermost lock (when needed) and ww_acquire_ctx is to be hoisted at highest level and passed down within i915_gem_ctx in the call chain h]h)}(hdma_resv will be the outermost lock (when needed) and ww_acquire_ctx is to be hoisted at highest level and passed down within i915_gem_ctx in the call chainh]hdma_resv will be the outermost lock (when needed) and ww_acquire_ctx is to be hoisted at highest level and passed down within i915_gem_ctx in the call chain}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjOubah}(h]h ]h"]h$]h&]uh1j:hjOhhhhhNubj:)}(hX>While holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowed * Enforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad. h](h)}(hjWhile holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowedh]hjWhile holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowed}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjOubjL)}(h* Enforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad. h]j:)}(hhh]j:)}(hEnforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad. h]h)}(hEnforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad.h]hEnforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjPubah}(h]h ]h"]h$]h&]uh1j:hjPubah}(h]h ]h"]h$]h&]j[;juh1j:hhhMlhjOubah}(h]h ]h"]h$]h&]uh1jKhhhMlhjOubeh}(h]h ]h"]h$]h&]uh1j:hjOhhhhhNubj:)}(hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations. h]h)}(hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations.h]hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations.}(hj2PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhj.Pubah}(h]h ]h"]h$]h&]uh1j:hjOhhhhhNubj:)}(h\The suggestion for lru/memory managers locks is that they are small enough to be spinlocks. h]h)}(h[The suggestion for lru/memory managers locks is that they are small enough to be spinlocks.h]h[The suggestion for lru/memory managers locks is that they are small enough to be spinlocks.}(hjJPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhjFPubah}(h]h ]h"]h$]h&]uh1j:hjOhhhhhNubj:)}(h]All features need to come with exhaustive kernel selftests and/or IGT tests when appropriate h]h)}(h\All features need to come with exhaustive kernel selftests and/or IGT tests when appropriateh]h\All features need to come with exhaustive kernel selftests and/or IGT tests when appropriate}(hjbPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhj^Pubah}(h]h ]h"]h$]h&]uh1j:hjOhhhhhNubj:)}(hXAll LMEM uAPI paths need to be fully restartable (_interruptible() for all locks/waits/sleeps) * Error handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases. * -EDEADLK handling with ww_mutex h](h)}(h^All LMEM uAPI paths need to be fully restartable (_interruptible() for all locks/waits/sleeps)h]h^All LMEM uAPI paths need to be fully restartable (_interruptible() for all locks/waits/sleeps)}(hjzPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjvPubjL)}(hX* Error handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases. * -EDEADLK handling with ww_mutex h]j:)}(hhh](j:)}(hError handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases. h]h)}(hError handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases.h]hError handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjPubah}(h]h ]h"]h$]h&]uh1j:hjPubj:)}(h -EDEADLK handling with ww_mutex h]h)}(h-EDEADLK handling with ww_mutexh]h-EDEADLK handling with ww_mutex}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPubah}(h]h ]h"]h$]h&]uh1j:hjPubeh}(h]h ]h"]h$]h&]j[;juh1j:hhhM~hjPubah}(h]h ]h"]h$]h&]uh1jKhhhM~hjvPubeh}(h]h ]h"]h$]h&]uh1j:hjOhhhhhNubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hjuOhhhhhM`ubeh}(h]locking-guidelinesah ]h"]locking guidelinesah$]h&]uh1hhj NhhhhhMYubh)}(hhh](h)}(h(GEM BO Management Implementation Detailsh]h(GEM BO Management Implementation Details}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhhhhhMubh)}(hA VMA represents a GEM BO that is bound into an address space. Therefore, a VMA's presence cannot be guaranteed before binding, or after unbinding the object into/from the address space.h]hA VMA represents a GEM BO that is bound into an address space. Therefore, a VMA’s presence cannot be guaranteed before binding, or after unbinding the object into/from the address space.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:393: ./drivers/gpu/drm/i915/i915_vma_types.hhK~hjPhhubh)}(hTo make things as simple as possible (ie. no refcounting), a VMA's lifetime will always be <= an objects lifetime. So object refcounting should cover us.h]hTo make things as simple as possible (ie. no refcounting), a VMA’s lifetime will always be <= an objects lifetime. So object refcounting should cover us.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:393: ./drivers/gpu/drm/i915/i915_vma_types.hhKhjPhhubeh}(h]j4Oah ]h"](gem bo management implementation detailsah$]h&]uh1hhj NhhhhhMj<Kubh)}(hhh](h)}(hBuffer Object Evictionh]hBuffer Object Eviction}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhhhhhMubh)}(hX=This section documents the interface functions for evicting buffer objects to make space available in the virtual gpu address spaces. Note that this is mostly orthogonal to shrinking buffer objects caches, which has the goal to make main memory (shared with the gpu through the unified memory architecture) available.h]hX=This section documents the interface functions for evicting buffer objects to make space available in the virtual gpu address spaces. Note that this is mostly orthogonal to shrinking buffer objects caches, which has the goal to make main memory (shared with the gpu through the unified memory architecture) available.}(hj&QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjQhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%i915_gem_evict_something (C function)c.i915_gem_evict_somethinghNtauh1jhjQhhhNhNubj')}(hhh](j,)}(hint i915_gem_evict_something (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, u64 min_size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned flags)h]j2)}(hint i915_gem_evict_something(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, u64 min_size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned flags)h](j)}(hinth]hint}(hjMQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIQhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKubji)}(h h]h }(hj\QhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIQhhhj[QhKubjz)}(hi915_gem_evict_somethingh]j;)}(hi915_gem_evict_somethingh]hi915_gem_evict_something}(hjnQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjQubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjIQhhhj[QhKubj)}(h(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, u64 min_size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned flags)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjQmodnameN classnameNjXj[)}j^]ja)}jTjpQsbc.i915_gem_evict_somethingasbuh1hhjQubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj)}(hjh]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj;)}(hvmh]hvm}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hj RhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjRmodnameN classnameNjXj[)}j^]jQc.i915_gem_evict_somethingasbuh1hhjQubji)}(h h]h }(hj8RhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj)}(hjh]h*}(hjFRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj;)}(hwwh]hww}(hjSRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(h u64 min_sizeh](h)}(hhh]j;)}(hu64h]hu64}(hjoRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjlRubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjqRmodnameN classnameNjXj[)}j^]jQc.i915_gem_evict_somethingasbuh1hhjhRubji)}(h h]h }(hjRhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhRubj;)}(hmin_sizeh]hmin_size}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhRubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(h u64 alignmenth](h)}(hhh]j;)}(hu64h]hu64}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjRmodnameN classnameNjXj[)}j^]jQc.i915_gem_evict_somethingasbuh1hhjRubji)}(h h]h }(hjRhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj;)}(h alignmenth]h alignment}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(hunsigned long colorh](j)}(hunsignedh]hunsigned}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubji)}(h h]h }(hj ShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj)}(hlongh]hlong}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubji)}(h h]h }(hj&ShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj;)}(hcolorh]hcolor}(hj4ShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(h u64 starth](h)}(hhh]j;)}(hu64h]hu64}(hjPShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjMSubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjRSmodnameN classnameNjXj[)}j^]jQc.i915_gem_evict_somethingasbuh1hhjISubji)}(h h]h }(hjnShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjISubj;)}(hstarth]hstart}(hj|ShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjISubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(hu64 endh](h)}(hhh]j;)}(hu64h]hu64}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjSmodnameN classnameNjXj[)}j^]jQc.i915_gem_evict_somethingasbuh1hhjSubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubj;)}(hendh]hend}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(hunsigned flagsh](j)}(hunsignedh]hunsigned}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubj;)}(hflagsh]hflags}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubeh}(h]h ]h"]h$]h&]jjuh1jhjIQhhhj[QhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjEQhhhj[QhKubah}(h]j@Qah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj[QhKhjBQhhubj1)}(hhh]h)}(h-Evict vmas to make room for binding a new oneh]h-Evict vmas to make room for binding a new one}(hj#ThhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chK|hj Thhubah}(h]h ]h"]h$]h&]uh1j0hjBQhhhj[QhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj;TjSj;TjTjUjVuh1j&hhhjQhNhNubjX)}(hXd**Parameters** ``struct i915_address_space *vm`` address space to evict from ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``u64 min_size`` size of the desired free space ``u64 alignment`` alignment constraint of the desired free space ``unsigned long color`` color for the desired space ``u64 start`` start (inclusive) of the range from which to evict objects ``u64 end`` end (exclusive) of the range from which to evict objects ``unsigned flags`` additional flags to control the eviction algorithm **Description** This function will try to evict vmas until a free space satisfying the requirements is found. Callers must check first whether any such hole exists already before calling this function. This function is used by the object/vma binding code. Since this function is only used to free up virtual address space it only ignores pinned vmas, and not object where the backing storage itself is pinned. Hence obj->pages_pin_count does not protect against eviction. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]jb)}(hjETh]h Parameters}(hjGThhhNhNubah}(h]h ]h"]h$]h&]uh1jahjCTubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj?Tubjx)}(hhh](j})}(h>``struct i915_address_space *vm`` address space to evict from h](j)}(h!``struct i915_address_space *vm``h]j)}(hjdTh]hstruct i915_address_space *vm}(hjfThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbTubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chK}hj^Tubj)}(hhh]h)}(haddress space to evict fromh]haddress space to evict from}(hj}ThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyThK}hjzTubah}(h]h ]h"]h$]h&]uh1jhj^Tubeh}(h]h ]h"]h$]h&]uh1j|hjyThK}hj[Tubj})}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hjTh]hstruct i915_gem_ww_ctx *ww}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chK~hjTubj)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThK~hjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j|hjThK~hj[Tubj})}(h0``u64 min_size`` size of the desired free space h](j)}(h``u64 min_size``h]j)}(hjTh]h u64 min_size}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjTubj)}(hhh]h)}(hsize of the desired free spaceh]hsize of the desired free space}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThKhjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j|hjThKhj[Tubj})}(hA``u64 alignment`` alignment constraint of the desired free space h](j)}(h``u64 alignment``h]j)}(hjUh]h u64 alignment}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Uubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj Uubj)}(hhh]h)}(h.alignment constraint of the desired free spaceh]h.alignment constraint of the desired free space}(hj(UhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$UhKhj%Uubah}(h]h ]h"]h$]h&]uh1jhj Uubeh}(h]h ]h"]h$]h&]uh1j|hj$UhKhj[Tubj})}(h4``unsigned long color`` color for the desired space h](j)}(h``unsigned long color``h]j)}(hjHUh]hunsigned long color}(hjJUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFUubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjBUubj)}(hhh]h)}(hcolor for the desired spaceh]hcolor for the desired space}(hjaUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]UhKhj^Uubah}(h]h ]h"]h$]h&]uh1jhjBUubeh}(h]h ]h"]h$]h&]uh1j|hj]UhKhj[Tubj})}(hI``u64 start`` start (inclusive) of the range from which to evict objects h](j)}(h ``u64 start``h]j)}(hjUh]h u64 start}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj{Uubj)}(hhh]h)}(h:start (inclusive) of the range from which to evict objectsh]h:start (inclusive) of the range from which to evict objects}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhKhjUubah}(h]h ]h"]h$]h&]uh1jhj{Uubeh}(h]h ]h"]h$]h&]uh1j|hjUhKhj[Tubj})}(hE``u64 end`` end (exclusive) of the range from which to evict objects h](j)}(h ``u64 end``h]j)}(hjUh]hu64 end}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjUubj)}(hhh]h)}(h8end (exclusive) of the range from which to evict objectsh]h8end (exclusive) of the range from which to evict objects}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhKhjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j|hjUhKhj[Tubj})}(hF``unsigned flags`` additional flags to control the eviction algorithm h](j)}(h``unsigned flags``h]j)}(hjUh]hunsigned flags}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjUubj)}(hhh]h)}(h2additional flags to control the eviction algorithmh]h2additional flags to control the eviction algorithm}(hj VhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhKhj Vubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j|hjVhKhj[Tubeh}(h]h ]h"]h$]h&]uh1jwhj?Tubh)}(h**Description**h]jb)}(hj.Vh]h Description}(hj0VhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,Vubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj?Tubh)}(hThis function will try to evict vmas until a free space satisfying the requirements is found. Callers must check first whether any such hole exists already before calling this function.h]hThis function will try to evict vmas until a free space satisfying the requirements is found. Callers must check first whether any such hole exists already before calling this function.}(hjDVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj?Tubh)}(h5This function is used by the object/vma binding code.h]h5This function is used by the object/vma binding code.}(hjSVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj?Tubh)}(hSince this function is only used to free up virtual address space it only ignores pinned vmas, and not object where the backing storage itself is pinned. Hence obj->pages_pin_count does not protect against eviction.h]hSince this function is only used to free up virtual address space it only ignores pinned vmas, and not object where the backing storage itself is pinned. Hence obj->pages_pin_count does not protect against eviction.}(hjbVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj?Tubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hjqVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhj?Tubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjQhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$i915_gem_evict_for_node (C function)c.i915_gem_evict_for_nodehNtauh1jhjQhhhNhNubj')}(hhh](j,)}(hint i915_gem_evict_for_node (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h]j2)}(hint i915_gem_evict_for_node(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h](j)}(hinth]hint}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMHubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVhhhjVhMHubjz)}(hi915_gem_evict_for_nodeh]j;)}(hi915_gem_evict_for_nodeh]hi915_gem_evict_for_node}(hjVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjVhhhjVhMHubj)}(hk(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjVmodnameN classnameNjXj[)}j^]ja)}jTjVsbc.i915_gem_evict_for_nodeasbuh1hhjVubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVubj)}(hjh]h*}(hj)WhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubj;)}(hvmh]hvm}(hj6WhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjVubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hjOWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKWubji)}(h h]h }(hj\WhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKWubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjmWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjWubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjoWmodnameN classnameNjXj[)}j^]jWc.i915_gem_evict_for_nodeasbuh1hhjKWubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKWubj)}(hjh]h*}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKWubj;)}(hwwh]hww}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKWubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjVubj)}(hstruct drm_mm_node *targeth](j)}(hjh]hstruct}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjWubh)}(hhh]j;)}(h drm_mm_nodeh]h drm_mm_node}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjWubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjWmodnameN classnameNjXj[)}j^]jWc.i915_gem_evict_for_nodeasbuh1hhjWubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjWubj)}(hjh]h*}(hj XhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj;)}(htargeth]htarget}(hjXhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjWubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjVubj)}(hunsigned int flagsh](j)}(hunsignedh]hunsigned}(hj/XhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+Xubji)}(h h]h }(hj=XhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+Xubj)}(hinth]hint}(hjKXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+Xubji)}(h h]h }(hjYXhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+Xubj;)}(hflagsh]hflags}(hjgXhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+Xubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjVubeh}(h]h ]h"]h$]h&]jjuh1jhjVhhhjVhMHubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjVhhhjVhMHubah}(h]jVah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjVhMHhjVhhubj1)}(hhh]h)}(h-Evict vmas to make room for binding a new oneh]h-Evict vmas to make room for binding a new one}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM=hjXhhubah}(h]h ]h"]h$]h&]uh1j0hjVhhhjVhMHubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjXjSjXjTjUjVuh1j&hhhjQhNhNubjX)}(hX**Parameters** ``struct i915_address_space *vm`` address space to evict from ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *target`` range (and color) to evict for ``unsigned int flags`` additional flags to control the eviction algorithm **Description** This function will try to evict vmas that overlap the target node. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]jb)}(hjXh]h Parameters}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMAhjXubjx)}(hhh](j})}(h>``struct i915_address_space *vm`` address space to evict from h](j)}(h!``struct i915_address_space *vm``h]j)}(hjXh]hstruct i915_address_space *vm}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM>hjXubj)}(hhh]h)}(haddress space to evict fromh]haddress space to evict from}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhM>hjXubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1j|hjXhM>hjXubj})}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hj Yh]hstruct i915_gem_ww_ctx *ww}(hj YhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Yubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM?hjYubj)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hj$YhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj YhM?hj!Yubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1j|hj YhM?hjXubj})}(h>``struct drm_mm_node *target`` range (and color) to evict for h](j)}(h``struct drm_mm_node *target``h]j)}(hjDYh]hstruct drm_mm_node *target}(hjFYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBYubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM@hj>Yubj)}(hhh]h)}(hrange (and color) to evict forh]hrange (and color) to evict for}(hj]YhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYYhM@hjZYubah}(h]h ]h"]h$]h&]uh1jhj>Yubeh}(h]h ]h"]h$]h&]uh1j|hjYYhM@hjXubj})}(hJ``unsigned int flags`` additional flags to control the eviction algorithm h](j)}(h``unsigned int flags``h]j)}(hj}Yh]hunsigned int flags}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{Yubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMAhjwYubj)}(hhh]h)}(h2additional flags to control the eviction algorithmh]h2additional flags to control the eviction algorithm}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMAhjYubah}(h]h ]h"]h$]h&]uh1jhjwYubeh}(h]h ]h"]h$]h&]uh1j|hjYhMAhjXubeh}(h]h ]h"]h$]h&]uh1jwhjXubh)}(h**Description**h]jb)}(hjYh]h Description}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjYubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMChjXubh)}(hBThis function will try to evict vmas that overlap the target node.h]hBThis function will try to evict vmas that overlap the target node.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMChjXubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMEhjXubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjQhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_evict_vm (C function)c.i915_gem_evict_vmhNtauh1jhjQhhhNhNubj')}(hhh](j,)}(hwint i915_gem_evict_vm (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h]j2)}(hvint i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h](j)}(hinth]hint}(hj ZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjZhhhjZhMubjz)}(hi915_gem_evict_vmh]j;)}(hi915_gem_evict_vmh]hi915_gem_evict_vm}(hj-ZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)Zubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjZhhhjZhMubj)}(ha(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hjIZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEZubji)}(h h]h }(hjVZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEZubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjgZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjdZubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjiZmodnameN classnameNjXj[)}j^]ja)}jTj/Zsbc.i915_gem_evict_vmasbuh1hhjEZubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEZubj)}(hjh]h*}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEZubj;)}(hvmh]hvm}(hjZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEZubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjAZubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjZubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjZubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjZmodnameN classnameNjXj[)}j^]jZc.i915_gem_evict_vmasbuh1hhjZubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjZubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj;)}(hwwh]hww}(hj[hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjZubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjAZubj)}(h$struct drm_i915_gem_object **busy_boh](j)}(hjh]hstruct}(hj+[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'[ubji)}(h h]h }(hj8[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'[ubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjI[hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjF[ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjK[modnameN classnameNjXj[)}j^]jZc.i915_gem_evict_vmasbuh1hhj'[ubji)}(h h]h }(hjg[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'[ubj)}(hjh]h*}(hju[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'[ubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'[ubj;)}(hbusy_boh]hbusy_bo}(hj[hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'[ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjAZubeh}(h]h ]h"]h$]h&]jjuh1jhjZhhhjZhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjZhhhjZhMubah}(h]jYah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjZhMhjZhhubj1)}(hhh]h)}(hEvict all idle vmas from a vmh]hEvict all idle vmas from a vm}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj[hhubah}(h]h ]h"]h$]h&]uh1j0hjZhhhjZhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj[jSj[jTjUjVuh1j&hhhjQhNhNubjX)}(hXm**Parameters** ``struct i915_address_space *vm`` Address space to cleanse ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well. ``struct drm_i915_gem_object **busy_bo`` Optional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object. **Description** This function evicts all vmas from a vm. This is used by the execbuf code as a last-ditch effort to defragment the address space. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]jb)}(hj[h]h Parameters}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj[ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj[ubjx)}(hhh](j})}(h;``struct i915_address_space *vm`` Address space to cleanse h](j)}(h!``struct i915_address_space *vm``h]j)}(hj[h]hstruct i915_address_space *vm}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj[ubj)}(hhh]h)}(hAddress space to cleanseh]hAddress space to cleanse}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMhj\ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hj\hMhj[ubj})}(h``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hj3\h]hstruct i915_gem_ww_ctx *ww}(hj5\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1\ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj-\ubj)}(hhh]h)}(hxAn optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well.h]hzAn optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma’s locked by the ww as well.}(hjL\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjI\ubah}(h]h ]h"]h$]h&]uh1jhj-\ubeh}(h]h ]h"]h$]h&]uh1j|hjH\hMhj[ubj})}(hX|``struct drm_i915_gem_object **busy_bo`` Optional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object. h](j)}(h(``struct drm_i915_gem_object **busy_bo``h]j)}(hjm\h]h$struct drm_i915_gem_object **busy_bo}(hjo\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk\ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjg\ubj)}(hhh]h)}(hXROptional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object.h](hOptional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then }(hj\hhhNhNubjb)}(h **busy_bo**h]hbusy_bo}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj\ubh will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object.}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj\ubah}(h]h ]h"]h$]h&]uh1jhjg\ubeh}(h]h ]h"]h$]h&]uh1j|hj\hMhj[ubeh}(h]h ]h"]h$]h&]uh1jwhj[ubh)}(h**Description**h]jb)}(hj\h]h Description}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj\ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj[ubh)}(h(This function evicts all vmas from a vm.h]h(This function evicts all vmas from a vm.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj[ubh)}(hXThis is used by the execbuf code as a last-ditch effort to defragment the address space.h]hXThis is used by the execbuf code as a last-ditch effort to defragment the address space.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj[ubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhj[ubeh}()h]h ] kernelindentah"]h$]h&]uh1jWhjQhhhNhNubeh}(h]buffer-object-evictionah ]h"]buffer object evictionah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(hBuffer Object Memory Shrinkingh]hBuffer Object Memory Shrinking}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ]hhhhhMubh)}(hXThis section documents the interface function for shrinking memory usage of buffer object caches. Shrinking is used to make main memory available. Note that this is mostly orthogonal to evicting buffer objects, which has the goal to make space in gpu virtual address spaces.h]hXThis section documents the interface function for shrinking memory usage of buffer object caches. Shrinking is used to make main memory available. Note that this is mostly orthogonal to evicting buffer objects, which has the goal to make space in gpu virtual address spaces.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ]hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_shrink (C function)c.i915_gem_shrinkhNtauh1jhj ]hhhNhNubj')}(hhh](j,)}(hunsigned long i915_gem_shrink (struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h]j2)}(hunsigned long i915_gem_shrink(struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h](j)}(hunsignedh]hunsigned}(hjE]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA]hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKfubji)}(h h]h }(hjT]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjA]hhhjS]hKfubj)}(hlongh]hlong}(hjb]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA]hhhjS]hKfubji)}(h h]h }(hjp]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjA]hhhjS]hKfubjz)}(hi915_gem_shrinkh]j;)}(hi915_gem_shrinkh]hi915_gem_shrink}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~]ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjA]hhhjS]hKfubj)}(h(struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h](j)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubji)}(h h]h }(hj]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]ubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj]ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj]modnameN classnameNjXj[)}j^]ja)}jTj]sbc.i915_gem_shrinkasbuh1hhj]ubji)}(h h]h }(hj]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]ubj)}(hjh]h*}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj;)}(hwwh]hww}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj]ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj]ubj)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ^ubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ^ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj.^hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+^ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0^modnameN classnameNjXj[)}j^]j]c.i915_gem_shrinkasbuh1hhj ^ubji)}(h h]h }(hjL^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ^ubj)}(hjh]h*}(hjZ^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ^ubj;)}(hi915h]hi915}(hjg^hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ^ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj]ubj)}(hunsigned long targeth](j)}(hunsignedh]hunsigned}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|^ubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|^ubj)}(hlongh]hlong}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|^ubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|^ubj;)}(htargeth]htarget}(hj^hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|^ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj]ubj)}(hunsigned long *nr_scannedh](j)}(hunsignedh]hunsigned}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj^ubj)}(hlongh]hlong}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj^ubj)}(hjh]h*}(hj _hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj;)}(h nr_scannedh]h nr_scanned}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj^ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj]ubj)}(hunsigned int shrinkh](j)}(hunsignedh]hunsigned}(hj/_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+_ubji)}(h h]h }(hj=_hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+_ubj)}(hinth]hint}(hjK_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+_ubji)}(h h]h }(hjY_hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+_ubj;)}(hshrinkh]hshrink}(hjg_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+_ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj]ubeh}(h]h ]h"]h$]h&]jjuh1jhjA]hhhjS]hKfubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj=]hhhjS]hKfubah}(h]j8]ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjS]hKfhj:]hhubj1)}(hhh]h)}(hShrink buffer object cachesh]hShrink buffer object caches}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKMhj_hhubah}(h]h ]h"]h$]h&]uh1j0hj:]hhhjS]hKfubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj_jSj_jTjUjVuh1j&hhhj ]hNhNubjX)}(hX **Parameters** ``struct i915_gem_ww_ctx *ww`` i915 gem ww acquire ctx, or NULL ``struct drm_i915_private *i915`` i915 device ``unsigned long target`` amount of memory to make available, in pages ``unsigned long *nr_scanned`` optional output for number of pages scanned (incremental) ``unsigned int shrink`` control flags for selecting cache types **Description** This function is the main interface to the shrinker. It will try to release up to **target** pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with **flags**. This is e.g. useful when purgeable objects should be removed from caches preferentially. Note that it's not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all(). Also note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object. **Return** The number of pages of backing storage actually released.h](h)}(h**Parameters**h]jb)}(hj_h]h Parameters}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj_ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKQhj_ubjx)}(hhh](j})}(h@``struct i915_gem_ww_ctx *ww`` i915 gem ww acquire ctx, or NULL h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hj_h]hstruct i915_gem_ww_ctx *ww}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKNhj_ubj)}(hhh]h)}(h i915 gem ww acquire ctx, or NULLh]h i915 gem ww acquire ctx, or NULL}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKNhj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hj_hKNhj_ubj})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hj `h]hstruct drm_i915_private *i915}(hj `hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj `ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKOhj`ubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hj$`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj `hKOhj!`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1j|hj `hKOhj_ubj})}(hF``unsigned long target`` amount of memory to make available, in pages h](j)}(h``unsigned long target``h]j)}(hjD`h]hunsigned long target}(hjF`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB`ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKPhj>`ubj)}(hhh]h)}(h,amount of memory to make available, in pagesh]h,amount of memory to make available, in pages}(hj]`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjY`hKPhjZ`ubah}(h]h ]h"]h$]h&]uh1jhj>`ubeh}(h]h ]h"]h$]h&]uh1j|hjY`hKPhj_ubj})}(hX``unsigned long *nr_scanned`` optional output for number of pages scanned (incremental) h](j)}(h``unsigned long *nr_scanned``h]j)}(hj}`h]hunsigned long *nr_scanned}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{`ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKQhjw`ubj)}(hhh]h)}(h9optional output for number of pages scanned (incremental)h]h9optional output for number of pages scanned (incremental)}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hKQhj`ubah}(h]h ]h"]h$]h&]uh1jhjw`ubeh}(h]h ]h"]h$]h&]uh1j|hj`hKQhj_ubj})}(h@``unsigned int shrink`` control flags for selecting cache types h](j)}(h``unsigned int shrink``h]j)}(hj`h]hunsigned int shrink}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKRhj`ubj)}(hhh]h)}(h'control flags for selecting cache typesh]h'control flags for selecting cache types}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hKRhj`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1j|hj`hKRhj_ubeh}(h]h ]h"]h$]h&]uh1jwhj_ubh)}(h**Description**h]jb)}(hj`h]h Description}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKThj_ubh)}(hX,This function is the main interface to the shrinker. It will try to release up to **target** pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with **flags**. This is e.g. useful when purgeable objects should be removed from caches preferentially.h](hRThis function is the main interface to the shrinker. It will try to release up to }(hjahhhNhNubjb)}(h **target**h]htarget}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jahjaubhm pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with }(hjahhhNhNubjb)}(h **flags**h]hflags}(hj!ahhhNhNubah}(h]h ]h"]h$]h&]uh1jahjaubhZ. This is e.g. useful when purgeable objects should be removed from caches preferentially.}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKThj_ubh)}(hX~Note that it's not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all().h]hXNote that it’s not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all().}(hj:ahhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKYhj_ubh)}(hAlso note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object.h]hAlso note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object.}(hjIahhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chK_hj_ubh)}(h **Return**h]jb)}(hjZah]hReturn}(hj\ahhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXaubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKchj_ubh)}(h9The number of pages of backing storage actually released.h]h9The number of pages of backing storage actually released.}(hjpahhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKchj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj ]hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_shrink_all (C function)c.i915_gem_shrink_allhNtauh1jhj ]hhhNhNubj')}(hhh](j,)}(hAunsigned long i915_gem_shrink_all (struct drm_i915_private *i915)h]j2)}(h@unsigned long i915_gem_shrink_all(struct drm_i915_private *i915)h](j)}(hunsignedh]hunsigned}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjahhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjahhhjahMubj)}(hlongh]hlong}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjahhhjahMubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjahhhjahMubjz)}(hi915_gem_shrink_allh]j;)}(hi915_gem_shrink_allh]hi915_gem_shrink_all}(hjahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjaubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjahhhjahMubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubji)}(h h]h }(hjbhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjaubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjbhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjbubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjbmodnameN classnameNjXj[)}j^]ja)}jTjasbc.i915_gem_shrink_allasbuh1hhjaubji)}(h h]h }(hj6bhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjaubj)}(hjh]h*}(hjDbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj;)}(hi915h]hi915}(hjQbhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjaubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjaubah}(h]h ]h"]h$]h&]jjuh1jhjahhhjahMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjahhhjahMubah}(h]jaah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjahMhjahhubj1)}(hhh]h)}(h&Shrink buffer object caches completelyh]h&Shrink buffer object caches completely}(hj{bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjxbhhubah}(h]h ]h"]h$]h&]uh1j0hjahhhjahMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjbjSjbjTjUjVuh1j&hhhj ]hNhNubjX)}(hX**Parameters** ``struct drm_i915_private *i915`` i915 device **Description** This is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects. This should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out. **Return** The number of pages of backing storage actually released.h](h)}(h**Parameters**h]jb)}(hjbh]h Parameters}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjbubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM hjbubjx)}(hhh]j})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjbh]hstruct drm_i915_private *i915}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjbubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMhjbubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1j|hjbhMhjbubah}(h]h ]h"]h$]h&]uh1jwhjbubh)}(h**Description**h]jb)}(hjbh]h Description}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjbubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjbubh)}(hThis is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects.h]hThis is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects.}(hj chhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjbubh)}(hThis should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out.h]hThis should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM hjbubh)}(h **Return**h]jb)}(hj-ch]hReturn}(hj/chhhNhNubah}(h]h ]h"]h$]h&]uh1jahj+cubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjbubh)}(h9The number of pages of backing storage actually released.h]h9The number of pages of backing storage actually released.}(hjCchhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjbubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj ]hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j".i915_gem_object_make_unshrinkable (C function)#c.i915_gem_object_make_unshrinkablehNtauh1jhj ]hhhNhNubj')}(hhh](j,)}(hHvoid i915_gem_object_make_unshrinkable (struct drm_i915_gem_object *obj)h]j2)}(hGvoid i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj)h](j)}(hvoidh]hvoid}(hjrchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnchhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnchhhjchMubjz)}(h!i915_gem_object_make_unshrinkableh]j;)}(h!i915_gem_object_make_unshrinkableh]h!i915_gem_object_make_unshrinkable}(hjchhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjnchhhjchMubj)}(h!(struct drm_i915_gem_object *obj)h]j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjchhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjcmodnameN classnameNjXj[)}j^]ja)}jTjcsb#c.i915_gem_object_make_unshrinkableasbuh1hhjcubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubj)}(hjh]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj;)}(hobjh]hobj}(hjdhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjcubah}(h]h ]h"]h$]h&]jjuh1jhjnchhhjchMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjjchhhjchMubah}(h]jecah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjchMhjgchhubj1)}(hhh]h)}(hHide the object from the shrinker. By default all object types that support shrinking(see IS_SHRINKABLE), will also make the object visible to the shrinker after allocating the system memory pages.h]hHide the object from the shrinker. By default all object types that support shrinking(see IS_SHRINKABLE), will also make the object visible to the shrinker after allocating the system memory pages.}(hj2dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj/dhhubah}(h]h ]h"]h$]h&]uh1j0hjgchhhjchMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjJdjSjJdjTjUjVuh1j&hhhj ]hNhNubjX)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** This is typically used for special kernel internal objects that can't be easily processed by the shrinker, like if they are perma-pinned.h](h)}(h**Parameters**h]jb)}(hjTdh]h Parameters}(hjVdhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjRdubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjNdubjx)}(hhh]j})}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hjsdh]hstruct drm_i915_gem_object *obj}(hjudhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqdubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjmdubj)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjdubah}(h]h ]h"]h$]h&]uh1jhjmdubeh}(h]h ]h"]h$]h&]uh1j|hjdhMhjjdubah}(h]h ]h"]h$]h&]uh1jwhjNdubh)}(h**Description**h]jb)}(hjdh]h Description}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjdubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjNdubh)}(hThis is typically used for special kernel internal objects that can't be easily processed by the shrinker, like if they are perma-pinned.h]hThis is typically used for special kernel internal objects that can’t be easily processed by the shrinker, like if they are perma-pinned.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjNdubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj ]hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j".__i915_gem_object_make_shrinkable (C function)#c.__i915_gem_object_make_shrinkablehNtauh1jhj ]hhhNhNubj')}(hhh](j,)}(hHvoid __i915_gem_object_make_shrinkable (struct drm_i915_gem_object *obj)h]j2)}(hGvoid __i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj)h](j)}(hvoidh]hvoid}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMubji)}(h h]h }(hjehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjdhhhjehMubjz)}(h!__i915_gem_object_make_shrinkableh]j;)}(h!__i915_gem_object_make_shrinkableh]h!__i915_gem_object_make_shrinkable}(hjehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjeubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjdhhhjehMubj)}(h!(struct drm_i915_gem_object *obj)h]j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hj0ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,eubji)}(h h]h }(hj=ehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj,eubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjNehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKeubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjPemodnameN classnameNjXj[)}j^]ja)}jTjesb#c.__i915_gem_object_make_shrinkableasbuh1hhj,eubji)}(h h]h }(hjnehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj,eubj)}(hjh]h*}(hj|ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,eubj;)}(hobjh]hobj}(hjehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj,eubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(eubah}(h]h ]h"]h$]h&]jjuh1jhjdhhhjehMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjdhhhjehMubah}(h]jdah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjehMhjdhhubj1)}(hhh]h)}(hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.h]hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjehhubah}(h]h ]h"]h$]h&]uh1j0hjdhhhjehMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjejSjejTjUjVuh1j&hhhj ]hNhNubjX)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** DO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h](h)}(h**Parameters**h]jb)}(hjeh]h Parameters}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jahjeubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjeubjx)}(hhh]j})}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hjeh]hstruct drm_i915_gem_object *obj}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjeubj)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hj fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj fhMhj fubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1j|hj fhMhjeubah}(h]h ]h"]h$]h&]uh1jwhjeubh)}(h**Description**h]jb)}(hj/fh]h Description}(hj1fhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-fubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjeubh)}(hDO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h]hDO NOT USE. This is intended to be called on very special objects that don’t yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.}(hjEfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjeubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj ]hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"-__i915_gem_object_make_purgeable (C function)"c.__i915_gem_object_make_purgeablehNtauh1jhj ]hhhNhNubj')}(hhh](j,)}(hGvoid __i915_gem_object_make_purgeable (struct drm_i915_gem_object *obj)h]j2)}(hFvoid __i915_gem_object_make_purgeable(struct drm_i915_gem_object *obj)h](j)}(hvoidh]hvoid}(hjtfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpfhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM/ubji)}(h h]h }(hjfhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjpfhhhjfhM/ubjz)}(h __i915_gem_object_make_purgeableh]j;)}(h __i915_gem_object_make_purgeableh]h __i915_gem_object_make_purgeable}(hjfhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjpfhhhjfhM/ubj)}(h!(struct drm_i915_gem_object *obj)h]j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubji)}(h h]h }(hjfhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjfhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjfmodnameN classnameNjXj[)}j^]ja)}jTjfsb"c.__i915_gem_object_make_purgeableasbuh1hhjfubji)}(h h]h }(hjfhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubj)}(hjh]h*}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubj;)}(hobjh]hobj}(hj ghhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjfubah}(h]h ]h"]h$]h&]jjuh1jhjpfhhhjfhM/ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjlfhhhjfhM/ubah}(h]jgfah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjfhM/hjifhhubj1)}(hhh]h)}(hyMove the object to the tail of the purgeable list. Objects on this list might be swapped out. Used with DONTNEED objects.h]hyMove the object to the tail of the purgeable list. Objects on this list might be swapped out. Used with DONTNEED objects.}(hj4ghhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM&hj1ghhubah}(h]h ]h"]h$]h&]uh1j0hjifhhhjfhM/ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjLgjSjLgjTjUjVuh1j&hhhj ]hNhNubjX)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** DO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h](h)}(h**Parameters**h]jb)}(hjVgh]h Parameters}(hjXghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjTgubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM*hjPgubjx)}(hhh]j})}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hjugh]hstruct drm_i915_gem_object *obj}(hjwghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsgubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM)hjogubj)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghM)hjgubah}(h]h ]h"]h$]h&]uh1jhjogubeh}(h]h ]h"]h$]h&]uh1j|hjghM)hjlgubah}(h]h ]h"]h$]h&]uh1jwhjPgubh)}(h**Description**h]jb)}(hjgh]h Description}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjgubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM+hjPgubh)}(hDO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h]hDO NOT USE. This is intended to be called on very special objects that don’t yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM+hjPgubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj ]hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",i915_gem_object_make_shrinkable (C function)!c.i915_gem_object_make_shrinkablehNtauh1jhj ]hhhNhNubj')}(hhh](j,)}(hFvoid i915_gem_object_make_shrinkable (struct drm_i915_gem_object *obj)h]j2)}(hEvoid i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj)h](j)}(hvoidh]hvoid}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjghhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM?ubji)}(h h]h }(hjhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjghhhjhhM?ubjz)}(hi915_gem_object_make_shrinkableh]j;)}(hi915_gem_object_make_shrinkableh]hi915_gem_object_make_shrinkable}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjghhhjhhM?ubj)}(h!(struct drm_i915_gem_object *obj)h]j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hj2hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hubji)}(h h]h }(hj?hhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.hubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjPhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjMhubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjRhmodnameN classnameNjXj[)}j^]ja)}jTjhsb!c.i915_gem_object_make_shrinkableasbuh1hhj.hubji)}(h h]h }(hjphhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.hubj)}(hjh]h*}(hj~hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hubj;)}(hobjh]hobj}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.hubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj*hubah}(h]h ]h"]h$]h&]jjuh1jhjghhhjhhM?ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjghhhjhhM?ubah}(h]jgah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhhM?hjghhubj1)}(hhh]h)}(hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.h]hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM6hjhhhubah}(h]h ]h"]h$]h&]uh1j0hjghhhjhhM?ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjhjSjhjTjUjVuh1j&hhhj ]hNhNubjX)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** MUST only be called on objects which have backing pages. MUST be balanced with previous call to i915_gem_object_make_unshrinkable().h](h)}(h**Parameters**h]jb)}(hjhh]h Parameters}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjhubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM:hjhubjx)}(hhh]j})}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hjhh]hstruct drm_i915_gem_object *obj}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM9hjhubj)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ihM9hj iubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1j|hj ihM9hjhubah}(h]h ]h"]h$]h&]uh1jwhjhubh)}(h**Description**h]jb)}(hj1ih]h Description}(hj3ihhhNhNubah}(h]h ]h"]h$]h&]uh1jahj/iubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM;hjhubh)}(h8MUST only be called on objects which have backing pages.h]h8MUST only be called on objects which have backing pages.}(hjGihhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM;hjhubh)}(hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().h]hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().}(hjVihhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM=hjhubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj ]hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+i915_gem_object_make_purgeable (C function) c.i915_gem_object_make_purgeablehNtauh1jhj ]hhhNhNubj')}(hhh](j,)}(hEvoid i915_gem_object_make_purgeable (struct drm_i915_gem_object *obj)h]j2)}(hDvoid i915_gem_object_make_purgeable(struct drm_i915_gem_object *obj)h](j)}(hvoidh]hvoid}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjihhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMPubji)}(h h]h }(hjihhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjihhhjihMPubjz)}(hi915_gem_object_make_purgeableh]j;)}(hi915_gem_object_make_purgeableh]hi915_gem_object_make_purgeable}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjiubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjihhhjihMPubj)}(h!(struct drm_i915_gem_object *obj)h]j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubji)}(h h]h }(hjihhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjiubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjiubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjimodnameN classnameNjXj[)}j^]ja)}jTjisb c.i915_gem_object_make_purgeableasbuh1hhjiubji)}(h h]h }(hjjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjiubj)}(hjh]h*}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubj;)}(hobjh]hobj}(hjjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjiubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjiubah}(h]h ]h"]h$]h&]jjuh1jhjihhhjihMPubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj}ihhhjihMPubah}(h]jxiah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjihMPhjzihhubj1)}(hhh]h)}(hMove the object to the tail of the purgeable list. Used with DONTNEED objects. Unlike with shrinkable objects, the shrinker will attempt to discard the backing pages, instead of trying to swap them out.h]hMove the object to the tail of the purgeable list. Used with DONTNEED objects. Unlike with shrinkable objects, the shrinker will attempt to discard the backing pages, instead of trying to swap them out.}(hjEjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMFhjBjhhubah}(h]h ]h"]h$]h&]uh1j0hjzihhhjihMPubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj]jjSj]jjTjUjVuh1j&hhhj ]hNhNubjX)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** MUST only be called on objects which have backing pages. MUST be balanced with previous call to i915_gem_object_make_unshrinkable().h](h)}(h**Parameters**h]jb)}(hjgjh]h Parameters}(hjijhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjejubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMJhjajubjx)}(hhh]j})}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hjjh]hstruct drm_i915_gem_object *obj}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMJhjjubj)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMJhjjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1j|hjjhMJhj}jubah}(h]h ]h"]h$]h&]uh1jwhjajubh)}(h**Description**h]jb)}(hjjh]h Description}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMLhjajubh)}(h8MUST only be called on objects which have backing pages.h]h8MUST only be called on objects which have backing pages.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMLhjajubh)}(hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().h]hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMNhjajubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj ]hhhNhNubeh}(h]buffer-object-memory-shrinkingah ]h"]buffer object memory shrinkingah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(hBatchbuffer Parsingh]hBatchbuffer Parsing}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubh)}(hXMotivation: Certain OpenGL features (e.g. transform feedback, performance monitoring) require userspace code to submit batches containing commands such as MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some generations of the hardware will noop these commands in "unsecure" batches (which includes all userspace batches submitted via i915) even though the commands may be safe and represent the intended programming model of the device.h]hXMotivation: Certain OpenGL features (e.g. transform feedback, performance monitoring) require userspace code to submit batches containing commands such as MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some generations of the hardware will noop these commands in “unsecure” batches (which includes all userspace batches submitted via i915) even though the commands may be safe and represent the intended programming model of the device.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK+hjkhhubh)}(hX6The software command parser is similar in operation to the command parsing done in hardware for unsecure batches. However, the software parser allows some operations that would be noop'd by hardware, if the parser determines the operation is safe, and submits the batch as "secure" to prevent hardware parsing.h]hX<The software command parser is similar in operation to the command parsing done in hardware for unsecure batches. However, the software parser allows some operations that would be noop’d by hardware, if the parser determines the operation is safe, and submits the batch as “secure” to prevent hardware parsing.}(hj$khhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK4hjkhhubh)}(hThreats: At a high level, the hardware (and software) checks attempt to prevent granting userspace undue privileges. There are three categories of privilege.h]hThreats: At a high level, the hardware (and software) checks attempt to prevent granting userspace undue privileges. There are three categories of privilege.}(hj3khhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK:hjkhhubh)}(hFirst, commands which are explicitly defined as privileged or which should only be used by the kernel driver. The parser rejects such commandsh]hFirst, commands which are explicitly defined as privileged or which should only be used by the kernel driver. The parser rejects such commands}(hjBkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK>hjkhhubh)}(hSecond, commands which access registers. To support correct/enhanced userspace functionality, particularly certain OpenGL extensions, the parser provides a whitelist of registers which userspace may safely accessh]hSecond, commands which access registers. To support correct/enhanced userspace functionality, particularly certain OpenGL extensions, the parser provides a whitelist of registers which userspace may safely access}(hjQkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKAhjkhhubh)}(hsThird, commands which access privileged memory (i.e. GGTT, HWS page, etc). The parser always rejects such commands.h]hsThird, commands which access privileged memory (i.e. GGTT, HWS page, etc). The parser always rejects such commands.}(hj`khhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKEhjkhhubh)}(hThe majority of the problematic commands fall in the MI_* range, with only a few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).h]hThe majority of the problematic commands fall in the MI_* range, with only a few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).}(hjokhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKHhjkhhubh)}(hImplementation: Each engine maintains tables of commands and registers which the parser uses in scanning batch buffers submitted to that engine.h]hImplementation: Each engine maintains tables of commands and registers which the parser uses in scanning batch buffers submitted to that engine.}(hj~khhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKKhjkhhubh)}(hXSince the set of commands that the parser must check for is significantly smaller than the number of commands supported, the parser tables contain only those commands required by the parser. This generally works because command opcode ranges have standard command length encodings. So for commands that the parser does not need to check, it can easily skip them. This is implemented via a per-engine length decoding vfunc.h]hXSince the set of commands that the parser must check for is significantly smaller than the number of commands supported, the parser tables contain only those commands required by the parser. This generally works because command opcode ranges have standard command length encodings. So for commands that the parser does not need to check, it can easily skip them. This is implemented via a per-engine length decoding vfunc.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKOhjkhhubh)}(hXUnfortunately, there are a number of commands that do not follow the standard length encoding for their opcode range, primarily amongst the MI_* commands. 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The parser implements a number of checks, including the privileged memory checks, via a general bitmasking mechanism.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK[hjkhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_engine_init_cmd_parser (C function)c.intel_engine_init_cmd_parserhNtauh1jhjkhhhNhNubj')}(hhh](j,)}(hAint intel_engine_init_cmd_parser (struct intel_engine_cs *engine)h]j2)}(h@int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)h](j)}(hinth]hint}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMubji)}(h h]h }(hjkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjkhhhjkhMubjz)}(hintel_engine_init_cmd_parserh]j;)}(hintel_engine_init_cmd_parserh]hintel_engine_init_cmd_parser}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjkubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjkhhhjkhMubj)}(h (struct intel_engine_cs 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]h"]h$]h&]uh1hhjlhMhjlubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1j|hjlhMhjlubah}(h]h ]h"]h$]h&]uh1jwhjlubh)}(h**Description**h]jb)}(hjmh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj mubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjlubh)}(hOptionally initializes fields related to batch buffer command parsing in the struct intel_engine_cs based on whether the platform requires software command parsing.h]hOptionally initializes fields related to batch buffer command parsing in the struct intel_engine_cs based on whether the platform requires software command parsing.}(hj%mhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjlubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjkhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_engine_cleanup_cmd_parser (C function)!c.intel_engine_cleanup_cmd_parserhNtauh1jhjkhhhNhNubj')}(hhh](j,)}(hEvoid intel_engine_cleanup_cmd_parser (struct intel_engine_cs *engine)h]j2)}(hDvoid intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)h](j)}(hvoidh]hvoid}(hjTmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPmhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM,ubji)}(h h]h }(hjcmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjPmhhhjbmhM,ubjz)}(hintel_engine_cleanup_cmd_parserh]j;)}(hintel_engine_cleanup_cmd_parserh]hintel_engine_cleanup_cmd_parser}(hjumhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjqmubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjPmhhhjbmhM,ubj)}(h (struct intel_engine_cs *engine)h]j)}(hstruct intel_engine_cs *engineh](j)}(hjh]hstruct}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjmubh)}(hhh]j;)}(hintel_engine_csh]hintel_engine_cs}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmmodnameN classnameNjXj[)}j^]ja)}jTjwmsb!c.intel_engine_cleanup_cmd_parserasbuh1hhjmubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjmubj)}(hjh]h*}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj;)}(hengineh]hengine}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjmubah}(h]h ]h"]h$]h&]jjuh1jhjPmhhhjbmhM,ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjLmhhhjbmhM,ubah}(h]jGmah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjbmhM,hjImhhubj1)}(hhh]h)}(h"clean up cmd parser related fieldsh]h"clean up cmd parser related fields}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM&hjnhhubah}(h]h ]h"]h$]h&]uh1j0hjImhhhjbmhM,ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj,njSj,njTjUjVuh1j&hhhjkhNhNubjX)}(h**Parameters** ``struct intel_engine_cs *engine`` the engine to clean up **Description** Releases any resources related to command parsing that may have been initialized for the specified engine.h](h)}(h**Parameters**h]jb)}(hj6nh]h Parameters}(hj8nhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj4nubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM*hj0nubjx)}(hhh]j})}(h:``struct intel_engine_cs *engine`` the engine to clean up h](j)}(h"``struct intel_engine_cs *engine``h]j)}(hjUnh]hstruct intel_engine_cs *engine}(hjWnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSnubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM'hjOnubj)}(hhh]h)}(hthe engine to clean uph]hthe engine to clean up}(hjnnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjnhM'hjknubah}(h]h ]h"]h$]h&]uh1jhjOnubeh}(h]h ]h"]h$]h&]uh1j|hjjnhM'hjLnubah}(h]h ]h"]h$]h&]uh1jwhj0nubh)}(h**Description**h]jb)}(hjnh]h Description}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjnubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM)hj0nubh)}(hjReleases any resources related to command parsing that may have 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batch_lengthh](j)}(hunsignedh]hunsigned}(hjEphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjApubji)}(h h]h }(hjSphhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjApubj)}(hlongh]hlong}(hjaphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjApubji)}(h h]h }(hjophhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjApubj;)}(h batch_lengthh]h batch_length}(hj}phhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjApubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj oubj)}(hstruct i915_vma *shadowh](j)}(hjh]hstruct}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubji)}(h h]h }(hjphhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjpubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjphhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjpubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjpmodnameN classnameNjXj[)}j^]jLoc.intel_engine_cmd_parserasbuh1hhjpubji)}(h h]h }(hjphhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjpubj)}(hjh]h*}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubj;)}(hshadowh]hshadow}(hjphhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjpubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj oubj)}(hbool trampolineh](j)}(hjh]hbool}(hjqhhhNhNubah}(h]h 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batch at which execution startsh]h2byte offset in the batch at which execution starts}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1j|hjrhMhjqubj})}(hC``unsigned long batch_length`` length of the commands in batch_obj h](j)}(h``unsigned long batch_length``h]j)}(hj7rh]hunsigned long batch_length}(hj9rhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5rubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhj1rubj)}(hhh]h)}(h#length of the commands in batch_objh]h#length of the commands in batch_obj}(hjPrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLrhMhjMrubah}(h]h ]h"]h$]h&]uh1jhj1rubeh}(h]h ]h"]h$]h&]uh1j|hjLrhMhjqubj})}(hK``struct i915_vma *shadow`` validated copy of the batch buffer in question h](j)}(h``struct i915_vma *shadow``h]j)}(hjprh]hstruct i915_vma *shadow}(hjrrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnrubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjjrubj)}(hhh]h)}(h.validated copy of the batch buffer in questionh]h.validated copy of the batch buffer in question}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1jhjjrubeh}(h]h ]h"]h$]h&]uh1j|hjrhMhjqubj})}(hL``bool trampoline`` true if we need to trampoline into privileged execution h](j)}(h``bool trampoline``h]j)}(hjrh]hbool trampoline}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjrubj)}(hhh]h)}(h7true if we need to trampoline into privileged executionh]h7true if we need to trampoline into privileged execution}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1j|hjrhMhjqubeh}(h]h ]h"]h$]h&]uh1jwhjgqubh)}(h**Description**h]jb)}(hjrh]h Description}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjrubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjgqubh)}(h`Parses the specified batch buffer looking for privilege violations as described in the overview.h]h`Parses the specified batch buffer looking for privilege violations as described in the overview.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjgqubh)}(h **Return**h]jb)}(hj sh]hReturn}(hj shhhNhNubah}(h]h ]h"]h$]h&]uh1jahj subah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjgqubh)}(h~non-zero if the parser finds violations or otherwise fails; -EACCES if the batch appears legal but should use hardware parsingh]h~non-zero if the parser finds violations or otherwise fails; -EACCES if the batch appears legal but should use hardware parsing}(hj!shhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: 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]juah"]h$]h&]uh1jhhjsubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjshhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjsmodnameN classnameNjXj[)}j^]ja)}jTjsssbc.i915_cmd_parser_get_versionasbuh1hhjsubji)}(h h]h }(hjshhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjsubj)}(hjh]h*}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj;)}(hdev_privh]hdev_priv}(hjshhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjsubah}(h]h ]h"]h$]h&]jjuh1jhjLshhhj^shM5ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjHshhhj^shM5ubah}(h]jCsah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj^shM5hjEshhubj1)}(hhh]h)}(h!get the cmd parser version numberh]h!get the cmd parser version number}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM-hj thhubah}(h]h ]h"]h$]h&]uh1j0hjEshhhj^shM5ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj(tjSj(tjTjUjVuh1j&hhhjkhNhNubjX)}(hX1**Parameters** ``struct drm_i915_private *dev_priv`` i915 device private **Description** The cmd parser maintains a simple increasing integer version number suitable for passing to userspace clients to determine what operations are permitted. **Return** the current version number of the cmd parserh](h)}(h**Parameters**h]jb)}(hj2th]h Parameters}(hj4thhhNhNubah}(h]h ]h"]h$]h&]uh1jahj0tubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM1hj,tubjx)}(hhh]j})}(h:``struct drm_i915_private *dev_priv`` i915 device private h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hjQth]h!struct drm_i915_private *dev_priv}(hjSthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOtubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM.hjKtubj)}(hhh]h)}(hi915 device privateh]hi915 device private}(hjjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfthM.hjgtubah}(h]h ]h"]h$]h&]uh1jhjKtubeh}(h]h ]h"]h$]h&]uh1j|hjfthM.hjHtubah}(h]h ]h"]h$]h&]uh1jwhj,tubh)}(h**Description**h]jb)}(hjth]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM0hj,tubh)}(hThe cmd parser maintains a simple increasing integer version number suitable for passing to userspace clients to determine what operations are permitted.h]hThe cmd parser maintains a simple increasing integer version number suitable for passing to userspace clients to determine what operations are permitted.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM0hj,tubh)}(h **Return**h]jb)}(hjth]hReturn}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM3hj,tubh)}(h,the current version number of the cmd parserh]h,the current version number of the cmd parser}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM3hj,tubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjkhhhNhNubeh}(h]batchbuffer-parsingah ]h"]batchbuffer parsingah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(hUser Batchbuffer Executionh]hUser Batchbuffer Execution}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_engines (C struct)c.i915_gem_engineshNtauh1jhjthhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhNubj')}(hhh](j,)}(hi915_gem_enginesh]j2)}(hstruct i915_gem_enginesh](j)}(hjh]hstruct}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubji)}(h h]h }(hj uhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuhhhjuhKubjz)}(hi915_gem_enginesh]j;)}(hj uh]hi915_gem_engines}(hj2uhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.uubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjuhhhjuhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj uhhhjuhKubah}(h]juah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjuhKhjuhhubj1)}(hhh]h)}(hA set of enginesh]hA set of engines}(hjTuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK"hjQuhhubah}(h]h ]h"]h$]h&]uh1j0hjuhhhjuhKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjlujSjlujTjUjVuh1j&hhhjthjuhNubjX)}(hXP**Definition**:: struct i915_gem_engines { union { struct list_head link; struct rcu_head rcu; }; struct i915_sw_fence fence; struct i915_gem_context *ctx; unsigned int num_engines; struct intel_context *engines[]; }; **Members** ``{unnamed_union}`` anonymous ``link`` Link in i915_gem_context::stale::engines ``rcu`` RCU to use when freeing ``fence`` Fence used for delayed destruction of engines ``ctx`` i915_gem_context backpointer ``num_engines`` Number of engines in this set ``engines`` Array of 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h](j)}(h``rcu``h]j)}(hj3vh]hrcu}(hj5vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1vubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj-vubj)}(hhh]h)}(hRCU to use when freeingh]hRCU to use when freeing}(hjLvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHvhKhjIvubah}(h]h ]h"]h$]h&]uh1jhj-vubeh}(h]h ]h"]h$]h&]uh1j|hjHvhKhjuubj})}(h8``fence`` Fence used for delayed destruction of engines h](j)}(h ``fence``h]j)}(hjlvh]hfence}(hjnvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjvubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjfvubj)}(hhh]h)}(h-Fence used for delayed destruction of enginesh]h-Fence used for delayed destruction of engines}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhKhjvubah}(h]h ]h"]h$]h&]uh1jhjfvubeh}(h]h ]h"]h$]h&]uh1j|hjvhKhjuubj})}(h%``ctx`` i915_gem_context backpointer h](j)}(h``ctx``h]j)}(hjvh]hctx}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h 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./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjwubj)}(hhh]h)}(hArray of enginesh]hArray of engines}(hj0whhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj-wubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1j|hj,whKhjuubeh}(h]h ]h"]h$]h&]uh1jwhjpuubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjthhhjuhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_engines_iter (C struct)c.i915_gem_engines_iterhNtauh1jhjthhhjuhNubj')}(hhh](j,)}(hi915_gem_engines_iterh]j2)}(hstruct i915_gem_engines_iterh](j)}(hjh]hstruct}(hjqwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmwhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubji)}(h h]h }(hjwhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjmwhhhj~whKubjz)}(hi915_gem_engines_iterh]j;)}(hjkwh]hi915_gem_engines_iter}(hjwhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjwubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjmwhhhj~whKubeh}(h]h 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};h]hcstruct i915_gem_engines_iter { unsigned int idx; const struct i915_gem_engines *engines; };}hjwsbah}(h]h ]h"]h$]h&]jjuh1j"hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKAhjwubh)}(h **Members**h]jb)}(hjxh]hMembers}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjwubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKFhjwubjx)}(hhh](j})}(h-``idx`` Index into i915_gem_engines::engines h](j)}(h``idx``h]j)}(hj xh]hidx}(hj"xhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK>hjxubj)}(hhh]h)}(h$Index into i915_gem_engines::enginesh]h$Index into i915_gem_engines::engines}(hj9xhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5xhK>hj6xubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1j|hj5xhK>hjxubj})}(h%``engines`` Engine set being iteratedh](j)}(h ``engines``h]j)}(hjYxh]hengines}(hj[xhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWxubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjSxubj)}(hhh]h)}(hEngine set being iteratedh]hEngine set being iterated}(hjrxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjoxubah}(h]h ]h"]h$]h&]uh1jhjSxubeh}(h]h ]h"]h$]h&]uh1j|hjnxhKhjxubeh}(h]h ]h"]h$]h&]uh1jwhjwubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjthhhjuhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_engine_type (C enum)c.i915_gem_engine_typehNtauh1jhjthhhjuhNubj')}(hhh](j,)}(hi915_gem_engine_typeh]j2)}(henum i915_gem_engine_typeh](j)}(hjh]henum}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubji)}(h h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxhhhjxhKubjz)}(hi915_gem_engine_typeh]j;)}(hjxh]hi915_gem_engine_type}(hjxhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjxubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjxhhhjxhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjxhhhjxhKubah}(h]jxah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjxhKhjxhhubj1)}(hhh]h)}(h.Describes the type of an i915_gem_proto_engineh]h.Describes the type of an i915_gem_proto_engine}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKFhjxhhubah}(h]h ]h"]h$]h&]uh1j0hjxhhhjxhKubeh}(h]h ](jRenumeh"]h$]h&]jQjRjRj yjSj yjTjUjVuh1j&hhhjthjuhNubjX)}(h**Constants** ``I915_GEM_ENGINE_TYPE_INVALID`` An invalid engine ``I915_GEM_ENGINE_TYPE_PHYSICAL`` A single physical engine ``I915_GEM_ENGINE_TYPE_BALANCED`` A load-balanced engine set ``I915_GEM_ENGINE_TYPE_PARALLEL`` A parallel engine seth](h)}(h **Constants**h]jb)}(hjyh]h Constants}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjyubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKJhjyubjx)}(hhh](j})}(h3``I915_GEM_ENGINE_TYPE_INVALID`` An invalid engine h](j)}(h ``I915_GEM_ENGINE_TYPE_INVALID``h]j)}(hj6yh]hI915_GEM_ENGINE_TYPE_INVALID}(hj8yhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4yubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKMhj0yubj)}(hhh]h)}(hAn invalid engineh]hAn invalid engine}(hjOyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKyhKMhjLyubah}(h]h ]h"]h$]h&]uh1jhj0yubeh}(h]h ]h"]h$]h&]uh1j|hjKyhKMhj-yubj})}(h;``I915_GEM_ENGINE_TYPE_PHYSICAL`` A single physical engine h](j)}(h!``I915_GEM_ENGINE_TYPE_PHYSICAL``h]j)}(hjoyh]hI915_GEM_ENGINE_TYPE_PHYSICAL}(hjqyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmyubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKPhjiyubj)}(hhh]h)}(hA single physical engineh]hA single physical engine}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhKPhjyubah}(h]h ]h"]h$]h&]uh1jhjiyubeh}(h]h ]h"]h$]h&]uh1j|hjyhKPhj-yubj})}(h=``I915_GEM_ENGINE_TYPE_BALANCED`` A load-balanced engine set h](j)}(h!``I915_GEM_ENGINE_TYPE_BALANCED``h]j)}(hjyh]hI915_GEM_ENGINE_TYPE_BALANCED}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKShjyubj)}(hhh]h)}(hA load-balanced engine seth]hA load-balanced engine set}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhKShjyubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjyhKShj-yubj})}(h7``I915_GEM_ENGINE_TYPE_PARALLEL`` A parallel engine seth](j)}(h!``I915_GEM_ENGINE_TYPE_PARALLEL``h]j)}(hjyh]hI915_GEM_ENGINE_TYPE_PARALLEL}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKUhjyubj)}(hhh]h)}(hA parallel engine seth]hA parallel engine set}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKVhjyubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjyhKUhj-yubeh}(h]h ]h"]h$]h&]uh1jwhjyubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjthhhjuhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_proto_engine (C struct)c.i915_gem_proto_enginehNtauh1jhjthhhjuhNubj')}(hhh](j,)}(hi915_gem_proto_engineh]j2)}(hstruct i915_gem_proto_engineh](j)}(hjh]hstruct}(hj;zhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7zhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK\ubji)}(h h]h }(hjIzhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj7zhhhjHzhK\ubjz)}(hi915_gem_proto_engineh]j;)}(hj5zh]hi915_gem_proto_engine}(hj[zhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjWzubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj7zhhhjHzhK\ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj3zhhhjHzhK\ubah}(h]j.zah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjHzhK\hj0zhhubj1)}(hhh]h)}(hprototype engineh]hprototype engine}(hj}zhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKWhjzzhhubah}(h]h ]h"]h$]h&]uh1j0hj0zhhhjHzhK\ubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjzjSjzjTjUjVuh1j&hhhjthjuhNubjX)}(hX"**Definition**:: struct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; }; **Members** ``type`` Type of this engine ``engine`` Engine, for physical ``num_siblings`` Number of balanced or parallel siblings ``width`` Width of each sibling ``siblings`` Balanced siblings or num_siblings * width for parallel ``sseu`` Client-set SSEU parametersh](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjzubh:}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK[hjzubj")}(hstruct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; };h]hstruct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; };}hjzsbah}(h]h ]h"]h$]h&]jjuh1j"hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK]hjzubh)}(h **Members**h]jb)}(hjzh]hMembers}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjzubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKfhjzubjx)}(hhh](j})}(h``type`` Type of this engine h](j)}(h``type``h]j)}(hjzh]htype}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKmhjzubj)}(hhh]h)}(hType of this engineh]hType of this engine}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhKmhj{ubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1j|hjzhKmhjzubj})}(h ``engine`` Engine, for physical h](j)}(h ``engine``h]j)}(hj#{h]hengine}(hj%{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!{ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj{ubj)}(hhh]h)}(hEngine, for physicalh]hEngine, for physical}(hj<{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8{hKhj9{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j|hj8{hKhjzubj})}(h9``num_siblings`` Number of balanced or parallel siblings h](j)}(h``num_siblings``h]j)}(hj\{h]h num_siblings}(hj^{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ{ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjV{ubj)}(hhh]h)}(h'Number of balanced or parallel siblingsh]h'Number of balanced or parallel siblings}(hju{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjq{hKhjr{ubah}(h]h ]h"]h$]h&]uh1jhjV{ubeh}(h]h ]h"]h$]h&]uh1j|hjq{hKhjzubj})}(h ``width`` Width of each sibling h](j)}(h ``width``h]j)}(hj{h]hwidth}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj{ubj)}(hhh]h)}(hWidth of each siblingh]hWidth of each sibling}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hKhj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j|hj{hKhjzubj})}(hD``siblings`` Balanced siblings or num_siblings * width for parallel h](j)}(h ``siblings``h]j)}(hj{h]hsiblings}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj{ubj)}(hhh]h)}(h6Balanced siblings or num_siblings * width for parallelh]h6Balanced siblings or num_siblings * width for parallel}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hKhj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j|hj{hKhjzubj})}(h#``sseu`` Client-set SSEU parametersh](j)}(h``sseu``h]j)}(hj|h]hsseu}(hj |hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|ubj)}(hhh]h)}(hClient-set SSEU parametersh]hClient-set SSEU parameters}(hj |hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1j|hj|hKhjzubeh}(h]h ]h"]h$]h&]uh1jwhjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjthhhjuhNubh)}(h**Description**h]jb)}(hjJ|h]h Description}(hjL|hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjH|ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubh)}(hUThis struct describes an engine that a context may contain. Engines have four types:h]hUThis struct describes an engine that a context may contain. Engines have four types:}(hj`|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKXhjthhubjL)}(hX - I915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines. - I915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine. - I915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings. - I915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings. h]j:)}(hhh](j:)}(hXII915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines. h]h)}(hXHI915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines.h]hXHI915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines.}(hjz|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK[hjv|ubah}(h]h ]h"]h$]h&]uh1j:hjs|ubj:)}(heI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine. h]h)}(hdI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine.h]hdI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKahj|ubah}(h]h ]h"]h$]h&]uh1j:hjs|ubj:)}(hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings. h]h)}(hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings.h]hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKdhj|ubah}(h]h ]h"]h$]h&]uh1j:hjs|ubj:)}(hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings. h]h)}(hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings.h]hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKghj|ubah}(h]h ]h"]h$]h&]uh1j:hjs|ubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hj|hK[hjo|ubah}(h]h ]h"]h$]h&]uh1jKhj|hK[hjthhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!i915_gem_proto_context (C struct)c.i915_gem_proto_contexthNtauh1jhjthhhjuhNubj')}(hhh](j,)}(hi915_gem_proto_contexth]j2)}(hstruct i915_gem_proto_contexth](j)}(hjh]hstruct}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|hhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKnubji)}(h h]h }(hj }hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|hhhj }hKnubjz)}(hi915_gem_proto_contexth]j;)}(hj|h]hi915_gem_proto_context}(hj}hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj}ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj|hhhj }hKnubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj|hhhj }hKnubah}(h]j|ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj }hKnhj|hhubj1)}(hhh]h)}(hprototype contexth]hprototype context}(hjA}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj>}hhubah}(h]h ]h"]h$]h&]uh1j0hj|hhhj }hKnubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjY}jSjY}jTjUjVuh1j&hhhjthjuhNubjX)}(hXo**Definition**:: struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct i915_gem_proto_engine *user_engines; struct intel_sseu legacy_rcs_sseu; bool single_timeline; bool uses_protected_content; intel_wakeref_t pxp_wakeref; }; **Members** ``fpriv`` Client which creates the context ``vm`` See :c:type:`i915_gem_context.vm ` ``user_flags`` See :c:type:`i915_gem_context.user_flags ` ``sched`` See :c:type:`i915_gem_context.sched ` ``num_user_engines`` Number of user-specified engines or -1 ``user_engines`` User-specified engines ``legacy_rcs_sseu`` Client-set SSEU parameters for the legacy RCS ``single_timeline`` See See :c:type:`i915_gem_context.syncobj ` ``uses_protected_content`` See :c:type:`i915_gem_context.uses_protected_content ` ``pxp_wakeref`` See :c:type:`i915_gem_context.pxp_wakeref `h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hje}hhhNhNubah}(h]h ]h"]h$]h&]uh1jahja}ubh:}(hja}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj]}ubj")}(hX{struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct i915_gem_proto_engine *user_engines; struct intel_sseu legacy_rcs_sseu; bool single_timeline; bool uses_protected_content; intel_wakeref_t pxp_wakeref; };h]hX{struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct i915_gem_proto_engine *user_engines; struct intel_sseu legacy_rcs_sseu; bool single_timeline; bool uses_protected_content; intel_wakeref_t pxp_wakeref; };}hj~}sbah}(h]h ]h"]h$]h&]jjuh1j"hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj]}ubh)}(h **Members**h]jb)}(hj}h]hMembers}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj}ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj]}ubjx)}(hhh](j})}(h+``fpriv`` Client which creates the context h](j)}(h ``fpriv``h]j)}(hj}h]hfpriv}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj}ubj)}(hhh]h)}(h Client which creates the contexth]h Client which creates the context}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hKhj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j|hj}hKhj}ubj})}(h<``vm`` See :c:type:`i915_gem_context.vm ` h](j)}(h``vm``h]j)}(hj}h]hvm}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj}ubj)}(hhh]h)}(h4See :c:type:`i915_gem_context.vm `h](hSee }(hj~hhhNhNubh)}(h0:c:type:`i915_gem_context.vm `h]j)}(hj ~h]hi915_gem_context.vm}(hj ~hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhj}hKhj~ubeh}(h]h ]h"]h$]h&]uh1hhj}hKhj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j|hj}hKhj}ubj})}(hL``user_flags`` See :c:type:`i915_gem_context.user_flags ` h](j)}(h``user_flags``h]j)}(hj?~h]h user_flags}(hjA~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=~ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj9~ubj)}(hhh]h)}(h`h](hSee }(hjX~hhhNhNubh)}(h8:c:type:`i915_gem_context.user_flags `h]j)}(hjb~h]hi915_gem_context.user_flags}(hjd~hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj`~ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhjT~hKhjX~ubeh}(h]h ]h"]h$]h&]uh1hhjT~hKhjU~ubah}(h]h ]h"]h$]h&]uh1jhj9~ubeh}(h]h ]h"]h$]h&]uh1j|hjT~hKhj}ubj})}(hB``sched`` See :c:type:`i915_gem_context.sched ` h](j)}(h ``sched``h]j)}(hj~h]hsched}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj~ubj)}(hhh]h)}(h7See :c:type:`i915_gem_context.sched `h](hSee }(hj~hhhNhNubh)}(h3:c:type:`i915_gem_context.sched `h]j)}(hj~h]hi915_gem_context.sched}(hj~hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhj~hKhj~ubeh}(h]h ]h"]h$]h&]uh1hhj~hKhj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1j|hj~hKhj}ubj})}(h<``num_user_engines`` Number of user-specified engines or -1 h](j)}(h``num_user_engines``h]j)}(hj~h]hnum_user_engines}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj~ubj)}(hhh]h)}(h&Number of user-specified engines or -1h]h&Number of user-specified engines or -1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj}ubj})}(h(``user_engines`` User-specified engines h](j)}(h``user_engines``h]j)}(hj(h]h user_engines}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj"ubj)}(hhh]h)}(hUser-specified enginesh]hUser-specified engines}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKhj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj=hKhj}ubj})}(hB``legacy_rcs_sseu`` Client-set SSEU parameters for the legacy RCS h](j)}(h``legacy_rcs_sseu``h]j)}(hjah]hlegacy_rcs_sseu}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj[ubj)}(hhh]h)}(h-Client-set SSEU parameters for the legacy RCSh]h-Client-set SSEU parameters for the legacy RCS}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhKhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hjvhKhj}ubj})}(hR``single_timeline`` See See :c:type:`i915_gem_context.syncobj ` h](j)}(h``single_timeline``h]j)}(hjh]hsingle_timeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(h=See See :c:type:`i915_gem_context.syncobj `h](hSee See }(hjhhhNhNubh)}(h5:c:type:`i915_gem_context.syncobj `h]j)}(hjh]hi915_gem_context.syncobj}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj}ubj})}(hd``uses_protected_content`` See :c:type:`i915_gem_context.uses_protected_content ` h](j)}(h``uses_protected_content``h]j)}(hjh]huses_protected_content}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hHSee :c:type:`i915_gem_context.uses_protected_content `h](hSee }(hj hhhNhNubh)}(hD:c:type:`i915_gem_context.uses_protected_content `h]j)}(hjh]h'i915_gem_context.uses_protected_content}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhjhKhj ubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj}ubj})}(hM``pxp_wakeref`` See :c:type:`i915_gem_context.pxp_wakeref `h](j)}(h``pxp_wakeref``h]j)}(hjJh]h pxp_wakeref}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjDubj)}(hhh]h)}(h=See :c:type:`i915_gem_context.pxp_wakeref `h](hSee }(hjchhhNhNubh)}(h9:c:type:`i915_gem_context.pxp_wakeref `h]j)}(hjmh]hi915_gem_context.pxp_wakeref}(hjohhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjcubeh}(h]h ]h"]h$]h&]uh1hhjhKhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j|hj_hKhj}ubeh}(h]h ]h"]h$]h&]uh1jwhj]}ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjthhhjuhNubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubh)}(hXThe struct i915_gem_proto_context represents the creation parameters for a struct i915_gem_context. This is used to gather parameters provided either through creation flags or via SET_CONTEXT_PARAM so that, when we create the final i915_gem_context, those parameters can be immutable.h]hXThe struct i915_gem_proto_context represents the creation parameters for a struct i915_gem_context. This is used to gather parameters provided either through creation flags or via SET_CONTEXT_PARAM so that, when we create the final i915_gem_context, those parameters can be immutable.}(hj€hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubh)}(hXcThe context uAPI allows for two methods of setting context parameters: SET_CONTEXT_PARAM and CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called at any time while the later happens as part of GEM_CONTEXT_CREATE. When these were initially added, Currently, everything settable via one is settable via the other. While some params are fairly simple and setting them on a live context is harmless such the context priority, others are far trickier such as the VM or the set of engines. To avoid some truly nasty race conditions, we don't allow setting the VM or the set of engines on live contexts.h]hXeThe context uAPI allows for two methods of setting context parameters: SET_CONTEXT_PARAM and CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called at any time while the later happens as part of GEM_CONTEXT_CREATE. When these were initially added, Currently, everything settable via one is settable via the other. While some params are fairly simple and setting them on a live context is harmless such the context priority, others are far trickier such as the VM or the set of engines. To avoid some truly nasty race conditions, we don’t allow setting the VM or the set of engines on live contexts.}(hjрhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubh)}(hX The way we dealt with this without breaking older userspace that sets the VM or engine set via SET_CONTEXT_PARAM is to delay the creation of the actual context until after the client is done configuring it with SET_CONTEXT_PARAM. From the perspective of the client, it has the same u32 context ID the whole time. From the perspective of i915, however, it's an i915_gem_proto_context right up until the point where we attempt to do something which the proto-context can't handle at which point the real context gets created.Ah]hXThe way we dealt with this without breaking older userspace that sets the VM or engine set via SET_CONTEXT_PARAM is to delay the creation of the actual context until after the client is done configuring it with SET_CONTEXT_PARAM. From the perspective of the client, it has the same u32 context ID the whole time. From the perspective of i915, however, it’s an i915_gem_proto_context right up until the point where we attempt to do something which the proto-context can’t handle at which point the real context gets created.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubh)}(hXThis is accomplished via a little xarray dance. When GEM_CONTEXT_CREATE is called, we create a proto-context, reserve a slot in context_xa but leave it NULL, the proto-context in the corresponding slot in proto_context_xa. Then, whenever we go to look up a context, we first check context_xa. If it's there, we return the i915_gem_context and we're done. If it's not, we look in proto_context_xa and, if we find it there, we create the actual context and kill the proto-context.h]hXThis is accomplished via a little xarray dance. When GEM_CONTEXT_CREATE is called, we create a proto-context, reserve a slot in context_xa but leave it NULL, the proto-context in the corresponding slot in proto_context_xa. Then, whenever we go to look up a context, we first check context_xa. If it’s there, we return the i915_gem_context and we’re done. If it’s not, we look in proto_context_xa and, if we find it there, we create the actual context and kill the proto-context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubh)}(hAt the time we made this change (April, 2021), we did a fairly complete audit of existing userspace to ensure this wouldn't break anything:h]hAt the time we made this change (April, 2021), we did a fairly complete audit of existing userspace to ensure this wouldn’t break anything:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubjL)}(hX- Mesa/i965 didn't use the engines or VM APIs at all - Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API. - Mesa/iris didn't use the engines or VM APIs at all - The open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE. - The media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that. h]j:)}(hhh](j:)}(h3Mesa/i965 didn't use the engines or VM APIs at all h]h)}(h2Mesa/i965 didn't use the engines or VM APIs at allh]h4Mesa/i965 didn’t use the engines or VM APIs at all}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h]Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API. h]h)}(h\Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API.h]h^Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn’t use the VM API.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj-ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h3Mesa/iris didn't use the engines or VM APIs at all h]h)}(h2Mesa/iris didn't use the engines or VM APIs at allh]h4Mesa/iris didn’t use the engines or VM APIs at all}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjFubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hThe open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE. h]h)}(hThe open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE.h]hThe open-source compute-runtime didn’t yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj_ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that. h]h)}(hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that.h]hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjxubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hj&hKhj ubah}(h]h ]h"]h$]h&]uh1jKhj&hKhjthhubh)}(hXiIn order for this dance to work properly, any modification to an i915_gem_proto_context that is exposed to the client via drm_i915_file_private::proto_context_xa must be guarded by drm_i915_file_private::proto_context_lock. The exception is when a proto-context has not yet been exposed such as when handling CONTEXT_CREATE_SET_PARAM during GEM_CONTEXT_CREATE.h]hXiIn order for this dance to work properly, any modification to an i915_gem_proto_context that is exposed to the client via drm_i915_file_private::proto_context_xa must be guarded by drm_i915_file_private::proto_context_lock. The exception is when a proto-context has not yet been exposed such as when handling CONTEXT_CREATE_SET_PARAM during GEM_CONTEXT_CREATE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_context (C struct)c.i915_gem_contexthNtauh1jhjthhhjuhNubj')}(hhh](j,)}(hi915_gem_contexth]j2)}(hstruct i915_gem_contexth](j)}(hjh]hstruct}(hjŁhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubji)}(h h]h }(hjӁhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjҁhKubjz)}(hi915_gem_contexth]j;)}(hjh]hi915_gem_context}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjҁhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjҁhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjҁhKhjhhubj1)}(hhh]h)}(h client stateh]h client state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjҁhKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjthjuhNubjX)}(hX**Definition**:: struct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines __rcu *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; }; **Members** ``i915`` i915 device backpointer ``file_priv`` owning file descriptor ``engines`` User defined engines for this context Various uAPI offer the ability to lookup up an index from this array to select an engine operate on. Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines. Execbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index. User defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set). ``engines_mutex`` guards writes to engines ``syncobj`` Shared timeline syncobj When the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care. ``vm`` unique address space (GTT) In full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others. In other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT. ``pid`` process id of creator Note that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated. ``link`` place with :c:type:`drm_i915_private.context_list ` ``client`` struct i915_drm_client ``client_link`` for linking onto :c:type:`i915_drm_client.ctx_list ` ``ref`` reference count A reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access. ``release_work`` Work item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context. FIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock. ``rcu`` rcu_head for deferred freeing. ``user_flags`` small set of booleans controlled by the user ``flags`` small set of booleans ``uses_protected_content`` context uses PXP-encrypted objects. This flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts. ``pxp_wakeref`` wakeref to keep the device awake when PXP is in use PXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics. ``mutex`` guards everything that isn't engines or handles_vma ``sched`` scheduler parameters ``guilty_count`` How many times this context has caused a GPU hang. ``active_count`` How many times this context was active during a GPU hang, but did not cause it. ``hang_timestamp`` The last time(s) this context caused a GPU hang ``remap_slice`` Bitmask of cache lines that need remapping ``handles_vma`` rbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT) ``lut_mutex`` Locks handles_vma ``name`` arbitrary name, used for user debug A name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages. ``stale`` tracks stale engines to be destroyedh](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubh:}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj#ubj")}(hXstruct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines __rcu *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; };h]hXstruct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines __rcu *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; };}hjDsbah}(h]h ]h"]h$]h&]jjuh1j"hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj#ubh)}(h **Members**h]jb)}(hjUh]hMembers}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjSubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj#ubjx)}(hhh](j})}(h!``i915`` i915 device backpointer h](j)}(h``i915``h]j)}(hjth]hi915}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjnubj)}(hhh]h)}(hi915 device backpointerh]hi915 device backpointer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubj})}(h%``file_priv`` owning file descriptor h](j)}(h ``file_priv``h]j)}(hjh]h file_priv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(howning file descriptorh]howning file descriptor}(hjƂhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj‚hKhjÂubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj‚hKhjkubj})}(hX``engines`` User defined engines for this context Various uAPI offer the ability to lookup up an index from this array to select an engine operate on. Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines. Execbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index. User defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set). h](j)}(h ``engines``h]j)}(hjh]hengines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh](h)}(h%User defined engines for this contexth]h%User defined engines for this context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hdVarious uAPI offer the ability to lookup up an index from this array to select an engine operate on.h]hdVarious uAPI offer the ability to lookup up an index from this array to select an engine operate on.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(h{Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines.h]h{Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hXExecbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index.h]hXExecbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hVUser defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set).h]hVUser defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set).}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubj})}(h+``engines_mutex`` guards writes to engines h](j)}(h``engines_mutex``h]j)}(hj\h]h engines_mutex}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjVubj)}(hhh]h)}(hguards writes to enginesh]hguards writes to engines}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhKhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j|hjqhKhjkubj})}(hX``syncobj`` Shared timeline syncobj When the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care. h](j)}(h ``syncobj``h]j)}(hjh]hsyncobj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj)}(hhh](h)}(hShared timeline syncobjh]hShared timeline syncobj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubh)}(hXWhen the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care.h]hXWhen the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn’t provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that’s not likely to yield well- defined results anyway so we choose to not care.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjkubj})}(hX``vm`` unique address space (GTT) In full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others. In other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT. h](j)}(h``vm``h]j)}(hjރh]hvm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj܃ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj؃ubj)}(hhh](h)}(hunique address space (GTT)h]hunique address space (GTT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubh)}(hvIn full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others.h]hvIn full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubh)}(hgIn other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT.h]hgIn other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhj؃ubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjkubj})}(hX``pid`` process id of creator Note that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated. h](j)}(h``pid``h]j)}(hj6h]hpid}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM%hj0ubj)}(hhh](h)}(hprocess id of creatorh]hprocess id of creator}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM hjLubh)}(hNote that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated.h]hNote that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM"hjLubeh}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1j|hjKhM%hjkubj})}(hO``link`` place with :c:type:`drm_i915_private.context_list ` h](j)}(h``link``h]j)}(hjh]hlink}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjyubj)}(hhh]h)}(hEplace with :c:type:`drm_i915_private.context_list `h](h place with }(hjhhhNhNubh)}(h::c:type:`drm_i915_private.context_list `h]j)}(hjh]hdrm_i915_private.context_list}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjdrm_i915_privateuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubj})}(h"``client`` struct i915_drm_client h](j)}(h ``client``h]j)}(hjׄh]hclient}(hjلhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjՄubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjфubj)}(hhh]h)}(hstruct i915_drm_clienth]hstruct i915_drm_client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjфubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubj})}(hV``client_link`` for linking onto :c:type:`i915_drm_client.ctx_list ` h](j)}(h``client_link``h]j)}(hjh]h client_link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj ubj)}(hhh]h)}(hEfor linking onto :c:type:`i915_drm_client.ctx_list `h](hfor linking onto }(hj)hhhNhNubh)}(h4:c:type:`i915_drm_client.ctx_list `h]j)}(hj3h]hi915_drm_client.ctx_list}(hj5hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_drm_clientuh1hhj%hKhj)ubeh}(h]h ]h"]h$]h&]uh1hhj%hKhj&ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj%hKhjkubj})}(hX9``ref`` reference count A reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access. h](j)}(h``ref``h]j)}(hjhh]href}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM9hjbubj)}(hhh](h)}(hreference counth]hreference count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM3hj~ubh)}(hXA reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access.h]hXA reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM5hj~ubeh}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1j|hj}hM9hjkubj})}(hX```release_work`` Work item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context. FIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock. h](j)}(h``release_work``h]j)}(hjh]h release_work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMChjubj)}(hhh](h)}(heWork item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context.h]heWork item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context.}(hjʅhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM>hjDžubh)}(hFIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock.h](h(FIXME: The only real reason for this is }(hjمhhhNhNubh)}(h3:c:type:`i915_gem_engines.fence `h]j)}(hjh]hi915_gem_engines.fence}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_enginesuh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMAhjمubh, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock.}(hjمhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMAhjDžubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjƅhMChjkubj})}(h'``rcu`` rcu_head for deferred freeing. h](j)}(h``rcu``h]j)}(hjh]hrcu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMJhjubj)}(hhh]h)}(hrcu_head for deferred freeing.h]hrcu_head for deferred freeing.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMJhj3ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj2hMJhjkubj})}(h<``user_flags`` small set of booleans controlled by the user h](j)}(h``user_flags``h]j)}(hjVh]h user_flags}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMOhjPubj)}(hhh]h)}(h,small set of booleans controlled by the userh]h,small set of booleans controlled by the user}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhMOhjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j|hjkhMOhjkubj})}(h ``flags`` small set of booleans h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMYhjubj)}(hhh]h)}(hsmall set of booleansh]hsmall set of booleans}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMYhjkubj})}(hX4``uses_protected_content`` context uses PXP-encrypted objects. This flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts. h](j)}(h``uses_protected_content``h]j)}(hjȆh]huses_protected_content}(hjʆhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjƆubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMehj†ubj)}(hhh](h)}(h#context uses PXP-encrypted objects.h]h#context uses PXP-encrypted objects.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM`hjކubh)}(hThis flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts.h]hThis flag can only be set at ctx creation time and it’s immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMbhjކubeh}(h]h ]h"]h$]h&]uh1jhj†ubeh}(h]h ]h"]h$]h&]uh1j|hj݆hMehjkubj})}(hX``pxp_wakeref`` wakeref to keep the device awake when PXP is in use PXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics. h](j)}(h``pxp_wakeref``h]j)}(hjh]h pxp_wakeref}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMqhj ubj)}(hhh](h)}(h3wakeref to keep the device awake when PXP is in useh]h3wakeref to keep the device awake when PXP is in use}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMjhj'ubh)}(hXgPXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics.h]hXiPXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn’t worsen our power metrics.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMlhj'ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj&hMqhjkubj})}(h>``mutex`` guards everything that isn't engines or handles_vma h](j)}(h ``mutex``h]j)}(hjZh]hmutex}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjTubj)}(hhh]h)}(h3guards everything that isn't engines or handles_vmah]h5guards everything that isn’t engines or handles_vma}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohKhjpubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j|hjohKhjkubj})}(h``sched`` scheduler parameters h](j)}(h ``sched``h]j)}(hjh]hsched}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hscheduler parametersh]hscheduler parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubj})}(hD``guilty_count`` How many times this context has caused a GPU hang. h](j)}(h``guilty_count``h]j)}(hj̇h]h guilty_count}(hj·hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjʇubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjƇubj)}(hhh]h)}(h2How many times this context has caused a GPU hang.h]h2How many times this context has caused a GPU hang.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjƇubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubj})}(ha``active_count`` How many times this context was active during a GPU hang, but did not cause it. h](j)}(h``active_count``h]j)}(hjh]h active_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj)}(hhh]h)}(hOHow many times this context was active during a GPU hang, but did not cause it.h]hOHow many times this context was active during a GPU hang, but did not cause it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjkubj})}(hC``hang_timestamp`` The last time(s) this context caused a GPU hang h](j)}(h``hang_timestamp``h]j)}(hj?h]hhang_timestamp}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj9ubj)}(hhh]h)}(h/The last time(s) this context caused a GPU hangh]h/The last time(s) this context caused a GPU hang}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThMhjUubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j|hjThMhjkubj})}(h;``remap_slice`` Bitmask of cache lines that need remapping h](j)}(h``remap_slice``h]j)}(hjxh]h remap_slice}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjrubj)}(hhh]h)}(h*Bitmask of cache lines that need remappingh]h*Bitmask of cache lines that need remapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubj})}(h``handles_vma`` rbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT) h](j)}(h``handles_vma``h]j)}(hjh]h handles_vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj)}(hhh]h)}(hrbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT)h]hrbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT)}(hjʈhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjLjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjƈhMhjkubj})}(h ``lut_mutex`` Locks handles_vma h](j)}(h ``lut_mutex``h]j)}(hjh]h lut_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hLocks handles_vmah]hLocks handles_vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubj})}(h``name`` arbitrary name, used for user debug A name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages. h](j)}(h``name``h]j)}(hj$h]hname}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj)}(hhh](h)}(h#arbitrary name, used for user debugh]h#arbitrary name, used for user debug}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj:ubh)}(hA name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages.h]hA name is constructed for the context from the creator’s process name, pid and user handle in order to uniquely identify the context in messages.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj:ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj9hMhjkubj})}(h.``stale`` tracks stale engines to be destroyedh](j)}(h ``stale``h]j)}(hjmh]hstale}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjgubj)}(hhh]h)}(h$tracks stale engines to be destroyedh]h$tracks stale engines to be destroyed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjkubeh}(h]h ]h"]h$]h&]uh1jwhj#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjthhhjuhNubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubh)}(hzThe struct i915_gem_context represents the combined view of the driver and logical hardware state for a particular client.h]hzThe struct i915_gem_context represents the combined view of the driver and logical hardware state for a particular client.}(hjƉhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjthhubh)}(hXUserspace submits commands to be executed on the GPU as an instruction stream within a GEM object we call a batchbuffer. This instructions may refer to other GEM objects containing auxiliary state such as kernels, samplers, render targets and even secondary batchbuffers. Userspace does not know where in the GPU memory these objects reside and so before the batchbuffer is passed to the GPU for execution, those addresses in the batchbuffer and auxiliary objects are updated. This is known as relocation, or patching. To try and avoid having to relocate each object on the next execution, userspace is told the location of those objects in this pass, but this remains just a hint as the kernel may choose a new location for any object in the future.h]hXUserspace submits commands to be executed on the GPU as an instruction stream within a GEM object we call a batchbuffer. This instructions may refer to other GEM objects containing auxiliary state such as kernels, samplers, render targets and even secondary batchbuffers. Userspace does not know where in the GPU memory these objects reside and so before the batchbuffer is passed to the GPU for execution, those addresses in the batchbuffer and auxiliary objects are updated. This is known as relocation, or patching. To try and avoid having to relocate each object on the next execution, userspace is told the location of those objects in this pass, but this remains just a hint as the kernel may choose a new location for any object in the future.}(hjՉhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKXhjthhubh)}(hAt the level of talking to the hardware, submitting a batchbuffer for the GPU to execute is to add content to a buffer from which the HW command streamer is reading.h]hAt the level of talking to the hardware, submitting a batchbuffer for the GPU to execute is to add content to a buffer from which the HW command streamer is reading.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKdhjthhubj:)}(hhh](j:)}(hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items. h]h)}(hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items.h]hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h2Add a command to invalidate caches to the buffer. h]h)}(h1Add a command to invalidate caches to the buffer.h]h1Add a command to invalidate caches to the buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKlhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed. h]h)}(hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed.h]hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKnhj(ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h$Add a pipeline flush to the buffer. h]h)}(h#Add a pipeline flush to the buffer.h]h#Add a pipeline flush to the buffer.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKrhjAubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hX4Add a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, ``i915_request::global_seqno``; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer. h]h)}(hX3Add a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, ``i915_request::global_seqno``; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer.h](hAdd a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, }(hj^hhhNhNubj)}(h``i915_request::global_seqno``h]hi915_request::global_seqno}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubho; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer.}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKthjZubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed. h]h)}(hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed.h]hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKzhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hcInform the hardware of the additional commands added to the buffer (by updating the tail pointer). h]h)}(hbInform the hardware of the additional commands added to the buffer (by updating the tail pointer).h]hbInform the hardware of the additional commands added to the buffer (by updating the tail pointer).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chK~hjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hjthhhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chNubh)}(hGProcessing an execbuf ioctl is conceptually split up into a few phases.h]hGProcessing an execbuf ioctl is conceptually split up into a few phases.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjthhubj:)}(hhh](j:)}(hBValidation - Ensure all the pointers, handles and flags are valid.h]h)}(hjҊh]hBValidation - Ensure all the pointers, handles and flags are valid.}(hjԊhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjЊubah}(h]h ]h"]h$]h&]uh1j:hj͊ubj:)}(h7Reservation - Assign GPU address space for every objecth]h)}(hjh]h7Reservation - Assign GPU address space for every object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjubah}(h]h ]h"]h$]h&]uh1j:hj͊ubj:)}(hARelocation - Update any addresses to point to the final locationsh]h)}(hjh]hARelocation - Update any addresses to point to the final locations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjubah}(h]h ]h"]h$]h&]uh1j:hj͊ubj:)}(hBSerialisation - Order the request with respect to its dependenciesh]h)}(hjh]hBSerialisation - Order the request with respect to its dependencies}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjubah}(h]h ]h"]h$]h&]uh1j:hj͊ubj:)}(h=Construction - Construct a request to execute the batchbufferh]h)}(hj2h]h=Construction - Construct a request to execute the batchbuffer}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj0ubah}(h]h ]h"]h$]h&]uh1j:hj͊ubj:)}(h3Submission (at some point in the future execution) h]h)}(h2Submission (at some point in the future execution)h]h2Submission (at some point in the future execution)}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjHubah}(h]h ]h"]h$]h&]uh1j:hj͊ubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hjthhhjhNubh)}(hXReserving resources for the execbuf is the most complicated phase. We neither want to have to migrate the object in the address space, nor do we want to have to update any relocations pointing to this object. Ideally, we want to leave the object where it is and for all the existing relocations to match. If the object is given a new address, or if userspace thinks the object is elsewhere, we have to parse all the relocation entries and update the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that all the target addresses in all of its objects match the value in the relocation entries and that they all match the presumed offsets given by the list of execbuffer objects. Using this knowledge, we know that if we haven't moved any buffers, all the relocation entries are valid and we can skip the update. (If userspace is wrong, the likely outcome is an impromptu GPU hang.) The requirement for using I915_EXEC_NO_RELOC are:h]hXReserving resources for the execbuf is the most complicated phase. We neither want to have to migrate the object in the address space, nor do we want to have to update any relocations pointing to this object. Ideally, we want to leave the object where it is and for all the existing relocations to match. If the object is given a new address, or if userspace thinks the object is elsewhere, we have to parse all the relocation entries and update the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that all the target addresses in all of its objects match the value in the relocation entries and that they all match the presumed offsets given by the list of execbuffer objects. Using this knowledge, we know that if we haven’t moved any buffers, all the relocation entries are valid and we can skip the update. (If userspace is wrong, the likely outcome is an impromptu GPU hang.) The requirement for using I915_EXEC_NO_RELOC are:}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjthhubjL)}(hX[The addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset. Any render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE. To avoid stalling, execobject.offset should match the current address of that object within the active context. h](h)}(hThe addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset.h]hThe addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjvubh)}(hRAny render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE.h]hRAny render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjvubh)}(hoTo avoid stalling, execobject.offset should match the current address of that object within the active context.h]hoTo avoid stalling, execobject.offset should match the current address of that object within the active context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjvubeh}(h]h ]h"]h$]h&]uh1jKhjhKhjthhubh)}(hXTThe reservation is done is multiple phases. First we try and keep any object already bound in its current location - so as long as meets the constraints imposed by the new execbuffer. Any object left unbound after the first pass is then fitted into any available idle space. If an object does not fit, all objects are removed from the reservation and the process rerun after sorting the objects into a priority order (more difficult to fit objects are tried first). Failing that, the entire VM is cleared and we try to fit the execbuf once last time before concluding that it simply will not fit.Yh]hXTThe reservation is done is multiple phases. First we try and keep any object already bound in its current location - so as long as meets the constraints imposed by the new execbuffer. Any object left unbound after the first pass is then fitted into any available idle space. If an object does not fit, all objects are removed from the reservation and the process rerun after sorting the objects into a priority order (more difficult to fit objects are tried first). Failing that, the entire VM is cleared and we try to fit the execbuf once last time before concluding that it simply will not fit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjthhubh)}(hXBA small complication to all of this is that we allow userspace not only to specify an alignment and a size for the object in the address space, but we also allow userspace to specify the exact offset. This objects are simpler to place (the location is known a priori) all we have to do is make sure the space is available.h]hXBA small complication to all of this is that we allow userspace not only to specify an alignment and a size for the object in the address space, but we also allow userspace to specify the exact offset. This objects are simpler to place (the location is known a priori) all we have to do is make sure the space is available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjthhubh)}(hX1Once all the objects are in place, patching up the buried pointers to point to the final locations is a fairly simple job of walking over the relocation entry arrays, looking up the right address and rewriting the value into the object. Simple! ... The relocation entries are stored in user memory and so to access them we have to copy them into a local buffer. That copy has to avoid taking any pagefaults as they may lead back to a GEM object requiring the struct_mutex (i.e. recursive deadlock). So once again we split the relocation into multiple passes. First we try to do everything within an atomic context (avoid the pagefaults) which requires that we never wait. If we detect that we may wait, or if we need to fault, then we have to fallback to a slower path. The slowpath has to drop the mutex. (Can you hear alarm bells yet?) Dropping the mutex means that we lose all the state we have built up so far for the execbuf and we must reset any global data. However, we do leave the objects pinned in their final locations - which is a potential issue for concurrent execbufs. Once we have left the mutex, we can allocate and copy all the relocation entries into a large array at our leisure, reacquire the mutex, reclaim all the objects and other state and then proceed to update any incorrect addresses with the objects.h]hX1Once all the objects are in place, patching up the buried pointers to point to the final locations is a fairly simple job of walking over the relocation entry arrays, looking up the right address and rewriting the value into the object. Simple! ... The relocation entries are stored in user memory and so to access them we have to copy them into a local buffer. That copy has to avoid taking any pagefaults as they may lead back to a GEM object requiring the struct_mutex (i.e. recursive deadlock). So once again we split the relocation into multiple passes. First we try to do everything within an atomic context (avoid the pagefaults) which requires that we never wait. If we detect that we may wait, or if we need to fault, then we have to fallback to a slower path. The slowpath has to drop the mutex. (Can you hear alarm bells yet?) Dropping the mutex means that we lose all the state we have built up so far for the execbuf and we must reset any global data. However, we do leave the objects pinned in their final locations - which is a potential issue for concurrent execbufs. Once we have left the mutex, we can allocate and copy all the relocation entries into a large array at our leisure, reacquire the mutex, reclaim all the objects and other state and then proceed to update any incorrect addresses with the objects.}(hjˋhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjthhubh)}(hXAs we process the relocation entries, we maintain a record of whether the object is being written to. Using NORELOC, we expect userspace to provide this information instead. We also check whether we can skip the relocation by comparing the expected value inside the relocation entry with the target's final address. If they differ, we have to map the current object and rewrite the 4 or 8 byte pointer within.h]hXAs we process the relocation entries, we maintain a record of whether the object is being written to. Using NORELOC, we expect userspace to provide this information instead. We also check whether we can skip the relocation by comparing the expected value inside the relocation entry with the target’s final address. If they differ, we have to map the current object and rewrite the 4 or 8 byte pointer within.}(hjڋhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjthhubh)}(hXSerialising an execbuf is quite simple according to the rules of the GEM ABI. Execution within each context is ordered by the order of submission. Writes to any GEM object are in order of submission and are exclusive. Reads from a GEM object are unordered with respect to other reads, but ordered by writes. A write submitted after a read cannot occur before the read, and similarly any read submitted after a write cannot occur before the write. Writes are ordered between engines such that only one write occurs at any time (completing any reads beforehand) - using semaphores where available and CPU serialisation otherwise. Other GEM access obey the same rules, any write (either via mmaps using set-domain, or via pwrite) must flush all GPU reads before starting, and any read (either using set-domain or pread) must flush all GPU writes before starting. (Note we only employ a barrier before, we currently rely on userspace not concurrently starting a new execution whilst reading or writing to an object. This may be an advantage or not depending on how much you trust userspace not to shoot themselves in the foot.) Serialisation may just result in the request being inserted into a DAG awaiting its turn, but most simple is to wait on the CPU until all dependencies are resolved.h]hXSerialising an execbuf is quite simple according to the rules of the GEM ABI. Execution within each context is ordered by the order of submission. Writes to any GEM object are in order of submission and are exclusive. Reads from a GEM object are unordered with respect to other reads, but ordered by writes. A write submitted after a read cannot occur before the read, and similarly any read submitted after a write cannot occur before the write. Writes are ordered between engines such that only one write occurs at any time (completing any reads beforehand) - using semaphores where available and CPU serialisation otherwise. Other GEM access obey the same rules, any write (either via mmaps using set-domain, or via pwrite) must flush all GPU reads before starting, and any read (either using set-domain or pread) must flush all GPU writes before starting. (Note we only employ a barrier before, we currently rely on userspace not concurrently starting a new execution whilst reading or writing to an object. This may be an advantage or not depending on how much you trust userspace not to shoot themselves in the foot.) Serialisation may just result in the request being inserted into a DAG awaiting its turn, but most simple is to wait on the CPU until all dependencies are resolved.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjthhubh)}(hX&After all of that, is just a matter of closing the request and handing it to the hardware (well, leaving it in a queue to be executed). However, we also offer the ability for batchbuffers to be run with elevated privileges so that they access otherwise hidden registers. (Used to adjust L3 cache etc.) Before any batch is given extra privileges we first must check that it contains no nefarious instructions, we check that each instruction is from our whitelist and all registers are also from an allowed list. We first copy the user's batchbuffer to a shadow (so that the user doesn't have access to it, either by the CPU or GPU as we scan it) and then parse each instruction. If everything is ok, we set a flag telling the hardware to run the batchbuffer in trusted mode, otherwise the ioctl is rejected.h]hX*After all of that, is just a matter of closing the request and handing it to the hardware (well, leaving it in a queue to be executed). However, we also offer the ability for batchbuffers to be run with elevated privileges so that they access otherwise hidden registers. (Used to adjust L3 cache etc.) Before any batch is given extra privileges we first must check that it contains no nefarious instructions, we check that each instruction is from our whitelist and all registers are also from an allowed list. We first copy the user’s batchbuffer to a shadow (so that the user doesn’t have access to it, either by the CPU or GPU as we scan it) and then parse each instruction. If everything is ok, we set a flag telling the hardware to run the batchbuffer in trusted mode, otherwise the ioctl is rejected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjthhubeh}(h]user-batchbuffer-executionah ]h"]user batchbuffer executionah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(h Schedulingh]h Scheduling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_sched_engine (C struct)c.i915_sched_enginehNtauh1jhjhhhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhNubj')}(hhh](j,)}(hi915_sched_engineh]j2)}(hstruct i915_sched_engineh](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKubji)}(h h]h }(hjHhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj6hhhjGhKubjz)}(hi915_sched_engineh]j;)}(hj4h]hi915_sched_engine}(hjZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj6hhhjGhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj2hhhjGhKubah}(h]j,ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjGhKhj/hhubj1)}(hhh]h)}(hscheduler engineh]hscheduler engine}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK_hjyhhubah}(h]h ]h"]h$]h&]uh1j0hj/hhhjGhKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhj.hNubjX)}(hXX **Definition**:: struct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); }; **Members** ``ref`` reference count of schedule engine object ``lock`` protects requests in priority lists, requests, hold and tasklet while running ``requests`` list of requests inflight on this schedule engine ``hold`` list of ready requests, but on hold ``tasklet`` softirq tasklet for submission ``default_priolist`` priority list for I915_PRIORITY_NORMAL ``queue_priority_hint`` Highest pending priority. When we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority. ``queue`` queue of requests, in priority lists ``no_priolist`` priority lists disabled ``private_data`` private data of the submission backend ``destroy`` destroy schedule engine / cleanup in backend ``disabled`` check if backend has disabled submission ``kick_backend`` kick backend after a request's priority has changed ``bump_inflight_request_prio`` update priority of an inflight request ``retire_inflight_request_prio`` indicate request is retired to priority tracking ``schedule`` adjust priority of request Call when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKchjubj")}(hXstruct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); };h]hXstruct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); };}hjsbah}(h]h ]h"]h$]h&]jjuh1j"he/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKehjubh)}(h **Members**h]jb)}(hjʌh]hMembers}(hǰhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjȌubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKxhjubjx)}(hhh](j})}(h2``ref`` reference count of schedule engine object h](j)}(h``ref``h]j)}(hjh]href}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKlhjubj)}(hhh]h)}(h)reference count of schedule engine objecth]h)reference count of schedule engine object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKlhjubj})}(hW``lock`` protects requests in priority lists, requests, hold and tasklet while running h](j)}(h``lock``h]j)}(hj"h]hlock}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKrhjubj)}(hhh]h)}(hMprotects requests in priority lists, requests, hold and tasklet while runningh]hMprotects requests in priority lists, requests, hold and tasklet while running}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKqhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj7hKrhjubj})}(h?``requests`` list of requests inflight on this schedule engine h](j)}(h ``requests``h]j)}(hj\h]hrequests}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKwhjVubj)}(hhh]h)}(h1list of requests inflight on this schedule engineh]h1list of requests inflight on this schedule engine}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhKwhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j|hjqhKwhjubj})}(h-``hold`` list of ready requests, but on hold h](j)}(h``hold``h]j)}(hjh]hhold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK|hjubj)}(hhh]h)}(h#list of ready requests, but on holdh]h#list of ready requests, but on hold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK|hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK|hjubj})}(h+``tasklet`` softirq tasklet for submission h](j)}(h ``tasklet``h]j)}(hj΍h]htasklet}(hjЍhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj̍ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjȍubj)}(hhh]h)}(hsoftirq tasklet for submissionh]hsoftirq tasklet for submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjȍubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h<``default_priolist`` priority list for I915_PRIORITY_NORMAL h](j)}(h``default_priolist``h]j)}(hjh]hdefault_priolist}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h&priority list for I915_PRIORITY_NORMALh]h&priority list for I915_PRIORITY_NORMAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hX ``queue_priority_hint`` Highest pending priority. When we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority. h](j)}(h``queue_priority_hint``h]j)}(hj@h]hqueue_priority_hint}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhj:ubj)}(hhh](h)}(hHighest pending priority.h]hHighest pending priority.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjVubh)}(hXWhen we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority.h]hXWhen we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjVubeh}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1j|hjUhKhjubj})}(h/``queue`` queue of requests, in priority lists h](j)}(h ``queue``h]j)}(hjh]hqueue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h$queue of requests, in priority listsh]h$queue of requests, in priority lists}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h(``no_priolist`` priority lists disabled h](j)}(h``no_priolist``h]j)}(hjŽh]h no_priolist}(hjĎhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(hpriority lists disabledh]hpriority lists disabled}(hjێhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj׎hKhj؎ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj׎hKhjubj})}(h8``private_data`` private data of the submission backend h](j)}(h``private_data``h]j)}(hjh]h private_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h&private data of the submission backendh]h&private data of the submission backend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h9``destroy`` destroy schedule engine / cleanup in backend h](j)}(h ``destroy``h]j)}(hj4h]hdestroy}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhj.ubj)}(hhh]h)}(h,destroy schedule engine / cleanup in backendh]h,destroy schedule engine / cleanup in backend}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhKhjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hjIhKhjubj})}(h6``disabled`` check if backend has disabled submission h](j)}(h ``disabled``h]j)}(hjmh]hdisabled}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjgubj)}(hhh]h)}(h(check if backend has disabled submissionh]h(check if backend has disabled submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hE``kick_backend`` kick backend after a request's priority has changed h](j)}(h``kick_backend``h]j)}(hjh]h kick_backend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h3kick backend after a request's priority has changedh]h5kick backend after a request’s priority has changed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hF``bump_inflight_request_prio`` update priority of an inflight request h](j)}(h``bump_inflight_request_prio``h]j)}(hjߏh]hbump_inflight_request_prio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjݏubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjُubj)}(hhh]h)}(h&update priority of an inflight requesth]h&update priority of an inflight request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjُubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hR``retire_inflight_request_prio`` indicate request is retired to priority tracking h](j)}(h ``retire_inflight_request_prio``h]j)}(hjh]hretire_inflight_request_prio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h0indicate request is retired to priority trackingh]h0indicate request is retired to priority tracking}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj-hKhjubj})}(h``schedule`` adjust priority of request Call when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h](j)}(h ``schedule``h]j)}(hjRh]hschedule}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjLubj)}(hhh](h)}(hadjust priority of requesth]hadjust priority of request}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjhubh)}(hCall when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h]hCall when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjhubeh}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjghKhjubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhj.hNubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjhhubh)}(hA schedule engine represents a submission queue with different priority bands. It contains all the common state (relative to the backend) to queue, track, and submit a request.h]hA schedule engine represents a submission queue with different priority bands. It contains all the common state (relative to the backend) to queue, track, and submit a request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK`hjhhubh)}(hThis object at the moment is quite i915 specific but will transition into a container for the drm_gpu_scheduler plus a few other variables once the i915 is integrated with the DRM scheduler.h]hThis object at the moment is quite i915 specific but will transition into a container for the drm_gpu_scheduler plus a few other variables once the i915 is integrated with the DRM scheduler.}(hjɐhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKdhjhhubeh}(h] schedulingah ]h"] schedulingah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(h2Logical Rings, Logical Ring Contexts and Execlistsh]h2Logical Rings, Logical Ring Contexts and Execlists}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hMotivation: GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". These expanded contexts enable a number of new abilities, especially "Execlists" (also implemented in this file).h]hMotivation: GEN8 brings an expansion of the HW contexts: “Logical Ring Contexts”. These expanded contexts enable a number of new abilities, especially “Execlists” (also implemented in this file).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhjhhubh)}(hOne of the main differences with the legacy HW contexts is that logical ring contexts incorporate many more things to the context's state, like PDPs or ringbuffer control registers:h]hOne of the main differences with the legacy HW contexts is that logical ring contexts incorporate many more things to the context’s state, like PDPs or ringbuffer control registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK hjhhubh)}(hX The reason why PDPs are included in the context is straightforward: as PPGTTs (per-process GTTs) are actually per-context, having the PDPs contained there mean you don't need to do a ppgtt->switch_mm yourself, instead, the GPU will do it for you on the context switch.h]hXThe reason why PDPs are included in the context is straightforward: as PPGTTs (per-process GTTs) are actually per-context, having the PDPs contained there mean you don’t need to do a ppgtt->switch_mm yourself, instead, the GPU will do it for you on the context switch.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhjhhubh)}(hXBut, what about the ringbuffer control registers (head, tail, etc..)? shouldn't we just need a set of those per engine command streamer? This is where the name "Logical Rings" starts to make sense: by virtualizing the rings, the engine cs shifts to a new "ring buffer" with every context switch. When you want to submit a workload to the GPU you: A) choose your context, B) find its appropriate virtualized ring, C) write commands to it and then, finally, D) tell the GPU to switch to that context.h]hXBut, what about the ringbuffer control registers (head, tail, etc..)? shouldn’t we just need a set of those per engine command streamer? This is where the name “Logical Rings” starts to make sense: by virtualizing the rings, the engine cs shifts to a new “ring buffer” with every context switch. When you want to submit a workload to the GPU you: A) choose your context, B) find its appropriate virtualized ring, C) write commands to it and then, finally, D) tell the GPU to switch to that context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhjhhubh)}(hInstead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch to a contexts is via a context execution list, ergo "Execlists".h]hInstead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch to a contexts is via a context execution list, ergo “Execlists”.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhjhhubh)}(h@LRC implementation: Regarding the creation of contexts, we have:h]h@LRC implementation: Regarding the creation of contexts, we have:}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK hjhhubj:)}(hhh](j:)}(hOne global default context.h]h)}(hjPh]hOne global default context.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK#hjNubah}(h]h ]h"]h$]h&]uh1j:hjKubj:)}(h-One local default context for each opened fd.h]h)}(hjhh]h-One local default context for each opened fd.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK$hjfubah}(h]h ]h"]h$]h&]uh1j:hjKubj:)}(hhjhhubh)}(hXWhen a request is committed, its commands (the BB start and any leading or trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer for the appropriate context. The tail pointer in the hardware context is not updated at this time, but instead, kept by the driver in the ringbuffer structure. A structure representing this request is added to a request queue for the appropriate engine: this structure contains a copy of the context's tail after the request was written to the ring buffer and a pointer to the context itself.h]hX!When a request is committed, its commands (the BB start and any leading or trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer for the appropriate context. The tail pointer in the hardware context is not updated at this time, but instead, kept by the driver in the ringbuffer structure. A structure representing this request is added to a request queue for the appropriate engine: this structure contains a copy of the context’s tail after the request was written to the ring buffer and a pointer to the context itself.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKChjhhubh)}(hXQIf the engine's request queue was empty before the request was added, the queue is processed immediately. Otherwise the queue will be processed during a context switch interrupt. In any case, elements on the queue will get sent (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a globally unique 20-bits submission ID.h]hXUIf the engine’s request queue was empty before the request was added, the queue is processed immediately. Otherwise the queue will be processed during a context switch interrupt. In any case, elements on the queue will get sent (in pairs) to the GPU’s ExecLists Submit Port (ELSP, for short) with a globally unique 20-bits submission ID.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKLhjhhubh)}(hXWhen execution of a request completes, the GPU updates the context status buffer with a context complete event and generates a context switch interrupt. During the interrupt handling, the driver examines the events in the buffer: for each context complete event, if the announced ID matches that on the head of the request queue, then that request is retired and removed from the queue.h]hXWhen execution of a request completes, the GPU updates the context status buffer with a context complete event and generates a context switch interrupt. During the interrupt handling, the driver examines the events in the buffer: for each context complete event, if the announced ID matches that on the head of the request queue, then that request is retired and removed from the queue.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKRhjhhubh)}(hXAfter processing, if any requests were retired and the queue is not empty then a new execution list can be submitted. The two requests at the front of the queue are next to be submitted but since a context may not occur twice in an execution list, if subsequent requests have the same ID as the first then the two requests must be combined. This is done simply by discarding requests at the head of the queue until either only one requests is left (in which case we use a NULL second context) or the first two requests have unique IDs.h]hXAfter processing, if any requests were retired and the queue is not empty then a new execution list can be submitted. The two requests at the front of the queue are next to be submitted but since a context may not occur twice in an execution list, if subsequent requests have the same ID as the first then the two requests must be combined. This is done simply by discarding requests at the head of the queue until either only one requests is left (in which case we use a NULL second context) or the first two requests have unique IDs.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKXhjhhubh)}(hXBy always executing the first two requests in the queue the driver ensures that the GPU is kept as busy as possible. In the case where a single context completes but a second context is still executing, the request for this second context will be at the head of the queue when we remove the first one. This request will then be resubmitted along with a new request for a different context, which will cause the hardware to continue executing the second request and queue the new request (the GPU detects the condition of a context getting preempted with the same context and optimizes the context switch flow by not doing preemption, but just sampling the new tail pointer).h]hXBy always executing the first two requests in the queue the driver ensures that the GPU is kept as busy as possible. In the case where a single context completes but a second context is still executing, the request for this second context will be at the head of the queue when we remove the first one. This request will then be resubmitted along with a new request for a different context, which will cause the hardware to continue executing the second request and queue the new request (the GPU detects the condition of a context getting preempted with the same context and optimizes the context switch flow by not doing preemption, but just sampling the new tail pointer).}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK`hjhhubeh}(h]1logical-rings-logical-ring-contexts-and-execlistsah ]h"]2logical rings, logical ring contexts and execlistsah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(hGlobal GTT viewsh]hGlobal GTT views}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhhhhhMubh)}(hBackground and previous stateh]hBackground and previous state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK&hjuhhubh)}(hHistorically objects could exists (be bound) in global GTT space only as singular instances with a view representing all of the object's backing pages in a linear fashion. This view will be called a normal view.h]hHistorically objects could exists (be bound) in global GTT space only as singular instances with a view representing all of the object’s backing pages in a linear fashion. This view will be called a normal view.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK(hjuhhubh)}(hTo support multiple views of the same object, where the number of mapped pages is not equal to the backing store, or where the layout of the pages is not linear, concept of a GGTT view was added.h]hTo support multiple views of the same object, where the number of mapped pages is not equal to the backing store, or where the layout of the pages is not linear, concept of a GGTT view was added.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK,hjuhhubh)}(hOne example of an alternative view is a stereo display driven by a single image. In this case we would have a framebuffer looking like this (2x2 pages):h]hOne example of an alternative view is a stereo display driven by a single image. In this case we would have a framebuffer looking like this (2x2 pages):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK0hjuhhubjL)}(h12 34 h]h)}(h12 34h]h12 34}(hjƒhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK4hj’ubah}(h]h ]h"]h$]h&]uh1jKhjԒhK4hjuhhubh)}(hAbove would represent a normal GGTT view as normally mapped for GPU or CPU rendering. In contrast, fed to the display engine would be an alternative view which could look something like this:h]hAbove would represent a normal GGTT view as normally mapped for GPU or CPU rendering. In contrast, fed to the display engine would be an alternative view which could look something like this:}(hjےhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK7hjuhhubjL)}(h 1212 3434 h]h)}(h 1212 3434h]h 1212 3434}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK;hjubah}(h]h ]h"]h$]h&]uh1jKhjhK;hjuhhubh)}(hlIn this example both the size and layout of pages in the alternative view is different from the normal view.h]hlIn this example both the size and layout of pages in the alternative view is different from the normal view.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK>hjuhhubh)}(hImplementation and usageh]hImplementation and usage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKAhjuhhubh)}(hqGGTT views are implemented using VMAs and are distinguished via enum i915_gtt_view_type and struct i915_gtt_view.h]hqGGTT views are implemented using VMAs and are distinguished via enum i915_gtt_view_type and struct i915_gtt_view.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKChjuhhubh)}(hXA new flavour of core GEM functions which work with GGTT bound objects were added with the _ggtt_ infix, and sometimes with _view postfix to avoid renaming in large amounts of code. They take the struct i915_gtt_view parameter encapsulating all metadata required to implement a view.h]hXA new flavour of core GEM functions which work with GGTT bound objects were added with the _ggtt_ infix, and sometimes with _view postfix to avoid renaming in large amounts of code. They take the struct i915_gtt_view parameter encapsulating all metadata required to implement a view.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKFhjuhhubh)}(hAs a helper for callers which are only interested in the normal view, globally const i915_gtt_view_normal singleton instance exists. All old core GEM API functions, the ones not taking the view parameter, are operating on, or with the normal GGTT view.h]hAs a helper for callers which are only interested in the normal view, globally const i915_gtt_view_normal singleton instance exists. All old core GEM API functions, the ones not taking the view parameter, are operating on, or with the normal GGTT view.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKKhjuhhubh)}(h4Code wanting to add or use a new GGTT view needs to:h]h4Code wanting to add or use a new GGTT view needs to:}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKPhjuhhubj:)}(hhh](j:)}(h$Add a new enum with a suitable name.h]h)}(hjbh]h$Add a new enum with a suitable name.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKRhj`ubah}(h]h ]h"]h$]h&]uh1j:hj]ubj:)}(h?Extend the metadata in the i915_gtt_view structure if required.h]h)}(hjzh]h?Extend the metadata in the i915_gtt_view structure if required.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKShjxubah}(h]h ]h"]h$]h&]uh1j:hj]ubj:)}(h%Add support to i915_get_vma_pages(). h]h)}(h$Add support to i915_get_vma_pages().h]h$Add support to i915_get_vma_pages().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKThjubah}(h]h ]h"]h$]h&]uh1j:hj]ubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hjuhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhNubh)}(hNew views are required to build a scatter-gather table from within the i915_get_vma_pages function. This table is stored in the vma.gtt_view and exists for the lifetime of an VMA.h]hNew views are required to build a scatter-gather table from within the i915_get_vma_pages function. This table is stored in the vma.gtt_view and exists for the lifetime of an VMA.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKVhjuhhubh)}(hCore API is designed to have copy semantics which means that passed in struct i915_gtt_view does not need to be persistent (left around after calling the core API functions).h]hCore API is designed to have copy semantics which means that passed in struct i915_gtt_view does not need to be persistent (left around after calling the core API functions).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKZhjuhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!i915_gem_gtt_reserve (C function)c.i915_gem_gtt_reservehNtauh1jhjuhhhNhNubj')}(hhh](j,)}(hint i915_gem_gtt_reserve (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h]j2)}(hint i915_gem_gtt_reserve(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chK`ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhK`ubjz)}(hi915_gem_gtt_reserveh]j;)}(hi915_gem_gtt_reserveh]hi915_gem_gtt_reserve}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhK`ubj)}(h(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj1hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjBhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj?ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjDmodnameN classnameNjXj[)}j^]ja)}jTj sbc.i915_gem_gtt_reserveasbuh1hhj ubji)}(h h]h }(hjbhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hvmh]hvm}(hj}hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j^c.i915_gem_gtt_reserveasbuh1hhjubji)}(h h]h }(hjҔhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hwwh]hww}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_mm_node *nodeh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h drm_mm_nodeh]h drm_mm_node}(hj$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj!ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj&modnameN classnameNjXj[)}j^]j^c.i915_gem_gtt_reserveasbuh1hhjubji)}(h h]h }(hjBhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hnodeh]hnode}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu64 sizeh](h)}(hhh]j;)}(hu64h]hu64}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjvubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj{modnameN classnameNjXj[)}j^]j^c.i915_gem_gtt_reserveasbuh1hhjrubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrubj;)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjrubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u64 offseth](h)}(hhh]j;)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjÕmodnameN classnameNjXj[)}j^]j^c.i915_gem_gtt_reserveasbuh1hhjubji)}(h h]h }(hjߕhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hoffseth]hoffset}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned long colorh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hlongh]hlong}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj0hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hcolorh]hcolor}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int flagsh](j)}(hunsignedh]hunsigned}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubji)}(h h]h }(hjehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubj)}(hinth]hint}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubj;)}(hflagsh]hflags}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhK`ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjߓhhhjhK`ubah}(h]jړah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhK`hjܓhhubj1)}(hhh]h)}(h(reserve a node in an address_space (GTT)h]h(reserve a node in an address_space (GTT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKGhjhhubah}(h]h ]h"]h$]h&]uh1j0hjܓhhhjhK`ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjіjSjіjTjUjVuh1j&hhhjuhNhNubjX)}(hX**Parameters** ``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) ``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned ``u64 offset`` where to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address space ``unsigned long color`` color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE ``unsigned int flags`` control search and eviction behaviour **Description** i915_gem_gtt_reserve() tries to insert the **node** at the exact **offset** inside the address space (using **size** and **color**). If the **node** does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure. **Return** 0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h](h)}(h**Parameters**h]jb)}(hjۖh]h Parameters}(hjݖhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjٖubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKKhjՖubjx)}(hhh](j})}(h_``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` h](j)}(h!``struct i915_address_space *vm``h]j)}(hjh]hstruct i915_address_space *vm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKHhjubj)}(hhh]h)}(h`h](hthe }(hjhhhNhNubh)}(h8:c:type:`struct i915_address_space `h]j)}(hjh]hstruct i915_address_space}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_address_spaceuh1hhjhKHhjubeh}(h]h ]h"]h$]h&]uh1hhjhKHhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKHhjubj})}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hjRh]hstruct i915_gem_ww_ctx *ww}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKIhjLubj)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghKIhjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjghKIhjubj})}(hf``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) h](j)}(h``struct drm_mm_node *node``h]j)}(hjh]hstruct drm_mm_node *node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKJhjubj)}(hhh]h)}(hHthe :c:type:`struct drm_mm_node ` (typically i915_vma.node)h](hthe }(hjhhhNhNubh)}(h*:c:type:`struct drm_mm_node `h]j)}(hjh]hstruct drm_mm_node}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjj drm_mm_nodeuh1hhjhKJhjubh (typically i915_vma.node)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKJhjubj})}(h\``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned h](j)}(h ``u64 size``h]j)}(hjh]hu64 size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKLhjubj)}(hhh]h)}(hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE alignedh]hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKLhjubj})}(h``u64 offset`` where to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address space h](j)}(h``u64 offset``h]j)}(hj!h]h u64 offset}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKOhjubj)}(hhh]h)}(hwhere to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address spaceh](hWwhere to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (}(hj:hhhNhNubjb)}(h **offset**h]hoffset}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj:ubh + }(hj:hhhNhNubjb)}(h**size**h]hsize}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jahj:ubh#) must fit within the address space}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKMhj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj6hKOhjubj})}(hv``unsigned long color`` color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE h](j)}(h``unsigned long color``h]j)}(hjh]hunsigned long color}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKQhjyubj)}(hhh]h)}(h]color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLEh]h]color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKPhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjhKQhjubj})}(h=``unsigned int flags`` control search and eviction behaviour h](j)}(h``unsigned int flags``h]j)}(hjh]hunsigned int flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKRhjubj)}(hhh]h)}(h%control search and eviction behaviourh]h%control search and eviction behaviour}(hjҘhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjΘhKRhjϘubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjΘhKRhjubeh}(h]h ]h"]h$]h&]uh1jwhjՖubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKThjՖubh)}(hXEi915_gem_gtt_reserve() tries to insert the **node** at the exact **offset** inside the address space (using **size** and **color**). If the **node** does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure.h](h+i915_gem_gtt_reserve() tries to insert the }(hj hhhNhNubjb)}(h**node**h]hnode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh at the exact }(hj hhhNhNubjb)}(h **offset**h]hoffset}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh! inside the address space (using }(hj hhhNhNubjb)}(h**size**h]hsize}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh and }(hj hhhNhNubjb)}(h **color**h]hcolor}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh ). If the }(hj hhhNhNubjb)}(h**node**h]hnode}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubhX does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKThjՖubh)}(h **Return**h]jb)}(hjuh]hReturn}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjsubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chK]hjՖubh)}(hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h]hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chK]hjՖubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjuhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_gtt_insert (C function)c.i915_gem_gtt_inserthNtauh1jhjuhhhNhNubj')}(hhh](j,)}(hint i915_gem_gtt_insert (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h]j2)}(hint i915_gem_gtt_insert(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKubji)}(h h]h }(hjəhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjșhKubjz)}(hi915_gem_gtt_inserth]j;)}(hi915_gem_gtt_inserth]hi915_gem_gtt_insert}(hjۙhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjיubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjșhKubj)}(h(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjݙsbc.i915_gem_gtt_insertasbuh1hhjubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hvmh]hvm}(hjPhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubji)}(h h]h }(hjvhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjeubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j1c.i915_gem_gtt_insertasbuh1hhjeubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjeubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj;)}(hwwh]hww}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjeubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_mm_node *nodeh](j)}(hjh]hstruct}(hjٚhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj՚ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj՚ubh)}(hhh]j;)}(h drm_mm_nodeh]h drm_mm_node}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j1c.i915_gem_gtt_insertasbuh1hhj՚ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj՚ubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj՚ubj;)}(hnodeh]hnode}(hj0hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj՚ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu64 sizeh](h)}(hhh]j;)}(hu64h]hu64}(hjLhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjNmodnameN classnameNjXj[)}j^]j1c.i915_gem_gtt_insertasbuh1hhjEubji)}(h h]h }(hjjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubj;)}(hsizeh]hsize}(hjxhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u64 alignmenth](h)}(hhh]j;)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j1c.i915_gem_gtt_insertasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h alignmenth]h alignment}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned long colorh](j)}(hunsignedh]hunsigned}(hjٛhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj՛ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj՛ubj)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj՛ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj՛ubj;)}(hcolorh]hcolor}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj՛ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u64 starth](h)}(hhh]j;)}(hu64h]hu64}(hj-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj*ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj/modnameN classnameNjXj[)}j^]j1c.i915_gem_gtt_insertasbuh1hhj&ubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj&ubj;)}(hstarth]hstart}(hjYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj&ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu64 endh](h)}(hhh]j;)}(hu64h]hu64}(hjuhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjrubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjwmodnameN classnameNjXj[)}j^]j1c.i915_gem_gtt_insertasbuh1hhjnubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnubj;)}(hendh]hend}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int flagsh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjȜhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hj֜hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hflagsh]hflags}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjșhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjșhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjșhKhjhhubj1)}(hhh]h)}(h)insert a node into an address_space (GTT)h]h)insert a node into an address_space (GTT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjșhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj4jSj4jTjUjVuh1j&hhhjuhNhNubjX)}(hX**Parameters** ``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) ``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned ``u64 alignment`` required alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENT ``unsigned long color`` color to apply to node ``u64 start`` start of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned ``u64 end`` end of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX ``unsigned int flags`` control search and eviction behaviour **Description** i915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to **alignment** and its **size** must then fit entirely within the [**start**, **end**] bounds. The nodes on either side of the hole must match **color**, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node's VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm. **Return** 0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h](h)}(h**Parameters**h]jb)}(hj>h]h Parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj<ubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj8ubjx)}(hhh](j})}(h_``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` h](j)}(h!``struct i915_address_space *vm``h]j)}(hj]h]hstruct i915_address_space *vm}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjWubj)}(hhh]h)}(h`h](hthe }(hjvhhhNhNubh)}(h8:c:type:`struct i915_address_space `h]j)}(hjh]hstruct i915_address_space}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype 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h](j)}(h``unsigned long color``h]j)}(hjh]hunsigned long color}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj)}(hhh]h)}(hcolor to apply to nodeh]hcolor to apply to node}(hjמhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjӞhKhjԞubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjӞhKhjTubj})}(hi``u64 start`` start of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned h](j)}(h ``u64 start``h]j)}(hjh]h u64 start}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj)}(hhh]h)}(hZstart of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE alignedh]hZstart of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hKhjTubj})}(hz``u64 end`` end of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX h](j)}(h ``u64 end``h]j)}(hj1h]hu64 end}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj+ubj)}(hhh]h)}(hmend of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAXh]hmend of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1j|hjFhKhjTubj})}(h=``unsigned int flags`` control search and eviction behaviour h](j)}(h``unsigned int flags``h]j)}(hjkh]hunsigned int flags}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjeubj)}(hhh]h)}(h%control search and eviction behaviourh]h%control search and eviction behaviour}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjTubeh}(h]h ]h"]h$]h&]uh1jwhj8ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj8ubh)}(hXi915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to **alignment** and its **size** must then fit entirely within the [**start**, **end**] bounds. The nodes on either side of the hole must match **color**, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node's VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm.h](h}i915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to }(hjhhhNhNubjb)}(h **alignment**h]h alignment}(hjğhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and its }(hjhhhNhNubjb)}(h**size**h]hsize}(hj֟hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh$ must then fit entirely within the [}(hjhhhNhNubjb)}(h **start**h]hstart}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh, }(hjhhhNhNubjb)}(h**end**h]hend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:] bounds. The nodes on either side of the hole must match }(hjhhhNhNubjb)}(h **color**h]hcolor}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubhX, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node’s VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj8ubh)}(h **Return**h]jb)}(hj'h]hReturn}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj%ubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj8ubh)}(hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h]hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjuhhhNhNubeh}(h]global-gtt-viewsah ]h"]global gtt viewsah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(hGTT Fences and Swizzlingh]hGTT Fences and Swizzling}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""i915_vma_revoke_fence (C function)c.i915_vma_revoke_fencehNtauh1jhj[hhhNhNubj')}(hhh](j,)}(h1void i915_vma_revoke_fence (struct i915_vma *vma)h]j2)}(h0void i915_vma_revoke_fence(struct i915_vma *vma)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM#ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM#ubjz)}(hi915_vma_revoke_fenceh]j;)}(hi915_vma_revoke_fenceh]hi915_vma_revoke_fence}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM#ubj)}(h(struct i915_vma *vma)h]j)}(hstruct i915_vma *vmah](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjϠhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjݠubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.i915_vma_revoke_fenceasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hvmah]hvma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM#ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj}hhhjhM#ubah}(h]jxah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM#hjzhhubj1)}(hhh]h)}(hforce-remove fence for a VMAh]hforce-remove fence for a VMA}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjBhhubah}(h]h ]h"]h$]h&]uh1j0hjzhhhjhM#ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj]jSj]jTjUjVuh1j&hhhj[hNhNubjX)}(h**Parameters** ``struct i915_vma *vma`` vma to map linearly (not through a fence reg) **Description** This function force-removes any fence from the given object, which is useful if the kernel wants to do untiled GTT access.h](h)}(h**Parameters**h]jb)}(hjgh]h Parameters}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jahjeubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM!hjaubjx)}(hhh]j})}(hG``struct i915_vma *vma`` vma to map linearly (not through a fence reg) h](j)}(h``struct i915_vma *vma``h]j)}(hjh]hstruct i915_vma *vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(h-vma to map linearly (not through a fence reg)h]h-vma to map linearly (not through a fence reg)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj}ubah}(h]h ]h"]h$]h&]uh1jwhjaubh)}(h**Description**h]jb)}(hjh]h Description}(hjáhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM hjaubh)}(hzThis function force-removes any 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](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct i915_vma *vma)h]j)}(hstruct i915_vma *vmah](j)}(hjh]hstruct}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubji)}(h h]h }(hjPhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?ubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj^ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjcmodnameN classnameNjXj[)}j^]ja)}jTj)sbc.i915_vma_pin_fenceasbuh1hhj?ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubj;)}(hvmah]hvma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj?ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj;ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hset up fencing for a vmah]hset up fencing for a vma}(hjƢhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjâhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjޢjSjޢjTjUjVuh1j&hhhj[hNhNubjX)}(hX)**Parameters** ``struct i915_vma *vma`` vma to map through a fence reg **Description** When mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for **obj**, stealing one if it can't find any. It then sets up the reg based on the object's properties: address, pitch and tiling format. For an untiled surface, this removes any existing fence. **Return** 0 on success, negative error code on failure.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubjx)}(hhh]j})}(h8``struct i915_vma *vma`` vma to map through a fence reg h](j)}(h``struct i915_vma *vma``h]j)}(hjh]hstruct i915_vma *vma}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(hvma to map through a fence regh]hvma to map through a fence reg}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjBh]h Description}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj@ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hWhen mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for **obj**, stealing one if it can't find any.h](hWhen mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for }(hjXhhhNhNubjb)}(h**obj**h]hobj}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXubh&, stealing one if it can’t find any.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(h[It then sets up the reg based on the object's properties: address, pitch and tiling format.h]h]It then sets up the reg based on the object’s properties: address, pitch and tiling format.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(h8For an untiled surface, this removes any existing fence.h]h8For an untiled surface, this removes any existing fence.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(h-0 on success, negative error code on failure.h]h-0 on success, negative error code on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj[hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_reserve_fence (C function)c.i915_reserve_fencehNtauh1jhj[hhhNhNubj')}(hhh](j,)}(hCstruct i915_fence_reg * i915_reserve_fence (struct i915_ggtt *ggtt)h]j2)}(hAstruct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt)h](j)}(hjh]hstruct}(hjޣhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjڣhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjڣhhhjhMubh)}(hhh]j;)}(hi915_fence_regh]hi915_fence_reg}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTi915_reserve_fencesbc.i915_reserve_fenceasbuh1hhjڣhhhjhMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjڣhhhjhMubj)}(hjh]h*}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjڣhhhjhMubjz)}(hi915_reserve_fenceh]j;)}(hjh]hi915_reserve_fence}(hj=hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj9ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjڣhhhjhMubj)}(h(struct i915_ggtt *ggtt)h]j)}(hstruct i915_ggtt *ggtth](j)}(hjh]hstruct}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubji)}(h h]h }(hjehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubh)}(hhh]j;)}(h i915_ggtth]h i915_ggtt}(hjvhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjxmodnameN classnameNjXj[)}j^]jc.i915_reserve_fenceasbuh1hhjTubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubj;)}(hggtth]hggtt}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjTubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjPubah}(h]h ]h"]h$]h&]jjuh1jhjڣhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj֣hhhjhMubah}(h]jѣah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjӣhhubj1)}(hhh]h)}(hReserve a fence for vGPUh]hReserve a fence for vGPU}(hj٤hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj֤hhubah}(h]h ]h"]h$]h&]uh1j0hjӣhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj[hNhNubjX)}(h**Parameters** ``struct i915_ggtt *ggtt`` Global GTT **Description** This function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubjx)}(hhh]j})}(h&``struct i915_ggtt *ggtt`` Global GTT h](j)}(h``struct i915_ggtt *ggtt``h]j)}(hjh]hstruct i915_ggtt *ggtt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(h Global GTTh]h Global GTT}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj/hMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjUh]h Description}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjSubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hThis function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.h]hThis function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj[hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!i915_unreserve_fence (C function)c.i915_unreserve_fencehNtauh1jhj[hhhNhNubj')}(hhh](j,)}(h8void i915_unreserve_fence (struct i915_fence_reg *fence)h]j2)}(h7void i915_unreserve_fence(struct i915_fence_reg *fence)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hi915_unreserve_fenceh]j;)}(hi915_unreserve_fenceh]hi915_unreserve_fence}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct i915_fence_reg *fence)h]j)}(hstruct i915_fence_reg *fenceh](j)}(hjh]hstruct}(hjץhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjӥubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjӥubh)}(hhh]j;)}(hi915_fence_regh]hi915_fence_reg}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.i915_unreserve_fenceasbuh1hhjӥubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjӥubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjӥubj;)}(hfenceh]hfence}(hj0hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjӥubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjϥubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hReclaim a reserved fenceh]hReclaim a reserved fence}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjWhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjrjSjrjTjUjVuh1j&hhhj[hNhNubjX)}(h**Parameters** ``struct i915_fence_reg *fence`` the fence reg **Description** This function add a reserved fence register from vGPU to the fence_list.h](h)}(h**Parameters**h]jb)}(hj|h]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjzubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjvubjx)}(hhh]j})}(h/``struct i915_fence_reg *fence`` the fence reg h](j)}(h ``struct i915_fence_reg *fence``h]j)}(hjh]hstruct i915_fence_reg *fence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(h the fence regh]h the fence reg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjvubh)}(h**Description**h]jb)}(hj֦h]h Description}(hjئhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjԦubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjvubh)}(hHThis function add a reserved fence register from vGPU to the fence_list.h]hHThis function add a reserved fence register from vGPU to the fence_list.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjvubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj[hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_ggtt_restore_fences (C function)c.intel_ggtt_restore_fenceshNtauh1jhj[hhhNhNubj')}(hhh](j,)}(h7void intel_ggtt_restore_fences (struct i915_ggtt *ggtt)h]j2)}(h6void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hj*hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj)hMubjz)}(hintel_ggtt_restore_fencesh]j;)}(hintel_ggtt_restore_fencesh]hintel_ggtt_restore_fences}(hj<hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj)hMubj)}(h(struct i915_ggtt *ggtt)h]j)}(hstruct i915_ggtt *ggtth](j)}(hjh]hstruct}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubji)}(h h]h }(hjehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubh)}(hhh]j;)}(h i915_ggtth]h i915_ggtt}(hjvhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjxmodnameN classnameNjXj[)}j^]ja)}jTj>sbc.intel_ggtt_restore_fencesasbuh1hhjTubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubj;)}(hggtth]hggtt}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjTubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjPubah}(h]h ]h"]h$]h&]jjuh1jhjhhhj)hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj)hMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj)hMhjhhubj1)}(hhh]h)}(hrestore fence stateh]hrestore fence state}(hjۧhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjاhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj)hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj[hNhNubjX)}(hX**Parameters** ``struct i915_ggtt *ggtt`` Global GTT **Description** Restore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubjx)}(hhh]j})}(h&``struct i915_ggtt *ggtt`` Global GTT h](j)}(h``struct i915_ggtt *ggtt``h]j)}(hjh]hstruct i915_ggtt *ggtt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(h Global GTTh]h Global GTT}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj1hMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjWh]h Description}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjUubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hRestore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.h]hRestore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj[hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!detect_bit_6_swizzle (C function)c.detect_bit_6_swizzlehNtauh1jhj[hhhNhNubj')}(hhh](j,)}(h2void detect_bit_6_swizzle (struct i915_ggtt *ggtt)h]j2)}(h1void detect_bit_6_swizzle(struct i915_ggtt *ggtt)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM<ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM<ubjz)}(hdetect_bit_6_swizzleh]j;)}(hdetect_bit_6_swizzleh]hdetect_bit_6_swizzle}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM<ubj)}(h(struct i915_ggtt *ggtt)h]j)}(hstruct i915_ggtt *ggtth](j)}(hjh]hstruct}(hj٨hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjըubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjըubh)}(hhh]j;)}(h i915_ggtth]h i915_ggtt}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.detect_bit_6_swizzleasbuh1hhjըubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjըubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjըubj;)}(hggtth]hggtt}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjըubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjѨubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM<ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM<ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM<hjhhubj1)}(hhh]h)}(hdetect bit 6 swizzling patternh]hdetect bit 6 swizzling pattern}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM6hjYhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM<ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjtjSjtjTjUjVuh1j&hhhj[hNhNubjX)}(h**Parameters** ``struct i915_ggtt *ggtt`` Global GGTT **Description** Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.h](h)}(h**Parameters**h]jb)}(hj~h]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj|ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM:hjxubjx)}(hhh]j})}(h'``struct i915_ggtt *ggtt`` Global GGTT h](j)}(h``struct i915_ggtt *ggtt``h]j)}(hjh]hstruct i915_ggtt *ggtt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM7hjubj)}(hhh]h)}(h Global GGTTh]h Global GGTT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM7hjubah}(h]h ]h"]h$]h&]uh1jwhjxubh)}(h**Description**h]jb)}(hjةh]h Description}(hjکhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj֩ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM9hjxubh)}(h`Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.h]h`Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM9hjxubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj[hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j".i915_gem_object_do_bit_17_swizzle (C function)#c.i915_gem_object_do_bit_17_swizzlehNtauh1jhj[hhhNhNubj')}(hhh](j,)}(h`void i915_gem_object_do_bit_17_swizzle (struct drm_i915_gem_object *obj, struct sg_table *pages)h]j2)}(h_void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM ubji)}(h h]h }(hj,hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj+hM ubjz)}(h!i915_gem_object_do_bit_17_swizzleh]j;)}(h!i915_gem_object_do_bit_17_swizzleh]h!i915_gem_object_do_bit_17_swizzle}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj:ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj+hM ubj)}(h9(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubji)}(h h]h }(hjghhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjxhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjuubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjzmodnameN classnameNjXj[)}j^]ja)}jTj@sb#c.i915_gem_object_do_bit_17_swizzleasbuh1hhjVubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubj;)}(hobjh]hobj}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjRubj)}(hstruct sg_table *pagesh](j)}(hjh]hstruct}(hj̪hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȪubji)}(h h]h }(hj٪hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjȪubh)}(hhh]j;)}(hsg_tableh]hsg_table}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j#c.i915_gem_object_do_bit_17_swizzleasbuh1hhjȪubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjȪubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȪubj;)}(hpagesh]hpages}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjȪubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjRubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj+hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj+hM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj+hM hjhhubj1)}(hhh]h)}(hfixup bit 17 swizzlingh]hfixup bit 17 swizzling}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjJhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj+hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjejSjejTjUjVuh1j&hhhj[hNhNubjX)}(hX**Parameters** ``struct drm_i915_gem_object *obj`` i915 GEM buffer object ``struct sg_table *pages`` the scattergather list of physical pages **Description** This function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle(). This is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).h](h)}(h**Parameters**h]jb)}(hjoh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjmubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjiubjx)}(hhh](j})}(h;``struct drm_i915_gem_object *obj`` i915 GEM buffer object h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hjh]hstruct drm_i915_gem_object *obj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(hi915 GEM buffer objecth]hi915 GEM buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hD``struct sg_table *pages`` the scattergather list of physical pages h](j)}(h``struct sg_table *pages``h]j)}(hjǫh]hstruct sg_table *pages}(hjɫhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjūubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(h(the scattergather list of physical pagesh]h(the scattergather list of physical pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjܫhMhjݫubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjܫhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjiubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjiubh)}(hThis function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle().h]hThis function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjiubh)}(hThis is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).h]hThis is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjiubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj[hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"0i915_gem_object_save_bit_17_swizzle (C function)%c.i915_gem_object_save_bit_17_swizzlehNtauh1jhj[hhhNhNubj')}(hhh](j,)}(hbvoid i915_gem_object_save_bit_17_swizzle (struct drm_i915_gem_object *obj, struct sg_table *pages)h]j2)}(havoid i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j)}(hvoidh]hvoid}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM*ubji)}(h h]h }(hjehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRhhhjdhM*ubjz)}(h#i915_gem_object_save_bit_17_swizzleh]j;)}(h#i915_gem_object_save_bit_17_swizzleh]h#i915_gem_object_save_bit_17_swizzle}(hjwhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjRhhhjdhM*ubj)}(h9(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjysb%c.i915_gem_object_save_bit_17_swizzleasbuh1hhjubji)}(h h]h }(hjѬhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj߬hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hobjh]hobj}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct sg_table *pagesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hsg_tableh]hsg_table}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj%modnameN classnameNjXj[)}j^]jͬ%c.i915_gem_object_save_bit_17_swizzleasbuh1hhjubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hpagesh]hpages}(hj\hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjRhhhjdhM*ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjNhhhjdhM*ubah}(h]jIah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjdhM*hjKhhubj1)}(hhh]h)}(hsave bit 17 swizzlingh]hsave bit 17 swizzling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM"hjhhubah}(h]h ]h"]h$]h&]uh1j0hjKhhhjdhM*ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj[hNhNubjX)}(hXs**Parameters** ``struct drm_i915_gem_object *obj`` i915 GEM buffer object ``struct sg_table *pages`` the scattergather list of physical pages **Description** This function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hjubjx)}(hhh](j})}(h;``struct drm_i915_gem_object *obj`` i915 GEM buffer object h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hjǭh]hstruct drm_i915_gem_object *obj}(hjɭhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjŭubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM#hjubj)}(hhh]h)}(hi915 GEM buffer objecth]hi915 GEM buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjܭhM#hjݭubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjܭhM#hjubj})}(hD``struct sg_table *pages`` the scattergather list of physical pages h](j)}(h``struct sg_table *pages``h]j)}(hjh]hstruct sg_table *pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM$hjubj)}(hhh]h)}(h(the scattergather list of physical pagesh]h(the scattergather list of physical pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM$hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj;h]h Description}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj9ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hjubh)}(hThis function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.h]hThis function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj[hhhNhNubh)}(hhh](h)}(hGlobal GTT Fence Handlingh]hGlobal GTT Fence Handling}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghhhhhMubh)}(hImportant to avoid confusions: "fences" in the i915 driver are not execution fences used to track command completion but hardware detiler objects which wrap a given range of the global GTT. Each platform has only a fairly limited set of these objects.h]hImportant to avoid confusions: “fences” in the i915 driver are not execution fences used to track command completion but hardware detiler objects which wrap a given range of the global GTT. Each platform has only a fairly limited set of these objects.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chKhjghhubh)}(hXFences are used to detile GTT memory mappings. They're also connected to the hardware frontbuffer render tracking and hence interact with frontbuffer compression. Furthermore on older platforms fences are required for tiled objects used by the display engine. They can also be used by the render engine - they're required for blitter commands and are optional for render commands. But on gen4+ both display (with the exception of fbc) and rendering have their own tiling state bits and don't need fences.h]hXFences are used to detile GTT memory mappings. They’re also connected to the hardware frontbuffer render tracking and hence interact with frontbuffer compression. Furthermore on older platforms fences are required for tiled objects used by the display engine. They can also be used by the render engine - they’re required for blitter commands and are optional for render commands. But on gen4+ both display (with the exception of fbc) and rendering have their own tiling state bits and don’t need fences.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chKhjghhubh)}(hAlso note that fences only support X and Y tiling and hence can't be used for the fancier new tiling formats like W, Ys and Yf.h]hAlso note that fences only support X and Y tiling and hence can’t be used for the fancier new tiling formats like W, Ys and Yf.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chKhjghhubh)}(hXFinally note that because fences are such a restricted resource they're dynamically associated with objects. Furthermore fence state is committed to the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must explicitly call i915_gem_object_get_fence() to synchronize fencing status for cpu access. Also note that some code wants an unfenced view, for those cases the fence can be removed forcefully with i915_gem_object_put_fence().h]hXFinally note that because fences are such a restricted resource they’re dynamically associated with objects. Furthermore fence state is committed to the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must explicitly call i915_gem_object_get_fence() to synchronize fencing status for cpu access. Also note that some code wants an unfenced view, for those cases the fence can be removed forcefully with i915_gem_object_put_fence().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chK"hjghhubh)}(hInternally these functions will synchronize with userspace access by removing CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.h]hInternally these functions will synchronize with userspace access by removing CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chK)hjghhubeh}(h]global-gtt-fence-handlingah ]h"]global gtt fence handlingah$]h&]uh1hhj[hhhhhMubh)}(hhh](h)}(h%Hardware Tiling and Swizzling Detailsh]h%Hardware Tiling and Swizzling Details}(hjήhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjˮhhhhhMubh)}(hThe idea behind tiling is to increase cache hit rates by rearranging pixel data so that a group of pixel accesses are in the same cacheline. Performance improvement from doing this on the back/depth buffer are on the order of 30%.h]hThe idea behind tiling is to increase cache hit rates by rearranging pixel data so that a group of pixel accesses are in the same cacheline. Performance improvement from doing this on the back/depth buffer are on the order of 30%.}(hjܮhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjˮhhubh)}(hXMIntel architectures make this somewhat more complicated, though, by adjustments made to addressing of data when the memory is in interleaved mode (matched pairs of DIMMS) to improve memory bandwidth. For interleaved memory, the CPU sends every sequential 64 bytes to an alternate memory channel so it can get the bandwidth from both.h]hXMIntel architectures make this somewhat more complicated, though, by adjustments made to addressing of data when the memory is in interleaved mode (matched pairs of DIMMS) to improve memory bandwidth. For interleaved memory, the CPU sends every sequential 64 bytes to an alternate memory channel so it can get the bandwidth from both.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM hjˮhhubh)}(hXThe GPU also rearranges its accesses for increased bandwidth to interleaved memory, and it matches what the CPU does for non-tiled. However, when tiled it does it a little differently, since one walks addresses not just in the X direction but also Y. So, along with alternating channels when bit 6 of the address flips, it also alternates when other bits flip -- Bits 9 (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) are common to both the 915 and 965-class hardware.h]hXThe GPU also rearranges its accesses for increased bandwidth to interleaved memory, and it matches what the CPU does for non-tiled. However, when tiled it does it a little differently, since one walks addresses not just in the X direction but also Y. So, along with alternating channels when bit 6 of the address flips, it also alternates when other bits flip -- Bits 9 (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) are common to both the 915 and 965-class hardware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjˮhhubh)}(hX*The CPU also sometimes XORs in higher bits as well, to improve bandwidth doing strided access like we do so frequently in graphics. This is called "Channel XOR Randomization" in the MCH documentation. The result is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address decode.h]hX.The CPU also sometimes XORs in higher bits as well, to improve bandwidth doing strided access like we do so frequently in graphics. This is called “Channel XOR Randomization” in the MCH documentation. The result is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address decode.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjˮhhubh)}(hAll of this bit 6 XORing has an effect on our memory management, as we need to make sure that the 3d driver can correctly address object contents.h]hAll of this bit 6 XORing has an effect on our memory management, as we need to make sure that the 3d driver can correctly address object contents.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjˮhhubh)}(hUIf we don't have interleaved memory, all tiling is safe and no swizzling is required.h]hWIf we don’t have interleaved memory, all tiling is safe and no swizzling is required.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM#hjˮhhubh)}(hWhen bit 17 is XORed in, we simply refuse to tile at all. Bit 17 is not just a page offset, so as we page an object out and back in, individual pages in it will have different bit 17 addresses, resulting in each 64 bytes being swapped with its neighbor!h]hWhen bit 17 is XORed in, we simply refuse to tile at all. Bit 17 is not just a page offset, so as we page an object out and back in, individual pages in it will have different bit 17 addresses, resulting in each 64 bytes being swapped with its neighbor!}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hjˮhhubh)}(hXOtherwise, if interleaved, we have to tell the 3d driver what the address swizzling it needs to do is, since it's writing with the CPU to the pages (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order to match what the GPU expects.h]hXOtherwise, if interleaved, we have to tell the 3d driver what the address swizzling it needs to do is, since it’s writing with the CPU to the pages (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order to match what the GPU expects.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM+hjˮhhubeh}(h]%hardware-tiling-and-swizzling-detailsah ]h"]%hardware tiling and swizzling detailsah$]h&]uh1hhj[hhhhhMubeh}(h]gtt-fences-and-swizzlingah ]h"]gtt fences and swizzlingah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(hObject Tiling IOCTLsh]hObject Tiling IOCTLs}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_fence_size (C function)c.i915_gem_fence_sizehNtauh1jhjdhhhNhNubj')}(hhh](j,)}(hku32 i915_gem_fence_size (struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h]j2)}(hju32 i915_gem_fence_size(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTi915_gem_fence_sizesbc.i915_gem_fence_sizeasbuh1hhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK7ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhK7ubjz)}(hi915_gem_fence_sizeh]j;)}(hjh]hi915_gem_fence_size}(hjůhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhK7ubj)}(hS(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjܯubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjܯubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.i915_gem_fence_sizeasbuh1hhjܯubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjܯubj)}(hjh]h*}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjܯubj;)}(hi915h]hi915}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjܯubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjدubj)}(hu32 sizeh](h)}(hhh]j;)}(hu32h]hu32}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjPubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjUmodnameN classnameNjXj[)}j^]jc.i915_gem_fence_sizeasbuh1hhjLubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjLubj;)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjLubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjدubj)}(hunsigned int tilingh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj°hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(htilingh]htiling}(hjаhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjدubj)}(hunsigned int strideh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hstrideh]hstride}(hj!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjدubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhK7ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhK7ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhK7hjhhubj1)}(hhh]h)}(h$required global GTT size for a fenceh]h$required global GTT size for a fence}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK.hjHhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhK7ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjcjSjcjTjUjVuh1j&hhhjdhNhNubjX)}(hX=**Parameters** ``struct drm_i915_private *i915`` i915 device ``u32 size`` object size ``unsigned int tiling`` tiling mode ``unsigned int stride`` tiling stride **Description** Return the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.h](h)}(h**Parameters**h]jb)}(hjmh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jahjkubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK2hjgubjx)}(hhh](j})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjh]hstruct drm_i915_private *i915}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK/hjubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK/hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK/hjubj})}(h``u32 size`` object size h](j)}(h ``u32 size``h]j)}(hjűh]hu32 size}(hjDZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjñubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK0hjubj)}(hhh]h)}(h object sizeh]h object size}(hjޱhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjڱhK0hj۱ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjڱhK0hjubj})}(h$``unsigned int tiling`` tiling mode h](j)}(h``unsigned int tiling``h]j)}(hjh]hunsigned int tiling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK1hjubj)}(hhh]h)}(h tiling modeh]h tiling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK1hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK1hjubj})}(h&``unsigned int stride`` tiling stride h](j)}(h``unsigned int stride``h]j)}(hj7h]hunsigned int stride}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK2hj1ubj)}(hhh]h)}(h tiling strideh]h tiling stride}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhK2hjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1j|hjLhK2hjubeh}(h]h ]h"]h$]h&]uh1jwhjgubh)}(h**Description**h]jb)}(hjrh]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjpubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK4hjgubh)}(hReturn the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.h]hReturn the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK4hjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjdhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%i915_gem_fence_alignment (C function)c.i915_gem_fence_alignmenthNtauh1jhjdhhhNhNubj')}(hhh](j,)}(hpu32 i915_gem_fence_alignment (struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h]j2)}(hou32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTi915_gem_fence_alignmentsbc.i915_gem_fence_alignmentasbuh1hhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK_ubji)}(h h]h }(hjܲhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj۲hK_ubjz)}(hi915_gem_fence_alignmenth]j;)}(hjزh]hi915_gem_fence_alignment}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj۲hK_ubj)}(hS(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj'hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj)modnameN classnameNjXj[)}j^]jֲc.i915_gem_fence_alignmentasbuh1hhjubji)}(h h]h }(hjEhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hi915h]hi915}(hj`hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu32 sizeh](h)}(hhh]j;)}(hu32h]hu32}(hj|hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjyubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj~modnameN classnameNjXj[)}j^]jֲc.i915_gem_fence_alignmentasbuh1hhjuubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuubj;)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjuubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int tilingh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjϳhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hjݳhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(htilingh]htiling}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int strideh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj<hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hstrideh]hstride}(hjJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj۲hK_ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj۲hK_ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj۲hK_hjhhubj1)}(hhh]h)}(h)required global GTT alignment for a fenceh]h)required global GTT alignment for a fence}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKVhjqhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj۲hK_ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjdhNhNubjX)}(hXD**Parameters** ``struct drm_i915_private *i915`` i915 device ``u32 size`` object size ``unsigned int tiling`` tiling mode ``unsigned int stride`` tiling stride **Description** Return the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKZhjubjx)}(hhh](j})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjh]hstruct drm_i915_private *i915}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKWhjubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hjδhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjʴhKWhj˴ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjʴhKWhjubj})}(h``u32 size`` object size h](j)}(h ``u32 size``h]j)}(hjh]hu32 size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKXhjubj)}(hhh]h)}(h object sizeh]h object size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKXhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKXhjubj})}(h$``unsigned int tiling`` tiling mode h](j)}(h``unsigned int tiling``h]j)}(hj'h]hunsigned int tiling}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKYhj!ubj)}(hhh]h)}(h tiling modeh]h tiling mode}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hKYhj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j|hj<hKYhjubj})}(h&``unsigned int stride`` tiling stride h](j)}(h``unsigned int stride``h]j)}(hj`h]hunsigned int stride}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKZhjZubj)}(hhh]h)}(h tiling strideh]h tiling stride}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhKZhjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1j|hjuhKZhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK\hjubh)}(hReturn the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.h]hReturn the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK\hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjdhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&i915_gem_set_tiling_ioctl (C function)c.i915_gem_set_tiling_ioctlhNtauh1jhjdhhhNhNubj')}(hhh](j,)}(hYint i915_gem_set_tiling_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j2)}(hXint i915_gem_set_tiling_ioctl(struct drm_device *dev, void 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]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h void *datah](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_file *fileh](j)}(hjh]hstruct}(hjѶhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjͶubji)}(h h]h }(hj޶hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjͶubh)}(hhh]j;)}(hdrm_fileh]hdrm_file}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jWc.i915_gem_set_tiling_ioctlasbuh1hhjͶubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjͶubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjͶubj;)}(hfileh]hfile}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjͶubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjܵhhhjhMVubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjصhhhjhMVubah}(h]jӵah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMVhjյhhubj1)}(hhh]h)}(h IOCTL handler to set tiling modeh]h IOCTL handler to set tiling mode}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMIhjOhhubah}(h]h ]h"]h$]h&]uh1j0hjյhhhjhMVubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjjSjjjTjUjVuh1j&hhhjdhNhNubjX)}(hXp**Parameters** ``struct drm_device *dev`` DRM device ``void *data`` data pointer for the ioctl ``struct drm_file *file`` DRM file for the ioctl call **Description** Sets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object. Called by the user via ioctl. **Return** Zero on success, negative errno on failure.h](h)}(h**Parameters**h]jb)}(hjth]h Parameters}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjrubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMMhjnubjx)}(hhh](j})}(h&``struct drm_device *dev`` DRM device h](j)}(h``struct drm_device *dev``h]j)}(hjh]hstruct drm_device *dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMJhjubj)}(hhh]h)}(h DRM deviceh]h DRM device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMJhjubj})}(h*``void *data`` data pointer for the ioctl h](j)}(h``void *data``h]j)}(hj̷h]h void *data}(hjηhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjʷubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMKhjƷubj)}(hhh]h)}(hdata pointer for the ioctlh]hdata pointer for the ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMKhjubah}(h]h ]h"]h$]h&]uh1jhjƷubeh}(h]h ]h"]h$]h&]uh1j|hjhMKhjubj})}(h6``struct drm_file *file`` DRM file for the ioctl call h](j)}(h``struct drm_file *file``h]j)}(hjh]hstruct drm_file *file}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMLhjubj)}(hhh]h)}(hDRM file for the ioctl callh]hDRM file for the ioctl call}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMLhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMLhjubeh}(h]h ]h"]h$]h&]uh1jwhjnubh)}(h**Description**h]jb)}(hj@h]h Description}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj>ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMNhjnubh)}(hhSets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object.h]hhSets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMNhjnubh)}(hCalled by the user via ioctl.h]hCalled by the user via ioctl.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMQhjnubh)}(h **Return**h]jb)}(hjvh]hReturn}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMShjnubh)}(h+Zero on success, negative errno on failure.h]h+Zero on success, negative errno on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMShjnubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjdhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&i915_gem_get_tiling_ioctl (C function)c.i915_gem_get_tiling_ioctlhNtauh1jhjdhhhNhNubj')}(hhh](j,)}(hYint i915_gem_get_tiling_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j2)}(hXint i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *file)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMubji)}(h h]h }(hjʸhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjɸhMubjz)}(hi915_gem_get_tiling_ioctlh]j;)}(hi915_gem_get_tiling_ioctlh]hi915_gem_get_tiling_ioctl}(hjܸhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjظubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjɸhMubj)}(h;(struct drm_device *dev, void *data, struct drm_file *file)h](j)}(hstruct drm_device *devh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h drm_deviceh]h drm_device}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTj޸sbc.i915_gem_get_tiling_ioctlasbuh1hhjubji)}(h h]h }(hj6hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdevh]hdev}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h void *datah](j)}(hvoidh]hvoid}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubji)}(h h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubj;)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_file *fileh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hdrm_fileh]hdrm_file}(hjʹhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjǹubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj̹modnameN classnameNjXj[)}j^]j2c.i915_gem_get_tiling_ioctlasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hfileh]hfile}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjɸhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjɸhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjɸhMhjhhubj1)}(hhh]h)}(h IOCTL handler to get tiling modeh]h IOCTL handler to get tiling mode}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhj*hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjɸhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjEjSjEjTjUjVuh1j&hhhjdhNhNubjX)}(hXT**Parameters** ``struct drm_device *dev`` DRM device ``void *data`` data pointer for the ioctl ``struct drm_file *file`` DRM file for the ioctl call **Description** Returns the current tiling mode and required bit 6 swizzling for the object. Called by the user via ioctl. **Return** Zero on success, negative errno on failure.h](h)}(h**Parameters**h]jb)}(hjOh]h Parameters}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjMubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjIubjx)}(hhh](j})}(h&``struct drm_device *dev`` DRM device h](j)}(h``struct drm_device *dev``h]j)}(hjnh]hstruct drm_device *dev}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjhubj)}(hhh]h)}(h DRM deviceh]h DRM device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjeubj})}(h*``void *data`` data pointer for the ioctl h](j)}(h``void *data``h]j)}(hjh]h void *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjubj)}(hhh]h)}(hdata pointer for the ioctlh]hdata pointer for the ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjeubj})}(h6``struct drm_file *file`` DRM file for the ioctl call h](j)}(h``struct drm_file *file``h]j)}(hjh]hstruct drm_file *file}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj޺ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjںubj)}(hhh]h)}(hDRM file for the ioctl callh]hDRM file for the ioctl call}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjںubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjeubeh}(h]h ]h"]h$]h&]uh1jwhjIubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjIubh)}(hLReturns the current tiling mode and required bit 6 swizzling for the object.h]hLReturns the current tiling mode and required bit 6 swizzling for the object.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjIubh)}(hCalled by the user via ioctl.h]hCalled by the user via ioctl.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjIubh)}(h **Return**h]jb)}(hjQh]hReturn}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jahjOubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjIubh)}(h+Zero on success, negative errno on failure.h]h+Zero on success, negative errno on failure.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjIubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjdhhhNhNubh)}(h~i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace interface to declare fence register requirements.h]h~i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace interface to declare fence register requirements.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjdhhubh)}(hIn principle GEM doesn't care at all about the internal data layout of an object, and hence it also doesn't care about tiling or swizzling. There's two exceptions:h]hIn principle GEM doesn’t care at all about the internal data layout of an object, and hence it also doesn’t care about tiling or swizzling. There’s two exceptions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjdhhubj:)}(hhh](j:)}(hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there's only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.h]h)}(hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there's only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.h]hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there’s only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely. h]h)}(hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely.h]hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjdhhubh)}(hSince neither of this applies for new tiling layouts on modern platforms like W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. Anything else can be handled in userspace entirely without the kernel's involvement.h]hSince neither of this applies for new tiling layouts on modern platforms like W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. Anything else can be handled in userspace entirely without the kernel’s involvement.}(hjֻhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK%hjdhhubeh}(h]object-tiling-ioctlsah ]h"]object tiling ioctlsah$]h&]uh1hhj NhhhhhMubh)}(hhh](h)}(hProtected Objectsh]hProtected Objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hPXP (Protected Xe Path) is a feature available in Gen12 and newer platforms. It allows execution and flip to display of protected (i.e. encrypted) objects. The SW support is enabled via the CONFIG_DRM_I915_PXP kconfig.h]hPXP (Protected Xe Path) is a feature available in Gen12 and newer platforms. It allows execution and flip to display of protected (i.e. encrypted) objects. The SW support is enabled via the CONFIG_DRM_I915_PXP kconfig.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:486: ./drivers/gpu/drm/i915/pxp/intel_pxp.chKhjhhubh)}(hXRObjects can opt-in to PXP encryption at creation time via the I915_GEM_CREATE_EXT_PROTECTED_CONTENT create_ext flag. For objects to be correctly protected they must be used in conjunction with a context created with the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. See the documentation of those two uapi flags for details and restrictions.h]hXRObjects can opt-in to PXP encryption at creation time via the I915_GEM_CREATE_EXT_PROTECTED_CONTENT create_ext flag. For objects to be correctly protected they must be used in conjunction with a context created with the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. See the documentation of those two uapi flags for details and restrictions.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:486: ./drivers/gpu/drm/i915/pxp/intel_pxp.chKhjhhubh)}(hXHProtected objects are tied to a pxp session; currently we only support one session, which i915 manages and whose index is available in the uapi (I915_PROTECTED_CONTENT_DEFAULT_SESSION) for use in instructions targeting protected objects. The session is invalidated by the HW when certain events occur (e.g. suspend/resume). When this happens, all the objects that were used with the session are marked as invalid and all contexts marked as using protected content are banned. Any further attempt at using them in an execbuf call is rejected, while flips are converted to black frames.h]hXHProtected objects are tied to a pxp session; currently we only support one session, which i915 manages and whose index is available in the uapi (I915_PROTECTED_CONTENT_DEFAULT_SESSION) for use in instructions targeting protected objects. The session is invalidated by the HW when certain events occur (e.g. suspend/resume). When this happens, all the objects that were used with the session are marked as invalid and all contexts marked as using protected content are banned. Any further attempt at using them in an execbuf call is rejected, while flips are converted to black frames.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:486: ./drivers/gpu/drm/i915/pxp/intel_pxp.chK!hjhhubh)}(hSome of the PXP setup operations are performed by the Management Engine, which is handled by the mei driver; communication between i915 and mei is performed via the mei_pxp component module.h]hSome of the PXP setup operations are performed by the Management Engine, which is handled by the mei driver; communication between i915 and mei is performed via the mei_pxp component module.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:486: ./drivers/gpu/drm/i915/pxp/intel_pxp.chK+hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_pxp (C struct) c.intel_pxphNtauh1jhjhhhNhNubj')}(hhh](j,)}(h intel_pxph]j2)}(hstruct intel_pxph](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjOhhhj`hKubjz)}(h intel_pxph]j;)}(hjMh]h intel_pxp}(hjshhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjoubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjOhhhj`hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjKhhhj`hKubah}(h]jFah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj`hKhjHhhubj1)}(hhh]h)}(h pxp stateh]h pxp state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjHhhhj`hKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX **Definition**:: struct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); }; **Members** ``ctrl_gt`` pointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform) ``platform_cfg_is_bad`` used to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called. ``kcr_base`` base mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile. ``gsccs_res`` resources for request submission for platforms that have a GSC engine. ``pxp_component`` i915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`. ``dev_link`` Enforce module relationship for power management ordering. ``pxp_component_added`` track if the pxp component has been added. Set and cleared in tee init and fini functions respectively. ``ce`` kernel-owned context used for PXP operations ``arb_mutex`` protects arb session start ``arb_is_valid`` tracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW. ``key_instance`` tracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one. ``tee_mutex`` protects the tee channel binding and messaging. ``stream_cmd`` LMEM obj used to send stream PXP commands to the GSC ``hw_state_invalidated`` if the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required. ``irq_enabled`` tracks the status of the kcr irqs ``termination`` tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`. ``session_work`` worker that manages session events. ``session_events`` pending session events, protected with gt->irq_lock.h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj")}(hXstruct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); };h]hXstruct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); };}hjҼsbah}(h]h ]h"]h$]h&]jjuh1j"hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubh)}(h **Members**h]jb)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK=hjubjx)}(hhh](j})}(h``ctrl_gt`` pointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform) h](j)}(h ``ctrl_gt``h]j)}(hjh]hctrl_gt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(hpointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform)h]hpointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hXf``platform_cfg_is_bad`` used to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called. h](j)}(h``platform_cfg_is_bad``h]j)}(hj<h]hplatform_cfg_is_bad}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK#hj6ubj)}(hhh]h)}(hXMused to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called.h]hXMused to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjRubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1j|hjQhK#hjubj})}(h``kcr_base`` base mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile. h](j)}(h ``kcr_base``h]j)}(hjvh]hkcr_base}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK)hjpubj)}(hhh]h)}(hbase mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile.h]hbase mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK(hjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1j|hjhK)hjubj})}(hU``gsccs_res`` resources for request submission for platforms that have a GSC engine. h](j)}(h ``gsccs_res``h]j)}(hjh]h gsccs_res}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK.hjubj)}(hhh]h)}(hFresources for request submission for platforms that have a GSC engine.h]hFresources for request submission for platforms that have a GSC engine.}(hjɽhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjŽhK.hjƽubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjŽhK.hjubj})}(h``pxp_component`` i915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`. h](j)}(h``pxp_component``h]j)}(hjh]h pxp_component}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK>hjubj)}(hhh]h)}(hi915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`.h](hi915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by }(hjhhhNhNubh)}(h:c:type:`tee_mutex`h]j)}(hj h]h tee_mutex}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjj tee_mutexuh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj})}(hH``dev_link`` Enforce module relationship for power management ordering. h](j)}(h ``dev_link``h]j)}(hjFh]hdev_link}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKChj@ubj)}(hhh]h)}(h:Enforce module relationship for power management ordering.h]h:Enforce module relationship for power management ordering.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hKChj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1j|hj[hKChjubj})}(h``pxp_component_added`` track if the pxp component has been added. Set and cleared in tee init and fini functions respectively. h](j)}(h``pxp_component_added``h]j)}(hjh]hpxp_component_added}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKHhjyubj)}(hhh]h)}(hgtrack if the pxp component has been added. Set and cleared in tee init and fini functions respectively.h]hgtrack if the pxp component has been added. Set and cleared in tee init and fini functions respectively.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKGhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjhKHhjubj})}(h4``ce`` kernel-owned context used for PXP operations h](j)}(h``ce``h]j)}(hjh]hce}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(h,kernel-owned context used for PXP operationsh]h,kernel-owned context used for PXP operations}(hjҾhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjξhKhjϾubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjξhKhjubj})}(h)``arb_mutex`` protects arb session start h](j)}(h ``arb_mutex``h]j)}(hjh]h arb_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(hprotects arb session starth]hprotects arb session start}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``arb_is_valid`` tracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW. h](j)}(h``arb_is_valid``h]j)}(hj+h]h arb_is_valid}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKUhj%ubj)}(hhh]h)}(htracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW.h]htracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can’t rely on the HW state of the session to know if it’s valid and need to track the status in SW.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKRhjAubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1j|hj@hKUhjubj})}(h``key_instance`` tracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one. h](j)}(h``key_instance``h]j)}(hjeh]h key_instance}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK\hj_ubj)}(hhh]h)}(htracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one.h]htracks which key instance we’re on, so we can use it to determine if an object was created using the current key or a previous one.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKZhj{ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hjzhK\hjubj})}(h>``tee_mutex`` protects the tee channel binding and messaging. h](j)}(h ``tee_mutex``h]j)}(hjh]h tee_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(h/protects the tee channel binding and messaging.h]h/protects the tee channel binding and messaging.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hD``stream_cmd`` LMEM obj used to send stream PXP commands to the GSC h](j)}(h``stream_cmd``h]j)}(hjؿh]h stream_cmd}(hjڿhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjֿubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjҿubj)}(hhh]h)}(h4LMEM obj used to send stream PXP commands to the GSCh]h4LMEM obj used to send stream PXP commands to the GSC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjҿubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``hw_state_invalidated`` if the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required. h](j)}(h``hw_state_invalidated``h]j)}(hjh]hhw_state_invalidated}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKmhj ubj)}(hhh]h)}(hif the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required.h]hif the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKjhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj&hKmhjubj})}(h2``irq_enabled`` tracks the status of the kcr irqs h](j)}(h``irq_enabled``h]j)}(hjKh]h irq_enabled}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjEubj)}(hhh]h)}(h!tracks the status of the kcr irqsh]h!tracks the status of the kcr irqs}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hKhjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1j|hj`hKhjubj})}(h``termination`` tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`. h](j)}(h``termination``h]j)}(hjh]h termination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKuhj~ubj)}(hhh]h)}(h{tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`.h](hdtracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in }(hjhhhNhNubh)}(h:c:type:`session_work`h]j)}(hjh]h session_work}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjj session_workuh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKthjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKthjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1j|hjhKuhjubj})}(h5``session_work`` worker that manages session events. h](j)}(h``session_work``h]j)}(hjh]h session_work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(h#worker that manages session events.h]h#worker that manages session events.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hG``session_events`` pending session events, protected with gt->irq_lock.h](j)}(h``session_events``h]j)}(hjh]hsession_events}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(h4pending session events, protected with gt->irq_lock.h]h4pending session events, protected with gt->irq_lock.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj/hKhjubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]protected-objectsah ]h"]protected objectsah$]h&]uh1hhj NhhhhhMubeh}(h](memory-management-and-command-submissionah ]h"](memory management and command submissionah$]h&]uh1hhhhhhhhM ubh)}(hhh](h)}(hMicrocontrollersh]hMicrocontrollers}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubh)}(hXyStarting from gen9, three microcontrollers are available on the HW: the graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the display microcontroller (DMC). The driver is responsible for loading the firmwares on the microcontrollers; the GuC and HuC firmwares are transferred to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.h]hXyStarting from gen9, three microcontrollers are available on the HW: the graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the display microcontroller (DMC). The driver is responsible for loading the firmwares on the microcontrollers; the GuC and HuC firmwares are transferred to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjkhhubh)}(hhh](h)}(hWOPCMh]hWOPCM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h WOPCM Layouth]h WOPCM Layout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hThe layout of the WOPCM will be fixed after writing to GuC WOPCM size and offset registers whose values are calculated and determined by HuC/GuC firmware size and set of hardware requirements/restrictions as shown below:h]hThe layout of the WOPCM will be fixed after writing to GuC WOPCM size and offset registers whose values are calculated and determined by HuC/GuC firmware size and set of hardware requirements/restrictions as shown below:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:506: ./drivers/gpu/drm/i915/gt/intel_wopcm.chK hjhhubj")}(hX +=========> +====================+ <== WOPCM Top ^ | HW contexts RSVD | | +===> +====================+ <== GuC WOPCM Top | ^ | | | | | | | | | | | GuC | | | WOPCM | | | Size +--------------------+ WOPCM | | GuC FW RSVD | | | +--------------------+ | | | GuC Stack RSVD | | | +------------------- + | v | GuC WOPCM RSVD | | +===> +====================+ <== GuC WOPCM base | | WOPCM RSVD | | +------------------- + <== HuC Firmware Top v | HuC FW | +=========> +====================+ <== WOPCM Baseh]hX +=========> +====================+ <== WOPCM Top ^ | HW contexts RSVD | | +===> +====================+ <== GuC WOPCM Top | ^ | | | | | | | | | | | GuC | | | WOPCM | | | Size +--------------------+ WOPCM | | GuC FW RSVD | | | +--------------------+ | | | GuC Stack RSVD | | | +------------------- + | v | GuC WOPCM RSVD | | +===> +====================+ <== GuC WOPCM base | | WOPCM RSVD | | +------------------- + <== HuC Firmware Top v | HuC FW | +=========> +====================+ <== WOPCM Base}hjsbah}(h]h ]h"]h$]h&]jjuh1j"h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:506: ./drivers/gpu/drm/i915/gt/intel_wopcm.chKhjhhubh)}(hGuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 context).h]hGuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 context).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:506: ./drivers/gpu/drm/i915/gt/intel_wopcm.chK$hjhhubeh}(h] wopcm-layoutah ]h"] wopcm layoutah$]h&]uh1hhjhhhhhMubeh}(h]wopcmah ]h"]wopcmah$]h&]uh1hhjkhhhhhMubh)}(hhh](h)}(hGuCh]hGuC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hThe GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is designed to offload some of the functionality usually performed by the host driver; currently the main operations it can take care of are:h]hThe GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is designed to offload some of the functionality usually performed by the host driver; currently the main operations it can take care of are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhjhhubj:)}(hhh](j:)}(hGAuthentication of the HuC, which is required to fully enable HuC usage.h]h)}(hjh]hGAuthentication of the HuC, which is required to fully enable HuC usage.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhj ubah}(h]h ]h"]h$]h&]uh1j:hj ubj:)}(h@Low latency graphics context scheduling (a.k.a. GuC submission).h]h)}(hj&h]h@Low latency graphics context scheduling (a.k.a. GuC submission).}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhj$ubah}(h]h ]h"]h$]h&]uh1j:hj ubj:)}(hGT Power management. h]h)}(hGT Power management.h]hGT Power management.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhj<ubah}(h]h ]h"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjhhubh)}(hThe enable_guc module parameter can be used to select which of those operations to enable within GuC. Note that not all the operations are supported on all gen9+ platforms.h]hThe enable_guc module parameter can be used to select which of those operations to enable within GuC. Note that not all the operations are supported on all gen9+ platforms.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhjhhubh)}(hX Enabling the GuC is not mandatory and therefore the firmware is only loaded if at least one of the operations is selected. However, not loading the GuC might result in the loss of some features that do require the GuC (currently just the HuC, but more are expected to land in the future).h]hX Enabling the GuC is not mandatory and therefore the firmware is only loaded if at least one of the operations is selected. However, not loading the GuC might result in the loss of some features that do require the GuC (currently just the HuC, but more are expected to land in the future).}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chK"hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_guc (C struct) c.intel_guchNtauh1jhjhhhNhNubj')}(hhh](j,)}(h intel_guch]j2)}(hstruct intel_guch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(h intel_guch]j;)}(hjh]h intel_guc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(hTop level structure of GuC.h]hTop level structure of GuC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX **Definition**:: struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; }; **Members** ``fw`` the GuC firmware ``log`` sub-structure containing GuC log related data and objects ``ct`` the command transport communication channel ``slpc`` sub-structure containing SLPC related data and objects ``capture`` the error-state-capture module's data and objects ``dbgfs_node`` debugfs node ``sched_engine`` Global engine used to submit requests to GuC ``stalled_request`` if GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed. ``submission_stall_reason`` reason why submission is stalled ``irq_lock`` protects GuC irq state ``msg_enabled_mask`` mask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message. ``outstanding_submission_g2h`` number of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle ``tlb_lookup`` xarray to store all pending TLB invalidation requests ``serial_slot`` id to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter. ``next_seqno`` the next id (sequence number) to allocate. ``interrupts`` pointers to GuC interrupt-managing functions. ``submission_state`` sub-structure for submission state protected by single lock ``submission_state.lock`` protects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero ``submission_state.guc_ids`` used to allocate new guc_ids, single-lrc ``submission_state.num_guc_ids`` Number of guc_ids, selftest feature to be able to reduce this number while testing. ``submission_state.guc_ids_bitmap`` used to allocate new guc_ids, multi-lrc ``submission_state.guc_id_list`` list of intel_context with valid guc_ids but no refs ``submission_state.guc_ids_in_use`` Number single-lrc guc_ids in use ``submission_state.destroyed_contexts`` list of contexts waiting to be destroyed (deregistered with the GuC) ``submission_state.destroyed_worker`` worker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping) ``submission_state.reset_fail_worker`` worker to trigger a GT reset after an engine reset fails ``submission_state.reset_fail_mask`` mask of engines that failed to reset ``submission_state.sched_disable_delay_ms`` schedule disable delay, in ms, for contexts ``submission_state.sched_disable_gucid_threshold`` threshold of min remaining available guc_ids before we start bypassing the schedule disable delay ``submission_supported`` tracks whether we support GuC submission on the current platform ``submission_selected`` tracks whether the user enabled GuC submission ``submission_initialized`` tracks whether GuC submission has been initialised ``submission_version`` Submission API version of the currently loaded firmware ``rc_supported`` tracks whether we support GuC rc on the current platform ``rc_selected`` tracks whether the user enabled GuC rc ``ads_vma`` object allocated to hold the GuC ADS ``ads_map`` contents of the GuC ADS ``ads_regset_size`` size of the save/restore regsets in the ADS ``ads_regset_count`` number of save/restore registers in the ADS for each engine ``ads_regset`` save/restore regsets in the ADS ``ads_golden_ctxt_size`` size of the golden contexts in the ADS ``ads_waklv_size`` size of workaround KLVs ``ads_capture_size`` size of register lists in the ADS used for error capture ``lrc_desc_pool_v69`` object allocated to hold the GuC LRC descriptor pool ``lrc_desc_pool_vaddr_v69`` contents of the GuC LRC descriptor pool ``context_lookup`` used to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC ``params`` Control params for fw initialization ``send_regs`` GuC's FW specific registers used for sending MMIO H2G ``notify_reg`` register used to send interrupts to the GuC FW ``mmio_msg`` notification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up. ``send_mutex`` used to serialize the intel_guc_send actions ``timestamp`` GT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker. ``timestamp.lock`` Lock protecting the below fields and the engine stats. ``timestamp.gt_stamp`` 64-bit extended value of the GT timestamp. ``timestamp.ping_delay`` Period for polling the GT timestamp for overflow. ``timestamp.work`` Periodic work to adjust GT timestamp, engine and context usage for overflows. ``timestamp.shift`` Right shift value for the gpm timestamp ``timestamp.last_stat_jiffies`` jiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required. ``dead_guc_worker`` Asynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker. ``last_dead_guc_jiffies`` timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC. ``number_guc_id_stolen`` The number of guc_ids that have been stolen ``fast_response_selftest`` Backdoor to CT handler for fast response selftesth](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK hjubj")}(hX struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; };h]hX struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j"h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK"hjubh)}(h **Members**h]jb)}(hj"h]hMembers}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKuhjubjx)}(hhh](j})}(h``fw`` the GuC firmware h](j)}(h``fw``h]j)}(hjAh]hfw}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK"hj;ubj)}(hhh]h)}(hthe GuC firmwareh]hthe GuC firmware}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhK"hjWubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j|hjVhK"hj8ubj})}(hB``log`` sub-structure containing GuC log related data and objects h](j)}(h``log``h]j)}(hjzh]hlog}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjtubj)}(hhh]h)}(h9sub-structure containing GuC log related data and objectsh]h9sub-structure containing GuC log related data and objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h3``ct`` the command transport communication channel h](j)}(h``ct``h]j)}(hjh]hct}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h+the command transport communication channelh]h+the command transport communication channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h@``slpc`` sub-structure containing SLPC related data and objects h](j)}(h``slpc``h]j)}(hjh]hslpc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h6sub-structure containing SLPC related data and objectsh]h6sub-structure containing SLPC related data and objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h>``capture`` the error-state-capture module's data and objects h](j)}(h ``capture``h]j)}(hj%h]hcapture}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h1the error-state-capture module's data and objectsh]h3the error-state-capture module’s data and objects}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj;ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj:hKhj8ubj})}(h``dbgfs_node`` debugfs node h](j)}(h``dbgfs_node``h]j)}(hj^h]h dbgfs_node}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjXubj)}(hhh]h)}(h debugfs nodeh]h debugfs node}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshKhjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1j|hjshKhj8ubj})}(h>``sched_engine`` Global engine used to submit requests to GuC h](j)}(h``sched_engine``h]j)}(hjh]h sched_engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h,Global engine used to submit requests to GuCh]h,Global engine used to submit requests to GuC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h``stalled_request`` if GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed. h](j)}(h``stalled_request``h]j)}(hjh]hstalled_request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK6hjubj)}(hhh]h)}(hif GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed.h]hif GuC can’t process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK4hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK6hj8ubj})}(h=``submission_stall_reason`` reason why submission is stalled h](j)}(h``submission_stall_reason``h]j)}(hj h]hsubmission_stall_reason}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK:hjubj)}(hhh]h)}(h reason why submission is stalledh]h reason why submission is stalled}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK:hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK:hj8ubj})}(h$``irq_lock`` protects GuC irq state h](j)}(h ``irq_lock``h]j)}(hjCh]hirq_lock}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj=ubj)}(hhh]h)}(hprotects GuC irq stateh]hprotects GuC irq state}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhKhjYubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1j|hjXhKhj8ubj})}(ho``msg_enabled_mask`` mask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message. h](j)}(h``msg_enabled_mask``h]j)}(hj|h]hmsg_enabled_mask}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKHhjvubj)}(hhh]h)}(hYmask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message.h]hYmask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKGhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1j|hjhKHhj8ubj})}(h``outstanding_submission_g2h`` number of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle h](j)}(h``outstanding_submission_g2h``h]j)}(hjh]houtstanding_submission_g2h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKOhjubj)}(hhh]h)}(hjnumber of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idleh]hjnumber of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKOhj8ubj})}(hE``tlb_lookup`` xarray to store all pending TLB invalidation requests h](j)}(h``tlb_lookup``h]j)}(hjh]h tlb_lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h5xarray to store all pending TLB invalidation requestsh]h5xarray to store all pending TLB invalidation requests}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hw``serial_slot`` id to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter. h](j)}(h``serial_slot``h]j)}(hj)h]h serial_slot}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKXhj#ubj)}(hhh]h)}(hfid to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter.h]hfid to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKWhj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1j|hj>hKXhj8ubj})}(h:``next_seqno`` the next id (sequence number) to allocate. h](j)}(h``next_seqno``h]j)}(hjch]h next_seqno}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj]ubj)}(hhh]h)}(h*the next id (sequence number) to allocate.h]h*the next id (sequence number) to allocate.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhKhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1j|hjxhKhj8ubj})}(h=``interrupts`` pointers to GuC interrupt-managing functions. h](j)}(h``interrupts``h]j)}(hjh]h interrupts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h-pointers to GuC interrupt-managing functions.h]h-pointers to GuC interrupt-managing functions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hQ``submission_state`` sub-structure for submission state protected by single lock h](j)}(h``submission_state``h]j)}(hjh]hsubmission_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKihjubj)}(hhh]h)}(h;sub-structure for submission state protected by single lockh]h;sub-structure for submission state protected by single lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKihj8ubj})}(h``submission_state.lock`` protects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero h](j)}(h``submission_state.lock``h]j)}(hjh]hsubmission_state.lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKohj ubj)}(hhh]h)}(hpprotects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zeroh]hpprotects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKmhj%ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj$hKohj8ubj})}(hF``submission_state.guc_ids`` used to allocate new guc_ids, single-lrc h](j)}(h``submission_state.guc_ids``h]j)}(hjIh]hsubmission_state.guc_ids}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKthjCubj)}(hhh]h)}(h(used to allocate new guc_ids, single-lrch]h(used to allocate new guc_ids, single-lrc}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKshj_ubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1j|hj^hKthj8ubj})}(hu``submission_state.num_guc_ids`` Number of guc_ids, selftest feature to be able to reduce this number while testing. h](j)}(h ``submission_state.num_guc_ids``h]j)}(hjh]hsubmission_state.num_guc_ids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKyhj}ubj)}(hhh]h)}(hSNumber of guc_ids, selftest feature to be able to reduce this number while testing.h]hSNumber of guc_ids, selftest feature to be able to reduce this number while testing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKxhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j|hjhKyhj8ubj})}(hL``submission_state.guc_ids_bitmap`` used to allocate new guc_ids, multi-lrc h](j)}(h#``submission_state.guc_ids_bitmap``h]j)}(hjh]hsubmission_state.guc_ids_bitmap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK~hjubj)}(hhh]h)}(h'used to allocate new guc_ids, multi-lrch]h'used to allocate new guc_ids, multi-lrc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK~hj8ubj})}(hV``submission_state.guc_id_list`` list of intel_context with valid guc_ids but no refs h](j)}(h ``submission_state.guc_id_list``h]j)}(hjh]hsubmission_state.guc_id_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h4list of intel_context with valid guc_ids but no refsh]h4list of intel_context with valid guc_ids but no refs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hKhj8ubj})}(hE``submission_state.guc_ids_in_use`` Number single-lrc guc_ids in use h](j)}(h#``submission_state.guc_ids_in_use``h]j)}(hj1h]hsubmission_state.guc_ids_in_use}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj+ubj)}(hhh]h)}(h Number single-lrc guc_ids in useh]h Number single-lrc guc_ids in use}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1j|hjFhKhj8ubj})}(hm``submission_state.destroyed_contexts`` list of contexts waiting to be destroyed (deregistered with the GuC) h](j)}(h'``submission_state.destroyed_contexts``h]j)}(hjkh]h#submission_state.destroyed_contexts}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjeubj)}(hhh]h)}(hDlist of contexts waiting to be destroyed (deregistered with the GuC)h]hDlist of contexts waiting to be destroyed (deregistered with the GuC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h``submission_state.destroyed_worker`` worker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping) h](j)}(h%``submission_state.destroyed_worker``h]j)}(hjh]h!submission_state.destroyed_worker}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hworker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping)h]hworker to deregister contexts, need as we need to take a GT PM reference and can’t from destroy function as it might be in an atomic context (no sleeping)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h```submission_state.reset_fail_worker`` worker to trigger a GT reset after an engine reset fails h](j)}(h&``submission_state.reset_fail_worker``h]j)}(hjh]h"submission_state.reset_fail_worker}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h8worker to trigger a GT reset after an engine reset failsh]h8worker to trigger a GT reset after an engine reset fails}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hJ``submission_state.reset_fail_mask`` mask of engines that failed to reset h](j)}(h$``submission_state.reset_fail_mask``h]j)}(hjh]h submission_state.reset_fail_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h$mask of engines that failed to reseth]h$mask of engines that failed to reset}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj.hKhj8ubj})}(hX``submission_state.sched_disable_delay_ms`` schedule disable delay, in ms, for contexts h](j)}(h+``submission_state.sched_disable_delay_ms``h]j)}(hjSh]h'submission_state.sched_disable_delay_ms}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjMubj)}(hhh]h)}(h+schedule disable delay, in ms, for contextsh]h+schedule disable delay, in ms, for contexts}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j|hjhhKhj8ubj})}(h``submission_state.sched_disable_gucid_threshold`` threshold of min remaining available guc_ids before we start bypassing the schedule disable delay h](j)}(h2``submission_state.sched_disable_gucid_threshold``h]j)}(hjh]h.submission_state.sched_disable_gucid_threshold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hathreshold of min remaining available guc_ids before we start bypassing the schedule disable delayh]hathreshold of min remaining available guc_ids before we start bypassing the schedule disable delay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hZ``submission_supported`` tracks whether we support GuC submission on the current platform h](j)}(h``submission_supported``h]j)}(hjh]hsubmission_supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h@tracks whether we support GuC submission on the current platformh]h@tracks whether we support GuC submission on the current platform}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hG``submission_selected`` tracks whether the user enabled GuC submission h](j)}(h``submission_selected``h]j)}(hjh]hsubmission_selected}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h.tracks whether the user enabled GuC submissionh]h.tracks whether the user enabled GuC submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hN``submission_initialized`` tracks whether GuC submission has been initialised h](j)}(h``submission_initialized``h]j)}(hj:h]hsubmission_initialized}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj4ubj)}(hhh]h)}(h2tracks whether GuC submission has been initialisedh]h2tracks whether GuC submission has been initialised}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhKhjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1j|hjOhKhj8ubj})}(hO``submission_version`` Submission API version of the currently loaded firmware h](j)}(h``submission_version``h]j)}(hjsh]hsubmission_version}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjmubj)}(hhh]h)}(h7Submission API version of the currently loaded firmwareh]h7Submission API version of the currently loaded firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hJ``rc_supported`` tracks whether we support GuC rc on the current platform h](j)}(h``rc_supported``h]j)}(hjh]h rc_supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h8tracks whether we support GuC rc on the current platformh]h8tracks whether we support GuC rc on the current platform}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h7``rc_selected`` tracks whether the user enabled GuC rc h](j)}(h``rc_selected``h]j)}(hjh]h rc_selected}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h&tracks whether the user enabled GuC rch]h&tracks whether the user enabled GuC rc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h1``ads_vma`` object allocated to hold the GuC ADS h](j)}(h ``ads_vma``h]j)}(hjh]hads_vma}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h$object allocated to hold the GuC ADSh]h$object allocated to hold the GuC ADS}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hKhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj3hKhj8ubj})}(h$``ads_map`` contents of the GuC ADS h](j)}(h ``ads_map``h]j)}(hjWh]hads_map}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjQubj)}(hhh]h)}(hcontents of the GuC ADSh]hcontents of the GuC ADS}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhKhjmubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1j|hjlhKhj8ubj})}(h@``ads_regset_size`` size of the save/restore regsets in the ADS h](j)}(h``ads_regset_size``h]j)}(hjh]hads_regset_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h+size of the save/restore regsets in the ADSh]h+size of the save/restore regsets in the ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hQ``ads_regset_count`` number of save/restore registers in the ADS for each engine h](j)}(h``ads_regset_count``h]j)}(hjh]hads_regset_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h;number of save/restore registers in the ADS for each engineh]h;number of save/restore registers in the ADS for each engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h/``ads_regset`` save/restore regsets in the ADS h](j)}(h``ads_regset``h]j)}(hjh]h ads_regset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hsave/restore regsets in the ADSh]hsave/restore regsets in the ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h@``ads_golden_ctxt_size`` size of the golden contexts in the ADS h](j)}(h``ads_golden_ctxt_size``h]j)}(hj<h]hads_golden_ctxt_size}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj6ubj)}(hhh]h)}(h&size of the golden contexts in the ADSh]h&size of the golden contexts in the ADS}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhKhjRubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1j|hjQhKhj8ubj})}(h+``ads_waklv_size`` size of workaround KLVs h](j)}(h``ads_waklv_size``h]j)}(hjuh]hads_waklv_size}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjoubj)}(hhh]h)}(hsize of workaround KLVsh]hsize of workaround KLVs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hN``ads_capture_size`` size of register lists in the ADS used for error capture h](j)}(h``ads_capture_size``h]j)}(hjh]hads_capture_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h8size of register lists in the ADS used for error captureh]h8size of register lists in the ADS used for error capture}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hK``lrc_desc_pool_v69`` object allocated to hold the GuC LRC descriptor pool h](j)}(h``lrc_desc_pool_v69``h]j)}(hjh]hlrc_desc_pool_v69}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h4object allocated to hold the GuC LRC descriptor poolh]h4object allocated to hold the GuC LRC descriptor pool}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hD``lrc_desc_pool_vaddr_v69`` contents of the GuC LRC descriptor pool h](j)}(h``lrc_desc_pool_vaddr_v69``h]j)}(hj h]hlrc_desc_pool_vaddr_v69}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h'contents of the GuC LRC descriptor poolh]h'contents of the GuC LRC descriptor pool}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hKhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj5hKhj8ubj})}(h``context_lookup`` used to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC h](j)}(h``context_lookup``h]j)}(hjYh]hcontext_lookup}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjSubj)}(hhh]h)}(hrused to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuCh]hrused to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1j|hjnhKhj8ubj})}(h0``params`` Control params for fw initialization h](j)}(h ``params``h]j)}(hjh]hparams}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h$Control params for fw initializationh]h$Control params for fw initialization}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hD``send_regs`` GuC's FW specific registers used for sending MMIO H2G h](j)}(h ``send_regs``h]j)}(hjh]h send_regs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h5GuC's FW specific registers used for sending MMIO H2Gh]h7GuC’s FW specific registers used for sending MMIO H2G}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h>``notify_reg`` register used to send interrupts to the GuC FW h](j)}(h``notify_reg``h]j)}(hjh]h notify_reg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h.register used to send interrupts to the GuC FWh]h.register used to send interrupts to the GuC FW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(h``mmio_msg`` notification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up. h](j)}(h ``mmio_msg``h]j)}(hj>h]hmmio_msg}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj8ubj)}(hhh]h)}(hnotification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up.h]hnotification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1j|hjShKhj8ubj})}(h<``send_mutex`` used to serialize the intel_guc_send actions h](j)}(h``send_mutex``h]j)}(hjxh]h send_mutex}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjrubj)}(hhh]h)}(h,used to serialize the intel_guc_send actionsh]h,used to serialize the intel_guc_send actions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hr``timestamp`` GT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker. h](j)}(h ``timestamp``h]j)}(hjh]h timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hcGT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker.h]hcGT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hJ``timestamp.lock`` Lock protecting the below fields and the engine stats. h](j)}(h``timestamp.lock``h]j)}(hjh]htimestamp.lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h6Lock protecting the below fields and the engine stats.h]h6Lock protecting the below fields and the engine stats.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj8ubj})}(hB``timestamp.gt_stamp`` 64-bit extended value of the GT timestamp. h](j)}(h``timestamp.gt_stamp``h]j)}(hj%h]htimestamp.gt_stamp}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(h*64-bit extended value of the GT timestamp.h]h*64-bit extended value of the GT timestamp.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj;ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj:hMhj8ubj})}(hK``timestamp.ping_delay`` Period for polling the GT timestamp for overflow. h](j)}(h``timestamp.ping_delay``h]j)}(hj_h]htimestamp.ping_delay}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM hjYubj)}(hhh]h)}(h1Period for polling the GT timestamp for overflow.h]h1Period for polling the GT timestamp for overflow.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM hjuubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1j|hjthM hj8ubj})}(ha``timestamp.work`` Periodic work to adjust GT timestamp, engine and context usage for overflows. h](j)}(h``timestamp.work``h]j)}(hjh]htimestamp.work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(hMPeriodic work to adjust GT timestamp, engine and context usage for overflows.h]hMPeriodic work to adjust GT timestamp, engine and context usage for overflows.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj8ubj})}(h<``timestamp.shift`` Right shift value for the gpm timestamp h](j)}(h``timestamp.shift``h]j)}(hjh]htimestamp.shift}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(h'Right shift value for the gpm timestamph]h'Right shift value for the gpm timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj8ubj})}(h``timestamp.last_stat_jiffies`` jiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required. h](j)}(h``timestamp.last_stat_jiffies``h]j)}(hj h]htimestamp.last_stat_jiffies}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(hjiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required.h]hjiffies at last actual stats collection time. We use this timestamp to ensure we don’t oversample the stats because runtime power management events can trigger stats collection at much higher rates than required.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj!hMhj8ubj})}(hX ``dead_guc_worker`` Asynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker. h](j)}(h``dead_guc_worker``h]j)}(hjFh]hdead_guc_worker}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM'hj@ubj)}(hhh]h)}(hAsynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker.h]hAsynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM$hj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1j|hj[hM'hj8ubj})}(h``last_dead_guc_jiffies`` timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC. h](j)}(h``last_dead_guc_jiffies``h]j)}(hjh]hlast_dead_guc_jiffies}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM-hjzubj)}(hhh]h)}(h~timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC.h]htimestamp of previous ‘dead guc’ occurrence used to prevent a fundamentally broken system from continuously reloading the GuC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM+hjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1j|hjhM-hj8ubj})}(hE``number_guc_id_stolen`` The number of guc_ids that have been stolen h](j)}(h``number_guc_id_stolen``h]j)}(hjh]hnumber_guc_id_stolen}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM3hjubj)}(hhh]h)}(h+The number of guc_ids that have been stolenh]h+The number of guc_ids that have been stolen}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM3hj8ubj})}(hL``fast_response_selftest`` Backdoor to CT handler for fast response selftesth](j)}(h``fast_response_selftest``h]j)}(hjh]hfast_response_selftest}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM6hjubj)}(hhh]h)}(h1Backdoor to CT handler for fast response selftesth]h1Backdoor to CT handler for fast response selftest}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM7hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM6hj8ubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubh)}(h**Description**h]jb)}(hj6h]h Description}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj4ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM:hjhhubh)}(hhIt handles firmware loading and manages client pool. intel_guc owns an i915_sched_engine for submission.h]hhIt handles firmware loading and manages client pool. intel_guc owns an i915_sched_engine for submission.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_guc_ggtt_offset (C function)c.intel_guc_ggtt_offsethNtauh1jhjhhhNhNubj')}(hhh](j,)}(hGu32 intel_guc_ggtt_offset (struct intel_guc *guc, struct i915_vma *vma)h]j2)}(hFu32 intel_guc_ggtt_offset(struct intel_guc *guc, struct i915_vma *vma)h](h)}(hhh]j;)}(hu32h]hu32}(hjwhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjtubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjymodnameN classnameNjXj[)}j^]ja)}jTintel_guc_ggtt_offsetsbc.intel_guc_ggtt_offsetasbuh1hhjphhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjphhhjhMubjz)}(hintel_guc_ggtt_offseth]j;)}(hjh]hintel_guc_ggtt_offset}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjphhhjhMubj)}(h-(struct intel_guc *guc, struct i915_vma *vma)h](j)}(hstruct intel_guc *guch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_guch]h intel_guc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_guc_ggtt_offsetasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hguch]hguc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct i915_vma *vmah](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2ubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjVmodnameN classnameNjXj[)}j^]jc.intel_guc_ggtt_offsetasbuh1hhj2ubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj;)}(hvmah]hvma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjphhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjlhhhjhMubah}(h]jgah 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Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. **Return** GGTT offset of the **vma**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubjx)}(hhh](j})}(h/``struct intel_guc *guc`` intel_guc structure. h](j)}(h``struct intel_guc *guc``h]j)}(hjh]hstruct intel_guc *guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(hintel_guc structure.h]hintel_guc structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(h<``struct i915_vma *vma`` i915 graphics virtual memory area. h](j)}(h``struct i915_vma *vma``h]j)}(hj?h]hstruct i915_vma *vma}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj9ubj)}(hhh]h)}(h"i915 graphics virtual memory area.h]h"i915 graphics virtual memory area.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThMhjUubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j|hjThMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjzh]h Description}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjxubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubh)}(hX[GuC does not allow any gfx GGTT address that falls into range [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.h]hX[GuC does not allow any gfx GGTT address that falls into range [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubh)}(hGGTT offset of the **vma**.h](hGGTT offset of the }(hjhhhNhNubjb)}(h**vma**h]hvma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubh)}(hhh](h)}(hGuC Firmware Layouth]hGuC Firmware Layout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h-The GuC/HuC firmware layout looks like this::h]h,The GuC/HuC firmware layout looks like this:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK hjhhubj")}(hX+======================================================================+ | Firmware blob | +===============+===============+============+============+============+ | CSS header | uCode | RSA key | modulus | exponent | +===============+===============+============+============+============+ <-header size-> <---header size continued -----------> <--- size -----------------------------------------------------------> <-key size-> <-mod size-> <-exp size->h]hX+======================================================================+ | Firmware blob | +===============+===============+============+============+============+ | CSS header | uCode | RSA key | modulus | exponent | +===============+===============+============+============+============+ <-header size-> <---header size continued -----------> <--- size -----------------------------------------------------------> <-key size-> <-mod size-> <-exp size->}hjsbah}(h]h ]h"]h$]h&]jjuh1j"hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhKhjhhubh)}(hXbThe firmware may or may not have modulus key and exponent data. The header, uCode and RSA signature are must-have components that will be used by driver. Length of each components, which is all in dwords, can be found in header. In the case that modulus and exponent are not present in fw, a.k.a truncated image, the length value still appears in header.h]hXbThe firmware may or may not have modulus key and exponent data. The header, uCode and RSA signature are must-have components that will be used by driver. Length of each components, which is all in dwords, can be found in header. In the case that modulus and exponent are not present in fw, a.k.a truncated image, the length value still appears in header.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhKhjhhubh)}(hJDriver will do some basic fw size validation based on the following rules:h]hJDriver will do some basic fw size validation based on the following rules:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK hjhhubj:)}(hhh](j:)}(h/Header, uCode and RSA are must-have components.h]h)}(hj1h]h/Header, uCode and RSA are must-have components.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK"hj/ubah}(h]h ]h"]h$]h&]uh1j:hj,ubj:)}(hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.h]h)}(hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.h]hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK#hjGubah}(h]h ]h"]h$]h&]uh1j:hj,ubj:)}(h@Length info of each component can be found in header, in dwords.h]h)}(hjbh]h@Length info of each component can be found in header, in dwords.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK%hj`ubah}(h]h ]h"]h$]h&]uh1j:hj,ubj:)}(hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case. h]h)}(hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case.h]hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK&hjxubah}(h]h ]h"]h$]h&]uh1j:hj,ubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhNubh)}(hXStarting from DG2, the HuC is loaded by the GSC instead of i915. The GSC firmware performs all the required integrity checks, we just need to check the version. Note that the header for GSC-managed blobs is different from the CSS used for dma-loaded firmwares.h]hXStarting from DG2, the HuC is loaded by the GSC instead of i915. The GSC firmware performs all the required integrity checks, we just need to check the version. Note that the header for GSC-managed blobs is different from the CSS used for dma-loaded firmwares.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK)hjhhubeh}(h]guc-firmware-layoutah ]h"]guc firmware layoutah$]h&]uh1hhjhhhhhMj<Kubh)}(hhh](h)}(hGuC Memory Managementh]hGuC Memory Management}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubh)}(hXGuC can't allocate any memory for its own usage, so all the allocations must be handled by the host driver. GuC accesses the memory via the GGTT, with the exception of the top and bottom parts of the 4GB address space, which are instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM) or other parts of the HW. The driver must take care not to place objects that the GuC is going to access in these reserved ranges. The layout of the GuC address space is shown below:h]hXGuC can’t allocate any memory for its own usage, so all the allocations must be handled by the host driver. GuC accesses the memory via the GGTT, with the exception of the top and bottom parts of the 4GB address space, which are instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM) or other parts of the HW. The driver must take care not to place objects that the GuC is going to access in these reserved ranges. The layout of the GuC address space is shown below:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:526: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjhhubj")}(hX +===========> +====================+ <== FFFF_FFFF ^ | Reserved | | +====================+ <== GUC_GGTT_TOP | | | | | DRAM | GuC | | Address +===> +====================+ <== GuC ggtt_pin_bias Space ^ | | | | | | | GuC | GuC | | WOPCM | WOPCM | | Size | | | | | | v v | | +=======+===> +====================+ <== 0000_0000h]hX +===========> +====================+ <== FFFF_FFFF ^ | Reserved | | +====================+ <== GUC_GGTT_TOP | | | | | DRAM | GuC | | Address +===> +====================+ <== GuC ggtt_pin_bias Space ^ | | | | | | | GuC | GuC | | WOPCM | WOPCM | | Size | | | | | | v v | | +=======+===> +====================+ <== 0000_0000}hjsbah}(h]h ]h"]h$]h&]jjuh1j"h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:526: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjhhubh)}(hThe lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.h]hThe lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:526: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_guc_allocate_vma (C function)c.intel_guc_allocate_vmahNtauh1jhjhhhNhNubj')}(hhh](j,)}(hJstruct i915_vma * intel_guc_allocate_vma (struct intel_guc *guc, u32 size)h]j2)}(hHstruct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj'modnameN classnameNjXj[)}j^]ja)}jTintel_guc_allocate_vmasbc.intel_guc_allocate_vmaasbuh1hhjhhhjhMubji)}(h h]h }(hjFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubj)}(hjh]h*}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubjz)}(hintel_guc_allocate_vmah]j;)}(hjCh]hintel_guc_allocate_vma}(hjehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjaubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h!(struct intel_guc *guc, u32 size)h](j)}(hstruct intel_guc *guch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|ubh)}(hhh]j;)}(h intel_guch]h intel_guc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jAc.intel_guc_allocate_vmaasbuh1hhj|ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubj;)}(hguch]hguc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxubj)}(hu32 sizeh](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jAc.intel_guc_allocate_vmaasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjxubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h!Allocate a GGTT VMA for GuC usageh]h!Allocate a GGTT VMA for GuC usage}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjFhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjajSjajTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_guc *guc`` the guc ``u32 size`` size of area to allocate (both virtual space and memory) **Description** This is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC. **Return** A i915_vma if successful, otherwise an ERR_PTR.h](h)}(h**Parameters**h]jb)}(hjkh]h Parameters}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjiubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjeubjx)}(hhh](j})}(h"``struct intel_guc *guc`` the guc h](j)}(h``struct intel_guc *guc``h]j)}(hjh]hstruct intel_guc *guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubj)}(hhh]h)}(hthe guch]hthe guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hF``u32 size`` size of area to allocate (both virtual space and memory) h](j)}(h ``u32 size``h]j)}(hjh]hu32 size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubj)}(hhh]h)}(h8size of area to allocate (both virtual space and memory)h]h8size of area to allocate (both virtual space and memory)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjeubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjeubh)}(hXHThis is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC.h]hXHThis is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjeubh)}(h **Return**h]jb)}(hj%h]hReturn}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjeubh)}(h/A i915_vma if successful, otherwise an ERR_PTR.h]h/A i915_vma if successful, otherwise an ERR_PTR.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjeubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]guc-memory-managementah ]h"]guc memory managementah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(hGuC-specific firmware loaderh]hGuC-specific firmware loader}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_guc_fw_upload (C function)c.intel_guc_fw_uploadhNtauh1jhjYhhhNhNubj')}(hhh](j,)}(h/int intel_guc_fw_upload (struct intel_guc *guc)h]j2)}(h.int intel_guc_fw_upload(struct intel_guc *guc)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_guc_fw_uploadh]j;)}(hintel_guc_fw_uploadh]hintel_guc_fw_upload}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct intel_guc *guc)h]j)}(hstruct intel_guc *guch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_guch]h intel_guc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_guc_fw_uploadasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hguch]hguc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj{hhhjhMubah}(h]jvah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjxhhubj1)}(hhh]h)}(hload GuC uCode to deviceh]hload GuC uCode to device}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhj@hhubah}(h]h ]h"]h$]h&]uh1j0hjxhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj[jSj[jTjUjVuh1j&hhhjYhNhNubjX)}(hX_**Parameters** ``struct intel_guc *guc`` intel_guc structure **Description** Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset. The firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w. **Return** non-zero code on errorh](h)}(h**Parameters**h]jb)}(hjeh]h Parameters}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjcubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhj_ubjx)}(hhh]j})}(h.``struct intel_guc *guc`` intel_guc structure h](j)}(h``struct intel_guc *guc``h]j)}(hjh]hstruct intel_guc *guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhj~ubj)}(hhh]h)}(hintel_guc structureh]hintel_guc structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj{ubah}(h]h ]h"]h$]h&]uh1jwhj_ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhj_ubh)}(h[Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset.h]h[Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhj_ubh)}(hThe firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w.h]hThe firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhj_ubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhj_ubh)}(hnon-zero code on errorh]hnon-zero code on error}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjYhhhNhNubeh}(h]guc-specific-firmware-loaderah ]h"]guc-specific firmware loaderah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hGuC-based command submissionh]hGuC-based command submission}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhMubh)}(hXThe Scratch registers: There are 16 MMIO-based registers start from 0xC180. The kernel driver writes a value to the action register (SOFT_SCRATCH_0) along with any data. It then triggers an interrupt on the GuC via another register write (0xC4C8). Firmware writes a success/fail code back to the action register after processes the request. The kernel driver polls waiting for this update and then proceeds.h]hXThe Scratch registers: There are 16 MMIO-based registers start from 0xC180. The kernel driver writes a value to the action register (SOFT_SCRATCH_0) along with any data. It then triggers an interrupt on the GuC via another register write (0xC4C8). Firmware writes a success/fail code back to the action register after processes the request. The kernel driver polls waiting for this update and then proceeds.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK'hj)hhubh)}(hCommand Transport buffers (CTBs): Covered in detail in other sections but CTBs (Host to GuC - H2G, GuC to Host - G2H) are a message interface between the i915 and GuC.h]hCommand Transport buffers (CTBs): Covered in detail in other sections but CTBs (Host to GuC - H2G, GuC to Host - G2H) are a message interface between the i915 and GuC.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK/hj)hhubh)}(hX#Context registration: Before a context can be submitted it must be registered with the GuC via a H2G. A unique guc_id is associated with each context. The context is either registered at request creation time (normal operation) or at submission time (abnormal operation, e.g. after a reset).h]hX#Context registration: Before a context can be submitted it must be registered with the GuC via a H2G. A unique guc_id is associated with each context. The context is either registered at request creation time (normal operation) or at submission time (abnormal operation, e.g. after a reset).}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK3hj)hhubh)}(hXContext submission: The i915 updates the LRC tail value in memory. The i915 must enable the scheduling of the context within the GuC for the GuC to actually consider it. Therefore, the first time a disabled context is submitted we use a schedule enable H2G, while follow up submissions are done via the context submit H2G, which informs the GuC that a previously enabled context has new work available.h]hXContext submission: The i915 updates the LRC tail value in memory. The i915 must enable the scheduling of the context within the GuC for the GuC to actually consider it. Therefore, the first time a disabled context is submitted we use a schedule enable H2G, while follow up submissions are done via the context submit H2G, which informs the GuC that a previously enabled context has new work available.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK9hj)hhubh)}(hX7Context unpin: To unpin a context a H2G is used to disable scheduling. When the corresponding G2H returns indicating the scheduling disable operation has completed it is safe to unpin the context. While a disable is in flight it isn't safe to resubmit the context so a fence is used to stall all future requests of that context until the G2H is returned. Because this interaction with the GuC takes a non-zero amount of time we delay the disabling of scheduling after the pin count goes to zero by a configurable period of time (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a window of time to resubmit something on the context before doing this costly operation. This delay is only done if the context isn't closed and the guc_id usage is less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).h]hX;Context unpin: To unpin a context a H2G is used to disable scheduling. When the corresponding G2H returns indicating the scheduling disable operation has completed it is safe to unpin the context. While a disable is in flight it isn’t safe to resubmit the context so a fence is used to stall all future requests of that context until the G2H is returned. Because this interaction with the GuC takes a non-zero amount of time we delay the disabling of scheduling after the pin count goes to zero by a configurable period of time (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a window of time to resubmit something on the context before doing this costly operation. This delay is only done if the context isn’t closed and the guc_id usage is less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKAhj)hhubh)}(hXContext deregistration: Before a context can be destroyed or if we steal its guc_id we must deregister the context with the GuC via H2G. If stealing the guc_id it isn't safe to submit anything to this guc_id until the deregister completes so a fence is used to stall all requests associated with this guc_id until the corresponding G2H returns indicating the guc_id has been deregistered.h]hXContext deregistration: Before a context can be destroyed or if we steal its guc_id we must deregister the context with the GuC via H2G. If stealing the guc_id it isn’t safe to submit anything to this guc_id until the deregister completes so a fence is used to stall all requests associated with this guc_id until the corresponding G2H returns indicating the guc_id has been deregistered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKNhj)hhubh)}(hsubmission_state.guc_ids: Unique number associated with private GuC context data passed in during context registration / submission / deregistration. 64k available. Simple ida is used for allocation.h]hsubmission_state.guc_ids: Unique number associated with private GuC context data passed in during context registration / submission / deregistration. 64k available. Simple ida is used for allocation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKUhj)hhubh)}(hX Stealing guc_ids: If no guc_ids are available they can be stolen from another context at request creation time if that context is unpinned. If a guc_id can't be found we punt this problem to the user as we believe this is near impossible to hit during normal use cases.h]hXStealing guc_ids: If no guc_ids are available they can be stolen from another context at request creation time if that context is unpinned. If a guc_id can’t be found we punt this problem to the user as we believe this is near impossible to hit during normal use cases.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKZhj)hhubh)}(hrLocking: In the GuC submission code we have 3 basic spin locks which protect everything. Details about each below.h]hrLocking: In the GuC submission code we have 3 basic spin locks which protect everything. Details about each below.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK`hj)hhubh)}(hX/sched_engine->lock This is the submission lock for all contexts that share an i915 schedule engine (sched_engine), thus only one of the contexts which share a sched_engine can be submitting at a time. Currently only one sched_engine is used for all of GuC submission but that could change in the future.h]hX/sched_engine->lock This is the submission lock for all contexts that share an i915 schedule engine (sched_engine), thus only one of the contexts which share a sched_engine can be submitting at a time. Currently only one sched_engine is used for all of GuC submission but that could change in the future.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKdhj)hhubh)}(hnguc->submission_state.lock Global lock for GuC submission state. Protects guc_ids and destroyed contexts list.h]hnguc->submission_state.lock Global lock for GuC submission state. Protects guc_ids and destroyed contexts list.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKjhj)hhubh)}(hXce->guc_state.lock Protects everything under ce->guc_state. Ensures that a context is in the correct state before issuing a H2G. e.g. We don't issue a schedule disable on a disabled context (bad idea), we don't issue a schedule enable when a schedule disable is in flight, etc... Also protects list of inflight requests on the context and the priority management state. Lock is individual to each context.h]hXce->guc_state.lock Protects everything under ce->guc_state. Ensures that a context is in the correct state before issuing a H2G. e.g. We don’t issue a schedule disable on a disabled context (bad idea), we don’t issue a schedule enable when a schedule disable is in flight, etc... Also protects list of inflight requests on the context and the priority management state. Lock is individual to each context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKnhj)hhubh)}(hnLock ordering rules: sched_engine->lock -> ce->guc_state.lock guc->submission_state.lock -> ce->guc_state.lockh]hnLock ordering rules: sched_engine->lock -> ce->guc_state.lock guc->submission_state.lock -> ce->guc_state.lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKvhj)hhubh)}(hXReset races: When a full GT reset is triggered it is assumed that some G2H responses to H2Gs can be lost as the GuC is also reset. Losing these G2H can prove to be fatal as we do certain operations upon receiving a G2H (e.g. destroy contexts, release guc_ids, etc...). When this occurs we can scrub the context state and cleanup appropriately, however this is quite racey. To avoid races, the reset code must disable submission before scrubbing for the missing G2H, while the submission code must check for submission being disabled and skip sending H2Gs and updating context states when it is. Both sides must also make sure to hold the relevant locks.h]hXReset races: When a full GT reset is triggered it is assumed that some G2H responses to H2Gs can be lost as the GuC is also reset. Losing these G2H can prove to be fatal as we do certain operations upon receiving a G2H (e.g. destroy contexts, release guc_ids, etc...). When this occurs we can scrub the context state and cleanup appropriately, however this is quite racey. To avoid races, the reset code must disable submission before scrubbing for the missing G2H, while the submission code must check for submission being disabled and skip sending H2Gs and updating context states when it is. Both sides must also make sure to hold the relevant locks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKzhj)hhubeh}(h]guc-based-command-submissionah ]h"]guc-based command submissionah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hGuC ABIh]hGuC ABI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM!ubhtarget)}(h.. _HXG Message:h]h}(h]h ]h"]h$]h&]j: hxg-messageuh1j%hKhjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hj<Kubh)}(h**HXG Message**h]jb)}(hj5h]h HXG Message}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj3ubah}(h]j1ah ]h"] hxg messageah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhexpect_referenced_by_name}jHj'sexpect_referenced_by_id}j1j'sj<Kubh)}(hAll messages exchanged with GuC are defined using 32 bit dwords. First dword is treated as a message header. Remaining dwords are optional.h]hAll messages exchanged with GuC are defined using 32 bit dwords. First dword is treated as a message header. Remaining dwords are optional.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK hjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | | | | | 0 | 31 | **ORIGIN** - originator of the message | | | | - _`GUC_HXG_ORIGIN_HOST` = 0 | | | | - _`GUC_HXG_ORIGIN_GUC` = 1 | | | | | | +-------+--------------------------------------------------------------+ | | 30:28 | **TYPE** - message type | | | | - _`GUC_HXG_TYPE_REQUEST` = 0 | | | | - _`GUC_HXG_TYPE_EVENT` = 1 | | | | - _`GUC_HXG_TYPE_FAST_REQUEST` = 2 | | | | - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3 | | | | - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5 | | | | - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6 | | | | - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7 | | +-------+--------------------------------------------------------------+ | | 27:0 | **AUX** - auxiliary data (depends on TYPE) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **PAYLOAD** - optional payload (depends on TYPE) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjjubhtbody)}(hhh](j)}(hhh](j)}(hhh]h)}(h0h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jx)}(hhh]j})}(h`**ORIGIN** - originator of the message - _`GUC_HXG_ORIGIN_HOST` = 0 - _`GUC_HXG_ORIGIN_GUC` = 1 h](j)}(h&**ORIGIN** - originator of the messageh](jb)}(h **ORIGIN**h]hORIGIN}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - originator of the message}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubj)}(hhh]j:)}(hhh](j:)}(h_`GUC_HXG_ORIGIN_HOST` = 0h]h)}(hjDh](j&)}(h_`GUC_HXG_ORIGIN_HOST`h]hGUC_HXG_ORIGIN_HOST}(hjIhhhNhNubah}(h]guc-hxg-origin-hostah ]h"]guc_hxg_origin_hostah$]h&]uh1j%hjFj<Kubh = 0}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjBubah}(h]h ]h"]h$]h&]uh1j:hj?ubj:)}(h_`GUC_HXG_ORIGIN_GUC` = 1 h]h)}(h_`GUC_HXG_ORIGIN_GUC` = 1h](j&)}(h_`GUC_HXG_ORIGIN_GUC`h]hGUC_HXG_ORIGIN_GUC}(hjrhhhNhNubah}(h]guc-hxg-origin-gucah ]h"]guc_hxg_origin_gucah$]h&]uh1j%hjnj<Kubh = 1}(hjnhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj;hKhjjubah}(h]h ]h"]h$]h&]uh1j:hj?ubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjchKhj<ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj;hKhjubah}(h]h ]h"]h$]h&]uh1jwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jx)}(hhh]j})}(hX**TYPE** - message type - _`GUC_HXG_TYPE_REQUEST` = 0 - _`GUC_HXG_TYPE_EVENT` = 1 - _`GUC_HXG_TYPE_FAST_REQUEST` = 2 - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3 - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5 - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6 - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7h](j)}(h**TYPE** - message typeh](jb)}(h**TYPE**h]hTYPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - message type}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubj)}(hhh]j:)}(hhh](j:)}(h_`GUC_HXG_TYPE_REQUEST` = 0h]h)}(hjh](j&)}(h_`GUC_HXG_TYPE_REQUEST`h]hGUC_HXG_TYPE_REQUEST}(hjhhhNhNubah}(h]guc-hxg-type-requestah ]h"]guc_hxg_type_requestah$]h&]uh1j%hjj<Kubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h_`GUC_HXG_TYPE_EVENT` = 1h]h)}(hj(h](j&)}(h_`GUC_HXG_TYPE_EVENT`h]hGUC_HXG_TYPE_EVENT}(hj-hhhNhNubah}(h]guc-hxg-type-eventah ]h"]guc_hxg_type_eventah$]h&]uh1j%hj*j<Kubh = 1}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj&ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h _`GUC_HXG_TYPE_FAST_REQUEST` = 2h]h)}(hjPh](j&)}(h_`GUC_HXG_TYPE_FAST_REQUEST`h]hGUC_HXG_TYPE_FAST_REQUEST}(hjUhhhNhNubah}(h]guc-hxg-type-fast-requestah ]h"]guc_hxg_type_fast_requestah$]h&]uh1j%hjRj<Kubh = 2}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjNubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h$_`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3h]h)}(hjxh](j&)}(h _`GUC_HXG_TYPE_NO_RESPONSE_BUSY`h]hGUC_HXG_TYPE_NO_RESPONSE_BUSY}(hj}hhhNhNubah}(h]guc-hxg-type-no-response-busyah ]h"]guc_hxg_type_no_response_busyah$]h&]uh1j%hjzj<Kubh = 3}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjvubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h%_`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5h]h)}(hjh](j&)}(h!_`GUC_HXG_TYPE_NO_RESPONSE_RETRY`h]hGUC_HXG_TYPE_NO_RESPONSE_RETRY}(hjhhhNhNubah}(h]guc-hxg-type-no-response-retryah ]h"]guc_hxg_type_no_response_retryah$]h&]uh1j%hjj<Kubh = 5}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h$_`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6h]h)}(hjh](j&)}(h _`GUC_HXG_TYPE_RESPONSE_FAILURE`h]hGUC_HXG_TYPE_RESPONSE_FAILURE}(hjhhhNhNubah}(h]guc-hxg-type-response-failureah ]h"]guc_hxg_type_response_failureah$]h&]uh1j%hjj<Kubh = 6}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h$_`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7h]h)}(hjh](j&)}(h _`GUC_HXG_TYPE_RESPONSE_SUCCESS`h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]guc-hxg-type-response-successah ]h"]guc_hxg_type_response_successah$]h&]uh1j%hjj<Kubh = 7}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubah}(h]h ]h"]h$]h&]uh1jwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj<ubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(h***AUX** - auxiliary data (depends on TYPE)h](jb)}(h**AUX**h]hAUX}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjWubh# - auxiliary data (depends on TYPE)}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjMhKhjTubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h0**PAYLOAD** - optional payload (depends on TYPE)h](jb)}(h **PAYLOAD**h]hPAYLOAD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh% - optional payload (depends on TYPE)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK#hjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjGh]hn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK%hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK%hj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]colsKuh1jhhjeubah}(h]h ]h"]h$]h&]uh1jchj_ubah}(h]h ]h"]h$]h&]uh1jKhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK hjhhubj&)}(h.. _HXG Request:h]h}(h]h ]h"]h$]h&]j: hxg-requestuh1j%hK#hjhhhj2j<Kubh)}(h**HXG Request**h]jb)}(hjeh]h HXG Request}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjcubah}(h]jbah ]h"] hxg requestah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK*hjhhjL}jxjXsjN}jbjXsj<Kubh)}(h}The `HXG Request`_ message should be used to initiate synchronous activity for which confirmation or return data is expected.h](hThe }(hj~hhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hj~j:Kubhk message should be used to initiate synchronous activity for which confirmation or return data is expected.}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK;hjhhubh)}(hThe recipient of this message shall use `HXG Response`_, `HXG Failure`_ or `HXG Retry`_ message as a definite reply, and may use `HXG Busy`_ message as a intermediate reply.h](h(The recipient of this message shall use }(hjhhhNhNubj!5)}(h`HXG Response`_h]h HXG Response}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Responsej: hxg-responseuh1j 5hjj:Kubh, }(hjhhhNhNubj!5)}(h`HXG Failure`_h]h HXG Failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Failurej: hxg-failureuh1j 5hjj:Kubh or }(hjhhhNhNubj!5)}(h `HXG Retry`_h]h HXG Retry}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Retryj: hxg-retryuh1j 5hjj:Kubh* message as a definite reply, and may use }(hjhhhNhNubj!5)}(h `HXG Busy`_h]hHXG Busy}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameHXG Busyj:hxg-busyuh1j 5hjj:Kubh! message as a intermediate reply.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK>hjhhubh)}(hLFormat of **DATA0** and all **DATAn** fields depends on the **ACTION** code.h](h Format of }(hjhhhNhNubjb)}(h **DATA0**h]hDATA0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and all }(hjhhhNhNubjb)}(h **DATAn**h]hDATAn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh fields depends on the }(hjhhhNhNubjb)}(h **ACTION**h]hACTION}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh code.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKBhjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **DATA0** - request data (depends on ACTION) | | +-------+--------------------------------------------------------------+ | | 15:0 | **ACTION** - requested action code | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - optional data (depends on ACTION) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjPubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjPubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjPubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjtubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKEhjubah}(h]h ]h"]h$]h&]uh1jhjtubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKEhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKGhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKGhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKGhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKIhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hj+hhhNhNubj!5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hj3hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESTj:juh1j 5hj+j:Kubeh}(h]h ]h"]h$]h&]uh1hhj!hKIhj(ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKKhjXubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(h,**DATA0** - request data (depends on ACTION)h](jb)}(h **DATA0**h]hDATA0}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjsubh# - request data (depends on ACTION)}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjihKKhjpubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h"**ACTION** - requested action codeh](jb)}(h **ACTION**h]hACTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - requested action code}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h-**DATAn** - optional data (depends on ACTION)h](jb)}(h **DATAn**h]hDATAn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh$ - optional data (depends on ACTION)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKQhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hKQhjBubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjGh]hn}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKShjkubah}(h]h ]h"]h$]h&]uh1jhjhubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hKShjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]colsKuh1jhhjMubah}(h]h ]h"]h$]h&]uh1jchjIubah}(h]h ]h"]h$]h&]uh1jKhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKDhjhhubj&)}(h.. _HXG Fast Request:h]h}(h]h ]h"]h$]h&]j:hxg-fast-requestuh1j%hKBhjhhhj2j<Kubh)}(h**HXG Fast Request**h]jb)}(hjh]hHXG Fast Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]hxg fast requestah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKXhjhhjL}jjsjN}jjsj<Kubh)}(hThe `HXG Request`_ message should be used to initiate asynchronous activity for which confirmation or return data is not expected.h](hThe }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:Kubhp message should be used to initiate asynchronous activity for which confirmation or return data is not expected.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK_hjhhubh)}(hFIf confirmation is required then `HXG Request`_ shall be used instead.h](h!If confirmation is required then }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hj hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:Kubh shall be used instead.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKbhjhhubh)}(h~The recipient of this message may only use `HXG Failure`_ message if it was unable to accept this request (like invalid data).h](h+The recipient of this message may only use }(hj%hhhNhNubj!5)}(h`HXG Failure`_h]h HXG Failure}(hj-hhhNhNubah}(h]h ]h"]h$]h&]name HXG Failurej:juh1j 5hj%j:KubhE message if it was unable to accept this request (like invalid data).}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKdhjhhubh)}(hPFormat of `HXG Fast Request`_ message is same as `HXG Request`_ except **TYPE**.h](h Format of }(hjHhhhNhNubj!5)}(h`HXG Fast Request`_h]hHXG Fast Request}(hjPhhhNhNubah}(h]h ]h"]h$]h&]nameHXG Fast Requestj:juh1j 5hjHj:Kubh message is same as }(hjHhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjdhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjHj:Kubh except }(hjHhhhNhNubjb)}(h**TYPE**h]hTYPE}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjHubh.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKghjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN - see `HXG Message`_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = `GUC_HXG_TYPE_FAST_REQUEST`_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 - see `HXG Request`_ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION - see `HXG Request`_ | +---+-------+--------------------------------------------------------------+ |...| | DATAn - see `HXG Request`_ | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKjhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKjhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKlhj ubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKlhj!ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGIN - see `HXG Message`_h](h ORIGIN - see }(hj;hhhNhNubj!5)}(h`HXG Message`_h]h HXG Message}(hjChhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagej:j1uh1j 5hj;j:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKlhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKnhjhubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(h#TYPE = `GUC_HXG_TYPE_FAST_REQUEST`_h](hTYPE = }(hjhhhNhNubj!5)}(h`GUC_HXG_TYPE_FAST_REQUEST`_h]hGUC_HXG_TYPE_FAST_REQUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_FAST_REQUESTj:j_uh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjyhKnhjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKphjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hDATA0 - see `HXG Request`_h](h DATA0 - see }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKphjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKrhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hACTION - see `HXG Request`_h](h ACTION - see }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhj hKrhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKthj@ubah}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh]h)}(hDATAn - see `HXG Request`_h](h DATAn - see }(hjdhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjlhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjdj:Kubeh}(h]h ]h"]h$]h&]uh1hhjQhKthjaubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhhjubah}(h]h ]h"]h$]h&]uh1jchjubah}(h]h ]h"]h$]h&]uh1jKhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKihjhhubj&)}(h.. _HXG Event:h]h}(h]h ]h"]h$]h&]j: hxg-eventuh1j%hK^hjhhhj2j<Kubh)}(h **HXG Event**h]jb)}(hjh]h HXG Event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"] hxg eventah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKyhjhhjL}jjsjN}jjsj<Kubh)}(hThe `HXG Event`_ message should be used to initiate asynchronous activity that does not involves immediate confirmation nor data.h](hThe }(hjhhhNhNubj!5)}(h `HXG Event`_h]h HXG Event}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Eventj:juh1j 5hjj:Kubhq message should be used to initiate asynchronous activity that does not involves immediate confirmation nor data.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK{hjhhubh)}(hLFormat of **DATA0** and all **DATAn** fields depends on the **ACTION** code.h](h Format of }(hjhhhNhNubjb)}(h **DATA0**h]hDATA0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and all }(hjhhhNhNubjb)}(h **DATAn**h]hDATAn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh fields depends on the }(hjhhhNhNubjb)}(h **ACTION**h]hACTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh code.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK~hjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_EVENT_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **DATA0** - event data (depends on ACTION) | | +-------+--------------------------------------------------------------+ | | 15:0 | **ACTION** - event action code | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - optional event data (depends on ACTION) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj=ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj=ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhj=ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(hBitsh]hBits}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjmubah}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKhjubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_EVENT_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_EVENT_h]hGUC_HXG_TYPE_EVENT}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_EVENTj:j7uh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjEubah}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh]h)}(h***DATA0** - event data (depends on ACTION)h](jb)}(h **DATA0**h]hDATA0}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubh! - event data (depends on ACTION)}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjVhKhj]ubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h**ACTION** - event action codeh](jb)}(h **ACTION**h]hACTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - event action code}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h4**DATAn** - optional event data (depends on ACTION)h](jb)}(h **DATAn**h]hDATAn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh+ - optional event data (depends on ACTION)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhj/ubah}(h]h ]h"]h$]h&]uh1jhj,ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjGh]hn}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjXubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(h31:0h]h31:0}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhKhjoubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]colsKuh1jhhj:ubah}(h]h ]h"]h$]h&]uh1jchj6ubah}(h]h ]h"]h$]h&]uh1jKhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj&)}(h .. _HXG Busy:h]h}(h]h ]h"]h$]h&]j:juh1j%hKyhjhhhj2j<Kubh)}(h **HXG Busy**h]jb)}(hjh]hHXG Busy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]hxg busyah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhjL}jjsjN}jjsj<Kubh)}(hThe `HXG Busy`_ message may be used to acknowledge reception of the `HXG Request`_ message if the recipient expects that it processing will be longer than default timeout.h](hThe }(hjhhhNhNubj!5)}(h `HXG Busy`_h]hHXG Busy}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameHXG Busyj:juh1j 5hjj:Kubh5 message may be used to acknowledge reception of the }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:KubhY message if the recipient expects that it processing will be longer than default timeout.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubh)}(h:The **COUNTER** field may be used as a progress indicator.h](hThe }(hjhhhNhNubjb)}(h **COUNTER**h]hCOUNTER}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh+ field may be used as a progress indicator.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_NO_RESPONSE_BUSY_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **COUNTER** - progress indicator | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj*ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj*ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhj*ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh]h)}(hBitsh]hBits}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjZubah}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh]h)}(h Descriptionh]h Description}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhKhjrubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhj*ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_NO_RESPONSE_BUSY_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_NO_RESPONSE_BUSY_h]hGUC_HXG_TYPE_NO_RESPONSE_BUSY}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_NO_RESPONSE_BUSYj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj2ubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(hhh]h)}(h **COUNTER** - progress indicatorh](jb)}(h **COUNTER**h]hCOUNTER}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjMubh - progress indicator}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjChKhjJubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]colsKuh1jhhj'ubah}(h]h ]h"]h$]h&]uh1jchj#ubah}(h]h ]h"]h$]h&]uh1jKhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj&)}(h.. _HXG Retry:h]h}(h]h ]h"]h$]h&]j:juh1j%hKhjhhhj2j<Kubh)}(h **HXG Retry**h]jb)}(hjh]h HXG Retry}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"] hxg retryah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhjL}jjsjN}jjsj<Kubh)}(hThe `HXG Retry`_ message should be used by recipient to indicate that the `HXG Request`_ message was dropped and it should be resent again.h](hThe }(hjhhhNhNubj!5)}(h `HXG Retry`_h]h HXG Retry}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Retryj:juh1j 5hjj:Kubh: message should be used by recipient to indicate that the }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:Kubh3 message was dropped and it should be resent again.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubh)}(hCThe **REASON** field may be used to provide additional information.h](hThe }(hjhhhNhNubjb)}(h **REASON**h]hREASON}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh5 field may be used to provide additional information.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_NO_RESPONSE_RETRY_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **REASON** - reason for retry | | | | - _`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0 | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj7ubj)}(hhh]h)}(hBitsh]hBits}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjCubah}(h]h ]h"]h$]h&]uh1jhj7ubj)}(hhh]h)}(h Descriptionh]h Description}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThKhj[ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj~ubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h&TYPE = GUC_HXG_TYPE_NO_RESPONSE_RETRY_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_NO_RESPONSE_RETRY_h]hGUC_HXG_TYPE_NO_RESPONSE_RETRY}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_NO_RESPONSE_RETRYj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj~ubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jx)}(hhh]j})}(hG**REASON** - reason for retry - _`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0 h](j)}(h**REASON** - reason for retryh](jb)}(h **REASON**h]hREASON}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj=ubh - reason for retry}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhj,hKhj9ubj)}(hhh]j:)}(hhh]j:)}(h'_`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0h]h)}(hjah](j&)}(h#_`GUC_HXG_RETRY_REASON_UNSPECIFIED`h]h GUC_HXG_RETRY_REASON_UNSPECIFIED}(hjfhhhNhNubah}(h] guc-hxg-retry-reason-unspecifiedah ]h"] guc_hxg_retry_reason_unspecifiedah$]h&]uh1j%hjcubh = 0}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj_ubah}(h]h ]h"]h$]h&]uh1j:hj\ubah}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjYubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j|hj,hKhj6ubah}(h]h ]h"]h$]h&]uh1jwhj3ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhhjubah}(h]h ]h"]h$]h&]uh1jchj ubah}(h]h ]h"]h$]h&]uh1jKhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj&)}(h.. _HXG Failure:h]h}(h]h ]h"]h$]h&]j:juh1j%hKhjhhhj2j<Kubh)}(h**HXG Failure**h]jb)}(hjh]h HXG Failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"] hxg failureah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhjL}jjsjN}jjsj<Kubh)}(h~The `HXG Failure`_ message shall be used as a reply to the `HXG Request`_ message that could not be processed due to an error.h](hThe }(hjhhhNhNubj!5)}(h`HXG Failure`_h]h HXG Failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Failurej:juh1j 5hjj:Kubh) message shall be used as a reply to the }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:Kubh5 message that could not be processed due to an error.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubjL)}(hXO+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_FAILURE_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **HINT** - additional error hint | | +-------+--------------------------------------------------------------+ | | 15:0 | **ERROR** - error/result code | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj(ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj(ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhj(ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjLubj)}(hhh]h)}(hBitsh]hBits}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjXubah}(h]h ]h"]h$]h&]uh1jhjLubj)}(hhh]h)}(h Descriptionh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKhjpubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_FAILURE_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_RESPONSE_FAILURE_h]hGUC_HXG_TYPE_RESPONSE_FAILURE}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_FAILUREj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj0ubah}(h]h ]h"]h$]h&]uh1jhj-ubj)}(hhh]h)}(h **HINT** - additional error hinth](jb)}(h**HINT**h]hHINT}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjKubh - additional error hint}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjAhKhjHubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjvubah}(h]h ]h"]h$]h&]uh1jhjsubj)}(hhh]h)}(h**ERROR** - error/result codeh](jb)}(h **ERROR**h]hERROR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - error/result code}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]colsKuh1jhhj%ubah}(h]h ]h"]h$]h&]uh1jchj!ubah}(h]h ]h"]h$]h&]uh1jKhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj&)}(h.. _HXG Response:h]h}(h]h ]h"]h$]h&]j:juh1j%hKhjhhhj2j<Kubh)}(h**HXG Response**h]jb)}(hjh]h HXG Response}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"] hxg responseah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhjL}jjsjN}jjsj<Kubh)}(hThe `HXG Response`_ message shall be used as a reply to the `HXG Request`_ message that was successfully processed without an error.h](hThe }(hjhhhNhNubj!5)}(h`HXG Response`_h]h HXG Response}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Responsej:juh1j 5hjj:Kubh) message shall be used as a reply to the }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:Kubh: message that was successfully processed without an error.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **DATA0** - data (depends on ACTION from `HXG Request`_) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - data (depends on ACTION from `HXG Request`_) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj6ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj6ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhj6ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjZubj)}(hhh]h)}(hBitsh]hBits}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjfubah}(h]h ]h"]h$]h&]uh1jhjZubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhKhj~ubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jhj6ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGINh]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESSj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj>ubah}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh]h)}(h8**DATA0** - data (depends on ACTION from `HXG Request`_)h](jb)}(h **DATA0**h]hDATA0}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjYubh - data (depends on ACTION from }(hjYhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjohhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjYj:Kubh)}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjOhKhjVubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h8**DATAn** - data (depends on ACTION from `HXG Request`_)h](jb)}(h **DATAn**h]hDATAn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - data (depends on ACTION from }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:jbuh1j 5hjj:Kubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjGh]hn}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj3ubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(hhh]h)}(h31:0h]h31:0}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChKhjJubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]colsKuh1jhhj3ubah}(h]h ]h"]h$]h&]uh1jchj/ubah}(h]h ]h"]h$]h&]uh1jKhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj&)}(h!.. _GuC MMIO based communication:h]h}(h]h ]h"]h$]h&]j:guc-mmio-based-communicationuh1j%hKhjhhhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hubh)}(h **GuC MMIO based communication**h]jb)}(hjh]hGuC MMIO based communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]guc mmio based communicationah$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhjL}jjsjN}jjsubh)}(hThe MMIO based communication between Host and GuC relies on special hardware registers which format could be defined by the software (so called scratch registers).h]hThe MMIO based communication between Host and GuC relies on special hardware registers which format could be defined by the software (so called scratch registers).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK hjhhubh)}(hEach MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) messages, which maximum length depends on number of available scratch registers, is directly written into those scratch registers.h]hEach MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) messages, which maximum length depends on number of available scratch registers, is directly written into those scratch registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhubh)}(hFor Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, but no H2G command takes more than 4 parameters and the GuC firmware itself uses an 4-element array to store the H2G message.h]hFor Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, but no H2G command takes more than 4 parameters and the GuC firmware itself uses an 4-element array to store the H2G message.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhubh)}(hFor Gen11+, there are additional 4 registers 0x190240-0x19024C, which are, regardless on lower count, preferred over legacy ones.h]hFor Gen11+, there are additional 4 registers 0x190240-0x19024C, which are, regardless on lower count, preferred over legacy ones.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhubh)}(hThe MMIO based communication is mainly used during driver initialization phase to setup the `CTB based communication`_ that will be used afterwards.h](h\The MMIO based communication is mainly used during driver initialization phase to setup the }(hjhhhNhNubj!5)}(h`CTB based communication`_h]hCTB based communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameCTB based communicationj:ctb-based-communicationuh1j 5hjj:Kubh that will be used afterwards.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhubj&)}(h.. _MMIO HXG Message:h]h}(h]h ]h"]h$]h&]j:mmio-hxg-messageuh1j%hKhjhhhjj<Kubh)}(h**MMIO HXG Message**h]jb)}(hjh]hMMIO HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]mmio hxg messageah$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhjL}j(jsjN}jjsj<Kubh)}(hBFormat of the MMIO messages follows definitions of `HXG Message`_.h](h3Format of the MMIO messages follows definitions of }(hj.hhhNhNubj!5)}(h`HXG Message`_h]h HXG Message}(hj6hhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagej:j1uh1j 5hj.j:Kubh.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK"hjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:0 | | +---+-------+ | |...| | [Embedded `HXG Message`_] | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjXubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjXubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjXubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK%hjubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK%hjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhjXubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[Embedded `HXG Message`_]h](h [Embedded }(hjhhhNhNubj!5)}(h`HXG Message`_h]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagej:j1uh1j 5hjj:Kubh]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK)hjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK)hj-ubah}(h]h ]h"]h$]h&]uh1jhj*ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjGh]hn}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK+hjVubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(hhh]h)}(h31:0h]h31:0}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhK+hjmubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]colsKuh1jhhjUubah}(h]h ]h"]h$]h&]uh1jchjQubah}(h]h ]h"]h$]h&]uh1jKhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK$hjhhubj&)}(h.. _CT Buffer:h]h}(h]h ]h"]h$]h&]j: ct-bufferuh1j%hKhjhhhNj<Kubh)}(h **CT Buffer**h]jb)}(hjh]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"] ct bufferah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhjL}jjsjN}jjsj<Kubh)}(h+Circular buffer used to send `CTB Message`_h](hCircular buffer used to send }(hjhhhNhNubj!5)}(h`CTB Message`_h]h CTB Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CTB Messagej: ctb-messageuh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubj&)}(h.. _CTB Descriptor:h]h}(h]h ]h"]h$]h&]j:ctb-descriptoruh1j%hKhjhhhNj<Kubh)}(h**CTB Descriptor**h]jb)}(hjh]hCTB Descriptor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]ctb descriptorah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhjL}j jsjN}jjsj<KubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:0 | **HEAD** - offset (in dwords) to the last dword that was | | | | read from the `CT Buffer`_. | | | | It can only be updated by the receiver. | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **TAIL** - offset (in dwords) to the last dword that was | | | | written to the `CT Buffer`_. | | | | It can only be updated by the sender. | +---+-------+--------------------------------------------------------------+ | 2 | 31:0 | **STATUS** - status of the CTB | | | | | | | | - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation) | | | | - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large) | | | | - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message) | | | | - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified) | | | | - _`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use) | +---+-------+--------------------------------------------------------------+ |...| | RESERVED = MBZ | +---+-------+--------------------------------------------------------------+ | 15| 31:0 | RESERVED = MBZ | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh]h)}(hBitsh]hBits}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjGubah}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh]h)}(h Descriptionh]h Description}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhKhj_ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h|**HEAD** - offset (in dwords) to the last dword that was read from the `CT Buffer`_. It can only be updated by the receiver.h](jb)}(h**HEAD**h]hHEAD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh? - offset (in dwords) to the last dword that was read from the }(hjhhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:juh1j 5hjj:Kubh). It can only be updated by the receiver.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h{**TAIL** - offset (in dwords) to the last dword that was written to the `CT Buffer`_. It can only be updated by the sender.h](jb)}(h**TAIL**h]hTAIL}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj)ubh@ - offset (in dwords) to the last dword that was written to the }(hj)hhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hj?hhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:juh1j 5hj)j:Kubh'. It can only be updated by the sender.}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhj&ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h2h]h2}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK hjhubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhK hjubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh](h)}(h**STATUS** - status of the CTBh](jb)}(h **STATUS**h]hSTATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - status of the CTB}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjyhK hjubjL)}(hX - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation) - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large) - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message) - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified) - _`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use)h]j:)}(hhh](j:)}(h1_`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation)h]h)}(hjh](j&)}(h_`GUC_CTB_STATUS_NO_ERROR`h]hGUC_CTB_STATUS_NO_ERROR}(hjhhhNhNubah}(h]guc-ctb-status-no-errorah ]h"]guc_ctb_status_no_errorah$]h&]uh1j%hjubh = 0 (normal operation)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK"hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h4_`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large)h]h)}(hjh](j&)}(h_`GUC_CTB_STATUS_OVERFLOW`h]hGUC_CTB_STATUS_OVERFLOW}(hjhhhNhNubah}(h]guc-ctb-status-overflowah ]h"]guc_ctb_status_overflowah$]h&]uh1j%hjubh = 1 (head/tail too large)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK#hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h3_`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)h]h)}(hjh](j&)}(h_`GUC_CTB_STATUS_UNDERFLOW`h]hGUC_CTB_STATUS_UNDERFLOW}(hjhhhNhNubah}(h]guc-ctb-status-underflowah ]h"]guc_ctb_status_underflowah$]h&]uh1j%hjubh = 2 (truncated message)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK$hj ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h3_`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)h]h)}(hj7h](j&)}(h_`GUC_CTB_STATUS_MISMATCH`h]hGUC_CTB_STATUS_MISMATCH}(hj<hhhNhNubah}(h]guc-ctb-status-mismatchah ]h"]guc_ctb_status_mismatchah$]h&]uh1j%hj9ubh = 4 (head/tail modified)}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK%hj5ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h0_`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use)h]h)}(hj_h](j&)}(h_`GUC_CTB_STATUS_UNUSED`h]hGUC_CTB_STATUS_UNUSED}(hjdhhhNhNubah}(h]guc-ctb-status-unusedah ]h"]guc_ctb_status_unusedah$]h&]uh1j%hjaubh = 8 (CTB is not in use)}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK&hj]ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhK"hjubah}(h]h ]h"]h$]h&]uh1jKhjhK"hjubeh}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15h]h15}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhhjubah}(h]h ]h"]h$]h&]uh1jchjubah}(h]h ]h"]h$]h&]uh1jKht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubj&)}(h.. _CTB Message:h]h}(h]h ]h"]h$]h&]j:juh1j%hK#hjhhhNj<Kubh)}(h**CTB Message**h]jb)}(hjSh]h CTB Message}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjQubah}(h]jah ]h"] ctb messageah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK/hjhhjL}jfjGsjN}jjGsj<KubjL)}(hXj+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | **FENCE** - message identifier | | +-------+--------------------------------------------------------------+ | | 15:12 | **FORMAT** - format of the CTB message | | | | - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_ | | +-------+--------------------------------------------------------------+ | | 11:8 | **RESERVED** | | +-------+--------------------------------------------------------------+ | | 7:0 | **NUM_DWORDS** - length of the CTB message (w/o header) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | optional (depends on FORMAT) | +---+-------+ | |...| | | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjsubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjsubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjsubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK?hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK?hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjsubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKAhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31:16h]h31:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKAhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h**FENCE** - message identifierh](jb)}(h **FENCE**h]hFENCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - message identifier}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKAhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:12h]h15:12}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKChjAubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh]jx)}(hhh]j})}(h[**FORMAT** - format of the CTB message - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_h](j)}(h&**FORMAT** - format of the CTB messageh](jb)}(h **FORMAT**h]hFORMAT}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjcubh - format of the CTB message}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjRhKChj_ubj)}(hhh]j:)}(hhh]j:)}(h2_`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_h]h)}(hjh](j&)}(h_`GUC_CTB_FORMAT_HXG`h]hGUC_CTB_FORMAT_HXG}(hjhhhNhNubah}(h]guc-ctb-format-hxgah ]h"]guc_ctb_format_hxgah$]h&]uh1j%hjj<Kubh = 0 - see }(hjhhhNhNubj!5)}(h`CTB HXG Message`_h]hCTB HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameCTB HXG Messagej:ctb-hxg-messageuh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKDhjubah}(h]h ]h"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKDhjubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hjRhKChj\ubah}(h]h ]h"]h$]h&]uh1jwhjYubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h11:8h]h11:8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKFhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h **RESERVED**h]jb)}(hjh]hRESERVED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhjhKFhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h7:0h]h7:0}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKHhj&ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(h7**NUM_DWORDS** - length of the CTB message (w/o header)h](jb)}(h**NUM_DWORDS**h]h NUM_DWORDS}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjAubh) - length of the CTB message (w/o header)}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj7hKHhj>ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKJhjlubah}(h]h ]h"]h$]h&]uh1jhjiubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hKJhjubah}(h]h ]h"]h$]h&]uh1jhjiubj)}(hhh]h)}(hoptional (depends on FORMAT)h]hoptional (depends on FORMAT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hKJhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjiubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKLhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjGh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKNhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKNhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]colsKuh1jhhjpubah}(h]h ]h"]h$]h&]uh1jchjlubah}(h]h ]h"]h$]h&]uh1jKht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK>hjhhubj&)}(h.. _CTB HXG Message:h]h}(h]h ]h"]h$]h&]j:juh1j%hK:hjhhhNj<Kubh)}(h**CTB HXG Message**h]jb)}(hj?h]hCTB HXG Message}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj=ubah}(h]jah ]h"]ctb hxg messageah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKShjhhjL}jRj3sjN}jj3sj<KubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | FENCE | | +-------+--------------------------------------------------------------+ | | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_ | | +-------+--------------------------------------------------------------+ | | 11:8 | RESERVED = MBZ | | +-------+--------------------------------------------------------------+ | | 7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | [Embedded `HXG Message`_] | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj_ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj_ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhj_ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK_hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK_hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj_ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKahjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31:16h]h31:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKahjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFENCEh]hFENCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKahjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:12h]h15:12}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKchjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFORMAT = GUC_CTB_FORMAT_HXG_h](h FORMAT = }(hj:hhhNhNubj!5)}(hGUC_CTB_FORMAT_HXG_h]hGUC_CTB_FORMAT_HXG}(hjBhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_CTB_FORMAT_HXGj:juh1j 5hj:j:Kubeh}(h]h ]h"]h$]h&]uh1hhj0hKchj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h11:8h]h11:8}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKehjgubah}(h]h ]h"]h$]h&]uh1jhjdubj)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhKehjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h7:0h]h7:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKghjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h;NUM_DWORDS = length (in dwords) of the embedded HXG messageh]h;NUM_DWORDS = length (in dwords) of the embedded HXG message}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKghjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKihjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKihjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[Embedded `HXG Message`_]h](h [Embedded }(hjhhhNhNubj!5)}(h`HXG Message`_h]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagej:j1uh1j 5hjj:Kubh]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKkhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hKkhj;ubah}(h]h ]h"]h$]h&]uh1jhj8ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjGh]hn}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKmhjdubah}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(h31:0h]h31:0}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthKmhj{ubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]colsKuh1jhhj\ubah}(h]h ]h"]h$]h&]uh1jchjXubah}(h]h ]h"]h$]h&]uh1jKht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK^hjhhubj&)}(h.. _CTB based communication:h]h}(h]h ]h"]h$]h&]j:juh1j%hKPhjhhhNj<Kubh)}(h**CTB based communication**h]jb)}(hjh]hCTB based communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]ctb based communicationah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKrhjhhjL}jjsjN}jjsj<Kubh)}(hThe CTB (command transport buffer) communication between Host and GuC is based on u32 data stream written to the shared buffer. One buffer can be used to transmit data only in one direction (one-directional channel).h]hThe CTB (command transport buffer) communication between Host and GuC is based on u32 data stream written to the shared buffer. One buffer can be used to transmit data only in one direction (one-directional channel).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKwhjhhubh)}(hX Current status of the each buffer is stored in the buffer descriptor. Buffer descriptor holds tail and head fields that represents active data stream. The tail field is updated by the data producer (sender), and head field is updated by the data consumer (receiver)::h]hX Current status of the each buffer is stored in the buffer descriptor. Buffer descriptor holds tail and head fields that represents active data stream. The tail field is updated by the data producer (sender), and head field is updated by the data consumer (receiver):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK{hjhhubj")}(hX+------------+ | DESCRIPTOR | +=================+============+========+ +============+ | | MESSAGE(s) | | | address |--------->+=================+============+========+ +------------+ | head | ^-----head--------^ +------------+ | tail | ^---------tail-----------------^ +------------+ | size | ^---------------size--------------------^ +------------+h]hX+------------+ | DESCRIPTOR | +=================+============+========+ +============+ | | MESSAGE(s) | | | address |--------->+=================+============+========+ +------------+ | head | ^-----head--------^ +------------+ | tail | ^---------tail-----------------^ +------------+ | size | ^---------------size--------------------^ +------------+}hjsbah}(h]h ]h"]h$]h&]jjuh1j"ht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubh)}(hEach message in data stream starts with the single u32 treated as a header, followed by optional set of u32 data that makes message specific payload::h]hEach message in data stream starts with the single u32 treated as a header, followed by optional set of u32 data that makes message specific payload:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubj")}(hX+------------+---------+---------+---------+ | MESSAGE | +------------+---------+---------+---------+ | msg[0] | [1] | ... | [n-1] | +------------+---------+---------+---------+ | MESSAGE | MESSAGE PAYLOAD | + HEADER +---------+---------+---------+ | | 0 | ... | n | +======+=====+=========+=========+=========+ | 31:16| code| | | | +------+-----+ | | | | 15:5|flags| | | | +------+-----+ | | | | 4:0| len| | | | +------+-----+---------+---------+---------+ ^-------------len-------------^h]hX+------------+---------+---------+---------+ | MESSAGE | +------------+---------+---------+---------+ | msg[0] | [1] | ... | [n-1] | +------------+---------+---------+---------+ | MESSAGE | MESSAGE PAYLOAD | + HEADER +---------+---------+---------+ | | 0 | ... | n | +======+=====+=========+=========+=========+ | 31:16| code| | | | +------+-----+ | | | | 15:5|flags| | | | +------+-----+ | | | | 4:0| len| | | | +------+-----+---------+---------+---------+ ^-------------len-------------^}hjsbah}(h]h ]h"]h$]h&]jjuh1j"ht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubh)}(hThe message header consists of:h]hThe message header consists of:}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubj:)}(hhh](j:)}(h9**len**, indicates length of the message payload (in u32)h]h)}(hj6h](jb)}(h**len**h]hlen}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj8ubh2, indicates length of the message payload (in u32)}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhj4ubah}(h]h ]h"]h$]h&]uh1j:hj1ubj:)}(h **code**, indicates message codeh]h)}(hj\h](jb)}(h**code**h]hcode}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jahj^ubh, indicates message code}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjZubah}(h]h ]h"]h$]h&]uh1j:hj1ubj:)}(h:**flags**, holds various bits to control message handling h]h)}(h9**flags**, holds various bits to control message handlingh](jb)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh0, holds various bits to control message handling}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hj1ubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjShKhjhhubj&)}(h.. _HOST2GUC_SELF_CFG:h]h}(h]h ]h"]h$]h&]j:host2guc-self-cfguh1j%hKhjhhhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hj<Kubh)}(h**HOST2GUC_SELF_CFG**h]jb)}(hjh]hHOST2GUC_SELF_CFG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]host2guc_self_cfgah$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjhhjL}jjsjN}jjsj<Kubh)}(hIThis message is used by Host KMD to setup of the `GuC Self Config KLVs`_.h](h1This message is used by Host KMD to setup of the }(hjhhhNhNubj!5)}(h`GuC Self Config KLVs`_h]hGuC Self Config KLVs}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVsj:guc-self-config-klvsuh1j 5hjj:Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjhhubh)}(h1This message must be sent as `MMIO HXG Message`_.h](hThis message must be sent as }(hjhhhNhNubj!5)}(h`MMIO HXG Message`_h]hMMIO HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameMMIO HXG Messagej:juh1j 5hjj:Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjhhubjL)}(hXT +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 = MBZ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508 | +---+-------+--------------------------------------------------------------+ | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_ | | +-------+--------------------------------------------------------------+ | | 15:0 | **KLV_LEN** - KLV length | | | | | | | | - 32 bit KLV = 1 | | | | - 64 bit KLV = 2 | +---+-------+--------------------------------------------------------------+ | 2 | 31:0 | **VALUE32** - Bits 31-0 of the KLV value | +---+-------+--------------------------------------------------------------+ | 3 | 31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2) | +---+-------+--------------------------------------------------------------+ +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized | +---+-------+--------------------------------------------------------------+ h](jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj"ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj"ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhj"ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjFubj)}(hhh]h)}(hBitsh]hBits}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjRubah}(h]h ]h"]h$]h&]uh1jhjFubj)}(hhh]h)}(h Descriptionh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchKhjjubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_HOST_h](h ORIGIN = }(hjhhhNhNubj!5)}(hGUC_HXG_ORIGIN_HOST_h]hGUC_HXG_ORIGIN_HOST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_HOSTj:jSuh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hLhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hj hhhNhNubj!5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESTj:juh1j 5hj j:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhj:ubah}(h]h ]h"]h$]h&]uh1jhj7ubj)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhKhjRubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjrubah}(h]h ]h"]h$]h&]uh1jhjoubj)}(hhh]h)}(h1ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508h](h ACTION = }(hjhhhNhNubj&)}(h_`GUC_ACTION_HOST2GUC_SELF_CFG`h]hGUC_ACTION_HOST2GUC_SELF_CFG}(hjhhhNhNubah}(h]guc-action-host2guc-self-cfgah ]h"]guc_action_host2guc_self_cfgah$]h&]uh1j%hjubh = 0x0508}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31:16h]h31:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h2**KLV_KEY** - KLV key, see `GuC Self Config KLVs`_h](jb)}(h **KLV_KEY**h]hKLV_KEY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - KLV key, see }(hjhhhNhNubj!5)}(h`GuC Self Config KLVs`_h]hGuC Self Config KLVs}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVsj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhj+ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh](h)}(h**KLV_LEN** - KLV lengthh](jb)}(h **KLV_LEN**h]hKLV_LEN}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFubh - KLV length}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj<hKhjCubjL)}(h!- 32 bit KLV = 1 - 64 bit KLV = 2h]j:)}(hhh](j:)}(h32 bit KLV = 1h]h)}(hjkh]h32 bit KLV = 1}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjiubah}(h]h ]h"]h$]h&]uh1j:hjfubj:)}(h64 bit KLV = 2h]h)}(hjh]h64 bit KLV = 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjfubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjzhKhjbubah}(h]h ]h"]h$]h&]uh1jKhjzhKhjCubeh}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjmh]h2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h(**VALUE32** - Bits 31-0 of the KLV valueh](jb)}(h **VALUE32**h]hVALUE32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - Bits 31-0 of the KLV value}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h3h]h3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK"hjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h31:0h]h31:0}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hK"hj(ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h;**VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2)h](jb)}(h **VALUE64**h]hVALUE64}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjBubh - Bits 63-32 of the KLV value (}(hjBhhhNhNubjb)}(h **KLV_LEN**h]hKLV_LEN}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjBubh = 2)}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj!hK"hj?ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]colsKuh1jhhjubah}(h]h ]h"]h$]h&]uh1jchjubjd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK&hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK&hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK(hjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_GUC_h](h ORIGIN = }(hj5hhhNhNubj!5)}(hGUC_HXG_ORIGIN_GUC_h]hGUC_HXG_ORIGIN_GUC}(hj=hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_GUCj:j|uh1j 5hj5j:Kubeh}(h]h ]h"]h$]h&]uh1hhjhK(hj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK*hjbubah}(h]h ]h"]h$]h&]uh1jhj_ubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hj}hhhNhNubj!5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESSj:juh1j 5hj}j:Kubeh}(h]h ]h"]h$]h&]uh1hhjshK*hjzubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h:DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognizedh](hDATA0 = }(hjhhhNhNubjb)}(h**NUM**h]hNUM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh+ - 1 if KLV was parsed, 0 if not recognized}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhhjubah}(h]h ]h"]h$]h&]uh1jchjubeh}(h]h ]h"]h$]h&]uh1jKhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjhhubj&)}(h.. _HOST2GUC_CONTROL_CTB:h]h}(h]h ]h"]h$]h&]j:host2guc-control-ctbuh1j%hK*hjhhhjubh)}(h**HOST2GUC_CONTROL_CTB**h]jb)}(hjh]hHOST2GUC_CONTROL_CTB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]host2guc_control_ctbah$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK1hjhhjL}j+j sjN}jj subh)}(hMThis H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_.h](h@This H2G action allows Vf Host to enable or disable H2G and G2H }(hj1hhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hj9hhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:juh1j 5hj1j:Kubh.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK>hjhhubh)}(h1This message must be sent as `MMIO HXG Message`_.h](hThis message must be sent as }(hjThhhNhNubj!5)}(h`MMIO HXG Message`_h]hMMIO HXG Message}(hj\hhhNhNubah}(h]h ]h"]h$]h&]nameMMIO HXG Messagej:juh1j 5hjTj:Kubh.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK@hjhhubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 = MBZ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509 | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **CONTROL** - control `CTB based communication`_ | | | | | | | | - _`GUC_CTB_CONTROL_DISABLE` = 0 | | | | - _`GUC_CTB_CONTROL_ENABLE` = 1 | +---+-------+--------------------------------------------------------------+ +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | DATA0 = MBZ | +---+-------+--------------------------------------------------------------+ h](jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj~ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhj~ubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhj~ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKChjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKChjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj~ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKEhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31h]h31}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKEhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_HOST_h](h ORIGIN = }(hj!hhhNhNubj!5)}(hGUC_HXG_ORIGIN_HOST_h]hGUC_HXG_ORIGIN_HOST}(hj)hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_HOSTj:jSuh1j 5hj!j:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKEhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKGhjNubah}(h]h ]h"]h$]h&]uh1jhjKubj)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hjihhhNhNubj!5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hjqhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESTj:juh1j 5hjij:Kubeh}(h]h ]h"]h$]h&]uh1hhj_hKGhjfubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h4ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509h](h ACTION = }(hjhhhNhNubj&)}(h"_`GUC_ACTION_HOST2GUC_CONTROL_CTB`h]hGUC_ACTION_HOST2GUC_CONTROL_CTB}(hjhhhNhNubah}(h]guc-action-host2guc-control-ctbah ]h"]guc_action_host2guc_control_ctbah$]h&]uh1j%hjubh = 0x4509}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hKMhj1ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h0**CONTROL** - control `CTB based communication`_h](jb)}(h **CONTROL**h]hCONTROL}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjKubh - control }(hjKhhhNhNubj!5)}(h`CTB based communication`_h]hCTB based communication}(hjahhhNhNubah}(h]h ]h"]h$]h&]nameCTB based communicationj:juh1j 5hjKj:Kubeh}(h]h ]h"]h$]h&]uh1hhj*hKMhjHubjL)}(h@- _`GUC_CTB_CONTROL_DISABLE` = 0 - _`GUC_CTB_CONTROL_ENABLE` = 1h]j:)}(hhh](j:)}(h_`GUC_CTB_CONTROL_DISABLE` = 0h]h)}(hjh](j&)}(h_`GUC_CTB_CONTROL_DISABLE`h]hGUC_CTB_CONTROL_DISABLE}(hjhhhNhNubah}(h]guc-ctb-control-disableah ]h"]guc_ctb_control_disableah$]h&]uh1j%hjubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKOhj~ubah}(h]h ]h"]h$]h&]uh1j:hj{ubj:)}(h_`GUC_CTB_CONTROL_ENABLE` = 1h]h)}(hjh](j&)}(h_`GUC_CTB_CONTROL_ENABLE`h]hGUC_CTB_CONTROL_ENABLE}(hjhhhNhNubah}(h]guc-ctb-control-enableah ]h"]guc_ctb_control_enableah$]h&]uh1j%hjubh = 1}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKPhjubah}(h]h ]h"]h$]h&]uh1j:hj{ubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKOhjwubah}(h]h ]h"]h$]h&]uh1jKhjhKOhjHubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]colsKuh1jhhj{ubah}(h]h ]h"]h$]h&]uh1jchjwubjd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hBitsh]hBits}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKThj,ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Descriptionh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKThjDubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKVhjmubah}(h]h ]h"]h$]h&]morerowsKuh1jhjjubj)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hKVhjubah}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_GUC_h](h ORIGIN = }(hjhhhNhNubj!5)}(hGUC_HXG_ORIGIN_GUC_h]hGUC_HXG_ORIGIN_GUC}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_GUCj:j|uh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhj}hKVhjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjgubj)}(hhh](j)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKXhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESSj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKXhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjgubj)}(hhh](j)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hKZhj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhhjubah}(h]h ]h"]h$]h&]uh1jchjwubeh}(h]h ]h"]h$]h&]uh1jKhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKBhjhhubj&)}(h .. _GuC KLV:h]h}(h]h ]h"]h$]h&]j:guc-klvuh1j%hKhjhhhNj<Kubh)}(h **GuC KLV**h]jb)}(hjph]hGuC KLV}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjnubah}(h]jmah ]h"]guc klvah$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjhhjL}jjcsjN}jmjcsj<KubjL)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | **KEY** - KLV key identifier | | | | - `GuC Self Config KLVs`_ | | | | | | +-------+--------------------------------------------------------------+ | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) | +---+-------+ | |...| | | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]jd)}(hhh]ji)}(hhh](jn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jmhjubjn)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jmhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubj)}(hhh]h)}(h31:16h]h31:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jx)}(hhh]j})}(h7**KEY** - KLV key identifier - `GuC Self Config KLVs`_ h](j)}(h**KEY** - KLV key identifierh](jb)}(h**KEY**h]hKEY}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj:ubh - KLV key identifier}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhj6ubj)}(hhh]j:)}(hhh]j:)}(h`GuC Self Config KLVs`_ h]h)}(h`GuC Self Config KLVs`_h]j!5)}(hjch]hGuC Self Config KLVs}(hjehhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVsj:juh1j 5hjaj:Kubah}(h]h ]h"]h$]h&]uh1hhjVhKhj]ubah}(h]h ]h"]h$]h&]uh1j:hjZubah}(h]h ]h"]h$]h&]j[;j\;uh1j:hjVhKhjWubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1j|hjVhKhj3ubah}(h]h ]h"]h$]h&]uh1jwhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h+**LEN** - length of VALUE (in 32bit dwords)h](jb)}(h**LEN**h]hLEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh$ - length of VALUE (in 32bit dwords)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h;**VALUE** - actual value of the KLV (format depends on KEY)h](jb)}(h **VALUE**h]hVALUE}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh2 - actual value of the KLV (format depends on KEY)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjJubah}(h]h ]h"]h$]h&]uh1jhjGubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hjGh]hn}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjtubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhhjubah}(h]h ]h"]h$]h&]uh1jchjubah}(h]h ]h"]h$]h&]uh1jKhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK hjhhubj&)}(h.. _GuC Self Config KLVs:h]h}(h]h ]h"]h$]h&]j:juh1j%hKhjhhhNj<Kubh)}(h**GuC Self Config KLVs**h]jb)}(hjh]hGuC Self Config KLVs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]guc self config klvsah$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjhhjL}jjsjN}jjsj<Kubh)}(h:`GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.h](j!5)}(h `GuC KLV`_h]hGuC KLV}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGuC KLVj:jmuh1j 5hjj:Kubh keys available for use with }(hjhhhNhNubj!5)}(hHOST2GUC_SELF_CFG_h]hHOST2GUC_SELF_CFG}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameHOST2GUC_SELF_CFGj:juh1j 5hjj:Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK%hjhhubjx)}(hhh](j})}(h_`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902 Refers to 64 bit Global Gfx address of H2G `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode. h](j)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR`h](j&)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR`h]hGUC_KLV_SELF_CFG_H2G_CTB_ADDR}(hj% hhhNhNubah}(h]guc-klv-self-cfg-h2g-ctb-addrah ]h"]guc_klv_self_cfg_h2g_ctb_addrah$]h&]uh1j%hj! ubhh}(hj! hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK)hj ubh classifier)}(h0x0902h]h0x0902}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1j? hj hj> ubj)}(hhh]h)}(hRefers to 64 bit Global Gfx address of H2G `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of H2G }(hjR hhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:juh1j 5hjR j:KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hjR hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK(hjO ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj> hK)hj ubj})}(h_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR` : 0x0903 Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode. h](j)}(h+_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR`h](j&)}(h+_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR`h]h(GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR}(hj hhhNhNubah}(h](guc-klv-self-cfg-h2g-ctb-descriptor-addrah ]h"](guc_klv_self_cfg_h2g_ctb_descriptor_addrah$]h&]uh1j%hj ubhh}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK-hj ubj@ )}(h0x0903h]h0x0903}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j? hj hj ubj)}(hhh]h)}(hRefers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of H2G }(hj hhhNhNubj!5)}(h`CTB Descriptor`_h]hCTB Descriptor}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameCTB Descriptorj:juh1j 5hj j:KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK,hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hK-hj ubj})}(hs_`GUC_KLV_SELF_CFG_H2G_CTB_SIZE` : 0x0904 Refers to size of H2G `CT Buffer`_ in bytes. Should be a multiple of 4K. h](j)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE`h](j&)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE`h]hGUC_KLV_SELF_CFG_H2G_CTB_SIZE}(hj hhhNhNubah}(h]guc-klv-self-cfg-h2g-ctb-sizeah ]h"]guc_klv_self_cfg_h2g_ctb_sizeah$]h&]uh1j%hj ubhh}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK1hj ubj@ )}(h0x0904h]h0x0904}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j? hj hj ubj)}(hhh]h)}(hHRefers to size of H2G `CT Buffer`_ in bytes. Should be a multiple of 4K.h](hRefers to size of H2G }(hj hhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hj hhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:juh1j 5hj j:Kubh& in bytes. Should be a multiple of 4K.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK0hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hK1hj ubj})}(h_`GUC_KLV_SELF_CFG_G2H_CTB_ADDR` : 0x0905 Refers to 64 bit Global Gfx address of G2H `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode. h](j)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR`h](j&)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR`h]hGUC_KLV_SELF_CFG_G2H_CTB_ADDR}(hjM hhhNhNubah}(h]guc-klv-self-cfg-g2h-ctb-addrah ]h"]guc_klv_self_cfg_g2h_ctb_addrah$]h&]uh1j%hjI ubhh}(hjI hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK5hjE ubj@ )}(h0x0905h]h0x0905}(hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1j? hjE hjf ubj)}(hhh]h)}(hRefers to 64 bit Global Gfx address of G2H `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of G2H }(hjx hhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hj hhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:juh1j 5hjx j:KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hjx hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK4hju ubah}(h]h ]h"]h$]h&]uh1jhjE ubeh}(h]h ]h"]h$]h&]uh1j|hjf hK5hj ubj})}(h_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR` : 0x0906 Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode. h](j)}(h+_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR`h](j&)}(h+_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR`h]h(GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR}(hj hhhNhNubah}(h](guc-klv-self-cfg-g2h-ctb-descriptor-addrah ]h"](guc_klv_self_cfg_g2h_ctb_descriptor_addrah$]h&]uh1j%hj ubhh}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK9hj ubj@ )}(h0x0906h]h0x0906}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j? hj hj ubj)}(hhh]h)}(hRefers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of G2H }(hj hhhNhNubj!5)}(h`CTB Descriptor`_h]hCTB Descriptor}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameCTB Descriptorj:juh1j 5hj j:KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK8hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hK9hj ubj})}(hs_`GUC_KLV_SELF_CFG_G2H_CTB_SIZE` : 0x0907 Refers to size of G2H `CT Buffer`_ in bytes. Should be a multiple of 4K. h](j)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE`h](j&)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE`h]hGUC_KLV_SELF_CFG_G2H_CTB_SIZE}(hj hhhNhNubah}(h]guc-klv-self-cfg-g2h-ctb-sizeah ]h"]guc_klv_self_cfg_g2h_ctb_sizeah$]h&]uh1j%hj ubhh}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK=hj ubj@ )}(h0x0907h]h0x0907}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1j? hj hj* ubj)}(hhh]h)}(hHRefers to size of G2H `CT Buffer`_ in bytes. Should be a multiple of 4K.h](hRefers to size of G2H }(hj< hhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjD hhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:juh1j 5hj< j:Kubh& in bytes. Should be a multiple of 4K.}(hj< hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK