.sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/gpu/i915modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/gpu/i915modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/gpu/i915modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hdrm/i915 Intel GFX Driverh]hdrm/i915 Intel GFX Driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh6/var/lib/git/docbuild/linux/Documentation/gpu/i915.rsthKubh paragraph)}(hXThe drm/i915 driver supports all (with the exception of some very early models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver.h]hXThe drm/i915 driver supports all (with the exception of some very early models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hCore Driver Infrastructureh]hCore Driver Infrastructure}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hhThis section covers core driver infrastructure used by both the display and the GEM parts of the driver.h]hhThis section covers core driver infrastructure used by both the display and the GEM parts of the driver.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hRuntime Power Managementh]hRuntime Power Management}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hXrThe i915 driver supports dynamic enabling and disabling of entire hardware blocks at runtime. This is especially important on the display side where software is supposed to control many power gates manually on recent hardware, since on the GT side a lot of the power management is done by the hardware. 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Raw references are not considered during wakelock assert checks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjYubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put_raw() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put_raw() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjYubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjYubh)}(h|the wakeref cookie to pass to intel_runtime_pm_put_raw(), evaluates as True if the wakeref was acquired, or False otherwise.h]h|the wakeref cookie to pass to intel_runtime_pm_put_raw(), evaluates as True if the wakeref was acquired, or False otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjYubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_runtime_pm_get (C function)c.intel_runtime_pm_gethNtauh1jhhhhhNhNubj')}(hhh](j,)}(hCintel_wakeref_t intel_runtime_pm_get (struct intel_runtime_pm *rpm)h]j2)}(hBintel_wakeref_t intel_runtime_pm_get(struct intel_runtime_pm *rpm)h](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hjChhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjEmodnameN classnameNjXj[)}j^]ja)}jTintel_runtime_pm_getsbc.intel_runtime_pm_getasbuh1hhj<hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKubji)}(h h]h }(hjehhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj<hhhjdhKubjz)}(hintel_runtime_pm_geth]j;)}(hjah]hintel_runtime_pm_get}(hjwhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj<hhhjdhKubj)}(h(struct intel_runtime_pm *rpm)h]j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j_c.intel_runtime_pm_getasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj<hhhjdhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj8hhhjdhKubah}(h]j3ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjdhKhj5hhubj1)}(hhh]h)}(hgrab a runtime pm referenceh]hgrab a runtime pm reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hj5hhhjdhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj+jSj+jTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up. 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Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubh)}(hThis function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up.h]hThis function grabs a device-level runtime pm reference (mostly used for GEM code to ensure the GTT or GT is on) and ensures that it is powered up.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubh)}(h4the wakeref cookie to pass to intel_runtime_pm_put()h]h4the wakeref cookie to pass to intel_runtime_pm_put()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"-__intel_runtime_pm_get_if_active (C function)"c.__intel_runtime_pm_get_if_activehNtauh1jhhhhhNhNubj')}(hhh](j,)}(heintel_wakeref_t __intel_runtime_pm_get_if_active (struct intel_runtime_pm *rpm, bool ignore_usecount)h]j2)}(hdintel_wakeref_t __intel_runtime_pm_get_if_active(struct intel_runtime_pm *rpm, bool ignore_usecount)h](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jT __intel_runtime_pm_get_if_activesb"c.__intel_runtime_pm_get_if_activeasbuh1hhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj.hKubjz)}(h __intel_runtime_pm_get_if_activeh]j;)}(hj+h]h __intel_runtime_pm_get_if_active}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj=ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj.hKubj)}(h4(struct intel_runtime_pm *rpm, bool ignore_usecount)h](j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubji)}(h h]h }(hjihhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjXubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hjzhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjwubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj|modnameN classnameNjXj[)}j^]j)"c.__intel_runtime_pm_get_if_activeasbuh1hhjXubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjXubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj;)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjXubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubj)}(hbool ignore_usecounth](hdesc_sig_keyword_type)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hignore_usecounth]hignore_usecount}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj.hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj.hKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj.hKhjhhubj1)}(hhh]h)}(h/grab a runtime pm reference if device is activeh]h/grab a runtime pm reference if device is active}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj.hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj-jSj-jTjUjVuh1j&hhhhhNhNubjX)}(hX-**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``bool ignore_usecount`` get a ref even if dev->power.usage_count is 0 **Description** This function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure. If **ignore_usecount** is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it's guaranteed that the device's runtime suspend hook has been called already or that it will be called (and hence it's also guaranteed that the device's runtime resume hook will be called eventually). Any runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again. **Return** the wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.h](h)}(h**Parameters**h]jb)}(hj7h]h Parameters}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj5ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubjx)}(hhh](j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjVh]hstruct intel_runtime_pm *rpm}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjPubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhKhjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j|hjkhKhjMubj})}(hG``bool ignore_usecount`` get a ref even if dev->power.usage_count is 0 h](j)}(h``bool ignore_usecount``h]j)}(hjh]hbool ignore_usecount}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhjubj)}(hhh]h)}(h-get a ref even if dev->power.usage_count is 0h]h-get a ref even if dev->power.usage_count is 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjMubeh}(h]h ]h"]h$]h&]uh1jwhj1ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(hThis function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure.h]hThis function grabs a device-level runtime pm reference if the device is already active and ensures that it is powered up. It is illegal to try and access the HW should intel_runtime_pm_get_if_active() report failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(hXIf **ignore_usecount** is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it's guaranteed that the device's runtime suspend hook has been called already or that it will be called (and hence it's also guaranteed that the device's runtime resume hook will be called eventually).h](hIf }(hjhhhNhNubjb)}(h**ignore_usecount**h]hignore_usecount}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubhX is true, a reference will be acquired even if there is no user requiring the device to be powered up (dev->power.usage_count == 0). If the function returns false in this case then it’s guaranteed that the device’s runtime suspend hook has been called already or that it will be called (and hence it’s also guaranteed that the device’s runtime resume hook will be called eventually).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(h **Return**h]jb)}(hj!h]hReturn}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubh)}(hxthe wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.h]hxthe wakeref cookie to pass to intel_runtime_pm_put(), evaluates as True if the wakeref was acquired, or False otherwise.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chKhj1ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"*intel_runtime_pm_get_noresume (C function)c.intel_runtime_pm_get_noresumehNtauh1jhhhhhNhNubj')}(hhh](j,)}(hLintel_wakeref_t intel_runtime_pm_get_noresume (struct intel_runtime_pm *rpm)h]j2)}(hKintel_wakeref_t intel_runtime_pm_get_noresume(struct intel_runtime_pm *rpm)h](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjkmodnameN classnameNjXj[)}j^]ja)}jTintel_runtime_pm_get_noresumesbc.intel_runtime_pm_get_noresumeasbuh1hhjbhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbhhhjhMubjz)}(hintel_runtime_pm_get_noresumeh]j;)}(hjh]hintel_runtime_pm_get_noresume}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjbhhhjhMubj)}(h(struct intel_runtime_pm *rpm)h]j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_runtime_pm_get_noresumeasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hrpmh]hrpm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjbhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj^hhhjhMubah}(h]jYah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhj[hhubj1)}(hhh]h)}(hgrab a runtime pm referenceh]hgrab a runtime pm reference}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhj6hhubah}(h]h ]h"]h$]h&]uh1j0hj[hhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjQjSjQjTjUjVuh1j&hhhhhNhNubjX)}(hX@**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function grabs a device-level runtime pm reference. It will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold. Any runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again. **Return** the wakeref cookie to pass to intel_runtime_pm_put()h](h)}(h**Parameters**h]jb)}(hj[h]h Parameters}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjYubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubjx)}(hhh]j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjzh]hstruct intel_runtime_pm *rpm}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjtubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjqubah}(h]h ]h"]h$]h&]uh1jwhjUubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(h8This function grabs a device-level runtime pm reference.h]h8This function grabs a device-level runtime pm reference.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(hIt will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold.h]hIt will _not_ resume the device but instead only get an extra wakeref. Therefore it is only valid to call this functions from contexts where the device is known to be active and with another wakeref previously hold.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.h]hAny runtime pm reference obtained by this function must have a symmetric call to intel_runtime_pm_put() to release the reference again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubh)}(h4the wakeref cookie to pass to intel_runtime_pm_put()h]h4the wakeref cookie to pass to intel_runtime_pm_put()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_runtime_pm_put_raw (C function)c.intel_runtime_pm_put_rawhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hRvoid intel_runtime_pm_put_raw (struct intel_runtime_pm *rpm, intel_wakeref_t wref)h]j2)}(hQvoid intel_runtime_pm_put_raw(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j)}(hvoidh]hvoid}(hj? hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj; hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM7ubji)}(h h]h }(hjN hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj; hhhjM hM7ubjz)}(hintel_runtime_pm_put_rawh]j;)}(hintel_runtime_pm_put_rawh]hintel_runtime_pm_put_raw}(hj` hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj; hhhjM hM7ubj)}(h4(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hj| hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjx ubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjb sbc.intel_runtime_pm_put_rawasbuh1hhjx ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjx ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx ubj;)}(hrpmh]hrpm}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjx ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjt ubj)}(hintel_wakeref_t wrefh](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]j c.intel_runtime_pm_put_rawasbuh1hhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj;)}(hwrefh]hwref}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjt ubeh}(h]h ]h"]h$]h&]jjuh1jhj; hhhjM hM7ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj7 hhhjM hM7ubah}(h]j2 ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjM hM7hj4 hhubj1)}(hhh]h)}(h"release a raw runtime pm referenceh]h"release a raw runtime pm reference}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM7hjD hhubah}(h]h ]h"]h$]h&]uh1j0hj4 hhhjM hM7ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj_ jSj_ jTjUjVuh1j&hhhhhNhNubjX)}(hXz**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``intel_wakeref_t wref`` wakeref acquired for the reference that is being released **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.h](h)}(h**Parameters**h]jb)}(hji h]h Parameters}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjg ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM;hjc ubjx)}(hhh](j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hj h]hstruct intel_runtime_pm *rpm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM8hj ubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM8hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hM8hj ubj})}(hS``intel_wakeref_t wref`` wakeref acquired for the reference that is being released h](j)}(h``intel_wakeref_t wref``h]j)}(hj h]hintel_wakeref_t wref}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM9hj ubj)}(hhh]h)}(h9wakeref acquired for the reference that is being releasedh]h9wakeref acquired for the reference that is being released}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM9hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hM9hj ubeh}(h]h ]h"]h$]h&]uh1jwhjc ubh)}(h**Description**h]jb)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM;hjc ubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get_raw() and might power down the corresponding hardware block right away if this is the last reference.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM;hjc ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+intel_runtime_pm_put_unchecked (C function) c.intel_runtime_pm_put_uncheckedhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hBvoid intel_runtime_pm_put_unchecked (struct intel_runtime_pm *rpm)h]j2)}(hAvoid intel_runtime_pm_put_unchecked(struct intel_runtime_pm *rpm)h](j)}(hvoidh]hvoid}(hjA hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj= hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMFubji)}(h h]h }(hjP hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj= hhhjO hMFubjz)}(hintel_runtime_pm_put_uncheckedh]j;)}(hintel_runtime_pm_put_uncheckedh]hintel_runtime_pm_put_unchecked}(hjb hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj^ ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj= hhhjO hMFubj)}(h(struct intel_runtime_pm *rpm)h]j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hj~ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz ubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjd sb c.intel_runtime_pm_put_uncheckedasbuh1hhjz ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz ubj;)}(hrpmh]hrpm}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjz ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjv ubah}(h]h ]h"]h$]h&]jjuh1jhj= hhhjO hMFubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj9 hhhjO hMFubah}(h]j4 ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjO hMFhj6 hhubj1)}(hhh]h)}(h)release an unchecked runtime pm referenceh]h)release an unchecked runtime pm reference}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMFhj hhubah}(h]h ]h"]h$]h&]uh1j0hj6 hhhjO hMFubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference. This function exists only for historical reasons and should be avoided in new code, as the correctness of its use cannot be checked. Always use intel_runtime_pm_put() instead.h](h)}(h**Parameters**h]jb)}(hj# h]h Parameters}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj! ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMJhj ubjx)}(hhh]j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjB h]hstruct intel_runtime_pm *rpm}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMGhj< ubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjW hMGhjX ubah}(h]h ]h"]h$]h&]uh1jhj< ubeh}(h]h ]h"]h$]h&]uh1j|hjW hMGhj9 ubah}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hj} h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj{ ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMIhj ubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMIhj ubh)}(hThis function exists only for historical reasons and should be avoided in new code, as the correctness of its use cannot be checked. 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Always use intel_runtime_pm_put() instead.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_runtime_pm_put (C function)c.intel_runtime_pm_puthNtauh1jhhhhhNhNubj')}(hhh](j,)}(hNvoid intel_runtime_pm_put (struct intel_runtime_pm *rpm, intel_wakeref_t wref)h]j2)}(hMvoid intel_runtime_pm_put(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMXubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj hhhj hMXubjz)}(hintel_runtime_pm_puth]j;)}(hintel_runtime_pm_puth]hintel_runtime_pm_put}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj hhhj hMXubj)}(h4(struct intel_runtime_pm *rpm, intel_wakeref_t wref)h](j)}(hstruct intel_runtime_pm *rpmh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hintel_runtime_pmh]hintel_runtime_pm}(hj, hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj) ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj. modnameN classnameNjXj[)}j^]ja)}jTj sbc.intel_runtime_pm_putasbuh1hhj ubji)}(h h]h }(hjL hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hjZ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hrpmh]hrpm}(hjg hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(hintel_wakeref_t wrefh](h)}(hhh]j;)}(hintel_wakeref_th]hintel_wakeref_t}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jH c.intel_runtime_pm_putasbuh1hhj| ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj| ubj;)}(hwrefh]hwref}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj| ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubeh}(h]h ]h"]h$]h&]jjuh1jhj hhhj hMXubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhj hMXubah}(h]j ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj hMXhj hhubj1)}(hhh]h)}(hrelease a runtime pm referenceh]hrelease a runtime pm reference}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMXhj hhubah}(h]h ]h"]h$]h&]uh1j0hj hhhj hMXubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhhhNhNubjX)}(hXv**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure ``intel_wakeref_t wref`` wakeref acquired for the reference that is being released **Description** This function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM\hj ubjx)}(hhh](j})}(h@``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure h](j)}(h ``struct intel_runtime_pm *rpm``h]j)}(hjh]hstruct intel_runtime_pm *rpm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMYhjubj)}(hhh]h)}(hthe intel_runtime_pm structureh]hthe intel_runtime_pm structure}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMYhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj/hMYhjubj})}(hS``intel_wakeref_t wref`` wakeref acquired for the reference that is being released h](j)}(h``intel_wakeref_t wref``h]j)}(hjSh]hintel_wakeref_t wref}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMZhjMubj)}(hhh]h)}(h9wakeref acquired for the reference that is being releasedh]h9wakeref acquired for the reference that is being released}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMZhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j|hjhhMZhjubeh}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM\hj ubh)}(hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.h]hThis function drops the device-level runtime pm reference obtained by intel_runtime_pm_get() and might power down the corresponding hardware block right away if this is the last reference.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chM\hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_runtime_pm_enable (C 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}(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hrpmh]hrpm}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMgubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMgubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMghjhhubj1)}(hhh]h)}(henable runtime pmh]henable runtime pm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMghjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMgubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hXC**Parameters** ``struct intel_runtime_pm *rpm`` the intel_runtime_pm structure **Description** This function enables runtime pm at the end of the driver load sequence. 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That is done by intel_power_domains_enable().h]hNote that this function does currently not enable runtime pm for the subordinate display power domains. That is done by intel_power_domains_enable().}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.chMlhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_uncore_forcewake_get (C function)c.intel_uncore_forcewake_gethNtauh1jhhhhhNhNubj')}(hhh](j,)}(h`void intel_uncore_forcewake_get (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(h_void intel_uncore_forcewake_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj_hhhjqhMubjz)}(hintel_uncore_forcewake_geth]j;)}(hintel_uncore_forcewake_geth]hintel_uncore_forcewake_get}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj_hhhjqhMubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_uncore_forcewake_getasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(henumh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hj1hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj3modnameN classnameNjXj[)}j^]jc.intel_uncore_forcewake_getasbuh1hhjubji)}(h h]h }(hjOhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h fw_domainsh]h fw_domains}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhj_hhhjqhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj[hhhjqhMubah}(h]jVah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjqhMhjXhhubj1)}(hhh]h)}(h grab forcewake domain referencesh]h grab forcewake domain references}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjXhhhjqhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to get reference on **Description** This function can be used get GT's forcewake domain references. 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Usually caller wants all the domains to be kept awake so the **fw_domains** would be then FORCEWAKE_ALL.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hL``enum forcewake_domains fw_domains`` forcewake domains to get reference on h](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hjh]h!enum forcewake_domains fw_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(h%forcewake domains to get reference onh]h%forcewake domains to get reference on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hj<h]h Description}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj:ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.c-hMhjubh)}(hXThis function can be used get GT's forcewake domain references. Normal register access will handle the forcewake domains automatically. However if some sequence requires the GT to not power down a particular forcewake domains this function should be called at the beginning of the sequence. And subsequently the reference should be dropped by symmetric call to intel_unforce_forcewake_put(). Usually caller wants all the domains to be kept awake so the **fw_domains** would be then FORCEWAKE_ALL.h](hXThis function can be used get GT’s forcewake domain references. Normal register access will handle the forcewake domains automatically. However if some sequence requires the GT to not power down a particular forcewake domains this function should be called at the beginning of the sequence. And subsequently the reference should be dropped by symmetric call to intel_unforce_forcewake_put(). Usually caller wants all the domains to be kept awake so the }(hjRhhhNhNubjb)}(h**fw_domains**h]h fw_domains}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjRubh would be then FORCEWAKE_ALL.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_uncore_forcewake_user_get (C function)!c.intel_uncore_forcewake_user_gethNtauh1jhhhhhNhNubj')}(hhh](j,)}(hBvoid intel_uncore_forcewake_user_get (struct intel_uncore *uncore)h]j2)}(hAvoid intel_uncore_forcewake_user_get(struct intel_uncore *uncore)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_uncore_forcewake_user_geth]j;)}(hintel_uncore_forcewake_user_geth]hintel_uncore_forcewake_user_get}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct intel_uncore *uncore)h]j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb!c.intel_uncore_forcewake_user_getasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hj)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h&claim forcewake on behalf of userspaceh]h&claim forcewake on behalf of userspace}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjPhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjkjSjkjTjUjVuh1j&hhhhhNhNubjX)}(hX **Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure **Description** This function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace's bypass.h](h)}(h**Parameters**h]jb)}(hjuh]h Parameters}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjsubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjoubjx)}(hhh]j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjoubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjoubh)}(hThis function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace's bypass.h]hThis function is a wrapper around intel_uncore_forcewake_get() to acquire the GT powerwell and in the process disable our debugging for the duration of userspace’s bypass.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjoubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_uncore_forcewake_user_put (C function)!c.intel_uncore_forcewake_user_puthNtauh1jhhhhhNhNubj')}(hhh](j,)}(hBvoid intel_uncore_forcewake_user_put (struct intel_uncore *uncore)h]j2)}(hAvoid intel_uncore_forcewake_user_put(struct intel_uncore *uncore)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hj#hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj"hMubjz)}(hintel_uncore_forcewake_user_puth]j;)}(hintel_uncore_forcewake_user_puth]hintel_uncore_forcewake_user_put}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj1ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj"hMubj)}(h(struct intel_uncore *uncore)h]j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjMubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hjohhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjlubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjqmodnameN classnameNjXj[)}j^]ja)}jTj7sb!c.intel_uncore_forcewake_user_putasbuh1hhjMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubj;)}(huncoreh]huncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjMubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjIubah}(h]h ]h"]h$]h&]jjuh1jhjhhhj"hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhj"hMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj"hMhj hhubj1)}(hhh]h)}(h(release forcewake on behalf of userspaceh]h(release forcewake on behalf of userspace}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj hhhj"hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(h**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure **Description** This function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubjx)}(hhh]j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj*hMhj ubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjPh]h Description}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubh)}(hThis function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.h]hThis function complements intel_uncore_forcewake_user_get() and releases the GT powerwell taken on behalf of the userspace bypass.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"/intel_uncore_forcewake_get__locked (C function)$c.intel_uncore_forcewake_get__lockedhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hhvoid intel_uncore_forcewake_get__locked (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(hgvoid intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(h"intel_uncore_forcewake_get__lockedh]j;)}(h"intel_uncore_forcewake_get__lockedh]h"intel_uncore_forcewake_get__locked}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb$c.intel_uncore_forcewake_get__lockedasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(hjh]henum}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@ubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hjbhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjdmodnameN classnameNjXj[)}j^]j $c.intel_uncore_forcewake_get__lockedasbuh1hhj@ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@ubj;)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h grab forcewake domain referencesh]h grab forcewake domain references}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hX3**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to get reference on **Description** See intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hL``enum forcewake_domains fw_domains`` forcewake domains to get reference on h](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hj2h]h!enum forcewake_domains fw_domains}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhj,ubj)}(hhh]h)}(h%forcewake domains to get reference onh]h%forcewake domains to get reference on}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjHubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1j|hjGhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjmh]h Description}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jahjkubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubh)}(hSee intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h]hSee intel_uncore_forcewake_get(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_uncore_forcewake_put (C function)c.intel_uncore_forcewake_puthNtauh1jhhhhhNhNubj')}(hhh](j,)}(h`void intel_uncore_forcewake_put (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(h_void intel_uncore_forcewake_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_uncore_forcewake_puth]j;)}(hintel_uncore_forcewake_puth]hintel_uncore_forcewake_put}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_uncore_forcewake_putasbuh1hhjubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hjHhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(hjh]henum}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubji)}(h h]h }(hjnhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]ubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j)c.intel_uncore_forcewake_putasbuh1hhj]ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]ubj;)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj]ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h$release a forcewake domain referenceh]h$release a forcewake domain reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to put references **Description** This function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hjh]hstruct intel_uncore *uncore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hMhj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj+hMhj ubj})}(hJ``enum forcewake_domains fw_domains`` forcewake domains to put references h](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hjOh]h!enum forcewake_domains fw_domains}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjIubj)}(hhh]h)}(h#forcewake domains to put referencesh]h#forcewake domains to put references}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjeubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1j|hjdhMhj ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubh)}(hoThis function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().h]hoThis function drops the device-level forcewakes for specified domains obtained by intel_uncore_forcewake_get().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_uncore_forcewake_flush (C function)c.intel_uncore_forcewake_flushhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hbvoid intel_uncore_forcewake_flush (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(havoid intel_uncore_forcewake_flush(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM3ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM3ubjz)}(hintel_uncore_forcewake_flushh]j;)}(hintel_uncore_forcewake_flushh]hintel_uncore_forcewake_flush}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM3ubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj*hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj,modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_uncore_forcewake_flushasbuh1hhjubji)}(h h]h }(hjJhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hjehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(hjh]henum}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jFc.intel_uncore_forcewake_flushasbuh1hhjzubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzubj;)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM3ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM3ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM3hjhhubj1)}(hhh]h)}(hflush the delayed releaseh]hflush the delayed release}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM3hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM3ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhhhNhNubjX)}(h**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to flushh](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM7hjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hj3h]hstruct intel_uncore *uncore}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM4hj-ubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhM4hjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1j|hjHhM4hj*ubj})}(h@``enum forcewake_domains fw_domains`` forcewake domains to flushh](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hjlh]h!enum forcewake_domains fw_domains}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM6hjfubj)}(hhh]h)}(hforcewake domains to flushh]hforcewake domains to flush}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM5hjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1j|hjhM6hj*ubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"/intel_uncore_forcewake_put__locked (C function)$c.intel_uncore_forcewake_put__lockedhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hhvoid intel_uncore_forcewake_put__locked (struct intel_uncore *uncore, enum forcewake_domains fw_domains)h]j2)}(hgvoid intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMIubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMIubjz)}(h"intel_uncore_forcewake_put__lockedh]j;)}(h"intel_uncore_forcewake_put__lockedh]h"intel_uncore_forcewake_put__locked}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMIubj)}(h@(struct intel_uncore *uncore, enum forcewake_domains fw_domains)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj#modnameN classnameNjXj[)}j^]ja)}jTjsb$c.intel_uncore_forcewake_put__lockedasbuh1hhjubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hj\hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h!enum forcewake_domains fw_domainsh](j)}(hjh]henum}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j=$c.intel_uncore_forcewake_put__lockedasbuh1hhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubj;)}(h fw_domainsh]h fw_domains}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjqubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMIubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMIubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMIhjhhubj1)}(hhh]h)}(h#release forcewake domain referencesh]h#release forcewake domain references}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMIhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMIubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhhhNhNubjX)}(hX1**Parameters** ``struct intel_uncore *uncore`` the intel_uncore structure ``enum forcewake_domains fw_domains`` forcewake domains to put references **Description** See intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMMhjubjx)}(hhh](j})}(h;``struct intel_uncore *uncore`` the intel_uncore structure h](j)}(h``struct intel_uncore *uncore``h]j)}(hj*h]hstruct intel_uncore *uncore}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMJhj$ubj)}(hhh]h)}(hthe intel_uncore structureh]hthe intel_uncore structure}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMJhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1j|hj?hMJhj!ubj})}(hJ``enum forcewake_domains fw_domains`` forcewake domains to put references h](j)}(h%``enum forcewake_domains fw_domains``h]j)}(hjch]h!enum forcewake_domains fw_domains}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMKhj]ubj)}(hhh]h)}(h#forcewake domains to put referencesh]h#forcewake domains to put references}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMKhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1j|hjxhMKhj!ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMMhjubh)}(hSee intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.h]hSee intel_uncore_forcewake_put(). This variant places the onus on the caller to explicitly handle the dev_priv->uncore.lock spinlock.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chMMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")__intel_wait_for_register_fw (C function)c.__intel_wait_for_register_fwhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hint __intel_wait_for_register_fw (struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h]j2)}(hint __intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(h__intel_wait_for_register_fwh]j;)}(h__intel_wait_for_register_fwh]h__intel_wait_for_register_fw}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj@modnameN classnameNjXj[)}j^]ja)}jTjsbc.__intel_wait_for_register_fwasbuh1hhjubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(huncoreh]huncore}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hi915_reg_t regh](h)}(hhh]j;)}(h i915_reg_th]h i915_reg_t}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jZc.__intel_wait_for_register_fwasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hregh]hreg}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu32 maskh](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jZc.__intel_wait_for_register_fwasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hmaskh]hmask}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj'modnameN classnameNjXj[)}j^]jZc.__intel_wait_for_register_fwasbuh1hhjubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hvalueh]hvalue}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int fast_timeout_ush](j)}(hunsignedh]hunsigned}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubji)}(h h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfubj;)}(hfast_timeout_ush]hfast_timeout_us}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int slow_timeout_msh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hslow_timeout_msh]hslow_timeout_ms}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu32 *out_valueh](h)}(hhh]j;)}(hu32h]hu32}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jZc.__intel_wait_for_register_fwasbuh1hhj ubji)}(h h]h }(hj- hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj; hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(h out_valueh]h out_value}(hjH hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h*wait until register matches expected stateh]h*wait until register matches expected state}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hjo hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhhhNhNubjX)}(hXr**Parameters** ``struct intel_uncore *uncore`` the struct intel_uncore ``i915_reg_t reg`` the register to read ``u32 mask`` mask to apply to register value ``u32 value`` expected value ``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait ``unsigned int slow_timeout_ms`` slow timeout in millisecond ``u32 *out_value`` optional placeholder to hold registry value **Description** This routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until :: (intel_uncore_read_fw(uncore, reg) & mask) == value Otherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds. Note that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow). **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubjx)}(hhh](j})}(h8``struct intel_uncore *uncore`` the struct intel_uncore h](j)}(h``struct intel_uncore *uncore``h]j)}(hj h]hstruct intel_uncore *uncore}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubj)}(hhh]h)}(hthe struct intel_uncoreh]hthe struct intel_uncore}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hM hj ubj})}(h(``i915_reg_t reg`` the register to read h](j)}(h``i915_reg_t reg``h]j)}(hj h]hi915_reg_t reg}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubj)}(hhh]h)}(hthe register to readh]hthe register to read}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj!hM hj ubj})}(h-``u32 mask`` mask to apply to register value h](j)}(h ``u32 mask``h]j)}(hj%!h]hu32 mask}(hj'!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hj>!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:!hM hj;!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j|hj:!hM hj ubj})}(h``u32 value`` expected value h](j)}(h ``u32 value``h]j)}(hj^!h]h u32 value}(hj`!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hjX!ubj)}(hhh]h)}(hexpected valueh]hexpected value}(hjw!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs!hM hjt!ubah}(h]h ]h"]h$]h&]uh1jhjX!ubeh}(h]h ]h"]h$]h&]uh1j|hjs!hM hj ubj})}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j)}(h ``unsigned int fast_timeout_us``h]j)}(hj!h]hunsigned int fast_timeout_us}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j|hj!hM hj ubj})}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j)}(h ``unsigned int slow_timeout_ms``h]j)}(hj!h]hunsigned int slow_timeout_ms}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj!ubj)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j|hj!hM hj ubj})}(h?``u32 *out_value`` optional placeholder to hold registry value h](j)}(h``u32 *out_value``h]j)}(hj "h]hu32 *out_value}(hj "hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj"ubj)}(hhh]h)}(h+optional placeholder to hold registry valueh]h+optional placeholder to hold registry value}(hj""hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj"hM hj ubeh}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjD"h]h Description}(hjF"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjB"ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hjZ"hhhNhNubjb)}(h**reg**h]hreg}(hjb"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZ"ubh contains the expected }(hjZ"hhhNhNubjb)}(h **value**h]hvalue}(hjt"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZ"ubh after applying the }(hjZ"hhhNhNubjb)}(h**mask**h]hmask}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZ"ubh, i.e. it waits until}(hjZ"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh literal_block)}(h3(intel_uncore_read_fw(uncore, reg) & mask) == valueh]h3(intel_uncore_read_fw(uncore, reg) & mask) == value}hj"sbah}(h]h ]h"]h$]h&]jjuh1j"h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(hOtherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds.h](h'Otherwise, the wait will timeout after }(hj"hhhNhNubjb)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubh" milliseconds. For atomic context }(hj"hhhNhNubjb)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubh must be zero and }(hj"hhhNhNubjb)}(h**fast_timeout_us**h]hfast_timeout_us}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubh. must be not larger than 20,0000 microseconds.}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(hNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow).h]hNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits. See intel_wait_for_register() if you wish to wait without holding forcewake for the duration (i.e. you expect the wait to be slow).}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(h **Return**h]jb)}(hj#h]hReturn}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&__intel_wait_for_register (C function)c.__intel_wait_for_registerhNtauh1jhhhhhNhNubj')}(hhh](j,)}(hint __intel_wait_for_register (struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h]j2)}(hint __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j)}(hinth]hint}(hjK#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG#hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM ubji)}(h h]h }(hjZ#hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjG#hhhjY#hM ubjz)}(h__intel_wait_for_registerh]j;)}(h__intel_wait_for_registerh]h__intel_wait_for_register}(hjl#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjh#ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjG#hhhjY#hM ubj)}(h(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubji)}(h h]h }(hj#hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj#ubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj#modnameN classnameNjXj[)}j^]ja)}jTjn#sbc.__intel_wait_for_registerasbuh1hhj#ubji)}(h h]h }(hj#hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj#ubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj;)}(huncoreh]huncore}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hi915_reg_t regh](h)}(hhh]j;)}(h i915_reg_th]h i915_reg_t}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj#modnameN classnameNjXj[)}j^]j#c.__intel_wait_for_registerasbuh1hhj#ubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj#ubj;)}(hregh]hreg}(hj)$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hu32 maskh](h)}(hhh]j;)}(hu32h]hu32}(hjE$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjB$ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjG$modnameN classnameNjXj[)}j^]j#c.__intel_wait_for_registerasbuh1hhj>$ubji)}(h h]h }(hjc$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>$ubj;)}(hmaskh]hmask}(hjq$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>$ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj$modnameN classnameNjXj[)}j^]j#c.__intel_wait_for_registerasbuh1hhj$ubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubj;)}(hvalueh]hvalue}(hj$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hunsigned int fast_timeout_ush](j)}(hunsignedh]hunsigned}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubj)}(hinth]hint}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubji)}(h h]h }(hj$hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubj;)}(hfast_timeout_ush]hfast_timeout_us}(hj %hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hunsigned int slow_timeout_msh](j)}(hunsignedh]hunsigned}(hj#%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubji)}(h h]h }(hj1%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj%ubj)}(hinth]hint}(hj?%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubji)}(h h]h }(hjM%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj%ubj;)}(hslow_timeout_msh]hslow_timeout_ms}(hj[%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubj)}(hu32 *out_valueh](h)}(hhh]j;)}(hu32h]hu32}(hjw%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjt%ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjy%modnameN classnameNjXj[)}j^]j#c.__intel_wait_for_registerasbuh1hhjp%ubji)}(h h]h }(hj%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjp%ubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp%ubj;)}(h out_valueh]h out_value}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjp%ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#ubeh}(h]h ]h"]h$]h&]jjuh1jhjG#hhhjY#hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjC#hhhjY#hM ubah}(h]j>#ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjY#hM hj@#hhubj1)}(hhh]h)}(h*wait until register matches expected stateh]h*wait until register matches expected state}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%hhubah}(h]h ]h"]h$]h&]uh1j0hj@#hhhjY#hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj%jSj%jTjUjVuh1j&hhhhhNhNubjX)}(hX**Parameters** ``struct intel_uncore *uncore`` the struct intel_uncore ``i915_reg_t reg`` the register to read ``u32 mask`` mask to apply to register value ``u32 value`` expected value ``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait ``unsigned int slow_timeout_ms`` slow timeout in millisecond ``u32 *out_value`` optional placeholder to hold registry value **Description** This routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until :: (intel_uncore_read(uncore, reg) & mask) == value Otherwise, the wait will timeout after **timeout_ms** milliseconds. **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]jb)}(hj%h]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj%ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubjx)}(hhh](j})}(h8``struct intel_uncore *uncore`` the struct intel_uncore h](j)}(h``struct intel_uncore *uncore``h]j)}(hj&h]hstruct intel_uncore *uncore}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh]h)}(hthe struct intel_uncoreh]hthe struct intel_uncore}(hj4&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0&hM hj1&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hj0&hM hj&ubj})}(h(``i915_reg_t reg`` the register to read h](j)}(h``i915_reg_t reg``h]j)}(hjT&h]hi915_reg_t reg}(hjV&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hjN&ubj)}(hhh]h)}(hthe register to readh]hthe register to read}(hjm&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji&hM hjj&ubah}(h]h ]h"]h$]h&]uh1jhjN&ubeh}(h]h ]h"]h$]h&]uh1j|hji&hM hj&ubj})}(h-``u32 mask`` mask to apply to register value h](j)}(h ``u32 mask``h]j)}(hj&h]hu32 mask}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hM hj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hj&hM hj&ubj})}(h``u32 value`` expected value h](j)}(h ``u32 value``h]j)}(hj&h]h u32 value}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh]h)}(hexpected valueh]hexpected value}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hM hj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hj&hM hj&ubj})}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j)}(h ``unsigned int fast_timeout_us``h]j)}(hj&h]hunsigned int fast_timeout_us}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj&ubj)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM hj'ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hj'hM hj&ubj})}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j)}(h ``unsigned int slow_timeout_ms``h]j)}(hj8'h]hunsigned int slow_timeout_ms}(hj:'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6'ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj2'ubj)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hjQ'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM'hM hjN'ubah}(h]h ]h"]h$]h&]uh1jhj2'ubeh}(h]h ]h"]h$]h&]uh1j|hjM'hM hj&ubj})}(h?``u32 *out_value`` optional placeholder to hold registry value h](j)}(h``u32 *out_value``h]j)}(hjq'h]hu32 *out_value}(hjs'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo'ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hjk'ubj)}(hhh]h)}(h+optional placeholder to hold registry valueh]h+optional placeholder to hold registry value}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM hj'ubah}(h]h ]h"]h$]h&]uh1jhjk'ubeh}(h]h ]h"]h$]h&]uh1j|hj'hM hj&ubeh}(h]h ]h"]h$]h&]uh1jwhj%ubh)}(h**Description**h]jb)}(hj'h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hj'hhhNhNubjb)}(h**reg**h]hreg}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubh contains the expected }(hj'hhhNhNubjb)}(h **value**h]hvalue}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubh after applying the }(hj'hhhNhNubjb)}(h**mask**h]hmask}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubh, i.e. it waits until}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubj")}(h0(intel_uncore_read(uncore, reg) & mask) == valueh]h0(intel_uncore_read(uncore, reg) & mask) == value}hj(sbah}(h]h ]h"]h$]h&]jjuh1j"h\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubh)}(hCOtherwise, the wait will timeout after **timeout_ms** milliseconds.h](h'Otherwise, the wait will timeout after }(hj(hhhNhNubjb)}(h**timeout_ms**h]h timeout_ms}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj(ubh milliseconds.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubh)}(h **Return**h]jb)}(hj9(h]hReturn}(hj;(hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj7(ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hjO(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM hj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+intel_uncore_forcewake_for_reg (C function) c.intel_uncore_forcewake_for_reghNtauh1jhhhhhNhNubj')}(hhh](j,)}(htenum forcewake_domains intel_uncore_forcewake_for_reg (struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h]j2)}(hsenum forcewake_domains intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h](j)}(hjh]henum}(hj~(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz(hhh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM* ubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz(hhhj(hM* ubh)}(hhh]j;)}(hforcewake_domainsh]hforcewake_domains}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj(modnameN classnameNjXj[)}j^]ja)}jTintel_uncore_forcewake_for_regsb c.intel_uncore_forcewake_for_regasbuh1hhjz(hhhj(hM* ubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz(hhhj(hM* ubjz)}(hintel_uncore_forcewake_for_regh]j;)}(hj(h]hintel_uncore_forcewake_for_reg}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjz(hhhj(hM* ubj)}(h>(struct intel_uncore *uncore, i915_reg_t reg, unsigned int op)h](j)}(hstruct intel_uncore *uncoreh](j)}(hjh]hstruct}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj(ubh)}(hhh]j;)}(h intel_uncoreh]h intel_uncore}(hj )hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj )modnameN classnameNjXj[)}j^]j( c.intel_uncore_forcewake_for_regasbuh1hhj(ubji)}(h h]h }(hj')hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj(ubj)}(hjh]h*}(hj5)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubj;)}(huncoreh]huncore}(hjB)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(ubj)}(hi915_reg_t regh](h)}(hhh]j;)}(h i915_reg_th]h i915_reg_t}(hj^)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj[)ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj`)modnameN classnameNjXj[)}j^]j( c.intel_uncore_forcewake_for_regasbuh1hhjW)ubji)}(h h]h }(hj|)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjW)ubj;)}(hregh]hreg}(hj)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjW)ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(ubj)}(hunsigned int oph](j)}(hunsignedh]hunsigned}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)ubj)}(hinth]hint}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)ubj;)}(hoph]hop}(hj)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(ubeh}(h]h ]h"]h$]h&]jjuh1jhjz(hhhj(hM* ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjv(hhhj(hM* ubah}(h]jq(ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj(hM* hjs(hhubj1)}(hhh]h)}(h7which forcewake domains are needed to access a registerh]h7which forcewake domains are needed to access a register}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM* hj*hhubah}(h]h ]h"]h$]h&]uh1j0hjs(hhhj(hM* ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj*jSj*jTjUjVuh1j&hhhhhNhNubjX)}(hXI**Parameters** ``struct intel_uncore *uncore`` pointer to struct intel_uncore ``i915_reg_t reg`` register in question ``unsigned int op`` operation bitmask of FW_REG_READ and/or FW_REG_WRITE **Description** Returns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors. **NOTE** On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.h](h)}(h**Parameters**h]jb)}(hj'*h]h Parameters}(hj)*hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj%*ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM. hj!*ubjx)}(hhh](j})}(h?``struct intel_uncore *uncore`` pointer to struct intel_uncore h](j)}(h``struct intel_uncore *uncore``h]j)}(hjF*h]hstruct intel_uncore *uncore}(hjH*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD*ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM, hj@*ubj)}(hhh]h)}(hpointer to struct intel_uncoreh]hpointer to struct intel_uncore}(hj_*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[*hM, hj\*ubah}(h]h ]h"]h$]h&]uh1jhj@*ubeh}(h]h ]h"]h$]h&]uh1j|hj[*hM, hj=*ubj})}(h(``i915_reg_t reg`` register in question h](j)}(h``i915_reg_t reg``h]j)}(hj*h]hi915_reg_t reg}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}*ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM- hjy*ubj)}(hhh]h)}(hregister in questionh]hregister in question}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM- hj*ubah}(h]h ]h"]h$]h&]uh1jhjy*ubeh}(h]h ]h"]h$]h&]uh1j|hj*hM- hj=*ubj})}(hI``unsigned int op`` operation bitmask of FW_REG_READ and/or FW_REG_WRITE h](j)}(h``unsigned int op``h]j)}(hj*h]hunsigned int op}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM. hj*ubj)}(hhh]h)}(h4operation bitmask of FW_REG_READ and/or FW_REG_WRITEh]h4operation bitmask of FW_REG_READ and/or FW_REG_WRITE}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM. hj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1j|hj*hM. hj=*ubeh}(h]h ]h"]h$]h&]uh1jwhj!*ubh)}(h**Description**h]jb)}(hj*h]h Description}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj*ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM0 hj!*ubh)}(hReturns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors.h]hReturns a set of forcewake domains required to be taken with for example intel_uncore_forcewake_get for the specified register to be accessible in the specified mode (read, write or read/write) with raw mmio accessors.}(hj +hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM0 hj!*ubh)}(h**NOTE**h]jb)}(hj+h]hNOTE}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj+ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM4 hj!*ubh)}(hOn Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.h]hOn Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the callers to do FIFO management on their own or risk losing writes.}(hj0+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/i915:25: ./drivers/gpu/drm/i915/intel_uncore.chM4 hj!*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhhhhhNhNubeh}(h]runtime-power-managementah ]h"]runtime power managementah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hInterrupt Handlingh]hInterrupt Handling}(hjQ+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjN+hhhhhKubh)}(hThese functions provide the basic support for enabling and disabling the interrupt handling support. There's a lot more functionality in i915_irq.c and related files, but that will be described in separate chapters.h]hThese functions provide the basic support for enabling and disabling the interrupt handling support. There’s a lot more functionality in i915_irq.c and related files, but that will be described in separate chapters.}(hj_+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:31: ./drivers/gpu/drm/i915/i915_irq.chK7hjN+hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_irq_init (C function)c.intel_irq_inithNtauh1jhjN+hhhNhNubj')}(hhh](j,)}(h7void intel_irq_init (struct drm_i915_private *dev_priv)h]j2)}(h6void intel_irq_init(struct drm_i915_private *dev_priv)h](j)}(hvoidh]hvoid}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chM`ubji)}(h h]h }(hj+hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+hhhj+hM`ubjz)}(hintel_irq_inith]j;)}(hintel_irq_inith]hintel_irq_init}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj+hhhj+hM`ubj)}(h#(struct drm_i915_private *dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubji)}(h h]h }(hj+hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj+modnameN classnameNjXj[)}j^]ja)}jTj+sbc.intel_irq_initasbuh1hhj+ubji)}(h h]h }(hj,hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+ubj)}(hjh]h*}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubj;)}(hdev_privh]hdev_priv}(hj,hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+ubah}(h]h ]h"]h$]h&]jjuh1jhj+hhhj+hM`ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj+hhhj+hM`ubah}(h]jz+ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj+hM`hj|+hhubj1)}(hhh]h)}(hinitializes irq supporth]hinitializes irq support}(hjG,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chM`hjD,hhubah}(h]h ]h"]h$]h&]uh1j0hj|+hhhj+hM`ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj_,jSj_,jTjUjVuh1j&hhhjN+hNhNubjX)}(h**Parameters** ``struct drm_i915_private *dev_priv`` i915 device instance **Description** This function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.h](h)}(h**Parameters**h]jb)}(hji,h]h Parameters}(hjk,hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjg,ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMdhjc,ubjx)}(hhh]j})}(h;``struct drm_i915_private *dev_priv`` i915 device instance h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hj,h]h!struct drm_i915_private *dev_priv}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMahj,ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMahj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1j|hj,hMahj,ubah}(h]h ]h"]h$]h&]uh1jwhjc,ubh)}(h**Description**h]jb)}(hj,h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMchjc,ubh)}(hThis function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.h]hThis function initializes all the irq support including work items, timers and all the vtables. It does not setup the interrupt itself though.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:34: ./drivers/gpu/drm/i915/i915_irq.chMchjc,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjN+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_irq_suspend (C function)c.intel_irq_suspendhNtauh1jhjN+hhhNhNubj')}(hhh](j,)}(h6void intel_irq_suspend (struct drm_i915_private *i915)h]j2)}(h5void intel_irq_suspend(struct drm_i915_private *i915)h](j)}(hvoidh]hvoid}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj-hhhj-hMubjz)}(hintel_irq_suspendh]j;)}(hintel_irq_suspendh]hintel_irq_suspend}(hj)-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%-ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj-hhhj-hMubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjE-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA-ubji)}(h h]h }(hjR-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjA-ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjc-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`-ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetje-modnameN classnameNjXj[)}j^]ja)}jTj+-sbc.intel_irq_suspendasbuh1hhjA-ubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjA-ubj)}(hjh]h*}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA-ubj;)}(hi915h]hi915}(hj-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjA-ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=-ubah}(h]h ]h"]h$]h&]jjuh1jhj-hhhj-hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj-hhhj-hMubah}(h]j,ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj-hMhj,hhubj1)}(hhh]h)}(hSuspend interruptsh]hSuspend interrupts}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj-hhubah}(h]h ]h"]h$]h&]uh1j0hj,hhhj-hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj-jSj-jTjUjVuh1j&hhhjN+hNhNubjX)}(h**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** This function is used to disable interrupts at runtime.h](h)}(h**Parameters**h]jb)}(hj-h]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubjx)}(hhh]j})}(h7``struct drm_i915_private *i915`` i915 device instance h](j)}(h!``struct drm_i915_private *i915``h]j)}(hj .h]hstruct drm_i915_private *i915}(hj .hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj.ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj".hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hj.hMhj.ubah}(h]h ]h"]h$]h&]uh1jwhj-ubh)}(h**Description**h]jb)}(hjD.h]h Description}(hjF.hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjB.ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubh)}(h7This function is used to disable interrupts at runtime.h]h7This function is used to disable interrupts at runtime.}(hjZ.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:37: ./drivers/gpu/drm/i915/i915_irq.chMhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjN+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_irq_resume (C function)c.intel_irq_resumehNtauh1jhjN+hhhNhNubj')}(hhh](j,)}(h5void intel_irq_resume (struct drm_i915_private *i915)h]j2)}(h4void intel_irq_resume(struct drm_i915_private *i915)h](j)}(hvoidh]hvoid}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hhhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.hhhj.hMubjz)}(hintel_irq_resumeh]j;)}(hintel_irq_resumeh]hintel_irq_resume}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj.hhhj.hMubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj.modnameN classnameNjXj[)}j^]ja)}jTj.sbc.intel_irq_resumeasbuh1hhj.ubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubj)}(hjh]h*}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubj;)}(hi915h]hi915}(hj/hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj.ubah}(h]h ]h"]h$]h&]jjuh1jhj.hhhj.hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj.hhhj.hMubah}(h]j|.ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj.hMhj~.hhubj1)}(hhh]h)}(hResume interruptsh]hResume interrupts}(hjI/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhjF/hhubah}(h]h ]h"]h$]h&]uh1j0hj~.hhhj.hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRja/jSja/jTjUjVuh1j&hhhjN+hNhNubjX)}(h**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** This function is used to enable interrupts at runtime.h](h)}(h**Parameters**h]jb)}(hjk/h]h Parameters}(hjm/hhhNhNubah}(h]h ]h"]h$]h&]uh1jahji/ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhje/ubjx)}(hhh]j})}(h7``struct drm_i915_private *i915`` i915 device instance h](j)}(h!``struct drm_i915_private *i915``h]j)}(hj/h]hstruct drm_i915_private *i915}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhj/ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1j|hj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jwhje/ubh)}(h**Description**h]jb)}(hj/h]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj/ubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhje/ubh)}(h6This function is used to enable interrupts at runtime.h]h6This function is used to enable interrupts at runtime.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhX/var/lib/git/docbuild/linux/Documentation/gpu/i915:40: ./drivers/gpu/drm/i915/i915_irq.chMhje/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjN+hhhNhNubeh}(h]interrupt-handlingah ]h"]interrupt handlingah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hIntel GVT-g Guest Support(vGPU)h]hIntel GVT-g Guest Support(vGPU)}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhK,ubh)}(hXIntel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine. This file provides vGPU specific optimizations when running in a virtual machine, to reduce the complexity of vGPU emulation and to improve the overall performance.h]hXIntel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. Each virtual machine is presented a virtual GPU (vGPU), which has equivalent features as the underlying physical GPU (pGPU), so i915 driver can run seamlessly in a virtual machine. This file provides vGPU specific optimizations when running in a virtual machine, to reduce the complexity of vGPU emulation and to improve the overall performance.}(hj 0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:46: ./drivers/gpu/drm/i915/i915_vgpu.chKhj/hhubh)}(hXA primary function introduced here is so-called "address space ballooning" technique. Intel GVT-g partitions global graphics memory among multiple VMs, so each VM can directly access a portion of the memory without hypervisor's intervention, e.g. filling textures or queuing commands. However with the partitioning an unmodified i915 driver would assume a smaller graphics memory starting from address ZERO, then requires vGPU emulation module to translate the graphics address between 'guest view' and 'host view', for all registers and command opcodes which contain a graphics memory address. To reduce the complexity, Intel GVT-g introduces "address space ballooning", by telling the exact partitioning knowledge to each guest i915 driver, which then reserves and prevents non-allocated portions from allocation. Thus vGPU emulation module only needs to scan and validate graphics addresses without complexity of address translation.h]hXA primary function introduced here is so-called “address space ballooning” technique. Intel GVT-g partitions global graphics memory among multiple VMs, so each VM can directly access a portion of the memory without hypervisor’s intervention, e.g. filling textures or queuing commands. However with the partitioning an unmodified i915 driver would assume a smaller graphics memory starting from address ZERO, then requires vGPU emulation module to translate the graphics address between ‘guest view’ and ‘host view’, for all registers and command opcodes which contain a graphics memory address. To reduce the complexity, Intel GVT-g introduces “address space ballooning”, by telling the exact partitioning knowledge to each guest i915 driver, which then reserves and prevents non-allocated portions from allocation. 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The ballooning related knowledge(starting address and size of the mappable/unmappable graphic memory) is described in the vgt_if structure in a reserved mmio range.h]hXAThis function is called at the initialization stage, to balloon out the graphic address space allocated to other vGPUs, by marking these spaces as reserved. The ballooning related knowledge(starting address and size of the mappable/unmappable graphic memory) is described in the vgt_if structure in a reserved mmio range.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(hX(To give an example, the drawing below depicts one typical scenario after ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned out each for the mappable and the non-mappable part. From the vGPU1 point of view, the total size is the same as the physical one, with the start address of its graphic space being zero. Yet there are some portions ballooned out( the shadow part, which are marked as reserved by drm allocator). From the host point of view, the graphic address space is partitioned by multiple vGPUs in different VMs. ::h]hX%To give an example, the drawing below depicts one typical scenario after ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned out each for the mappable and the non-mappable part. From the vGPU1 point of view, the total size is the same as the physical one, with the start address of its graphic space being zero. Yet there are some portions ballooned out( the shadow part, which are marked as reserved by drm allocator). From the host point of view, the graphic address space is partitioned by multiple vGPUs in different VMs.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubj")}(hXk vGPU1 view Host view 0 ------> +-----------+ +-----------+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ mappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | v |###########| | Host | +=======+===========+ +===========+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ unmappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | | |###########| | Host | v |###########| | | total GM size ------> +-----------+ +-----------+h]hXk vGPU1 view Host view 0 ------> +-----------+ +-----------+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ mappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | v |###########| | Host | +=======+===========+ +===========+ ^ |###########| | vGPU3 | | |###########| +-----------+ | |###########| | vGPU2 | | +-----------+ +-----------+ unmappable GM | available | ==> | vGPU1 | | +-----------+ +-----------+ | |###########| | | | |###########| | Host | v |###########| | | total GM size ------> +-----------+ +-----------+}hj4sbah}(h]h ]h"]h$]h&]jjuh1j"hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(h **Return**h]jb)}(hj4h]hReturn}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj4ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubh)}(hGzero on success, non-zero if configuration invalid or ballooning failedh]hGzero on success, non-zero if configuration invalid or ballooning failed}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:49: ./drivers/gpu/drm/i915/i915_vgpu.chKhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj/hhhNhNubeh}(h]intel-gvt-g-guest-support-vgpuah ]h"]intel gvt-g guest support(vgpu)ah$]h&]uh1hhhhhhhhK,ubh)}(hhh](h)}(h+Intel GVT-g Host Support(vGPU device model)h]h+Intel GVT-g Host Support(vGPU device model)}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhK5ubh)}(hX6Intel GVT-g is a graphics virtualization technology which shares the GPU among multiple virtual machines on a time-sharing basis. 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*dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj5ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj5ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj5modnameN classnameNjXj[)}j^]ja)}jTjx5sbc.intel_gvt_initasbuh1hhj5ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj5ubj)}(hjh]h*}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubj;)}(hdev_privh]hdev_priv}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj5ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj5ubah}(h]h ]h"]h$]h&]jjuh1jhjQ5hhhjc5hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjM5hhhjc5hKubah}(h]jH5ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjc5hKhjJ5hhubj1)}(hhh]h)}(hinitialize GVT componentsh]hinitialize GVT components}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj6hhubah}(h]h ]h"]h$]h&]uh1j0hjJ5hhhjc5hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj-6jSj-6jTjUjVuh1j&hhhj4hNhNubjX)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private data **Description** This function is called at the initialization stage to create a GVT device. **Return** Zero on success, negative error code if failed.h](h)}(h**Parameters**h]jb)}(hj76h]h Parameters}(hj96hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj56ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubjx)}(hhh]j})}(h<``struct drm_i915_private *dev_priv`` drm i915 private data h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hjV6h]h!struct drm_i915_private *dev_priv}(hjX6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhjP6ubj)}(hhh]h)}(hdrm i915 private datah]hdrm i915 private data}(hjo6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk6hKhjl6ubah}(h]h ]h"]h$]h&]uh1jhjP6ubeh}(h]h ]h"]h$]h&]uh1j|hjk6hKhjM6ubah}(h]h ]h"]h$]h&]uh1jwhj16ubh)}(h**Description**h]jb)}(hj6h]h Description}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj6ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubh)}(hKThis function is called at the initialization stage to create a GVT device.h]hKThis function is called at the initialization stage to create a GVT device.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubh)}(h **Return**h]jb)}(hj6h]hReturn}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj6ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubh)}(h/Zero on success, negative error code if failed.h]h/Zero on success, negative error code if failed.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj16ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj4hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_gvt_driver_remove (C function)c.intel_gvt_driver_removehNtauh1jhj4hhhNhNubj')}(hhh](j,)}(h@void intel_gvt_driver_remove (struct drm_i915_private *dev_priv)h]j2)}(h?void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)h](j)}(hvoidh]hvoid}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKubji)}(h h]h }(hj 7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj6hhhj 7hKubjz)}(hintel_gvt_driver_removeh]j;)}(hintel_gvt_driver_removeh]hintel_gvt_driver_remove}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj6hhhj 7hKubj)}(h#(struct drm_i915_private *dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hj:7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj67ubji)}(h h]h }(hjG7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj67ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjX7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjU7ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjZ7modnameN classnameNjXj[)}j^]ja)}jTj 7sbc.intel_gvt_driver_removeasbuh1hhj67ubji)}(h h]h }(hjx7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj67ubj)}(hjh]h*}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj67ubj;)}(hdev_privh]hdev_priv}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj67ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj27ubah}(h]h ]h"]h$]h&]jjuh1jhj6hhhj 7hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj6hhhj 7hKubah}(h]j6ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj 7hKhj6hhubj1)}(hhh]h)}(h4cleanup GVT components when i915 driver is unbindingh]h4cleanup GVT components when i915 driver is unbinding}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj7hhubah}(h]h ]h"]h$]h&]uh1j0hj6hhhj 7hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj7jSj7jTjUjVuh1j&hhhj4hNhNubjX)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private * **Description** This function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.h](h)}(h**Parameters**h]jb)}(hj7h]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj7ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhj7ubjx)}(hhh]j})}(h9``struct drm_i915_private *dev_priv`` drm i915 private * h](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hj7h]h!struct drm_i915_private *dev_priv}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chKhj7ubj)}(hhh]h)}(hdrm i915 private *h]hdrm i915 private *}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hKhj8ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1j|hj8hKhj7ubah}(h]h ]h"]h$]h&]uh1jwhj7ubh)}(h**Description**h]jb)}(hj98h]h Description}(hj;8hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj78ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhj7ubh)}(hyThis function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.h]hyThis function is called at the i915 driver unloading stage, to shutdown GVT components and release the related resources.}(hjO8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj4hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_gvt_resume (C function)c.intel_gvt_resumehNtauh1jhj4hhhNhNubj')}(hhh](j,)}(h9void intel_gvt_resume (struct drm_i915_private *dev_priv)h]j2)}(h8void intel_gvt_resume(struct drm_i915_private *dev_priv)h](j)}(hvoidh]hvoid}(hj~8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz8hhhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chM ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjz8hhhj8hM ubjz)}(hintel_gvt_resumeh]j;)}(hintel_gvt_resumeh]hintel_gvt_resume}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjz8hhhj8hM ubj)}(h#(struct drm_i915_private *dev_priv)h]j)}(h!struct drm_i915_private *dev_privh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj8ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj8modnameN classnameNjXj[)}j^]ja)}jTj8sbc.intel_gvt_resumeasbuh1hhj8ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj8ubj)}(hjh]h*}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj;)}(hdev_privh]hdev_priv}(hj9hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj8ubah}(h]h ]h"]h$]h&]jjuh1jhjz8hhhj8hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjv8hhhj8hM ubah}(h]jq8ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj8hM hjs8hhubj1)}(hhh]h)}(hGVT resume routine wrapperh]hGVT resume routine wrapper}(hj>9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chM hj;9hhubah}(h]h ]h"]h$]h&]uh1j0hjs8hhhj8hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjV9jSjV9jTjUjVuh1j&hhhj4hNhNubjX)}(h**Parameters** ``struct drm_i915_private *dev_priv`` drm i915 private * **Description** This function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.h](h)}(h**Parameters**h]jb)}(hj`9h]h Parameters}(hjb9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj^9ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhjZ9ubjx)}(hhh]j})}(h9``struct drm_i915_private *dev_priv`` drm i915 private * zh](j)}(h%``struct drm_i915_private *dev_priv``h]j)}(hj9h]h!struct drm_i915_private *dev_priv}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhjy9ubj)}(hhh]h)}(hdrm i915 private *h]hdrm i915 private *}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhjy9ubeh}(h]h ]h"]h$]h&]uh1j|hj9hMhjv9ubah}(h]h ]h"]h$]h&]uh1jwhjZ9ubh)}(h**Description**h]jb)}(hj9h]h Description}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj9ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhjZ9ubh)}(hThis function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.h]hThis function is called at the i915 driver resume stage to restore required HW status for GVT so that vGPU can continue running after resumed.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:58: ./drivers/gpu/drm/i915/intel_gvt.chMhjZ9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj4hhhNhNubeh}(h]*intel-gvt-g-host-support-vgpu-device-modelah ]h"]+intel gvt-g host support(vgpu device model)ah$]h&]uh1hhhhhhhhK5ubh)}(hhh](h)}(h Workaroundsh]h Workarounds}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhK>ubh)}(hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:h]hHardware workarounds are register programming documented to be executed in the driver that fall outside of the normal programming sequences for a platform. There are some basic categories of workarounds, depending on how/when they are applied:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKhj9hhubh bullet_list)}(hhh](h list_item)}(hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers. Context workarounds should be implemented in the \*_ctx_workarounds_init() variants respective to the targeted platforms. h](h)}(hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a "primed golden context", i.e. a context image that already contains the changes needed to all the registers.h]hXContext workarounds: workarounds that touch registers that are saved/restored to/from the HW context image. The list is emitted (via Load Register Immediate commands) once when initializing the device and saved in the default context. That default context is then used on every context creation to have a “primed golden context”, i.e. a context image that already contains the changes needed to all the registers.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKhj:ubh)}(hyContext workarounds should be implemented in the \*_ctx_workarounds_init() variants respective to the targeted platforms.h]hyContext workarounds should be implemented in the *_ctx_workarounds_init() variants respective to the targeted platforms.}(hj(:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK#hj:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hX Engine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. Workarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine's MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode(). h](h)}(hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It's also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference.h](hXEngine workarounds: the list of these WAs is applied whenever the specific engine is reset. It’s also possible that a set of engine classes share a common power domain and they are reset together. This happens on some platforms with render and compute engines. In this case (at least) one of them need to keeep the workaround programming: the approach taken in the driver is to tie those workarounds to the first compute/render engine that is registered. When executing with GuC submission, engine resets are outside of kernel driver control, hence the list of registers involved in written once, on engine initialization, and then passed to GuC, that saves/restores their values before/after the reset takes place. See }(hjA:hhhNhNubj)}(h.``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c``h]h*drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c}(hjI:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA:ubh for reference.}(hjA:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK&hj=:ubh)}(hXWorkarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine's MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode().h]hXWorkarounds for registers specific to RCS and CCS should be implemented in rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for registers belonging to BCS, VCS or VECS should be implemented in xcs_engine_wa_init(). Workarounds for registers not belonging to a specific engine’s MMIO range but that are part of of the common RCS/CCS reset domain should be implemented in general_render_compute_wa_init(). The settings about the CCS load balancing should be added in ccs_engine_wa_mode().}(hjb:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK2hj=:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hXGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc. GT workarounds should be implemented in the \*_gt_workarounds_init() variants respective to the targeted platforms. h](h)}(hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume [1]_, etc.h](hGT workarounds: the list of these WAs is applied whenever these registers revert to their default values: on GPU reset, suspend/resume }(hj{:hhhNhNubhfootnote_reference)}(h[1]_h]h1}(hj:hhhNhNubah}(h]id1ah ]h"]h$]h&]refidid2docnamegpu/i915uh1j:hj{:resolvedKubh, etc.}(hj{:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK:hjw:ubh)}(hsGT workarounds should be implemented in the \*_gt_workarounds_init() variants respective to the targeted platforms.h]hsGT workarounds should be implemented in the *_gt_workarounds_init() variants respective to the targeted platforms.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK=hjw:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hXRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers). Register whitelisting should be done in the \*_whitelist_build() variants respective to the targeted platforms. h](h)}(hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).h]hXdRegister whitelist: some workarounds need to be implemented in userspace, but need to touch privileged registers. The whitelist in the kernel instructs the hardware to allow the access to happen. From the kernel side, this is just a special case of a MMIO workaround (as we write the list of these to/be-whitelisted registers to some special HW registers).}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK@hj:ubh)}(hoRegister whitelisting should be done in the \*_whitelist_build() variants respective to the targeted platforms.h]hoRegister whitelisting should be done in the *_whitelist_build() variants respective to the targeted platforms.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKFhj:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hX`Workaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms: #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms. #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver. h](h)}(hXRWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms:h]hXRWorkaround batchbuffers: buffers that get executed automatically by the hardware on every HW context restore. These buffers are created and programmed in the default context so the hardware always go through those programming sequences when switching contexts. The support for workaround batchbuffers is enabled these hardware mechanisms:}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKIhj:ubhenumerated_list)}(hhh](j:)}(hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms. h]h)}(hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms.h]hXINDIRECT_CTX: A batchbuffer and an offset are provided in the default context, pointing the hardware to jump to that location when that offset is reached in the context restore. Workaround batchbuffer in the driver currently uses this mechanism for all platforms.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKOhj:ubah}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver. h]h)}(hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver.h]hBB_PER_CTX_PTR: A batchbuffer is provided in the default context, pointing the hardware to a buffer to continue executing after the engine registers are restored in a context restore sequence. This is currently not used in the driver.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKThj;ubah}(h]h ]h"]h$]h&]uh1j:hj:ubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j:hj:ubeh}(h]h ]h"]h$]h&]uh1j:hj:ubj:)}(hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example. h]h)}(hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example.h]hOther: There are WAs that, due to their nature, cannot be applied from a central place. Those are peppered around the rest of the code, as needed. Workarounds related to the display IP are the main example.}(hj@;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chKYhj<;ubah}(h]h ]h"]h$]h&]uh1j:hj:ubeh}(h]h ]h"]h$]h&]bullet-uh1j:hj':hKhj9hhubhfootnote)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver. h](hlabel)}(h1h]h1}(hje;hhhNhNubah}(h]h ]h"]h$]h&]uh1jc;hj_;ubh)}(hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it's the approach taken in the driver.h]hTechnically, some registers are powercontext saved & restored, so they survive a suspend/resume. In practice, writing them again is not too costly and simplifies things, so it’s the approach taken in the driver.}(hjs;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:64: ./drivers/gpu/drm/i915/gt/intel_workarounds.chK]hj_;ubeh}(h]j:ah ]h"]1ah$]h&]j:aj:j:uh1j];hj;hK]hj9hhj:Kubeh}(h] workaroundsah ]h"] workaroundsah$]h&]uh1hhhhhhhhK>ubeh}(h]core-driver-infrastructureah ]h"]core driver infrastructureah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hDisplay Hardware Handlingh]hDisplay Hardware Handling}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhKDubh)}(hThis section covers everything related to the display hardware including the mode setting infrastructure, plane, sprite and cursor handling and display, output probing and related topics.h]hThis section covers everything related to the display hardware including the mode setting infrastructure, plane, sprite and cursor handling and display, output probing and related topics.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhj;hhubh)}(hhh](h)}(hMode Setting Infrastructureh]hMode Setting Infrastructure}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhKKubh)}(hThe i915 driver is thus far the only DRM driver which doesn't use the common DRM helper code to implement mode setting sequences. Thus it has its own tailor-made infrastructure for executing a display configuration change.h]hThe i915 driver is thus far the only DRM driver which doesn’t use the common DRM helper code to implement mode setting sequences. Thus it has its own tailor-made infrastructure for executing a display configuration change.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhj;hhubeh}(h]mode-setting-infrastructureah ]h"]mode setting infrastructureah$]h&]uh1hhj;hhhhhKKubh)}(hhh](h)}(hFrontbuffer Trackingh]hFrontbuffer Tracking}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhKSubh)}(hMany features require us to track changes to the currently active frontbuffer, especially rendering targeted at the frontbuffer.h]hMany features require us to track changes to the currently active frontbuffer, especially rendering targeted at the frontbuffer.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:85: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj;hhubh)}(hX To be able to do so we track frontbuffers using a bitmask for all possible frontbuffer slots through intel_frontbuffer_track(). The functions in this file are then called when the contents of the frontbuffer are invalidated, when frontbuffer rendering has stopped again to flush out all the changes and when the frontbuffer is exchanged with a flip. Subsystems interested in frontbuffer changes (e.g. PSR, FBC, DRRS) should directly put their callbacks into the relevant places and filter for the frontbuffer slots that they are interested int.h]hX To be able to do so we track frontbuffers using a bitmask for all possible frontbuffer slots through intel_frontbuffer_track(). The functions in this file are then called when the contents of the frontbuffer are invalidated, when frontbuffer rendering has stopped again to flush out all the changes and when the frontbuffer is exchanged with a flip. Subsystems interested in frontbuffer changes (e.g. PSR, FBC, DRRS) should directly put their callbacks into the relevant places and filter for the frontbuffer slots that they are interested int.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:85: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj;hhubh)}(hX&On a high level there are two types of powersaving features. The first one work like a special cache (FBC and PSR) and are interested when they should stop caching and when to restart caching. This is done by placing callbacks into the invalidate and the flush functions: At invalidate the caching must be stopped and at flush time it can be restarted. And maybe they need to know when the frontbuffer changes (e.g. when the hw doesn't initiate an invalidate and flush on its own) which can be achieved with placing callbacks into the flip functions.h]hX(On a high level there are two types of powersaving features. The first one work like a special cache (FBC and PSR) and are interested when they should stop caching and when to restart caching. This is done by placing callbacks into the invalidate and the flush functions: At invalidate the caching must be stopped and at flush time it can be restarted. And maybe they need to know when the frontbuffer changes (e.g. when the hw doesn’t initiate an invalidate and flush on its own) which can be achieved with placing callbacks into the flip functions.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:85: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chK(hj;hhubh)}(hXRThe other type of display power saving feature only cares about busyness (e.g. DRRS). In that case all three (invalidate, flush and flip) indicate busyness. There is no direct way to detect idleness. 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?ubh)}(hhh]j;)}(h fb_op_originh]h fb_op_origin}(hj.?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+?ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0?modnameN classnameNjXj[)}j^]j>c.intel_frontbuffer_flushasbuh1hhj ?ubji)}(h h]h }(hjL?hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ?ubj;)}(horiginh]horigin}(hjZ?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ?ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubeh}(h]h ]h"]h$]h&]jjuh1jhj]>hhhjo>hKwubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjY>hhhjo>hKwubah}(h]jT>ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjo>hKwhjV>hhubj1)}(hhh]h)}(hflush frontbuffer objecth]hflush frontbuffer object}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:88: ./drivers/gpu/drm/i915/display/intel_frontbuffer.hhKwhj?hhubah}(h]h ]h"]h$]h&]uh1j0hjV>hhhjo>hKwubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj?jSj?jTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_frontbuffer *front`` GEM object to flush ``enum fb_op_origin origin`` which operation caused the flush **Description** This function gets called every time rendering on the given object has completed and frontbuffer caching can be started again.h](h)}(h**Parameters**h]jb)}(hj?h]h Parameters}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:88: ./drivers/gpu/drm/i915/display/intel_frontbuffer.hhK{hj?ubjx)}(hhh](j})}(h8``struct intel_frontbuffer *front`` GEM object to flush h](j)}(h#``struct intel_frontbuffer *front``h]j)}(hj?h]hstruct intel_frontbuffer *front}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:88: ./drivers/gpu/drm/i915/display/intel_frontbuffer.hhKxhj?ubj)}(hhh]h)}(hGEM object to flushh]hGEM object to flush}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hKxhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j|hj?hKxhj?ubj})}(h>``enum fb_op_origin origin`` which operation caused the flush h](j)}(h``enum fb_op_origin origin``h]j)}(hj?h]henum fb_op_origin origin}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:88: ./drivers/gpu/drm/i915/display/intel_frontbuffer.hhKyhj?ubj)}(hhh]h)}(h which operation caused the flushh]h which operation caused the flush}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hKyhj@ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j|hj@hKyhj?ubeh}(h]h ]h"]h$]h&]uh1jwhj?ubh)}(h**Description**h]jb)}(hj9@h]h Description}(hj;@hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj7@ubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:88: ./drivers/gpu/drm/i915/display/intel_frontbuffer.hhK{hj?ubh)}(h~This function gets called every time rendering on the given object has completed and frontbuffer caching can be started again.h]h~This function gets called every time rendering on the given object has completed and frontbuffer caching can be started again.}(hjO@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:88: 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originh](j)}(hjh]henum}(hj~AhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzAubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzAubh)}(hhh]j;)}(h fb_op_originh]h fb_op_origin}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjAmodnameN classnameNjXj[)}j^]j@c.frontbuffer_flushasbuh1hhjzAubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzAubj;)}(horiginh]horigin}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzAubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj@ubeh}(h]h ]h"]h$]h&]jjuh1jhjz@hhhj@hKIubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjv@hhhj@hKIubah}(h]jq@ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj@hKIhjs@hhubj1)}(hhh]h)}(hflush frontbufferh]hflush frontbuffer}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKIhjAhhubah}(h]h ]h"]h$]h&]uh1j0hjs@hhhj@hKIubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj BjSj BjTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device ``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the flush **Description** This function gets called every time rendering on the given planes has completed and frontbuffer caching can be started again. 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]h"]h$]h&]jjj"uh1j1j#j$hjJIhhhj`IhKubah}(h]jEIah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj`IhKhjGIhhubj1)}(hhh]h)}(h!queue flushing frontbuffer objecth]h!queue flushing frontbuffer object}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhjJhhubah}(h]h ]h"]h$]h&]uh1j0hjGIhhhj`IhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj*JjSj*JjTjUjVuh1j&hhhj;hNhNubjX)}(h**Parameters** ``struct intel_frontbuffer *front`` GEM object to flush **Description** This function is targeted for our dirty callback for queueing flush when dma fence is signalsh](h)}(h**Parameters**h]jb)}(hj4Jh]h Parameters}(hj6JhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj2Jubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj.Jubjx)}(hhh]j})}(h8``struct intel_frontbuffer *front`` GEM object to flush h](j)}(h#``struct intel_frontbuffer *front``h]j)}(hjSJh]hstruct intel_frontbuffer *front}(hjUJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQJubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhjMJubj)}(hhh]h)}(hGEM object to flushh]hGEM object to flush}(hjlJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhJhKhjiJubah}(h]h ]h"]h$]h&]uh1jhjMJubeh}(h]h ]h"]h$]h&]uh1j|hjhJhKhjJJubah}(h]h ]h"]h$]h&]uh1jwhj.Jubh)}(h**Description**h]jb)}(hjJh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjJubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj.Jubh)}(h]This function is targeted for our dirty callback for queueing flush when dma fence is signalsh]h]This function is targeted for our dirty callback for queueing flush when dma fence is signals}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chKhj.Jubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_frontbuffer_track (C function)c.intel_frontbuffer_trackhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hzvoid intel_frontbuffer_track (struct intel_frontbuffer *old, struct intel_frontbuffer *new, unsigned int frontbuffer_bits)h]j2)}(hyvoid intel_frontbuffer_track(struct intel_frontbuffer *old, struct intel_frontbuffer *new, unsigned int frontbuffer_bits)h](j)}(hvoidh]hvoid}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJhhhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM;ubji)}(h h]h }(hjJhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjJhhhjJhM;ubjz)}(hintel_frontbuffer_trackh]j;)}(hintel_frontbuffer_trackh]hintel_frontbuffer_track}(hjJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjJubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjJhhhjJhM;ubj)}(h](struct intel_frontbuffer *old, struct intel_frontbuffer *new, unsigned int frontbuffer_bits)h](j)}(hstruct intel_frontbuffer *oldh](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Kubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj Kubh)}(hhh]j;)}(hintel_frontbufferh]hintel_frontbuffer}(hj.KhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+Kubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0KmodnameN classnameNjXj[)}j^]ja)}jTjJsbc.intel_frontbuffer_trackasbuh1hhj Kubji)}(h h]h }(hjNKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj Kubj)}(hjh]h*}(hj\KhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Kubj;)}(holdh]hold}(hjiKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj Kubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubj)}(hstruct intel_frontbuffer *newh](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Kubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~Kubh)}(hhh]j;)}(hintel_frontbufferh]hintel_frontbuffer}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjKmodnameN classnameNjXj[)}j^]jJKc.intel_frontbuffer_trackasbuh1hhj~Kubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~Kubj)}(hjh]h*}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~Kubj;)}(hnewh]hnew}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~Kubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubj)}(hunsigned int frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hjLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj)}(hinth]hint}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hjLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hj*LhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubeh}(h]h ]h"]h$]h&]jjuh1jhjJhhhjJhM;ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjJhhhjJhM;ubah}(h]jJah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjJhM;hjJhhubj1)}(hhh]h)}(hupdate frontbuffer trackingh]hupdate frontbuffer tracking}(hjTLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM;hjQLhhubah}(h]h ]h"]h$]h&]uh1j0hjJhhhjJhM;ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjlLjSjlLjTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_frontbuffer *old`` current buffer for the frontbuffer slots ``struct intel_frontbuffer *new`` new buffer for the frontbuffer slots ``unsigned int frontbuffer_bits`` bitmask of frontbuffer slots **Description** This updates the frontbuffer tracking bits **frontbuffer_bits** by clearing them from **old** and setting them in **new**. Both **old** and **new** can be NULL.h](h)}(h**Parameters**h]jb)}(hjvLh]h Parameters}(hjxLhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtLubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM?hjpLubjx)}(hhh](j})}(hK``struct intel_frontbuffer *old`` current buffer for the frontbuffer slots h](j)}(h!``struct intel_frontbuffer *old``h]j)}(hjLh]hstruct intel_frontbuffer *old}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM<hjLubj)}(hhh]h)}(h(current buffer for the frontbuffer slotsh]h(current buffer for the frontbuffer slots}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM<hjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjLhM<hjLubj})}(hG``struct intel_frontbuffer *new`` new buffer for the frontbuffer slots h](j)}(h!``struct intel_frontbuffer *new``h]j)}(hjLh]hstruct intel_frontbuffer *new}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM=hjLubj)}(hhh]h)}(h$new buffer for the frontbuffer slotsh]h$new buffer for the frontbuffer slots}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM=hjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjLhM=hjLubj})}(h?``unsigned int frontbuffer_bits`` bitmask of frontbuffer slots h](j)}(h!``unsigned int frontbuffer_bits``h]j)}(hjMh]hunsigned int frontbuffer_bits}(hj MhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM>hjMubj)}(hhh]h)}(hbitmask of frontbuffer slotsh]hbitmask of frontbuffer slots}(hj MhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhM>hjMubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j|hjMhM>hjLubeh}(h]h ]h"]h$]h&]uh1jwhjpLubh)}(h**Description**h]jb)}(hjBMh]h Description}(hjDMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj@Mubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM@hjpLubh)}(hThis updates the frontbuffer tracking bits **frontbuffer_bits** by clearing them from **old** and setting them in **new**. Both **old** and **new** can be NULL.h](h+This updates the frontbuffer tracking bits }(hjXMhhhNhNubjb)}(h**frontbuffer_bits**h]hfrontbuffer_bits}(hj`MhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh by clearing them from }(hjXMhhhNhNubjb)}(h**old**h]hold}(hjrMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh and setting them in }(hjXMhhhNhNubjb)}(h**new**h]hnew}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh. Both }(hjXMhhhNhNubjb)}(h**old**h]hold}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh and }(hjXMhhhNhNubjb)}(h**new**h]hnew}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXMubh can be NULL.}(hjXMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/gpu/i915:91: ./drivers/gpu/drm/i915/display/intel_frontbuffer.chM@hjpLubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubeh}(h]frontbuffer-trackingah ]h"]frontbuffer trackingah$]h&]uh1hhj;hhhhhKSubh)}(hhh](h)}(hDisplay FIFO Underrun Reportingh]hDisplay FIFO Underrun Reporting}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhK_ubh)}(hThe i915 driver checks for display fifo underruns using the interrupt signals provided by the hardware. This is enabled by default and fairly useful to debug display issues, especially watermark settings.h]hThe i915 driver checks for display fifo underruns using the interrupt signals provided by the hardware. This is enabled by default and fairly useful to debug display issues, especially watermark settings.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:97: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK(hjMhhubh)}(hIf an underrun is detected this is logged into dmesg. To avoid flooding logs and occupying the cpu underrun interrupts are disabled after the first occurrence until the next modeset on a given pipe.h]hIf an underrun is detected this is logged into dmesg. To avoid flooding logs and occupying the cpu underrun interrupts are disabled after the first occurrence until the next modeset on a given pipe.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:97: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK,hjMhhubh)}(hXFNote that underrun detection on gmch platforms is a bit more ugly since there is no interrupt (despite that the signalling bit is in the PIPESTAT pipe interrupt register). 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Also on some other platforms underrun interrupts are shared, which means that if we detect an underrun we need to disable underrun reporting on all pipes.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:97: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK0hjMhhubh)}(h@The code also supports underrun detection on the PCH transcoder.h]h@The code also supports underrun detection on the PCH transcoder.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:97: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chK6hjMhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"2intel_set_cpu_fifo_underrun_reporting (C function)'c.intel_set_cpu_fifo_underrun_reportinghNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hgbool intel_set_cpu_fifo_underrun_reporting (struct intel_display *display, enum pipe pipe, bool enable)h]j2)}(hfbool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable)h](j)}(hjh]hbool}(hj6NhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2Nhhhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMubji)}(h h]h }(hjDNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2NhhhjCNhMubjz)}(h%intel_set_cpu_fifo_underrun_reportingh]j;)}(h%intel_set_cpu_fifo_underrun_reportingh]h%intel_set_cpu_fifo_underrun_reporting}(hjVNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRNubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj2NhhhjCNhMubj)}(h<(struct intel_display *display, enum pipe pipe, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjrNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnNubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnNubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjNmodnameN classnameNjXj[)}j^]ja)}jTjXNsb'c.intel_set_cpu_fifo_underrun_reportingasbuh1hhjnNubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnNubj)}(hjh]h*}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnNubj;)}(hdisplayh]hdisplay}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnNubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjNubj)}(henum pipe pipeh](j)}(hjh]henum}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjNubh)}(hhh]j;)}(hpipeh]hpipe}(hjOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjOmodnameN classnameNjXj[)}j^]jN'c.intel_set_cpu_fifo_underrun_reportingasbuh1hhjNubji)}(h h]h }(hj OhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjNubj;)}(hpipeh]hpipe}(hj.OhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjNubj)}(h bool enableh](j)}(hjh]hbool}(hjGOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCOubji)}(h h]h }(hjTOhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjCOubj;)}(henableh]henable}(hjbOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCOubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjNubeh}(h]h ]h"]h$]h&]jjuh1jhj2NhhhjCNhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj.NhhhjCNhMubah}(h]j)Nah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjCNhMhj+Nhhubj1)}(hhh]h)}(h%set cpu fifo underrun reporting stateh]h%set cpu fifo underrun reporting state}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjOhhubah}(h]h ]h"]h$]h&]uh1j0hj+NhhhjCNhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjOjSjOjTjUjVuh1j&hhhjMhNhNubjX)}(hXc**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pipe`` (CPU) pipe to set state for ``bool enable`` whether underruns should be reported or not **Description** This function sets the fifo underrun state for **pipe**. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe. Notice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though. Returns the previous state of underrun reporting.h](h)}(h**Parameters**h]jb)}(hjOh]h Parameters}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjOubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjOubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjOh]hstruct intel_display *display}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjOubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhMhjOubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j|hjOhMhjOubj})}(h/``enum pipe pipe`` (CPU) pipe to set state for h](j)}(h``enum pipe pipe``h]j)}(hjPh]henum pipe pipe}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjPubj)}(hhh]h)}(h(CPU) pipe to set state forh]h(CPU) pipe to set state for}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j|hjPhMhjOubj})}(h<``bool enable`` whether underruns should be reported or not h](j)}(h``bool enable``h]j)}(hj?Ph]h bool enable}(hjAPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=Pubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj9Pubj)}(hhh]h)}(h+whether underruns should be reported or noth]h+whether underruns should be reported or not}(hjXPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTPhMhjUPubah}(h]h ]h"]h$]h&]uh1jhj9Pubeh}(h]h ]h"]h$]h&]uh1j|hjTPhMhjOubeh}(h]h ]h"]h$]h&]uh1jwhjOubh)}(h**Description**h]jb)}(hjzPh]h Description}(hj|PhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjxPubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjOubh)}(hThis function sets the fifo underrun state for **pipe**. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe.h](h/This function sets the fifo underrun state for }(hjPhhhNhNubjb)}(h**pipe**h]hpipe}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjPubh. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjOubh)}(hNotice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though.h]hNotice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjOubh)}(h1Returns the previous state of underrun reporting.h]h1Returns the previous state of underrun reporting.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM"hjOubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"2intel_set_pch_fifo_underrun_reporting (C function)'c.intel_set_pch_fifo_underrun_reportinghNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hqbool intel_set_pch_fifo_underrun_reporting (struct intel_display *display, enum pipe pch_transcoder, bool enable)h]j2)}(hpbool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable)h](j)}(hjh]hbool}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM2ubji)}(h h]h }(hjPhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjPhhhjPhM2ubjz)}(h%intel_set_pch_fifo_underrun_reportingh]j;)}(h%intel_set_pch_fifo_underrun_reportingh]h%intel_set_pch_fifo_underrun_reporting}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj Qubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjPhhhjPhM2ubj)}(hF(struct intel_display *display, enum pipe pch_transcoder, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj+QhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'Qubji)}(h h]h }(hj8QhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'Qubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjIQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFQubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjKQmodnameN classnameNjXj[)}j^]ja)}jTjQsb'c.intel_set_pch_fifo_underrun_reportingasbuh1hhj'Qubji)}(h h]h }(hjiQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'Qubj)}(hjh]h*}(hjwQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'Qubj;)}(hdisplayh]hdisplay}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'Qubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#Qubj)}(henum pipe pch_transcoderh](j)}(hjh]henum}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubh)}(hhh]j;)}(hpipeh]hpipe}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjQmodnameN classnameNjXj[)}j^]jeQ'c.intel_set_pch_fifo_underrun_reportingasbuh1hhjQubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj;)}(hpch_transcoderh]hpch_transcoder}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#Qubj)}(h bool enableh](j)}(hjh]hbool}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hj RhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj;)}(henableh]henable}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj#Qubeh}(h]h ]h"]h$]h&]jjuh1jhjPhhhjPhM2ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjPhhhjPhM2ubah}(h]jPah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjPhM2hjPhhubj1)}(hhh]h)}(h%set PCH fifo underrun reporting stateh]h%set PCH fifo underrun reporting state}(hjERhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM2hjBRhhubah}(h]h ]h"]h$]h&]uh1j0hjPhhhjPhM2ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj]RjSj]RjTjUjVuh1j&hhhjMhNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) ``bool enable`` whether underruns should be reported or not **Description** This function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there's just one interrupt mask/enable bit for all the transcoders. Returns the previous state of underrun reporting.h](h)}(h**Parameters**h]jb)}(hjgRh]h Parameters}(hjiRhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjeRubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM6hjaRubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjRh]hstruct intel_display *display}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM3hjRubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhM3hjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j|hjRhM3hj}Rubj})}(hP``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) h](j)}(h``enum pipe pch_transcoder``h]j)}(hjRh]henum pipe pch_transcoder}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM4hjRubj)}(hhh]h)}(h2the PCH transcoder (same as pipe on IVB and older)h]h2the PCH transcoder (same as pipe on IVB and older)}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhM4hjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j|hjRhM4hj}Rubj})}(h<``bool enable`` whether underruns should be reported or not h](j)}(h``bool enable``h]j)}(hjRh]h bool enable}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM5hjRubj)}(hhh]h)}(h+whether underruns should be reported or noth]h+whether underruns should be reported or not}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ShM5hjSubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j|hj ShM5hj}Rubeh}(h]h ]h"]h$]h&]uh1jwhjaRubh)}(h**Description**h]jb)}(hj3Sh]h Description}(hj5ShhhNhNubah}(h]h ]h"]h$]h&]uh1jahj1Subah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM7hjaRubh)}(hX_This function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there's just one interrupt mask/enable bit for all the transcoders.h]hXaThis function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there’s just one interrupt mask/enable bit for all the transcoders.}(hjIShhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM7hjaRubh)}(h1Returns the previous state of underrun reporting.h]h1Returns the previous state of underrun reporting.}(hjXShhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chM=hjaRubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"0intel_cpu_fifo_underrun_irq_handler (C function)%c.intel_cpu_fifo_underrun_irq_handlerhNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hXvoid intel_cpu_fifo_underrun_irq_handler (struct intel_display *display, enum pipe pipe)h]j2)}(hWvoid intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pipe)h](j)}(hvoidh]hvoid}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjShhhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMcubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjShhhjShMcubjz)}(h#intel_cpu_fifo_underrun_irq_handlerh]j;)}(h#intel_cpu_fifo_underrun_irq_handlerh]h#intel_cpu_fifo_underrun_irq_handler}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjShhhjShMcubj)}(h/(struct intel_display *display, enum pipe pipe)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubji)}(h h]h }(hjShhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjSmodnameN classnameNjXj[)}j^]ja)}jTjSsb%c.intel_cpu_fifo_underrun_irq_handlerasbuh1hhjSubji)}(h h]h }(hjThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubj)}(hjh]h*}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubj;)}(hdisplayh]hdisplay}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjSubj)}(henum pipe pipeh](j)}(hjh]henum}(hj6ThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2Tubji)}(h h]h }(hjCThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2Tubh)}(hhh]j;)}(hpipeh]hpipe}(hjTThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQTubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjVTmodnameN classnameNjXj[)}j^]jS%c.intel_cpu_fifo_underrun_irq_handlerasbuh1hhj2Tubji)}(h h]h }(hjrThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2Tubj;)}(hpipeh]hpipe}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2Tubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjSubeh}(h]h ]h"]h$]h&]jjuh1jhjShhhjShMcubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjShhhjShMcubah}(h]jzSah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjShMchj|Shhubj1)}(hhh]h)}(h"handle CPU fifo underrun interrupth]h"handle CPU fifo underrun interrupt}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMchjThhubah}(h]h ]h"]h$]h&]uh1j0hj|ShhhjShMcubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjTjSjTjTjUjVuh1j&hhhjMhNhNubjX)}(hXF**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pipe`` (CPU) pipe to set state for **Description** This handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h](h)}(h**Parameters**h]jb)}(hjTh]h Parameters}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jahjTubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMghjTubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjTh]hstruct intel_display *display}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMdhjTubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMdhjUubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j|hjUhMdhjTubj})}(h/``enum pipe pipe`` (CPU) pipe to set state for h](j)}(h``enum pipe pipe``h]j)}(hj$Uh]henum pipe pipe}(hj&UhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"Uubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMehjUubj)}(hhh]h)}(h(CPU) pipe to set state forh]h(CPU) pipe to set state for}(hj=UhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9UhMehj:Uubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j|hj9UhMehjTubeh}(h]h ]h"]h$]h&]uh1jwhjTubh)}(h**Description**h]jb)}(hj_Uh]h Description}(hjaUhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj]Uubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMghjTubh)}(hThis handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h]hThis handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.}(hjuUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMghjTubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"0intel_pch_fifo_underrun_irq_handler (C function)%c.intel_pch_fifo_underrun_irq_handlerhNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hbvoid intel_pch_fifo_underrun_irq_handler (struct intel_display *display, enum pipe pch_transcoder)h]j2)}(havoid intel_pch_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pch_transcoder)h](j)}(hvoidh]hvoid}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUhhhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMubji)}(h h]h }(hjUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjUhhhjUhMubjz)}(h#intel_pch_fifo_underrun_irq_handlerh]j;)}(h#intel_pch_fifo_underrun_irq_handlerh]h#intel_pch_fifo_underrun_irq_handler}(hjUhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjUubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjUhhhjUhMubj)}(h9(struct intel_display *display, enum pipe pch_transcoder)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubji)}(h h]h }(hjUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjUubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjUhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjUubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjVmodnameN classnameNjXj[)}j^]ja)}jTjUsb%c.intel_pch_fifo_underrun_irq_handlerasbuh1hhjUubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjUubj)}(hjh]h*}(hj-VhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubj;)}(hdisplayh]hdisplay}(hj:VhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjUubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjUubj)}(henum pipe pch_transcoderh](j)}(hjh]henum}(hjSVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOVubji)}(h h]h }(hj`VhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjOVubh)}(hhh]j;)}(hpipeh]hpipe}(hjqVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnVubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjsVmodnameN classnameNjXj[)}j^]jV%c.intel_pch_fifo_underrun_irq_handlerasbuh1hhjOVubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjOVubj;)}(hpch_transcoderh]hpch_transcoder}(hjVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjOVubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjUubeh}(h]h ]h"]h$]h&]jjuh1jhjUhhhjUhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjUhhhjUhMubah}(h]jUah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjUhMhjUhhubj1)}(hhh]h)}(h"handle PCH fifo underrun interrupth]h"handle PCH fifo underrun interrupt}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjVhhubah}(h]h ]h"]h$]h&]uh1j0hjUhhhjUhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjVjSjVjTjUjVuh1j&hhhjMhNhNubjX)}(hXg**Parameters** ``struct intel_display *display`` display device instance ``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) **Description** This handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h](h)}(h**Parameters**h]jb)}(hjVh]h Parameters}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjVubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjVubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjWh]hstruct intel_display *display}(hj WhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjWubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj!WhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhMhjWubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1j|hjWhMhjVubj})}(hP``enum pipe pch_transcoder`` the PCH transcoder (same as pipe on IVB and older) h](j)}(h``enum pipe pch_transcoder``h]j)}(hjAWh]henum pipe pch_transcoder}(hjCWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?Wubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj;Wubj)}(hhh]h)}(h2the PCH transcoder (same as pipe on IVB and older)h]h2the PCH transcoder (same as pipe on IVB and older)}(hjZWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVWhMhjWWubah}(h]h ]h"]h$]h&]uh1jhj;Wubeh}(h]h ]h"]h$]h&]uh1j|hjVWhMhjVubeh}(h]h ]h"]h$]h&]uh1jwhjVubh)}(h**Description**h]jb)}(hj|Wh]h Description}(hj~WhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjzWubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjVubh)}(hThis handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.h]hThis handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjVubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+intel_check_cpu_fifo_underruns (C function) c.intel_check_cpu_fifo_underrunshNtauh1jhjMhhhNhNubj')}(hhh](j,)}(hCvoid intel_check_cpu_fifo_underruns (struct intel_display *display)h]j2)}(hBvoid intel_check_cpu_fifo_underruns(struct intel_display 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}(hjQYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>YhhhjPYhMubjz)}(hintel_check_pch_fifo_underrunsh]j;)}(hintel_check_pch_fifo_underrunsh]hintel_check_pch_fifo_underruns}(hjcYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_Yubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj>YhhhjPYhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{Yubji)}(h h]h }(hjYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{Yubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjYubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjYmodnameN classnameNjXj[)}j^]ja)}jTjeYsb c.intel_check_pch_fifo_underrunsasbuh1hhj{Yubji)}(h h]h }(hjYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{Yubj)}(hjh]h*}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{Yubj;)}(hdisplayh]hdisplay}(hjYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{Yubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjwYubah}(h]h ]h"]h$]h&]jjuh1jhj>YhhhjPYhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj:YhhhjPYhMubah}(h]j5Yah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjPYhMhj7Yhhubj1)}(hhh]h)}(h(check for PCH fifo underruns immediatelyh]h(check for PCH fifo underruns immediately}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjYhhubah}(h]h ]h"]h$]h&]uh1j0hj7YhhhjPYhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjZjSjZjTjUjVuh1j&hhhjMhNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device instance **Description** Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won't necessarily raise an interrupt.h](h)}(h**Parameters**h]jb)}(hj$Zh]h Parameters}(hj&ZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"Zubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjZubjx)}(hhh]j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjCZh]hstruct intel_display *display}(hjEZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAZubah}(h]h ]h"]h$]h&]uh1jhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhj=Zubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj\ZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXZhMhjYZubah}(h]h ]h"]h$]h&]uh1jhj=Zubeh}(h]h ]h"]h$]h&]uh1j|hjXZhMhj:Zubah}(h]h ]h"]h$]h&]uh1jwhjZubh)}(h**Description**h]jb)}(hj~Zh]h Description}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj|Zubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjZubh)}(hCheck for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won't necessarily raise an interrupt.h]hCheck for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won’t necessarily raise an interrupt.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/gpu/i915:100: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.chMhjZubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjMhhhNhNubeh}(h]display-fifo-underrun-reportingah ]h"]display fifo underrun reportingah$]h&]uh1hhj;hhhhhK_ubh)}(hhh](h)}(hPlane Configurationh]hPlane Configuration}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhKhubh)}(hX5This section covers plane configuration and composition with the primary plane, sprites, cursors and overlays. This includes the infrastructure to do atomic vsync'ed updates of all this state and also tightly coupled topics like watermark setup and computation, framebuffer compression and panel self refresh.h]hX7This section covers plane configuration and composition with the primary plane, sprites, cursors and overlays. This includes the infrastructure to do atomic vsync’ed updates of all this state and also tightly coupled topics like watermark setup and computation, framebuffer compression and panel self refresh.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjZhhubeh}(h]plane-configurationah ]h"]plane configurationah$]h&]uh1hhj;hhhhhKhubh)}(hhh](h)}(hAtomic Plane Helpersh]hAtomic Plane Helpers}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhKqubh)}(hX0The functions here are used by the atomic plane helper functions to implement legacy plane updates (i.e., drm_plane->update_plane() and drm_plane->disable_plane()). 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*planeh](j)}(hjh]hstruct}(hjO[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjK[ubji)}(h h]h }(hj\[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjK[ubh)}(hhh]j;)}(h drm_planeh]h drm_plane}(hjm[hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjj[ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjo[modnameN classnameNjXj[)}j^]ja)}jTj5[sbc.intel_plane_destroyasbuh1hhjK[ubji)}(h h]h }(hj[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjK[ubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjK[ubj;)}(hplaneh]hplane}(hj[hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjK[ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjG[ubah}(h]h ]h"]h$]h&]jjuh1jhj[hhhj [hKdubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj [hhhj [hKdubah}(h]j[ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj [hKdhj[hhubj1)}(hhh]h)}(hdestroy a planeh]hdestroy a plane}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKdhj[hhubah}(h]h ]h"]h$]h&]uh1j0hj[hhhj [hKdubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj[jSj[jTjUjVuh1j&hhhjZhNhNubjX)}(h**Parameters** ``struct drm_plane *plane`` plane to destroy **Description** Common destruction function for all types of planes (primary, cursor, sprite).h](h)}(h**Parameters**h]jb)}(hj[h]h Parameters}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj[ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhhj[ubjx)}(hhh]j})}(h-``struct drm_plane *plane`` plane to destroy h](j)}(h``struct drm_plane *plane``h]j)}(hj\h]hstruct drm_plane *plane}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKehj \ubj)}(hhh]h)}(hplane to destroyh]hplane to destroy}(hj,\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(\hKehj)\ubah}(h]h ]h"]h$]h&]uh1jhj \ubeh}(h]h ]h"]h$]h&]uh1j|hj(\hKehj \ubah}(h]h ]h"]h$]h&]uh1jwhj[ubh)}(h**Description**h]jb)}(hjN\h]h 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classnameNjXj[)}j^]j\c.intel_plane_duplicate_stateasbuh1hhj ]ubji)}(h h]h }(hjI]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ]ubj)}(hjh]h*}(hjW]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ]ubj;)}(hplaneh]hplane}(hjd]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ]ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj]ubah}(h]h ]h"]h$]h&]jjuh1jhj\hhhj\hKqubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj\hhhj\hKqubah}(h]j\ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj\hKqhj\hhubj1)}(hhh]h)}(hduplicate plane stateh]hduplicate plane state}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKqhj]hhubah}(h]h ]h"]h$]h&]uh1j0hj\hhhj\hKqubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj]jSj]jTjUjVuh1j&hhhjZhNhNubjX)}(h**Parameters** ``struct drm_plane *plane`` drm plane **Description** Allocates and returns a copy of the plane state (both common and Intel-specific) for the specified plane. **Return** The newly allocated plane state, or NULL on failure.h](h)}(h**Parameters**h]jb)}(hj]h]h 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]juah"]h$]h&]uh1jhhj^ubj)}(hjh]h*}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj;)}(hplaneh]hplane}(hj _hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj^ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj^ubj)}(hstruct drm_plane_state *stateh](j)}(hjh]hstruct}(hj%_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!_ubji)}(h h]h }(hj2_hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj!_ubh)}(hhh]j;)}(hdrm_plane_stateh]hdrm_plane_state}(hjC_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@_ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjE_modnameN classnameNjXj[)}j^]j^c.intel_plane_destroy_stateasbuh1hhj!_ubji)}(h h]h }(hja_hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj!_ubj)}(hjh]h*}(hjo_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!_ubj;)}(hstateh]hstate}(hj|_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj!_ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj^ubeh}(h]h ]h"]h$]h&]jjuh1jhjr^hhhj^hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjn^hhhj^hKubah}(h]ji^ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj^hKhjk^hhubj1)}(hhh]h)}(hdestroy plane stateh]hdestroy plane state}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj_hhubah}(h]h ]h"]h$]h&]uh1j0hjk^hhhj^hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj_jSj_jTjUjVuh1j&hhhjZhNhNubjX)}(h**Parameters** ``struct drm_plane *plane`` drm plane ``struct drm_plane_state *state`` state object to destroy **Description** Destroys the plane state (both common and Intel-specific) for the specified plane.h](h)}(h**Parameters**h]jb)}(hj_h]h Parameters}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj_ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj_ubjx)}(hhh](j})}(h&``struct drm_plane *plane`` drm plane h](j)}(h``struct drm_plane *plane``h]j)}(hj_h]hstruct drm_plane *plane}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj_ubj)}(hhh]h)}(h drm planeh]h drm plane}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hj_hKhj_ubj})}(h:``struct drm_plane_state *state`` state object to destroy h](j)}(h!``struct drm_plane_state *state``h]j)}(hj `h]hstruct drm_plane_state *state}(hj"`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj`ubj)}(hhh]h)}(hstate object to destroyh]hstate object to destroy}(hj9`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5`hKhj6`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1j|hj5`hKhj_ubeh}(h]h ]h"]h$]h&]uh1jwhj_ubh)}(h**Description**h]jb)}(hj[`h]h Description}(hj]`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjY`ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj_ubh)}(hRDestroys the plane state (both common and Intel-specific) for the specified plane.h]hRDestroys the plane state (both common and Intel-specific) for the specified plane.}(hjq`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chKhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjZhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_prepare_plane_fb (C function)c.intel_prepare_plane_fbhNtauh1jhjZhhhNhNubj')}(hhh](j,)}(h_int intel_prepare_plane_fb (struct drm_plane *_plane, struct drm_plane_state *_new_plane_state)h]j2)}(h^int intel_prepare_plane_fb(struct drm_plane *_plane, struct drm_plane_state *_new_plane_state)h](j)}(hinth]hint}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`hhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMubji)}(h h]h }(hj`hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`hhhj`hMubjz)}(hintel_prepare_plane_fbh]j;)}(hintel_prepare_plane_fbh]hintel_prepare_plane_fb}(hj`hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj`hhhj`hMubj)}(hD(struct drm_plane *_plane, struct drm_plane_state *_new_plane_state)h](j)}(hstruct drm_plane *_planeh](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubji)}(h h]h }(hj`hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubh)}(hhh]j;)}(h drm_planeh]h drm_plane}(hj`hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj`modnameN classnameNjXj[)}j^]ja)}jTj`sbc.intel_prepare_plane_fbasbuh1hhj`ubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubj)}(hjh]h*}(hj)ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubj;)}(h_planeh]h_plane}(hj6ahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj`ubj)}(h(struct drm_plane_state *_new_plane_stateh](j)}(hjh]hstruct}(hjOahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKaubji)}(h h]h }(hj\ahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKaubh)}(hhh]j;)}(hdrm_plane_stateh]hdrm_plane_state}(hjmahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjaubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjoamodnameN classnameNjXj[)}j^]jac.intel_prepare_plane_fbasbuh1hhjKaubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKaubj)}(hjh]h*}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKaubj;)}(h_new_plane_stateh]h_new_plane_state}(hjahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKaubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj`ubeh}(h]h ]h"]h$]h&]jjuh1jhj`hhhj`hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj`hhhj`hMubah}(h]j`ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj`hMhj`hhubj1)}(hhh]h)}(hPrepare fb for usage on planeh]hPrepare fb for usage on plane}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjahhubah}(h]h ]h"]h$]h&]uh1j0hj`hhhj`hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjajSjajTjUjVuh1j&hhhjZhNhNubjX)}(hX**Parameters** ``struct drm_plane *_plane`` drm plane to prepare for ``struct drm_plane_state *_new_plane_state`` the plane state being prepared **Description** Prepares a framebuffer for usage on a display plane. Generally this involves pinning the underlying object and updating the frontbuffer tracking bits. Some older platforms need special physical address handling for cursor planes. Returns 0 on success, negative error code on failure.h](h)}(h**Parameters**h]jb)}(hjah]h Parameters}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jahjaubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjaubjx)}(hhh](j})}(h6``struct drm_plane *_plane`` drm plane to prepare for h](j)}(h``struct drm_plane *_plane``h]j)}(hjbh]hstruct drm_plane *_plane}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj bubj)}(hhh]h)}(hdrm plane to prepare forh]hdrm plane to prepare for}(hj*bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&bhMhj'bubah}(h]h ]h"]h$]h&]uh1jhj bubeh}(h]h ]h"]h$]h&]uh1j|hj&bhMhjbubj})}(hL``struct drm_plane_state *_new_plane_state`` the plane state being prepared h](j)}(h,``struct drm_plane_state *_new_plane_state``h]j)}(hjJbh]h(struct drm_plane_state *_new_plane_state}(hjLbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHbubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjDbubj)}(hhh]h)}(hthe plane state being preparedh]hthe plane state being prepared}(hjcbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_bhMhj`bubah}(h]h ]h"]h$]h&]uh1jhjDbubeh}(h]h ]h"]h$]h&]uh1j|hj_bhMhjbubeh}(h]h ]h"]h$]h&]uh1jwhjaubh)}(h**Description**h]jb)}(hjbh]h Description}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjbubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjaubh)}(hPrepares a framebuffer for usage on a display plane. Generally this involves pinning the underlying object and updating the frontbuffer tracking bits. Some older platforms need special physical address handling for cursor planes.h]hPrepares a framebuffer for usage on a display plane. Generally this involves pinning the underlying object and updating the frontbuffer tracking bits. Some older platforms need special physical address handling for cursor planes.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjaubh)}(h5Returns 0 on success, negative error code on failure.h]h5Returns 0 on success, negative error code on failure.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjaubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjZhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_cleanup_plane_fb (C function)c.intel_cleanup_plane_fbhNtauh1jhjZhhhNhNubj')}(hhh](j,)}(h_void intel_cleanup_plane_fb (struct drm_plane *plane, struct drm_plane_state *_old_plane_state)h]j2)}(h^void intel_cleanup_plane_fb(struct drm_plane *plane, struct drm_plane_state *_old_plane_state)h](j)}(hvoidh]hvoid}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMubji)}(h h]h }(hjbhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbhhhjbhMubjz)}(hintel_cleanup_plane_fbh]j;)}(hintel_cleanup_plane_fbh]hintel_cleanup_plane_fb}(hjbhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjbubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjbhhhjbhMubj)}(hC(struct drm_plane *plane, struct drm_plane_state *_old_plane_state)h](j)}(hstruct drm_plane *planeh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubji)}(h h]h }(hj#chhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubh)}(hhh]j;)}(h drm_planeh]h drm_plane}(hj4chhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj1cubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj6cmodnameN classnameNjXj[)}j^]ja)}jTjbsbc.intel_cleanup_plane_fbasbuh1hhjcubji)}(h h]h }(hjTchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubj)}(hjh]h*}(hjbchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj;)}(hplaneh]hplane}(hjochhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjcubj)}(h(struct drm_plane_state *_old_plane_stateh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubh)}(hhh]j;)}(hdrm_plane_stateh]hdrm_plane_state}(hjchhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjcmodnameN classnameNjXj[)}j^]jPcc.intel_cleanup_plane_fbasbuh1hhjcubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcubj)}(hjh]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj;)}(h_old_plane_stateh]h_old_plane_state}(hjchhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjcubeh}(h]h ]h"]h$]h&]jjuh1jhjbhhhjbhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjbhhhjbhMubah}(h]jbah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjbhMhjbhhubj1)}(hhh]h)}(hCleans up an fb after plane useh]hCleans up an fb after plane use}(hj dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjdhhubah}(h]h ]h"]h$]h&]uh1j0hjbhhhjbhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj!djSj!djTjUjVuh1j&hhhjZhNhNubjX)}(h**Parameters** ``struct drm_plane *plane`` drm plane to clean up for ``struct drm_plane_state *_old_plane_state`` the state from the previous modeset **Description** Cleans up a framebuffer that has just been removed from a plane.h](h)}(h**Parameters**h]jb)}(hj+dh]h Parameters}(hj-dhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj)dubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj%dubjx)}(hhh](j})}(h6``struct drm_plane *plane`` drm plane to clean up for h](j)}(h``struct drm_plane *plane``h]j)}(hjJdh]hstruct drm_plane *plane}(hjLdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHdubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhjDdubj)}(hhh]h)}(hdrm plane to clean up forh]hdrm plane to clean up for}(hjcdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_dhMhj`dubah}(h]h ]h"]h$]h&]uh1jhjDdubeh}(h]h ]h"]h$]h&]uh1j|hj_dhMhjAdubj})}(hQ``struct drm_plane_state *_old_plane_state`` the state from the previous modeset h](j)}(h,``struct drm_plane_state *_old_plane_state``h]j)}(hjdh]h(struct drm_plane_state *_old_plane_state}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj}dubj)}(hhh]h)}(h#the state from the previous modeseth]h#the state from the previous modeset}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjdubah}(h]h ]h"]h$]h&]uh1jhj}dubeh}(h]h ]h"]h$]h&]uh1j|hjdhMhjAdubeh}(h]h ]h"]h$]h&]uh1jwhj%dubh)}(h**Description**h]jb)}(hjdh]h Description}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjdubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj%dubh)}(h@Cleans up a framebuffer that has just been removed from a plane.h]h@Cleans up a framebuffer that has just been removed from a plane.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:118: ./drivers/gpu/drm/i915/display/intel_atomic_plane.chMhj%dubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjZhhhNhNubeh}(h]atomic-plane-helpersah ]h"]atomic plane helpersah$]h&]uh1hhj;hhhhhKqubh)}(hhh](h)}(hAsynchronous Page Fliph]hAsynchronous Page Flip}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhhhhhKzubh)}(hAsynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC flag. Currently async flip is only supported via the drmModePageFlip IOCTL. Correspondingly, support is currently added for primary plane only.h]hAsynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC flag. Currently async flip is only supported via the drmModePageFlip IOCTL. Correspondingly, support is currently added for primary plane only.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:124: ./drivers/gpu/drm/i915/display/intel_display.chMhjdhhubh)}(hAsync flip can only change the plane surface address, so anything else changing is rejected from the intel_async_flip_check_hw() function. Once this check is cleared, flip done interrupt is enabled using the intel_crtc_enable_flip_done() function.h]hAsync flip can only change the plane surface address, so anything else changing is rejected from the intel_async_flip_check_hw() function. Once this check is cleared, flip done interrupt is enabled using the intel_crtc_enable_flip_done() function.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:124: ./drivers/gpu/drm/i915/display/intel_display.chMhjdhhubh)}(hXLAs soon as the surface address register is written, flip done interrupt is generated and the requested events are sent to the userspace in the interrupt handler itself. The timestamp and sequence sent during the flip done event correspond to the last vblank and have no relation to the actual time when the flip done event was sent.h]hXLAs soon as the surface address register is written, flip done interrupt is generated and the requested events are sent to the userspace in the interrupt handler itself. The timestamp and sequence sent during the flip done event correspond to the last vblank and have no relation to the actual time when the flip done event was sent.}(hj!ehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:124: ./drivers/gpu/drm/i915/display/intel_display.chMhjdhhubeh}(h]asynchronous-page-flipah ]h"]asynchronous page flipah$]h&]uh1hhj;hhhhhKzubh)}(hhh](h)}(hOutput Probingh]hOutput Probing}(hj;ehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8ehhhhhKubh)}(hThis section covers output probing and related infrastructure like the hotplug interrupt storm detection and mitigation code. Note that the i915 driver still uses most of the common DRM helper code for output probing, so those sections fully apply.h]hThis section covers output probing and related infrastructure like the hotplug interrupt storm detection and mitigation code. Note that the i915 driver still uses most of the common DRM helper code for output probing, so those sections fully apply.}(hjIehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj8ehhubeh}(h]output-probingah ]h"]output probingah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hHotplugh]hHotplug}(hjbehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_ehhhhhKubh)}(hSimply put, hotplug occurs when a display is connected to or disconnected from the system. However, there may be adapters and docking stations and Display Port short pulses and MST devices involved, complicating matters.h]hSimply put, hotplug occurs when a display is connected to or disconnected from the system. However, there may be adapters and docking stations and Display Port short pulses and MST devices involved, complicating matters.}(hjpehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK(hj_ehhubh)}(hCHotplug in i915 is handled in many different levels of abstraction.h]hCHotplug in i915 is handled in many different levels of abstraction.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK,hj_ehhubh)}(hXThe platform dependent interrupt handling code in i915_irq.c enables, disables, and does preliminary handling of the interrupts. The interrupt handlers gather the hotplug detect (HPD) information from relevant registers into a platform independent mask of hotplug pins that have fired.h]hXThe platform dependent interrupt handling code in i915_irq.c enables, disables, and does preliminary handling of the interrupts. The interrupt handlers gather the hotplug detect (HPD) information from relevant registers into a platform independent mask of hotplug pins that have fired.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK.hj_ehhubh)}(hThe platform independent interrupt handler intel_hpd_irq_handler() in intel_hotplug.c does hotplug irq storm detection and mitigation, and passes further processing to appropriate bottom halves (Display Port specific and regular hotplug).h]hThe platform independent interrupt handler intel_hpd_irq_handler() in intel_hotplug.c does hotplug irq storm detection and mitigation, and passes further processing to appropriate bottom halves (Display Port specific and regular hotplug).}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK3hj_ehhubh)}(hThe Display Port work function i915_digport_work_func() calls into intel_dp_hpd_pulse() via hooks, which handles DP short pulses and DP MST long pulses, with failures and non-MST long pulses triggering regular hotplug processing on the connector.h]hThe Display Port work function i915_digport_work_func() calls into intel_dp_hpd_pulse() via hooks, which handles DP short pulses and DP MST long pulses, with failures and non-MST long pulses triggering regular hotplug processing on the connector.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK8hj_ehhubh)}(hThe regular hotplug work function i915_hotplug_work_func() calls connector detect hooks, and, if connector status changes, triggers sending of hotplug uevent to userspace via drm_kms_helper_hotplug_event().h]hThe regular hotplug work function i915_hotplug_work_func() calls connector detect hooks, and, if connector status changes, triggers sending of hotplug uevent to userspace via drm_kms_helper_hotplug_event().}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chK=hj_ehhubh)}(hFinally, the userspace is responsible for triggering a modeset upon receiving the hotplug uevent, disabling or enabling the crtc as needed.h]hFinally, the userspace is responsible for triggering a modeset upon receiving the hotplug uevent, disabling or enabling the crtc as needed.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chKAhj_ehhubh)}(hXThe hotplug interrupt storm detection and mitigation code keeps track of the number of interrupts per hotplug pin per a period of time, and if the number of interrupts exceeds a certain threshold, the interrupt is disabled for a while before being re-enabled. The intention is to mitigate issues raising from broken hardware triggering massive amounts of interrupts and grinding the system to a halt.h]hXThe hotplug interrupt storm detection and mitigation code keeps track of the number of interrupts per hotplug pin per a period of time, and if the number of interrupts exceeds a certain threshold, the interrupt is disabled for a while before being re-enabled. The intention is to mitigate issues raising from broken hardware triggering massive amounts of interrupts and grinding the system to a halt.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chKDhj_ehhubh)}(hXCurrent implementation expects that hotplug interrupt storm will not be seen when display port sink is connected, hence on platforms whose DP callback is handled by i915_digport_work_func reenabling of hpd is not performed (it was never expected to be disabled in the first place ;) ) this is specific to DP sinks handled by this routine and any other display such as HDMI or DVI enabled on the same port will have proper logic since it will use i915_hotplug_work_func where this logic is handled.h]hXCurrent implementation expects that hotplug interrupt storm will not be seen when display port sink is connected, hence on platforms whose DP callback is handled by i915_digport_work_func reenabling of hpd is not performed (it was never expected to be disabled in the first place ;) ) this is specific to DP sinks handled by this routine and any other display such as HDMI or DVI enabled on the same port will have proper logic since it will use i915_hotplug_work_func where this logic is handled.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:138: ./drivers/gpu/drm/i915/display/intel_hotplug.chKKhj_ehhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_hpd_pin_default (C function)c.intel_hpd_pin_defaulthNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(h3enum hpd_pin intel_hpd_pin_default (enum port port)h]j2)}(h2enum hpd_pin intel_hpd_pin_default(enum port port)h](j)}(hjh]henum}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj fhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKWubji)}(h h]h }(hjfhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj fhhhjfhKWubh)}(hhh]j;)}(hhpd_pinh]hhpd_pin}(hj/fhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj,fubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj1fmodnameN classnameNjXj[)}j^]ja)}jTintel_hpd_pin_defaultsbc.intel_hpd_pin_defaultasbuh1hhj fhhhjfhKWubji)}(h h]h }(hjPfhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj fhhhjfhKWubjz)}(hintel_hpd_pin_defaulth]j;)}(hjMfh]hintel_hpd_pin_default}(hjbfhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj^fubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj fhhhjfhKWubj)}(h(enum port port)h]j)}(henum port porth](j)}(hjh]henum}(hj}fhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyfubji)}(h h]h }(hjfhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjyfubh)}(hhh]j;)}(hporth]hport}(hjfhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjfmodnameN classnameNjXj[)}j^]jKfc.intel_hpd_pin_defaultasbuh1hhjyfubji)}(h h]h }(hjfhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjyfubj;)}(hporth]hport}(hjfhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjyfubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjufubah}(h]h ]h"]h$]h&]jjuh1jhj fhhhjfhKWubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjfhhhjfhKWubah}(h]jfah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjfhKWhjfhhubj1)}(hhh]h)}(h0return default pin associated with certain port.h]h0return default pin associated with certain port.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKWhjfhhubah}(h]h ]h"]h$]h&]uh1j0hjfhhhjfhKWubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj gjSj gjTjUjVuh1j&hhhj_ehNhNubjX)}(h**Parameters** ``enum port port`` the hpd port to get associated pin **Description** It is only valid and used by digital port encoder. Return pin that is associatade with **port**.h](h)}(h**Parameters**h]jb)}(hjgh]h Parameters}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjgubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK[hj gubjx)}(hhh]j})}(h6``enum port port`` the hpd port to get associated pin h](j)}(h``enum port port``h]j)}(hj2gh]henum port port}(hj4ghhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0gubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKXhj,gubj)}(hhh]h)}(h"the hpd port to get associated pinh]h"the hpd port to get associated pin}(hjKghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGghKXhjHgubah}(h]h ]h"]h$]h&]uh1jhj,gubeh}(h]h ]h"]h$]h&]uh1j|hjGghKXhj)gubah}(h]h ]h"]h$]h&]uh1jwhj gubh)}(h**Description**h]jb)}(hjmgh]h Description}(hjoghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjkgubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKZhj gubh)}(h2It is only valid and used by digital port encoder.h]h2It is only valid and used by digital port encoder.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKZhj gubh)}(h-Return pin that is associatade with **port**.h](h$Return pin that is associatade with }(hjghhhNhNubjb)}(h**port**h]hport}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjgubh.}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK\hj gubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_hpd_irq_storm_detect (C function)c.intel_hpd_irq_storm_detecthNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(h`bool intel_hpd_irq_storm_detect (struct intel_display *display, enum hpd_pin pin, bool long_hpd)h]j2)}(h_bool intel_hpd_irq_storm_detect(struct intel_display *display, enum hpd_pin pin, bool long_hpd)h](j)}(hjh]hbool}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjghhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKyubji)}(h h]h }(hjghhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjghhhjghKyubjz)}(hintel_hpd_irq_storm_detecth]j;)}(hintel_hpd_irq_storm_detecth]hintel_hpd_irq_storm_detect}(hjghhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjgubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjghhhjghKyubj)}(h@(struct intel_display *display, enum hpd_pin pin, bool long_hpd)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hubji)}(h h]h }(hjhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj hubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj-hhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj*hubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj/hmodnameN classnameNjXj[)}j^]ja)}jTjgsbc.intel_hpd_irq_storm_detectasbuh1hhj hubji)}(h h]h }(hjMhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj hubj)}(hjh]h*}(hj[hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hubj;)}(hdisplayh]hdisplay}(hjhhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj hubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjhubj)}(henum hpd_pin pinh](j)}(hjh]henum}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hubji)}(h h]h }(hjhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj}hubh)}(hhh]j;)}(hhpd_pinh]hhpd_pin}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjhmodnameN classnameNjXj[)}j^]jIhc.intel_hpd_irq_storm_detectasbuh1hhj}hubji)}(h h]h }(hjhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj}hubj;)}(hpinh]hpin}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj}hubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjhubj)}(h bool long_hpdh](j)}(hjh]hbool}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubji)}(h h]h }(hjhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhubj;)}(hlong_hpdh]hlong_hpd}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjhubeh}(h]h ]h"]h$]h&]jjuh1jhjghhhjghKyubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjghhhjghKyubah}(h]jgah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjghKyhjghhubj1)}(hhh]h)}(h.gather stats and detect HPD IRQ storm on a pinh]h.gather stats and detect HPD IRQ storm on a pin}(hj)ihhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKyhj&ihhubah}(h]h ]h"]h$]h&]uh1j0hjghhhjghKyubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjAijSjAijTjUjVuh1j&hhhj_ehNhNubjX)}(hX~**Parameters** ``struct intel_display *display`` display device ``enum hpd_pin pin`` the pin to gather stats on ``bool long_hpd`` whether the HPD IRQ was long or short **Description** Gather stats about HPD IRQs from the specified **pin**, and detect IRQ storms. Only the pin specific stats and state are changed, the caller is responsible for further action. The number of IRQs that are allowed within **HPD_STORM_DETECT_PERIOD** is stored in **display->hotplug.hpd_storm_threshold** which defaults to **HPD_STORM_DEFAULT_THRESHOLD**. Long IRQs count as +10 to this threshold, and short IRQs count as +1. If this threshold is exceeded, it's considered an IRQ storm and the IRQ state is set to **HPD_MARK_DISABLED**. By default, most systems will only count long IRQs towards :c:type:`display->hotplug `.hpd_storm_threshold. However, some older systems also suffer from short IRQ storms and must also track these. Because short IRQ storms are naturally caused by sideband interactions with DP MST devices, short IRQ detection is only enabled for systems without DP MST support. Systems which are new enough to support DP MST are far less likely to suffer from IRQ storms at all, so this is fine. The HPD threshold can be controlled through i915_hpd_storm_ctl in debugfs, and should only be adjusted for automated hotplug testing. Return true if an IRQ storm was detected on **pin**.h](h)}(h**Parameters**h]jb)}(hjKih]h Parameters}(hjMihhhNhNubah}(h]h ]h"]h$]h&]uh1jahjIiubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK}hjEiubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjjih]hstruct intel_display *display}(hjlihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhiubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKzhjdiubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKzhjiubah}(h]h ]h"]h$]h&]uh1jhjdiubeh}(h]h ]h"]h$]h&]uh1j|hjihKzhjaiubj})}(h0``enum hpd_pin pin`` the pin to gather stats on h](j)}(h``enum hpd_pin pin``h]j)}(hjih]henum hpd_pin pin}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK{hjiubj)}(hhh]h)}(hthe pin to gather stats onh]hthe pin to gather stats on}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihK{hjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1j|hjihK{hjaiubj})}(h8``bool long_hpd`` whether the HPD IRQ was long or short h](j)}(h``bool long_hpd``h]j)}(hjih]h bool long_hpd}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK|hjiubj)}(hhh]h)}(h%whether the HPD IRQ was long or shorth]h%whether the HPD IRQ was long or short}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihK|hjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1j|hjihK|hjaiubeh}(h]h ]h"]h$]h&]uh1jwhjEiubh)}(h**Description**h]jb)}(hjjh]h Description}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK~hjEiubh)}(hGather stats about HPD IRQs from the specified **pin**, and detect IRQ storms. Only the pin specific stats and state are changed, the caller is responsible for further action.h](h/Gather stats about HPD IRQs from the specified }(hj-jhhhNhNubjb)}(h**pin**h]hpin}(hj5jhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-jubhy, and detect IRQ storms. Only the pin specific stats and state are changed, the caller is responsible for further action.}(hj-jhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chK~hjEiubh)}(hXdThe number of IRQs that are allowed within **HPD_STORM_DETECT_PERIOD** is stored in **display->hotplug.hpd_storm_threshold** which defaults to **HPD_STORM_DEFAULT_THRESHOLD**. Long IRQs count as +10 to this threshold, and short IRQs count as +1. If this threshold is exceeded, it's considered an IRQ storm and the IRQ state is set to **HPD_MARK_DISABLED**.h](h+The number of IRQs that are allowed within }(hjNjhhhNhNubjb)}(h**HPD_STORM_DETECT_PERIOD**h]hHPD_STORM_DETECT_PERIOD}(hjVjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNjubh is stored in }(hjNjhhhNhNubjb)}(h(**display->hotplug.hpd_storm_threshold**h]h$display->hotplug.hpd_storm_threshold}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNjubh which defaults to }(hjNjhhhNhNubjb)}(h**HPD_STORM_DEFAULT_THRESHOLD**h]hHPD_STORM_DEFAULT_THRESHOLD}(hjzjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNjubh. Long IRQs count as +10 to this threshold, and short IRQs count as +1. If this threshold is exceeded, it’s considered an IRQ storm and the IRQ state is set to }(hjNjhhhNhNubjb)}(h**HPD_MARK_DISABLED**h]hHPD_MARK_DISABLED}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNjubh.}(hjNjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKhjEiubh)}(hXBy default, most systems will only count long IRQs towards :c:type:`display->hotplug `.hpd_storm_threshold. However, some older systems also suffer from short IRQ storms and must also track these. Because short IRQ storms are naturally caused by sideband interactions with DP MST devices, short IRQ detection is only enabled for systems without DP MST support. Systems which are new enough to support DP MST are far less likely to suffer from IRQ storms at all, so this is fine.h](h;By default, most systems will only count long IRQs towards }(hjjhhhNhNubh)}(h$:c:type:`display->hotplug `h]j)}(hjjh]hdisplay->hotplug}(hjjhhhNhNubah}(h]h ](xrefjRc-typeeh"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXj[)}j^]sb reftargetdisplayuh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKhjjubhX.hpd_storm_threshold. However, some older systems also suffer from short IRQ storms and must also track these. Because short IRQ storms are naturally caused by sideband interactions with DP MST devices, short IRQ detection is only enabled for systems without DP MST support. Systems which are new enough to support DP MST are far less likely to suffer from IRQ storms at all, so this is fine.}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjjhKhjEiubh)}(hThe HPD threshold can be controlled through i915_hpd_storm_ctl in debugfs, and should only be adjusted for automated hotplug testing.h]hThe HPD threshold can be controlled through i915_hpd_storm_ctl in debugfs, and should only be adjusted for automated hotplug testing.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKhjEiubh)}(h4Return true if an IRQ storm was detected on **pin**.h](h,Return true if an IRQ storm was detected on }(hjjhhhNhNubjb)}(h**pin**h]hpin}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjjubh.}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chKhjEiubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_hpd_trigger_irq (C function)c.intel_hpd_trigger_irqhNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(h@void intel_hpd_trigger_irq (struct intel_digital_port *dig_port)h]j2)}(h?void intel_hpd_trigger_irq(struct intel_digital_port *dig_port)h](j)}(hvoidh]hvoid}(hj,khhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(khhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMubji)}(h h]h }(hj;khhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj(khhhj:khMubjz)}(hintel_hpd_trigger_irqh]j;)}(hintel_hpd_trigger_irqh]hintel_hpd_trigger_irq}(hjMkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIkubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj(khhhj:khMubj)}(h%(struct intel_digital_port *dig_port)h]j)}(h#struct intel_digital_port *dig_porth](j)}(hjh]hstruct}(hjikhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjekubji)}(h h]h }(hjvkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjekubh)}(hhh]j;)}(hintel_digital_porth]hintel_digital_port}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjkubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjkmodnameN classnameNjXj[)}j^]ja)}jTjOksbc.intel_hpd_trigger_irqasbuh1hhjekubji)}(h h]h }(hjkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjekubj)}(hjh]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjekubj;)}(hdig_porth]hdig_port}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjekubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjakubah}(h]h ]h"]h$]h&]jjuh1jhj(khhhj:khMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj$khhhj:khMubah}(h]jkah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj:khMhj!khhubj1)}(hhh]h)}(h#trigger an hpd irq event for a porth]h#trigger an hpd irq event for a port}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjkhhubah}(h]h ]h"]h$]h&]uh1j0hj!khhhj:khMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjljSjljTjUjVuh1j&hhhj_ehNhNubjX)}(h**Parameters** ``struct intel_digital_port *dig_port`` digital port **Description** Trigger an HPD interrupt event for the given port, emulating a short pulse generated by the sink, and schedule the dig port work to handle it.h](h)}(h**Parameters**h]jb)}(hjlh]h Parameters}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj lubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjlubjx)}(hhh]j})}(h5``struct intel_digital_port *dig_port`` digital port h](j)}(h'``struct intel_digital_port *dig_port``h]j)}(hj-lh]h#struct intel_digital_port *dig_port}(hj/lhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+lubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhj'lubj)}(hhh]h)}(h digital porth]h digital port}(hjFlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBlhMhjClubah}(h]h ]h"]h$]h&]uh1jhj'lubeh}(h]h ]h"]h$]h&]uh1j|hjBlhMhj$lubah}(h]h ]h"]h$]h&]uh1jwhjlubh)}(h**Description**h]jb)}(hjhlh]h Description}(hjjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjflubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjlubh)}(hTrigger an HPD interrupt event for the given port, emulating a short pulse generated by the sink, and schedule the dig port work to handle it.h]hTrigger an HPD interrupt event for the given port, emulating a short pulse generated by the sink, and schedule the dig port work to handle it.}(hj~lhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjlubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_hpd_irq_handler (C function)c.intel_hpd_irq_handlerhNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(hWvoid intel_hpd_irq_handler (struct intel_display *display, u32 pin_mask, u32 long_mask)h]j2)}(hVvoid intel_hpd_irq_handler(struct intel_display *display, u32 pin_mask, u32 long_mask)h](j)}(hvoidh]hvoid}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM?ubji)}(h h]h }(hjlhhhNhNubah}(h]h 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The platform specific irq handlers call the platform specific hotplug irq handlers, which read and decode the appropriate registers into bitmasks about hpd pins that have triggered (**pin_mask**), and which of those pins may be long pulses (**long_mask**). The **long_mask** is ignored if the port corresponding to the pin is not a digital port. Here, we do hotplug irq storm detection and mitigation, and pass further processing to appropriate bottom halves.h](h)}(h**Parameters**h]jb)}(hjnh]h Parameters}(hj!nhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjnubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMChjnubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hj>nh]hstruct intel_display *display}(hj@nhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmode_config.mutex, we do the actual hotplug enabling in a separate worker. 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Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. On Valleyview and Cherryview systems, this also happens when we shut off all of the powerwells.h]hXThis function enables polling for all connectors which support HPD. Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. 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Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. On Valleyview and Cherryview systems, this also happens when we shut off all of the powerwells.h]hXThis function disables polling for all connectors which support HPD. Under certain conditions HPD may not be functional. On most Intel GPUs, this happens when we enter runtime suspend. On Valleyview and Cherryview systems, this also happens when we shut off all of the powerwells.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM{hjsubh)}(hSince this function can get called in contexts where we're already holding dev->mode_config.mutex, we do the actual hotplug enabling in a separate worker.h]hSince this function can get called in contexts where we’re already holding dev->mode_config.mutex, we do the actual hotplug enabling in a separate worker.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjsubh)}(h^Also used during driver init to initialize connector->polled appropriately for all connectors.h]h^Also used during driver init to initialize connector->polled appropriately for all connectors.}(hj#thhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjsubh)}(h7Also see: intel_hpd_init() and intel_hpd_poll_enable().h]h7Also see: intel_hpd_init() and intel_hpd_poll_enable().}(hj2thhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_hpd_block (C function)c.intel_hpd_blockhNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(h4void intel_hpd_block (struct intel_encoder *encoder)h]j2)}(h3void intel_hpd_block(struct intel_encoder *encoder)h](j)}(hvoidh]hvoid}(hjathhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]thhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMubji)}(h h]h }(hjpthhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]thhhjothMubjz)}(hintel_hpd_blockh]j;)}(hintel_hpd_blockh]hintel_hpd_block}(hjthhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~tubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj]thhhjothMubj)}(h(struct intel_encoder *encoder)h]j)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubji)}(h h]h }(hjthhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjtubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hjthhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjtubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjtmodnameN classnameNjXj[)}j^]ja)}jTjtsbc.intel_hpd_blockasbuh1hhjtubji)}(h h]h }(hjthhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjtubj)}(hjh]h*}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubj;)}(hencoderh]hencoder}(hjthhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjtubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjtubah}(h]h ]h"]h$]h&]jjuh1jhj]thhhjothMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjYthhhjothMubah}(h]jTtah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjothMhjVthhubj1)}(hhh]h)}(h(Block handling of HPD IRQs on an HPD pinh]h(Block handling of HPD IRQs on an HPD pin}(hj!uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhjuhhubah}(h]h ]h"]h$]h&]uh1j0hjVthhhjothMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj9ujSj9ujTjUjVuh1j&hhhj_ehNhNubjX)}(hXy**Parameters** ``struct intel_encoder *encoder`` Encoder to block the HPD handling for **Description** Blocks the handling of HPD IRQs on the HPD pin of **encoder**. On return: - It's guaranteed that the blocked encoders' HPD pulse handler (via intel_digital_port::hpd_pulse()) is not running. - The hotplug event handling (via intel_encoder::hotplug()) of an HPD IRQ pending at the time this function is called may be still running. - Detection on the encoder's connector (via drm_connector_helper_funcs::detect_ctx(), drm_connector_funcs::detect()) remains allowed, for instance as part of userspace connector probing, or DRM core's connector polling. The call must be followed by calling intel_hpd_unblock(), or intel_hpd_clear_and_unblock(). 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]h"]h$]h&]uh1jahjuubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhj=uubh)}(h>Blocks the handling of HPD IRQs on the HPD pin of **encoder**.h](h2Blocks the handling of HPD IRQs on the HPD pin of }(hjuhhhNhNubjb)}(h **encoder**h]hencoder}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjuubh.}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chMhj=uubh)}(h On return:h]h On return:}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM hj=uubj:)}(hhh](j:)}(hrIt's guaranteed that the blocked encoders' HPD pulse handler (via intel_digital_port::hpd_pulse()) is not running.h]h)}(hrIt's guaranteed that the blocked encoders' HPD pulse handler (via intel_digital_port::hpd_pulse()) is not running.h]hvIt’s guaranteed that the blocked encoders’ HPD pulse handler (via intel_digital_port::hpd_pulse()) is not running.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM"hjuubah}(h]h ]h"]h$]h&]uh1j:hjuubj:)}(hThe hotplug event handling (via intel_encoder::hotplug()) of an HPD IRQ pending at the time this function is called may be still running.h]h)}(hThe hotplug event handling (via intel_encoder::hotplug()) of an HPD IRQ pending at the time this function is called may be still running.h]hThe hotplug event handling (via intel_encoder::hotplug()) of an HPD IRQ pending at the time this function is called may be still running.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM$hjuubah}(h]h ]h"]h$]h&]uh1j:hjuubj:)}(hDetection on the encoder's connector (via drm_connector_helper_funcs::detect_ctx(), drm_connector_funcs::detect()) remains allowed, for instance as part of userspace connector probing, or DRM core's connector polling. h]h)}(hDetection on the encoder's connector (via drm_connector_helper_funcs::detect_ctx(), drm_connector_funcs::detect()) remains allowed, for instance as part of userspace connector probing, or DRM core's connector polling.h]hDetection on the encoder’s connector (via drm_connector_helper_funcs::detect_ctx(), drm_connector_funcs::detect()) remains allowed, for instance as part of userspace connector probing, or DRM core’s connector polling.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM'hjvubah}(h]h ]h"]h$]h&]uh1j:hjuubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjuhM"hj=uubh)}(h[The call must be followed by calling intel_hpd_unblock(), or intel_hpd_clear_and_unblock().h]h[The call must be followed by calling intel_hpd_unblock(), or intel_hpd_clear_and_unblock().}(hj7vhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM,hj=uubh)}(hzNote that the handling of HPD IRQs for another encoder using the same HPD pin as that of **encoder** will be also blocked.h](hYNote that the handling of HPD IRQs for another encoder using the same HPD pin as that of }(hjFvhhhNhNubjb)}(h **encoder**h]hencoder}(hjNvhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFvubh will be also blocked.}(hjFvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:141: ./drivers/gpu/drm/i915/display/intel_hotplug.chM/hj=uubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj_ehhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_hpd_unblock (C function)c.intel_hpd_unblockhNtauh1jhj_ehhhNhNubj')}(hhh](j,)}(h6void intel_hpd_unblock (struct intel_encoder *encoder)h]j2)}(h5void intel_hpd_unblock(struct intel_encoder *encoder)h](j)}(hvoidh]hvoid}(hjvhhhNhNubah}(h]h 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]jah"]h$]h&]uh1jhjzubj;)}(hencoderh]hencoder}(hj7{hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjzubj)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hconsth]hconst}(hjP{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL{ubji)}(h h]h }(hj^{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjL{ubj)}(hjh]hstruct}(hjl{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL{ubji)}(h h]h }(hjy{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjL{ubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hj{hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj{modnameN classnameNjXj[)}j^]j{c.intel_audio_codec_enableasbuh1hhjL{ubji)}(h h]h }(hj{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjL{ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL{ubj;)}(h crtc_stateh]h crtc_state}(hj{hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjL{ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjzubj)}(h,const struct drm_connector_state *conn_stateh](j)}(hjR{h]hconst}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubji)}(h h]h }(hj{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{ubj)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubji)}(h h]h }(hj|hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{ubh)}(hhh]j;)}(hdrm_connector_stateh]hdrm_connector_state}(hj|hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj|modnameN classnameNjXj[)}j^]j{c.intel_audio_codec_enableasbuh1hhj{ubji)}(h h]h }(hj3|hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{ubj)}(hjh]h*}(hjA|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj;)}(h conn_stateh]h conn_state}(hjN|hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjzubeh}(h]h ]h"]h$]h&]jjuh1jhjzhhhjzhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjzhhhjzhMubah}(h]jzah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjzhMhjzhhubj1)}(hhh]h)}(h#Enable the audio codec for HD audioh]h#Enable the audio codec for HD audio}(hjx|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhju|hhubah}(h]h ]h"]h$]h&]uh1j0hjzhhhjzhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj|jSj|jTjUjVuh1j&hhhjyhNhNubjX)}(hX**Parameters** ``struct intel_encoder *encoder`` encoder on which to enable audio ``const struct intel_crtc_state *crtc_state`` pointer to the current crtc state. ``const struct drm_connector_state *conn_state`` pointer to the current connector state. **Description** The enable sequences may only be performed after enabling the transcoder and port, and after completed link training.h](h)}(h**Parameters**h]jb)}(hj|h]h Parameters}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj|ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj|ubjx)}(hhh](j})}(hC``struct intel_encoder *encoder`` encoder on which to enable audio h](j)}(h!``struct intel_encoder *encoder``h]j)}(hj|h]hstruct intel_encoder *encoder}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: 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*conn_state}(hj-}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)}ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj%}ubj)}(hhh]h)}(h'pointer to the current connector state.h]h'pointer to the current connector state.}(hjD}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@}hMhjA}ubah}(h]h ]h"]h$]h&]uh1jhj%}ubeh}(h]h ]h"]h$]h&]uh1j|hj@}hMhj|ubeh}(h]h ]h"]h$]h&]uh1jwhj|ubh)}(h**Description**h]jb)}(hjf}h]h Description}(hjh}hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjd}ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj|ubh)}(huThe enable sequences may only be performed after enabling the transcoder and port, and after completed link training.h]huThe enable sequences may only be performed after enabling the transcoder and port, and after completed link training.}(hj|}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: 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]juah"]h$]h&]uh1jhhjV~ubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hj~hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj~modnameN classnameNjXj[)}j^]j"~c.intel_audio_codec_disableasbuh1hhjV~ubji)}(h h]h }(hj~hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjV~ubj)}(hjh]h*}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjV~ubj;)}(hold_crtc_stateh]hold_crtc_state}(hj~hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjV~ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj}ubj)}(h0const struct drm_connector_state *old_conn_stateh](j)}(hjR{h]hconst}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubji)}(h h]h }(hj~hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~ubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~ubh)}(hhh]j;)}(hdrm_connector_stateh]hdrm_connector_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]j"~c.intel_audio_codec_disableasbuh1hhj~ubji)}(h h]h }(hj<hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~ubj)}(hjh]h*}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj;)}(hold_conn_stateh]hold_conn_state}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj}ubeh}(h]h ]h"]h$]h&]jjuh1jhj}hhhj}hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj}hhhj}hMubah}(h]j}ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj}hMhj}hhubj1)}(hhh]h)}(h$Disable the audio codec for HD audioh]h$Disable the audio codec for HD audio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj~hhubah}(h]h ]h"]h$]h&]uh1j0hj}hhhj}hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjyhNhNubjX)}(hXh**Parameters** ``struct intel_encoder *encoder`` encoder on which to disable audio ``const struct intel_crtc_state *old_crtc_state`` pointer to the old crtc state. ``const struct drm_connector_state *old_conn_state`` pointer to the old connector state. **Description** The disable sequences must be performed before disabling the transcoder or port.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjubjx)}(hhh](j})}(hD``struct intel_encoder *encoder`` encoder on which to disable audio h](j)}(h!``struct intel_encoder *encoder``h]j)}(hjh]hstruct intel_encoder *encoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjubj)}(hhh]h)}(h!encoder on which to disable audioh]h!encoder on which to disable audio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hQ``const struct intel_crtc_state *old_crtc_state`` pointer to the old crtc state. h](j)}(h1``const struct intel_crtc_state *old_crtc_state``h]j)}(hjh]h-const struct intel_crtc_state *old_crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjubj)}(hhh]h)}(hpointer to the old crtc state.h]hpointer to the old crtc state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hY``const struct drm_connector_state *old_conn_state`` pointer to the old connector state. h](j)}(h4``const struct drm_connector_state *old_conn_state``h]j)}(hj4h]h0const struct drm_connector_state *old_conn_state}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhj.ubj)}(hhh]h)}(h#pointer to the old connector state.h]h#pointer to the old connector state.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMhjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hjIhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjoh]h Description}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjmubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjubh)}(hPThe disable sequences must be performed before disabling the transcoder or port.h]hPThe disable sequences must be performed before disabling the transcoder or port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjyhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_audio_hooks_init (C function)c.intel_audio_hooks_inithNtauh1jhjyhhhNhNubj')}(hhh](j,)}(h;void intel_audio_hooks_init (struct intel_display *display)h]j2)}(h:void intel_audio_hooks_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chM|ubji)}(h h]h }(hjÀhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj€hM|ubjz)}(hintel_audio_hooks_inith]j;)}(hintel_audio_hooks_inith]hintel_audio_hooks_init}(hjՀhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjрubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj€hM|ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTj׀sbc.intel_audio_hooks_initasbuh1hhjubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhj€hM|ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj€hM|ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj€hM|hjhhubj1)}(hhh]h)}(h Set up chip specific audio hooksh]h Set up chip specific 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]jah"]h$]h&]uh1jhjHubji)}(h h]h }(hjYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjgubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjlmodnameN classnameNjXj[)}j^]ja)}jTj2sbc.intel_audio_component_initasbuh1hhjHubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjHubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjDubah}(h]h ]h"]h$]h&]jjuh1jhj hhhjhM&ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM&ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM&hjhhubj1)}(hhh]h)}(h+initialize and register the audio componenth]h+initialize and register the audio component}(hjςhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chM&hĵhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM&ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjyhNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device **Description** This will register with the component framework a child component which will bind dynamically to the snd_hda_intel driver's corresponding master component when the latter is registered. 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Each side can break the binding at any point by deregistering its own component after which each side’s component unbind callback is called.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chM)hjubh)}(hjWe ignore any error during registration and continue with reduced functionality (i.e. without HDMI audio).h]hjWe ignore any error during registration and continue with reduced functionality (i.e. without HDMI audio).}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chM2hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjyhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"*intel_audio_component_cleanup (C function)c.intel_audio_component_cleanuphNtauh1jhjyhhhNhNubj')}(hhh](j,)}(hBvoid intel_audio_component_cleanup (struct intel_display *display)h]j2)}(hAvoid intel_audio_component_cleanup(struct intel_display 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]jGah"]h$]h&]uh1j:hj؃ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjԃubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMcubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMcubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMchjhhubj1)}(hhh]h)}(hderegister the audio componenth]hderegister the audio component}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMchj\hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMcubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjwjSjwjTjUjVuh1j&hhhjyhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display device **Description** Deregisters the audio component, breaking any existing binding to the corresponding snd_hda_intel driver's master component.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMghj{ubjx)}(hhh]j})}(h1``struct intel_display *display`` display device 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]h"]h$]h&] refdomainjRreftypejT reftargetj}modnameN classnameNjXj[)}j^]ja)}jTjCsbc.intel_audio_initasbuh1hhjYubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjYubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjUubah}(h]h ]h"]h$]h&]jjuh1jhjhhhj.hMsubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj.hMsubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj.hMshjhhubj1)}(hhh]h)}(hVInitialize the audio driver either using component framework or using lpe audio bridgeh]hVInitialize the audio driver either using component framework or using lpe audio bridge}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:150: ./drivers/gpu/drm/i915/display/intel_audio.chMshj݅hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj.hMsubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjyhNhNubjX)}(hB**Parameters** ``struct intel_display *display`` display deviceh](h)}(h**Parameters**h]jb)}(hjh]h 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Create IRQ chip to forward the LPE audio irqs. the hdmi-lpe-audio driver probes the lpe audio device and creates a new sound card}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:159: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chK%hjhhubh)}(hXLThreats: Due to the restriction in Linux platform device model, user need manually uninstall the hdmi-lpe-audio driver before uninstalling i915 module, otherwise we might run into use-after-free issues after i915 removes the platform device: even though hdmi-lpe-audio driver is released, the modules is still in "installed" status.h]hXPThreats: Due to the restriction in Linux platform device model, user need manually uninstall the hdmi-lpe-audio driver before uninstalling i915 module, otherwise we might run into use-after-free issues after i915 removes the platform device: even though hdmi-lpe-audio driver is released, the modules is still in “installed” status.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:159: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chK.hjhhubh)}(hImplementation: The MMIO/REG platform resources are created according to the registers specification. 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Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMhjIubh)}(hQthe LPE Audio irq is forwarded to the irq handler registered by LPE audio driver.h]hQthe LPE Audio irq is forwarded to the irq handler registered by LPE audio driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMhjIubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_lpe_audio_init (C function)c.intel_lpe_audio_inithNtauh1jhjhhhNhNubj')}(hhh](j,)}(h8int intel_lpe_audio_init (struct intel_display *display)h]j2)}(h7int intel_lpe_audio_init(struct intel_display *display)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMubji)}(h h]h }(hjhhhNhNubah}(h]h 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i915 bridge.h]h8release all the resources for LPE audio <-> i915 bridge.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chM-hjKubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_lpe_audio_notify (C function)c.intel_lpe_audio_notifyhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hvoid intel_lpe_audio_notify (struct intel_display *display, enum transcoder cpu_transcoder, enum port port, const void *eld, int ls_clock, bool dp_output)h]j2)}(hvoid intel_lpe_audio_notify(struct intel_display *display, enum transcoder cpu_transcoder, enum port port, const void *eld, int ls_clock, bool dp_output)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chM=ubji)}(h h]h }(hjhhhNhNubah}(h]h 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h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h transcoderh]h transcoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jgc.intel_lpe_audio_notifyasbuh1hhjubji)}(h h]h }(hjێhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hcpu_transcoderh]hcpu_transcoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj%ubj)}(henum port porth](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hporth]hport}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj"modnameN classnameNjXj[)}j^]jgc.intel_lpe_audio_notifyasbuh1hhjubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hporth]hport}(hjLhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj%ubj)}(hconst void *eldh](j)}(hjR{h]hconst}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjaubj)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjaubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj;)}(heldh]held}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjaubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj%ubj)}(h int ls_clockh](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjЏhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hls_clockh]hls_clock}(hjޏhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj%ubj)}(hbool dp_outputh](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h dp_outputh]h dp_output}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj%ubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM=ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM=ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM=hjhhubj1)}(hhh]h)}(h,notify lpe audio event audio driver and i915h]h,notify lpe audio event audio driver and i915}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chM=hj9hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM=ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjTjSjTjTjUjVuh1j&hhhjhNhNubjX)}(hXC**Parameters** ``struct intel_display *display`` display device ``enum transcoder cpu_transcoder`` CPU transcoder ``enum port port`` port ``const void *eld`` ELD data ``int ls_clock`` Link symbol clock in kHz ``bool dp_output`` Driving a DP output? **Description** Notify lpe audio driver of eld change.h](h)}(h**Parameters**h]jb)}(hj^h]h Parameters}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj\ubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMAhjXubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hj}h]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h 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./drivers/gpu/drm/i915/display/intel_lpe_audio.chMAhjubj)}(hhh]h)}(hporth]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMAhjtubj})}(h``const void *eld`` ELD data h](j)}(h``const void *eld``h]j)}(hj(h]hconst void *eld}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMBhj"ubj)}(hhh]h)}(hELD datah]hELD data}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMBhj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj=hMBhjtubj})}(h*``int ls_clock`` Link symbol clock in kHz h](j)}(h``int ls_clock``h]j)}(hjah]h int ls_clock}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMChj[ubj)}(hhh]h)}(hLink symbol clock in kHzh]hLink symbol clock in kHz}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMChjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hjvhMChjtubj})}(h(``bool dp_output`` Driving a DP output? h](j)}(h``bool dp_output``h]j)}(hjh]hbool dp_output}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMDhjubj)}(hhh]h)}(hDriving a DP output?h]hDriving a DP output?}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMDhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMDhjtubeh}(h]h ]h"]h$]h&]uh1jwhjXubh)}(h**Description**h]jb)}(hjՑh]h Description}(hjבhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjӑubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMFhjXubh)}(h&Notify lpe audio driver of eld change.h]h&Notify lpe audio driver of eld change.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:162: ./drivers/gpu/drm/i915/display/intel_lpe_audio.chMFhjXubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]intel-hdmi-lpe-audio-supportah ]h"]intel hdmi lpe audio supportah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(h Panel Self Refresh PSR (PSR/SRD)h]h Panel Self Refresh PSR (PSR/SRD)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hXSince Haswell Display controller supports Panel Self-Refresh on display panels witch have a remote frame buffer (RFB) implemented according to PSR spec in eDP1.3. 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PSR feature allows the display to go to lower standby states when system is idle but display is on as it eliminates display refresh request to DDR memory completely as long as the frame buffer for that display is unchanged.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chK7hj hhubh)}(hPPanel Self Refresh must be supported by both Hardware (source) and Panel (sink).h]hPPanel Self Refresh must be supported by both Hardware (source) and Panel (sink).}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chK>hj hhubh)}(hPSR saves power by caching the framebuffer in the panel RFB, which allows us to power down the link and memory controller. For DSI panels the same idea is called "manual mode".h]hPSR saves power by caching the framebuffer in the panel RFB, which allows us to power down the link and memory controller. For DSI panels the same idea is called “manual mode”.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKAhj hhubh)}(hXThe implementation uses the hardware-based PSR support which automatically enters/exits self-refresh mode. The hardware takes care of sending the required DP aux message and could even retrain the link (that part isn't enabled yet though). The hardware also keeps track of any frontbuffer changes to know when to exit self-refresh mode again. Unfortunately that part doesn't work too well, hence why the i915 PSR support uses the software frontbuffer tracking to make sure it doesn't miss a screen update. For this integration intel_psr_invalidate() and intel_psr_flush() get called by the frontbuffer tracking code. Note that because of locking issues the self-refresh re-enable code is done from a work queue, which must be correctly synchronized/cancelled when shutting down the pipe."h]hXThe implementation uses the hardware-based PSR support which automatically enters/exits self-refresh mode. The hardware takes care of sending the required DP aux message and could even retrain the link (that part isn’t enabled yet though). The hardware also keeps track of any frontbuffer changes to know when to exit self-refresh mode again. Unfortunately that part doesn’t work too well, hence why the i915 PSR support uses the software frontbuffer tracking to make sure it doesn’t miss a screen update. For this integration intel_psr_invalidate() and intel_psr_flush() get called by the frontbuffer tracking code. Note that because of locking issues the self-refresh re-enable code is done from a work queue, which must be correctly synchronized/cancelled when shutting down the pipe.”}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKEhj hhubh)}(hDC3CO (DC3 clock off)h]hDC3CO (DC3 clock off)}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKQhj hhubh)}(hXNOn top of PSR2, GEN12 adds a intermediate power savings state that turns clock off automatically during PSR2 idle state. The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep entry/exit allows the HW to enter a low-power state even when page flipping periodically (for instance a 30fps video playback scenario).h]hXNOn top of PSR2, GEN12 adds a intermediate power savings state that turns clock off automatically during PSR2 idle state. The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep entry/exit allows the HW to enter a low-power state even when page flipping periodically (for instance a 30fps video playback scenario).}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKShj hhubh)}(hXEvery time a flips occurs PSR2 will get out of deep sleep state(if it was), so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 frames, if no other flip occurs and the function above is executed, DC3CO is disabled and PSR2 is configured to enter deep sleep, resetting again in case of another flip. Front buffer modifications do not trigger DC3CO activation on purpose as it would bring a lot of complexity and most of the moderns systems will only use page flips.h]hXEvery time a flips occurs PSR2 will get out of deep sleep state(if it was), so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 frames, if no other flip occurs and the function above is executed, DC3CO is disabled and PSR2 is configured to enter deep sleep, resetting again in case of another flip. Front buffer modifications do not trigger DC3CO activation on purpose as it would bring a lot of complexity and most of the moderns systems will only use page flips.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:168: ./drivers/gpu/drm/i915/display/intel_psr.chKYhj hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_disable (C function)c.intel_psr_disablehNtauh1jhj hhhNhNubj')}(hhh](j,)}(havoid intel_psr_disable (struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h]j2)}(h`void intel_psr_disable(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_psr_disableh]j;)}(hintel_psr_disableh]hintel_psr_disable}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(hJ(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state)h](j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjْhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjՒubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjՒubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_disableasbuh1hhjՒubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjՒubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjՒubj;)}(hintel_dph]hintel_dp}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjՒubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjђubj)}(h-const struct intel_crtc_state *old_crtc_stateh](j)}(hjR{h]hconst}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubji)}(h h]h }(hjXhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjGubj)}(hjh]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubji)}(h h]h }(hjshhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjGubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_psr_disableasbuh1hhjGubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjGubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj;)}(hold_crtc_stateh]hold_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjGubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjђubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h Disable PSRh]h Disable PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(h**Parameters** ``struct intel_dp *intel_dp`` Intel DP ``const struct intel_crtc_state *old_crtc_state`` old CRTC state **Description** This function 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./drivers/gpu/drm/i915/display/intel_psr.chMhj[ubj)}(hhh]h)}(hold CRTC stateh]hold CRTC state}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hjvhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(h7This function needs to be called before disabling pipe.h]h7This function needs to be called before disabling pipe.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_pause (C function)c.intel_psr_pausehNtauh1jhj hhhNhNubj')}(hhh](j,)}(h0void intel_psr_pause (struct intel_dp *intel_dp)h]j2)}(h/void intel_psr_pause(struct intel_dp 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]h"]h$]h&]jjj"uh1j1j#j$hjٔhhhjhMubah}(h]jԔah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhj֔hhubj1)}(hhh]h)}(h Pause PSRh]h Pause PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj֔hhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(h~**Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function need to be called after enabling psr.h](h)}(h**Parameters**h]jb)}(hjÕh]h Parameters}(hjŕhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjx)}(hhh]j})}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjܕubj)}(hhh]h)}(hIntel DPh]hIntel DP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjܕubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjٕubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(h3This function need to be called after enabling psr.h]h3This function need to be called after enabling psr.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_resume (C function)c.intel_psr_resumehNtauh1jhj hhhNhNubj')}(hhh](j,)}(h1void intel_psr_resume (struct intel_dp *intel_dp)h]j2)}(h0void intel_psr_resume(struct intel_dp *intel_dp)h](j)}(hvoidh]hvoid}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj^hhhjphMubjz)}(hintel_psr_resumeh]j;)}(hintel_psr_resumeh]hintel_psr_resume}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj^hhhjphMubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_resumeasbuh1hhjubji)}(h h]h }(hjݖhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj^hhhjphMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjZhhhjphMubah}(h]jUah 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DP}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1j|hjxhMhjZubah}(h]h ]h"]h$]h&]uh1jwhj>ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj>ubh)}(h2This function need to be called after pausing psr.h]h2This function need to be called after pausing psr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"0intel_psr_needs_vblank_notification (C function)%c.intel_psr_needs_vblank_notificationhNtauh1jhj hhhNhNubj')}(hhh](j,)}(hTbool intel_psr_needs_vblank_notification (const struct intel_crtc_state *crtc_state)h]j2)}(hSbool intel_psr_needs_vblank_notification(const struct intel_crtc_state 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h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjߗhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjۗhhhjhMubah}(h]j֗ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjؗhhubj1)}(hhh]h)}(h5Check if PSR need vblank enable/disable notification.h]h5Check if PSR need vblank enable/disable notification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjؗhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj՘jSj՘jTjUjVuh1j&hhhj hNhNubjX)}(hX**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC status **Description** We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't prevent it in case of Panel Replay. Panel Replay switches main link off on DC entry. This means vblank interrupts are not fired and is a problem if user-space is polling for vblank events. Also Wa_16025596647 needs information when vblank is enabled/disabled.h](h)}(h**Parameters**h]jb)}(hjߘh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjݘubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hj٘ubjx)}(hhh]j})}(h:``const struct intel_crtc_state *crtc_state`` CRTC status h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(h CRTC statush]h CRTC status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhj٘ubh)}(h**Description**h]jb)}(hj9h]h Description}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj7ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hj٘ubh)}(hXNWe need to block DC6 entry in case of Panel Replay as enabling VBI doesn't prevent it in case of Panel Replay. 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Also Wa_16025596647 needs information when vblank is enabled/disabled.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hj٘ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"1intel_psr_trigger_frame_change_event (C function)&c.intel_psr_trigger_frame_change_eventhNtauh1jhj hhhNhNubj')}(hhh](j,)}(h|void intel_psr_trigger_frame_change_event (struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h]j2)}(h{void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hvoidh]hvoid}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM$ ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzhhhjhM$ ubjz)}(h$intel_psr_trigger_frame_change_eventh]j;)}(h$intel_psr_trigger_frame_change_eventh]h$intel_psr_trigger_frame_change_event}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjzhhhjhM$ ubj)}(hR(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjșhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_dsbh]h intel_dsb}(hjٙhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj֙ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjۙmodnameN classnameNjXj[)}j^]ja)}jTjsb&c.intel_psr_trigger_frame_change_eventasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdsbh]hdsb}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubji)}(h h]h }(hj:hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)ubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjHubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjMmodnameN classnameNjXj[)}j^]j&c.intel_psr_trigger_frame_change_eventasbuh1hhj)ubji)}(h h]h }(hjihhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)ubj)}(hjh]h*}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj;)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j&c.intel_psr_trigger_frame_change_eventasbuh1hhjubji)}(h h]h }(hjٚhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjzhhhjhM$ ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjvhhhjhM$ ubah}(h]jqah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM$ hjshhubj1)}(hhh]h)}(hTrigger "Frame Change" eventh]h Trigger “Frame Change” event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM$ hjhhubah}(h]h ]h"]h$]h&]uh1j0hjshhhjhM$ ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj6jSj6jTjUjVuh1j&hhhj hNhNubjX)}(h**Parameters** ``struct intel_dsb *dsb`` DSB context ``struct intel_atomic_state *state`` the atomic state ``struct intel_crtc *crtc`` the CRTC **Description** Generate PSR "Frame Change" event.h](h)}(h**Parameters**h]jb)}(hj@h]h Parameters}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj>ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM( hj:ubjx)}(hhh](j})}(h&``struct intel_dsb *dsb`` DSB context h](j)}(h``struct intel_dsb *dsb``h]j)}(hj_h]hstruct intel_dsb *dsb}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM% hjYubj)}(hhh]h)}(h DSB contexth]h DSB context}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthM% hjuubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1j|hjthM% hjVubj})}(h6``struct intel_atomic_state *state`` the atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM& hjubj)}(hhh]h)}(hthe atomic stateh]hthe atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM& hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM& hjVubj})}(h%``struct intel_crtc *crtc`` the CRTC h](j)}(h``struct intel_crtc *crtc``h]j)}(hjћh]hstruct intel_crtc *crtc}(hjӛhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϛubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM' hj˛ubj)}(hhh]h)}(hthe CRTCh]hthe CRTC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM' hjubah}(h]h ]h"]h$]h&]uh1jhj˛ubeh}(h]h ]h"]h$]h&]uh1j|hjhM' hjVubeh}(h]h ]h"]h$]h&]uh1jwhj:ubh)}(h**Description**h]jb)}(hj h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM) hj:ubh)}(h"Generate PSR "Frame Change" event.h]h&Generate PSR “Frame Change” event.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM) hj:ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_psr_min_vblank_delay (C function)c.intel_psr_min_vblank_delayhNtauh1jhj hhhNhNubj')}(hhh](j,)}(hJint intel_psr_min_vblank_delay (const struct intel_crtc_state *crtc_state)h]j2)}(hIint intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state)h](j)}(hinth]hint}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM9 ubji)}(h h]h }(hj`hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjMhhhj_hM9 ubjz)}(hintel_psr_min_vblank_delayh]j;)}(hintel_psr_min_vblank_delayh]hintel_psr_min_vblank_delay}(hjrhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjMhhhj_hM9 ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjǜhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjĜubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjɜmodnameN classnameNjXj[)}j^]ja)}jTjtsbc.intel_psr_min_vblank_delayasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjMhhhj_hM9 ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjIhhhj_hM9 ubah}(h]jDah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj_hM9 hjFhhubj1)}(hhh]h)}(h"Minimum vblank delay needed by PSRh]h"Minimum vblank delay needed by PSR}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM9 hj)hhubah}(h]h ]h"]h$]h&]uh1j0hjFhhhj_hM9 ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjDjSjDjTjUjVuh1j&hhhj hNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Return minimum vblank delay needed by PSR.h](h)}(h**Parameters**h]jb)}(hjNh]h Parameters}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjLubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM= hjHubjx)}(hhh]j})}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjmh]h)const struct intel_crtc_state *crtc_state}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM: hjgubj)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM: hjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1j|hjhM: hjdubah}(h]h ]h"]h$]h&]uh1jwhjHubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM< hjHubh)}(h*Return minimum vblank delay needed by PSR.h]h*Return minimum vblank delay needed by PSR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM< hjHubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+intel_psr_wait_for_idle_locked (C function) c.intel_psr_wait_for_idle_lockedhNtauh1jhj hhhNhNubj')}(hhh](j,)}(hSvoid intel_psr_wait_for_idle_locked (const struct intel_crtc_state *new_crtc_state)h]j2)}(hRvoid intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_psr_wait_for_idle_lockedh]j;)}(hintel_psr_wait_for_idle_lockedh]hintel_psr_wait_for_idle_locked}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h/(const struct intel_crtc_state *new_crtc_state)h]j)}(h-const struct intel_crtc_state *new_crtc_stateh](j)}(hjR{h]hconst}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubji)}(h h]h }(hj7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj&ubj)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubji)}(h h]h }(hjRhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj&ubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjchhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjemodnameN classnameNjXj[)}j^]ja)}jTjsb c.intel_psr_wait_for_idle_lockedasbuh1hhj&ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj&ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj;)}(hnew_crtc_stateh]hnew_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj&ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj"ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h'wait for PSR be ready for a pipe updateh]h'wait for PSR be ready for a pipe update}(hjȞhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjŞhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *new_crtc_state`` new CRTC state **Description** This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubjx)}(hhh]j})}(hA``const struct intel_crtc_state *new_crtc_state`` new CRTC state h](j)}(h1``const struct intel_crtc_state *new_crtc_state``h]j)}(hj h]h-const struct intel_crtc_state *new_crtc_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj)}(hhh]h)}(hnew CRTC stateh]hnew CRTC state}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjDh]h Description}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjBubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(h|This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.h]h|This function is expected to be called from pipe_update_start() where it is not expected to race with PSR enable or disable.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_psr_invalidate (C function)c.intel_psr_invalidatehNtauh1jhj hhhNhNubj')}(hhh](j,)}(hnvoid intel_psr_invalidate (struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h]j2)}(hmvoid intel_psr_invalidate(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_psr_invalidateh]j;)}(hintel_psr_invalidateh]hintel_psr_invalidate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(hT(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjƟhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjŸubji)}(h h]h }(hjӟhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjŸubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_invalidateasbuh1hhjŸubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjŸubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjŸubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjŸubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubji)}(h h]h }(hjFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj4ubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj4ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(henum fb_op_origin originh](j)}(hjh]henum}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubji)}(h h]h }(hjzhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjiubh)}(hhh]j;)}(h fb_op_originh]h fb_op_origin}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_psr_invalidateasbuh1hhjiubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjiubj;)}(horiginh]horigin}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjiubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]j|ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hj~hhubj1)}(hhh]h)}(hInvalidate PSRh]hInvalidate PSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjޠhhubah}(h]h ]h"]h$]h&]uh1j0hj~hhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(hXA**Parameters** ``struct intel_display *display`` display device ``unsigned frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the invalidate **Description** Since the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering starts and a buffer gets dirtied. PSR must be disabled if the frontbuffer mask contains a buffer relevant to PSR. Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hj"h]hstruct intel_display *display}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hM hj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj7hM hjubj})}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h``unsigned frontbuffer_bits``h]j)}(hj[h]hunsigned frontbuffer_bits}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjUubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphM hjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j|hjphM hjubj})}(hC``enum fb_op_origin origin`` which operation caused the invalidate h](j)}(h``enum fb_op_origin origin``h]j)}(hjh]henum fb_op_origin origin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubj)}(hhh]h)}(h%which operation caused the invalidateh]h%which operation caused the invalidate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjϡh]h Description}(hjѡhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj͡ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. 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PSR must be disabled if the frontbuffer mask contains a buffer relevant to PSR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubh)}(hIDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."h]hKDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_flush (C function)c.intel_psr_flushhNtauh1jhj hhhNhNubj')}(hhh](j,)}(hivoid intel_psr_flush (struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h]j2)}(hhvoid intel_psr_flush(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hvoidh]hvoid}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM( ubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj1hM( ubjz)}(hintel_psr_flushh]j;)}(hintel_psr_flushh]hintel_psr_flush}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj1hM( ubj)}(hT(struct intel_display *display, unsigned frontbuffer_bits, enum fb_op_origin origin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj~hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjFsbc.intel_psr_flushasbuh1hhj\ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjXubj)}(hunsigned frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hjҢhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj΢ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj΢ubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj΢ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjXubj)}(henum fb_op_origin originh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h fb_op_originh]h fb_op_origin}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj'modnameN classnameNjXj[)}j^]jc.intel_psr_flushasbuh1hhjubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(horiginh]horigin}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjXubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj1hM( ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj1hM( ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj1hM( hjhhubj1)}(hhh]h)}(h Flush PSRh]h Flush PSR}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM( hjxhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj1hM( ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(hX=**Parameters** ``struct intel_display *display`` display device ``unsigned frontbuffer_bits`` frontbuffer plane tracking bits ``enum fb_op_origin origin`` which operation caused the flush **Description** Since the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty. Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM, hjubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM) hjubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjգhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjѣhM) hjңubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjѣhM) hjubj})}(h>``unsigned frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h``unsigned frontbuffer_bits``h]j)}(hjh]hunsigned frontbuffer_bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM* hjubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM* hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hM* hjubj})}(h>``enum fb_op_origin origin`` which operation caused the flush h](j)}(h``enum fb_op_origin origin``h]j)}(hj.h]henum fb_op_origin origin}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM+ hj(ubj)}(hhh]h)}(h which operation caused the flushh]h which operation caused the flush}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChM+ hjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1j|hjChM+ hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjih]h Description}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjgubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM- hjubh)}(hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty.h]hXSince the hardware frontbuffer tracking has gaps we need to integrate with the software frontbuffer tracking. This function gets called every time frontbuffer rendering has completed and flushed out to memory. PSR can be enabled again if no other frontbuffer relevant to PSR is dirty.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM- hjubh)}(hHDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.h]hHDirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM2 hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_init (C function)c.intel_psr_inithNtauh1jhj hhhNhNubj')}(hhh](j,)}(h/void intel_psr_init (struct intel_dp *intel_dp)h]j2)}(h.void intel_psr_init(struct intel_dp *intel_dp)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMa ubji)}(h h]h }(hj̤hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjˤhMa ubjz)}(hintel_psr_inith]j;)}(hintel_psr_inith]hintel_psr_init}(hjޤhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjڤubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjˤhMa ubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_initasbuh1hhjubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hintel_dph]hintel_dp}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjˤhMa ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjˤhMa ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjˤhMa hjhhubj1)}(hhh]h)}(hInit basic PSR work and mutex.h]hInit basic PSR work and mutex.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMa hjzhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjˤhMa ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(hX **Parameters** ``struct intel_dp *intel_dp`` Intel DP **Description** This function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMe hjubjx)}(hhh]j})}(h'``struct intel_dp *intel_dp`` Intel DP h](j)}(h``struct intel_dp *intel_dp``h]j)}(hjh]hstruct intel_dp *intel_dp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMb hjubj)}(hhh]h)}(hIntel DPh]hIntel DP}(hjץhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjӥhMb hjԥubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjӥhMb hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMd hjubh)}(hThis function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.h]hThis function is called after the initializing connector. (the initializing of connector treats the handling of connector capabilities) And it initializes basic PSR stuff for each DP Encoder.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMd hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_link_ok (C function)c.intel_psr_link_okhNtauh1jhj hhhNhNubj')}(hhh](j,)}(h2bool intel_psr_link_ok (struct intel_dp *intel_dp)h]j2)}(h1bool intel_psr_link_ok(struct intel_dp *intel_dp)h](j)}(hjh]hbool}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM#ubji)}(h h]h }(hjLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj:hhhjKhM#ubjz)}(hintel_psr_link_okh]j;)}(hintel_psr_link_okh]hintel_psr_link_ok}(hj^hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjZubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj:hhhjKhM#ubj)}(h(struct intel_dp *intel_dp)h]j)}(hstruct intel_dp *intel_dph](j)}(hjh]hstruct}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjvubh)}(hhh]j;)}(hintel_dph]hintel_dp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTj`sbc.intel_psr_link_okasbuh1hhjvubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjvubj)}(hjh]h*}(hjƦhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj;)}(hintel_dph]hintel_dp}(hjӦhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjvubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjrubah}(h]h ]h"]h$]h&]jjuh1jhj:hhhjKhM#ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj6hhhjKhM#ubah}(h]j1ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjKhM#hj3hhubj1)}(hhh]h)}(hreturn psr->link_okh]hreturn psr->link_ok}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM#hjhhubah}(h]h ]h"]h$]h&]uh1j0hj3hhhjKhM#ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(hX**Parameters** ``struct intel_dp *intel_dp`` struct intel_dp **Description** We are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter. Return value of link_okh](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM'hjubjx)}(hhh]j})}(h.``struct intel_dp *intel_dp`` struct intel_dp h](j)}(h``struct intel_dp *intel_dp``h]j)}(hj>h]hstruct intel_dp *intel_dp}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM$hj8ubj)}(hhh]h)}(hstruct intel_dph]hstruct intel_dp}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShM$hjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1j|hjShM$hj5ubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjyh]h Description}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjwubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM&hjubh)}(hXRWe are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter.h]hXRWe are seeing unexpected link re-trainings with some panels. This is caused by panel stating bad link status after PSR is enabled. Code checking link status can call this to ensure it can ignore bad link status stated by the panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link is ok caller should rely on latter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM&hjubh)}(hReturn value of link_okh]hReturn value of link_ok}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM,hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_lock (C function)c.intel_psr_lockhNtauh1jhj hhhNhNubj')}(hhh](j,)}(h?void intel_psr_lock (const struct intel_crtc_state *crtc_state)h]j2)}(h>void intel_psr_lock(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjͧhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjɧhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM>ubji)}(h h]h }(hjܧhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjɧhhhjۧhM>ubjz)}(hintel_psr_lockh]j;)}(hintel_psr_lockh]hintel_psr_lock}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjɧhhhjۧhM>ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjR{h]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjChhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjEmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_lockasbuh1hhjubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hj~hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjɧhhhjۧhM>ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjŧhhhjۧhM>ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjۧhM>hj§hhubj1)}(hhh]h)}(h grab PSR lockh]h grab PSR lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM>hjhhubah}(h]h ]h"]h$]h&]uh1j0hj§hhhjۧhM>ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(hX**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** This is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.h](h)}(h**Parameters**h]jb)}(hjʨh]h Parameters}(hj̨hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjȨubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMBhjĨubjx)}(hhh]j})}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM?hjubj)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM?hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM?hjubah}(h]h ]h"]h$]h&]uh1jwhjĨubh)}(h**Description**h]jb)}(hj$h]h Description}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMAhjĨubh)}(hThis is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.h]hThis is initially meant to be used by around CRTC update, when vblank sensitive registers are updated and we need grab the lock before it to avoid vblank evasion.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMAhjĨubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_psr_unlock (C function)c.intel_psr_unlockhNtauh1jhj hhhNhNubj')}(hhh](j,)}(hAvoid intel_psr_unlock (const struct intel_crtc_state *crtc_state)h]j2)}(h@void intel_psr_unlock(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjehhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMWubji)}(h h]h }(hjxhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjehhhjwhMWubjz)}(hintel_psr_unlockh]j;)}(hintel_psr_unlockh]hintel_psr_unlock}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjehhhjwhMWubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjΩhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjߩhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjܩubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_unlockasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjehhhjwhMWubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjahhhjwhMWubah}(h]j\ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjwhMWhj^hhubj1)}(hhh]h)}(hrelease PSR lockh]hrelease PSR lock}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMWhjAhhubah}(h]h ]h"]h$]h&]uh1j0hj^hhhjwhMWubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj\jSj\jTjUjVuh1j&hhhj hNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Release the PSR lock that was held during pipe update.h](h)}(h**Parameters**h]jb)}(hjfh]h Parameters}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjdubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chM[hj`ubjx)}(hhh]j})}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMXhjubj)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMXhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMXhj|ubah}(h]h ]h"]h$]h&]uh1jwhj`ubh)}(h**Description**h]jb)}(hjh]h Description}(hjªhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMZhj`ubh)}(h6Release the PSR lock that was held during pipe update.h]h6Release the PSR lock that was held during pipe update.}(hj֪hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMZhj`ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_psr_notify_dc5_dc6 (C function)c.intel_psr_notify_dc5_dc6hNtauh1jhj hhhNhNubj')}(hhh](j,)}(h=void intel_psr_notify_dc5_dc6 (struct intel_display *display)h]j2)}(hubji)}(h h]h }(hjOhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj`hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj]ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjbmodnameN classnameNjXj[)}j^]ja)}jTj(sbc.intel_psr_notify_dc5_dc6asbuh1hhj>ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj:ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h'Notify PSR about enable/disable dc5/dc6h]h'Notify PSR about enable/disable dc5/dc6}(hjūhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj«hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjݫjSjݫjTjUjVuh1j&hhhj hNhNubjX)}(h**Parameters** ``struct intel_display *display`` intel atomic state **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule psr_dc5_dc6_wa_work used for applying/removing the workaround.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjx)}(hhh]j})}(h5``struct intel_display *display`` intel atomic state h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjAh]h Description}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule psr_dc5_dc6_wa_work used for applying/removing the workaround.h]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule psr_dc5_dc6_wa_work used for applying/removing the workaround.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_psr_dc5_dc6_wa_init (C function)c.intel_psr_dc5_dc6_wa_inithNtauh1jhj hhhNhNubj')}(hhh](j,)}(h>void intel_psr_dc5_dc6_wa_init (struct intel_display *display)h]j2)}(h=void intel_psr_dc5_dc6_wa_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_psr_dc5_dc6_wa_inith]j;)}(hintel_psr_dc5_dc6_wa_inith]hintel_psr_dc5_dc6_wa_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjìhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjЬhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjެubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_psr_dc5_dc6_wa_initasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj~hhhjhMubah}(h]jyah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhj{hhubj1)}(hhh]h)}(h,Init work for underrun on idle PSR HW bug wah]h,Init work for underrun on idle PSR HW bug wa}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjChhubah}(h]h ]h"]h$]h&]uh1j0hj{hhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj^jSj^jTjUjVuh1j&hhhj hNhNubjX)}(h**Parameters** ``struct intel_display *display`` intel atomic state **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.h](h)}(h**Parameters**h]jb)}(hjhh]h Parameters}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjfubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjbubjx)}(hhh]j})}(h5``struct intel_display *display`` intel atomic state h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj~ubah}(h]h ]h"]h$]h&]uh1jwhjbubh)}(h**Description**h]jb)}(hj­h]h Description}(hjĭhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjbubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.h]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init psr_dc5_dc6_wa_work used for applying the workaround.}(hjحhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjbubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_psr_notify_pipe_change (C function)c.intel_psr_notify_pipe_changehNtauh1jhj hhhNhNubj')}(hhh](j,)}(hjvoid intel_psr_notify_pipe_change (struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h]j2)}(hivoid intel_psr_notify_pipe_change(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_psr_notify_pipe_changeh]j;)}(hintel_psr_notify_pipe_changeh]hintel_psr_notify_pipe_change}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(hH(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@ubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjbhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjdmodnameN classnameNjXj[)}j^]ja)}jTj*sbc.intel_psr_notify_pipe_changeasbuh1hhj@ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubj;)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj<ubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjîhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjԮhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjѮubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj֮modnameN classnameNjXj[)}j^]j~c.intel_psr_notify_pipe_changeasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj<ubj)}(h bool enableh](j)}(hjh]hbool}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubji)}(h h]h }(hj3hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj"ubj;)}(henableh]henable}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj<ubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h)Notify PSR about enable/disable of a pipeh]h)Notify PSR about enable/disable of a pipe}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(hX.**Parameters** ``struct intel_atomic_state *state`` intel atomic state ``struct intel_crtc *crtc`` intel crtc ``bool enable`` enable/disable **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabledh](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjx)}(hhh](j})}(h8``struct intel_atomic_state *state`` intel atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjůhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhj¯ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(h'``struct intel_crtc *crtc`` intel crtc h](j)}(h``struct intel_crtc *crtc``h]j)}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhj߯ubj)}(hhh]h)}(h intel crtch]h intel crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj߯ubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(h``bool enable`` enable/disable h](j)}(h``bool enable``h]j)}(hjh]h bool enable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(henable/disableh]henable/disable}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj3hMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjYh]h Description}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjWubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabledh]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when pipe is getting enabled/disabled}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"3intel_psr_notify_vblank_enable_disable (C function)(c.intel_psr_notify_vblank_enable_disablehNtauh1jhj hhhNhNubj')}(hhh](j,)}(hXvoid intel_psr_notify_vblank_enable_disable (struct intel_display *display, bool enable)h]j2)}(hWvoid intel_psr_notify_vblank_enable_disable(struct intel_display *display, bool enable)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(h&intel_psr_notify_vblank_enable_disableh]j;)}(h&intel_psr_notify_vblank_enable_disableh]h&intel_psr_notify_vblank_enable_disable}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h,(struct intel_display *display, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj۰hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjװubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjװubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb(c.intel_psr_notify_vblank_enable_disableasbuh1hhjװubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjװubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjװubj;)}(hdisplayh]hdisplay}(hj4hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjװubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjӰubj)}(h bool enableh](j)}(hjh]hbool}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIubj;)}(henableh]henable}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjӰubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h)Notify PSR about enable/disable of vblankh]h)Notify PSR about enable/disable of vblank}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj hNhNubjX)}(hX**Parameters** ``struct intel_display *display`` intel display struct ``bool enable`` enable/disable **Description** This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when vblank is getting enabled/disabledh](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubjx)}(hhh](j})}(h7``struct intel_display *display`` intel display struct h](j)}(h!``struct intel_display *display``h]j)}(hjӱh]hstruct intel_display *display}(hjձhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjѱubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjͱubj)}(hhh]h)}(hintel display structh]hintel display struct}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjͱubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjʱubj})}(h``bool enable`` enable/disable h](j)}(h``bool enable``h]j)}(hj h]h bool enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubj)}(hhh]h)}(henable/disableh]henable/disable}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMhj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj!hMhjʱubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjGh]h Description}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjEubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubh)}(hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when vblank is getting enabled/disabledh]hThis is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply remove the workaround when vblank is getting enabled/disabled}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:171: ./drivers/gpu/drm/i915/display/intel_psr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubeh}(h]panel-self-refresh-psr-psr-srdah ]h"] panel self refresh psr (psr/srd)ah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hFrame Buffer Compression (FBC)h]hFrame Buffer Compression (FBC)}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hhhhhKubh)}(hFBC tries to save memory bandwidth (and so power consumption) by compressing the amount of memory used by the display. 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]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hj-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj*ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj/modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_fbc_disableasbuh1hhj ubji)}(h h]h }(hjMhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hcrtch]hcrtc}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjβhhhjhMnubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjʲhhhjhMnubah}(h]jŲah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMnhjDzhhubj1)}(hhh]h)}(h(disable FBC if it's associated with crtch]h*disable FBC if it’s associated with crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMnhjhhubah}(h]h ]h"]h$]h&]uh1j0hjDzhhhjhMnubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj{hNhNubjX)}(h**Parameters** ``struct intel_crtc *crtc`` the CRTC **Description** This function disables FBC if it's associated with the provided CRTC.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMrhjubjx)}(hhh]j})}(h%``struct intel_crtc *crtc`` the CRTC h](j)}(h``struct intel_crtc *crtc``h]j)}(hjӳh]hstruct intel_crtc *crtc}(hjճhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjѳubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMohjͳubj)}(hhh]h)}(hthe CRTCh]hthe CRTC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMohjubah}(h]h ]h"]h$]h&]uh1jhjͳubeh}(h]h ]h"]h$]h&]uh1j|hjhMohjʳubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMqhjubh)}(hEThis function disables FBC if it's associated with the provided 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](jjeh"]h$]h&]jjuh1jyhjOhhhjahMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjvsb$c.intel_fbc_handle_fifo_underrun_irqasbuh1hhjubji)}(h h]h }(hjδhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjܴhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjOhhhjahMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjKhhhjahMubah}(h]jFah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjahMhjHhhubj1)}(hhh]h)}(h'disable FBC when we get a FIFO underrunh]h'disable FBC when we get a FIFO underrun}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjHhhhjahMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj+jSj+jTjUjVuh1j&hhhj{hNhNubjX)}(hX=**Parameters** ``struct intel_display *display`` display **Description** Without FBC, most underruns are harmless and don't really cause too many problems, except for an annoying message on dmesg. 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This function is called from the IRQ handler.h](h)}(h**Parameters**h]jb)}(hj5h]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj3ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhj/ubjx)}(hhh]j})}(h*``struct intel_display *display`` display h](j)}(h!``struct intel_display *display``h]j)}(hjTh]hstruct intel_display *display}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhjNubj)}(hhh]h)}(hdisplayh]hdisplay}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMhjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1j|hjihMhjKubah}(h]h ]h"]h$]h&]uh1jwhj/ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhj/ubh)}(hXWithout FBC, most underruns are harmless and don't really cause too many problems, except for an annoying message on dmesg. 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An underrun on any pipe already suggests that watermarks may be bad, so try to be as safe as possible.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhj/ubh)}(h-This function is called from the IRQ handler.h]h-This function is called from the IRQ handler.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj{hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_fbc_init (C function)c.intel_fbc_inithNtauh1jhj{hhhNhNubj')}(hhh](j,)}(h3void intel_fbc_init (struct intel_display *display)h]j2)}(h2void intel_fbc_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjߵhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM>ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjߵhhhjhM>ubjz)}(hintel_fbc_inith]j;)}(hintel_fbc_inith]hintel_fbc_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjߵhhhjhM>ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj@modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_fbc_initasbuh1hhjubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjߵhhhjhM>ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj۵hhhjhM>ubah}(h]jֵah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM>hjصhhubj1)}(hhh]h)}(hInitialize FBCh]hInitialize FBC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM>hjhhubah}(h]h ]h"]h$]h&]uh1j0hjصhhhjhM>ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj{hNhNubjX)}(h**Parameters** ``struct intel_display *display`` display **Description** This function might be called during PM init process.h](h)}(h**Parameters**h]jb)}(hjŶh]h Parameters}(hjǶhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjöubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMBhjubjx)}(hhh]j})}(h*``struct intel_display *display`` display h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chM?hj޶ubj)}(hhh]h)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM?hjubah}(h]h ]h"]h$]h&]uh1jhj޶ubeh}(h]h ]h"]h$]h&]uh1j|hjhM?hj۶ubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMAhjubh)}(h5This function might be called during PM init process.h]h5This function might be called during PM init process.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMAhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj{hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_fbc_sanitize (C function)c.intel_fbc_sanitizehNtauh1jhj{hhhNhNubj')}(hhh](j,)}(h7void intel_fbc_sanitize (struct intel_display *display)h]j2)}(h6void intel_fbc_sanitize(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMPubji)}(h h]h }(hjshhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`hhhjrhMPubjz)}(hintel_fbc_sanitizeh]j;)}(hintel_fbc_sanitizeh]hintel_fbc_sanitize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj`hhhjrhMPubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_fbc_sanitizeasbuh1hhjubji)}(h h]h }(hj߷hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj`hhhjrhMPubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj\hhhjrhMPubah}(h]jWah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjrhMPhjYhhubj1)}(hhh]h)}(h Sanitize FBCh]h Sanitize FBC}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMPhj!hhubah}(h]h ]h"]h$]h&]uh1j0hjYhhhjrhMPubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj<jSj<jTjUjVuh1j&hhhj{hNhNubjX)}(h**Parameters** ``struct intel_display *display`` display **Description** Make sure FBC is initially disabled since we have no idea eg. into which parts of stolen it might be scribbling into.h](h)}(h**Parameters**h]jb)}(hjFh]h Parameters}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjDubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMThj@ubjx)}(hhh]j})}(h*``struct intel_display *display`` display h](j)}(h!``struct intel_display *display``h]j)}(hjeh]hstruct intel_display *display}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMQhj_ubj)}(hhh]h)}(hdisplayh]hdisplay}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMQhj{ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hjzhMQhj\ubah}(h]h ]h"]h$]h&]uh1jwhj@ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMShj@ubh)}(huMake sure FBC is initially disabled since we have no idea eg. into which parts of stolen it might be scribbling into.h]huMake sure FBC is initially disabled since we have no idea eg. into which parts of stolen it might be scribbling into.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:180: ./drivers/gpu/drm/i915/display/intel_fbc.chMShj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj{hhhNhNubeh}(h]frame-buffer-compression-fbcah ]h"]frame buffer compression (fbc)ah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(h%Display Refresh Rate Switching (DRRS)h]h%Display Refresh Rate Switching (DRRS)}(hj׸hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjԸhhhhhKubh)}(hDisplay Refresh Rate Switching (DRRS) is a power conservation feature which enables swtching between low and high refresh rates, dynamically, based on the usage scenario. This feature is applicable for internal panels.h]hDisplay Refresh Rate Switching (DRRS) is a power conservation feature which enables swtching between low and high refresh rates, dynamically, based on the usage scenario. This feature is applicable for internal panels.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjԸhhubh)}(hIndication that the panel supports DRRS is given by the panel EDID, which would list multiple refresh rates for one resolution.h]hIndication that the panel supports DRRS is given by the panel EDID, which would list multiple refresh rates for one resolution.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjԸhhubh)}(hX\DRRS is of 2 types - static and seamless. Static DRRS involves changing refresh rate (RR) by doing a full modeset (may appear as a blink on screen) and is used in dock-undock scenario. Seamless DRRS involves changing RR without any visual effect to the user and can be used during normal system usage. This is done by programming certain registers.h]hX\DRRS is of 2 types - static and seamless. Static DRRS involves changing refresh rate (RR) by doing a full modeset (may appear as a blink on screen) and is used in dock-undock scenario. Seamless DRRS involves changing RR without any visual effect to the user and can be used during normal system usage. This is done by programming certain registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjԸhhubh)}(haSupport for static/seamless DRRS may be indicated in the VBT based on inputs from the panel spec.h]haSupport for static/seamless DRRS may be indicated in the VBT based on inputs from the panel spec.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK!hjԸhhubh)}(hADRRS saves power by switching to low RR based on usage scenarios.h]hADRRS saves power by switching to low RR based on usage scenarios.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK$hjԸhhubh)}(hX4The implementation is based on frontbuffer tracking implementation. When there is a disturbance on the screen triggered by user activity or a periodic system activity, DRRS is disabled (RR is changed to high RR). When there is no movement on screen, after a timeout of 1 second, a switch to low RR is made.h]hX4The implementation is based on frontbuffer tracking implementation. When there is a disturbance on the screen triggered by user activity or a periodic system activity, DRRS is disabled (RR is changed to high RR). When there is no movement on screen, after a timeout of 1 second, a switch to low RR is made.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK&hjԸhhubh)}(hjFor integration with frontbuffer tracking code, intel_drrs_invalidate() and intel_drrs_flush() are called.h]hjFor integration with frontbuffer tracking code, intel_drrs_invalidate() and intel_drrs_flush() are called.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK,hjԸhhubh)}(hDRRS can be further extended to support other internal panels and also the scenario of video playback wherein RR is set based on the rate requested by userspace.h]hDRRS can be further extended to support other internal panels and also the scenario of video playback wherein RR is set based on the rate requested by userspace.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:186: ./drivers/gpu/drm/i915/display/intel_drrs.chK/hjԸhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_drrs_activate (C function)c.intel_drrs_activatehNtauh1jhjԸhhhNhNubj')}(hhh](j,)}(hDvoid intel_drrs_activate (const struct intel_crtc_state *crtc_state)h]j2)}(hCvoid intel_drrs_activate(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrhhhjhKubjz)}(hintel_drrs_activateh]j;)}(hintel_drrs_activateh]hintel_drrs_activate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjrhhhjhKubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjιhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj۹hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_drrs_activateasbuh1hhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hj'hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjrhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjnhhhjhKubah}(h]jiah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjkhhubj1)}(hhh]h)}(h activate DRRSh]h activate DRRS}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjNhhubah}(h]h ]h"]h$]h&]uh1j0hjkhhhjhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjijSjijTjUjVuh1j&hhhjԸhNhNubjX)}(h|**Parameters** ``const struct intel_crtc_state *crtc_state`` the crtc state **Description** Activates DRRS on the crtc.h](h)}(h**Parameters**h]jb)}(hjsh]h Parameters}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjqubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjmubjx)}(hhh]j})}(h=``const struct intel_crtc_state *crtc_state`` the crtc state h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjubj)}(hhh]h)}(hthe crtc stateh]hthe crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubah}(h]h ]h"]h$]h&]uh1jwhjmubh)}(h**Description**h]jb)}(hjͺh]h Description}(hjϺhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj˺ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjmubh)}(hActivates DRRS on the crtc.h]hActivates DRRS on the crtc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjmubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjԸhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_drrs_deactivate (C function)c.intel_drrs_deactivatehNtauh1jhjԸhhhNhNubj')}(hhh](j,)}(hJvoid intel_drrs_deactivate (const struct intel_crtc_state *old_crtc_state)h]j2)}(hIvoid intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKubji)}(h h]h }(hj!hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj hKubjz)}(hintel_drrs_deactivateh]j;)}(hintel_drrs_deactivateh]hintel_drrs_deactivate}(hj3hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj hKubj)}(h/(const struct intel_crtc_state *old_crtc_state)h]j)}(h-const struct intel_crtc_state *old_crtc_stateh](j)}(hjR{h]hconst}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hj\hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj)}(hjh]hstruct}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hjwhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTj5sbc.intel_drrs_deactivateasbuh1hhjKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubj;)}(hold_crtc_stateh]hold_crtc_state}(hjûhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjGubah}(h]h ]h"]h$]h&]jjuh1jhjhhhj hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhj hKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj hKhjhhubj1)}(hhh]h)}(hdeactivate DRRSh]hdeactivate DRRS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjԸhNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *old_crtc_state`` the old crtc state **Description** Deactivates DRRS on the crtc.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhj ubjx)}(hhh]j})}(hE``const struct intel_crtc_state *old_crtc_state`` the old crtc state h](j)}(h1``const struct intel_crtc_state *old_crtc_state``h]j)}(hj.h]h-const struct intel_crtc_state *old_crtc_state}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhj(ubj)}(hhh]h)}(hthe old crtc stateh]hthe old crtc state}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChKhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1j|hjChKhj%ubah}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjih]h Description}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjgubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhj ubh)}(hDeactivates DRRS on the crtc.h]hDeactivates DRRS on the crtc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chKhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjԸhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_drrs_invalidate (C function)c.intel_drrs_invalidatehNtauh1jhjԸhhhNhNubj')}(hhh](j,)}(hYvoid intel_drrs_invalidate (struct intel_display *display, unsigned int frontbuffer_bits)h]j2)}(hXvoid intel_drrs_invalidate(struct intel_display *display, unsigned int frontbuffer_bits)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_drrs_invalidateh]j;)}(hintel_drrs_invalidateh]hintel_drrs_invalidate}(hjϼhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj˼ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h>(struct intel_display *display, unsigned int frontbuffer_bits)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjѼsbc.intel_drrs_invalidateasbuh1hhjubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubji)}(h h]h }(hjkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYubj)}(hinth]hint}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjYubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hDisable Idleness DRRSh]hDisable Idleness DRRS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj׽jSj׽jTjUjVuh1j&hhhjԸhNhNubjX)}(hXi**Parameters** ``struct intel_display *display`` display device ``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits **Description** This function gets called everytime rendering on the given planes start. Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj߽ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM hj۽ubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hB``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h!``unsigned int frontbuffer_bits``h]j)}(hj9h]hunsigned int frontbuffer_bits}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhj3ubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhMhjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j|hjNhMhjubeh}(h]h ]h"]h$]h&]uh1jwhj۽ubh)}(h**Description**h]jb)}(hjth]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjrubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM hj۽ubh)}(hThis function gets called everytime rendering on the given planes start. Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).h]hThis function gets called everytime rendering on the given planes start. Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM hj۽ubh)}(hIDirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.h]hIDirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM hj۽ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjԸhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_drrs_flush (C function)c.intel_drrs_flushhNtauh1jhjԸhhhNhNubj')}(hhh](j,)}(hTvoid intel_drrs_flush (struct intel_display *display, unsigned int frontbuffer_bits)h]j2)}(hSvoid intel_drrs_flush(struct intel_display *display, unsigned int frontbuffer_bits)h](j)}(hvoidh]hvoid}(hjȾhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjľhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMubji)}(h h]h }(hj׾hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjľhhhj־hMubjz)}(hintel_drrs_flushh]j;)}(hintel_drrs_flushh]hintel_drrs_flush}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjľhhhj־hMubj)}(h>(struct intel_display *display, unsigned int frontbuffer_bits)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj%modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_drrs_flushasbuh1hhjubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj^hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int frontbuffer_bitsh](j)}(hunsignedh]hunsigned}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjsubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjsubj;)}(hfrontbuffer_bitsh]hfrontbuffer_bits}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjľhhhj־hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj־hMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj־hMhjhhubj1)}(hhh]h)}(hRestart Idleness DRRSh]hRestart Idleness DRRS}(hjٿhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjֿhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj־hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjԸhNhNubjX)}(hX**Parameters** ``struct intel_display *display`` display device ``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits **Description** This function gets called every time rendering on the given planes has completed or flip on a crtc is completed. So DRRS should be upclocked (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, if no other planes are dirty. Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj/hMhjubj})}(hB``unsigned int frontbuffer_bits`` frontbuffer plane tracking bits h](j)}(h!``unsigned int frontbuffer_bits``h]j)}(hjSh]hunsigned int frontbuffer_bits}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjMubj)}(hhh]h)}(hfrontbuffer plane tracking bitsh]hfrontbuffer plane tracking bits}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j|hjhhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjubh)}(hThis function gets called every time rendering on the given planes has completed or flip on a crtc is completed. So DRRS should be upclocked (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, if no other planes are dirty.h]hThis function gets called every time rendering on the given planes has completed or flip on a crtc is completed. So DRRS should be upclocked (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, if no other planes are dirty.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjubh)}(hIDirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.h]hIDirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjԸhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_drrs_crtc_init (C function)c.intel_drrs_crtc_inithNtauh1jhjԸhhhNhNubj')}(hhh](j,)}(h3void intel_drrs_crtc_init (struct intel_crtc *crtc)h]j2)}(h2void intel_drrs_crtc_init(struct intel_crtc *crtc)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM(ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM(ubjz)}(hintel_drrs_crtc_inith]j;)}(hintel_drrs_crtc_inith]hintel_drrs_crtc_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM(ubj)}(h(struct intel_crtc *crtc)h]j)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj,hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hj=hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj:ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj?modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_drrs_crtc_initasbuh1hhjubji)}(h h]h }(hj]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hjxhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM(ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM(ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM(hjhhubj1)}(hhh]h)}(hInit DRRS for CRTCh]hInit DRRS for CRTC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM(hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM(ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjԸhNhNubjX)}(h**Parameters** ``struct intel_crtc *crtc`` crtc **Description** This function is called only once at driver load to initialize basic DRRS stuff.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM,hjubjx)}(hhh]j})}(h!``struct intel_crtc *crtc`` crtc h](j)}(h``struct intel_crtc *crtc``h]j)}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM)hjubj)}(hhh]h)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM)hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM+hjubh)}(hPThis function is called only once at driver load to initialize basic DRRS stuff.h]hPThis function is called only once at driver load to initialize basic DRRS stuff.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:189: ./drivers/gpu/drm/i915/display/intel_drrs.chM+hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjԸhhhNhNubeh}(h]#display-refresh-rate-switching-drrsah ]h"]%display refresh rate switching (drrs)ah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hDPIOh]hDPIO}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhhhhhKubh)}(hXVLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI ports. DPIO is the name given to such a display PHY. These PHYs don't follow the standard programming model using direct MMIO registers, and instead their registers must be accessed through IOSF sideband. VLV has one such PHY for driving ports B and C, and CHV adds another PHY for driving port D. Each PHY responds to specific IOSF-SB port.h]hXVLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI ports. DPIO is the name given to such a display PHY. These PHYs don’t follow the standard programming model using direct MMIO registers, and instead their registers must be accessed through IOSF sideband. VLV has one such PHY for driving ports B and C, and CHV adds another PHY for driving port D. Each PHY responds to specific IOSF-SB port.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK&hjRhhubh)}(hX9Each display PHY is made up of one or two channels. Each channel houses a common lane part which contains the PLL and other common logic. CH0 common lane also contains the IOSF-SB logic for the Common Register Interface (CRI) ie. the DPIO registers. CRI clock must be running when any DPIO registers are accessed.h]hX9Each display PHY is made up of one or two channels. Each channel houses a common lane part which contains the PLL and other common logic. CH0 common lane also contains the IOSF-SB logic for the Common Register Interface (CRI) ie. the DPIO registers. CRI clock must be running when any DPIO registers are accessed.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK.hjRhhubh)}(hIn addition to having their own registers, the PHYs are also controlled through some dedicated signals from the display controller. These include PLL reference clock enable, PLL enable, and CRI clock selection, for example.h]hIn addition to having their own registers, the PHYs are also controlled through some dedicated signals from the display controller. These include PLL reference clock enable, PLL enable, and CRI clock selection, for example.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK4hjRhhubh)}(hX,Eeach channel also has two splines (also called data lanes), and each spline is made up of one Physical Access Coding Sub-Layer (PCS) block and two TX lanes. So each channel has two PCS blocks and four TX lanes. The TX lanes are used as DP lanes or TMDS data/clock pairs depending on the output type.h]hX,Eeach channel also has two splines (also called data lanes), and each spline is made up of one Physical Access Coding Sub-Layer (PCS) block and two TX lanes. So each channel has two PCS blocks and four TX lanes. The TX lanes are used as DP lanes or TMDS data/clock pairs depending on the output type.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK9hjRhhubh)}(hX$Additionally the PHY also contains an AUX lane with AUX blocks for each channel. This is used for DP AUX communication, but this fact isn't really relevant for the driver since AUX is controlled from the display controller side. No DPIO registers need to be accessed during AUX communication,h]hX&Additionally the PHY also contains an AUX lane with AUX blocks for each channel. This is used for DP AUX communication, but this fact isn’t really relevant for the driver since AUX is controlled from the display controller side. No DPIO registers need to be accessed during AUX communication,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK?hjRhhubh)}(hmGenerally on VLV/CHV the common lane corresponds to the pipe and the spline (PCS/TX) corresponds to the port.h]hmGenerally on VLV/CHV the common lane corresponds to the pipe and the spline (PCS/TX) corresponds to the port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKEhjRhhubh)}(hFor dual channel PHY (VLV/CHV):h]hFor dual channel PHY (VLV/CHV):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKHhjRhhubh block_quote)}(hapipe A == CMN/PLL/REF CH0 pipe B == CMN/PLL/REF CH1 port B == PCS/TX CH0 port C == PCS/TX CH1 h](h)}(hpipe A == CMN/PLL/REF CH0h]hpipe A == CMN/PLL/REF CH0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKJhjubh)}(hpipe B == CMN/PLL/REF CH1h]hpipe B == CMN/PLL/REF CH1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKLhjubh)}(hport B == PCS/TX CH0h]hport B == PCS/TX CH0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKNhjubh)}(hport C == PCS/TX CH1h]hport C == PCS/TX CH1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKPhjubeh}(h]h ]h"]h$]h&]uh1jhjhKJhjRhhubh)}(hkThis is especially important when we cross the streams ie. drive port B with pipe B, or port C with pipe A.h]hkThis is especially important when we cross the streams ie. drive port B with pipe B, or port C with pipe A.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKRhjRhhubh)}(hFor single channel PHY (CHV):h]hFor single channel PHY (CHV):}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKUhjRhhubj)}(h0pipe C == CMN/PLL/REF CH0 port D == PCS/TX CH0 h](h)}(hpipe C == CMN/PLL/REF CH0h]hpipe C == CMN/PLL/REF CH0}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKWhj2ubh)}(hport D == PCS/TX CH0h]hport D == PCS/TX CH0}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKYhj2ubeh}(h]h ]h"]h$]h&]uh1jhjDhKWhjRhhubh)}(hX3On BXT the entire PHY channel corresponds to the port. That means the PLL is also now associated with the port rather than the pipe, and so the clock needs to be routed to the appropriate transcoder. Port A PLL is directly connected to transcoder EDP and port B/C PLLs can be routed to any transcoder A/B/C.h]hX3On BXT the entire PHY channel corresponds to the port. That means the PLL is also now associated with the port rather than the pipe, and so the clock needs to be routed to the appropriate transcoder. Port A PLL is directly connected to transcoder EDP and port B/C PLLs can be routed to any transcoder A/B/C.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chK[hjRhhubh)}(hiNote: DDI0 is digital port B, DD1 is digital port C, and DDI2 is digital port D (CHV) or port A (BXT). ::h]hfNote: DDI0 is digital port B, DD1 is digital port C, and DDI2 is digital port D (CHV) or port A (BXT).}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKahjRhhubj")}(hXwDual channel PHY (VLV/CHV/BXT) --------------------------------- | CH0 | CH1 | | CMN/PLL/REF | CMN/PLL/REF | |---------------|---------------| Display PHY | PCS01 | PCS23 | PCS01 | PCS23 | |-------|-------|-------|-------| |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| --------------------------------- | DDI0 | DDI1 | DP/HDMI ports --------------------------------- Single channel PHY (CHV/BXT) ----------------- | CH0 | | CMN/PLL/REF | |---------------| Display PHY | PCS01 | PCS23 | |-------|-------| |TX0|TX1|TX2|TX3| ----------------- | DDI2 | DP/HDMI port -----------------h]hXwDual channel PHY (VLV/CHV/BXT) --------------------------------- | CH0 | CH1 | | CMN/PLL/REF | CMN/PLL/REF | |---------------|---------------| Display PHY | PCS01 | PCS23 | PCS01 | PCS23 | |-------|-------|-------|-------| |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| --------------------------------- | DDI0 | DDI1 | DP/HDMI ports --------------------------------- Single channel PHY (CHV/BXT) ----------------- | CH0 | | CMN/PLL/REF | |---------------| Display PHY | PCS01 | PCS23 | |-------|-------| |TX0|TX1|TX2|TX3| ----------------- | DDI2 | DP/HDMI port -----------------}hjxsbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:195: ./drivers/gpu/drm/i915/display/intel_dpio_phy.chKehjRhhubeh}(h]dpioah ]h"]dpioah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hDMC Firmware Supporth]hDMC Firmware Support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hFrom gen9 onwards we have newly added DMC (Display microcontroller) in display engine to save and restore the state of display engine when it enter into low-power state and comes back to normal.h]hFrom gen9 onwards we have newly added DMC (Display microcontroller) in display engine to save and restore the state of display engine when it enter into low-power state and comes back to normal.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:201: ./drivers/gpu/drm/i915/display/intel_dmc.chK&hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!intel_dmc_block_pkgc (C function)c.intel_dmc_block_pkgchNtauh1jhjhhhNhNubj')}(hhh](j,)}(hUvoid intel_dmc_block_pkgc (struct intel_display *display, enum pipe pipe, bool block)h]j2)}(hTvoid intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, bool block)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_dmc_block_pkgch]j;)}(hintel_dmc_block_pkgch]hintel_dmc_block_pkgc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h;(struct intel_display *display, enum pipe pipe, bool block)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj%modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_block_pkgcasbuh1hhjubji)}(h h]h }(hjChhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj^hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(henum pipe pipeh](j)}(hjh]henum}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjsubh)}(hhh]j;)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j?c.intel_dmc_block_pkgcasbuh1hhjsubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjsubj;)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjsubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h bool blockh](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hblockh]hblock}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hblock PKG C-stateh]hblock PKG C-state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj7jSj7jTjUjVuh1j&hhhjhNhNubjX)}(hXA**Parameters** ``struct intel_display *display`` display instance ``enum pipe pipe`` pipe which register use to block ``bool block`` block/unblock **Description** This interface is target for Wa_16025596647 usage. I.e. to set/clear PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register.h](h)}(h**Parameters**h]jb)}(hjAh]h Parameters}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM hj;ubjx)}(hhh](j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj`h]hstruct intel_display *display}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM hjZubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhM hjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1j|hjuhM hjWubj})}(h4``enum pipe pipe`` pipe which register use to block h](j)}(h``enum pipe pipe``h]j)}(hjh]henum pipe pipe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM hjubj)}(hhh]h)}(h pipe which register use to blockh]h pipe which register use to block}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjWubj})}(h``bool block`` block/unblock h](j)}(h``bool block``h]j)}(hjh]h bool block}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM hjubj)}(hhh]h)}(h block/unblockh]h block/unblock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjWubeh}(h]h ]h"]h$]h&]uh1jwhj;ubh)}(h**Description**h]jb)}(hj h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM hj;ubh)}(hThis interface is target for Wa_16025596647 usage. I.e. to set/clear PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register.h]hThis interface is target for Wa_16025596647 usage. I.e. to set/clear PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM hj;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"Cintel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank (C function)8c.intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hxvoid intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank (struct intel_display *display, enum pipe pipe, bool enable)h]j2)}(hwvoid intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, enum pipe pipe, bool enable)h](j)}(hvoidh]hvoid}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMubji)}(h h]h }(hjahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjNhhhj`hMubjz)}(h6intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankh]j;)}(h6intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankh]h6intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank}(hjshhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjoubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjNhhhj`hMubj)}(h<(struct intel_display *display, enum pipe pipe, bool enable)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjusb8c.intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(henum pipe pipeh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hpipeh]hpipe}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj!modnameN classnameNjXj[)}j^]j8c.intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankasbuh1hhjubji)}(h h]h }(hj=hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hpipeh]hpipe}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h bool enableh](j)}(hjh]hbool}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubj;)}(henableh]henable}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjNhhhj`hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjJhhhj`hMubah}(h]jEah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj`hMhjGhhubj1)}(hhh]h)}(hstart of PKG C-state exith]hstart of PKG C-state exit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjGhhhj`hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX%**Parameters** ``struct intel_display *display`` display instance ``enum pipe pipe`` pipe which register use to block ``bool enable`` enable/disable **Description** This interface is target for Wa_16025596647 usage. I.e. start the package C exit at the start of the undelayed vblankh](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubjx)}(hhh](j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(h4``enum pipe pipe`` pipe which register use to block h](j)}(h``enum pipe pipe``h]j)}(hj#h]henum pipe pipe}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]h)}(h pipe which register use to blockh]h pipe which register use to block}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj8hMhjubj})}(h``bool enable`` enable/disable h](j)}(h``bool enable``h]j)}(hj\h]h bool enable}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjVubj)}(hhh]h)}(henable/disableh]henable/disable}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhMhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j|hjqhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubh)}(huThis interface is target for Wa_16025596647 usage. I.e. start the package C exit at the start of the undelayed vblankh]huThis interface is target for Wa_16025596647 usage. I.e. start the package C exit at the start of the undelayed vblank}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_dmc_load_program (C function)c.intel_dmc_load_programhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h;void intel_dmc_load_program (struct intel_display *display)h]j2)}(h:void intel_dmc_load_program(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMsubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMsubjz)}(hintel_dmc_load_programh]j;)}(hintel_dmc_load_programh]hintel_dmc_load_program}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMsubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj&hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj4ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj9modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_load_programasbuh1hhjubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjrhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMsubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMsubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMshjhhubj1)}(hhh]h)}(h+write the firmware from memory to register.h]h+write the firmware from memory to register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMshjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMsubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX$**Parameters** ``struct intel_display *display`` display instance **Description** DMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMwhjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMthjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMthjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMthjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMvhjubh)}(hDMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.h]hDMC firmware is read from a .bin file and kept in internal memory one time. Everytime display comes back from low power state this function is called to copy the firmware from internal memory to registers.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMvhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_dmc_disable_program (C function)c.intel_dmc_disable_programhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h>void intel_dmc_disable_program (struct intel_display *display)h]j2)}(h=void intel_dmc_disable_program(struct intel_display *display)h](j)}(hvoidh]hvoid}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMubji)}(h h]h }(hjlhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYhhhjkhMubjz)}(hintel_dmc_disable_programh]j;)}(hintel_dmc_disable_programh]hintel_dmc_disable_program}(hj~hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjYhhhjkhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_disable_programasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjYhhhjkhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjUhhhjkhMubah}(h]jPah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjkhMhjRhhubj1)}(hhh]h)}(hdisable the firmwareh]hdisable the firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjRhhhjkhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj5jSj5jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Disable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.h](h)}(h**Parameters**h]jb)}(hj?h]h Parameters}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj=ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj9ubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj^h]hstruct intel_display *display}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjXubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMhjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1j|hjshMhjUubah}(h]h ]h"]h$]h&]uh1jwhj9ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj9ubh)}(htDisable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.h]htDisable all event handlers in the firmware, making sure the firmware is inactive after the display is uninitialized.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dmc_init (C function)c.intel_dmc_inithNtauh1jhjhhhNhNubj')}(hhh](j,)}(h3void intel_dmc_init (struct intel_display *display)h]j2)}(h2void intel_dmc_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM[ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM[ubjz)}(hintel_dmc_inith]j;)}(hintel_dmc_inith]hintel_dmc_init}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM[ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj9hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj6ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj;modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_initasbuh1hhjubji)}(h h]h }(hjYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjthhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM[ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM[ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM[hjhhubj1)}(hhh]h)}(h initialize the firmware loading.h]h initialize the firmware loading.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM[hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM[ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** This function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM_hjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM\hjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM\hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM\hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM^hjubh)}(hThis function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.h]hThis function is called at the time of loading the display driver to read firmware from a .bin file and copied into a internal memory.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chM^hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dmc_suspend (C function)c.intel_dmc_suspendhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h6void intel_dmc_suspend (struct intel_display *display)h]j2)}(h5void intel_dmc_suspend(struct intel_display *display)h](j)}(hvoidh]hvoid}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMubji)}(h h]h }(hjnhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj[hhhjmhMubjz)}(hintel_dmc_suspendh]j;)}(hintel_dmc_suspendh]hintel_dmc_suspend}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj[hhhjmhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_suspendasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj[hhhjmhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjWhhhjmhMubah}(h]jRah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjmhMhjThhubj1)}(hhh]h)}(h*prepare DMC firmware before system suspendh]h*prepare DMC firmware before system suspend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjThhhjmhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj7jSj7jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Prepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.h](h)}(h**Parameters**h]jb)}(hjAh]h Parameters}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj;ubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj`h]hstruct intel_display *display}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjZubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1j|hjuhMhjWubah}(h]h ]h"]h$]h&]uh1jwhj;ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj;ubh)}(hPrepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.h]hPrepare the DMC firmware before entering system suspend. This includes flushing pending work items and releasing any resources acquired during init.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dmc_resume (C function)c.intel_dmc_resumehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h5void intel_dmc_resume (struct intel_display *display)h]j2)}(h4void intel_dmc_resume(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_dmc_resumeh]j;)}(hintel_dmc_resumeh]hintel_dmc_resume}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj*hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj8ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj=modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_resumeasbuh1hhjubji)}(h h]h }(hj[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjvhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h&init DMC firmware during system resumeh]h&init DMC firmware during system resume}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Reinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubh)}(hnReinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().h]hnReinitialize the DMC firmware during system resume, reacquiring any resources released in intel_dmc_suspend().}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dmc_fini (C function)c.intel_dmc_finihNtauh1jhjhhhNhNubj')}(hhh](j,)}(h3void intel_dmc_fini (struct intel_display *display)h]j2)}(h2void intel_dmc_fini(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMubji)}(h h]h }(hjphhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]hhhjohMubjz)}(hintel_dmc_finih]j;)}(hintel_dmc_finih]hintel_dmc_fini}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj]hhhjohMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dmc_finiasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj]hhhjohMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjYhhhjohMubah}(h]jTah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjohMhjVhhubj1)}(hhh]h)}(hunload the DMC firmware.h]hunload the DMC firmware.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjVhhhjohMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj9jSj9jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Firmmware unloading includes freeing the internal memory and reset the firmware loading status.h](h)}(h**Parameters**h]jb)}(hjCh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjAubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj=ubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjbh]hstruct intel_display *display}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:204: ./drivers/gpu/drm/i915/display/intel_dmc.chMhj\ubj)}(hhh]h)}(hdisplay instanceh]hdisplay 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Wake lock is only required when DC5, DC6, or DC6v have been enabled in DC_STATE_EN and the wake lock mode of operation has been enabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:210: ./drivers/gpu/drm/i915/display/intel_dmc_wl.chKhjhhubh)}(hXThe wakelock mechanism in DMC allows the display engine to exit DC states explicitly before programming registers that may be powered down. In earlier hardware, this was done automatically and implicitly when the display engine accessed a register. With the wakelock implementation, the driver asserts a wakelock in DMC, which forces it to exit the DC state until the wakelock is deasserted.h]hXThe wakelock mechanism in DMC allows the display engine to exit DC states explicitly before programming registers that may be powered down. In earlier hardware, this was done automatically and implicitly when the display engine accessed a register. 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The other definitions are here for potential future use.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:210: ./drivers/gpu/drm/i915/display/intel_dmc_wl.chK#hjhhubeh}(h]dmc-wakelock-supportah ]h"]dmc wakelock supportah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hVideo BIOS Table (VBT)h]hVideo BIOS Table (VBT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX/The Video BIOS Table, or VBT, provides platform and board specific configuration information to the driver that is not discoverable or available through other means. The configuration is mostly related to display hardware. The VBT is available via the ACPI OpRegion or, on older systems, in the PCI ROM.h]hX/The Video BIOS Table, or VBT, provides platform and board specific configuration information to the driver that is not discoverable or available through other means. The configuration is mostly related to display hardware. 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The data blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of data. (Block 53, the MIPI Sequence Block is an exception.)}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj_hK6hjhhubh)}(hThe driver parses the VBT during load. The relevant information is stored in driver private data for ease of use, and the actual VBT is not read after that.h]hThe driver parses the VBT during load. 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size_t sizeh](h)}(hhh]j;)}(hsize_th]hsize_t}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j+c.intel_bios_is_valid_vbtasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h)does the given buffer contain a valid VBTh]h)does the given buffer contain a valid VBT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj1jSj1jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display device ``const void *buf`` pointer to a buffer to validate ``size_t size`` size of the buffer **Description** Returns true on valid VBT.h](h)}(h**Parameters**h]jb)}(hj;h]h Parameters}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj9ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hj5ubjx)}(hhh](j})}(h1``struct intel_display *display`` display device h](j)}(h!``struct intel_display *display``h]j)}(hjZh]hstruct intel_display *display}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjTubj)}(hhh]h)}(hdisplay deviceh]hdisplay device}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohM hjpubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j|hjohM hjQubj})}(h4``const void *buf`` pointer to a buffer to validate h](j)}(h``const void *buf``h]j)}(hjh]hconst void *buf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubj)}(hhh]h)}(hpointer to a buffer to validateh]hpointer to a buffer to validate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjQubj})}(h#``size_t size`` size of the buffer h](j)}(h``size_t size``h]j)}(hjh]h size_t size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubj)}(hhh]h)}(hsize of the bufferh]hsize of the buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjQubeh}(h]h ]h"]h$]h&]uh1jwhj5ubh)}(h**Description**h]jb)}(hjh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hj5ubh)}(hReturns true on valid VBT.h]hReturns true on valid VBT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: 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refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjosbc.intel_bios_initasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjHhhhjZhMB ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjDhhhjZhMB ubah}(h]j?ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjZhMB hjAhhubj1)}(hhh]h)}(h.find VBT and initialize settings from the BIOSh]h.find VBT and initialize settings from the BIOS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMB hj hhubah}(h]h ]h"]h$]h&]uh1j0hjAhhhjZhMB ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj$jSj$jTjUjVuh1j&hhhjhNhNubjX)}(hX)**Parameters** ``struct intel_display *display`` display device instance **Description** Parse and initialize settings from the Video BIOS Tables (VBT). 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Also initialize some defaults if the VBT is not present at all.h](h)}(h**Parameters**h]jb)}(hj.h]h Parameters}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMF hj(ubjx)}(hhh]j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjMh]hstruct intel_display *display}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMC hjGubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMC hjcubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1j|hjbhMC hjDubah}(h]h ]h"]h$]h&]uh1jwhj(ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chME hj(ubh)}(hParse and initialize settings from the Video BIOS Tables (VBT). If the VBT was not found in ACPI OpRegion, try to find it in PCI ROM first. Also initialize some defaults if the VBT is not present at all.h]hParse and initialize settings from the Video BIOS Tables (VBT). If the VBT was not found in ACPI OpRegion, try to find it in PCI ROM first. Also initialize some defaults if the VBT is not present at all.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chME hj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_bios_driver_remove (C function)c.intel_bios_driver_removehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h=void intel_bios_driver_remove (struct intel_display *display)h]j2)}(hubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj=hM hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjch]h Description}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jahjaubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubh)}(h]Return true if TV is present. If no child devices were parsed from VBT, assume TV is present.h]h]Return true if TV is present. If no child devices were parsed from VBT, assume TV is present.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_bios_is_lvds_present (C function)c.intel_bios_is_lvds_presenthNtauh1jhjhhhNhNubj')}(hhh](j,)}(hLbool intel_bios_is_lvds_present (struct intel_display *display, u8 *i2c_pin)h]j2)}(hKbool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_bios_is_lvds_presenth]j;)}(hintel_bios_is_lvds_presenth]hintel_bios_is_lvds_present}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h,(struct intel_display *display, u8 *i2c_pin)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_bios_is_lvds_presentasbuh1hhjubji)}(h h]h }(hj"hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj=hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u8 *i2c_pinh](h)}(hhh]j;)}(hu8h]hu8}(hjYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj[modnameN classnameNjXj[)}j^]jc.intel_bios_is_lvds_presentasbuh1hhjRubji)}(h h]h }(hjwhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj;)}(hi2c_pinh]hi2c_pin}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(his LVDS present in VBTh]his LVDS present in VBT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display device instance ``u8 *i2c_pin`` i2c pin for LVDS if present **Description** Return true if LVDS is present. If no child devices were parsed from VBT, assume LVDS is present.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubj})}(h,``u8 *i2c_pin`` i2c pin for LVDS if present h](j)}(h``u8 *i2c_pin``h]j)}(hj6h]h u8 *i2c_pin}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hj0ubj)}(hhh]h)}(hi2c pin for LVDS if presenth]hi2c pin for LVDS if present}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM hjLubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1j|hjKhM hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjqh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jahjoubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubh)}(haReturn true if LVDS is present. If no child devices were parsed from VBT, assume LVDS is present.h]haReturn true if LVDS is present. If no child devices were parsed from VBT, assume LVDS is present.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_bios_is_port_present (C function)c.intel_bios_is_port_presenthNtauh1jhjhhhNhNubj')}(hhh](j,)}(hObool intel_bios_is_port_present (struct intel_display *display, enum port port)h]j2)}(hNbool intel_bios_is_port_present(struct intel_display *display, enum port port)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM/ ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM/ ubjz)}(hintel_bios_is_port_presenth]j;)}(hintel_bios_is_port_presenth]hintel_bios_is_port_present}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM/ ubj)}(h/(struct intel_display *display, enum port port)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_bios_is_port_presentasbuh1hhjubji)}(h h]h }(hj0hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(henum port porth](j)}(hjh]henum}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubh)}(hhh]j;)}(hporth]hport}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j,c.intel_bios_is_port_presentasbuh1hhj`ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubj;)}(hporth]hport}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM/ ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM/ ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM/ hjhhubj1)}(hhh]h)}(h%is the specified digital port presenth]h%is the specified digital port present}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM/ hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM/ ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display device instance ``enum port port`` port to check **Description** Return true if the device in ``port`` is present.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM3 hjubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM0 hjubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hM0 hj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj.hM0 hjubj})}(h!``enum port port`` port to check h](j)}(h``enum port port``h]j)}(hjRh]henum port port}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM1 hjLubj)}(hhh]h)}(h port to checkh]h port to check}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghM1 hjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjghM1 hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM3 hjubh)}(h1Return true if the device in ``port`` is present.h](hReturn true if the device in }(hjhhhNhNubj)}(h``port``h]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh is present.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM3 hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_bios_is_dsi_present (C function)c.intel_bios_is_dsi_presenthNtauh1jhjhhhNhNubj')}(hhh](j,)}(hObool intel_bios_is_dsi_present (struct intel_display *display, enum port *port)h]j2)}(hNbool intel_bios_is_dsi_present(struct intel_display *display, enum port *port)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM` ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM` ubjz)}(hintel_bios_is_dsi_presenth]j;)}(hintel_bios_is_dsi_presenth]hintel_bios_is_dsi_present}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM` ubj)}(h0(struct intel_display *display, enum port *port)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj@modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_bios_is_dsi_presentasbuh1hhjubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(henum port *porth](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hporth]hport}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jZc.intel_bios_is_dsi_presentasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hporth]hport}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM` ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM` ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM` hjhhubj1)}(hhh]h)}(his DSI present in VBTh]his DSI present in VBT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chM` hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM` ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj+jSj+jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` display device instance ``enum port *port`` port for DSI if present **Description** Return true if DSI is present, and return the port in ``port``.h](h)}(h**Parameters**h]jb)}(hj5h]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj3ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMd hj/ubjx)}(hhh](j})}(h:``struct intel_display *display`` display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjTh]hstruct intel_display *display}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: ./drivers/gpu/drm/i915/display/intel_bios.chMa hjNubj)}(hhh]h)}(hdisplay device instanceh]hdisplay device instance}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMa hjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1j|hjihMa hjKubj})}(h,``enum port *port`` port for DSI if present h](j)}(h``enum port *port``h]j)}(hjh]henum port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:219: 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Downscaling must also be accounted as that increases the effective pixel rate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chK:hj}hhubh)}(hXOn several platforms the CDCLK frequency can be changed dynamically to minimize power consumption for a given display configuration. Typically changes to the CDCLK frequency require all the display pipes to be shut down while the frequency is being changed.h]hXOn several platforms the CDCLK frequency can be changed dynamically to minimize power consumption for a given display configuration. Typically changes to the CDCLK frequency require all the display pipes to be shut down while the frequency is being changed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chK?hj}hhubh)}(hOn SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. DMC will not change the active CDCLK frequency however, so that part will still be performed by the driver directly.h]hOn SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. DMC will not change the active CDCLK frequency however, so that part will still be performed by the driver directly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKDhj}hhubh)}(hPThere are multiple components involved in the generation of the CDCLK frequency:h]hPThere are multiple components involved in the generation of the CDCLK frequency:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKHhj}hhubj:)}(hhh](j:)}(hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.h]h)}(hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.h]hhWe have the CDCLK PLL, which generates an output clock based on a reference clock and a ratio parameter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.h]h)}(htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.h]htThe CD2X Divider, which divides the output of the PLL based on a divisor selected from a set of pre-defined choices.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKMhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero "squashes out" a clock cycle.h]h)}(hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero "squashes out" a clock cycle.h]hThe CD2X Squasher, which further divides the output based on a waveform represented as a sequence of bits where each zero “squashes out” a clock cycle.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKOhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hFAnd, finally, a fixed divider that divides the output frequency by 2. h]h)}(hEAnd, finally, a fixed divider that divides the output frequency by 2.h]hEAnd, finally, a fixed divider that divides the output frequency by 2.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKRhj'ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKKhj}hhubh)}(hTAs such, the resulting CDCLK frequency can be calculated with the following formula:h]hTAs such, the resulting CDCLK frequency can be calculated with the following formula:}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKThj}hhubj)}(h/cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 h]h)}(h.cdclk = vco / cd2x_div / (sq_len / sq_div) / 2h]h.cdclk = vco / cd2x_div / (sq_len / sq_div) / 2}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKWhjUubah}(h]h ]h"]h$]h&]uh1jhjghKWhj}hhubh)}(h, where vco is the frequency generated by the PLL; cd2x_div represents the CD2X Divider; sq_len and sq_div are the bit length and the number of high bits for the CD2X Squasher waveform, respectively; and 2 represents the fixed divider.h]h, where vco is the frequency generated by the PLL; cd2x_div represents the CD2X Divider; sq_len and sq_div are the bit length and the number of high bits for the CD2X Squasher waveform, respectively; and 2 represents the fixed divider.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKYhj}hhubh)}(hNote that some older platforms do not contain the CD2X Divider and/or CD2X Squasher, in which case we can ignore their respective factors in the formula above.h]hNote that some older platforms do not contain the CD2X Divider and/or CD2X Squasher, in which case we can ignore their respective factors in the formula above.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chK^hj}hhubh)}(hfSeveral methods exist to change the CDCLK frequency, which ones are supported depends on the platform:h]hfSeveral methods exist to change the CDCLK frequency, which ones are supported depends on the platform:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKbhj}hhubj:)}(hhh](j:)}(hLFull PLL disable + re-enable with new VCO frequency. Pipes must be inactive.h]h)}(hjh]hLFull PLL disable + re-enable with new VCO frequency. Pipes must be inactive.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKehjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hyCD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe's start of vblank.h]h)}(hyCD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe's start of vblank.h]h{CD2X divider update. Single pipe can be active as the divider update can be synchronized with the pipe’s start of vblank.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKfhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hECrawl the PLL smoothly to the new VCO frequency. Pipes can be active.h]h)}(hjh]hECrawl the PLL smoothly to the new VCO frequency. Pipes can be active.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKhhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h,Squash waveform update. Pipes can be active.h]h)}(hjh]h,Squash waveform update. Pipes can be active.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKihjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hECrawl and squash can also be done back to back. Pipes can be active. h]h)}(hDCrawl and squash can also be done back to back. Pipes can be active.h]hDCrawl and squash can also be done back to back. Pipes can be active.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKjhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKehj}hhubh)}(hRAWCLK is a fixed frequency clock, often used by various auxiliary blocks such as AUX CH or backlight PWM. Hence the only thing we really need to know about RAWCLK is its frequency so that various dividers can be programmed correctly.h]hRAWCLK is a fixed frequency clock, often used by various auxiliary blocks such as AUX CH or backlight PWM. Hence the only thing we really need to know about RAWCLK is its frequency so that various dividers can be programmed correctly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:228: ./drivers/gpu/drm/i915/display/intel_cdclk.chKlhj}hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_cdclk_init_hw (C function)c.intel_cdclk_init_hwhNtauh1jhj}hhhNhNubj')}(hhh](j,)}(h8void intel_cdclk_init_hw (struct intel_display *display)h]j2)}(h7void intel_cdclk_init_hw(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMubji)}(h h]h }(hjUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjBhhhjThMubjz)}(hintel_cdclk_init_hwh]j;)}(hintel_cdclk_init_hwh]hintel_cdclk_init_hw}(hjghhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjBhhhjThMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjisbc.intel_cdclk_init_hwasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj{ubah}(h]h ]h"]h$]h&]jjuh1jhjBhhhjThMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj>hhhjThMubah}(h]j9ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjThMhj;hhubj1)}(hhh]h)}(hInitialize CDCLK hardwareh]hInitialize CDCLK hardware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj;hhhjThMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj}hNhNubjX)}(hXf**Parameters** ``struct intel_display *display`` display instance **Description** Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.h](h)}(h**Parameters**h]jb)}(hj(h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj&ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj"ubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjGh]hstruct intel_display *display}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjAubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hM hj]ubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1j|hj\hM hj>ubah}(h]h ]h"]h$]h&]uh1jwhj"ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj"ubh)}(hXInitialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.h]hXInitialize CDCLK. This consists mainly of initializing display->cdclk.hw and sanitizing the state of the hardware if needed. This is generally done only during the display core initialization sequence, after which the DMC will take care of turning CDCLK off/on as needed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_cdclk_uninit_hw (C function)c.intel_cdclk_uninit_hwhNtauh1jhj}hhhNhNubj')}(hhh](j,)}(h:void intel_cdclk_uninit_hw (struct intel_display *display)h]j2)}(h9void intel_cdclk_uninit_hw(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_cdclk_uninit_hwh]j;)}(hintel_cdclk_uninit_hwh]hintel_cdclk_uninit_hw}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj"hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj$modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_cdclk_uninit_hwasbuh1hhjubji)}(h h]h }(hjBhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(hUninitialize CDCLK hardwareh]hUninitialize CDCLK hardware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj}hNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Uninitialize CDCLK. This is done only during the display core uninitialization sequence.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubh)}(hXUninitialize CDCLK. This is done only during the display core uninitialization sequence.h]hXUninitialize CDCLK. This is done only during the display core uninitialization sequence.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_cdclk_clock_changed (C function)c.intel_cdclk_clock_changedhNtauh1jhj}hhhNhNubj')}(hhh](j,)}(hgbool intel_cdclk_clock_changed (const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j2)}(hfbool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hjh]hbool}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM^ ubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjDhhhjUhM^ ubjz)}(hintel_cdclk_clock_changedh]j;)}(hintel_cdclk_clock_changedh]hintel_cdclk_clock_changed}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjdubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjDhhhjUhM^ ubj)}(hH(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(h"const struct intel_cdclk_config *ah](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjjsbc.intel_cdclk_clock_changedasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hah]ha}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj|ubj)}(h"const struct intel_cdclk_config *bh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]hstruct}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj9hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjJhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjGubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjLmodnameN classnameNjXj[)}j^]jc.intel_cdclk_clock_changedasbuh1hhj ubji)}(h h]h }(hjhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hbh]hb}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj|ubeh}(h]h ]h"]h$]h&]jjuh1jhjDhhhjUhM^ ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj@hhhjUhM^ ubah}(h]j;ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjUhM^ hj=hhubj1)}(hhh]h)}(hCheck whether the clock changedh]hCheck whether the clock changed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM^ hjhhubah}(h]h ]h"]h$]h&]uh1j0hj=hhhjUhM^ ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj}hNhNubjX)}(h**Parameters** ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if CDCLK changed in a way that requires re-programming and False otherwise.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMb hjubjx)}(hhh](j})}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hjh]h"const struct intel_cdclk_config *a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM_ hjubj)}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM_ hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM_ hjubj})}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hj'h]h"const struct intel_cdclk_config *b}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM` hj!ubj)}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM` hj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j|hj<hM` hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h **Return**h]jb)}(hjbh]hReturn}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMb hjubh)}(hPTrue if CDCLK changed in a way that requires re-programming and False otherwise.h]hPTrue if CDCLK changed in a way that requires re-programming and False otherwise.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMb hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"(intel_cdclk_can_cd2x_update (C function)c.intel_cdclk_can_cd2x_updatehNtauh1jhj}hhhNhNubj')}(hhh](j,)}(hbool intel_cdclk_can_cd2x_update (struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j2)}(hbool intel_cdclk_can_cd2x_update(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMo ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMo ubjz)}(hintel_cdclk_can_cd2x_updateh]j;)}(hintel_cdclk_can_cd2x_updateh]hintel_cdclk_can_cd2x_update}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMo ubj)}(hg(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_cdclk_can_cd2x_updateasbuh1hhjubji)}(h h]h }(hj!hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj<hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h"const struct intel_cdclk_config *ah](j)}(hjR{h]hconst}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hjbhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj)}(hjh]hstruct}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hj}hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_cdclk_can_cd2x_updateasbuh1hhjQubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj;)}(hjh]ha}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h"const struct intel_cdclk_config *bh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_cdclk_can_cd2x_updateasbuh1hhjubji)}(h h]h }(hj6hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hjh]hb}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMo ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMo ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMo hjhhubj1)}(hhh]h)}(h^Determine if changing between the two CDCLK configurations requires only a cd2x divider updateh]h^Determine if changing between the two CDCLK configurations requires only a cd2x divider update}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMo hjwhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMo ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj}hNhNubjX)}(hXK**Parameters** ``struct intel_display *display`` display instance ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMs hjubjx)}(hhh](j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMq hjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMq hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMq hjubj})}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hjh]h"const struct intel_cdclk_config *a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMr hjubj)}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMr hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hMr hjubj})}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hj-h]h"const struct intel_cdclk_config *b}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMs hj'ubj)}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMs hjCubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1j|hjBhMs hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h **Return**h]jb)}(hjhh]hReturn}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjfubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMu hjubh)}(hpTrue if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.h]hpTrue if changing between the two CDCLK configurations can be done with just a cd2x divider update, false if not.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMu hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_cdclk_changed (C function)c.intel_cdclk_changedhNtauh1jhj}hhhNhNubj')}(hhh](j,)}(habool intel_cdclk_changed (const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h]j2)}(h`bool intel_cdclk_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_cdclk_changedh]j;)}(hintel_cdclk_changedh]hintel_cdclk_changed}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(hH(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b)h](j)}(h"const struct intel_cdclk_config *ah](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hj"hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj$modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_cdclk_changedasbuh1hhjubji)}(h h]h }(hjBhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hjh]ha}(hj]hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h"const struct intel_cdclk_config *bh](j)}(hjR{h]hconst}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubh)}(hhh]j;)}(hintel_cdclk_configh]hintel_cdclk_config}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j>c.intel_cdclk_changedasbuh1hhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj;)}(hjh]hb}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjqubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h3Determine if two CDCLK configurations are differenth]h3Determine if two CDCLK configurations are different}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj(jSj(jTjUjVuh1j&hhhj}hNhNubjX)}(h**Parameters** ``const struct intel_cdclk_config *a`` first CDCLK configuration ``const struct intel_cdclk_config *b`` second CDCLK configuration **Return** True if the CDCLK configurations don't match, false if they do.h](h)}(h**Parameters**h]jb)}(hj2h]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj0ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj,ubjx)}(hhh](j})}(hA``const struct intel_cdclk_config *a`` first CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *a``h]j)}(hjQh]h"const struct intel_cdclk_config *a}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjKubj)}(hhh]h)}(hfirst CDCLK configurationh]hfirst CDCLK configuration}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhM hjgubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1j|hjfhM hjHubj})}(hB``const struct intel_cdclk_config *b`` second CDCLK configuration h](j)}(h&``const struct intel_cdclk_config *b``h]j)}(hjh]h"const struct intel_cdclk_config *b}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hsecond CDCLK configurationh]hsecond CDCLK configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjHubeh}(h]h ]h"]h$]h&]uh1jwhj,ubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj,ubh)}(h?True if the CDCLK configurations don't match, false if they do.h]hATrue if the CDCLK configurations don’t match, false if they do.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"-intel_set_cdclk_pre_plane_update (C function)"c.intel_set_cdclk_pre_plane_updatehNtauh1jhj}hhhNhNubj')}(hhh](j,)}(hHvoid intel_set_cdclk_pre_plane_update (struct intel_atomic_state *state)h]j2)}(hGvoid intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMd ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMd ubjz)}(h intel_set_cdclk_pre_plane_updateh]j;)}(h intel_set_cdclk_pre_plane_updateh]h intel_set_cdclk_pre_plane_update}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMd ubj)}(h"(struct intel_atomic_state *state)h]j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubji)}(h h]h }(hjThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjCubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjbubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjgmodnameN classnameNjXj[)}j^]ja)}jTj-sb"c.intel_set_cdclk_pre_plane_updateasbuh1hhjCubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjCubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubj;)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj?ubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMd ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMd ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMd hjhhubj1)}(hhh]h)}(h$Push the CDCLK state to the hardwareh]h$Push the CDCLK state to the hardware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMd hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMd ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj}hNhNubjX)}(h**Parameters** ``struct intel_atomic_state *state`` intel atomic state **Description** Program the hardware before updating the HW plane state based on the new CDCLK state, if necessary.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMh hjubjx)}(hhh]j})}(h8``struct intel_atomic_state *state`` intel atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hj h]h struct intel_atomic_state *state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMe hjubj)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMe hj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hMe hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjFh]h Description}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjDubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMg hjubh)}(hcProgram the hardware before updating the HW plane state based on the new CDCLK state, if necessary.h]hcProgram the hardware before updating the HW plane state based on the new CDCLK state, if necessary.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chMg hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j".intel_set_cdclk_post_plane_update (C function)#c.intel_set_cdclk_post_plane_updatehNtauh1jhj}hhhNhNubj')}(hhh](j,)}(hIvoid intel_set_cdclk_post_plane_update (struct intel_atomic_state *state)h]j2)}(hHvoid intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(h!intel_set_cdclk_post_plane_updateh]j;)}(h!intel_set_cdclk_post_plane_updateh]h!intel_set_cdclk_post_plane_update}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h"(struct intel_atomic_state *state)h]j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsb#c.intel_set_cdclk_post_plane_updateasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hstateh]hstate}(hj!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]j~ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h$Push the CDCLK state to the hardwareh]h$Push the CDCLK state to the hardware}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjHhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjcjSjcjTjUjVuh1j&hhhj}hNhNubjX)}(h**Parameters** ``struct intel_atomic_state *state`` intel atomic state **Description** Program the hardware after updating the HW plane state based on the new CDCLK state, if necessary.h](h)}(h**Parameters**h]jb)}(hjmh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jahjkubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjgubjx)}(hhh]j})}(h8``struct intel_atomic_state *state`` intel atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hintel atomic stateh]hintel atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubah}(h]h ]h"]h$]h&]uh1jwhjgubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjgubh)}(hbProgram the hardware after updating the HW plane state based on the new CDCLK state, if necessary.h]hbProgram the hardware after updating the HW plane state based on the new CDCLK state, if necessary.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_update_max_cdclk (C function)c.intel_update_max_cdclkhNtauh1jhj}hhhNhNubj')}(hhh](j,)}(h;void intel_update_max_cdclk (struct intel_display *display)h]j2)}(h:void intel_update_max_cdclk(struct intel_display *display)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM6 ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM6 ubjz)}(hintel_update_max_cdclkh]j;)}(hintel_update_max_cdclkh]hintel_update_max_cdclk}(hj-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM6 ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjghhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjdubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjimodnameN classnameNjXj[)}j^]ja)}jTj/sbc.intel_update_max_cdclkasbuh1hhjEubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjAubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM6 ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM6 ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM6 hjhhubj1)}(hhh]h)}(h-Determine the maximum support CDCLK frequencyh]h-Determine the maximum support CDCLK frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM6 hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM6 ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj}hNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Determine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM: hjubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hj h]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM7 hjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM7 hj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj"hM7 hjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjHh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM9 hjubh)}(hDetermine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.h]hDetermine the maximum CDCLK frequency the platform supports, and also derive the maximum dot clock frequency the maximum CDCLK frequency allows.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM9 hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_update_cdclk (C function)c.intel_update_cdclkhNtauh1jhj}hhhNhNubj')}(hhh](j,)}(h7void intel_update_cdclk (struct intel_display *display)h]j2)}(h6void intel_update_cdclk(struct intel_display *display)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hintel_update_cdclkh]j;)}(hintel_update_cdclkh]hintel_update_cdclk}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_update_cdclkasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj#hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h%Determine the current CDCLK frequencyh]h%Determine the current CDCLK frequency}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjJhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjejSjejTjUjVuh1j&hhhj}hNhNubjX)}(h}**Parameters** ``struct intel_display *display`` display instance **Description** Determine the current CDCLK frequency.h](h)}(h**Parameters**h]jb)}(hjoh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjmubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjiubjx)}(hhh]j})}(h3``struct intel_display *display`` display instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjubj)}(hhh]h)}(hdisplay instanceh]hdisplay instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM hjubah}(h]h ]h"]h$]h&]uh1jwhjiubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjiubh)}(h&Determine the current CDCLK frequency.h]h&Determine the current CDCLK frequency.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjiubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj}hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_read_rawclk (C function)c.intel_read_rawclkhNtauh1jhj}hhhNhNubj')}(hhh](j,)}(h5u32 intel_read_rawclk (struct intel_display *display)h]j2)}(h4u32 intel_read_rawclk(struct intel_display *display)h](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTintel_read_rawclksbc.intel_read_rawclkasbuh1hhj hhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM ubji)}(h h]h }(hj3hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj hhhj2hM ubjz)}(hintel_read_rawclkh]j;)}(hj/h]hintel_read_rawclk}(hjEhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj hhhj2hM ubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj~hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j-c.intel_read_rawclkasbuh1hhj\ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjXubah}(h]h ]h"]h$]h&]jjuh1jhj hhhj2hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj2hM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj2hM hjhhubj1)}(hhh]h)}(h&Determine the current RAWCLK frequencyh]h&Determine the current RAWCLK frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:231: ./drivers/gpu/drm/i915/display/intel_cdclk.chM hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj2hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj}hNhNubjX)}(h**Parameters** ``struct intel_display *display`` display instance **Description** Determine the current RAWCLK frequency. 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While some have per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL from a pool. In the latter scenario, it is possible that multiple pipes share a PLL if their configurations match.h]hXDisplay PLLs used for driving outputs vary by platform. While some have per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL from a pool. In the latter scenario, it is possible that multiple pipes share a PLL if their configurations match.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:237: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chK/hjhhubh)}(hXcThis file provides an abstraction over display PLLs. The function intel_shared_dpll_init() initializes the PLLs for the given platform. The users of a PLL are tracked and that tracking is integrated with the atomic modset interface. During an atomic operation, required PLLs can be reserved for a given CRTC and encoder configuration by calling intel_reserve_shared_dplls() and previously reserved PLLs can be released with intel_release_shared_dplls(). Changes to the users are first staged in the atomic state, and then made effective by calling intel_shared_dpll_swap_state() during the atomic commit phase.h]hXcThis file provides an abstraction over display PLLs. The function intel_shared_dpll_init() initializes the PLLs for the given platform. The users of a PLL are tracked and that tracking is integrated with the atomic modset interface. During an atomic operation, required PLLs can be reserved for a given CRTC and encoder configuration by calling intel_reserve_shared_dplls() and previously reserved PLLs can be released with intel_release_shared_dplls(). Changes to the users are first staged in the atomic state, and then made effective by calling intel_shared_dpll_swap_state() during the atomic commit phase.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:237: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chK4hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"(intel_get_shared_dpll_by_id (C function)c.intel_get_shared_dpll_by_idhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hmstruct intel_shared_dpll * intel_get_shared_dpll_by_id (struct intel_display *display, enum intel_dpll_id id)h]j2)}(hkstruct intel_shared_dpll *intel_get_shared_dpll_by_id(struct intel_display *display, enum intel_dpll_id id)h](j)}(hjh]hstruct}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKubji)}(h h]h }(hjBhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj0hhhjAhKubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjPubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjUmodnameN classnameNjXj[)}j^]ja)}jTintel_get_shared_dpll_by_idsbc.intel_get_shared_dpll_by_idasbuh1hhj0hhhjAhKubji)}(h h]h }(hjthhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj0hhhjAhKubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0hhhjAhKubjz)}(hintel_get_shared_dpll_by_idh]j;)}(hjqh]hintel_get_shared_dpll_by_id}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj0hhhjAhKubj)}(h6(struct intel_display *display, enum intel_dpll_id id)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]joc.intel_get_shared_dpll_by_idasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(henum intel_dpll_id idh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj+hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_dpll_idh]h intel_dpll_id}(hj<hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj9ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj>modnameN classnameNjXj[)}j^]joc.intel_get_shared_dpll_by_idasbuh1hhjubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hidh]hid}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhj0hhhjAhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj,hhhjAhKubah}(h]j'ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjAhKhj)hhubj1)}(hhh]h)}(hget a DPLL given its idh]hget a DPLL given its id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hj)hhhjAhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` intel_display device instance ``enum intel_dpll_id id`` pll id **Return** A pointer to the DPLL with **id**h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubjx)}(hhh](j})}(h@``struct intel_display *display`` intel_display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubj)}(hhh]h)}(hintel_display device instanceh]hintel_display device instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h!``enum intel_dpll_id id`` pll id h](j)}(h``enum intel_dpll_id id``h]j)}(hj h]henum intel_dpll_id id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubj)}(hhh]h)}(hpll idh]hpll id}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hKhj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj!hKhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h **Return**h]jb)}(hjGh]hReturn}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjEubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubh)}(h!A pointer to the DPLL with **id**h](hA pointer to the DPLL with }(hj]hhhNhNubjb)}(h**id**h]hid}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jahj]ubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_enable_shared_dpll (C function)c.intel_enable_shared_dpllhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hIvoid intel_enable_shared_dpll (const struct intel_crtc_state *crtc_state)h]j2)}(hHvoid intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(hintel_enable_shared_dpllh]j;)}(hintel_enable_shared_dpllh]hintel_enable_shared_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_enable_shared_dpllasbuh1hhjubji)}(h h]h }(hj0hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(henable a CRTC's shared DPLLh]henable a CRTC’s shared DPLL}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjrhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL **Description** Enable the shared DPLL used by **crtc**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh]j})}(h[``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjh]h)const struct intel_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chKhjubj)}(hhh]h)}(h,CRTC, and its state, which has a shared DPLLh]h,CRTC, and its state, which has a shared DPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(h(Enable the shared DPLL used by **crtc**.h](hEnable the shared DPLL used by }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_disable_shared_dpll (C function)c.intel_disable_shared_dpllhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hJvoid intel_disable_shared_dpll (const struct intel_crtc_state *crtc_state)h]j2)}(hIvoid intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)h](j)}(hvoidh]hvoid}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM+ubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjDhhhjVhM+ubjz)}(hintel_disable_shared_dpllh]j;)}(hintel_disable_shared_dpllh]hintel_disable_shared_dpll}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjeubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjDhhhjVhM+ubj)}(h+(const struct intel_crtc_state *crtc_state)h]j)}(h)const struct intel_crtc_state *crtc_stateh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjksbc.intel_disable_shared_dpllasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj}ubah}(h]h ]h"]h$]h&]jjuh1jhjDhhhjVhM+ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj@hhhjVhM+ubah}(h]j;ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjVhM+hj=hhubj1)}(hhh]h)}(hdisable a CRTC's shared DPLLh]hdisable a CRTC’s shared DPLL}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM+hj hhubah}(h]h ]h"]h$]h&]uh1j0hj=hhhjVhM+ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj;jSj;jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL **Description** Disable the shared DPLL used by **crtc**.h](h)}(h**Parameters**h]jb)}(hjEh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjCubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM/hj?ubjx)}(hhh]j})}(h[``const struct intel_crtc_state *crtc_state`` CRTC, and its state, which has a shared DPLL h](j)}(h-``const struct intel_crtc_state *crtc_state``h]j)}(hjdh]h)const struct intel_crtc_state *crtc_state}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM,hj^ubj)}(hhh]h)}(h,CRTC, and its state, which has a shared DPLLh]h,CRTC, and its state, which has a shared DPLL}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhM,hjzubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1j|hjyhM,hj[ubah}(h]h ]h"]h$]h&]uh1jwhj?ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM.hj?ubh)}(h)Disable the shared DPLL used by **crtc**.h](h Disable the shared DPLL used by }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM.hj?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"-intel_reference_shared_dpll_crtc (C function)"c.intel_reference_shared_dpll_crtchNtauh1jhjhhhNhNubj')}(hhh](j,)}(hvoid intel_reference_shared_dpll_crtc (const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h]j2)}(hvoid intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(h intel_reference_shared_dpll_crtch]j;)}(h intel_reference_shared_dpll_crtch]h intel_reference_shared_dpll_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(hw(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h](j)}(hconst struct intel_crtc *crtch](j)}(hjR{h]hconst}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubji)}(h h]h }(hj@hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/ubj)}(hjh]hstruct}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubji)}(h h]h }(hj[hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/ubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjlhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjiubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjnmodnameN classnameNjXj[)}j^]ja)}jTjsb"c.intel_reference_shared_dpll_crtcasbuh1hhj/ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+ubj)}(h#const struct intel_shared_dpll *pllh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j"c.intel_reference_shared_dpll_crtcasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hpllh]hpll}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+ubj)}(h1struct intel_shared_dpll_state *shared_dpll_stateh](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubji)}(h h]h }(hjXhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjGubh)}(hhh]j;)}(hintel_shared_dpll_stateh]hintel_shared_dpll_state}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjfubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjkmodnameN classnameNjXj[)}j^]j"c.intel_reference_shared_dpll_crtcasbuh1hhjGubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjGubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj;)}(hshared_dpll_stateh]hshared_dpll_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjGubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+ubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hGet a DPLL reference for a CRTCh]hGet a DPLL reference for a CRTC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXt**Parameters** ``const struct intel_crtc *crtc`` CRTC on which behalf the reference is taken ``const struct intel_shared_dpll *pll`` DPLL for which the reference is taken ``struct intel_shared_dpll_state *shared_dpll_state`` the DPLL atomic state in which the reference is tracked **Description** Take a reference for **pll** tracking the use of it by **crtc**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(hN``const struct intel_crtc *crtc`` CRTC on which behalf the reference is taken h](j)}(h!``const struct intel_crtc *crtc``h]j)}(hj h]hconst struct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h+CRTC on which behalf the reference is takenh]h+CRTC on which behalf the reference is taken}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj"hMhjubj})}(hN``const struct intel_shared_dpll *pll`` DPLL for which the reference is taken h](j)}(h'``const struct intel_shared_dpll *pll``h]j)}(hjFh]h#const struct intel_shared_dpll *pll}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj@ubj)}(hhh]h)}(h%DPLL for which the reference is takenh]h%DPLL for which the reference is taken}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hMhj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1j|hj[hMhjubj})}(hn``struct intel_shared_dpll_state *shared_dpll_state`` the DPLL atomic state in which the reference is tracked h](j)}(h5``struct intel_shared_dpll_state *shared_dpll_state``h]j)}(hjh]h1struct intel_shared_dpll_state *shared_dpll_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjyubj)}(hhh]h)}(h7the DPLL atomic state in which the reference is trackedh]h7the DPLL atomic state in which the reference is tracked}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(h@Take a reference for **pll** tracking the use of it by **crtc**.h](hTake a reference for }(hjhhhNhNubjb)}(h**pll**h]hpll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh tracking the use of it by }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"/intel_unreference_shared_dpll_crtc (C function)$c.intel_unreference_shared_dpll_crtchNtauh1jhjhhhNhNubj')}(hhh](j,)}(hvoid intel_unreference_shared_dpll_crtc (const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h]j2)}(hvoid intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h](j)}(hvoidh]hvoid}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj1hMubjz)}(h"intel_unreference_shared_dpll_crtch]j;)}(h"intel_unreference_shared_dpll_crtch]h"intel_unreference_shared_dpll_crtc}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj1hMubj)}(hw(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state)h](j)}(hconst struct intel_crtc *crtch](j)}(hjR{h]hconst}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\ubj)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\ubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjFsb$c.intel_unreference_shared_dpll_crtcasbuh1hhj\ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj\ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjXubj)}(h#const struct intel_shared_dpll *pllh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hj&hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj(modnameN classnameNjXj[)}j^]j$c.intel_unreference_shared_dpll_crtcasbuh1hhjubji)}(h h]h }(hjDhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hpllh]hpll}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjXubj)}(h1struct intel_shared_dpll_state *shared_dpll_stateh](j)}(hjh]hstruct}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjtubh)}(hhh]j;)}(hintel_shared_dpll_stateh]hintel_shared_dpll_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j$c.intel_unreference_shared_dpll_crtcasbuh1hhjtubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjtubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubj;)}(hshared_dpll_stateh]hshared_dpll_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjtubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjXubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj1hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj1hMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj1hMhjhhubj1)}(hhh]h)}(h Drop a DPLL reference for a CRTCh]h Drop a DPLL reference for a CRTC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj1hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``const struct intel_crtc *crtc`` CRTC on which behalf the reference is dropped ``const struct intel_shared_dpll *pll`` DPLL for which the reference is dropped ``struct intel_shared_dpll_state *shared_dpll_state`` the DPLL atomic state in which the reference is tracked **Description** Drop a reference for **pll** tracking the end of use of it by **crtc**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(hP``const struct intel_crtc *crtc`` CRTC on which behalf the reference is dropped h](j)}(h!``const struct intel_crtc *crtc``h]j)}(hj:h]hconst struct intel_crtc *crtc}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj4ubj)}(hhh]h)}(h-CRTC on which behalf the reference is droppedh]h-CRTC on which behalf the reference is dropped}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhMhjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1j|hjOhMhj1ubj})}(hP``const struct intel_shared_dpll *pll`` DPLL for which the reference is dropped h](j)}(h'``const struct intel_shared_dpll *pll``h]j)}(hjsh]h#const struct intel_shared_dpll *pll}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjmubj)}(hhh]h)}(h'DPLL for which the reference is droppedh]h'DPLL for which the reference is dropped}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj1ubj})}(hn``struct intel_shared_dpll_state *shared_dpll_state`` the DPLL atomic state in which the reference is tracked h](j)}(h5``struct intel_shared_dpll_state *shared_dpll_state``h]j)}(hjh]h1struct intel_shared_dpll_state *shared_dpll_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h7the DPLL atomic state in which the reference is trackedh]h7the DPLL atomic state in which the reference is tracked}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhj1ubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hGDrop a reference for **pll** tracking the end of use of it by **crtc**.h](hDrop a reference for }(hjhhhNhNubjb)}(h**pll**h]hpll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh" tracking the end of use of it by }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_shared_dpll_swap_state (C function)c.intel_shared_dpll_swap_statehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hDvoid intel_shared_dpll_swap_state (struct intel_atomic_state *state)h]j2)}(hCvoid intel_shared_dpll_swap_state(struct intel_atomic_state *state)h](j)}(hvoidh]hvoid}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hj_hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjLhhhj^hMubjz)}(hintel_shared_dpll_swap_stateh]j;)}(hintel_shared_dpll_swap_stateh]hintel_shared_dpll_swap_state}(hjqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjLhhhj^hMubj)}(h"(struct intel_atomic_state *state)h]j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjssbc.intel_shared_dpll_swap_stateasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjLhhhj^hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjHhhhj^hMubah}(h]jCah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj^hMhjEhhubj1)}(hhh]h)}(h(make atomic DPLL configuration effectiveh]h(make atomic DPLL configuration effective}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj hhubah}(h]h ]h"]h$]h&]uh1j0hjEhhhj^hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj(jSj(jTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state **Description** This is the dpll version of drm_atomic_helper_swap_state() since the helper does not handle driver-specific global state. For consistency with atomic helpers this function does a complete swap, i.e. it also puts the current state into **state**, even though there is no need for that at this moment.h](h)}(h**Parameters**h]jb)}(hj2h]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj0ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj,ubjx)}(hhh]j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjQh]h struct intel_atomic_state *state}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjKubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMhjgubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1j|hjfhMhjHubah}(h]h ]h"]h$]h&]uh1jwhj,ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj,ubh)}(hyThis is the dpll version of drm_atomic_helper_swap_state() since the helper does not handle driver-specific global state.h]hyThis is the dpll version of drm_atomic_helper_swap_state() since the helper does not handle driver-specific global state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj,ubh)}(hFor consistency with atomic helpers this function does a complete swap, i.e. it also puts the current state into **state**, even though there is no need for that at this moment.h](hqFor consistency with atomic helpers this function does a complete swap, i.e. it also puts the current state into }(hjhhhNhNubjb)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh7, even though there is no need for that at this moment.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%icl_set_active_port_dpll (C function)c.icl_set_active_port_dpllhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hgvoid icl_set_active_port_dpll (struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id)h]j2)}(hfvoid icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM ubjz)}(hicl_set_active_port_dpllh]j;)}(hicl_set_active_port_dpllh]hicl_set_active_port_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM ubj)}(hI(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id)h](j)}(h#struct intel_crtc_state *crtc_stateh](j)}(hjh]hstruct}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubji)}(h h]h }(hj<hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+ubh)}(hhh]j;)}(hintel_crtc_stateh]hintel_crtc_state}(hjMhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjJubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjOmodnameN classnameNjXj[)}j^]ja)}jTjsbc.icl_set_active_port_dpllasbuh1hhj+ubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubj;)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj'ubj)}(h"enum icl_port_dpll_id port_dpll_idh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hicl_port_dpll_idh]hicl_port_dpll_id}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jic.icl_set_active_port_dpllasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h port_dpll_idh]h port_dpll_id}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj'ubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM hjhhubj1)}(hhh]h)}(h,select the active port DPLL for a given CRTCh]h,select the active port DPLL for a given CRTC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hj hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj- jSj- jTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_crtc_state *crtc_state`` state for the CRTC to select the DPLL for ``enum icl_port_dpll_id port_dpll_id`` the active **port_dpll_id** to select **Description** Select the given **port_dpll_id** instance from the DPLLs reserved for the CRTC.h](h)}(h**Parameters**h]jb)}(hj7 h]h Parameters}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj5 ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hj1 ubjx)}(hhh](j})}(hR``struct intel_crtc_state *crtc_state`` state for the CRTC to select the DPLL for h](j)}(h'``struct intel_crtc_state *crtc_state``h]j)}(hjV h]h#struct intel_crtc_state *crtc_state}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjP ubj)}(hhh]h)}(h)state for the CRTC to select the DPLL forh]h)state for the CRTC to select the DPLL for}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk hM hjl ubah}(h]h ]h"]h$]h&]uh1jhjP ubeh}(h]h ]h"]h$]h&]uh1j|hjk hM hjM ubj})}(hM``enum icl_port_dpll_id port_dpll_id`` the active **port_dpll_id** to select h](j)}(h&``enum icl_port_dpll_id port_dpll_id``h]j)}(hj h]h"enum icl_port_dpll_id port_dpll_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hj ubj)}(hhh]h)}(h%the active **port_dpll_id** to selecth](h the active }(hj hhhNhNubjb)}(h**port_dpll_id**h]h port_dpll_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh to select}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hM hjM ubeh}(h]h ]h"]h$]h&]uh1jwhj1 ubh)}(h**Description**h]jb)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hj1 ubh)}(hPSelect the given **port_dpll_id** instance from the DPLLs reserved for the CRTC.h](hSelect the given }(hj hhhNhNubjb)}(h**port_dpll_id**h]h port_dpll_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh/ instance from the DPLLs reserved for the CRTC.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hj1 ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_shared_dpll_init (C function)c.intel_shared_dpll_inithNtauh1jhjhhhNhNubj')}(hhh](j,)}(h;void intel_shared_dpll_init (struct intel_display *display)h]j2)}(h:void intel_shared_dpll_init(struct intel_display *display)h](j)}(hvoidh]hvoid}(hj3 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjB hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/ hhhjA hMubjz)}(hintel_shared_dpll_inith]j;)}(hintel_shared_dpll_inith]hintel_shared_dpll_init}(hjT hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjP ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj/ hhhjA hMubj)}(h(struct intel_display *display)h]j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjp hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl ubji)}(h h]h }(hj} hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjl ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjV sbc.intel_shared_dpll_initasbuh1hhjl ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjl ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl ubj;)}(hdisplayh]hdisplay}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjl ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjh ubah}(h]h ]h"]h$]h&]jjuh1jhj/ hhhjA hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj+ hhhjA hMubah}(h]j& ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjA hMhj( hhubj1)}(hhh]h)}(hInitialize shared DPLLsh]hInitialize shared DPLLs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj hhubah}(h]h ]h"]h$]h&]uh1j0hj( hhhjA hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct intel_display *display`` intel_display device **Description** Initialize shared DPLLs for **display**.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubjx)}(hhh]j})}(h7``struct intel_display *display`` intel_display device h](j)}(h!``struct intel_display *display``h]j)}(hj4 h]hstruct intel_display *display}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2 ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj. ubj)}(hhh]h)}(hintel_display deviceh]hintel_display device}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI hMhjJ ubah}(h]h ]h"]h$]h&]uh1jhj. ubeh}(h]h ]h"]h$]h&]uh1j|hjI hMhj+ ubah}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjo h]h Description}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjm ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubh)}(h(Initialize shared DPLLs for **display**.h](hInitialize shared DPLLs for }(hj hhhNhNubjb)}(h **display**h]hdisplay}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_compute_shared_dplls (C function)c.intel_compute_shared_dpllshNtauh1jhjhhhNhNubj')}(hhh](j,)}(hyint intel_compute_shared_dplls (struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h]j2)}(hxint intel_compute_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(hinth]hint}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj hhhj hM ubjz)}(hintel_compute_shared_dpllsh]j;)}(hintel_compute_shared_dpllsh]hintel_compute_shared_dplls}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj hhhj hM ubj)}(hZ(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hj! hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj# modnameN classnameNjXj[)}j^]ja)}jTj sbc.intel_compute_shared_dpllsasbuh1hhj ubji)}(h h]h }(hjA hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hjO hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hstateh]hstate}(hj\ hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hju hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjq ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjq ubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]j= c.intel_compute_shared_dpllsasbuh1hhjq ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjq ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjq ubj;)}(hcrtch]hcrtc}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjq ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]j= c.intel_compute_shared_dpllsasbuh1hhj ubji)}(h h]h }(hj! hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj/ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hencoderh]hencoder}(hj< hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubeh}(h]h ]h"]h$]h&]jjuh1jhj hhhj hM ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhj hM ubah}(h]j ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj hM hj hhubj1)}(hhh]h)}(h/compute DPLL state CRTC and encoder combinationh]h/compute DPLL state CRTC and encoder combination}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM hjc hhubah}(h]h ]h"]h$]h&]uh1j0hj hhhj hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj~ jSj~ jTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` CRTC to compute DPLLs for ``struct intel_encoder *encoder`` encoder **Description** This function computes the DPLL state for the given CRTC and encoder. The new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state(). **Return** 0 on success, negative error code on failure.h](h)}(h**Parameters**h]jb)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubjx)}(hhh](j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hj h]h struct intel_atomic_state *state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(h atomic stateh]h atomic state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hMhj ubj})}(h6``struct intel_crtc *crtc`` CRTC to compute DPLLs for h](j)}(h``struct intel_crtc *crtc``h]j)}(hj h]hstruct intel_crtc *crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(hCRTC to compute DPLLs forh]hCRTC to compute DPLLs for}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hMhj ubj})}(h*``struct intel_encoder *encoder`` encoder h](j)}(h!``struct intel_encoder *encoder``h]j)}(hjh]hstruct intel_encoder *encoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(hencoderh]hencoder}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj.hMhj ubeh}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjTh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjRubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubh)}(hEThis function computes the DPLL state for the given CRTC and encoder.h]hEThis function computes the DPLL state for the given CRTC and encoder.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubh)}(hqThe new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state().h](h+The new configuration in the atomic commit }(hjyhhhNhNubjb)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjyubh= is made effective by calling intel_shared_dpll_swap_state().}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubh)}(h-0 on success, negative error code on failure.h]h-0 on success, negative error code on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_reserve_shared_dplls (C function)c.intel_reserve_shared_dpllshNtauh1jhjhhhNhNubj')}(hhh](j,)}(hyint intel_reserve_shared_dplls (struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h]j2)}(hxint intel_reserve_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM(ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM(ubjz)}(hintel_reserve_shared_dpllsh]j;)}(hintel_reserve_shared_dpllsh]hintel_reserve_shared_dplls}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM(ubj)}(hZ(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj+hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hj<hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj9ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj>modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_reserve_shared_dpllsasbuh1hhjubji)}(h h]h }(hj\hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hstateh]hstate}(hjwhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jXc.intel_reserve_shared_dpllsasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jXc.intel_reserve_shared_dpllsasbuh1hhjubji)}(h h]h }(hj<hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hencoderh]hencoder}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM(ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM(ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM(hjhhubj1)}(hhh]h)}(h.reserve DPLLs for CRTC and encoder combinationh]h.reserve DPLLs for CRTC and encoder combination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM(hj~hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM(ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX}**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` CRTC to reserve DPLLs for ``struct intel_encoder *encoder`` encoder **Description** This function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit **state** and the new **crtc** atomic state. The new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state(). The reserved DPLLs should be released by calling intel_release_shared_dplls(). **Return** 0 if all required DPLLs were successfully reserved, negative error code otherwise.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM,hjubjx)}(hhh](j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM)hjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM)hjubj})}(h6``struct intel_crtc *crtc`` CRTC to reserve DPLLs for h](j)}(h``struct intel_crtc *crtc``h]j)}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM*hjubj)}(hhh]h)}(hCRTC to reserve DPLLs forh]hCRTC to reserve DPLLs for}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM*hjubj})}(h*``struct intel_encoder *encoder`` encoder h](j)}(h!``struct intel_encoder *encoder``h]j)}(hj4h]hstruct intel_encoder *encoder}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM+hj.ubj)}(hhh]h)}(hencoderh]hencoder}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhM+hjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hjIhM+hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjoh]h Description}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjmubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM-hjubh)}(hThis function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit **state** and the new **crtc** atomic state.h](hrThis function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit }(hjhhhNhNubjb)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and the new }(hjhhhNhNubjb)}(h**crtc**h]hcrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh atomic state.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM-hjubh)}(hqThe new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state().h](h+The new configuration in the atomic commit }(hjhhhNhNubjb)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh= is made effective by calling intel_shared_dpll_swap_state().}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM1hjubh)}(hNThe reserved DPLLs should be released by calling intel_release_shared_dplls().h]hNThe reserved DPLLs should be released by calling intel_release_shared_dplls().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM4hjubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM7hjubh)}(hR0 if all required DPLLs were successfully reserved, negative error code otherwise.h]hR0 if all required DPLLs were successfully reserved, negative error code otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM7hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_release_shared_dplls (C function)c.intel_release_shared_dpllshNtauh1jhjhhhNhNubj')}(hhh](j,)}(h[void intel_release_shared_dplls (struct intel_atomic_state *state, struct intel_crtc *crtc)h]j2)}(hZvoid intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(hvoidh]hvoid}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMIubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+hhhj=hMIubjz)}(hintel_release_shared_dpllsh]j;)}(hintel_release_shared_dpllsh]hintel_release_shared_dplls}(hjPhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjLubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj+hhhj=hMIubj)}(h;(struct intel_atomic_state *state, struct intel_crtc *crtc)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubji)}(h h]h }(hjyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjRsbc.intel_release_shared_dpllsasbuh1hhjhubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj;)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjdubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_release_shared_dpllsasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hcrtch]hcrtc}(hj5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjdubeh}(h]h ]h"]h$]h&]jjuh1jhj+hhhj=hMIubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj'hhhj=hMIubah}(h]j"ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj=hMIhj$hhubj1)}(hhh]h)}(h(end use of DPLLs by CRTC in atomic stateh]h(end use of DPLLs by CRTC in atomic state}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMIhj\hhubah}(h]h ]h"]h$]h&]uh1j0hj$hhhj=hMIubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjwjSjwjTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` crtc from which the DPLLs are to be released **Description** This function releases all DPLLs reserved by intel_reserve_shared_dplls() from the current atomic commit **state** and the old **crtc** atomic state. The new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state().h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMMhj{ubjx)}(hhh](j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMJhjubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMJhjubj})}(hI``struct intel_crtc *crtc`` crtc from which the DPLLs are to be released h](j)}(h``struct intel_crtc *crtc``h]j)}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMKhjubj)}(hhh]h)}(h,crtc from which the DPLLs are to be releasedh]h,crtc from which the DPLLs are to be released}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMKhjubeh}(h]h ]h"]h$]h&]uh1jwhj{ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMMhj{ubh)}(hThis function releases all DPLLs reserved by intel_reserve_shared_dplls() from the current atomic commit **state** and the old **crtc** atomic state.h](hiThis function releases all DPLLs reserved by intel_reserve_shared_dplls() from the current atomic commit }(hj*hhhNhNubjb)}(h **state**h]hstate}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj*ubh and the old }(hj*hhhNhNubjb)}(h**crtc**h]hcrtc}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj*ubh atomic state.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMMhj{ubh)}(hqThe new configuration in the atomic commit **state** is made effective by calling intel_shared_dpll_swap_state().h](h+The new configuration in the atomic commit }(hj]hhhNhNubjb)}(h **state**h]hstate}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jahj]ubh= is made effective by calling intel_shared_dpll_swap_state().}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMPhj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_update_active_dpll (C function)c.intel_update_active_dpllhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hxvoid intel_update_active_dpll (struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h]j2)}(hwvoid intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMfubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMfubjz)}(hintel_update_active_dpllh]j;)}(hintel_update_active_dpllh]hintel_update_active_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMfubj)}(hZ(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_update_active_dpllasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hstateh]hstate}(hj4hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubji)}(h h]h }(hjZhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmmodnameN classnameNjXj[)}j^]jc.intel_update_active_dpllasbuh1hhjIubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj;)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_encoder *encoderh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_encoderh]h intel_encoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_update_active_dpllasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hencoderh]hencoder}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMfubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMfubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMfhjhhubj1)}(hhh]h)}(h)update the active DPLL for a CRTC/encoderh]h)update the active DPLL for a CRTC/encoder}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMfhj;hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMfubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjVjSjVjTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` atomic state ``struct intel_crtc *crtc`` the CRTC for which to update the active DPLL ``struct intel_encoder *encoder`` encoder determining the type of port DPLL **Description** Update the active DPLL for the given **crtc**/**encoder** in **crtc**'s atomic state, from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The DPLL selected will be based on the current mode of the encoder's port.h](h)}(h**Parameters**h]jb)}(hj`h]h Parameters}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj^ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMjhjZubjx)}(hhh](j})}(h2``struct intel_atomic_state *state`` atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hjh]h struct intel_atomic_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMghjyubj)}(hhh]h)}(h atomic stateh]h atomic state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMghjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjhMghjvubj})}(hI``struct intel_crtc *crtc`` the CRTC for which to update the active DPLL h](j)}(h``struct intel_crtc *crtc``h]j)}(hjh]hstruct intel_crtc *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhhjubj)}(hhh]h)}(h,the CRTC for which to update the active DPLLh]h,the CRTC for which to update the active DPLL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhhjvubj})}(hL``struct intel_encoder *encoder`` encoder determining the type of port DPLL h](j)}(h!``struct intel_encoder *encoder``h]j)}(hjh]hstruct intel_encoder *encoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMihjubj)}(hhh]h)}(h)encoder determining the type of port DPLLh]h)encoder determining the type of port DPLL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMihjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMihjvubeh}(h]h ]h"]h$]h&]uh1jwhjZubh)}(h**Description**h]jb)}(hj,h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj*ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMkhjZubh)}(hUpdate the active DPLL for the given **crtc**/**encoder** in **crtc**'s atomic state, from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The DPLL selected will be based on the current mode of the encoder's port.h](h%Update the active DPLL for the given }(hjBhhhNhNubjb)}(h**crtc**h]hcrtc}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjBubh/}(hjBhhhNhNubjb)}(h **encoder**h]hencoder}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjBubh in }(hjBhhhNhNubjb)}(h**crtc**h]hcrtc}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjBubh’s atomic state, from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The DPLL selected will be based on the current mode of the encoder’s port.}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMkhjZubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_dpll_get_freq (C function)c.intel_dpll_get_freqhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hint intel_dpll_get_freq (struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h]j2)}(hint intel_dpll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM}ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM}ubjz)}(hintel_dpll_get_freqh]j;)}(hintel_dpll_get_freqh]hintel_dpll_get_freq}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM}ubj)}(hu(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dpll_get_freqasbuh1hhjubji)}(h h]h }(hj"hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj=hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h#const struct intel_shared_dpll *pllh](j)}(hjR{h]hconst}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubji)}(h h]h }(hjchhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj)}(hjh]hstruct}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubji)}(h h]h }(hj~hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_dpll_get_freqasbuh1hhjRubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj;)}(hpllh]hpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h/const struct intel_dpll_hw_state *dpll_hw_stateh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_dpll_get_freqasbuh1hhjubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h dpll_hw_stateh]h dpll_hw_state}(hjShhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM}ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM}ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM}hjhhubj1)}(hhh]h)}(h%calculate the DPLL's output frequencyh]h'calculate the DPLL’s output frequency}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM}hjzhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM}ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXy**Parameters** ``struct intel_display *display`` intel_display device ``const struct intel_shared_dpll *pll`` DPLL for which to calculate the output frequency ``const struct intel_dpll_hw_state *dpll_hw_state`` DPLL state from which to calculate the output frequency **Description** Return the output frequency corresponding to **pll**'s passed in **dpll_hw_state**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(h7``struct intel_display *display`` intel_display device h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chM~hjubj)}(hhh]h)}(hintel_display deviceh]hintel_display device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM~hjubj})}(hY``const struct intel_shared_dpll *pll`` DPLL for which to calculate the output frequency h](j)}(h'``const struct intel_shared_dpll *pll``h]j)}(hjh]h#const struct intel_shared_dpll *pll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h0DPLL for which to calculate the output frequencyh]h0DPLL for which to calculate the output frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hMhjubj})}(hl``const struct intel_dpll_hw_state *dpll_hw_state`` DPLL state from which to calculate the output frequency h](j)}(h3``const struct intel_dpll_hw_state *dpll_hw_state``h]j)}(hj0h]h/const struct intel_dpll_hw_state *dpll_hw_state}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj*ubj)}(hhh]h)}(h7DPLL state from which to calculate the output frequencyh]h7DPLL state from which to calculate the output frequency}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1j|hjEhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjkh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjiubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(hSReturn the output frequency corresponding to **pll**'s passed in **dpll_hw_state**.h](h-Return the output frequency corresponding to }(hjhhhNhNubjb)}(h**pll**h]hpll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh’s passed in }(hjhhhNhNubjb)}(h**dpll_hw_state**h]h dpll_hw_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_dpll_get_hw_state (C function)c.intel_dpll_get_hw_statehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hbool intel_dpll_get_hw_state (struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h]j2)}(hbool intel_dpll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_dpll_get_hw_stateh]j;)}(hintel_dpll_get_hw_stateh]hintel_dpll_get_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(hi(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj0modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dpll_get_hw_stateasbuh1hhj ubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hdisplayh]hdisplay}(hjihhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct intel_shared_dpll *pllh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~ubh)}(hhh]j;)}(hintel_shared_dpllh]hintel_shared_dpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jJc.intel_dpll_get_hw_stateasbuh1hhj~ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj;)}(hpllh]hpll}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj~ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h)struct intel_dpll_hw_state *dpll_hw_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jJc.intel_dpll_get_hw_stateasbuh1hhjubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h dpll_hw_stateh]h dpll_hw_state}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h!readout the DPLL's hardware stateh]h#readout the DPLL’s hardware state}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjphhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX:**Parameters** ``struct intel_display *display`` intel_display device instance ``struct intel_shared_dpll *pll`` DPLL for which to calculate the output frequency ``struct intel_dpll_hw_state *dpll_hw_state`` DPLL's hardware state **Description** Read out **pll**'s hardware state into **dpll_hw_state**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(h@``struct intel_display *display`` intel_display device instance h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(hintel_display device instanceh]hintel_display device instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hS``struct intel_shared_dpll *pll`` DPLL for which to calculate the output frequency h](j)}(h!``struct intel_shared_dpll *pll``h]j)}(hjh]hstruct intel_shared_dpll *pll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(h0DPLL for which to calculate the output frequencyh]h0DPLL for which to calculate the output frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hD``struct intel_dpll_hw_state *dpll_hw_state`` DPLL's hardware state h](j)}(h-``struct intel_dpll_hw_state *dpll_hw_state``h]j)}(hj&h]h)struct intel_dpll_hw_state *dpll_hw_state}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj ubj)}(hhh]h)}(hDPLL's hardware stateh]hDPLL’s hardware state}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj;hMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjah]h Description}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jahj_ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(h9Read out **pll**'s hardware state into **dpll_hw_state**.h](h Read out }(hjwhhhNhNubjb)}(h**pll**h]hpll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjwubh’s hardware state into }(hjwhhhNhNubjb)}(h**dpll_hw_state**h]h dpll_hw_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjwubh.}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_dpll_dump_hw_state (C function)c.intel_dpll_dump_hw_statehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hvoid intel_dpll_dump_hw_state (struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h]j2)}(hvoid intel_dpll_dump_hw_state(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_dpll_dump_hw_stateh]j;)}(hintel_dpll_dump_hw_stateh]hintel_dpll_dump_hw_state}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(hg(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj'modnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_dpll_dump_hw_stateasbuh1hhjubji)}(h h]h }(hjEhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdisplayh]hdisplay}(hj`hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_printer *ph](j)}(hjh]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuubh)}(hhh]j;)}(h drm_printerh]h drm_printer}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jAc.intel_dpll_dump_hw_stateasbuh1hhjuubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubj;)}(hjh]hp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjuubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h/const struct intel_dpll_hw_state *dpll_hw_stateh](j)}(hjR{h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hj!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj#modnameN classnameNjXj[)}j^]jAc.intel_dpll_dump_hw_stateasbuh1hhjubji)}(h h]h }(hj?hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(h dpll_hw_stateh]h dpll_hw_state}(hjZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h dump hw_stateh]h dump hw_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_display *display`` intel_display structure ``struct drm_printer *p`` where to print the state to ``const struct intel_dpll_hw_state *dpll_hw_state`` hw state to be dumped **Description** Dumo out the relevant values in **dpll_hw_state**.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubjx)}(hhh](j})}(h:``struct intel_display *display`` intel_display structure h](j)}(h!``struct intel_display *display``h]j)}(hjh]hstruct intel_display *display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(hintel_display structureh]hintel_display structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(h6``struct drm_printer *p`` where to print the state to h](j)}(h``struct drm_printer *p``h]j)}(hjh]hstruct drm_printer *p}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubj)}(hhh]h)}(hwhere to print the state toh]hwhere to print the state to}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hMhjubj})}(hJ``const struct intel_dpll_hw_state *dpll_hw_state`` hw state to be dumped h](j)}(h3``const struct intel_dpll_hw_state *dpll_hw_state``h]j)}(hj7 h]h/const struct intel_dpll_hw_state *dpll_hw_state}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5 ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj1 ubj)}(hhh]h)}(hhw state to be dumpedh]hhw state to be dumped}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjL hMhjM ubah}(h]h ]h"]h$]h&]uh1jhj1 ubeh}(h]h ]h"]h$]h&]uh1j|hjL hMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjr h]h Description}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjp ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubh)}(h2Dumo out the relevant values in **dpll_hw_state**.h](h Dumo out the relevant values in }(hj hhhNhNubjb)}(h**dpll_hw_state**h]h dpll_hw_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"(intel_dpll_compare_hw_state (C function)c.intel_dpll_compare_hw_statehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hbool intel_dpll_compare_hw_state (struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h]j2)}(hbool intel_dpll_compare_hw_state(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h](j)}(hjh]hbool}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj hhhj hMubjz)}(hintel_dpll_compare_hw_stateh]j;)}(hintel_dpll_compare_hw_stateh]hintel_dpll_compare_hw_state}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj hhhj hMubj)}(hi(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)h](j)}(hstruct intel_display *displayh](j)}(hjh]hstruct}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubji)}(h h]h }(hj!hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj!ubh)}(hhh]j;)}(h intel_displayh]h intel_display}(hj#!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj !ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj%!modnameN classnameNjXj[)}j^]ja)}jTj sbc.intel_dpll_compare_hw_stateasbuh1hhj!ubji)}(h h]h }(hjC!hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj!ubj)}(hjh]h*}(hjQ!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj;)}(hdisplayh]hdisplay}(hj^!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj!ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(h#const struct intel_dpll_hw_state *ah](j)}(hjR{h]hconst}(hjw!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs!ubji)}(h h]h }(hj!hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjs!ubj)}(hjh]hstruct}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs!ubji)}(h h]h }(hj!hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjs!ubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hj!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj!ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj!modnameN classnameNjXj[)}j^]j?!c.intel_dpll_compare_hw_stateasbuh1hhjs!ubji)}(h h]h }(hj!hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjs!ubj)}(hjh]h*}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs!ubj;)}(hjh]ha}(hj!hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjs!ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(h#const struct intel_dpll_hw_state *bh](j)}(hjR{h]hconst}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubji)}(h h]h }(hj"hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj!ubj)}(hjh]hstruct}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubji)}(h h]h }(hj)"hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj!ubh)}(hhh]j;)}(hintel_dpll_hw_stateh]hintel_dpll_hw_state}(hj:"hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7"ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj<"modnameN classnameNjXj[)}j^]j?!c.intel_dpll_compare_hw_stateasbuh1hhj!ubji)}(h h]h }(hjX"hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj!ubj)}(hjh]h*}(hjf"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj;)}(hjh]hb}(hjs"hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj!ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubeh}(h]h ]h"]h$]h&]jjuh1jhj hhhj hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj hhhj hMubah}(h]j ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj hMhj hhubj1)}(hhh]h)}(hcompare the two statesh]hcompare the two states}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj"hhubah}(h]h ]h"]h$]h&]uh1j0hj hhhj hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj"jSj"jTjUjVuh1j&hhhjhNhNubjX)}(hXC**Parameters** ``struct intel_display *display`` intel_display structure ``const struct intel_dpll_hw_state *a`` first DPLL hw state ``const struct intel_dpll_hw_state *b`` second DPLL hw state **Description** Compare DPLL hw states **a** and **b**. **Return** true if the states are equal, false if the differh](h)}(h**Parameters**h]jb)}(hj"h]h Parameters}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj"ubjx)}(hhh](j})}(h:``struct intel_display *display`` intel_display structure h](j)}(h!``struct intel_display *display``h]j)}(hj"h]hstruct intel_display *display}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj"ubj)}(hhh]h)}(hintel_display structureh]hintel_display structure}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj"hMhj"ubj})}(h<``const struct intel_dpll_hw_state *a`` first DPLL hw state h](j)}(h'``const struct intel_dpll_hw_state *a``h]j)}(hj#h]h#const struct intel_dpll_hw_state *a}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj#ubj)}(hhh]h)}(hfirst DPLL hw stateh]hfirst DPLL hw state}(hj/#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+#hMhj,#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1j|hj+#hMhj"ubj})}(h=``const struct intel_dpll_hw_state *b`` second DPLL hw state h](j)}(h'``const struct intel_dpll_hw_state *b``h]j)}(hjO#h]h#const struct intel_dpll_hw_state *b}(hjQ#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM#ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhjI#ubj)}(hhh]h)}(hsecond DPLL hw stateh]hsecond DPLL hw state}(hjh#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjd#hMhje#ubah}(h]h ]h"]h$]h&]uh1jhjI#ubeh}(h]h ]h"]h$]h&]uh1j|hjd#hMhj"ubeh}(h]h ]h"]h$]h&]uh1jwhj"ubh)}(h**Description**h]jb)}(hj#h]h Description}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj"ubh)}(h'Compare DPLL hw states **a** and **b**.h](hCompare DPLL hw states }(hj#hhhNhNubjb)}(h**a**h]ha}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubh and }(hj#hhhNhNubjb)}(h**b**h]hb}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubh.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj"ubh)}(h **Return**h]jb)}(hj#h]hReturn}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj"ubh)}(h1true if the states are equal, false if the differh]h1true if the states are equal, false if the differ}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:240: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.chMhj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dpll_id (C enum)c.intel_dpll_idhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h intel_dpll_idh]j2)}(henum intel_dpll_idh](j)}(hjh]henum}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhKubji)}(h h]h }(hj($hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$hhhj'$hKubjz)}(h intel_dpll_idh]j;)}(hj$h]h intel_dpll_id}(hj:$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj6$ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj$hhhj'$hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj$hhhj'$hKubah}(h]j $ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj'$hKhj$hhubj1)}(hhh]h)}(hpossible DPLL idsh]hpossible DPLL ids}(hj\$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK/hjY$hhubah}(h]h ]h"]h$]h&]uh1j0hj$hhhj'$hKubeh}(h]h ](jRenumeh"]h$]h&]jQjRjRjt$jSjt$jTjUjVuh1j&hhhjhNhNubjX)}(hX**Constants** ``DPLL_ID_PRIVATE`` non-shared dpll in use ``DPLL_ID_PCH_PLL_A`` DPLL A in ILK, SNB and IVB ``DPLL_ID_PCH_PLL_B`` DPLL B in ILK, SNB and IVB ``DPLL_ID_WRPLL1`` HSW and BDW WRPLL1 ``DPLL_ID_WRPLL2`` HSW and BDW WRPLL2 ``DPLL_ID_SPLL`` HSW and BDW SPLL ``DPLL_ID_LCPLL_810`` HSW and BDW 0.81 GHz LCPLL ``DPLL_ID_LCPLL_1350`` HSW and BDW 1.35 GHz LCPLL ``DPLL_ID_LCPLL_2700`` HSW and BDW 2.7 GHz LCPLL ``DPLL_ID_SKL_DPLL0`` SKL and later DPLL0 ``DPLL_ID_SKL_DPLL1`` SKL and later DPLL1 ``DPLL_ID_SKL_DPLL2`` SKL and later DPLL2 ``DPLL_ID_SKL_DPLL3`` SKL and later DPLL3 ``DPLL_ID_ICL_DPLL0`` ICL/TGL combo PHY DPLL0 ``DPLL_ID_ICL_DPLL1`` ICL/TGL combo PHY DPLL1 ``DPLL_ID_EHL_DPLL4`` EHL combo PHY DPLL4 ``DPLL_ID_ICL_TBTPLL`` ICL/TGL TBT PLL ``DPLL_ID_ICL_MGPLL1`` ICL MG PLL 1 port 1 (C), TGL TC PLL 1 port 1 (TC1) ``DPLL_ID_ICL_MGPLL2`` ICL MG PLL 1 port 2 (D) TGL TC PLL 1 port 2 (TC2) ``DPLL_ID_ICL_MGPLL3`` ICL MG PLL 1 port 3 (E) TGL TC PLL 1 port 3 (TC3) ``DPLL_ID_ICL_MGPLL4`` ICL MG PLL 1 port 4 (F) TGL TC PLL 1 port 4 (TC4) ``DPLL_ID_TGL_MGPLL5`` TGL TC PLL port 5 (TC5) ``DPLL_ID_TGL_MGPLL6`` TGL TC PLL port 6 (TC6) ``DPLL_ID_DG1_DPLL0`` DG1 combo PHY DPLL0 ``DPLL_ID_DG1_DPLL1`` DG1 combo PHY DPLL1 ``DPLL_ID_DG1_DPLL2`` DG1 combo PHY DPLL2 ``DPLL_ID_DG1_DPLL3`` DG1 combo PHY DPLL3h](h)}(h **Constants**h]jb)}(hj~$h]h Constants}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj|$ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK3hjx$ubjx)}(hhh](j})}(h+``DPLL_ID_PRIVATE`` non-shared dpll in use h](j)}(h``DPLL_ID_PRIVATE``h]j)}(hj$h]hDPLL_ID_PRIVATE}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK6hj$ubj)}(hhh]h)}(hnon-shared dpll in useh]hnon-shared dpll in use}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hK6hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1j|hj$hK6hj$ubj})}(h1``DPLL_ID_PCH_PLL_A`` DPLL A in ILK, SNB and IVB h](j)}(h``DPLL_ID_PCH_PLL_A``h]j)}(hj$h]hDPLL_ID_PCH_PLL_A}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK9hj$ubj)}(hhh]h)}(hDPLL A in ILK, SNB and IVBh]hDPLL A in ILK, SNB and IVB}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hK9hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1j|hj$hK9hj$ubj})}(h1``DPLL_ID_PCH_PLL_B`` DPLL B in ILK, SNB and IVB h](j)}(h``DPLL_ID_PCH_PLL_B``h]j)}(hj%h]hDPLL_ID_PCH_PLL_B}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj %ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK= 0.h]hJEnumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.}(hjh+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK0hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_shared_dpll_state (C struct)c.intel_shared_dpll_statehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hintel_shared_dpll_stateh]j2)}(hstruct intel_shared_dpll_stateh](j)}(hjh]hstruct}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhK5ubji)}(h h]h }(hj+hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+hhhj+hK5ubjz)}(hintel_shared_dpll_stateh]j;)}(hj+h]hintel_shared_dpll_state}(hj+hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj+ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj+hhhj+hK5ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj+hhhj+hK5ubah}(h]j+ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj+hK5hj+hhubj1)}(hhh]h)}(hhold the DPLL atomic stateh]hhold the DPLL atomic state}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhj+hhubah}(h]h ]h"]h$]h&]uh1j0hj+hhhj+hK5ubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRj+jSj+jTjUjVuh1j&hhhjhNhNubjX)}(hX)**Definition**:: struct intel_shared_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; }; **Members** ``pipe_mask`` mask of pipes using this DPLL, active or not ``hw_state`` hardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj+ubh:}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhj+ubj")}(h^struct intel_shared_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; };h]h^struct intel_shared_dpll_state { u8 pipe_mask; struct intel_dpll_hw_state hw_state; };}hj,sbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM!hj+ubh)}(h **Members**h]jb)}(hj ,h]hMembers}(hj",hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM&hj+ubjx)}(hhh](j})}(h;``pipe_mask`` mask of pipes using this DPLL, active or not h](j)}(h ``pipe_mask``h]j)}(hj?,h]h pipe_mask}(hjA,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=,ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM'hj9,ubj)}(hhh]h)}(h,mask of pipes using this DPLL, active or noth]h,mask of pipes using this DPLL, active or not}(hjX,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT,hM'hjU,ubah}(h]h ]h"]h$]h&]uh1jhj9,ubeh}(h]h ]h"]h$]h&]uh1j|hjT,hM'hj6,ubj})}(h```hw_state`` hardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](j)}(h ``hw_state``h]j)}(hjx,h]hhw_state}(hjz,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjv,ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM,hjr,ubj)}(hhh]h)}(hShardware configuration for the DPLL stored in struct :c:type:`intel_dpll_hw_state`.h](h5hardware configuration for the DPLL stored in struct }(hj,hhhNhNubh)}(h:c:type:`intel_dpll_hw_state`h]j)}(hj,h]hintel_dpll_hw_state}(hj,hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjintel_dpll_hw_stateuh1hhj,hM,hj,ubh.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj,hM,hj,ubah}(h]h ]h"]h$]h&]uh1jhjr,ubeh}(h]h ]h"]h$]h&]uh1j|hj,hM,hj6,ubeh}(h]h ]h"]h$]h&]uh1jwhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubh)}(h**Description**h]jb)}(hj,h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM0hjhhubh)}(hXThis structure holds an atomic state for the DPLL, that can represent either its current state (in struct :c:type:`intel_shared_dpll`) or a desired future state which would be applied by an atomic mode set (stored in a struct :c:type:`intel_atomic_state`).h](hjThis structure holds an atomic state for the DPLL, that can represent either its current state (in struct }(hj,hhhNhNubh)}(h:c:type:`intel_shared_dpll`h]j)}(hj,h]hintel_shared_dpll}(hj,hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjintel_shared_dplluh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhj,ubh]) or a desired future state which would be applied by an atomic mode set (stored in a struct }(hj,hhhNhNubh)}(h:c:type:`intel_atomic_state`h]j)}(hj!-h]hintel_atomic_state}(hj#-hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjintel_atomic_stateuh1hhj-hMhj,ubh).}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj-hMhjhhubh)}(hGSee also intel_reserve_shared_dplls() and intel_release_shared_dplls().h]hGSee also intel_reserve_shared_dplls() and intel_release_shared_dplls().}(hjH-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM!hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"dpll_info (C struct) c.dpll_infohNtauh1jhjhhhNhNubj')}(hhh](j,)}(h dpll_infoh]j2)}(hstruct dpll_infoh](j)}(hjh]hstruct}(hjp-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl-hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM&ubji)}(h h]h }(hj~-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjl-hhhj}-hM&ubjz)}(h dpll_infoh]j;)}(hjj-h]h dpll_info}(hj-hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj-ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjl-hhhj}-hM&ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjh-hhhj}-hM&ubah}(h]jc-ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj}-hM&hje-hhubj1)}(hhh]h)}(h"display PLL platform specific infoh]h"display PLL platform specific info}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM2hj-hhubah}(h]h ]h"]h$]h&]uh1j0hje-hhhj}-hM&ubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRj-jSj-jTjUjVuh1j&hhhjhNhNubjX)}(hX**Definition**:: struct dpll_info { const char *name; const struct intel_shared_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; }; **Members** ``name`` DPLL name; used for logging ``funcs`` platform specific hooks ``id`` unique identifier for this DPLL ``power_domain`` extra power domain required by the DPLL ``always_on`` Inform the state checker that the DPLL is kept enabled even if not in use by any CRTC. ``is_alt_port_dpll`` Inform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-ubh:}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM6hj-ubj")}(hstruct dpll_info { const char *name; const struct intel_shared_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; };h]hstruct dpll_info { const char *name; const struct intel_shared_dpll_funcs *funcs; enum intel_dpll_id id; enum intel_display_power_domain power_domain; bool always_on; bool is_alt_port_dpll; };}hj-sbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM8hj-ubh)}(h **Members**h]jb)}(hj.h]hMembers}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMAhj-ubjx)}(hhh](j})}(h%``name`` DPLL name; used for logging h](j)}(h``name``h]j)}(hj.h]hname}(hj!.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM7hj.ubj)}(hhh]h)}(hDPLL name; used for loggingh]hDPLL name; used for logging}(hj8.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4.hM7hj5.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hj4.hM7hj.ubj})}(h"``funcs`` platform specific hooks h](j)}(h ``funcs``h]j)}(hjX.h]hfuncs}(hjZ.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjV.ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM<hjR.ubj)}(hhh]h)}(hplatform specific hooksh]hplatform specific hooks}(hjq.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjm.hM<hjn.ubah}(h]h ]h"]h$]h&]uh1jhjR.ubeh}(h]h ]h"]h$]h&]uh1j|hjm.hM<hj.ubj})}(h'``id`` unique identifier for this DPLL h](j)}(h``id``h]j)}(hj.h]hid}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMAhj.ubj)}(hhh]h)}(hunique identifier for this DPLLh]hunique identifier for this DPLL}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMAhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hj.hMAhj.ubj})}(h9``power_domain`` extra power domain required by the DPLL h](j)}(h``power_domain``h]j)}(hj.h]h power_domain}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMFhj.ubj)}(hhh]h)}(h'extra power domain required by the DPLLh]h'extra power domain required by the DPLL}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMFhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hj.hMFhj.ubj})}(he``always_on`` Inform the state checker that the DPLL is kept enabled even if not in use by any CRTC. h](j)}(h ``always_on``h]j)}(hj/h]h always_on}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMLhj.ubj)}(hhh]h)}(hVInform the state checker that the DPLL is kept enabled even if not in use by any CRTC.h]hVInform the state checker that the DPLL is kept enabled even if not in use by any CRTC.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMKhj/ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hj/hMLhj.ubj})}(hm``is_alt_port_dpll`` Inform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h](j)}(h``is_alt_port_dpll``h]j)}(hj=/h]his_alt_port_dpll}(hj?/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;/ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMShj7/ubj)}(hhh]h)}(hXInform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).h]hXInform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).}(hjV/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR/hMShjS/ubah}(h]h ]h"]h$]h&]uh1jhj7/ubeh}(h]h ]h"]h$]h&]uh1j|hjR/hMShj.ubeh}(h]h ]h"]h$]h&]uh1jwhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_shared_dpll (C struct)c.intel_shared_dpllhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hintel_shared_dpllh]j2)}(hstruct intel_shared_dpllh](j)}(hjh]hstruct}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/hhhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMZubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/hhhj/hMZubjz)}(hintel_shared_dpllh]j;)}(hj/h]hintel_shared_dpll}(hj/hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj/hhhj/hMZubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj/hhhj/hMZubah}(h]j/ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj/hMZhj/hhubj1)}(hhh]h)}(h(display PLL with tracked state and usersh]h(display PLL with tracked state and users}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM[hj/hhubah}(h]h ]h"]h$]h&]uh1j0hj/hhhj/hMZubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRj/jSj/jTjUjVuh1j&hhhjhNhNubjX)}(hX**Definition**:: struct intel_shared_dpll { struct intel_shared_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; intel_wakeref_t wakeref; }; **Members** ``state`` Store the state for the pll, including its hw state and CRTCs using it. ``index`` index for atomic state ``active_mask`` mask of active pipes (i.e. DPMS on) using this DPLL ``on`` is the PLL actually active? Disabled during modeset ``info`` platform specific info ``wakeref`` In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabledh](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj/ubh:}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM_hj/ubj")}(hstruct intel_shared_dpll { struct intel_shared_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; intel_wakeref_t wakeref; };h]hstruct intel_shared_dpll { struct intel_shared_dpll_state state; u8 index; u8 active_mask; bool on; const struct dpll_info *info; intel_wakeref_t wakeref; };}hj0sbah}(h]h ]h"]h$]h&]jjuh1j"hg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMahj/ubh)}(h **Members**h]jb)}(hj&0h]hMembers}(hj(0hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj$0ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMjhj/ubjx)}(hhh](j})}(hR``state`` Store the state for the pll, including its hw state and CRTCs using it. h](j)}(h ``state``h]j)}(hjE0h]hstate}(hjG0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC0ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMahj?0ubj)}(hhh]h)}(hGStore the state for the pll, including its hw state and CRTCs using it.h]hGStore the state for the pll, including its hw state and CRTCs using it.}(hj^0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM`hj[0ubah}(h]h ]h"]h$]h&]uh1jhj?0ubeh}(h]h ]h"]h$]h&]uh1j|hjZ0hMahj<0ubj})}(h!``index`` index for atomic state h](j)}(h ``index``h]j)}(hj0h]hindex}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}0ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMhhjy0ubj)}(hhh]h)}(hindex for atomic stateh]hindex for atomic state}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhhj0ubah}(h]h ]h"]h$]h&]uh1jhjy0ubeh}(h]h ]h"]h$]h&]uh1j|hj0hMhhj<0ubj})}(hD``active_mask`` mask of active pipes (i.e. DPMS on) using this DPLL h](j)}(h``active_mask``h]j)}(hj0h]h active_mask}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMmhj0ubj)}(hhh]h)}(h3mask of active pipes (i.e. DPMS on) using this DPLLh]h3mask of active pipes (i.e. DPMS on) using this DPLL}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMmhj0ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1j|hj0hMmhj<0ubj})}(h;``on`` is the PLL actually active? Disabled during modeset h](j)}(h``on``h]j)}(hj0h]hon}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMrhj0ubj)}(hhh]h)}(h3is the PLL actually active? Disabled during modeseth]h3is the PLL actually active? Disabled during modeset}(hj 1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMrhj1ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1j|hj1hMrhj<0ubj})}(h ``info`` platform specific info h](j)}(h``info``h]j)}(hj*1h]hinfo}(hj,1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(1ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhMwhj$1ubj)}(hhh]h)}(hplatform specific infoh]hplatform specific info}(hjC1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?1hMwhj@1ubah}(h]h ]h"]h$]h&]uh1jhj$1ubeh}(h]h ]h"]h$]h&]uh1j|hj?1hMwhj<0ubj})}(h``wakeref`` In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabledh](j)}(h ``wakeref``h]j)}(hjc1h]hwakeref}(hje1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja1ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:243: ./drivers/gpu/drm/i915/display/intel_dpll_mgr.hhM|hj]1ubj)}(hhh]h)}(h|In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabledh]h|In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabled}(hj|1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx1hM|hjy1ubah}(h]h ]h"]h$]h&]uh1jhj]1ubeh}(h]h ]h"]h$]h&]uh1j|hjx1hM|hj<0ubeh}(h]h ]h"]h$]h&]uh1jwhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h] display-pllsah ]h"] display pllsah$]h&]uh1hhj;hhhhhKubh)}(hhh](h)}(hDisplay State Bufferh]hDisplay State Buffer}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hhhhhKubh)}(hXA DSB (Display State Buffer) is a queue of MMIO instructions in the memory which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA engine that can be programmed to download the DSB from memory. It allows driver to batch submit display HW programming. This helps to reduce loading time and CPU activity, thereby making the context switch faster. DSB Support added from Gen12 Intel graphics based platform.h]hXA DSB (Display State Buffer) is a queue of MMIO instructions in the memory which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA engine that can be programmed to download the DSB from memory. It allows driver to batch submit display HW programming. This helps to reduce loading time and CPU activity, thereby making the context switch faster. DSB Support added from Gen12 Intel graphics based platform.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/display/intel_dsb.chK>hj1hhubh)}(hSDSB's can access only the pipe, plane, and transcoder Data Island Packet registers.h]hUDSB’s can access only the pipe, plane, and transcoder Data Island Packet registers.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/display/intel_dsb.chKEhj1hhubh)}(hDSB HW can support only register writes (both indexed and direct MMIO writes). There are no registers reads possible with DSB HW engine.h]hDSB HW can support only register writes (both indexed and direct MMIO writes). There are no registers reads possible with DSB HW engine.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:249: ./drivers/gpu/drm/i915/display/intel_dsb.chKHhj1hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"(intel_dsb_reg_write_indexed (C function)c.intel_dsb_reg_write_indexedhNtauh1jhj1hhhNhNubj')}(hhh](j,)}(hQvoid intel_dsb_reg_write_indexed (struct intel_dsb *dsb, i915_reg_t reg, u32 val)h]j2)}(hPvoid intel_dsb_reg_write_indexed(struct intel_dsb *dsb, i915_reg_t reg, u32 val)h](j)}(hvoidh]hvoid}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj1hhhj2hMubjz)}(hintel_dsb_reg_write_indexedh]j;)}(hintel_dsb_reg_write_indexedh]hintel_dsb_reg_write_indexed}(hj#2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj1hhhj2hMubj)}(h0(struct intel_dsb *dsb, i915_reg_t reg, u32 val)h](j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hj?2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;2ubji)}(h h]h }(hjL2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj;2ubh)}(hhh]j;)}(h intel_dsbh]h intel_dsb}(hj]2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjZ2ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj_2modnameN classnameNjXj[)}j^]ja)}jTj%2sbc.intel_dsb_reg_write_indexedasbuh1hhj;2ubji)}(h h]h }(hj}2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj;2ubj)}(hjh]h*}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;2ubj;)}(hdsbh]hdsb}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;2ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj72ubj)}(hi915_reg_t regh](h)}(hhh]j;)}(h i915_reg_th]h i915_reg_t}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj2modnameN classnameNjXj[)}j^]jy2c.intel_dsb_reg_write_indexedasbuh1hhj2ubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2ubj;)}(hregh]hreg}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj72ubj)}(hu32 valh](h)}(hhh]j;)}(hu32h]hu32}(hj2hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj2modnameN classnameNjXj[)}j^]jy2c.intel_dsb_reg_write_indexedasbuh1hhj2ubji)}(h h]h }(hj3hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj2ubj;)}(hvalh]hval}(hj(3hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj2ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj72ubeh}(h]h ]h"]h$]h&]jjuh1jhj1hhhj2hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj1hhhj2hMubah}(h]j1ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj2hMhj1hhubj1)}(hhh]h)}(h.Emit indexed register write to the DSB contexth]h.Emit indexed register write to the DSB context}(hjR3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjO3hhubah}(h]h ]h"]h$]h&]uh1j0hj1hhhj2hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjj3jSjj3jTjUjVuh1j&hhhj1hNhNubjX)}(hX[**Parameters** ``struct intel_dsb *dsb`` DSB context ``i915_reg_t reg`` register address. ``u32 val`` value. **Description** This function is used for writing register-value pair in command buffer of DSB. Note that indexed writes are slower than normal MMIO writes for a small number (less than 5 or so) of writes to the same register.h](h)}(h**Parameters**h]jb)}(hjt3h]h Parameters}(hjv3hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjr3ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjn3ubjx)}(hhh](j})}(h&``struct intel_dsb *dsb`` DSB context h](j)}(h``struct intel_dsb *dsb``h]j)}(hj3h]hstruct intel_dsb *dsb}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj3ubj)}(hhh]h)}(h DSB contexth]h DSB context}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j|hj3hMhj3ubj})}(h%``i915_reg_t reg`` register address. h](j)}(h``i915_reg_t reg``h]j)}(hj3h]hi915_reg_t reg}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj3ubj)}(hhh]h)}(hregister address.h]hregister address.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j|hj3hMhj3ubj})}(h``u32 val`` value. h](j)}(h ``u32 val``h]j)}(hj4h]hu32 val}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj3ubj)}(hhh]h)}(hvalue.h]hvalue.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j|hj4hMhj3ubeh}(h]h ]h"]h$]h&]uh1jwhjn3ubh)}(h**Description**h]jb)}(hj@4h]h Description}(hjB4hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj>4ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjn3ubh)}(hOThis function is used for writing register-value pair in command buffer of DSB.h]hOThis function is used for writing register-value pair in command buffer of DSB.}(hjV4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjn3ubh)}(hNote that indexed writes are slower than normal MMIO writes for a small number (less than 5 or so) of writes to the same register.h]hNote that indexed writes are slower than normal MMIO writes for a small number (less than 5 or so) of writes to the same register.}(hje4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjn3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj1hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dsb_commit (C function)c.intel_dsb_commithNtauh1jhj1hhhNhNubj')}(hhh](j,)}(hCvoid intel_dsb_commit (struct intel_dsb *dsb, bool wait_for_vblank)h]j2)}(hBvoid intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)h](j)}(hvoidh]hvoid}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMubji)}(h h]h }(hj4hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj4hhhj4hMubjz)}(hintel_dsb_commith]j;)}(hintel_dsb_commith]hintel_dsb_commit}(hj4hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj4ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj4hhhj4hMubj)}(h-(struct intel_dsb *dsb, bool wait_for_vblank)h](j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubji)}(h h]h }(hj4hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj4ubh)}(hhh]j;)}(h intel_dsbh]h intel_dsb}(hj4hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj4ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj4modnameN classnameNjXj[)}j^]ja)}jTj4sbc.intel_dsb_commitasbuh1hhj4ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj4ubj)}(hjh]h*}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj;)}(hdsbh]hdsb}(hj*5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj4ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj4ubj)}(hbool wait_for_vblankh](j)}(hjh]hbool}(hjC5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?5ubji)}(h h]h }(hjP5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?5ubj;)}(hwait_for_vblankh]hwait_for_vblank}(hj^5hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj?5ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj4ubeh}(h]h ]h"]h$]h&]jjuh1jhj4hhhj4hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj4hhhj4hMubah}(h]j4ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj4hMhj4hhubj1)}(hhh]h)}(h"Trigger workload execution of DSB.h]h"Trigger workload execution of DSB.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj5hhubah}(h]h ]h"]h$]h&]uh1j0hj4hhhj4hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj5jSj5jTjUjVuh1j&hhhj1hNhNubjX)}(h**Parameters** ``struct intel_dsb *dsb`` DSB context ``bool wait_for_vblank`` wait for vblank before executing **Description** This function is used to do actual write to hardware using DSB.h](h)}(h**Parameters**h]jb)}(hj5h]h Parameters}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj5ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj5ubjx)}(hhh](j})}(h&``struct intel_dsb *dsb`` DSB context h](j)}(h``struct intel_dsb *dsb``h]j)}(hj5h]hstruct intel_dsb *dsb}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj5ubj)}(hhh]h)}(h DSB contexth]h DSB context}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1j|hj5hMhj5ubj})}(h:``bool wait_for_vblank`` wait for vblank before executing h](j)}(h``bool wait_for_vblank``h]j)}(hj6h]hbool wait_for_vblank}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj5ubj)}(hhh]h)}(h wait for vblank before executingh]h wait for vblank before executing}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1j|hj6hMhj5ubeh}(h]h ]h"]h$]h&]uh1jwhj5ubh)}(h**Description**h]jb)}(hj=6h]h Description}(hj?6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj;6ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj5ubh)}(h?This function is used to do actual write to hardware using DSB.h]h?This function is used to do actual write to hardware using DSB.}(hjS6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj1hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dsb_prepare (C function)c.intel_dsb_preparehNtauh1jhj1hhhNhNubj')}(hhh](j,)}(hstruct intel_dsb * intel_dsb_prepare (struct intel_atomic_state *state, struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds)h]j2)}(hstruct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds)h](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~6hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMubji)}(h h]h }(hj6hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~6hhhj6hMubh)}(hhh]j;)}(h intel_dsbh]h intel_dsb}(hj6hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj6ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj6modnameN classnameNjXj[)}j^]ja)}jTintel_dsb_preparesbc.intel_dsb_prepareasbuh1hhj~6hhhj6hMubji)}(h h]h }(hj6hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj~6hhhj6hMubj)}(hjh]h*}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~6hhhj6hMubjz)}(hintel_dsb_prepareh]j;)}(hj6h]hintel_dsb_prepare}(hj6hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj6ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj~6hhhj6hMubj)}(hl(struct intel_atomic_state *state, struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds)h](j)}(h struct intel_atomic_state *stateh](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubji)}(h h]h }(hj 7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj6ubh)}(hhh]j;)}(hintel_atomic_stateh]hintel_atomic_state}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj7modnameN classnameNjXj[)}j^]j6c.intel_dsb_prepareasbuh1hhj6ubji)}(h h]h }(hj87hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj6ubj)}(hjh]h*}(hjF7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj;)}(hstateh]hstate}(hjS7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj6ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj6ubj)}(hstruct intel_crtc *crtch](j)}(hjh]hstruct}(hjl7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjh7ubji)}(h h]h }(hjy7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjh7ubh)}(hhh]j;)}(h intel_crtch]h intel_crtc}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj7modnameN classnameNjXj[)}j^]j6c.intel_dsb_prepareasbuh1hhjh7ubji)}(h h]h }(hj7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjh7ubj)}(hjh]h*}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjh7ubj;)}(hcrtch]hcrtc}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjh7ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj6ubj)}(henum intel_dsb_id dsb_idh](j)}(hjh]henum}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubji)}(h h]h }(hj7hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj7ubh)}(hhh]j;)}(h intel_dsb_idh]h intel_dsb_id}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj7modnameN classnameNjXj[)}j^]j6c.intel_dsb_prepareasbuh1hhj7ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj7ubj;)}(hdsb_idh]hdsb_id}(hj&8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj6ubj)}(hunsigned int max_cmdsh](j)}(hunsignedh]hunsigned}(hj?8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;8ubji)}(h h]h }(hjM8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj;8ubj)}(hinth]hint}(hj[8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;8ubji)}(h h]h }(hji8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj;8ubj;)}(hmax_cmdsh]hmax_cmds}(hjw8hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;8ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj6ubeh}(h]h ]h"]h$]h&]jjuh1jhj~6hhhj6hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjz6hhhj6hMubah}(h]ju6ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj6hMhjw6hhubj1)}(hhh]h)}(h-Allocate, pin and map the DSB command buffer.h]h-Allocate, pin and map the DSB command buffer.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj8hhubah}(h]h ]h"]h$]h&]uh1j0hjw6hhhj6hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj8jSj8jTjUjVuh1j&hhhj1hNhNubjX)}(hX**Parameters** ``struct intel_atomic_state *state`` the atomic state ``struct intel_crtc *crtc`` the CRTC ``enum intel_dsb_id dsb_id`` the DSB engine to use ``unsigned int max_cmds`` number of commands we need to fit into command buffer **Description** This function prepare the command buffer which is used to store dsb instructions with data. **Return** DSB context, NULL on failureh](h)}(h**Parameters**h]jb)}(hj8h]h Parameters}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj8ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj8ubjx)}(hhh](j})}(h6``struct intel_atomic_state *state`` the atomic state h](j)}(h$``struct intel_atomic_state *state``h]j)}(hj8h]h struct intel_atomic_state *state}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj8ubj)}(hhh]h)}(hthe atomic stateh]hthe atomic state}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1j|hj8hMhj8ubj})}(h%``struct intel_crtc *crtc`` the CRTC h](j)}(h``struct intel_crtc *crtc``h]j)}(hj9h]hstruct intel_crtc *crtc}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj9ubj)}(hhh]h)}(hthe CRTCh]hthe CRTC}(hj49hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj09hMhj19ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j|hj09hMhj8ubj})}(h3``enum intel_dsb_id dsb_id`` the DSB engine to use h](j)}(h``enum intel_dsb_id dsb_id``h]j)}(hjT9h]henum intel_dsb_id dsb_id}(hjV9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR9ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhjN9ubj)}(hhh]h)}(hthe DSB engine to useh]hthe DSB engine to use}(hjm9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji9hMhjj9ubah}(h]h ]h"]h$]h&]uh1jhjN9ubeh}(h]h ]h"]h$]h&]uh1j|hji9hMhj8ubj})}(hP``unsigned int max_cmds`` number of commands we need to fit into command buffer h](j)}(h``unsigned int max_cmds``h]j)}(hj9h]hunsigned int max_cmds}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj9ubj)}(hhh]h)}(h5number of commands we need to fit into command bufferh]h5number of commands we need to fit into command buffer}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j|hj9hMhj8ubeh}(h]h ]h"]h$]h&]uh1jwhj8ubh)}(h**Description**h]jb)}(hj9h]h Description}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj9ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj8ubh)}(h[This function prepare the command buffer which is used to store dsb instructions with data.h]h[This function prepare the command buffer which is used to store dsb instructions with data.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj8ubh)}(h **Return**h]jb)}(hj9h]hReturn}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj9ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj8ubh)}(hDSB context, NULL on failureh]hDSB context, NULL on failure}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj1hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_dsb_cleanup (C function)c.intel_dsb_cleanuphNtauh1jhj1hhhNhNubj')}(hhh](j,)}(h.void intel_dsb_cleanup (struct intel_dsb *dsb)h]j2)}(h-void intel_dsb_cleanup(struct intel_dsb *dsb)h](j)}(hvoidh]hvoid}(hj4:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0:hhhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMOubji)}(h h]h }(hjC:hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj0:hhhjB:hMOubjz)}(hintel_dsb_cleanuph]j;)}(hintel_dsb_cleanuph]hintel_dsb_cleanup}(hjU:hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQ:ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj0:hhhjB:hMOubj)}(h(struct intel_dsb *dsb)h]j)}(hstruct intel_dsb *dsbh](j)}(hjh]hstruct}(hjq:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm:ubji)}(h h]h }(hj~:hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjm:ubh)}(hhh]j;)}(h intel_dsbh]h intel_dsb}(hj:hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj:ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj:modnameN classnameNjXj[)}j^]ja)}jTjW:sbc.intel_dsb_cleanupasbuh1hhjm:ubji)}(h h]h }(hj:hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjm:ubj)}(hjh]h*}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm:ubj;)}(hdsbh]hdsb}(hj:hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjm:ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhji:ubah}(h]h ]h"]h$]h&]jjuh1jhj0:hhhjB:hMOubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj,:hhhjB:hMOubah}(h]j':ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjB:hMOhj):hhubj1)}(hhh]h)}(hTo cleanup DSB context.h]hTo cleanup DSB context.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMOhj:hhubah}(h]h ]h"]h$]h&]uh1j0hj):hhhjB:hMOubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj ;jSj ;jTjUjVuh1j&hhhj1hNhNubjX)}(h**Parameters** ``struct intel_dsb *dsb`` DSB context **Description** This function cleanup the DSB context by unpinning and releasing the VMA object associated with it.h](h)}(h**Parameters**h]jb)}(hj;h]h Parameters}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj;ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMShj;ubjx)}(hhh]j})}(h&``struct intel_dsb *dsb`` DSB context h](j)}(h``struct intel_dsb *dsb``h]j)}(hj5;h]hstruct intel_dsb *dsb}(hj7;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3;ubah}(h]h ]h"]h$]h&]uh1jhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMPhj/;ubj)}(hhh]h)}(h DSB contexth]h DSB context}(hjN;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ;hMPhjK;ubah}(h]h ]h"]h$]h&]uh1jhj/;ubeh}(h]h ]h"]h$]h&]uh1j|hjJ;hMPhj,;ubah}(h]h ]h"]h$]h&]uh1jwhj;ubh)}(h**Description**h]jb)}(hjp;h]h Description}(hjr;hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjn;ubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMRhj;ubh)}(hcThis function cleanup the DSB context by unpinning and releasing the VMA object associated with it.h]hcThis function cleanup the DSB context by unpinning and releasing the VMA object associated with it.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhb/var/lib/git/docbuild/linux/Documentation/gpu/i915:252: ./drivers/gpu/drm/i915/display/intel_dsb.chMRhj;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj1hhhNhNubeh}(h]display-state-bufferah ]h"]display state bufferah$]h&]uh1hhj;hhhhhKubeh}(h]display-hardware-handlingah ]h"]display hardware handlingah$]h&]uh1hhhhhhhhKDubh)}(hhh](h)}(hGT Programmingh]hGT Programming}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhMubh)}(hhh](h)}(h$Multicast/Replicated (MCR) Registersh]h$Multicast/Replicated (MCR) Registers}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhMubh)}(hXwSome GT registers are designed as "multicast" or "replicated" registers: multiple instances of the same register share a single MMIO offset. MCR registers are generally used when the hardware needs to potentially track independent values of a register per hardware unit (e.g., per-subslice, per-L3bank, etc.). The specific types of replication that exist vary per-platform.h]hXSome GT registers are designed as “multicast” or “replicated” registers: multiple instances of the same register share a single MMIO offset. MCR registers are generally used when the hardware needs to potentially track independent values of a register per hardware unit (e.g., per-subslice, per-L3bank, etc.). The specific types of replication that exist vary per-platform.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:261: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chK hj;hhubh)}(hXMMIO accesses to MCR registers are controlled according to the settings programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR registers can be done in either a (i.e., a single write updates all instances of the register to the same value) or unicast (a write updates only one specific instance). Reads of MCR registers always operate in a unicast manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR. Selection of a specific MCR instance for unicast operations is referred to as "steering."h]hXMMIO accesses to MCR registers are controlled according to the settings programmed in the platform’s MCR_SELECTOR register(s). MMIO writes to MCR registers can be done in either a (i.e., a single write updates all instances of the register to the same value) or unicast (a write updates only one specific instance). Reads of MCR registers always operate in a unicast manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR. 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On MTL and beyond, a hardware lock will also be taken to serialize access not only for the driver, but also for external hardware and firmware agents.h]hPerforms locking to protect the steering for the duration of an MCR operation. On MTL and beyond, a hardware lock will also be taken to serialize access not only for the driver, but also for external hardware and firmware agents.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM=hjN=ubh)}(h **Context**h]jb)}(hj>h]hContext}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj >ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMBhjN=ubh)}(hTakes gt->mcr_lock. uncore->lock should *not* be held when this function is called, although it may be acquired after this function call.h](h)Takes gt->mcr_lock. uncore->lock should }(hj$>hhhNhNubhemphasis)}(h*not*h]hnot}(hj.>hhhNhNubah}(h]h ]h"]h$]h&]uh1j,>hj$>ubh\ be held when this function is called, although it may be acquired after this function call.}(hj$>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMBhjN=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_gt_mcr_unlock (C function)c.intel_gt_mcr_unlockhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hCvoid intel_gt_mcr_unlock (struct intel_gt *gt, unsigned long flags)h]j2)}(hBvoid intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags)h](j)}(hvoidh]hvoid}(hjg>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc>hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM}ubji)}(h h]h }(hjv>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjc>hhhju>hM}ubjz)}(hintel_gt_mcr_unlockh]j;)}(hintel_gt_mcr_unlockh]hintel_gt_mcr_unlock}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjc>hhhju>hM}ubj)}(h*(struct intel_gt *gt, unsigned long flags)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>ubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj>modnameN classnameNjXj[)}j^]ja)}jTj>sbc.intel_gt_mcr_unlockasbuh1hhj>ubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj>ubj)}(hjh]h*}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubj;)}(hgth]hgt}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubj)}(hunsigned long flagsh](j)}(hunsignedh]hunsigned}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubji)}(h h]h }(hj$?hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?ubj)}(hlongh]hlong}(hj2?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubji)}(h h]h }(hj@?hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj?ubj;)}(hflagsh]hflags}(hjN?hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj?ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj>ubeh}(h]h ]h"]h$]h&]jjuh1jhjc>hhhju>hM}ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj_>hhhju>hM}ubah}(h]jZ>ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hju>hM}hj\>hhubj1)}(hhh]h)}(hRelease MCR steering lockh]hRelease MCR steering lock}(hjx?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM}hju?hhubah}(h]h ]h"]h$]h&]uh1j0hj\>hhhju>hM}ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj?jSj?jTjUjVuh1j&hhhj;hNhNubjX)}(h**Parameters** ``struct intel_gt *gt`` GT structure ``unsigned long flags`` IRQ flags to restore **Description** Releases the lock acquired by intel_gt_mcr_lock(). **Context** Releases gt->mcr_lockh](h)}(h**Parameters**h]jb)}(hj?h]h Parameters}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj?ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj?h]hstruct intel_gt *gt}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM~hj?ubj)}(hhh]h)}(h GT structureh]h GT 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lock}(hjYAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjVAhhubah}(h]h ]h"]h$]h&]uh1j0hj@hhhj@hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjqAjSjqAjTjUjVuh1j&hhhj;hNhNubjX)}(hXE**Parameters** ``struct intel_gt *gt`` GT structure **Description** This will be used to sanitize the initial status of the hardware lock during driver load and resume since there won't be any concurrent access from other agents at those times, but it's possible that boot firmware may have left the lock in a bad state.h](h)}(h**Parameters**h]jb)}(hj{Ah]h Parameters}(hj}AhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjyAubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjuAubjx)}(hhh]j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjAh]hstruct intel_gt *gt}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjAubj)}(hhh]h)}(h GT structureh]h GT structure}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhMhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1j|hjAhMhjAubah}(h]h ]h"]h$]h&]uh1jwhjuAubh)}(h**Description**h]jb)}(hjAh]h Description}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjAubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjuAubh)}(hThis will be used to sanitize the initial status of the hardware lock during driver load and resume since there won't be any concurrent access from other agents at those times, but it's possible that boot firmware may have left the lock in a bad state.h]hXThis will be used to sanitize the initial status of the hardware lock during driver load and resume since there won’t be any concurrent access from other agents at those times, but it’s possible that boot firmware may have left the lock in a bad state.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjuAubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_gt_mcr_read (C function)c.intel_gt_mcr_readhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hXu32 intel_gt_mcr_read (struct intel_gt *gt, i915_mcr_reg_t reg, int group, int instance)h]j2)}(hWu32 intel_gt_mcr_read(struct intel_gt *gt, i915_mcr_reg_t reg, int group, int instance)h](h)}(hhh]j;)}(hu32h]hu32}(hjBhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjBubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjBmodnameN classnameNjXj[)}j^]ja)}jTintel_gt_mcr_readsbc.intel_gt_mcr_readasbuh1hhjBhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hj?BhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjBhhhj>BhMubjz)}(hintel_gt_mcr_readh]j;)}(hj;Bh]hintel_gt_mcr_read}(hjQBhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjMBubah}(h]h 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](jRfunctioneh"]h$]h&]jQjRjRjCjSjCjTjUjVuh1j&hhhj;hNhNubjX)}(hXJ**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to read ``int group`` the MCR group ``int instance`` the MCR instance **Context** Takes and releases gt->mcr_lock **Description** Returns the value read from an MCR register after steering toward a specific group/instance.h](h)}(h**Parameters**h]jb)}(hjCh]h Parameters}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jahjCubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjCubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjCh]hstruct intel_gt *gt}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjCubj)}(hhh]h)}(h GT structureh]h GT structure}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMhjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1j|hjChMhjCubj})}(h0``i915_mcr_reg_t reg`` the MCR register to read h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjDh]hi915_mcr_reg_t reg}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjDubj)}(hhh]h)}(hthe MCR register to readh]hthe MCR register to read}(hj2DhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.DhMhj/Dubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j|hj.DhMhjCubj})}(h``int group`` the MCR group h](j)}(h ``int group``h]j)}(hjRDh]h int group}(hjTDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPDubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjLDubj)}(hhh]h)}(h the MCR grouph]h the MCR group}(hjkDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgDhMhjhDubah}(h]h ]h"]h$]h&]uh1jhjLDubeh}(h]h ]h"]h$]h&]uh1j|hjgDhMhjCubj})}(h"``int instance`` the MCR instance h](j)}(h``int instance``h]j)}(hjDh]h int instance}(hjDhhhNhNubah}(h]h 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refdomainjRreftypejT reftargetjEmodnameN classnameNjXj[)}j^]jEc.intel_gt_mcr_unicast_writeasbuh1hhjEubji)}(h h]h }(hjFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubj;)}(hregh]hreg}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjgEubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj,FhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)Fubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj.FmodnameN classnameNjXj[)}j^]jEc.intel_gt_mcr_unicast_writeasbuh1hhj%Fubji)}(h h]h }(hjJFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj%Fubj;)}(hvalueh]hvalue}(hjXFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%Fubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjgEubj)}(h int grouph](j)}(hinth]hint}(hjqFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmFubji)}(h h]h }(hjFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjmFubj;)}(hgrouph]hgroup}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmFubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjgEubj)}(h int instanceh](j)}(hinth]hint}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubji)}(h h]h }(hjFhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjFubj;)}(hinstanceh]hinstance}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjgEubeh}(h]h ]h"]h$]h&]jjuh1jhj.Ehhhj@EhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj*Ehhhj@EhMubah}(h]j%Eah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj@EhMhj'Ehhubj1)}(hhh]h)}(h,write a specific instance of an MCR registerh]h,write a specific instance of an MCR register}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjFhhubah}(h]h ]h"]h$]h&]uh1j0hj'Ehhhj@EhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjGjSjGjTjUjVuh1j&hhhj;hNhNubjX)}(hX{**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to write ``u32 value`` value to write ``int group`` the MCR group ``int instance`` the MCR instance **Description** Write an MCR register in unicast mode after steering toward a specific group/instance. **Context** Calls a function that takes and releases gt->mcr_lockh](h)}(h**Parameters**h]jb)}(hjGh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj Gubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj-Gh]hstruct intel_gt *gt}(hj/GhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+Gubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj'Gubj)}(hhh]h)}(h GT structureh]h GT structure}(hjFGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBGhMhjCGubah}(h]h ]h"]h$]h&]uh1jhj'Gubeh}(h]h ]h"]h$]h&]uh1j|hjBGhMhj$Gubj})}(h1``i915_mcr_reg_t reg`` the MCR register to write h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjfGh]hi915_mcr_reg_t reg}(hjhGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdGubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj`Gubj)}(hhh]h)}(hthe MCR register to writeh]hthe MCR register to write}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{GhMhj|Gubah}(h]h ]h"]h$]h&]uh1jhj`Gubeh}(h]h ]h"]h$]h&]uh1j|hj{GhMhj$Gubj})}(h``u32 value`` value to write h](j)}(h ``u32 value``h]j)}(hjGh]h u32 value}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubj)}(hhh]h)}(hvalue to writeh]hvalue to write}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1j|hjGhMhj$Gubj})}(h``int group`` the MCR group h](j)}(h ``int group``h]j)}(hjGh]h int group}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubj)}(hhh]h)}(h the MCR grouph]h the MCR group}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1j|hjGhMhj$Gubj})}(h"``int instance`` the MCR instance h](j)}(h``int instance``h]j)}(hjHh]h int instance}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj Hubj)}(hhh]h)}(hthe MCR instanceh]hthe MCR instance}(hj*HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&HhMhj'Hubah}(h]h ]h"]h$]h&]uh1jhj Hubeh}(h]h ]h"]h$]h&]uh1j|hj&HhMhj$Gubeh}(h]h ]h"]h$]h&]uh1jwhjGubh)}(h**Description**h]jb)}(hjLHh]h Description}(hjNHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjJHubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubh)}(hVWrite an MCR register in unicast mode after steering toward a specific group/instance.h]hVWrite an MCR register in unicast mode after steering toward a specific group/instance.}(hjbHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubh)}(h **Context**h]jb)}(hjsHh]hContext}(hjuHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjqHubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubh)}(h5Calls a function that takes and releases gt->mcr_lockh]h5Calls a function that takes and releases gt->mcr_lock}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjGubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_gt_mcr_multicast_write (C function)c.intel_gt_mcr_multicast_writehNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hVvoid intel_gt_mcr_multicast_write (struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h]j2)}(hUvoid intel_gt_mcr_multicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j)}(hvoidh]hvoid}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hjHhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHhhhjHhMubjz)}(hintel_gt_mcr_multicast_writeh]j;)}(hintel_gt_mcr_multicast_writeh]hintel_gt_mcr_multicast_write}(hjHhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjHubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjHhhhjHhMubj)}(h4(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubji)}(h h]h }(hjIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjImodnameN classnameNjXj[)}j^]ja)}jTjHsbc.intel_gt_mcr_multicast_writeasbuh1hhjHubji)}(h h]h }(hj3IhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHubj)}(hjh]h*}(hjAIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubj;)}(hgth]hgt}(hjNIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjHubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjHubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjgIubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjlImodnameN classnameNjXj[)}j^]j/Ic.intel_gt_mcr_multicast_writeasbuh1hhjcIubji)}(h h]h }(hjIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjcIubj;)}(hregh]hreg}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjcIubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjHubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjImodnameN classnameNjXj[)}j^]j/Ic.intel_gt_mcr_multicast_writeasbuh1hhjIubji)}(h h]h }(hjIhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjIubj;)}(hvalueh]hvalue}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjHubeh}(h]h ]h"]h$]h&]jjuh1jhjHhhhjHhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjHhhhjHhMubah}(h]jHah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjHhMhjHhhubj1)}(hhh]h)}(h1write a value to all instances of an MCR registerh]h1write a value to all instances of an MCR register}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjJhhubah}(h]h ]h"]h$]h&]uh1j0hjHhhhjHhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj JjSj JjTjUjVuh1j&hhhj;hNhNubjX)}(hX **Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to write ``u32 value`` value to write **Description** Write an MCR register in multicast mode to update all instances. **Context** Takes and releases gt->mcr_lockh](h)}(h**Parameters**h]jb)}(hj*Jh]h Parameters}(hj,JhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj(Jubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj$Jubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjIJh]hstruct intel_gt *gt}(hjKJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGJubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjCJubj)}(hhh]h)}(h GT structureh]h GT structure}(hjbJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^JhMhj_Jubah}(h]h ]h"]h$]h&]uh1jhjCJubeh}(h]h ]h"]h$]h&]uh1j|hj^JhMhj@Jubj})}(h1``i915_mcr_reg_t reg`` the MCR register to write h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjJh]hi915_mcr_reg_t reg}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj|Jubj)}(hhh]h)}(hthe MCR register to writeh]hthe MCR register to write}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMhjJubah}(h]h ]h"]h$]h&]uh1jhj|Jubeh}(h]h ]h"]h$]h&]uh1j|hjJhMhj@Jubj})}(h``u32 value`` value to write h](j)}(h ``u32 value``h]j)}(hjJh]h u32 value}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjJubj)}(hhh]h)}(hvalue to writeh]hvalue to write}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMhjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1j|hjJhMhj@Jubeh}(h]h ]h"]h$]h&]uh1jwhj$Jubh)}(h**Description**h]jb)}(hjJh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjJubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj$Jubh)}(h@Write an MCR register in multicast mode to update all instances.h]h@Write an MCR register in multicast mode to update all instances.}(hj KhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj$Jubh)}(h **Context**h]jb)}(hjKh]hContext}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjKubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj$Jubh)}(hTakes and releases gt->mcr_lockh]hTakes and releases gt->mcr_lock}(hj3KhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj$Jubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_gt_mcr_multicast_write_fw (C function)!c.intel_gt_mcr_multicast_write_fwhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hYvoid intel_gt_mcr_multicast_write_fw (struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h]j2)}(hXvoid intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j)}(hvoidh]hvoid}(hjbKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^Khhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hjqKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj^KhhhjpKhMubjz)}(hintel_gt_mcr_multicast_write_fwh]j;)}(hintel_gt_mcr_multicast_write_fwh]hintel_gt_mcr_multicast_write_fw}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj^KhhhjpKhMubj)}(h4(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjKmodnameN classnameNjXj[)}j^]ja)}jTjKsb!c.intel_gt_mcr_multicast_write_fwasbuh1hhjKubji)}(h h]h }(hjKhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj)}(hjh]h*}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubj;)}(hgth]hgt}(hjKhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjLhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjLubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjLmodnameN classnameNjXj[)}j^]jK!c.intel_gt_mcr_multicast_write_fwasbuh1hhj Lubji)}(h h]h }(hj2LhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj Lubj;)}(hregh]hreg}(hj@LhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj Lubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubj)}(h u32 valueh](h)}(hhh]j;)}(hu32h]hu32}(hj\LhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjYLubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj^LmodnameN classnameNjXj[)}j^]jK!c.intel_gt_mcr_multicast_write_fwasbuh1hhjULubji)}(h h]h }(hjzLhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjULubj;)}(hvalueh]hvalue}(hjLhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjULubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjKubeh}(h]h ]h"]h$]h&]jjuh1jhj^KhhhjpKhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjZKhhhjpKhMubah}(h]jUKah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjpKhMhjWKhhubj1)}(hhh]h)}(h1write a value to all instances of an MCR registerh]h1write a value to all instances of an MCR register}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjLhhubah}(h]h ]h"]h$]h&]uh1j0hjWKhhhjpKhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjLjSjLjTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to write ``u32 value`` value to write **Description** Write an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically. **Context** The caller must hold gt->mcr_lock.h](h)}(h**Parameters**h]jb)}(hjLh]h Parameters}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjLubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjLubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjLh]hstruct intel_gt *gt}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjLubj)}(hhh]h)}(h GT structureh]h GT structure}(hj MhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhMhj Mubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjMhMhjLubj})}(h1``i915_mcr_reg_t reg`` the MCR register to write h](j)}(h``i915_mcr_reg_t reg``h]j)}(hj,Mh]hi915_mcr_reg_t reg}(hj.MhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*Mubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj&Mubj)}(hhh]h)}(hthe MCR register to writeh]hthe MCR register to write}(hjEMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAMhMhjBMubah}(h]h ]h"]h$]h&]uh1jhj&Mubeh}(h]h ]h"]h$]h&]uh1j|hjAMhMhjLubj})}(h``u32 value`` value to write h](j)}(h ``u32 value``h]j)}(hjeMh]h u32 value}(hjgMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcMubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj_Mubj)}(hhh]h)}(hvalue to writeh]hvalue to write}(hj~MhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzMhMhj{Mubah}(h]h ]h"]h$]h&]uh1jhj_Mubeh}(h]h ]h"]h$]h&]uh1j|hjzMhMhjLubeh}(h]h ]h"]h$]h&]uh1jwhjLubh)}(h**Description**h]jb)}(hjMh]h Description}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjMubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjLubh)}(hWrite an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically.h]hWrite an MCR register in multicast mode to update all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_write() in cases where forcewake should be obtained automatically.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjLubh)}(h **Context**h]jb)}(hjMh]hContext}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjMubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjLubh)}(h"The caller must hold gt->mcr_lock.h]h"The caller must hold gt->mcr_lock.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjLubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"'intel_gt_mcr_multicast_rmw (C function)c.intel_gt_mcr_multicast_rmwhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(h\u32 intel_gt_mcr_multicast_rmw (struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h]j2)}(h[u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h](h)}(hhh]j;)}(hu32h]hu32}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj Nubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjNmodnameN classnameNjXj[)}j^]ja)}jTintel_gt_mcr_multicast_rmwsbc.intel_gt_mcr_multicast_rmwasbuh1hhjNhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hj1NhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjNhhhj0NhMubjz)}(hintel_gt_mcr_multicast_rmwh]j;)}(hj-Nh]hintel_gt_mcr_multicast_rmw}(hjCNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj?Nubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjNhhhj0NhMubj)}(h=(struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hj^NhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZNubji)}(h h]h }(hjkNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjZNubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hj|NhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjyNubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj~NmodnameN classnameNjXj[)}j^]j+Nc.intel_gt_mcr_multicast_rmwasbuh1hhjZNubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjZNubj)}(hjh]h*}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZNubj;)}(hgth]hgt}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjZNubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjVNubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjNmodnameN classnameNjXj[)}j^]j+Nc.intel_gt_mcr_multicast_rmwasbuh1hhjNubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjNubj;)}(hregh]hreg}(hjNhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjVNubj)}(h u32 clearh](h)}(hhh]j;)}(hu32h]hu32}(hjOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjOubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjOmodnameN classnameNjXj[)}j^]j+Nc.intel_gt_mcr_multicast_rmwasbuh1hhjOubji)}(h h]h }(hj7OhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjOubj;)}(hclearh]hclear}(hjEOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjOubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjVNubj)}(hu32 seth](h)}(hhh]j;)}(hu32h]hu32}(hjaOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj^Oubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjcOmodnameN classnameNjXj[)}j^]j+Nc.intel_gt_mcr_multicast_rmwasbuh1hhjZOubji)}(h h]h }(hjOhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjZOubj;)}(hseth]hset}(hjOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjZOubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjVNubeh}(h]h ]h"]h$]h&]jjuh1jhjNhhhj0NhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjNhhhj0NhMubah}(h]jMah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj0NhMhjNhhubj1)}(hhh]h)}(h#Performs a multicast RMW operationsh]h#Performs a multicast RMW operations}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjOhhubah}(h]h ]h"]h$]h&]uh1j0hjNhhhj0NhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjOjSjOjTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` the MCR register to read and write ``u32 clear`` bits to clear during RMW ``u32 set`` bits to set during RMW **Description** Performs a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances. This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically. Returns the old (unmodified) value read. **Context** Calls functions that take and release gt->mcr_lockh](h)}(h**Parameters**h]jb)}(hjOh]h Parameters}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjOubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hjOubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjOh]hstruct intel_gt *gt}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjOubj)}(hhh]h)}(h GT structureh]h GT structure}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj PhMhjPubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j|hj PhMhjOubj})}(h:``i915_mcr_reg_t reg`` the MCR register to read and write h](j)}(h``i915_mcr_reg_t reg``h]j)}(hj1Ph]hi915_mcr_reg_t reg}(hj3PhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/Pubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj+Pubj)}(hhh]h)}(h"the MCR register to read and writeh]h"the MCR register to read and write}(hjJPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFPhMhjGPubah}(h]h ]h"]h$]h&]uh1jhj+Pubeh}(h]h ]h"]h$]h&]uh1j|hjFPhMhjOubj})}(h'``u32 clear`` bits to clear during RMW h](j)}(h ``u32 clear``h]j)}(hjjPh]h u32 clear}(hjlPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhPubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hjdPubj)}(hhh]h)}(hbits to clear during RMWh]hbits to clear during RMW}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM hjPubah}(h]h ]h"]h$]h&]uh1jhjdPubeh}(h]h ]h"]h$]h&]uh1j|hjPhM hjOubj})}(h#``u32 set`` bits to set during RMW h](j)}(h ``u32 set``h]j)}(hjPh]hu32 set}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hjPubj)}(hhh]h)}(hbits to set during RMWh]hbits to set during RMW}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM hjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j|hjPhM hjOubeh}(h]h ]h"]h$]h&]uh1jwhjOubh)}(h**Description**h]jb)}(hjPh]h Description}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjPubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hjOubh)}(hXPerforms a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances.h]hXPerforms a read-modify-write on an MCR register in a multicast manner. This operation only makes sense on MCR registers where all instances are expected to have the same value. The read will target any non-terminated instance and the write will be applied to all instances.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM hjOubh)}(hThis function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically.h]hThis function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should be obtained automatically.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjOubh)}(h(Returns the old (unmodified) value read.h]h(Returns the old (unmodified) value read.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjOubh)}(h **Context**h]jb)}(hj#Qh]hContext}(hj%QhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj!Qubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjOubh)}(h2Calls functions that take and release gt->mcr_lockh]h2Calls functions that take and release gt->mcr_lock}(hj9QhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjOubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"4intel_gt_mcr_get_nonterminated_steering (C function))c.intel_gt_mcr_get_nonterminated_steeringhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hovoid intel_gt_mcr_get_nonterminated_steering (struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h]j2)}(hnvoid intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h](j)}(hvoidh]hvoid}(hjhQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdQhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hjwQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjdQhhhjvQhMubjz)}(h'intel_gt_mcr_get_nonterminated_steeringh]j;)}(h'intel_gt_mcr_get_nonterminated_steeringh]h'intel_gt_mcr_get_nonterminated_steering}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjdQhhhjvQhMubj)}(hB(struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjQmodnameN classnameNjXj[)}j^]ja)}jTjQsb)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhjQubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj)}(hjh]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj;)}(hgth]hgt}(hjQhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjRmodnameN classnameNjXj[)}j^]jQ)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhjRubji)}(h h]h }(hj8RhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj;)}(hregh]hreg}(hjFRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(h u8 *grouph](h)}(hhh]j;)}(hu8h]hu8}(hjbRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_Rubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjdRmodnameN classnameNjXj[)}j^]jQ)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhj[Rubji)}(h h]h }(hjRhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj[Rubj)}(hjh]h*}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[Rubj;)}(hgrouph]hgroup}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj[Rubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubj)}(h u8 *instanceh](h)}(hhh]j;)}(hu8h]hu8}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjRmodnameN classnameNjXj[)}j^]jQ)c.intel_gt_mcr_get_nonterminated_steeringasbuh1hhjRubji)}(h h]h }(hjRhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj)}(hjh]h*}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj;)}(hinstanceh]hinstance}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjQubeh}(h]h ]h"]h$]h&]jjuh1jhjdQhhhjvQhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj`QhhhjvQhMubah}(h]j[Qah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjvQhMhj]Qhhubj1)}(hhh]h)}(hRfind group/instance values that will steer a register to a non-terminated instanceh]hRfind group/instance values that will steer a register to a non-terminated instance}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjShhubah}(h]h ]h"]h$]h&]uh1j0hj]QhhhjvQhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj2SjSj2SjTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` register for which the steering is required ``u8 *group`` return variable for group steering ``u8 *instance`` return variable for instance steering **Description** This function returns a group/instance pair that is guaranteed to work for read steering of the given register. Note that a value will be returned even if the register is not replicated and therefore does not actually require steering.h](h)}(h**Parameters**h]jb)}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jahj:Subah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6Subjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj[Sh]hstruct intel_gt *gt}(hj]ShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYSubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjUSubj)}(hhh]h)}(h GT structureh]h GT structure}(hjtShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpShMhjqSubah}(h]h ]h"]h$]h&]uh1jhjUSubeh}(h]h ]h"]h$]h&]uh1j|hjpShMhjRSubj})}(hC``i915_mcr_reg_t reg`` register for which the steering is required h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjSh]hi915_mcr_reg_t reg}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjSubj)}(hhh]h)}(h+register for which the steering is requiredh]h+register for which the steering is required}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMhjSubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1j|hjShMhjRSubj})}(h1``u8 *group`` return variable for group steering h](j)}(h ``u8 *group``h]j)}(hjSh]h u8 *group}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjSubj)}(hhh]h)}(h"return variable for group steeringh]h"return variable for group steering}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMhjSubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1j|hjShMhjRSubj})}(h7``u8 *instance`` return variable for instance steering h](j)}(h``u8 *instance``h]j)}(hjTh]h u8 *instance}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjTubj)}(hhh]h)}(h%return variable for instance steeringh]h%return variable for instance steering}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThMhjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j|hjThMhjRSubeh}(h]h ]h"]h$]h&]uh1jwhj6Subh)}(h**Description**h]jb)}(hjATh]h Description}(hjCThhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?Tubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6Subh)}(hThis function returns a group/instance pair that is guaranteed to work for read steering of the given register. Note that a value will be returned even if the register is not replicated and therefore does not actually require steering.h]hThis function returns a group/instance pair that is guaranteed to work for read steering of the given register. Note that a value will be returned even if the register is not replicated and therefore does not actually require steering.}(hjWThhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj6Subeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%intel_gt_mcr_read_any_fw (C function)c.intel_gt_mcr_read_any_fwhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hFu32 intel_gt_mcr_read_any_fw (struct intel_gt *gt, i915_mcr_reg_t reg)h]j2)}(hEu32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg)h](h)}(hhh]j;)}(hu32h]hu32}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjTubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjTmodnameN classnameNjXj[)}j^]ja)}jTintel_gt_mcr_read_any_fwsbc.intel_gt_mcr_read_any_fwasbuh1hhjThhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hjThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjThhhjThMubjz)}(hintel_gt_mcr_read_any_fwh]j;)}(hjTh]hintel_gt_mcr_read_any_fw}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjTubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjThhhjThMubj)}(h)(struct intel_gt *gt, i915_mcr_reg_t reg)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubji)}(h h]h }(hjThhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjThhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjTubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjTmodnameN classnameNjXj[)}j^]jTc.intel_gt_mcr_read_any_fwasbuh1hhjTubji)}(h h]h }(hjUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjTubj)}(hjh]h*}(hj"UhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubj;)}(hgth]hgt}(hj/UhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjTubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjKUhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjHUubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjMUmodnameN classnameNjXj[)}j^]jTc.intel_gt_mcr_read_any_fwasbuh1hhjDUubji)}(h h]h }(hjiUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjDUubj;)}(hregh]hreg}(hjwUhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjDUubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjTubeh}(h]h ]h"]h$]h&]jjuh1jhjThhhjThMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj~ThhhjThMubah}(h]jyTah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjThMhj{Thhubj1)}(hhh]h)}(h%reads one instance of an MCR registerh]h%reads one instance of an MCR register}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjUhhubah}(h]h ]h"]h$]h&]uh1j0hj{ThhhjThMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjUjSjUjTjUjVuh1j&hhhj;hNhNubjX)}(hX **Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` register to read **Description** Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically. Returns the value from a non-terminated instance of **reg**. **Context** The caller must hold gt->mcr_lock.h](h)}(h**Parameters**h]jb)}(hjUh]h Parameters}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjUubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjUubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hjUh]hstruct intel_gt *gt}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjUubj)}(hhh]h)}(h GT structureh]h GT structure}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j|hjUhMhjUubj})}(h(``i915_mcr_reg_t reg`` register to read h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjVh]hi915_mcr_reg_t reg}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjVubj)}(hhh]h)}(hregister to readh]hregister to read}(hj4VhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0VhMhj1Vubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j|hj0VhMhjUubeh}(h]h ]h"]h$]h&]uh1jwhjUubh)}(h**Description**h]jb)}(hjVVh]h Description}(hjXVhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjTVubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjUubh)}(hX=Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically.h]hX?Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn’t fused off or powered down by power gating). This function assumes the caller is already holding any necessary forcewake domains; use intel_gt_mcr_read_any() in cases where forcewake should be obtained automatically.}(hjlVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjUubh)}(hmcr_lock.h]h"The caller must hold gt->mcr_lock.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_gt_mcr_read_any (C function)c.intel_gt_mcr_read_anyhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hCu32 intel_gt_mcr_read_any (struct intel_gt *gt, i915_mcr_reg_t reg)h]j2)}(hBu32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg)h](h)}(hhh]j;)}(hu32h]hu32}(hjVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjVmodnameN classnameNjXj[)}j^]ja)}jTintel_gt_mcr_read_anysbc.intel_gt_mcr_read_anyasbuh1hhjVhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVhhhjWhMubjz)}(hintel_gt_mcr_read_anyh]j;)}(hjWh]hintel_gt_mcr_read_any}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjWubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjVhhhjWhMubj)}(h)(struct intel_gt *gt, i915_mcr_reg_t reg)h](j)}(hstruct intel_gt *gth](j)}(hjh]hstruct}(hj5WhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1Wubji)}(h h]h }(hjBWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj1Wubh)}(hhh]j;)}(hintel_gth]hintel_gt}(hjSWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjPWubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjUWmodnameN classnameNjXj[)}j^]jWc.intel_gt_mcr_read_anyasbuh1hhj1Wubji)}(h h]h }(hjqWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj1Wubj)}(hjh]h*}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1Wubj;)}(hgth]hgt}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj1Wubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj-Wubj)}(hi915_mcr_reg_t regh](h)}(hhh]j;)}(hi915_mcr_reg_th]hi915_mcr_reg_t}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjWubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjWmodnameN classnameNjXj[)}j^]jWc.intel_gt_mcr_read_anyasbuh1hhjWubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjWubj;)}(hregh]hreg}(hjWhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjWubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj-Wubeh}(h]h ]h"]h$]h&]jjuh1jhjVhhhjWhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjVhhhjWhMubah}(h]jVah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjWhMhjVhhubj1)}(hhh]h)}(h%reads one instance of an MCR registerh]h%reads one instance of an MCR register}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjWhhubah}(h]h ]h"]h$]h&]uh1j0hjVhhhjWhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjXjSjXjTjUjVuh1j&hhhj;hNhNubjX)}(hX**Parameters** ``struct intel_gt *gt`` GT structure ``i915_mcr_reg_t reg`` register to read **Description** Reads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating). Returns the value from a non-terminated instance of **reg**. **Context** Calls a function that takes and releases gt->mcr_lock.h](h)}(h**Parameters**h]jb)}(hj Xh]h Parameters}(hj"XhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj?Xh]hstruct intel_gt *gt}(hjAXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=Xubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhj9Xubj)}(hhh]h)}(h GT structureh]h GT structure}(hjXXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTXhMhjUXubah}(h]h ]h"]h$]h&]uh1jhj9Xubeh}(h]h ]h"]h$]h&]uh1j|hjTXhMhj6Xubj})}(h(``i915_mcr_reg_t reg`` register to read h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjxXh]hi915_mcr_reg_t reg}(hjzXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvXubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjrXubj)}(hhh]h)}(hregister to readh]hregister to read}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhMhjXubah}(h]h ]h"]h$]h&]uh1jhjrXubeh}(h]h ]h"]h$]h&]uh1j|hjXhMhj6Xubeh}(h]h ]h"]h$]h&]uh1jwhjXubh)}(h**Description**h]jb)}(hjXh]h Description}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubh)}(hReads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn't fused off or powered down by power gating).h]hReads a GT MCR register. The read will be steered to a non-terminated instance (i.e., one that isn’t fused off or powered down by power gating).}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubh)}(hmcr_lock.h]h6Calls a function that takes and releases gt->mcr_lock.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMhjXubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_gt_mcr_get_ss_steering (C function)c.intel_gt_mcr_get_ss_steeringhNtauh1jhj;hhhNhNubj')}(hhh](j,)}(hvvoid intel_gt_mcr_get_ss_steering (struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance)h]j2)}(huvoid intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance)h](j)}(hvoidh]hvoid}(hj@YhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmcr_lock **Return** 0 if the register matches the desired condition, or -ETIMEDOUT.h](h)}(h**Parameters**h]jb)}(hj^h]h Parameters}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj^ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM2hj^ubjx)}(hhh](j})}(h%``struct intel_gt *gt`` GT structure h](j)}(h``struct intel_gt *gt``h]j)}(hj_h]hstruct intel_gt *gt}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM/hj_ubj)}(hhh]h)}(h GT structureh]h GT structure}(hj1_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-_hM/hj._ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hj-_hM/hj_ubj})}(h,``i915_mcr_reg_t reg`` the register to read h](j)}(h``i915_mcr_reg_t reg``h]j)}(hjQ_h]hi915_mcr_reg_t reg}(hjS_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjO_ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM0hjK_ubj)}(hhh]h)}(hthe register to readh]hthe register to read}(hjj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf_hM0hjg_ubah}(h]h ]h"]h$]h&]uh1jhjK_ubeh}(h]h ]h"]h$]h&]uh1j|hjf_hM0hj_ubj})}(h-``u32 mask`` mask to apply to register value h](j)}(h ``u32 mask``h]j)}(hj_h]hu32 mask}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM1hj_ubj)}(hhh]h)}(hmask to apply to register valueh]hmask to apply to register value}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM1hj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hj_hM1hj_ubj})}(h ``u32 value`` value to wait for h](j)}(h ``u32 value``h]j)}(hj_h]h u32 value}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM2hj_ubj)}(hhh]h)}(hvalue to wait forh]hvalue to wait for}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM2hj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hj_hM2hj_ubj})}(hS``unsigned int fast_timeout_us`` fast timeout in microsecond for atomic/tight wait h](j)}(h ``unsigned int fast_timeout_us``h]j)}(hj_h]hunsigned int fast_timeout_us}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM3hj_ubj)}(hhh]h)}(h1fast timeout in microsecond for atomic/tight waith]h1fast timeout in microsecond for atomic/tight wait}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hM3hj`ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hj`hM3hj_ubj})}(h=``unsigned int slow_timeout_ms`` slow timeout in millisecond h](j)}(h ``unsigned int slow_timeout_ms``h]j)}(hj5`h]hunsigned int slow_timeout_ms}(hj7`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3`ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM4hj/`ubj)}(hhh]h)}(hslow timeout in millisecondh]hslow timeout in millisecond}(hjN`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ`hM4hjK`ubah}(h]h ]h"]h$]h&]uh1jhj/`ubeh}(h]h ]h"]h$]h&]uh1j|hjJ`hM4hj_ubeh}(h]h ]h"]h$]h&]uh1jwhj^ubh)}(h**Description**h]jb)}(hjp`h]h Description}(hjr`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjn`ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM6hj^ubh)}(hThis routine waits until the target register **reg** contains the expected **value** after applying the **mask**, i.e. it waits until ::h](h-This routine waits until the target register }(hj`hhhNhNubjb)}(h**reg**h]hreg}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubh contains the expected }(hj`hhhNhNubjb)}(h **value**h]hvalue}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubh after applying the }(hj`hhhNhNubjb)}(h**mask**h]hmask}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubh, i.e. it waits until}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM6hj^ubj")}(h3(intel_gt_mcr_read_any_fw(gt, reg) & mask) == valueh]h3(intel_gt_mcr_read_any_fw(gt, reg) & mask) == value}hj`sbah}(h]h ]h"]h$]h&]jjuh1j"h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM9hj^ubh)}(hOtherwise, the wait will timeout after **slow_timeout_ms** milliseconds. For atomic context **slow_timeout_ms** must be zero and **fast_timeout_us** must be not larger than 20,0000 microseconds.h](h'Otherwise, the wait will timeout after }(hj`hhhNhNubjb)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubh" milliseconds. For atomic context }(hj`hhhNhNubjb)}(h**slow_timeout_ms**h]hslow_timeout_ms}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubh must be zero and }(hj`hhhNhNubjb)}(h**fast_timeout_us**h]hfast_timeout_us}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jahj`ubh. must be not larger than 20,0000 microseconds.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM;hj^ubh)}(hX#This function is basically an MCR-friendly version of __intel_wait_for_register_fw(). Generally this function will only be used on GAM registers which are a bit special --- although they're MCR registers, reads (e.g., waiting for status updates) are always directed to the primary instance.h]hX%This function is basically an MCR-friendly version of __intel_wait_for_register_fw(). Generally this function will only be used on GAM registers which are a bit special --- although they’re MCR registers, reads (e.g., waiting for status updates) are always directed to the primary instance.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chM?hj^ubh)}(hkNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits.h]hkNote that this routine assumes the caller holds forcewake asserted, it is not suitable for very long waits.}(hj.ahhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMEhj^ubh)}(h **Context**h]jb)}(hj?ah]hContext}(hjAahhhNhNubah}(h]h ]h"]h$]h&]uh1jahj=aubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMHhj^ubh)}(h5Calls a function that takes and releases gt->mcr_lockh]h5Calls a function that takes and releases gt->mcr_lock}(hjUahhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMHhj^ubh)}(h **Return**h]jb)}(hjfah]hReturn}(hjhahhhNhNubah}(h]h ]h"]h$]h&]uh1jahjdaubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMJhj^ubh)}(h?0 if the register matches the desired condition, or -ETIMEDOUT.h]h?0 if the register matches the desired condition, or -ETIMEDOUT.}(hj|ahhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:264: ./drivers/gpu/drm/i915/gt/intel_gt_mcr.chMIhj^ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj;hhhNhNubeh}(h]"multicast-replicated-mcr-registersah ]h"]$multicast/replicated (mcr) registersah$]h&]uh1hhj;hhhhhMubeh}(h]gt-programmingah ]h"]gt programmingah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h(Memory Management and Command Submissionh]h(Memory Management and Command Submission}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahhhhhM ubh)}(hUThis sections covers all things related to the GEM implementation in the i915 driver.h]hUThis sections covers all things related to the GEM implementation in the i915 driver.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjahhubh)}(hhh](h)}(hIntel GPU Basicsh]hIntel GPU Basics}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahhhhhMubh)}(hBAn Intel GPU has multiple engines. There are several engine types:h]hBAn Intel GPU has multiple engines. There are several engine types:}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjahhubj:)}(hhh](j:)}(hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.h]h)}(hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.h]hQRender Command Streamer (RCS). An engine for rendering 3D and performing compute.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjaubah}(h]h ]h"]h$]h&]uh1j:hjahhhhhNubj:)}(h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.h]h)}(h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.h]h]Blitting Command Streamer (BCS). An engine for performing blitting and/or copying operations.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjaubah}(h]h ]h"]h$]h&]uh1j:hjahhhhhNubj:)}(h~Video Command Streamer. An engine used for video encoding and decoding. Also sometimes called 'BSD' in hardware documentation.h]h)}(h~Video Command Streamer. An engine used for video encoding and decoding. Also sometimes called 'BSD' in hardware documentation.h]hVideo Command Streamer. An engine used for video encoding and decoding. Also sometimes called ‘BSD’ in hardware documentation.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjbubah}(h]h ]h"]h$]h&]uh1j:hjahhhhhNubj:)}(hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called 'VEBOX' in hardware documentation.h]h)}(hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called 'VEBOX' in hardware documentation.h]hVideo Enhancement Command Streamer (VECS). An engine for video enhancement. Also sometimes called ‘VEBOX’ in hardware documentation.}(hj/bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+bubah}(h]h ]h"]h$]h&]uh1j:hjahhhhhNubj:)}(htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.h]h)}(htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.h]htCompute Command Streamer (CCS). An engine that has access to the media and GPGPU pipelines, but not the 3D pipeline.}(hjGbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjCbubah}(h]h ]h"]h$]h&]uh1j:hjahhhhhNubj:)}(hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication. h]h)}(hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication.h]hGraphics Security Controller (GSCCS). A dedicated engine for internal communication with GSC controller on security related tasks like High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), and HuC firmware authentication.}(hj_bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj[bubah}(h]h ]h"]h$]h&]uh1j:hjahhhhhNubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hhhMhjahhubh)}(hXThe Intel GPU family is a family of integrated GPU's using Unified Memory Access. For having the GPU "do work", user space will feed the GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will instruct the GPU to perform work (for example rendering) and that work needs memory from which to read and memory to which to write. All memory is encapsulated within GEM buffer objects (usually created with the ioctl `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU to create will also list all GEM buffer objects that the batchbuffer reads and/or writes. For implementation details of memory management see `GEM BO Management Implementation Details`_.h](hThe Intel GPU family is a family of integrated GPU’s using Unified Memory Access. For having the GPU “do work”, user space will feed the GPU batch buffers via one of the ioctls }(hjybhhhNhNubhtitle_reference)}(h `DRM_IOCTL_I915_GEM_EXECBUFFER2`h]hDRM_IOCTL_I915_GEM_EXECBUFFER2}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jbhjybubh or }(hjybhhhNhNubjb)}(h#`DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`h]h!DRM_IOCTL_I915_GEM_EXECBUFFER2_WR}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jbhjybubh. Most such batchbuffers will instruct the GPU to perform work (for example rendering) and that work needs memory from which to read and memory to which to write. All memory is encapsulated within GEM buffer objects (usually created with the ioctl }(hjybhhhNhNubjb)}(h`DRM_IOCTL_I915_GEM_CREATE`h]hDRM_IOCTL_I915_GEM_CREATE}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jbhjybubh). An ioctl providing a batchbuffer for the GPU to create will also list all GEM buffer objects that the batchbuffer reads and/or writes. For implementation details of memory management see }(hjybhhhNhNubj!5)}(h+`GEM BO Management Implementation Details`_h]h(GEM BO Management Implementation Details}(hjbhhhNhNubah}(h]h ]h"]h$]h&]name(GEM BO Management Implementation Detailsj:(gem-bo-management-implementation-detailsuh1j 5hjybj:Kubh.}(hjybhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM%hjahhubh)}(hXThe i915 driver allows user space to create a context via the ioctl `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit integer. Such a context should be viewed by user-space as -loosely- analogous to the idea of a CPU process of an operating system. The i915 driver guarantees that commands issued to a fixed context are to be executed so that writes of a previously issued command are seen by reads of following commands. Actions issued between different contexts (even if from the same file descriptor) are NOT given that guarantee and the only way to synchronize across contexts (even from the same file descriptor) is through the use of fences. At least as far back as Gen4, also have that a context carries with it a GPU HW context; the HW context is essentially (most of at least) the state of a GPU. In addition to the ordering guarantees, the kernel will restore GPU state via HW context when commands are issued to a context, this saves user space the need to restore (most of at least) the GPU state at the start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use with the command.h](hDThe i915 driver allows user space to create a context via the ioctl }(hjbhhhNhNubjb)}(h#`DRM_IOCTL_I915_GEM_CONTEXT_CREATE`h]h!DRM_IOCTL_I915_GEM_CONTEXT_CREATE}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jbhjbubhXl which is identified by a 32-bit integer. Such a context should be viewed by user-space as -loosely- analogous to the idea of a CPU process of an operating system. The i915 driver guarantees that commands issued to a fixed context are to be executed so that writes of a previously issued command are seen by reads of following commands. Actions issued between different contexts (even if from the same file descriptor) are NOT given that guarantee and the only way to synchronize across contexts (even from the same file descriptor) is through the use of fences. At least as far back as Gen4, also have that a context carries with it a GPU HW context; the HW context is essentially (most of at least) the state of a GPU. In addition to the ordering guarantees, the kernel will restore GPU state via HW context when commands are issued to a context, this saves user space the need to restore (most of at least) the GPU state at the start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use with the command.}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM1hjahhubh)}(hXThe GPU has its own memory management and address space. The kernel driver maintains the memory translation table for the GPU. For older GPUs (i.e. those before Gen8), there is a single global such translation table, a global Graphics Translation Table (GTT). For newer generation GPUs each context has its own translation table, called Per-Process Graphics Translation Table (PPGTT). Of important note, is that although PPGTT is named per-process it is actually per context. When user space submits a batchbuffer, the kernel walks the list of GEM buffer objects used by the batchbuffer and guarantees that not only is the memory of each such GEM buffer object resident but it is also present in the (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, then it is given an address. Two consequences of this are: the kernel needs to edit the batchbuffer submitted to write the correct value of the GPU address when a GEM BO is assigned a GPU address and the kernel might evict a different GEM BO from the (PP)GTT to make address room for another GEM BO. Consequently, the ioctls submitting a batchbuffer for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation.h]hXThe GPU has its own memory management and address space. The kernel driver maintains the memory translation table for the GPU. For older GPUs (i.e. those before Gen8), there is a single global such translation table, a global Graphics Translation Table (GTT). For newer generation GPUs each context has its own translation table, called Per-Process Graphics Translation Table (PPGTT). Of important note, is that although PPGTT is named per-process it is actually per context. When user space submits a batchbuffer, the kernel walks the list of GEM buffer objects used by the batchbuffer and guarantees that not only is the memory of each such GEM buffer object resident but it is also present in the (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, then it is given an address. Two consequences of this are: the kernel needs to edit the batchbuffer submitted to write the correct value of the GPU address when a GEM BO is assigned a GPU address and the kernel might evict a different GEM BO from the (PP)GTT to make address room for another GEM BO. Consequently, the ioctls submitting a batchbuffer for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhjahhubeh}(h]intel-gpu-basicsah ]h"]intel gpu basicsah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(hLocking Guidelinesh]hLocking Guidelines}(hj chhhNhNubah}(h]h ]h"]h$]h&]uh1hhj chhhhhMYubhnote)}(hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.h]h)}(hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.h]hThis is a description of how the locking should be after refactoring is done. Does not necessarily reflect what the locking looks like while WIP.}(hj!chhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hjcubah}(h]h ]h"]h$]h&]uh1jchj chhhhhNubj:)}(hhh](j:)}(hqAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed. h]h)}(hpAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed.h]hpAll locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed.}(hjWhile holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowed * Enforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad. h](h)}(hjWhile holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowedh]hjWhile holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowed}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjcubj)}(h* Enforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad. h]j:)}(hhh]j:)}(hEnforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad. h]h)}(hEnforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad.h]hEnforce this by priming lockdep (with fs_reclaim). If we allocate memory while holding these looks we get a rehash of the shrinker vs. struct_mutex saga, and that would be real bad.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjcubah}(h]h ]h"]h$]h&]uh1j:hjcubah}(h]h ]h"]h$]h&]j[;juh1j:hhhMlhjcubah}(h]h ]h"]h$]h&]uh1jhhhMlhjcubeh}(h]h ]h"]h$]h&]uh1j:hj5chhhhhNubj:)}(hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations. h]h)}(hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations.h]hDo not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhjcubah}(h]h ]h"]h$]h&]uh1j:hj5chhhhhNubj:)}(h\The suggestion for lru/memory managers locks is that they are small enough to be spinlocks. h]h)}(h[The suggestion for lru/memory managers locks is that they are small enough to be spinlocks.h]h[The suggestion for lru/memory managers locks is that they are small enough to be spinlocks.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhjcubah}(h]h ]h"]h$]h&]uh1j:hj5chhhhhNubj:)}(h]All features need to come with exhaustive kernel selftests and/or IGT tests when appropriate h]h)}(h\All features need to come with exhaustive kernel selftests and/or IGT tests when appropriateh]h\All features need to come with exhaustive kernel selftests and/or IGT tests when appropriate}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhjcubah}(h]h ]h"]h$]h&]uh1j:hj5chhhhhNubj:)}(hXAll LMEM uAPI paths need to be fully restartable (_interruptible() for all locks/waits/sleeps) * Error handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases. * -EDEADLK handling with ww_mutex h](h)}(h^All LMEM uAPI paths need to be fully restartable (_interruptible() for all locks/waits/sleeps)h]h^All LMEM uAPI paths need to be fully restartable (_interruptible() for all locks/waits/sleeps)}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hj dubj)}(hX* Error handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases. * -EDEADLK handling with ww_mutex h]j:)}(hhh](j:)}(hError handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases. h]h)}(hError handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases.h]hError handling validation through signal injection. Still the best strategy we have for validating GEM uAPI corner cases. Must be excessively used in the IGT, and we need to check that we really have full path coverage of all error cases.}(hj(dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hj$dubah}(h]h ]h"]h$]h&]uh1j:hj!dubj:)}(h -EDEADLK handling with ww_mutex h]h)}(h-EDEADLK handling with ww_mutexh]h-EDEADLK handling with ww_mutex}(hj@dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjpages_pin_count does not protect against eviction. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]jb)}(hjgh]h Parameters}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jahjgubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjgubjx)}(hhh](j})}(h>``struct i915_address_space *vm`` address space to evict from h](j)}(h!``struct i915_address_space *vm``h]j)}(hjgh]hstruct i915_address_space *vm}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chK}hjgubj)}(hhh]h)}(haddress space to evict fromh]haddress space to evict from}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhK}hjhubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1j|hjhhK}hjgubj})}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hj2hh]hstruct i915_gem_ww_ctx *ww}(hj4hhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0hubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chK~hj,hubj)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hjKhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhhK~hjHhubah}(h]h ]h"]h$]h&]uh1jhj,hubeh}(h]h ]h"]h$]h&]uh1j|hjGhhK~hjgubj})}(h0``u64 min_size`` size of the desired free space h](j)}(h``u64 min_size``h]j)}(hjkhh]h u64 min_size}(hjmhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjihubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjehubj)}(hhh]h)}(hsize of the desired free spaceh]hsize of the desired free space}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhKhjhubah}(h]h ]h"]h$]h&]uh1jhjehubeh}(h]h ]h"]h$]h&]uh1j|hjhhKhjgubj})}(hA``u64 alignment`` alignment constraint of the desired free space h](j)}(h``u64 alignment``h]j)}(hjhh]h u64 alignment}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjhubj)}(hhh]h)}(h.alignment constraint of the desired free spaceh]h.alignment constraint of the desired free space}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhKhjhubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1j|hjhhKhjgubj})}(h4``unsigned long color`` color for the desired space h](j)}(h``unsigned long color``h]j)}(hjhh]hunsigned long color}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjhubj)}(hhh]h)}(hcolor for the desired spaceh]hcolor for the desired space}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhKhjhubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1j|hjhhKhjgubj})}(hI``u64 start`` start (inclusive) of the range from which to evict objects h](j)}(h ``u64 start``h]j)}(hjih]h u64 start}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjiubj)}(hhh]h)}(h:start (inclusive) of the range from which to evict objectsh]h:start (inclusive) of the range from which to evict objects}(hj/ihhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+ihKhj,iubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1j|hj+ihKhjgubj})}(hE``u64 end`` end (exclusive) of the range from which to evict objects h](j)}(h ``u64 end``h]j)}(hjOih]hu64 end}(hjQihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMiubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjIiubj)}(hhh]h)}(h8end (exclusive) of the range from which to evict objectsh]h8end (exclusive) of the range from which to evict objects}(hjhihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdihKhjeiubah}(h]h ]h"]h$]h&]uh1jhjIiubeh}(h]h ]h"]h$]h&]uh1j|hjdihKhjgubj})}(hF``unsigned flags`` additional flags to control the eviction algorithm h](j)}(h``unsigned flags``h]j)}(hjih]hunsigned flags}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjiubj)}(hhh]h)}(h2additional flags to control the eviction algorithmh]h2additional flags to control the eviction algorithm}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKhjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1j|hjihKhjgubeh}(h]h ]h"]h$]h&]uh1jwhjgubh)}(h**Description**h]jb)}(hjih]h Description}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jahjiubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjgubh)}(hThis function will try to evict vmas until a free space satisfying the requirements is found. Callers must check first whether any such hole exists already before calling this function.h]hThis function will try to evict vmas until a free space satisfying the requirements is found. Callers must check first whether any such hole exists already before calling this function.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjgubh)}(h5This function is used by the object/vma binding code.h]h5This function is used by the object/vma binding code.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjgubh)}(hSince this function is only used to free up virtual address space it only ignores pinned vmas, and not object where the backing storage itself is pinned. Hence obj->pages_pin_count does not protect against eviction.h]hSince this function is only used to free up virtual address space it only ignores pinned vmas, and not object where the backing storage itself is pinned. Hence obj->pages_pin_count does not protect against eviction.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjgubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chKhjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjdhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$i915_gem_evict_for_node (C function)c.i915_gem_evict_for_nodehNtauh1jhjdhhhNhNubj')}(hhh](j,)}(hint i915_gem_evict_for_node (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h]j2)}(hint i915_gem_evict_for_node(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h](j)}(hinth]hint}(hj5jhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1jhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM=ubji)}(h h]h }(hjDjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj1jhhhjCjhM=ubjz)}(hi915_gem_evict_for_nodeh]j;)}(hi915_gem_evict_for_nodeh]hi915_gem_evict_for_node}(hjVjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj1jhhhjCjhM=ubj)}(hk(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *target, unsigned int flags)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hjrjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnjubji)}(h h]h }(hjjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnjubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjjmodnameN classnameNjXj[)}j^]ja)}jTjXjsbc.i915_gem_evict_for_nodeasbuh1hhjnjubji)}(h h]h }(hjjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnjubj)}(hjh]h*}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnjubj;)}(hvmh]hvm}(hjjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjjubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubji)}(h h]h }(hjjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjjubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjkmodnameN classnameNjXj[)}j^]jjc.i915_gem_evict_for_nodeasbuh1hhjjubji)}(h h]h }(hj khhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjjubj)}(hjh]h*}(hj.khhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj;)}(hwwh]hww}(hj;khhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjjubj)}(hstruct drm_mm_node *targeth](j)}(hjh]hstruct}(hjTkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPkubji)}(h h]h }(hjakhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjPkubh)}(hhh]j;)}(h drm_mm_nodeh]h drm_mm_node}(hjrkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjokubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjtkmodnameN classnameNjXj[)}j^]jjc.i915_gem_evict_for_nodeasbuh1hhjPkubji)}(h h]h }(hjkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjPkubj)}(hjh]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPkubj;)}(htargeth]htarget}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjPkubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjjubj)}(hunsigned int flagsh](j)}(hunsignedh]hunsigned}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubji)}(h h]h }(hjkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjkubj)}(hinth]hint}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubji)}(h h]h }(hjkhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjkubj;)}(hflagsh]hflags}(hjkhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjkubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjjjubeh}(h]h ]h"]h$]h&]jjuh1jhj1jhhhjCjhM=ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj-jhhhjCjhM=ubah}(h]j(jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjCjhM=hj*jhhubj1)}(hhh]h)}(h-Evict vmas to make room for binding a new oneh]h-Evict vmas to make room for binding a new one}(hj&lhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM=hj#lhhubah}(h]h ]h"]h$]h&]uh1j0hj*jhhhjCjhM=ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj>ljSj>ljTjUjVuh1j&hhhjdhNhNubjX)}(hX**Parameters** ``struct i915_address_space *vm`` address space to evict from ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *target`` range (and color) to evict for ``unsigned int flags`` additional flags to control the eviction algorithm **Description** This function will try to evict vmas that overlap the target node. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]jb)}(hjHlh]h Parameters}(hjJlhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFlubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMAhjBlubjx)}(hhh](j})}(h>``struct i915_address_space *vm`` address space to evict from h](j)}(h!``struct i915_address_space *vm``h]j)}(hjglh]hstruct i915_address_space *vm}(hjilhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjelubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM>hjalubj)}(hhh]h)}(haddress space to evict fromh]haddress space to evict from}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|lhM>hj}lubah}(h]h ]h"]h$]h&]uh1jhjalubeh}(h]h ]h"]h$]h&]uh1j|hj|lhM>hj^lubj})}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hjlh]hstruct i915_gem_ww_ctx *ww}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM?hjlubj)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhM?hjlubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1j|hjlhM?hj^lubj})}(h>``struct drm_mm_node *target`` range (and color) to evict for h](j)}(h``struct drm_mm_node *target``h]j)}(hjlh]hstruct drm_mm_node *target}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chM@hjlubj)}(hhh]h)}(hrange (and color) to evict forh]hrange (and color) to evict for}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhM@hjlubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1j|hjlhM@hj^lubj})}(hJ``unsigned int flags`` additional flags to control the eviction algorithm h](j)}(h``unsigned int flags``h]j)}(hjmh]hunsigned int flags}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMAhj mubj)}(hhh]h)}(h2additional flags to control the eviction algorithmh]h2additional flags to control the eviction algorithm}(hj+mhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'mhMAhj(mubah}(h]h ]h"]h$]h&]uh1jhj mubeh}(h]h ]h"]h$]h&]uh1j|hj'mhMAhj^lubeh}(h]h ]h"]h$]h&]uh1jwhjBlubh)}(h**Description**h]jb)}(hjMmh]h Description}(hjOmhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjKmubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMChjBlubh)}(hBThis function will try to evict vmas that overlap the target node.h]hBThis function will try to evict vmas that overlap the target node.}(hjcmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMChjBlubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hjrmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMEhjBlubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjdhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_evict_vm (C function)c.i915_gem_evict_vmhNtauh1jhjdhhhNhNubj')}(hhh](j,)}(hwint i915_gem_evict_vm (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h]j2)}(hvint i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h](j)}(hinth]hint}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjmhhhjmhMubjz)}(hi915_gem_evict_vmh]j;)}(hi915_gem_evict_vmh]hi915_gem_evict_vm}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjmhhhjmhMubj)}(ha(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_i915_gem_object **busy_bo)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubji)}(h h]h }(hjmhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjmubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjmhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmmodnameN classnameNjXj[)}j^]ja)}jTjmsbc.i915_gem_evict_vmasbuh1hhjmubji)}(h h]h }(hjnhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjmubj)}(hjh]h*}(hj*nhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj;)}(hvmh]hvm}(hj7nhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjmubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hjPnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLnubji)}(h h]h }(hj]nhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjLnubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjnnhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjknubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjpnmodnameN classnameNjXj[)}j^]jnc.i915_gem_evict_vmasbuh1hhjLnubji)}(h h]h }(hjnhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjLnubj)}(hjh]h*}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLnubj;)}(hwwh]hww}(hjnhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjLnubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjmubj)}(h$struct drm_i915_gem_object **busy_boh](j)}(hjh]hstruct}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubji)}(h h]h }(hjnhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjnhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjnmodnameN classnameNjXj[)}j^]jnc.i915_gem_evict_vmasbuh1hhjnubji)}(h h]h }(hjnhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjnubj)}(hjh]h*}(hj ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(hjh]h*}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj;)}(hbusy_boh]hbusy_bo}(hj$ohhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjnubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjmubeh}(h]h ]h"]h$]h&]jjuh1jhjmhhhjmhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjmhhhjmhMubah}(h]jmah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjmhMhjmhhubj1)}(hhh]h)}(hEvict all idle vmas from a vmh]hEvict all idle vmas from a vm}(hjNohhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjKohhubah}(h]h ]h"]h$]h&]uh1j0hjmhhhjmhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjfojSjfojTjUjVuh1j&hhhjdhNhNubjX)}(hXm**Parameters** ``struct i915_address_space *vm`` Address space to cleanse ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well. ``struct drm_i915_gem_object **busy_bo`` Optional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object. **Description** This function evicts all vmas from a vm. This is used by the execbuf code as a last-ditch effort to defragment the address space. To clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h](h)}(h**Parameters**h]jb)}(hjpoh]h Parameters}(hjrohhhNhNubah}(h]h ]h"]h$]h&]uh1jahjnoubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjjoubjx)}(hhh](j})}(h;``struct i915_address_space *vm`` Address space to cleanse h](j)}(h!``struct i915_address_space *vm``h]j)}(hjoh]hstruct i915_address_space *vm}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubj)}(hhh]h)}(hAddress space to cleanseh]hAddress space to cleanse}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohMhjoubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1j|hjohMhjoubj})}(h``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hjoh]hstruct i915_gem_ww_ctx *ww}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubj)}(hhh]h)}(hxAn optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma's locked by the ww as well.h]hzAn optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm will be able to evict vma’s locked by the ww as well.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1j|hjohMhjoubj})}(hX|``struct drm_i915_gem_object **busy_bo`` Optional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object. h](j)}(h(``struct drm_i915_gem_object **busy_bo``h]j)}(hjph]h$struct drm_i915_gem_object **busy_bo}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjoubj)}(hhh]h)}(hXROptional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then **busy_bo** will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object.h](hOptional pointer to struct drm_i915_gem_object. If not NULL, then in the event i915_gem_evict_vm() is unable to trylock an object for eviction, then }(hjphhhNhNubjb)}(h **busy_bo**h]hbusy_bo}(hj#phhhNhNubah}(h]h ]h"]h$]h&]uh1jahjpubh will point to it. -EBUSY is also returned. The caller must drop the vm->mutex, before trying again to acquire the contended lock. The caller also owns a reference to the object.}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjpubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1j|hjphMhjoubeh}(h]h ]h"]h$]h&]uh1jwhjjoubh)}(h**Description**h]jb)}(hjPph]h Description}(hjRphhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNpubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjjoubh)}(h(This function evicts all vmas from a vm.h]h(This function evicts all vmas from a vm.}(hjfphhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjjoubh)}(hXThis is used by the execbuf code as a last-ditch effort to defragment the address space.h]hXThis is used by the execbuf code as a last-ditch effort to defragment the address space.}(hjuphhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjjoubh)}(hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.h]hfTo clarify: This is for freeing up virtual address space, not for freeing memory in e.g. the shrinker.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:405: ./drivers/gpu/drm/i915/i915_gem_evict.chMhjjoubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjdhhhNhNubeh}(h]buffer-object-evictionah ]h"]buffer object evictionah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(hBuffer Object Memory Shrinkingh]hBuffer Object Memory Shrinking}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphhhhhMubh)}(hXThis section documents the interface function for shrinking memory usage of buffer object caches. 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Note that this is mostly orthogonal to evicting buffer objects, which has the goal to make space in gpu virtual address spaces.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjphhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_shrink (C function)c.i915_gem_shrinkhNtauh1jhjphhhNhNubj')}(hhh](j,)}(hunsigned long i915_gem_shrink (struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h]j2)}(hunsigned long i915_gem_shrink(struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h](j)}(hunsignedh]hunsigned}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjphhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKLubji)}(h h]h }(hjphhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjphhhjphKLubj)}(hlongh]hlong}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjphhhjphKLubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjphhhjphKLubjz)}(hi915_gem_shrinkh]j;)}(hi915_gem_shrinkh]hi915_gem_shrink}(hjqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjqubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjphhhjphKLubj)}(h(struct i915_gem_ww_ctx *ww, struct drm_i915_private *i915, unsigned long target, unsigned long *nr_scanned, unsigned int shrink)h](j)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hj3qhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/qubji)}(h h]h }(hj@qhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/qubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjQqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNqubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjSqmodnameN classnameNjXj[)}j^]ja)}jTjqsbc.i915_gem_shrinkasbuh1hhj/qubji)}(h h]h }(hjqqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj/qubj)}(hjh]h*}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/qubj;)}(hwwh]hww}(hjqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj/qubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+qubj)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjqubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjqmodnameN classnameNjXj[)}j^]jmqc.i915_gem_shrinkasbuh1hhjqubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubj)}(hjh]h*}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj;)}(hi915h]hi915}(hjqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjqubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+qubj)}(hunsigned long targeth](j)}(hunsignedh]hunsigned}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubji)}(h h]h }(hj#rhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrubj)}(hlongh]hlong}(hj1rhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubji)}(h h]h }(hj?rhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrubj;)}(htargeth]htarget}(hjMrhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjrubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+qubj)}(hunsigned long *nr_scannedh](j)}(hunsignedh]hunsigned}(hjfrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbrubji)}(h h]h }(hjtrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbrubj)}(hlongh]hlong}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbrubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbrubj)}(hjh]h*}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbrubj;)}(h nr_scannedh]h nr_scanned}(hjrhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjbrubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+qubj)}(hunsigned int shrinkh](j)}(hunsignedh]hunsigned}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrubj)}(hinth]hint}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrubj;)}(hshrinkh]hshrink}(hjrhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjrubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj+qubeh}(h]h ]h"]h$]h&]jjuh1jhjphhhjphKLubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjphhhjphKLubah}(h]jpah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjphKLhjphhubj1)}(hhh]h)}(hShrink buffer object cachesh]hShrink buffer object caches}(hj&shhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKLhj#shhubah}(h]h ]h"]h$]h&]uh1j0hjphhhjphKLubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj>sjSj>sjTjUjVuh1j&hhhjphNhNubjX)}(hX **Parameters** ``struct i915_gem_ww_ctx *ww`` i915 gem ww acquire ctx, or NULL ``struct drm_i915_private *i915`` i915 device ``unsigned long target`` amount of memory to make available, in pages ``unsigned long *nr_scanned`` optional output for number of pages scanned (incremental) ``unsigned int shrink`` control flags for selecting cache types **Description** This function is the main interface to the shrinker. It will try to release up to **target** pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with **flags**. This is e.g. useful when purgeable objects should be removed from caches preferentially. Note that it's not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all(). Also note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object. **Return** The number of pages of backing storage actually released.h](h)}(h**Parameters**h]jb)}(hjHsh]h Parameters}(hjJshhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFsubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKPhjBsubjx)}(hhh](j})}(h@``struct i915_gem_ww_ctx *ww`` i915 gem ww acquire ctx, or NULL h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hjgsh]hstruct i915_gem_ww_ctx *ww}(hjishhhNhNubah}(h]h ]h"]h$]h&]uh1jhjesubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKMhjasubj)}(hhh]h)}(h i915 gem ww acquire ctx, or NULLh]h i915 gem ww acquire ctx, or NULL}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|shKMhj}subah}(h]h ]h"]h$]h&]uh1jhjasubeh}(h]h ]h"]h$]h&]uh1j|hj|shKMhj^subj})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjsh]hstruct drm_i915_private *i915}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKNhjsubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshKNhjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1j|hjshKNhj^subj})}(hF``unsigned long target`` amount of memory to make available, in pages h](j)}(h``unsigned long target``h]j)}(hjsh]hunsigned long target}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKOhjsubj)}(hhh]h)}(h,amount of memory to make available, in pagesh]h,amount of memory to make available, in pages}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshKOhjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1j|hjshKOhj^subj})}(hX``unsigned long *nr_scanned`` optional output for number of pages scanned (incremental) h](j)}(h``unsigned long *nr_scanned``h]j)}(hjth]hunsigned long *nr_scanned}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKPhj tubj)}(hhh]h)}(h9optional output for number of pages scanned (incremental)h]h9optional output for number of pages scanned (incremental)}(hj+thhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'thKPhj(tubah}(h]h ]h"]h$]h&]uh1jhj tubeh}(h]h ]h"]h$]h&]uh1j|hj'thKPhj^subj})}(h@``unsigned int shrink`` control flags for selecting cache types h](j)}(h``unsigned int shrink``h]j)}(hjKth]hunsigned int shrink}(hjMthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjItubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKQhjEtubj)}(hhh]h)}(h'control flags for selecting cache typesh]h'control flags for selecting cache types}(hjdthhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`thKQhjatubah}(h]h ]h"]h$]h&]uh1jhjEtubeh}(h]h ]h"]h$]h&]uh1j|hj`thKQhj^subeh}(h]h ]h"]h$]h&]uh1jwhjBsubh)}(h**Description**h]jb)}(hjth]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKShjBsubh)}(hX,This function is the main interface to the shrinker. It will try to release up to **target** pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with **flags**. This is e.g. useful when purgeable objects should be removed from caches preferentially.h](hRThis function is the main interface to the shrinker. It will try to release up to }(hjthhhNhNubjb)}(h **target**h]htarget}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubhm pages of main memory backing storage from buffer objects. Selection of the specific caches can be done with }(hjthhhNhNubjb)}(h **flags**h]hflags}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubhZ. This is e.g. useful when purgeable objects should be removed from caches preferentially.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKShjBsubh)}(hX~Note that it's not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all().h]hXNote that it’s not guaranteed that released amount is actually available as free system memory - the pages might still be in-used to due to other reasons (like cpu mmaps) or the mm core has reused them before we could grab them. Therefore code that needs to explicitly shrink buffer objects caches (e.g. to avoid deadlocks in memory reclaim) must fall back to i915_gem_shrink_all().}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKXhjBsubh)}(hAlso note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object.h]hAlso note that any kind of pinning (both per-vma address space pins and backing storage pins at the buffer object level) result in the shrinker code having to skip the object.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chK^hjBsubh)}(h **Return**h]jb)}(hjth]hReturn}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjtubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKbhjBsubh)}(h9The number of pages of backing storage actually released.h]h9The number of pages of backing storage actually released.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chKbhjBsubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_shrink_all (C function)c.i915_gem_shrink_allhNtauh1jhjphhhNhNubj')}(hhh](j,)}(hAunsigned long i915_gem_shrink_all (struct drm_i915_private *i915)h]j2)}(h@unsigned long i915_gem_shrink_all(struct drm_i915_private *i915)h](j)}(hunsignedh]hunsigned}(hj4uhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0uhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMubji)}(h h]h }(hjCuhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj0uhhhjBuhMubj)}(hlongh]hlong}(hjQuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0uhhhjBuhMubji)}(h h]h }(hj_uhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj0uhhhjBuhMubjz)}(hi915_gem_shrink_allh]j;)}(hi915_gem_shrink_allh]hi915_gem_shrink_all}(hjquhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmuubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj0uhhhjBuhMubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubji)}(h h]h }(hjuhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjuhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjuubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjumodnameN classnameNjXj[)}j^]ja)}jTjsusbc.i915_gem_shrink_allasbuh1hhjuubji)}(h h]h }(hjuhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjuubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubj;)}(hi915h]hi915}(hjuhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjuubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjuubah}(h]h ]h"]h$]h&]jjuh1jhj0uhhhjBuhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj,uhhhjBuhMubah}(h]j'uah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjBuhMhj)uhhubj1)}(hhh]h)}(h&Shrink buffer object caches completelyh]h&Shrink buffer object caches completely}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj vhhubah}(h]h ]h"]h$]h&]uh1j0hj)uhhhjBuhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj(vjSj(vjTjUjVuh1j&hhhjphNhNubjX)}(hX**Parameters** ``struct drm_i915_private *i915`` i915 device **Description** This is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects. This should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out. **Return** The number of pages of backing storage actually released.h](h)}(h**Parameters**h]jb)}(hj2vh]h Parameters}(hj4vhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj0vubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj,vubjx)}(hhh]j})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjQvh]hstruct drm_i915_private *i915}(hjSvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOvubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhjKvubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hjjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfvhMhjgvubah}(h]h ]h"]h$]h&]uh1jhjKvubeh}(h]h ]h"]h$]h&]uh1j|hjfvhMhjHvubah}(h]h ]h"]h$]h&]uh1jwhj,vubh)}(h**Description**h]jb)}(hjvh]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjvubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj,vubh)}(hThis is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects.h]hThis is a simple wrapper around i915_gem_shrink() to aggressively shrink all caches completely. It also first waits for and retires all outstanding requests to also be able to release backing storage for active objects.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj,vubh)}(hThis should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out.h]hThis should only be used in code to intentionally quiescent the gpu or as a last-ditch effort when memory seems to have run out.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM hj,vubh)}(h **Return**h]jb)}(hjvh]hReturn}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjvubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj,vubh)}(h9The number of pages of backing storage actually released.h]h9The number of pages of backing storage actually released.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMhj,vubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j".i915_gem_object_make_unshrinkable (C function)#c.i915_gem_object_make_unshrinkablehNtauh1jhjphhhNhNubj')}(hhh](j,)}(hHvoid i915_gem_object_make_unshrinkable (struct drm_i915_gem_object *obj)h]j2)}(hGvoid i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj)h](j)}(hvoidh]hvoid}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMubji)}(h h]h }(hjwhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjwhhhjwhMubjz)}(h!i915_gem_object_make_unshrinkableh]j;)}(h!i915_gem_object_make_unshrinkableh]h!i915_gem_object_make_unshrinkable}(hj(whhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$wubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjwhhhjwhMubj)}(h!(struct drm_i915_gem_object *obj)h]j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hjDwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@wubji)}(h h]h }(hjQwhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@wubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjbwhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_wubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjdwmodnameN classnameNjXj[)}j^]ja)}jTj*wsb#c.i915_gem_object_make_unshrinkableasbuh1hhj@wubji)}(h h]h }(hjwhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@wubj)}(hjh]h*}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@wubj;)}(hobjh]hobj}(hjwhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@wubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjzubah}(h]h ]h"]h$]h&]jjuh1jhjzhhhjzhM%ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjzhhhjzhM%ubah}(h]jyah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjzhM%hjyhhubj1)}(hhh]h)}(hyMove the object to the tail of the purgeable list. Objects on this list might be swapped out. Used with DONTNEED objects.h]hyMove the object to the tail of the purgeable list. Objects on this list might be swapped out. Used with DONTNEED objects.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM%hjzhhubah}(h]h ]h"]h$]h&]uh1j0hjyhhhjzhM%ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjzjSjzjTjUjVuh1j&hhhjphNhNubjX)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** DO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h](h)}(h**Parameters**h]jb)}(hjzh]h Parameters}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjzubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM)hjzubjx)}(hhh]j})}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hj {h]hstruct drm_i915_gem_object *obj}(hj {hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM(hj{ubj)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hj#{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hM(hj {ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j|hj{hM(hj{ubah}(h]h ]h"]h$]h&]uh1jwhjzubh)}(h**Description**h]jb)}(hjE{h]h Description}(hjG{hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjC{ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM*hjzubh)}(hDO NOT USE. This is intended to be called on very special objects that don't yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.h]hDO NOT USE. This is intended to be called on very special objects that don’t yet have mm.pages, but are guaranteed to have potentially reclaimable pages underneath.}(hj[{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM*hjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",i915_gem_object_make_shrinkable (C function)!c.i915_gem_object_make_shrinkablehNtauh1jhjphhhNhNubj')}(hhh](j,)}(hFvoid i915_gem_object_make_shrinkable (struct drm_i915_gem_object *obj)h]j2)}(hEvoid i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj)h](j)}(hvoidh]hvoid}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM5ubji)}(h h]h }(hj{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{hhhj{hM5ubjz)}(hi915_gem_object_make_shrinkableh]j;)}(hi915_gem_object_make_shrinkableh]hi915_gem_object_make_shrinkable}(hj{hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj{hhhj{hM5ubj)}(h!(struct drm_i915_gem_object *obj)h]j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubji)}(h h]h }(hj{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{ubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hj{hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj{modnameN classnameNjXj[)}j^]ja)}jTj{sb!c.i915_gem_object_make_shrinkableasbuh1hhj{ubji)}(h h]h }(hj|hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj{ubj)}(hjh]h*}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj;)}(hobjh]hobj}(hj |hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj{ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj{ubah}(h]h ]h"]h$]h&]jjuh1jhj{hhhj{hM5ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj{hhhj{hM5ubah}(h]j}{ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj{hM5hj{hhubj1)}(hhh]h)}(hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.h]hzMove the object to the tail of the shrinkable list. Objects on this list might be swapped out. Used with WILLNEED objects.}(hjJ|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM5hjG|hhubah}(h]h ]h"]h$]h&]uh1j0hj{hhhj{hM5ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjb|jSjb|jTjUjVuh1j&hhhjphNhNubjX)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** MUST only be called on objects which have backing pages. MUST be balanced with previous call to i915_gem_object_make_unshrinkable().h](h)}(h**Parameters**h]jb)}(hjl|h]h Parameters}(hjn|hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjj|ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM9hjf|ubjx)}(hhh]j})}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hj|h]hstruct drm_i915_gem_object *obj}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM8hj|ubj)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hM8hj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1j|hj|hM8hj|ubah}(h]h ]h"]h$]h&]uh1jwhjf|ubh)}(h**Description**h]jb)}(hj|h]h Description}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj|ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM:hjf|ubh)}(h8MUST only be called on objects which have backing pages.h]h8MUST only be called on objects which have backing pages.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM:hjf|ubh)}(hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().h]hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chM<hjf|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjphhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"+i915_gem_object_make_purgeable (C function) c.i915_gem_object_make_purgeablehNtauh1jhjphhhNhNubj')}(hhh](j,)}(hEvoid i915_gem_object_make_purgeable (struct drm_i915_gem_object *obj)h]j2)}(hDvoid i915_gem_object_make_purgeable(struct drm_i915_gem_object *obj)h](j)}(hvoidh]hvoid}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMEubji)}(h h]h }(hj)}hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj}hhhj(}hMEubjz)}(hi915_gem_object_make_purgeableh]j;)}(hi915_gem_object_make_purgeableh]hi915_gem_object_make_purgeable}(hj;}hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7}ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj}hhhj(}hMEubj)}(h!(struct drm_i915_gem_object *obj)h]j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hjW}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjS}ubji)}(h h]h }(hjd}hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjS}ubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hju}hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjr}ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjw}modnameN classnameNjXj[)}j^]ja)}jTj=}sb c.i915_gem_object_make_purgeableasbuh1hhjS}ubji)}(h h]h }(hj}hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjS}ubj)}(hjh]h*}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjS}ubj;)}(hobjh]hobj}(hj}hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjS}ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjO}ubah}(h]h ]h"]h$]h&]jjuh1jhj}hhhj(}hMEubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj}hhhj(}hMEubah}(h]j }ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj(}hMEhj}hhubj1)}(hhh]h)}(hMove the object to the tail of the purgeable list. Used with DONTNEED objects. Unlike with shrinkable objects, the shrinker will attempt to discard the backing pages, instead of trying to swap them out.h]hMove the object to the tail of the purgeable list. Used with DONTNEED objects. Unlike with shrinkable objects, the shrinker will attempt to discard the backing pages, instead of trying to swap them out.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMEhj}hhubah}(h]h ]h"]h$]h&]uh1j0hj}hhhj(}hMEubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj}jSj}jTjUjVuh1j&hhhjphNhNubjX)}(h**Parameters** ``struct drm_i915_gem_object *obj`` The GEM object. **Description** MUST only be called on objects which have backing pages. MUST be balanced with previous call to i915_gem_object_make_unshrinkable().h](h)}(h**Parameters**h]jb)}(hj}h]h Parameters}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj}ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMIhj}ubjx)}(hhh]j})}(h4``struct drm_i915_gem_object *obj`` The GEM object. h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hj~h]hstruct drm_i915_gem_object *obj}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMIhj~ubj)}(hhh]h)}(hThe GEM object.h]hThe GEM object.}(hj4~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0~hMIhj1~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1j|hj0~hMIhj~ubah}(h]h ]h"]h$]h&]uh1jwhj}ubh)}(h**Description**h]jb)}(hjV~h]h Description}(hjX~hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjT~ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMKhj}ubh)}(h8MUST only be called on objects which have backing pages.h]h8MUST only be called on objects which have backing pages.}(hjl~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMKhj}ubh)}(hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().h]hKMUST be balanced with previous call to i915_gem_object_make_unshrinkable().}(hj{~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:416: ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.chMMhj}ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjphhhNhNubeh}(h]buffer-object-memory-shrinkingah ]h"]buffer object memory shrinkingah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(hBatchbuffer Parsingh]hBatchbuffer Parsing}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhhhMubh)}(hXMotivation: Certain OpenGL features (e.g. transform feedback, performance monitoring) require userspace code to submit batches containing commands such as MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some generations of the hardware will noop these commands in "unsecure" batches (which includes all userspace batches submitted via i915) even though the commands may be safe and represent the intended programming model of the device.h]hXMotivation: Certain OpenGL features (e.g. transform feedback, performance monitoring) require userspace code to submit batches containing commands such as MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some generations of the hardware will noop these commands in “unsecure” batches (which includes all userspace batches submitted via i915) even though the commands may be safe and represent the intended programming model of the device.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK+hj~hhubh)}(hX6The software command parser is similar in operation to the command parsing done in hardware for unsecure batches. However, the software parser allows some operations that would be noop'd by hardware, if the parser determines the operation is safe, and submits the batch as "secure" to prevent hardware parsing.h]hX<The software command parser is similar in operation to the command parsing done in hardware for unsecure batches. However, the software parser allows some operations that would be noop’d by hardware, if the parser determines the operation is safe, and submits the batch as “secure” to prevent hardware parsing.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK4hj~hhubh)}(hThreats: At a high level, the hardware (and software) checks attempt to prevent granting userspace undue privileges. There are three categories of privilege.h]hThreats: At a high level, the hardware (and software) checks attempt to prevent granting userspace undue privileges. There are three categories of privilege.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK:hj~hhubh)}(hFirst, commands which are explicitly defined as privileged or which should only be used by the kernel driver. The parser rejects such commandsh]hFirst, commands which are explicitly defined as privileged or which should only be used by the kernel driver. The parser rejects such commands}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK>hj~hhubh)}(hSecond, commands which access registers. To support correct/enhanced userspace functionality, particularly certain OpenGL extensions, the parser provides a whitelist of registers which userspace may safely accessh]hSecond, commands which access registers. To support correct/enhanced userspace functionality, particularly certain OpenGL extensions, the parser provides a whitelist of registers which userspace may safely access}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKAhj~hhubh)}(hsThird, commands which access privileged memory (i.e. GGTT, HWS page, etc). The parser always rejects such commands.h]hsThird, commands which access privileged memory (i.e. GGTT, HWS page, etc). The parser always rejects such commands.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKEhj~hhubh)}(hThe majority of the problematic commands fall in the MI_* range, with only a few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).h]hThe majority of the problematic commands fall in the MI_* range, with only a few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKHhj~hhubh)}(hImplementation: Each engine maintains tables of commands and registers which the parser uses in scanning batch buffers submitted to that engine.h]hImplementation: Each engine maintains tables of commands and registers which the parser uses in scanning batch buffers submitted to that engine.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKKhj~hhubh)}(hXSince the set of commands that the parser must check for is significantly smaller than the number of commands supported, the parser tables contain only those commands required by the parser. This generally works because command opcode ranges have standard command length encodings. So for commands that the parser does not need to check, it can easily skip them. This is implemented via a per-engine length decoding vfunc.h]hXSince the set of commands that the parser must check for is significantly smaller than the number of commands supported, the parser tables contain only those commands required by the parser. This generally works because command opcode ranges have standard command length encodings. So for commands that the parser does not need to check, it can easily skip them. This is implemented via a per-engine length decoding vfunc.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKOhj~hhubh)}(hXUnfortunately, there are a number of commands that do not follow the standard length encoding for their opcode range, primarily amongst the MI_* commands. To handle this, the parser provides a way to define explicit "skip" entries in the per-engine command tables.h]hX Unfortunately, there are a number of commands that do not follow the standard length encoding for their opcode range, primarily amongst the MI_* commands. To handle this, the parser provides a way to define explicit “skip” entries in the per-engine command tables.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chKVhj~hhubh)}(hOther command table entries map fairly directly to high level categories mentioned above: rejected, register whitelist. The parser implements a number of checks, including the privileged memory checks, via a general bitmasking mechanism.h]hOther command table entries map fairly directly to high level categories mentioned above: rejected, register whitelist. The parser implements a number of checks, including the privileged memory checks, via a general bitmasking mechanism.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:422: ./drivers/gpu/drm/i915/i915_cmd_parser.chK[hj~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j")intel_engine_init_cmd_parser (C function)c.intel_engine_init_cmd_parserhNtauh1jhj~hhhNhNubj')}(hhh](j,)}(hAint intel_engine_init_cmd_parser (struct intel_engine_cs *engine)h]j2)}(h@int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)h](j)}(hinth]hint}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMubji)}(h h]h }(hjwhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjdhhhjvhMubjz)}(hintel_engine_init_cmd_parserh]j;)}(hintel_engine_init_cmd_parserh]hintel_engine_init_cmd_parser}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjdhhhjvhMubj)}(h (struct intel_engine_cs *engine)h]j)}(hstruct intel_engine_cs *engineh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_engine_csh]hintel_engine_cs}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_engine_init_cmd_parserasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hengineh]hengine}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjdhhhjvhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj`hhhjvhMubah}(h]j[ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjvhMhj]hhubj1)}(hhh]h)}(h+set cmd parser related fields for an engineh]h+set cmd parser related fields for an engine}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhj%hhubah}(h]h ]h"]h$]h&]uh1j0hj]hhhjvhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj@jSj@jTjUjVuh1j&hhhj~hNhNubjX)}(hX**Parameters** ``struct intel_engine_cs *engine`` the engine to initialize **Description** Optionally initializes fields related to batch buffer command parsing in the struct intel_engine_cs based on whether the platform requires software command parsing.h](h)}(h**Parameters**h]jb)}(hjJh]h Parameters}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjHubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjDubjx)}(hhh]j})}(h<``struct intel_engine_cs *engine`` the engine to initialize h](j)}(h"``struct intel_engine_cs *engine``h]j)}(hjih]hstruct intel_engine_cs *engine}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjcubj)}(hhh]h)}(hthe engine to initializeh]hthe engine to initialize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hMhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1j|hj~hMhj`ubah}(h]h ]h"]h$]h&]uh1jwhjDubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjDubh)}(hOptionally initializes fields related to batch buffer command parsing in the struct intel_engine_cs based on whether the platform requires software command parsing.h]hOptionally initializes fields related to batch buffer command parsing in the struct intel_engine_cs based on whether the platform requires software command parsing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhjDubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j",intel_engine_cleanup_cmd_parser (C function)!c.intel_engine_cleanup_cmd_parserhNtauh1jhj~hhhNhNubj')}(hhh](j,)}(hEvoid intel_engine_cleanup_cmd_parser (struct intel_engine_cs *engine)h]j2)}(hDvoid intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM&ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM&ubjz)}(hintel_engine_cleanup_cmd_parserh]j;)}(hintel_engine_cleanup_cmd_parserh]hintel_engine_cleanup_cmd_parser}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM&ubj)}(h (struct intel_engine_cs *engine)h]j)}(hstruct intel_engine_cs *engineh](j)}(hjh]hstruct}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubji)}(h h]h }(hj3hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj"ubh)}(hhh]j;)}(hintel_engine_csh]hintel_engine_cs}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjFmodnameN classnameNjXj[)}j^]ja)}jTj sb!c.intel_engine_cleanup_cmd_parserasbuh1hhj"ubji)}(h h]h }(hjdhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj"ubj)}(hjh]h*}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj;)}(hengineh]hengine}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM&ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM&ubah}(h]j܀ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM&hjހhhubj1)}(hhh]h)}(h"clean up cmd parser related fieldsh]h"clean up cmd parser related fields}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM&hjhhubah}(h]h ]h"]h$]h&]uh1j0hjހhhhjhM&ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj~hNhNubjX)}(h**Parameters** ``struct intel_engine_cs *engine`` the engine to clean up **Description** Releases any resources related to command parsing that may have been initialized for the specified engine.h](h)}(h**Parameters**h]jb)}(hjˁh]h Parameters}(hj́hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjɁubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM*hjŁubjx)}(hhh]j})}(h:``struct intel_engine_cs *engine`` the engine to clean up h](j)}(h"``struct intel_engine_cs *engine``h]j)}(hjh]hstruct intel_engine_cs *engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM'hjubj)}(hhh]h)}(hthe engine to clean uph]hthe engine to clean up}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM'hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM'hjubah}(h]h ]h"]h$]h&]uh1jwhjŁubh)}(h**Description**h]jb)}(hj%h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj#ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM)hjŁubh)}(hjReleases any resources related to command parsing that may have been initialized for the specified engine.h]hjReleases any resources related to command parsing that may have been initialized for the specified engine.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM)hjŁubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$intel_engine_cmd_parser (C function)c.intel_engine_cmd_parserhNtauh1jhj~hhhNhNubj')}(hhh](j,)}(hint intel_engine_cmd_parser (struct intel_engine_cs *engine, struct i915_vma *batch, unsigned long batch_offset, unsigned long batch_length, struct i915_vma *shadow, bool trampoline)h]j2)}(hint intel_engine_cmd_parser(struct intel_engine_cs *engine, struct i915_vma *batch, unsigned long batch_offset, unsigned long batch_length, struct i915_vma *shadow, bool trampoline)h](j)}(hinth]hint}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMubji)}(h h]h }(hjyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjfhhhjxhMubjz)}(hintel_engine_cmd_parserh]j;)}(hintel_engine_cmd_parserh]hintel_engine_cmd_parser}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjfhhhjxhMubj)}(h(struct intel_engine_cs *engine, struct i915_vma *batch, unsigned long batch_offset, unsigned long batch_length, struct i915_vma *shadow, bool trampoline)h](j)}(hstruct intel_engine_cs *engineh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hintel_engine_csh]hintel_engine_cs}(hjłhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj‚ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjǂmodnameN classnameNjXj[)}j^]ja)}jTjsbc.intel_engine_cmd_parserasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hengineh]hengine}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct i915_vma *batchh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj&hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hj7hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj4ubah}(h]h ]h"]h$]h&]E refdomainjRreftypejT reftargetj9modnameN classnameNjXj[)}j^]jc.intel_engine_cmd_parserasbuh1hhjubji)}(h h]h }(hjUhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hbatchh]hbatch}(hjphhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned long batch_offseth](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h batch_offseth]h batch_offset}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned long batch_lengthh](j)}(hunsignedh]hunsigned}(hjڃhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjփubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjփubj)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjփubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjփubj;)}(h batch_lengthh]h batch_length}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjփubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct i915_vma *shadowh](j)}(hjh]hstruct}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'ubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjKmodnameN classnameNjXj[)}j^]jc.intel_engine_cmd_parserasbuh1hhj'ubji)}(h h]h }(hjghhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'ubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj;)}(hshadowh]hshadow}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hbool trampolineh](j)}(hjh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(h trampolineh]h trampoline}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjfhhhjxhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjbhhhjxhMubah}(h]j]ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjxhMhj_hhubj1)}(hhh]h)}(h-parse a batch buffer for privilege violationsh]h-parse a batch buffer for privilege violations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chMhj݄hhubah}(h]h ]h"]h$]h&]uh1j0hj_hhhjxhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj~hNhNubjX)}(hX**Parameters** ``struct intel_engine_cs *engine`` the engine on which the batch is to execute ``struct i915_vma *batch`` the batch buffer in question ``unsigned long batch_offset`` byte offset in the batch at which execution starts ``unsigned long batch_length`` length of the commands in batch_obj ``struct i915_vma *shadow`` validated copy of the batch buffer in question ``bool trampoline`` true if we need to trampoline into privileged execution **Description** Parses the specified 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userspace clients to determine what operations are permitted.h]hThe cmd parser maintains a simple increasing integer version number suitable for passing to userspace clients to determine what operations are permitted.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM0hjubh)}(h **Return**h]jb)}(hjHh]hReturn}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM3hjubh)}(h,the current version number of the cmd parserh]h,the current version number of the cmd parser}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:425: ./drivers/gpu/drm/i915/i915_cmd_parser.chM3hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj~hhhNhNubeh}(h]batchbuffer-parsingah ]h"]batchbuffer parsingah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(hUser Batchbuffer Executionh]hUser Batchbuffer Execution}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_engines (C struct)c.i915_gem_engineshNtauh1jhj|hhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhNubj')}(hhh](j,)}(hi915_gem_enginesh]j2)}(hstruct i915_gem_enginesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(hi915_gem_enginesh]j;)}(hjh]hi915_gem_engines}(hjLjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjÈubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(hA set of enginesh]hA set of engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK!hjhhubah}(h]h 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``fence``h]j)}(hjh]hfence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(h-Fence used for delayed destruction of enginesh]h-Fence used for delayed destruction of engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjMubj})}(h%``ctx`` i915_gem_context backpointer h](j)}(h``ctx``h]j)}(hj:h]hctx}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj4ubj)}(hhh]h)}(hi915_gem_context backpointerh]hi915_gem_context backpointer}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhKhjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1j|hjOhKhjMubj})}(h.``num_engines`` Number of engines in this set h](j)}(h``num_engines``h]j)}(hjsh]h num_engines}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjmubj)}(hhh]h)}(hNumber of engines in this seth]hNumber of engines in this set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjMubj})}(h``engines`` Array of enginesh](j)}(h ``engines``h]j)}(hjh]hengines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hArray of enginesh]hArray of engines}(hjŊhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjŠubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjMubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj|hhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_engines_iter (C struct)c.i915_gem_engines_iterhNtauh1jhj|hhhjhNubj')}(hhh](j,)}(hi915_gem_engines_iterh]j2)}(hstruct i915_gem_engines_iterh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(hi915_gem_engines_iterh]j;)}(hjh]hi915_gem_engines_iter}(hj&hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(h$Iterator for an i915_gem_engines seth]h$Iterator for an i915_gem_engines set}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK:hjEhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRj`jSj`jTjUjVuh1j&hhhj|hjhNubjX)}(h**Definition**:: struct i915_gem_engines_iter { unsigned int idx; const struct i915_gem_engines *engines; }; **Members** ``idx`` Index into i915_gem_engines::engines ``engines`` Engine set being iteratedh](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjhubh:}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK>hjdubj")}(hcstruct i915_gem_engines_iter { unsigned int idx; const struct i915_gem_engines *engines; };h]hcstruct i915_gem_engines_iter { unsigned int idx; const struct i915_gem_engines *engines; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j"hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK@hjdubh)}(h **Members**h]jb)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKEhjdubjx)}(hhh](j})}(h-``idx`` Index into i915_gem_engines::engines h](j)}(h``idx``h]j)}(hjh]hidx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK=hjubj)}(hhh]h)}(h$Index into i915_gem_engines::enginesh]h$Index into i915_gem_engines::engines}(hj΋hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjʋhK=hjˋubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjʋhK=hjubj})}(h%``engines`` Engine set being iteratedh](j)}(h ``engines``h]j)}(hjh]hengines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hEngine set being iteratedh]hEngine set being iterated}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubeh}(h]h ]h"]h$]h&]uh1jwhjdubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj|hhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_engine_type (C enum)c.i915_gem_engine_typehNtauh1jhj|hhhjhNubj')}(hhh](j,)}(hi915_gem_engine_typeh]j2)}(henum i915_gem_engine_typeh](j)}(hjh]henum}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubji)}(h h]h }(hjVhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjDhhhjUhKubjz)}(hi915_gem_engine_typeh]j;)}(hjBh]hi915_gem_engine_type}(hjhhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjdubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjDhhhjUhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj@hhhjUhKubah}(h]j;ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjUhKhj=hhubj1)}(hhh]h)}(h.Describes the type of an i915_gem_proto_engineh]h.Describes the type of an i915_gem_proto_engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKEhjhhubah}(h]h ]h"]h$]h&]uh1j0hj=hhhjUhKubeh}(h]h ](jRenumeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj|hjhNubjX)}(h**Constants** ``I915_GEM_ENGINE_TYPE_INVALID`` An invalid engine ``I915_GEM_ENGINE_TYPE_PHYSICAL`` A single physical engine ``I915_GEM_ENGINE_TYPE_BALANCED`` A load-balanced engine set ``I915_GEM_ENGINE_TYPE_PARALLEL`` A parallel engine seth](h)}(h **Constants**h]jb)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKIhjubjx)}(hhh](j})}(h3``I915_GEM_ENGINE_TYPE_INVALID`` An invalid engine h](j)}(h ``I915_GEM_ENGINE_TYPE_INVALID``h]j)}(hjˌh]hI915_GEM_ENGINE_TYPE_INVALID}(hj͌hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjɌubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKLhjŌubj)}(hhh]h)}(hAn invalid engineh]hAn invalid engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKLhjubah}(h]h ]h"]h$]h&]uh1jhjŌubeh}(h]h ]h"]h$]h&]uh1j|hjhKLhjŒubj})}(h;``I915_GEM_ENGINE_TYPE_PHYSICAL`` A single physical engine h](j)}(h!``I915_GEM_ENGINE_TYPE_PHYSICAL``h]j)}(hjh]hI915_GEM_ENGINE_TYPE_PHYSICAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKOhjubj)}(hhh]h)}(hA single physical engineh]hA single physical engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKOhjŒubj})}(h=``I915_GEM_ENGINE_TYPE_BALANCED`` A load-balanced engine set h](j)}(h!``I915_GEM_ENGINE_TYPE_BALANCED``h]j)}(hj=h]hI915_GEM_ENGINE_TYPE_BALANCED}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKRhj7ubj)}(hhh]h)}(hA load-balanced engine seth]hA load-balanced engine set}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhKRhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1j|hjRhKRhjŒubj})}(h7``I915_GEM_ENGINE_TYPE_PARALLEL`` A parallel engine seth](j)}(h!``I915_GEM_ENGINE_TYPE_PARALLEL``h]j)}(hjvh]hI915_GEM_ENGINE_TYPE_PARALLEL}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKThjpubj)}(hhh]h)}(hA parallel engine seth]hA parallel engine set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKUhjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1j|hjhKThjŒubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj|hhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_proto_engine (C struct)c.i915_gem_proto_enginehNtauh1jhj|hhhjhNubj')}(hhh](j,)}(hi915_gem_proto_engineh]j2)}(hstruct i915_gem_proto_engineh](j)}(hjh]hstruct}(hjЍhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̍hhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKZubji)}(h h]h }(hjލhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj̍hhhjݍhKZubjz)}(hi915_gem_proto_engineh]j;)}(hjʍh]hi915_gem_proto_engine}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj̍hhhjݍhKZubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjȍhhhjݍhKZubah}(h]jÍah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjݍhKZhjōhhubj1)}(hhh]h)}(hprototype engineh]hprototype engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKVhjhhubah}(h]h ]h"]h$]h&]uh1j0hjōhhhjݍhKZubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRj*jSj*jTjUjVuh1j&hhhj|hjhNubjX)}(hX"**Definition**:: struct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; }; **Members** ``type`` Type of this engine ``engine`` Engine, for physical ``num_siblings`` Number of balanced or parallel siblings ``width`` Width of each sibling ``siblings`` Balanced siblings or num_siblings * width for parallel ``sseu`` Client-set SSEU parametersh](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj2ubh:}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKZhj.ubj")}(hstruct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; };h]hstruct i915_gem_proto_engine { enum i915_gem_engine_type type; struct intel_engine_cs *engine; unsigned int num_siblings; unsigned int width; struct intel_engine_cs **siblings; struct intel_sseu sseu; };}hjOsbah}(h]h ]h"]h$]h&]jjuh1j"hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK\hj.ubh)}(h **Members**h]jb)}(hj`h]hMembers}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj^ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKehj.ubjx)}(hhh](j})}(h``type`` Type of this engine h](j)}(h``type``h]j)}(hjh]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKlhjyubj)}(hhh]h)}(hType of this engineh]hType of this engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKlhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j|hjhKlhjvubj})}(h ``engine`` Engine, for physical h](j)}(h ``engine``h]j)}(hjh]hengine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hEngine, for physicalh]hEngine, for physical}(hjюhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj͎hKhjΎubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj͎hKhjvubj})}(h9``num_siblings`` Number of balanced or parallel siblings h](j)}(h``num_siblings``h]j)}(hjh]h num_siblings}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(h'Number of balanced or parallel siblingsh]h'Number of balanced or parallel siblings}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjvubj})}(h ``width`` Width of each sibling h](j)}(h ``width``h]j)}(hj*h]hwidth}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj$ubj)}(hhh]h)}(hWidth of each siblingh]hWidth of each sibling}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hKhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1j|hj?hKhjvubj})}(hD``siblings`` Balanced siblings or num_siblings * width for parallel h](j)}(h ``siblings``h]j)}(hjch]hsiblings}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj]ubj)}(hhh]h)}(h6Balanced siblings or num_siblings * width for parallelh]h6Balanced siblings or num_siblings * width for parallel}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhKhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1j|hjxhKhjvubj})}(h#``sseu`` Client-set SSEU parametersh](j)}(h``sseu``h]j)}(hjh]hsseu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hClient-set SSEU parametersh]hClient-set SSEU parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjvubeh}(h]h ]h"]h$]h&]uh1jwhj.ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj|hhhjhNubh)}(h**Description**h]jb)}(hjߏh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjݏubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubh)}(hUThis struct describes an engine that a context may contain. Engines have four types:h]hUThis struct describes an engine that a context may contain. Engines have four types:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKWhj|hhubj)}(hX - I915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines. - I915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine. - I915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings. - I915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings. h]j:)}(hhh](j:)}(hXII915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines. h]h)}(hXHI915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines.h]hXHI915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they show up as a NULL in i915_gem_engines::engines[i] and any attempt to use them by the user results in -EINVAL. They are also useful during proto-context construction because the client may create invalid engines and then set them up later as virtual engines.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKZhj ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(heI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine. h]h)}(hdI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine.h]hdI915_GEM_ENGINE_TYPE_PHYSICAL: A single physical engine, described by i915_gem_proto_engine::engine.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhK`hj$ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings. h]h)}(hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings.h]hI915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKchj=ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings. h]h)}(hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings.h]hI915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and i915_gem_proto_engine::siblings.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKfhjVubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKZhjubah}(h]h ]h"]h$]h&]uh1jhjhKZhj|hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!i915_gem_proto_context (C struct)c.i915_gem_proto_contexthNtauh1jhj|hhhjhNubj')}(hhh](j,)}(hi915_gem_proto_contexth]j2)}(hstruct i915_gem_proto_contexth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKmubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKmubjz)}(hi915_gem_proto_contexth]j;)}(hjh]hi915_gem_proto_context}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKmubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKmubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKmhjhhubj1)}(hhh]h)}(hprototype contexth]hprototype context}(hj֐hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjӐhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKmubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj|hjhNubjX)}(hXo**Definition**:: struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct i915_gem_proto_engine *user_engines; struct intel_sseu legacy_rcs_sseu; bool single_timeline; bool uses_protected_content; intel_wakeref_t pxp_wakeref; }; **Members** ``fpriv`` Client which creates the context ``vm`` See :c:type:`i915_gem_context.vm ` ``user_flags`` See :c:type:`i915_gem_context.user_flags ` ``sched`` See :c:type:`i915_gem_context.sched ` ``num_user_engines`` Number of user-specified engines or -1 ``user_engines`` User-specified engines ``legacy_rcs_sseu`` Client-set SSEU parameters for the legacy RCS ``single_timeline`` See See :c:type:`i915_gem_context.syncobj ` ``uses_protected_content`` See :c:type:`i915_gem_context.uses_protected_content ` ``pxp_wakeref`` See :c:type:`i915_gem_context.pxp_wakeref `h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj")}(hX{struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct i915_gem_proto_engine *user_engines; struct intel_sseu legacy_rcs_sseu; bool single_timeline; bool uses_protected_content; intel_wakeref_t pxp_wakeref; };h]hX{struct i915_gem_proto_context { struct drm_i915_file_private *fpriv; struct i915_address_space *vm; unsigned long user_flags; struct i915_sched_attr sched; int num_user_engines; struct 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:c:type:`i915_gem_context.vm ` h](j)}(h``vm``h]j)}(hj|h]hvm}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjvubj)}(hhh]h)}(h4See :c:type:`i915_gem_context.vm `h](hSee }(hjhhhNhNubh)}(h0:c:type:`i915_gem_context.vm `h]j)}(hjh]hi915_gem_context.vm}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj:ubj})}(hL``user_flags`` See :c:type:`i915_gem_context.user_flags ` h](j)}(h``user_flags``h]j)}(hjԑh]h user_flags}(hj֑hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjґubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjΑubj)}(hhh]h)}(h`h](hSee }(hjhhhNhNubh)}(h8:c:type:`i915_gem_context.user_flags `h]j)}(hjh]hi915_gem_context.user_flags}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjΑubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj:ubj})}(hB``sched`` See :c:type:`i915_gem_context.sched ` h](j)}(h ``sched``h]j)}(hj,h]hsched}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj&ubj)}(hhh]h)}(h7See :c:type:`i915_gem_context.sched `h](hSee }(hjEhhhNhNubh)}(h3:c:type:`i915_gem_context.sched `h]j)}(hjOh]hi915_gem_context.sched}(hjQhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhjAhKhjEubeh}(h]h ]h"]h$]h&]uh1hhjAhKhjBubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hjAhKhj:ubj})}(h<``num_user_engines`` Number of user-specified engines or -1 h](j)}(h``num_user_engines``h]j)}(hjh]hnum_user_engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj~ubj)}(hhh]h)}(h&Number of user-specified engines or -1h]h&Number of user-specified engines or -1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj:ubj})}(h(``user_engines`` User-specified engines h](j)}(h``user_engines``h]j)}(hjh]h user_engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hUser-specified enginesh]hUser-specified engines}(hj֒hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjҒhKhjӒubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjҒhKhj:ubj})}(hB``legacy_rcs_sseu`` Client-set SSEU parameters for the legacy RCS h](j)}(h``legacy_rcs_sseu``h]j)}(hjh]hlegacy_rcs_sseu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(h-Client-set SSEU parameters for the legacy RCSh]h-Client-set SSEU parameters for the legacy RCS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hKhj:ubj})}(hR``single_timeline`` See See :c:type:`i915_gem_context.syncobj ` h](j)}(h``single_timeline``h]j)}(hj/h]hsingle_timeline}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj)ubj)}(hhh]h)}(h=See See :c:type:`i915_gem_context.syncobj `h](hSee See }(hjHhhhNhNubh)}(h5:c:type:`i915_gem_context.syncobj `h]j)}(hjRh]hi915_gem_context.syncobj}(hjThhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhjDhKhjHubeh}(h]h ]h"]h$]h&]uh1hhjDhKhjEubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1j|hjDhKhj:ubj})}(hd``uses_protected_content`` See :c:type:`i915_gem_context.uses_protected_content ` h](j)}(h``uses_protected_content``h]j)}(hjh]huses_protected_content}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hHSee :c:type:`i915_gem_context.uses_protected_content `h](hSee }(hjhhhNhNubh)}(hD:c:type:`i915_gem_context.uses_protected_content `h]j)}(hjh]h'i915_gem_context.uses_protected_content}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj:ubj})}(hM``pxp_wakeref`` See :c:type:`i915_gem_context.pxp_wakeref `h](j)}(h``pxp_wakeref``h]j)}(hjߓh]h pxp_wakeref}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjݓubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjٓubj)}(hhh]h)}(h=See :c:type:`i915_gem_context.pxp_wakeref `h](hSee }(hjhhhNhNubh)}(h9:c:type:`i915_gem_context.pxp_wakeref `h]j)}(hjh]hi915_gem_context.pxp_wakeref}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_contextuh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjٓubeh}(h]h ]h"]h$]h&]uh1j|hjhKhj:ubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj|hhhjhNubh)}(h**Description**h]jb)}(hjAh]h Description}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubh)}(hXThe struct i915_gem_proto_context represents the creation parameters for a struct i915_gem_context. This is used to gather parameters provided either through creation flags or via SET_CONTEXT_PARAM so that, when we create the final i915_gem_context, those parameters can be immutable.h]hXThe struct i915_gem_proto_context represents the creation parameters for a struct i915_gem_context. This is used to gather parameters provided either through creation flags or via SET_CONTEXT_PARAM so that, when we create the final i915_gem_context, those parameters can be immutable.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubh)}(hXcThe context uAPI allows for two methods of setting context parameters: SET_CONTEXT_PARAM and CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called at any time while the later happens as part of GEM_CONTEXT_CREATE. When these were initially added, Currently, everything settable via one is settable via the other. While some params are fairly simple and setting them on a live context is harmless such the context priority, others are far trickier such as the VM or the set of engines. To avoid some truly nasty race conditions, we don't allow setting the VM or the set of engines on live contexts.h]hXeThe context uAPI allows for two methods of setting context parameters: SET_CONTEXT_PARAM and CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called at any time while the later happens as part of GEM_CONTEXT_CREATE. When these were initially added, Currently, everything settable via one is settable via the other. While some params are fairly simple and setting them on a live context is harmless such the context priority, others are far trickier such as the VM or the set of engines. To avoid some truly nasty race conditions, we don’t allow setting the VM or the set of engines on live contexts.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubh)}(hX The way we dealt with this without breaking older userspace that sets the VM or engine set via SET_CONTEXT_PARAM is to delay the creation of the actual context until after the client is done configuring it with SET_CONTEXT_PARAM. From the perspective of the client, it has the same u32 context ID the whole time. From the perspective of i915, however, it's an i915_gem_proto_context right up until the point where we attempt to do something which the proto-context can't handle at which point the real context gets created.h]hXThe way we dealt with this without breaking older userspace that sets the VM or engine set via SET_CONTEXT_PARAM is to delay the creation of the actual context until after the client is done configuring it with SET_CONTEXT_PARAM. From the perspective of the client, it has the same u32 context ID the whole time. From the perspective of i915, however, it’s an i915_gem_proto_context right up until the point where we attempt to do something which the proto-context can’t handle at which point the real context gets created.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubh)}(hXThis is accomplished via a little xarray dance. When GEM_CONTEXT_CREATE is called, we create a proto-context, reserve a slot in context_xa but leave it NULL, the proto-context in the corresponding slot in proto_context_xa. Then, whenever we go to look up a context, we first check context_xa. If it's there, we return the i915_gem_context and we're done. If it's not, we look in proto_context_xa and, if we find it there, we create the actual context and kill the proto-context.h]hXThis is accomplished via a little xarray dance. When GEM_CONTEXT_CREATE is called, we create a proto-context, reserve a slot in context_xa but leave it NULL, the proto-context in the corresponding slot in proto_context_xa. Then, whenever we go to look up a context, we first check context_xa. If it’s there, we return the i915_gem_context and we’re done. If it’s not, we look in proto_context_xa and, if we find it there, we create the actual context and kill the proto-context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubh)}(hAt the time we made this change (April, 2021), we did a fairly complete audit of existing userspace to ensure this wouldn't break anything:h]hAt the time we made this change (April, 2021), we did a fairly complete audit of existing userspace to ensure this wouldn’t break anything:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubj)}(hX- Mesa/i965 didn't use the engines or VM APIs at all - Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API. - Mesa/iris didn't use the engines or VM APIs at all - The open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE. - The media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that. h]j:)}(hhh](j:)}(h3Mesa/i965 didn't use the engines or VM APIs at all h]h)}(h2Mesa/i965 didn't use the engines or VM APIs at allh]h4Mesa/i965 didn’t use the engines or VM APIs at all}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h]Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API. h]h)}(h\Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn't use the VM API.h]h^Mesa/ANV used the engines API but via CONTEXT_CREATE_EXT_SETPARAM and didn’t use the VM API.}(hjƔhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj”ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h3Mesa/iris didn't use the engines or VM APIs at all h]h)}(h2Mesa/iris didn't use the engines or VM APIs at allh]h4Mesa/iris didn’t use the engines or VM APIs at all}(hjߔhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj۔ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hThe open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE. h]h)}(hThe open-source compute-runtime didn't yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE.h]hThe open-source compute-runtime didn’t yet use the engines API but did use the VM API via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that. h]h)}(hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that.h]hThe media driver sets engines and bonding/balancing via SET_CONTEXT_PARAM. However, CONTEXT_SETPARAM to set the VM was always the second ioctl on that context, immediately following GEM_CONTEXT_CREATE and setting engines immediately followed that.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjhKhj|hhubh)}(hXiIn order for this dance to work properly, any modification to an i915_gem_proto_context that is exposed to the client via drm_i915_file_private::proto_context_xa must be guarded by drm_i915_file_private::proto_context_lock. The exception is when a proto-context has not yet been exposed such as when handling CONTEXT_CREATE_SET_PARAM during GEM_CONTEXT_CREATE.h]hXiIn order for this dance to work properly, any modification to an i915_gem_proto_context that is exposed to the client via drm_i915_file_private::proto_context_xa must be guarded by drm_i915_file_private::proto_context_lock. The exception is when a proto-context has not yet been exposed such as when handling CONTEXT_CREATE_SET_PARAM during GEM_CONTEXT_CREATE.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_gem_context (C struct)c.i915_gem_contexthNtauh1jhj|hhhjhNubj')}(hhh](j,)}(hi915_gem_contexth]j2)}(hstruct i915_gem_contexth](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKubji)}(h h]h }(hjhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjVhhhjghKubjz)}(hi915_gem_contexth]j;)}(hjTh]hi915_gem_context}(hjzhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjvubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjVhhhjghKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjRhhhjghKubah}(h]jMah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjghKhjOhhubj1)}(hhh]h)}(h client stateh]h client state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjOhhhjghKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj|hjhNubjX)}(hX**Definition**:: struct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines __rcu *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; }; **Members** ``i915`` i915 device backpointer ``file_priv`` owning file descriptor ``engines`` User defined engines for this context Various uAPI offer the ability to lookup up an index from this array to select an engine operate on. Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines. Execbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index. User defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set). ``engines_mutex`` guards writes to engines ``syncobj`` Shared timeline syncobj When the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care. ``vm`` unique address space (GTT) In full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others. In other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT. ``pid`` process id of creator Note that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated. ``link`` place with :c:type:`drm_i915_private.context_list ` ``client`` struct i915_drm_client ``client_link`` for linking onto :c:type:`i915_drm_client.ctx_list ` ``ref`` reference count A reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access. ``release_work`` Work item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context. FIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock. ``rcu`` rcu_head for deferred freeing. ``user_flags`` small set of booleans controlled by the user ``flags`` small set of booleans ``uses_protected_content`` context uses PXP-encrypted objects. This flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts. ``pxp_wakeref`` wakeref to keep the device awake when PXP is in use PXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics. ``mutex`` guards everything that isn't engines or handles_vma ``sched`` scheduler parameters ``guilty_count`` How many times this context has caused a GPU hang. ``active_count`` How many times this context was active during a GPU hang, but did not cause it. ``hang_timestamp`` The last time(s) this context caused a GPU hang ``remap_slice`` Bitmask of cache lines that need remapping ``handles_vma`` rbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT) ``lut_mutex`` Locks handles_vma ``name`` arbitrary name, used for user debug A name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages. ``stale`` tracks stale engines to be destroyedh](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj")}(hXstruct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines __rcu *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; };h]hXstruct i915_gem_context { struct drm_i915_private *i915; struct drm_i915_file_private *file_priv; struct i915_gem_engines __rcu *engines; struct mutex engines_mutex; struct drm_syncobj *syncobj; struct i915_address_space *vm; struct pid *pid; struct list_head link; struct i915_drm_client *client; struct list_head client_link; struct kref ref; struct work_struct release_work; struct rcu_head rcu; unsigned long user_flags; #define UCONTEXT_NO_ERROR_CAPTURE 1; #define UCONTEXT_BANNABLE 2; #define UCONTEXT_RECOVERABLE 3; #define UCONTEXT_PERSISTENCE 4; #define UCONTEXT_LOW_LATENCY 5; unsigned long flags; #define CONTEXT_CLOSED 0; #define CONTEXT_USER_ENGINES 1; bool uses_protected_content; intel_wakeref_t pxp_wakeref; struct mutex mutex; struct i915_sched_attr sched; atomic_t guilty_count; atomic_t active_count; unsigned long hang_timestamp[2]; #define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) ; u8 remap_slice; struct radix_tree_root handles_vma; struct mutex lut_mutex; char name[TASK_COMM_LEN + 8]; struct { spinlock_t lock; struct list_head engines; } stale; };}hjٕsbah}(h]h ]h"]h$]h&]jjuh1j"hk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(h **Members**h]jb)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM hjubjx)}(hhh](j})}(h!``i915`` i915 device backpointer h](j)}(h``i915``h]j)}(hj h]hi915}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hi915 device backpointerh]hi915 device backpointer}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h%``file_priv`` owning file descriptor h](j)}(h ``file_priv``h]j)}(hjBh]h file_priv}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj<ubj)}(hhh]h)}(howning file descriptorh]howning file descriptor}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhKhjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1j|hjWhKhjubj})}(hX``engines`` User defined engines for this context Various uAPI offer the ability to lookup up an index from this array to select an engine operate on. Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines. Execbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index. User defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set). h](j)}(h ``engines``h]j)}(hj{h]hengines}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjuubj)}(hhh](h)}(h%User defined engines for this contexth]h%User defined engines for this context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hdVarious uAPI offer the ability to lookup up an index from this array to select an engine operate on.h]hdVarious uAPI offer the ability to lookup up an index from this array to select an engine operate on.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(h{Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines.h]h{Multiple logically distinct instances of the same engine may be defined in the array, as well as composite virtual engines.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hXExecbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index.h]hXExecbuf uses the I915_EXEC_RING_MASK as an index into this array to select which HW context + engine to execute on. For the default array, the user_ring_map[] is used to translate the legacy uABI onto the appropriate index (e.g. both I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same context, and I915_EXEC_BSD is weird). For a user defined array, execbuf uses I915_EXEC_RING_MASK as a plain index.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubh)}(hVUser defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set).h]hVUser defined by I915_CONTEXT_PARAM_ENGINE (when the CONTEXT_USER_ENGINES flag is set).}(hjЖhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h+``engines_mutex`` guards writes to engines h](j)}(h``engines_mutex``h]j)}(hjh]h engines_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hguards writes to enginesh]hguards writes to engines}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hX``syncobj`` Shared timeline syncobj When the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care. h](j)}(h ``syncobj``h]j)}(hj*h]hsyncobj}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj$ubj)}(hhh](h)}(hShared timeline syncobjh]hShared timeline syncobj}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj@ubh)}(hXWhen the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn't provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that's not likely to yield well- defined results anyway so we choose to not care.h]hXWhen the SHARED_TIMELINE flag is set on context creation, we emulate a single timeline across all engines using this syncobj. For every execbuffer2 call, this syncobj is used as both an in- and out-fence. Unlike the real intel_timeline, this doesn’t provide perfect atomic in-order guarantees if the client races with itself by calling execbuffer2 twice concurrently. However, if userspace races with itself, that’s not likely to yield well- defined results anyway so we choose to not care.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj@ubeh}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1j|hj?hMhjubj})}(hX``vm`` unique address space (GTT) In full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others. In other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT. h](j)}(h``vm``h]j)}(hjsh]hvm}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjmubj)}(hhh](h)}(hunique address space (GTT)h]hunique address space (GTT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubh)}(hvIn full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others.h]hvIn full-ppgtt mode, each context has its own address space ensuring complete separation of one client from all others.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubh)}(hgIn other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT.h]hgIn other modes, this is a NULL pointer with the expectation that the caller uses the shared global GTT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hX``pid`` process id of creator Note that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated. h](j)}(h``pid``h]j)}(hj˗h]hpid}(hj͗hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjɗubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM$hjŗubj)}(hhh](h)}(hprocess id of creatorh]hprocess id of creator}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubh)}(hNote that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated.h]hNote that who created the context may not be the principle user, as the context may be shared across a local socket. However, that should only affect the default context, all contexts created explicitly by the client are expected to be isolated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM!hjubeh}(h]h ]h"]h$]h&]uh1jhjŗubeh}(h]h ]h"]h$]h&]uh1j|hjhM$hjubj})}(hO``link`` place with :c:type:`drm_i915_private.context_list ` h](j)}(h``link``h]j)}(hjh]hlink}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hEplace with :c:type:`drm_i915_private.context_list `h](h place with }(hj-hhhNhNubh)}(h::c:type:`drm_i915_private.context_list `h]j)}(hj7h]hdrm_i915_private.context_list}(hj9hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjdrm_i915_privateuh1hhj)hKhj-ubeh}(h]h ]h"]h$]h&]uh1hhj)hKhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj)hKhjubj})}(h"``client`` struct i915_drm_client h](j)}(h ``client``h]j)}(hjlh]hclient}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjfubj)}(hhh]h)}(hstruct i915_drm_clienth]hstruct i915_drm_client}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hV``client_link`` for linking onto :c:type:`i915_drm_client.ctx_list ` h](j)}(h``client_link``h]j)}(hjh]h client_link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(hEfor linking onto :c:type:`i915_drm_client.ctx_list `h](hfor linking onto }(hjhhhNhNubh)}(h4:c:type:`i915_drm_client.ctx_list `h]j)}(hjȘh]hi915_drm_client.ctx_list}(hjʘhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjƘubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_drm_clientuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hX9``ref`` reference count A reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access. h](j)}(h``ref``h]j)}(hjh]href}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM8hjubj)}(hhh](h)}(hreference counth]hreference count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM2hjubh)}(hXA reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access.h]hXA reference to a context is held by both the client who created it and on each request submitted to the hardware using the request (to ensure the hardware has access to the state until it has finished all pending writes). See i915_gem_context_get() and i915_gem_context_put() for access.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM4hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM8hjubj})}(hX```release_work`` Work item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context. FIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock. h](j)}(h``release_work``h]j)}(hjFh]h release_work}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMBhj@ubj)}(hhh](h)}(heWork item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context.h]heWork item for deferred cleanup, since i915_gem_context_put() tends to be called from hardirq context.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM=hj\ubh)}(hFIXME: The only real reason for this is :c:type:`i915_gem_engines.fence `, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock.h](h(FIXME: The only real reason for this is }(hjnhhhNhNubh)}(h3:c:type:`i915_gem_engines.fence `h]j)}(hjxh]hi915_gem_engines.fence}(hjzhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_gem_enginesuh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM@hjnubh, all other callers are from process context and need at most some mild shuffling to pull the i915_gem_context_put() call out of a spinlock.}(hjnhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM@hj\ubeh}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1j|hj[hMBhjubj})}(h'``rcu`` rcu_head for deferred freeing. h](j)}(h``rcu``h]j)}(hjh]hrcu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMIhjubj)}(hhh]h)}(hrcu_head for deferred freeing.h]hrcu_head for deferred freeing.}(hj˙hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjǙhMIhjșubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjǙhMIhjubj})}(h<``user_flags`` small set of booleans controlled by the user h](j)}(h``user_flags``h]j)}(hjh]h user_flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMNhjubj)}(hhh]h)}(h,small set of booleans controlled by the userh]h,small set of booleans controlled by the user}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMNhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMNhjubj})}(h ``flags`` small set of booleans h](j)}(h ``flags``h]j)}(hj$h]hflags}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMXhjubj)}(hhh]h)}(hsmall set of booleansh]hsmall set of booleans}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMXhj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj9hMXhjubj})}(hX4``uses_protected_content`` context uses PXP-encrypted objects. This flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts. h](j)}(h``uses_protected_content``h]j)}(hj]h]huses_protected_content}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMdhjWubj)}(hhh](h)}(h#context uses PXP-encrypted objects.h]h#context uses PXP-encrypted objects.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM_hjsubh)}(hThis flag can only be set at ctx creation time and it's immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts.h]hThis flag can only be set at ctx creation time and it’s immutable for the lifetime of the context. See I915_CONTEXT_PARAM_PROTECTED_CONTENT in uapi/drm/i915_drm.h for more info on setting restrictions and expected behaviour of marked contexts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMahjsubeh}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1j|hjrhMdhjubj})}(hX``pxp_wakeref`` wakeref to keep the device awake when PXP is in use PXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics. h](j)}(h``pxp_wakeref``h]j)}(hjh]h pxp_wakeref}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMphjubj)}(hhh](h)}(h3wakeref to keep the device awake when PXP is in useh]h3wakeref to keep the device awake when PXP is in use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMihjubh)}(hXgPXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn't worsen our power metrics.h]hXiPXP sessions are invalidated when the device is suspended, which in turns invalidates all contexts and objects using it. To keep the flow simple, we keep the device awake when contexts using PXP objects are in use. It is expected that the userspace application only uses PXP when the display is on, so taking a wakeref here shouldn’t worsen our power metrics.}(hjΚhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMkhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMphjubj})}(h>``mutex`` guards everything that isn't engines or handles_vma h](j)}(h ``mutex``h]j)}(hjh]hmutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(h3guards everything that isn't engines or handles_vmah]h5guards everything that isn’t engines or handles_vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``sched`` scheduler parameters h](j)}(h ``sched``h]j)}(hj(h]hsched}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj"ubj)}(hhh]h)}(hscheduler parametersh]hscheduler parameters}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKhj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj=hKhjubj})}(hD``guilty_count`` How many times this context has caused a GPU hang. h](j)}(h``guilty_count``h]j)}(hjah]h guilty_count}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj[ubj)}(hhh]h)}(h2How many times this context has caused a GPU hang.h]h2How many times this context has caused a GPU hang.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhKhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hjvhKhjubj})}(ha``active_count`` How many times this context was active during a GPU hang, but did not cause it. h](j)}(h``active_count``h]j)}(hjh]h active_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM~hjubj)}(hhh]h)}(hOHow many times this context was active during a GPU hang, but did not cause it.h]hOHow many times this context was active during a GPU hang, but did not cause it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhM}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM~hjubj})}(hC``hang_timestamp`` The last time(s) this context caused a GPU hang h](j)}(h``hang_timestamp``h]j)}(hjԛh]hhang_timestamp}(hj֛hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjқubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjΛubj)}(hhh]h)}(h/The last time(s) this context caused a GPU hangh]h/The last time(s) this context caused a GPU hang}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjΛubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(h;``remap_slice`` Bitmask of cache lines that need remapping h](j)}(h``remap_slice``h]j)}(hj h]h remap_slice}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(h*Bitmask of cache lines that need remappingh]h*Bitmask of cache lines that need remapping}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hKhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj"hKhjubj})}(h``handles_vma`` rbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT) h](j)}(h``handles_vma``h]j)}(hjFh]h handles_vma}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj@ubj)}(hhh]h)}(hrbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT)h]hrbtree to look up our context specific obj/vma for the user handle. (user handles are per fd, but the binding is per vm, which may be one per context or shared with the global GTT)}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1j|hj[hMhjubj})}(h ``lut_mutex`` Locks handles_vma h](j)}(h ``lut_mutex``h]j)}(hjh]h lut_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjzubj)}(hhh]h)}(hLocks handles_vmah]hLocks handles_vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``name`` arbitrary name, used for user debug A name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages. h](j)}(h``name``h]j)}(hjh]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjubj)}(hhh](h)}(h#arbitrary name, used for user debugh]h#arbitrary name, used for user debug}(hjҜhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjϜubh)}(hA name is constructed for the context from the creator's process name, pid and user handle in order to uniquely identify the context in messages.h]hA name is constructed for the context from the creator’s process name, pid and user handle in order to uniquely identify the context in messages.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhMhjϜubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjΜhMhjubj})}(h.``stale`` tracks stale engines to be destroyedh](j)}(h ``stale``h]j)}(hjh]hstale}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubj)}(hhh]h)}(h$tracks stale engines to be destroyedh]h$tracks stale engines to be destroyed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj|hhhjhNubh)}(h**Description**h]jb)}(hjEh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjCubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubh)}(hzThe struct i915_gem_context represents the combined view of the driver and logical hardware state for a particular client.h]hzThe struct i915_gem_context represents the combined view of the driver and logical hardware state for a particular client.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:431: ./drivers/gpu/drm/i915/gem/i915_gem_context_types.hhKhj|hhubh)}(hXUserspace submits commands to be executed on the GPU as an instruction stream within a GEM object we call a batchbuffer. This instructions may refer to other GEM objects containing auxiliary state such as kernels, samplers, render targets and even secondary batchbuffers. Userspace does not know where in the GPU memory these objects reside and so before the batchbuffer is passed to the GPU for execution, those addresses in the batchbuffer and auxiliary objects are updated. This is known as relocation, or patching. To try and avoid having to relocate each object on the next execution, userspace is told the location of those objects in this pass, but this remains just a hint as the kernel may choose a new location for any object in the future.h]hXUserspace submits commands to be executed on the GPU as an instruction stream within a GEM object we call a batchbuffer. This instructions may refer to other GEM objects containing auxiliary state such as kernels, samplers, render targets and even secondary batchbuffers. Userspace does not know where in the GPU memory these objects reside and so before the batchbuffer is passed to the GPU for execution, those addresses in the batchbuffer and auxiliary objects are updated. This is known as relocation, or patching. To try and avoid having to relocate each object on the next execution, userspace is told the location of those objects in this pass, but this remains just a hint as the kernel may choose a new location for any object in the future.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKWhj|hhubh)}(hAt the level of talking to the hardware, submitting a batchbuffer for the GPU to execute is to add content to a buffer from which the HW command streamer is reading.h]hAt the level of talking to the hardware, submitting a batchbuffer for the GPU to execute is to add content to a buffer from which the HW command streamer is reading.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKchj|hhubj:)}(hhh](j:)}(hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items. h]h)}(hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items.h]hAdd a command to load the HW context. For Logical Ring Contexts, i.e. Execlists, this command is not placed on the same buffer as the remaining items.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKghjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h2Add a command to invalidate caches to the buffer. h]h)}(h1Add a command to invalidate caches to the buffer.h]h1Add a command to invalidate caches to the buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKkhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed. h]h)}(hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed.h]hAdd a batchbuffer start command to the buffer; the start command is essentially a token together with the GPU address of the batchbuffer to be executed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKmhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h$Add a pipeline flush to the buffer. h]h)}(h#Add a pipeline flush to the buffer.h]h#Add a pipeline flush to the buffer.}(hjڝhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKqhj֝ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hX4Add a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, ``i915_request::global_seqno``; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer. h]h)}(hX3Add a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, ``i915_request::global_seqno``; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer.h](hAdd a memory write command to the buffer to record when the GPU is done executing the batchbuffer. The memory write writes the global sequence number of the request, }(hjhhhNhNubj)}(h``i915_request::global_seqno``h]hi915_request::global_seqno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubho; the i915 driver uses the current value in the register to determine if the GPU has completed the batchbuffer.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKshjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed. h]h)}(hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed.h]hAdd a user interrupt command to the buffer. This command instructs the GPU to issue an interrupt when the command, pipeline flush and memory write are completed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKyhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hcInform the hardware of the additional commands added to the buffer (by updating the tail pointer). h]h)}(hbInform the hardware of the additional commands added to the buffer (by updating the tail pointer).h]hbInform the hardware of the additional commands added to the buffer (by updating the tail pointer).}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chK}hj3ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hj|hhhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chNubh)}(hGProcessing an execbuf ioctl is conceptually split up into a few phases.h]hGProcessing an execbuf ioctl is conceptually split up into a few phases.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj|hhubj:)}(hhh](j:)}(hBValidation - Ensure all the pointers, handles and flags are valid.h]h)}(hjgh]hBValidation - Ensure all the pointers, handles and flags are valid.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjeubah}(h]h ]h"]h$]h&]uh1j:hjbubj:)}(h7Reservation - Assign GPU address space for every objecth]h)}(hjh]h7Reservation - Assign GPU address space for every object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj}ubah}(h]h ]h"]h$]h&]uh1j:hjbubj:)}(hARelocation - Update any addresses to point to the final locationsh]h)}(hjh]hARelocation - Update any addresses to point to the final locations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjubah}(h]h ]h"]h$]h&]uh1j:hjbubj:)}(hBSerialisation - Order the request with respect to its dependenciesh]h)}(hjh]hBSerialisation - Order the request with respect to its dependencies}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjubah}(h]h ]h"]h$]h&]uh1j:hjbubj:)}(h=Construction - Construct a request to execute the batchbufferh]h)}(hjǞh]h=Construction - Construct a request to execute the batchbuffer}(hjɞhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjŞubah}(h]h ]h"]h$]h&]uh1j:hjbubj:)}(h3Submission (at some point in the future execution) h]h)}(h2Submission (at some point in the future execution)h]h2Submission (at some point in the future execution)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhjݞubah}(h]h ]h"]h$]h&]uh1j:hjbubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hj|hhhjRhNubh)}(hXReserving resources for the execbuf is the most complicated phase. We neither want to have to migrate the object in the address space, nor do we want to have to update any relocations pointing to this object. Ideally, we want to leave the object where it is and for all the existing relocations to match. If the object is given a new address, or if userspace thinks the object is elsewhere, we have to parse all the relocation entries and update the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that all the target addresses in all of its objects match the value in the relocation entries and that they all match the presumed offsets given by the list of execbuffer objects. Using this knowledge, we know that if we haven't moved any buffers, all the relocation entries are valid and we can skip the update. (If userspace is wrong, the likely outcome is an impromptu GPU hang.) The requirement for using I915_EXEC_NO_RELOC are:h]hXReserving resources for the execbuf is the most complicated phase. We neither want to have to migrate the object in the address space, nor do we want to have to update any relocations pointing to this object. Ideally, we want to leave the object where it is and for all the existing relocations to match. If the object is given a new address, or if userspace thinks the object is elsewhere, we have to parse all the relocation entries and update the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that all the target addresses in all of its objects match the value in the relocation entries and that they all match the presumed offsets given by the list of execbuffer objects. Using this knowledge, we know that if we haven’t moved any buffers, all the relocation entries are valid and we can skip the update. (If userspace is wrong, the likely outcome is an impromptu GPU hang.) The requirement for using I915_EXEC_NO_RELOC are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj|hhubj)}(hX[The addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset. Any render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE. To avoid stalling, execobject.offset should match the current address of that object within the active context. h](h)}(hThe addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset.h]hThe addresses written in the objects must match the corresponding reloc.presumed_offset which in turn must match the corresponding execobject.offset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj ubh)}(hRAny render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE.h]hRAny render targets written to in the batch must be flagged with EXEC_OBJECT_WRITE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj ubh)}(hoTo avoid stalling, execobject.offset should match the current address of that object within the active context.h]hoTo avoid stalling, execobject.offset should match the current address of that object within the active context.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj ubeh}(h]h ]h"]h$]h&]uh1jhjhKhj|hhubh)}(hXTThe reservation is done is multiple phases. First we try and keep any object already bound in its current location - so as long as meets the constraints imposed by the new execbuffer. Any object left unbound after the first pass is then fitted into any available idle space. If an object does not fit, all objects are removed from the reservation and the process rerun after sorting the objects into a priority order (more difficult to fit objects are tried first). Failing that, the entire VM is cleared and we try to fit the execbuf once last time before concluding that it simply will not fit.h]hXTThe reservation is done is multiple phases. First we try and keep any object already bound in its current location - so as long as meets the constraints imposed by the new execbuffer. Any object left unbound after the first pass is then fitted into any available idle space. If an object does not fit, all objects are removed from the reservation and the process rerun after sorting the objects into a priority order (more difficult to fit objects are tried first). Failing that, the entire VM is cleared and we try to fit the execbuf once last time before concluding that it simply will not fit.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj|hhubh)}(hXBA small complication to all of this is that we allow userspace not only to specify an alignment and a size for the object in the address space, but we also allow userspace to specify the exact offset. This objects are simpler to place (the location is known a priori) all we have to do is make sure the space is available.h]hXBA small complication to all of this is that we allow userspace not only to specify an alignment and a size for the object in the address space, but we also allow userspace to specify the exact offset. This objects are simpler to place (the location is known a priori) all we have to do is make sure the space is available.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj|hhubh)}(hX1Once all the objects are in place, patching up the buried pointers to point to the final locations is a fairly simple job of walking over the relocation entry arrays, looking up the right address and rewriting the value into the object. Simple! ... The relocation entries are stored in user memory and so to access them we have to copy them into a local buffer. That copy has to avoid taking any pagefaults as they may lead back to a GEM object requiring the struct_mutex (i.e. recursive deadlock). So once again we split the relocation into multiple passes. First we try to do everything within an atomic context (avoid the pagefaults) which requires that we never wait. If we detect that we may wait, or if we need to fault, then we have to fallback to a slower path. The slowpath has to drop the mutex. (Can you hear alarm bells yet?) Dropping the mutex means that we lose all the state we have built up so far for the execbuf and we must reset any global data. However, we do leave the objects pinned in their final locations - which is a potential issue for concurrent execbufs. Once we have left the mutex, we can allocate and copy all the relocation entries into a large array at our leisure, reacquire the mutex, reclaim all the objects and other state and then proceed to update any incorrect addresses with the objects.h]hX1Once all the objects are in place, patching up the buried pointers to point to the final locations is a fairly simple job of walking over the relocation entry arrays, looking up the right address and rewriting the value into the object. Simple! ... The relocation entries are stored in user memory and so to access them we have to copy them into a local buffer. That copy has to avoid taking any pagefaults as they may lead back to a GEM object requiring the struct_mutex (i.e. recursive deadlock). So once again we split the relocation into multiple passes. First we try to do everything within an atomic context (avoid the pagefaults) which requires that we never wait. If we detect that we may wait, or if we need to fault, then we have to fallback to a slower path. The slowpath has to drop the mutex. (Can you hear alarm bells yet?) Dropping the mutex means that we lose all the state we have built up so far for the execbuf and we must reset any global data. However, we do leave the objects pinned in their final locations - which is a potential issue for concurrent execbufs. Once we have left the mutex, we can allocate and copy all the relocation entries into a large array at our leisure, reacquire the mutex, reclaim all the objects and other state and then proceed to update any incorrect addresses with the objects.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj|hhubh)}(hXAs we process the relocation entries, we maintain a record of whether the object is being written to. Using NORELOC, we expect userspace to provide this information instead. We also check whether we can skip the relocation by comparing the expected value inside the relocation entry with the target's final address. If they differ, we have to map the current object and rewrite the 4 or 8 byte pointer within.h]hXAs we process the relocation entries, we maintain a record of whether the object is being written to. Using NORELOC, we expect userspace to provide this information instead. We also check whether we can skip the relocation by comparing the expected value inside the relocation entry with the target’s final address. If they differ, we have to map the current object and rewrite the 4 or 8 byte pointer within.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj|hhubh)}(hXSerialising an execbuf is quite simple according to the rules of the GEM ABI. Execution within each context is ordered by the order of submission. Writes to any GEM object are in order of submission and are exclusive. Reads from a GEM object are unordered with respect to other reads, but ordered by writes. A write submitted after a read cannot occur before the read, and similarly any read submitted after a write cannot occur before the write. Writes are ordered between engines such that only one write occurs at any time (completing any reads beforehand) - using semaphores where available and CPU serialisation otherwise. Other GEM access obey the same rules, any write (either via mmaps using set-domain, or via pwrite) must flush all GPU reads before starting, and any read (either using set-domain or pread) must flush all GPU writes before starting. (Note we only employ a barrier before, we currently rely on userspace not concurrently starting a new execution whilst reading or writing to an object. This may be an advantage or not depending on how much you trust userspace not to shoot themselves in the foot.) Serialisation may just result in the request being inserted into a DAG awaiting its turn, but most simple is to wait on the CPU until all dependencies are resolved.h]hXSerialising an execbuf is quite simple according to the rules of the GEM ABI. Execution within each context is ordered by the order of submission. Writes to any GEM object are in order of submission and are exclusive. Reads from a GEM object are unordered with respect to other reads, but ordered by writes. A write submitted after a read cannot occur before the read, and similarly any read submitted after a write cannot occur before the write. Writes are ordered between engines such that only one write occurs at any time (completing any reads beforehand) - using semaphores where available and CPU serialisation otherwise. Other GEM access obey the same rules, any write (either via mmaps using set-domain, or via pwrite) must flush all GPU reads before starting, and any read (either using set-domain or pread) must flush all GPU writes before starting. (Note we only employ a barrier before, we currently rely on userspace not concurrently starting a new execution whilst reading or writing to an object. This may be an advantage or not depending on how much you trust userspace not to shoot themselves in the foot.) Serialisation may just result in the request being inserted into a DAG awaiting its turn, but most simple is to wait on the CPU until all dependencies are resolved.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj|hhubh)}(hX&After all of that, is just a matter of closing the request and handing it to the hardware (well, leaving it in a queue to be executed). However, we also offer the ability for batchbuffers to be run with elevated privileges so that they access otherwise hidden registers. (Used to adjust L3 cache etc.) Before any batch is given extra privileges we first must check that it contains no nefarious instructions, we check that each instruction is from our whitelist and all registers are also from an allowed list. We first copy the user's batchbuffer to a shadow (so that the user doesn't have access to it, either by the CPU or GPU as we scan it) and then parse each instruction. If everything is ok, we set a flag telling the hardware to run the batchbuffer in trusted mode, otherwise the ioctl is rejected.h]hX*After all of that, is just a matter of closing the request and handing it to the hardware (well, leaving it in a queue to be executed). However, we also offer the ability for batchbuffers to be run with elevated privileges so that they access otherwise hidden registers. (Used to adjust L3 cache etc.) Before any batch is given extra privileges we first must check that it contains no nefarious instructions, we check that each instruction is from our whitelist and all registers are also from an allowed list. We first copy the user’s batchbuffer to a shadow (so that the user doesn’t have access to it, either by the CPU or GPU as we scan it) and then parse each instruction. If everything is ok, we set a flag telling the hardware to run the batchbuffer in trusted mode, otherwise the ioctl is rejected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhh/var/lib/git/docbuild/linux/Documentation/gpu/i915:433: ./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.chKhj|hhubeh}(h]user-batchbuffer-executionah ]h"]user batchbuffer executionah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(h Schedulingh]h Scheduling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_sched_engine (C struct)c.i915_sched_enginehNtauh1jhjhhhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhNubj')}(hhh](j,)}(hi915_sched_engineh]j2)}(hstruct i915_sched_engineh](j)}(hjh]hstruct}(hjϟhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj˟hhhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKubji)}(h h]h }(hjݟhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj˟hhhjܟhKubjz)}(hi915_sched_engineh]j;)}(hjɟh]hi915_sched_engine}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj˟hhhjܟhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjǟhhhjܟhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjܟhKhjğhhubj1)}(hhh]h)}(hscheduler engineh]hscheduler engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK_hjhhubah}(h]h ]h"]h$]h&]uh1j0hjğhhhjܟhKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRj)jSj)jTjUjVuh1j&hhhjhjßhNubjX)}(hXX **Definition**:: struct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); }; **Members** ``ref`` reference count of schedule engine object ``lock`` protects requests in priority lists, requests, hold and tasklet while running ``requests`` list of requests inflight on this schedule engine ``hold`` list of ready requests, but on hold ``tasklet`` softirq tasklet for submission ``default_priolist`` priority list for I915_PRIORITY_NORMAL ``queue_priority_hint`` Highest pending priority. When we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority. ``queue`` queue of requests, in priority lists ``no_priolist`` priority lists disabled ``private_data`` private data of the submission backend ``destroy`` destroy schedule engine / cleanup in backend ``disabled`` check if backend has disabled submission ``kick_backend`` kick backend after a request's priority has changed ``bump_inflight_request_prio`` update priority of an inflight request ``retire_inflight_request_prio`` indicate request is retired to priority tracking ``schedule`` adjust priority of request Call when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj1ubh:}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKchj-ubj")}(hXstruct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); };h]hXstruct i915_sched_engine { struct kref ref; spinlock_t lock; struct list_head requests; struct list_head hold; struct tasklet_struct tasklet; struct i915_priolist default_priolist; int queue_priority_hint; struct rb_root_cached queue; bool no_priolist; void *private_data; void (*destroy)(struct kref *kref); bool (*disabled)(struct i915_sched_engine *sched_engine); void (*kick_backend)(const struct i915_request *rq, int prio); void (*bump_inflight_request_prio)(struct i915_request *rq, int prio); void (*retire_inflight_request_prio)(struct i915_request *rq); void (*schedule)(struct i915_request *request, const struct i915_sched_attr *attr); };}hjNsbah}(h]h ]h"]h$]h&]jjuh1j"he/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKehj-ubh)}(h **Members**h]jb)}(hj_h]hMembers}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jahj]ubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKxhj-ubjx)}(hhh](j})}(h2``ref`` reference count of schedule engine object h](j)}(h``ref``h]j)}(hj~h]href}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKlhjxubj)}(hhh]h)}(h)reference count of schedule engine objecth]h)reference count of schedule engine object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKlhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1j|hjhKlhjuubj})}(hW``lock`` protects requests in priority lists, requests, hold and tasklet while running h](j)}(h``lock``h]j)}(hjh]hlock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKrhjubj)}(hhh]h)}(hMprotects requests in priority lists, requests, hold and tasklet while runningh]hMprotects requests in priority lists, requests, hold and tasklet while running}(hjРhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKqhj͠ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj̠hKrhjuubj})}(h?``requests`` list of requests inflight on this schedule engine h](j)}(h ``requests``h]j)}(hjh]hrequests}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKwhjubj)}(hhh]h)}(h1list of requests inflight on this schedule engineh]h1list of requests inflight on this schedule engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKwhjuubj})}(h-``hold`` list of ready requests, but on hold h](j)}(h``hold``h]j)}(hj*h]hhold}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK|hj$ubj)}(hhh]h)}(h#list of ready requests, but on holdh]h#list of ready requests, but on hold}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hK|hj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1j|hj?hK|hjuubj})}(h+``tasklet`` softirq tasklet for submission h](j)}(h ``tasklet``h]j)}(hjch]htasklet}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhj]ubj)}(hhh]h)}(hsoftirq tasklet for submissionh]hsoftirq tasklet for submission}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhKhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1j|hjxhKhjuubj})}(h<``default_priolist`` priority list for I915_PRIORITY_NORMAL h](j)}(h``default_priolist``h]j)}(hjh]hdefault_priolist}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h&priority list for I915_PRIORITY_NORMALh]h&priority list for I915_PRIORITY_NORMAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjuubj})}(hX ``queue_priority_hint`` Highest pending priority. When we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority. h](j)}(h``queue_priority_hint``h]j)}(hjաh]hqueue_priority_hint}(hjסhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjӡubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjϡubj)}(hhh](h)}(hHighest pending priority.h]hHighest pending priority.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubh)}(hXWhen we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority.h]hXWhen we add requests into the queue, or adjust the priority of executing requests, we compute the maximum priority of those pending requests. We can then use this value to determine if we need to preempt the executing requests to service the queue. However, since the we may have recorded the priority of an inflight request we wanted to preempt but since completed, at the time of dequeuing the priority hint may no longer may match the highest available request priority.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjϡubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjuubj})}(h/``queue`` queue of requests, in priority lists h](j)}(h ``queue``h]j)}(hjh]hqueue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h$queue of requests, in priority listsh]h$queue of requests, in priority lists}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hKhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj3hKhjuubj})}(h(``no_priolist`` priority lists disabled h](j)}(h``no_priolist``h]j)}(hjWh]h no_priolist}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjQubj)}(hhh]h)}(hpriority lists disabledh]hpriority lists disabled}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhKhjmubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1j|hjlhKhjuubj})}(h8``private_data`` private data of the submission backend h](j)}(h``private_data``h]j)}(hjh]h private_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h&private data of the submission backendh]h&private data of the submission backend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjuubj})}(h9``destroy`` destroy schedule engine / cleanup in backend h](j)}(h ``destroy``h]j)}(hjɢh]hdestroy}(hjˢhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjǢubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjâubj)}(hhh]h)}(h,destroy schedule engine / cleanup in backendh]h,destroy schedule engine / cleanup in backend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjޢhKhjߢubah}(h]h ]h"]h$]h&]uh1jhjâubeh}(h]h ]h"]h$]h&]uh1j|hjޢhKhjuubj})}(h6``disabled`` check if backend has disabled submission h](j)}(h ``disabled``h]j)}(hjh]hdisabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h(check if backend has disabled submissionh]h(check if backend has disabled submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjuubj})}(hE``kick_backend`` kick backend after a request's priority has changed h](j)}(h``kick_backend``h]j)}(hj;h]h kick_backend}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhj5ubj)}(hhh]h)}(h3kick backend after a request's priority has changedh]h5kick backend after a request’s priority has changed}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhKhjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1j|hjPhKhjuubj})}(hF``bump_inflight_request_prio`` update priority of an inflight request h](j)}(h``bump_inflight_request_prio``h]j)}(hjth]hbump_inflight_request_prio}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjnubj)}(hhh]h)}(h&update priority of an inflight requesth]h&update priority of an inflight request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjuubj})}(hR``retire_inflight_request_prio`` indicate request is retired to priority tracking h](j)}(h ``retire_inflight_request_prio``h]j)}(hjh]hretire_inflight_request_prio}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh]h)}(h0indicate request is retired to priority trackingh]h0indicate request is retired to priority tracking}(hjƣhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjãubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj£hKhjuubj})}(h``schedule`` adjust priority of request Call when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h](j)}(h ``schedule``h]j)}(hjh]hschedule}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubj)}(hhh](h)}(hadjust priority of requesth]hadjust priority of request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubh)}(hCall when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!h]hCall when the priority on a request has changed and it and its dependencies may need rescheduling. Note the request itself may not be ready to run!}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjuubeh}(h]h ]h"]h$]h&]uh1jwhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhjßhNubh)}(h**Description**h]jb)}(hj9h]h Description}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj7ubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKhjhhubh)}(hA schedule engine represents a submission queue with different priority bands. It contains all the common state (relative to the backend) to queue, track, and submit a request.h]hA schedule engine represents a submission queue with different priority bands. It contains all the common state (relative to the backend) to queue, track, and submit a request.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhK`hjhhubh)}(hThis object at the moment is quite i915 specific but will transition into a container for the drm_gpu_scheduler plus a few other variables once the i915 is integrated with the DRM scheduler.h]hThis object at the moment is quite i915 specific but will transition into a container for the drm_gpu_scheduler plus a few other variables once the i915 is integrated with the DRM scheduler.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhe/var/lib/git/docbuild/linux/Documentation/gpu/i915:438: ./drivers/gpu/drm/i915/i915_scheduler_types.hhKdhjhhubeh}(h] schedulingah ]h"] schedulingah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(h2Logical Rings, Logical Ring Contexts and Execlistsh]h2Logical Rings, Logical Ring Contexts and Execlists}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhhhhhMubh)}(hMotivation: GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". These expanded contexts enable a number of new abilities, especially "Execlists" (also implemented in this file).h]hMotivation: GEN8 brings an expansion of the HW contexts: “Logical Ring Contexts”. These expanded contexts enable a number of new abilities, especially “Execlists” (also implemented in this file).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhjuhhubh)}(hOne of the main differences with the legacy HW contexts is that logical ring contexts incorporate many more things to the context's state, like PDPs or ringbuffer control registers:h]hOne of the main differences with the legacy HW contexts is that logical ring contexts incorporate many more things to the context’s state, like PDPs or ringbuffer control registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK hjuhhubh)}(hX The reason why PDPs are included in the context is straightforward: as PPGTTs (per-process GTTs) are actually per-context, having the PDPs contained there mean you don't need to do a ppgtt->switch_mm yourself, instead, the GPU will do it for you on the context switch.h]hXThe reason why PDPs are included in the context is straightforward: as PPGTTs (per-process GTTs) are actually per-context, having the PDPs contained there mean you don’t need to do a ppgtt->switch_mm yourself, instead, the GPU will do it for you on the context switch.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhjuhhubh)}(hXBut, what about the ringbuffer control registers (head, tail, etc..)? shouldn't we just need a set of those per engine command streamer? This is where the name "Logical Rings" starts to make sense: by virtualizing the rings, the engine cs shifts to a new "ring buffer" with every context switch. When you want to submit a workload to the GPU you: A) choose your context, B) find its appropriate virtualized ring, C) write commands to it and then, finally, D) tell the GPU to switch to that context.h]hXBut, what about the ringbuffer control registers (head, tail, etc..)? shouldn’t we just need a set of those per engine command streamer? This is where the name “Logical Rings” starts to make sense: by virtualizing the rings, the engine cs shifts to a new “ring buffer” with every context switch. When you want to submit a workload to the GPU you: A) choose your context, B) find its appropriate virtualized ring, C) write commands to it and then, finally, D) tell the GPU to switch to that context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhjuhhubh)}(hInstead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch to a contexts is via a context execution list, ergo "Execlists".h]hInstead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch to a contexts is via a context execution list, ergo “Execlists”.}(hj¤hhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKhjuhhubh)}(h@LRC implementation: Regarding the creation of contexts, we have:h]h@LRC implementation: Regarding the creation of contexts, we have:}(hjѤhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK hjuhhubj:)}(hhh](j:)}(hOne global default context.h]h)}(hjh]hOne global default context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK#hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h-One local default context for each opened fd.h]h)}(hjh]h-One local default context for each opened fd.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK$hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hhjuhhubh)}(hXWhen a request is committed, its commands (the BB start and any leading or trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer for the appropriate context. The tail pointer in the hardware context is not updated at this time, but instead, kept by the driver in the ringbuffer structure. A structure representing this request is added to a request queue for the appropriate engine: this structure contains a copy of the context's tail after the request was written to the ring buffer and a pointer to the context itself.h]hX!When a request is committed, its commands (the BB start and any leading or trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer for the appropriate context. The tail pointer in the hardware context is not updated at this time, but instead, kept by the driver in the ringbuffer structure. A structure representing this request is added to a request queue for the appropriate engine: this structure contains a copy of the context’s tail after the request was written to the ring buffer and a pointer to the context itself.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKChjuhhubh)}(hXQIf the engine's request queue was empty before the request was added, the queue is processed immediately. Otherwise the queue will be processed during a context switch interrupt. In any case, elements on the queue will get sent (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a globally unique 20-bits submission ID.h]hXUIf the engine’s request queue was empty before the request was added, the queue is processed immediately. Otherwise the queue will be processed during a context switch interrupt. In any case, elements on the queue will get sent (in pairs) to the GPU’s ExecLists Submit Port (ELSP, for short) with a globally unique 20-bits submission ID.}(hjƥhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKLhjuhhubh)}(hXWhen execution of a request completes, the GPU updates the context status buffer with a context complete event and generates a context switch interrupt. During the interrupt handling, the driver examines the events in the buffer: for each context complete event, if the announced ID matches that on the head of the request queue, then that request is retired and removed from the queue.h]hXWhen execution of a request completes, the GPU updates the context status buffer with a context complete event and generates a context switch interrupt. During the interrupt handling, the driver examines the events in the buffer: for each context complete event, if the announced ID matches that on the head of the request queue, then that request is retired and removed from the queue.}(hjեhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKRhjuhhubh)}(hXAfter processing, if any requests were retired and the queue is not empty then a new execution list can be submitted. The two requests at the front of the queue are next to be submitted but since a context may not occur twice in an execution list, if subsequent requests have the same ID as the first then the two requests must be combined. This is done simply by discarding requests at the head of the queue until either only one requests is left (in which case we use a NULL second context) or the first two requests have unique IDs.h]hXAfter processing, if any requests were retired and the queue is not empty then a new execution list can be submitted. The two requests at the front of the queue are next to be submitted but since a context may not occur twice in an execution list, if subsequent requests have the same ID as the first then the two requests must be combined. This is done simply by discarding requests at the head of the queue until either only one requests is left (in which case we use a NULL second context) or the first two requests have unique IDs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chKXhjuhhubh)}(hXBy always executing the first two requests in the queue the driver ensures that the GPU is kept as busy as possible. In the case where a single context completes but a second context is still executing, the request for this second context will be at the head of the queue when we remove the first one. This request will then be resubmitted along with a new request for a different context, which will cause the hardware to continue executing the second request and queue the new request (the GPU detects the condition of a context getting preempted with the same context and optimizes the context switch flow by not doing preemption, but just sampling the new tail pointer).h]hXBy always executing the first two requests in the queue the driver ensures that the GPU is kept as busy as possible. In the case where a single context completes but a second context is still executing, the request for this second context will be at the head of the queue when we remove the first one. This request will then be resubmitted along with a new request for a different context, which will cause the hardware to continue executing the second request and queue the new request (the GPU detects the condition of a context getting preempted with the same context and optimizes the context switch flow by not doing preemption, but just sampling the new tail pointer).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/gpu/i915:444: ./drivers/gpu/drm/i915/gt/intel_execlists_submission.chK`hjuhhubeh}(h]1logical-rings-logical-ring-contexts-and-execlistsah ]h"]2logical rings, logical ring contexts and execlistsah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(hGlobal GTT viewsh]hGlobal GTT views}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hBackground and previous stateh]hBackground and previous state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK&hj hhubh)}(hHistorically objects could exists (be bound) in global GTT space only as singular instances with a view representing all of the object's backing pages in a linear fashion. This view will be called a normal view.h]hHistorically objects could exists (be bound) in global GTT space only as singular instances with a view representing all of the object’s backing pages in a linear fashion. This view will be called a normal view.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK(hj hhubh)}(hTo support multiple views of the same object, where the number of mapped pages is not equal to the backing store, or where the layout of the pages is not linear, concept of a GGTT view was added.h]hTo support multiple views of the same object, where the number of mapped pages is not equal to the backing store, or where the layout of the pages is not linear, concept of a GGTT view was added.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK,hj hhubh)}(hOne example of an alternative view is a stereo display driven by a single image. In this case we would have a framebuffer looking like this (2x2 pages):h]hOne example of an alternative view is a stereo display driven by a single image. In this case we would have a framebuffer looking like this (2x2 pages):}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK0hj hhubj)}(h12 34 h]h)}(h12 34h]h12 34}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK4hjWubah}(h]h ]h"]h$]h&]uh1jhjihK4hj hhubh)}(hAbove would represent a normal GGTT view as normally mapped for GPU or CPU rendering. In contrast, fed to the display engine would be an alternative view which could look something like this:h]hAbove would represent a normal GGTT view as normally mapped for GPU or CPU rendering. In contrast, fed to the display engine would be an alternative view which could look something like this:}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK7hj hhubj)}(h 1212 3434 h]h)}(h 1212 3434h]h 1212 3434}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK;hjubah}(h]h ]h"]h$]h&]uh1jhjhK;hj hhubh)}(hlIn this example both the size and layout of pages in the alternative view is different from the normal view.h]hlIn this example both the size and layout of pages in the alternative view is different from the normal view.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhK>hj hhubh)}(hImplementation and usageh]hImplementation and usage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKAhj hhubh)}(hqGGTT views are implemented using VMAs and are distinguished via enum i915_gtt_view_type and struct i915_gtt_view.h]hqGGTT views are implemented using VMAs and are distinguished via enum i915_gtt_view_type and struct i915_gtt_view.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKChj hhubh)}(hXA new flavour of core GEM functions which work with GGTT bound objects were added with the _ggtt_ infix, and sometimes with _view postfix to avoid renaming in large amounts of code. They take the struct i915_gtt_view parameter encapsulating all metadata required to implement a view.h]hXA new flavour of core GEM functions which work with GGTT bound objects were added with the _ggtt_ infix, and sometimes with _view postfix to avoid renaming in large amounts of code. They take the struct i915_gtt_view parameter encapsulating all metadata required to implement a view.}(hjŦhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKFhj hhubh)}(hAs a helper for callers which are only interested in the normal view, globally const i915_gtt_view_normal singleton instance exists. All old core GEM API functions, the ones not taking the view parameter, are operating on, or with the normal GGTT view.h]hAs a helper for callers which are only interested in the normal view, globally const i915_gtt_view_normal singleton instance exists. All old core GEM API functions, the ones not taking the view parameter, are operating on, or with the normal GGTT view.}(hjԦhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKKhj hhubh)}(h4Code wanting to add or use a new GGTT view needs to:h]h4Code wanting to add or use a new GGTT view needs to:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKPhj hhubj:)}(hhh](j:)}(h$Add a new enum with a suitable name.h]h)}(hjh]h$Add a new enum with a suitable name.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKRhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h?Extend the metadata in the i915_gtt_view structure if required.h]h)}(hjh]h?Extend the metadata in the i915_gtt_view structure if required.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKShj ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h%Add support to i915_get_vma_pages(). h]h)}(h$Add support to i915_get_vma_pages().h]h$Add support to i915_get_vma_pages().}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKThj%ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hj hhh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhNubh)}(hNew views are required to build a scatter-gather table from within the i915_get_vma_pages function. This table is stored in the vma.gtt_view and exists for the lifetime of an VMA.h]hNew views are required to build a scatter-gather table from within the i915_get_vma_pages function. This table is stored in the vma.gtt_view and exists for the lifetime of an VMA.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKVhj hhubh)}(hCore API is designed to have copy semantics which means that passed in struct i915_gtt_view does not need to be persistent (left around after calling the core API functions).h]hCore API is designed to have copy semantics which means that passed in struct i915_gtt_view does not need to be persistent (left around after calling the core API functions).}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:450: ./drivers/gpu/drm/i915/i915_vma_types.hhKZhj hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!i915_gem_gtt_reserve (C function)c.i915_gem_gtt_reservehNtauh1jhj hhhNhNubj')}(hhh](j,)}(hint i915_gem_gtt_reserve (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h]j2)}(hint i915_gem_gtt_reserve(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h](j)}(hinth]hint}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxhhh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKGubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjxhhhjhKGubjz)}(hi915_gem_gtt_reserveh]j;)}(hi915_gem_gtt_reserveh]hi915_gem_gtt_reserve}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjxhhhjhKGubj)}(h(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 offset, unsigned long color, unsigned int flags)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjƧhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjקhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjԧubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj٧modnameN classnameNjXj[)}j^]ja)}jTjsbc.i915_gem_gtt_reserveasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hvmh]hvm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubji)}(h h]h }(hj8hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'ubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjIhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjKmodnameN classnameNjXj[)}j^]jc.i915_gem_gtt_reserveasbuh1hhj'ubji)}(h h]h }(hjghhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'ubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj;)}(hwwh]hww}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj'ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_mm_node *nodeh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h drm_mm_nodeh]h drm_mm_node}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.i915_gem_gtt_reserveasbuh1hhjubji)}(h h]h }(hjרhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hnodeh]hnode}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu64 sizeh](h)}(hhh]j;)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.i915_gem_gtt_reserveasbuh1hhjubji)}(h h]h }(hj,hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hsizeh]hsize}(hj:hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u64 offseth](h)}(hhh]j;)}(hu64h]hu64}(hjVhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjXmodnameN classnameNjXj[)}j^]jc.i915_gem_gtt_reserveasbuh1hhjOubji)}(h h]h }(hjthhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjOubj;)}(hoffseth]hoffset}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjOubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned long colorh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjũhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hcolorh]hcolor}(hjөhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int flagsh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hflagsh]hflags}(hj$hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjxhhhjhKGubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjthhhjhKGubah}(h]joah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKGhjqhhubj1)}(hhh]h)}(h(reserve a node in an address_space (GTT)h]h(reserve a node in an address_space (GTT)}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKGhjKhhubah}(h]h ]h"]h$]h&]uh1j0hjqhhhjhKGubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjfjSjfjTjUjVuh1j&hhhj hNhNubjX)}(hX**Parameters** ``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) ``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned ``u64 offset`` where to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address space ``unsigned long color`` color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE ``unsigned int flags`` control search and eviction behaviour **Description** i915_gem_gtt_reserve() tries to insert the **node** at the exact **offset** inside the address space (using **size** and **color**). If the **node** does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure. **Return** 0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h](h)}(h**Parameters**h]jb)}(hjph]h Parameters}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjnubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKKhjjubjx)}(hhh](j})}(h_``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` h](j)}(h!``struct i915_address_space *vm``h]j)}(hjh]hstruct i915_address_space *vm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKHhjubj)}(hhh]h)}(h`h](hthe }(hjhhhNhNubh)}(h8:c:type:`struct i915_address_space `h]j)}(hjh]hstruct i915_address_space}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_address_spaceuh1hhjhKHhjubeh}(h]h ]h"]h$]h&]uh1hhjhKHhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKHhjubj})}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hjh]hstruct i915_gem_ww_ctx *ww}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKIhjubj)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKIhjubj})}(hf``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) h](j)}(h``struct drm_mm_node *node``h]j)}(hj h]hstruct drm_mm_node *node}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKJhjubj)}(hhh]h)}(hHthe :c:type:`struct drm_mm_node ` (typically i915_vma.node)h](hthe }(hj9hhhNhNubh)}(h*:c:type:`struct drm_mm_node `h]j)}(hjCh]hstruct drm_mm_node}(hjEhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjj drm_mm_nodeuh1hhj5hKJhj9ubh (typically i915_vma.node)}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj5hKJhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj5hKJhjubj})}(h\``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned h](j)}(h ``u64 size``h]j)}(hj|h]hu64 size}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKLhjvubj)}(hhh]h)}(hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE alignedh]hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKKhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1j|hjhKLhjubj})}(h``u64 offset`` where to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address space h](j)}(h``u64 offset``h]j)}(hjh]h u64 offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKOhjubj)}(hhh]h)}(hwhere to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (**offset** + **size**) must fit within the address spaceh](hWwhere to insert inside the GTT, must be #I915_GTT_MIN_ALIGNMENT aligned, and the node (}(hjϫhhhNhNubjb)}(h **offset**h]hoffset}(hj׫hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjϫubh + }(hjϫhhhNhNubjb)}(h**size**h]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjϫubh#) must fit within the address space}(hjϫhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKMhj̫ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj˫hKOhjubj})}(hv``unsigned long color`` color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE h](j)}(h``unsigned long color``h]j)}(hjh]hunsigned long color}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKQhjubj)}(hhh]h)}(h]color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLEh]h]color to apply to node, if this node is not from a VMA, color must be #I915_COLOR_UNEVICTABLE}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKPhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj)hKQhjubj})}(h=``unsigned int flags`` control search and eviction behaviour h](j)}(h``unsigned int flags``h]j)}(hjNh]hunsigned int flags}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKRhjHubj)}(hhh]h)}(h%control search and eviction behaviourh]h%control search and eviction behaviour}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchKRhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1j|hjchKRhjubeh}(h]h ]h"]h$]h&]uh1jwhjjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKThjjubh)}(hXEi915_gem_gtt_reserve() tries to insert the **node** at the exact **offset** inside the address space (using **size** and **color**). If the **node** does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure.h](h+i915_gem_gtt_reserve() tries to insert the }(hjhhhNhNubjb)}(h**node**h]hnode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh at the exact }(hjhhhNhNubjb)}(h **offset**h]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh! inside the address space (using }(hjhhhNhNubjb)}(h**size**h]hsize}(hjˬhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and }(hjhhhNhNubjb)}(h **color**h]hcolor}(hjݬhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh ). If the }(hjhhhNhNubjb)}(h**node**h]hnode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubhX does not fit, it tries to evict any overlapping nodes from the GTT, including any neighbouring nodes if the colors do not match (to ensure guard pages between differing domains). See i915_gem_evict_for_node() for the gory details on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on evicting active overlapping objects, and any overlapping node that is pinned or marked as unevictable will also result in failure.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKThjjubh)}(h **Return**h]jb)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chK]hjjubh)}(hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h]hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chK]hjjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_gtt_insert (C function)c.i915_gem_gtt_inserthNtauh1jhj hhhNhNubj')}(hhh](j,)}(hint i915_gem_gtt_insert (struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h]j2)}(hint i915_gem_gtt_insert(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h](j)}(hinth]hint}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKhhh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKubji)}(h h]h }(hj^hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKhhhj]hKubjz)}(hi915_gem_gtt_inserth]j;)}(hi915_gem_gtt_inserth]hi915_gem_gtt_insert}(hjphhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjlubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjKhhhj]hKubj)}(h(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww, struct drm_mm_node *node, u64 size, u64 alignment, unsigned long color, u64 start, u64 end, unsigned int flags)h](j)}(hstruct i915_address_space *vmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hi915_address_spaceh]hi915_address_space}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjrsbc.i915_gem_gtt_insertasbuh1hhjubji)}(h h]h }(hjʭhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjحhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hvmh]hvm}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct i915_gem_ww_ctx *wwh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hi915_gem_ww_ctxh]hi915_gem_ww_ctx}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jƭc.i915_gem_gtt_insertasbuh1hhjubji)}(h h]h }(hj:hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hwwh]hww}(hjUhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_mm_node *nodeh](j)}(hjh]hstruct}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubji)}(h h]h }(hj{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjjubh)}(hhh]j;)}(h drm_mm_nodeh]h drm_mm_node}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jƭc.i915_gem_gtt_insertasbuh1hhjjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj;)}(hnodeh]hnode}(hjŮhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu64 sizeh](h)}(hhh]j;)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjޮubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jƭc.i915_gem_gtt_insertasbuh1hhjڮubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjڮubj;)}(hsizeh]hsize}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjڮubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u64 alignmenth](h)}(hhh]j;)}(hu64h]hu64}(hj)hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj&ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj+modnameN classnameNjXj[)}j^]jƭc.i915_gem_gtt_insertasbuh1hhj"ubji)}(h h]h }(hjGhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj"ubj;)}(h alignmenth]h alignment}(hjUhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj"ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned long colorh](j)}(hunsignedh]hunsigned}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubji)}(h h]h }(hj|hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjjubj)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjjubj;)}(hcolorh]hcolor}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h u64 starth](h)}(hhh]j;)}(hu64h]hu64}(hj¯hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjįmodnameN classnameNjXj[)}j^]jƭc.i915_gem_gtt_insertasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hstarth]hstart}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu64 endh](h)}(hhh]j;)}(hu64h]hu64}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jƭc.i915_gem_gtt_insertasbuh1hhjubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hendh]hend}(hj6hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int flagsh](j)}(hunsignedh]hunsigned}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hj]hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj)}(hinth]hint}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubji)}(h h]h }(hjyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjKubj;)}(hflagsh]hflags}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjKubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjKhhhj]hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjGhhhj]hKubah}(h]jBah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj]hKhjDhhubj1)}(hhh]h)}(h)insert a node into an address_space (GTT)h]h)insert a node into an address_space (GTT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjhhubah}(h]h ]h"]h$]h&]uh1j0hjDhhhj]hKubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjɰjSjɰjTjUjVuh1j&hhhj hNhNubjX)}(hX**Parameters** ``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` ``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. ``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) ``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned ``u64 alignment`` required alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENT ``unsigned long color`` color to apply to node ``u64 start`` start of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned ``u64 end`` end of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX ``unsigned int flags`` control search and eviction behaviour **Description** i915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to **alignment** and its **size** must then fit entirely within the [**start**, **end**] bounds. The nodes on either side of the hole must match **color**, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node's VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm. **Return** 0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h](h)}(h**Parameters**h]jb)}(hjӰh]h Parameters}(hjհhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjѰubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjͰubjx)}(hhh](j})}(h_``struct i915_address_space *vm`` the :c:type:`struct i915_address_space ` h](j)}(h!``struct i915_address_space *vm``h]j)}(hjh]hstruct i915_address_space *vm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj)}(hhh]h)}(h`h](hthe }(hj hhhNhNubh)}(h8:c:type:`struct i915_address_space `h]j)}(hjh]hstruct i915_address_space}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjji915_address_spaceuh1hhjhKhj ubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hC``struct i915_gem_ww_ctx *ww`` An optional struct i915_gem_ww_ctx. h](j)}(h``struct i915_gem_ww_ctx *ww``h]j)}(hjJh]hstruct i915_gem_ww_ctx *ww}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjDubj)}(hhh]h)}(h#An optional struct i915_gem_ww_ctx.h]h#An optional struct i915_gem_ww_ctx.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j|hj_hKhjubj})}(hf``struct drm_mm_node *node`` the :c:type:`struct drm_mm_node ` (typically i915_vma.node) h](j)}(h``struct drm_mm_node *node``h]j)}(hjh]hstruct drm_mm_node *node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj}ubj)}(hhh]h)}(hHthe :c:type:`struct drm_mm_node ` (typically i915_vma.node)h](hthe }(hjhhhNhNubh)}(h*:c:type:`struct drm_mm_node `h]j)}(hjh]hstruct drm_mm_node}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjj drm_mm_nodeuh1hhjhKhjubh (typically i915_vma.node)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h\``u64 size`` how much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned h](j)}(h ``u64 size``h]j)}(hj߱h]hu64 size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjݱubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjٱubj)}(hhh]h)}(hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE alignedh]hNhow much space to allocate inside the GTT, must be #I915_GTT_PAGE_SIZE aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubah}(h]h ]h"]h$]h&]uh1jhjٱubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``u64 alignment`` required alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENT h](j)}(h``u64 alignment``h]j)}(hjh]h u64 alignment}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj)}(hhh]h)}(hrequired alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENTh]hrequired alignment of starting offset, may be 0 but if specified, this must be a power-of-two and at least #I915_GTT_MIN_ALIGNMENT}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj.hKhjubj})}(h/``unsigned long color`` color to apply to node h](j)}(h``unsigned long color``h]j)}(hjSh]hunsigned long color}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjMubj)}(hhh]h)}(hcolor to apply to nodeh]hcolor to apply to node}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhKhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j|hjhhKhjubj})}(hi``u64 start`` start of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned h](j)}(h ``u64 start``h]j)}(hjh]h u64 start}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj)}(hhh]h)}(hZstart of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE alignedh]hZstart of any range restriction inside GTT (0 for all), must be #I915_GTT_PAGE_SIZE aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hz``u64 end`` end of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX h](j)}(h ``u64 end``h]j)}(hjƲh]hu64 end}(hjȲhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIJubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj)}(hhh]h)}(hmend of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAXh]hmend of any range restriction inside GTT (U64_MAX for all), must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX}(hj߲hhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjܲubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj۲hKhjubj})}(h=``unsigned int flags`` control search and eviction behaviour h](j)}(h``unsigned int flags``h]j)}(hjh]hunsigned int flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjubj)}(hhh]h)}(h%control search and eviction behaviourh]h%control search and eviction behaviour}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubeh}(h]h ]h"]h$]h&]uh1jwhjͰubh)}(h**Description**h]jb)}(hj;h]h Description}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj9ubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjͰubh)}(hXi915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to **alignment** and its **size** must then fit entirely within the [**start**, **end**] bounds. The nodes on either side of the hole must match **color**, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node's VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm.h](h}i915_gem_gtt_insert() first searches for an available hole into which is can insert the node. The hole address is aligned to }(hjQhhhNhNubjb)}(h **alignment**h]h alignment}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjQubh and its }(hjQhhhNhNubjb)}(h**size**h]hsize}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjQubh$ must then fit entirely within the [}(hjQhhhNhNubjb)}(h **start**h]hstart}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjQubh, }(hjQhhhNhNubjb)}(h**end**h]hend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjQubh:] bounds. The nodes on either side of the hole must match }(hjQhhhNhNubjb)}(h **color**h]hcolor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjQubhX, or else a guard page will be inserted between the two nodes (or the node evicted). If no suitable hole is found, first a victim is randomly selected and tested for eviction, otherwise then the LRU list of objects within the GTT is scanned to find the first set of replacement nodes to create the hole. Those old overlapping nodes are evicted from the GTT (and so must be rebound before any future use). Any node that is currently pinned cannot be evicted (see i915_vma_pin()). Similar if the node’s VMA is currently active and #PIN_NONBLOCK is specified, that node is also skipped when searching for an eviction candidate. See i915_gem_evict_something() for the gory details on the eviction algorithm.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjͰubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjͰubh)}(hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.h]hi0 on success, -ENOSPC if no suitable hole is found, -EINTR if asked to wait for eviction and interrupted.}(hjҳhhhNhNubah}(h]h ]h"]h$]h&]uh1hh]/var/lib/git/docbuild/linux/Documentation/gpu/i915:453: ./drivers/gpu/drm/i915/i915_gem_gtt.chKhjͰubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj hhhNhNubeh}(h]global-gtt-viewsah ]h"]global gtt viewsah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(hGTT Fences and Swizzlingh]hGTT Fences and Swizzling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""i915_vma_revoke_fence (C function)c.i915_vma_revoke_fencehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h1void i915_vma_revoke_fence (struct i915_vma *vma)h]j2)}(h0void i915_vma_revoke_fence(struct i915_vma *vma)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj(hMubjz)}(hi915_vma_revoke_fenceh]j;)}(hi915_vma_revoke_fenceh]hi915_vma_revoke_fence}(hj;hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj7ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj(hMubj)}(h(struct i915_vma *vma)h]j)}(hstruct i915_vma *vmah](j)}(hjh]hstruct}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubji)}(h h]h }(hjdhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjuhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjrubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjwmodnameN classnameNjXj[)}j^]ja)}jTj=sbc.i915_vma_revoke_fenceasbuh1hhjSubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjSubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubj;)}(hvmah]hvma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjSubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjOubah}(h]h ]h"]h$]h&]jjuh1jhjhhhj(hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj(hMubah}(h]j ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj(hMhjhhubj1)}(hhh]h)}(hforce-remove fence for a VMAh]hforce-remove fence for a VMA}(hjڴhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj״hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj(hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct i915_vma *vma`` vma to map linearly (not through a fence reg) **Description** This function force-removes any fence from the given object, which is useful if the kernel wants to do untiled GTT access.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM!hjubjx)}(hhh]j})}(hG``struct i915_vma *vma`` vma to map linearly (not through a fence reg) h](j)}(h``struct i915_vma *vma``h]j)}(hjh]hstruct i915_vma *vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(h-vma to map linearly (not through a fence reg)h]h-vma to map linearly (not through a fence reg)}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj0hMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjVh]h Description}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjTubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM hjubh)}(hzThis function force-removes any fence from the given object, which is useful if the kernel wants to do untiled GTT access.h]hzThis function force-removes any fence from the given object, which is useful if the kernel wants to do untiled GTT access.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_vma_pin_fence (C function)c.i915_vma_pin_fencehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h-int i915_vma_pin_fence (struct i915_vma *vma)h]j2)}(h,int i915_vma_pin_fence(struct i915_vma *vma)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hi915_vma_pin_fenceh]j;)}(hi915_vma_pin_fenceh]hi915_vma_pin_fence}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct i915_vma *vma)h]j)}(hstruct i915_vma *vmah](j)}(hjh]hstruct}(hjصhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjԵubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjԵubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.i915_vma_pin_fenceasbuh1hhjԵubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjԵubj)}(hjh]h*}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjԵubj;)}(hvmah]hvma}(hj1hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjԵubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjеubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hset up fencing for a vmah]hset up fencing for a vma}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjXhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjsjSjsjTjUjVuh1j&hhhjhNhNubjX)}(hX)**Parameters** ``struct i915_vma *vma`` vma to map through a fence reg **Description** When mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for **obj**, stealing one if it can't find any. It then sets up the reg based on the object's properties: address, pitch and tiling format. For an untiled surface, this removes any existing fence. **Return** 0 on success, negative error code on failure.h](h)}(h**Parameters**h]jb)}(hj}h]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj{ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjwubjx)}(hhh]j})}(h8``struct i915_vma *vma`` vma to map through a fence reg h](j)}(h``struct i915_vma *vma``h]j)}(hjh]hstruct i915_vma *vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(hvma to map through a fence regh]hvma to map through a fence reg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubah}(h]h ]h"]h$]h&]uh1jwhjwubh)}(h**Description**h]jb)}(hj׶h]h Description}(hjٶhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjնubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjwubh)}(hWhen mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for **obj**, stealing one if it can't find any.h](hWhen mapping objects through the GTT, userspace wants to be able to write to them without having to worry about swizzling if the object is tiled. This function walks the fence regs looking for a free one for }(hjhhhNhNubjb)}(h**obj**h]hobj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh&, stealing one if it can’t find any.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjwubh)}(h[It then sets up the reg based on the object's properties: address, pitch and tiling format.h]h]It then sets up the reg based on the object’s properties: address, pitch and tiling format.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjwubh)}(h8For an untiled surface, this removes any existing fence.h]h8For an untiled surface, this removes any existing fence.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjwubh)}(h **Return**h]jb)}(hj.h]hReturn}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjwubh)}(h-0 on success, negative error code on failure.h]h-0 on success, negative error code on failure.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjwubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_reserve_fence (C function)c.i915_reserve_fencehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hCstruct i915_fence_reg * i915_reserve_fence (struct i915_ggtt *ggtt)h]j2)}(hAstruct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt)h](j)}(hjh]hstruct}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjohhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjohhhjhMubh)}(hhh]j;)}(hi915_fence_regh]hi915_fence_reg}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTi915_reserve_fencesbc.i915_reserve_fenceasbuh1hhjohhhjhMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjohhhjhMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjohhhjhMubjz)}(hi915_reserve_fenceh]j;)}(hjh]hi915_reserve_fence}(hjҷhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjηubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjohhhjhMubj)}(h(struct i915_ggtt *ggtt)h]j)}(hstruct i915_ggtt *ggtth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h i915_ggtth]h i915_ggtt}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jc.i915_reserve_fenceasbuh1hhjubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hggtth]hggtt}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjohhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjkhhhjhMubah}(h]jfah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhhubj1)}(hhh]h)}(hReserve a fence for vGPUh]hReserve a fence for vGPU}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjkhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct i915_ggtt *ggtt`` Global GTT **Description** This function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubjx)}(hhh]j})}(h&``struct i915_ggtt *ggtt`` Global GTT h](j)}(h``struct i915_ggtt *ggtt``h]j)}(hjh]hstruct i915_ggtt *ggtt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(h Global GTTh]h Global GTT}(hjȸhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjĸhMhjŸubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjĸhMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hThis function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.h]hThis function walks the fence regs looking for a free one and remove it from the fence_list. It is used to reserve fence for vGPU to use.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!i915_unreserve_fence (C function)c.i915_unreserve_fencehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h8void i915_unreserve_fence (struct i915_fence_reg *fence)h]j2)}(h7void i915_unreserve_fence(struct i915_fence_reg *fence)h](j)}(hvoidh]hvoid}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hj>hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj+hhhj=hMubjz)}(hi915_unreserve_fenceh]j;)}(hi915_unreserve_fenceh]hi915_unreserve_fence}(hjPhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjLubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj+hhhj=hMubj)}(h(struct i915_fence_reg *fence)h]j)}(hstruct i915_fence_reg *fenceh](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubji)}(h h]h }(hjyhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhubh)}(hhh]j;)}(hi915_fence_regh]hi915_fence_reg}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjRsbc.i915_unreserve_fenceasbuh1hhjhubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj;)}(hfenceh]hfence}(hjŹhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjhubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjdubah}(h]h ]h"]h$]h&]jjuh1jhj+hhhj=hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj'hhhj=hMubah}(h]j"ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj=hMhj$hhubj1)}(hhh]h)}(hReclaim a reserved fenceh]hReclaim a reserved fence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj$hhhj=hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct i915_fence_reg *fence`` the fence reg **Description** This function add a reserved fence register from vGPU to the fence_list.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj ubjx)}(hhh]j})}(h/``struct i915_fence_reg *fence`` the fence reg h](j)}(h ``struct i915_fence_reg *fence``h]j)}(hj0h]hstruct i915_fence_reg *fence}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj*ubj)}(hhh]h)}(h the fence regh]h the fence reg}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1j|hjEhMhj'ubah}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjkh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjiubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj ubh)}(hHThis function add a reserved fence register from vGPU to the fence_list.h]hHThis function add a reserved fence register from vGPU to the fence_list.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&intel_ggtt_restore_fences (C function)c.intel_ggtt_restore_fenceshNtauh1jhjhhhNhNubj')}(hhh](j,)}(h7void intel_ggtt_restore_fences (struct i915_ggtt *ggtt)h]j2)}(h6void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_ggtt_restore_fencesh]j;)}(hintel_ggtt_restore_fencesh]hintel_ggtt_restore_fences}(hjѺhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjͺubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h(struct i915_ggtt *ggtt)h]j)}(hstruct i915_ggtt *ggtth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h i915_ggtth]h i915_ggtt}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]ja)}jTjӺsbc.intel_ggtt_restore_fencesasbuh1hhjubji)}(h h]h }(hj+hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hggtth]hggtt}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hrestore fence stateh]hrestore fence state}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjmhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct i915_ggtt *ggtt`` Global GTT **Description** Restore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubjx)}(hhh]j})}(h&``struct i915_ggtt *ggtt`` Global GTT h](j)}(h``struct i915_ggtt *ggtt``h]j)}(hjh]hstruct i915_ggtt *ggtt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(h Global GTTh]h Global GTT}(hjʻhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjƻhMhjǻubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjƻhMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hRestore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.h]hRestore the hw fence state to match the software tracking again, to be called after a gpu reset and on resume. Note that on runtime suspend we only cancel the fences, to be reacquired by the user later.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!detect_bit_6_swizzle (C function)c.detect_bit_6_swizzlehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h2void detect_bit_6_swizzle (struct i915_ggtt *ggtt)h]j2)}(h1void detect_bit_6_swizzle(struct i915_ggtt *ggtt)h](j)}(hvoidh]hvoid}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-hhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM6ubji)}(h h]h }(hj@hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj-hhhj?hM6ubjz)}(hdetect_bit_6_swizzleh]j;)}(hdetect_bit_6_swizzleh]hdetect_bit_6_swizzle}(hjRhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjNubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj-hhhj?hM6ubj)}(h(struct i915_ggtt *ggtt)h]j)}(hstruct i915_ggtt *ggtth](j)}(hjh]hstruct}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubji)}(h h]h }(hj{hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjjubh)}(hhh]j;)}(h i915_ggtth]h i915_ggtt}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjTsbc.detect_bit_6_swizzleasbuh1hhjjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj;)}(hggtth]hggtt}(hjǼhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjfubah}(h]h ]h"]h$]h&]jjuh1jhj-hhhj?hM6ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj)hhhj?hM6ubah}(h]j$ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj?hM6hj&hhubj1)}(hhh]h)}(hdetect bit 6 swizzling patternh]hdetect bit 6 swizzling pattern}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM6hjhhubah}(h]h ]h"]h$]h&]uh1j0hj&hhhj?hM6ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj jSj jTjUjVuh1j&hhhjhNhNubjX)}(h**Parameters** ``struct i915_ggtt *ggtt`` Global GGTT **Description** Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM:hj ubjx)}(hhh]j})}(h'``struct i915_ggtt *ggtt`` Global GGTT h](j)}(h``struct i915_ggtt *ggtt``h]j)}(hj2h]hstruct i915_ggtt *ggtt}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM7hj,ubj)}(hhh]h)}(h Global GGTTh]h Global GGTT}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhM7hjHubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1j|hjGhM7hj)ubah}(h]h ]h"]h$]h&]uh1jwhj ubh)}(h**Description**h]jb)}(hjmh]h Description}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jahjkubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM9hj ubh)}(h`Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.h]h`Detects bit 6 swizzling of address lookup between IGD access and CPU access through main memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM9hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j".i915_gem_object_do_bit_17_swizzle (C function)#c.i915_gem_object_do_bit_17_swizzlehNtauh1jhjhhhNhNubj')}(hhh](j,)}(h`void i915_gem_object_do_bit_17_swizzle (struct drm_i915_gem_object *obj, struct sg_table *pages)h]j2)}(h_void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(h!i915_gem_object_do_bit_17_swizzleh]j;)}(h!i915_gem_object_do_bit_17_swizzleh]h!i915_gem_object_do_bit_17_swizzle}(hjӽhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjϽubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h9(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjսsb#c.i915_gem_object_do_bit_17_swizzleasbuh1hhjubji)}(h h]h }(hj-hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hobjh]hobj}(hjHhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct sg_table *pagesh](j)}(hjh]hstruct}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubji)}(h h]h }(hjnhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]ubh)}(hhh]j;)}(hsg_tableh]hsg_table}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j)#c.i915_gem_object_do_bit_17_swizzleasbuh1hhj]ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj]ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj;)}(hpagesh]hpages}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj]ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hfixup bit 17 swizzlingh]hfixup bit 17 swizzling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj߾hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct drm_i915_gem_object *obj`` i915 GEM buffer object ``struct sg_table *pages`` the scattergather list of physical pages **Description** This function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle(). This is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubjx)}(hhh](j})}(h;``struct drm_i915_gem_object *obj`` i915 GEM buffer object h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hj#h]hstruct drm_i915_gem_object *obj}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubj)}(hhh]h)}(hi915 GEM buffer objecth]hi915 GEM buffer object}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj8hMhjubj})}(hD``struct sg_table *pages`` the scattergather list of physical pages h](j)}(h``struct sg_table *pages``h]j)}(hj\h]hstruct sg_table *pages}(hj^hhh.NhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjVubj)}(hhh]h)}(h(the scattergather list of physical pagesh]h(the scattergather list of physical pages}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhMhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j|hjqhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hThis function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle().h]hThis function fixes up the swizzling in case any page frame number for this object has changed in bit 17 since that state has been saved with i915_gem_object_save_bit_17_swizzle().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubh)}(hThis is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).h]hThis is called when pinning backing storage again, since the kernel is free to move unpinned backing storage around (either by directly moving pages or by swapping them out and back in again).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"0i915_gem_object_save_bit_17_swizzle (C function)%c.i915_gem_object_save_bit_17_swizzlehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hbvoid i915_gem_object_save_bit_17_swizzle (struct drm_i915_gem_object *obj, struct sg_table *pages)h]j2)}(havoid i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM"ubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhM"ubjz)}(h#i915_gem_object_save_bit_17_swizzleh]j;)}(h#i915_gem_object_save_bit_17_swizzleh]h#i915_gem_object_save_bit_17_swizzle}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhM"ubj)}(h9(struct drm_i915_gem_object *obj, struct sg_table *pages)h](j)}(hstruct drm_i915_gem_object *objh](j)}(hjh]hstruct}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubh)}(hhh]j;)}(hdrm_i915_gem_objecth]hdrm_i915_gem_object}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjHmodnameN classnameNjXj[)}j^]ja)}jTjsb%c.i915_gem_object_save_bit_17_swizzleasbuh1hhj$ubji)}(h h]h }(hjfhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj$ubj)}(hjh]h*}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj;)}(hobjh]hobj}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(hstruct sg_table *pagesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hsg_tableh]hsg_table}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jb%c.i915_gem_object_save_bit_17_swizzleasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hpagesh]hpages}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhM"ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhM"ubah}(h]j޿ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhM"hjhhubj1)}(hhh]h)}(hsave bit 17 swizzlingh]hsave bit 17 swizzling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM"hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhM"ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj3jSj3jTjUjVuh1j&hhhjhNhNubjX)}(hXs**Parameters** ``struct drm_i915_gem_object *obj`` i915 GEM buffer object ``struct sg_table *pages`` the scattergather list of physical pages **Description** This function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.h](h)}(h**Parameters**h]jb)}(hj=h]h Parameters}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj;ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hj7ubjx)}(hhh](j})}(h;``struct drm_i915_gem_object *obj`` i915 GEM buffer object h](j)}(h#``struct drm_i915_gem_object *obj``h]j)}(hj\h]hstruct drm_i915_gem_object *obj}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM#hjVubj)}(hhh]h)}(hi915 GEM buffer objecth]hi915 GEM buffer object}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhM#hjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j|hjqhM#hjSubj})}(hD``struct sg_table *pages`` the scattergather list of physical pages h](j)}(h``struct sg_table *pages``h]j)}(hjh]hstruct sg_table *pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM$hjubj)}(hhh]h)}(h(the scattergather list of physical pagesh]h(the scattergather list of physical pages}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM$hjSubeh}(h]h ]h"]h$]h&]uh1jwhj7ubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hj7ubh)}(hThis function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.h]hThis function saves the bit 17 of each page frame number so that swizzling can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must be called before the backing storage can be unpinned.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:459: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubh)}(hhh](h)}(hGlobal GTT Fence Handlingh]hGlobal GTT Fence Handling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hImportant to avoid confusions: "fences" in the i915 driver are not execution fences used to track command completion but hardware detiler objects which wrap a given range of the global GTT. Each platform has only a fairly limited set of these objects.h]hImportant to avoid confusions: “fences” in the i915 driver are not execution fences used to track command completion but hardware detiler objects which wrap a given range of the global GTT. Each platform has only a fairly limited set of these objects.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chKhjhhubh)}(hXFences are used to detile GTT memory mappings. They're also connected to the hardware frontbuffer render tracking and hence interact with frontbuffer compression. Furthermore on older platforms fences are required for tiled objects used by the display engine. They can also be used by the render engine - they're required for blitter commands and are optional for render commands. But on gen4+ both display (with the exception of fbc) and rendering have their own tiling state bits and don't need fences.h]hXFences are used to detile GTT memory mappings. They’re also connected to the hardware frontbuffer render tracking and hence interact with frontbuffer compression. Furthermore on older platforms fences are required for tiled objects used by the display engine. They can also be used by the render engine - they’re required for blitter commands and are optional for render commands. But on gen4+ both display (with the exception of fbc) and rendering have their own tiling state bits and don’t need fences.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chKhjhhubh)}(hAlso note that fences only support X and Y tiling and hence can't be used for the fancier new tiling formats like W, Ys and Yf.h]hAlso note that fences only support X and Y tiling and hence can’t be used for the fancier new tiling formats like W, Ys and Yf.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chKhjhhubh)}(hXFinally note that because fences are such a restricted resource they're dynamically associated with objects. Furthermore fence state is committed to the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must explicitly call i915_gem_object_get_fence() to synchronize fencing status for cpu access. Also note that some code wants an unfenced view, for those cases the fence can be removed forcefully with i915_gem_object_put_fence().h]hXFinally note that because fences are such a restricted resource they’re dynamically associated with objects. Furthermore fence state is committed to the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must explicitly call i915_gem_object_get_fence() to synchronize fencing status for cpu access. Also note that some code wants an unfenced view, for those cases the fence can be removed forcefully with i915_gem_object_put_fence().}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chK"hjhhubh)}(hInternally these functions will synchronize with userspace access by removing CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.h]hInternally these functions will synchronize with userspace access by removing CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:465: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chK)hjhhubeh}(h]global-gtt-fence-handlingah ]h"]global gtt fence handlingah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h%Hardware Tiling and Swizzling Detailsh]h%Hardware Tiling and Swizzling Details}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hhhhhMubh)}(hThe idea behind tiling is to increase cache hit rates by rearranging pixel data so that a group of pixel accesses are in the same cacheline. Performance improvement from doing this on the back/depth buffer are on the order of 30%.h]hThe idea behind tiling is to increase cache hit rates by rearranging pixel data so that a group of pixel accesses are in the same cacheline. Performance improvement from doing this on the back/depth buffer are on the order of 30%.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj`hhubh)}(hXMIntel architectures make this somewhat more complicated, though, by adjustments made to addressing of data when the memory is in interleaved mode (matched pairs of DIMMS) to improve memory bandwidth. For interleaved memory, the CPU sends every sequential 64 bytes to an alternate memory channel so it can get the bandwidth from both.h]hXMIntel architectures make this somewhat more complicated, though, by adjustments made to addressing of data when the memory is in interleaved mode (matched pairs of DIMMS) to improve memory bandwidth. For interleaved memory, the CPU sends every sequential 64 bytes to an alternate memory channel so it can get the bandwidth from both.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM hj`hhubh)}(hXThe GPU also rearranges its accesses for increased bandwidth to interleaved memory, and it matches what the CPU does for non-tiled. However, when tiled it does it a little differently, since one walks addresses not just in the X direction but also Y. So, along with alternating channels when bit 6 of the address flips, it also alternates when other bits flip -- Bits 9 (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) are common to both the 915 and 965-class hardware.h]hXThe GPU also rearranges its accesses for increased bandwidth to interleaved memory, and it matches what the CPU does for non-tiled. However, when tiled it does it a little differently, since one walks addresses not just in the X direction but also Y. So, along with alternating channels when bit 6 of the address flips, it also alternates when other bits flip -- Bits 9 (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) are common to both the 915 and 965-class hardware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj`hhubh)}(hX*The CPU also sometimes XORs in higher bits as well, to improve bandwidth doing strided access like we do so frequently in graphics. This is called "Channel XOR Randomization" in the MCH documentation. The result is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address decode.h]hX.The CPU also sometimes XORs in higher bits as well, to improve bandwidth doing strided access like we do so frequently in graphics. This is called “Channel XOR Randomization” in the MCH documentation. The result is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address decode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj`hhubh)}(hAll of this bit 6 XORing has an effect on our memory management, as we need to make sure that the 3d driver can correctly address object contents.h]hAll of this bit 6 XORing has an effect on our memory management, as we need to make sure that the 3d driver can correctly address object contents.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chMhj`hhubh)}(hUIf we don't have interleaved memory, all tiling is safe and no swizzling is required.h]hWIf we don’t have interleaved memory, all tiling is safe and no swizzling is required.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM#hj`hhubh)}(hWhen bit 17 is XORed in, we simply refuse to tile at all. Bit 17 is not just a page offset, so as we page an object out and back in, individual pages in it will have different bit 17 addresses, resulting in each 64 bytes being swapped with its neighbor!h]hWhen bit 17 is XORed in, we simply refuse to tile at all. Bit 17 is not just a page offset, so as we page an object out and back in, individual pages in it will have different bit 17 addresses, resulting in each 64 bytes being swapped with its neighbor!}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM&hj`hhubh)}(hXOtherwise, if interleaved, we have to tell the 3d driver what the address swizzling it needs to do is, since it's writing with the CPU to the pages (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order to match what the GPU expects.h]hXOtherwise, if interleaved, we have to tell the 3d driver what the address swizzling it needs to do is, since it’s writing with the CPU to the pages (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order to match what the GPU expects.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:471: ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.chM+hj`hhubeh}(h]%hardware-tiling-and-swizzling-detailsah ]h"]%hardware tiling and swizzling detailsah$]h&]uh1hhjhhhhhMubeh}(h]gtt-fences-and-swizzlingah ]h"]gtt fences and swizzlingah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(hObject Tiling IOCTLsh]hObject Tiling IOCTLs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" i915_gem_fence_size (C function)c.i915_gem_fence_sizehNtauh1jhjhhhNhNubj')}(hhh](j,)}(hku32 i915_gem_fence_size (struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h]j2)}(hju32 i915_gem_fence_size(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](h)}(hhh]j;)}(hu32h]hu32}(hj&hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj#ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj(modnameN classnameNjXj[)}j^]ja)}jTi915_gem_fence_sizesbc.i915_gem_fence_sizeasbuh1hhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK-ubji)}(h h]h }(hjHhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjGhK-ubjz)}(hi915_gem_fence_sizeh]j;)}(hjDh]hi915_gem_fence_size}(hjZhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjVubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjGhK-ubj)}(hS(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jBc.i915_gem_fence_sizeasbuh1hhjqubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj;)}(hi915h]hi915}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjqubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjmubj)}(hu32 sizeh](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jBc.i915_gem_fence_sizeasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjmubj)}(hunsigned int tilingh](j)}(hunsignedh]hunsigned}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubji)}(h h]h }(hj;hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)ubj)}(hinth]hint}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubji)}(h h]h }(hjWhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)ubj;)}(htilingh]htiling}(hjehhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj)ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjmubj)}(hunsigned int strideh](j)}(hunsignedh]hunsigned}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjzubj;)}(hstrideh]hstride}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjzubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjmubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjGhK-ubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjGhK-ubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjGhK-hjhhubj1)}(hhh]h)}(h$required global GTT size for a fenceh]h$required global GTT size for a fence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK-hjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjGhK-ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX=**Parameters** ``struct drm_i915_private *i915`` i915 device ``u32 size`` object size ``unsigned int tiling`` tiling mode ``unsigned int stride`` tiling stride **Description** Return the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK1hjubjx)}(hhh](j})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hj!h]hstruct drm_i915_private *i915}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK.hjubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hK.hj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj6hK.hjubj})}(h``u32 size`` object size h](j)}(h ``u32 size``h]j)}(hjZh]hu32 size}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK/hjTubj)}(hhh]h)}(h object sizeh]h object size}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohK/hjpubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j|hjohK/hjubj})}(h$``unsigned int tiling`` tiling mode h](j)}(h``unsigned int tiling``h]j)}(hjh]hunsigned int tiling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK0hjubj)}(hhh]h)}(h tiling modeh]h tiling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK0hjubj})}(h&``unsigned int stride`` tiling stride h](j)}(h``unsigned int stride``h]j)}(hjh]hunsigned int stride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK1hjubj)}(hhh]h)}(h tiling strideh]h tiling stride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK1hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK1hjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK3hjubh)}(hReturn the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.h]hReturn the required global GTT size for a fence (view of a tiled object), taking into account potential fence register mapping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK3hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%i915_gem_fence_alignment (C function)c.i915_gem_fence_alignmenthNtauh1jhjhhhNhNubj')}(hhh](j,)}(hpu32 i915_gem_fence_alignment (struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h]j2)}(hou32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](h)}(hhh]j;)}(hu32h]hu32}(hjOhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjLubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjQmodnameN classnameNjXj[)}j^]ja)}jTi915_gem_fence_alignmentsbc.i915_gem_fence_alignmentasbuh1hhjHhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKUubji)}(h h]h }(hjqhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjHhhhjphKUubjz)}(hi915_gem_fence_alignmenth]j;)}(hjmh]hi915_gem_fence_alignment}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjHhhhjphKUubj)}(hS(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride)h](j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jkc.i915_gem_fence_alignmentasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hi915h]hi915}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hu32 sizeh](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jkc.i915_gem_fence_alignmentasbuh1hhj ubji)}(h h]h }(hj/hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj;)}(hsizeh]hsize}(hj=hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int tilingh](j)}(hunsignedh]hunsigned}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubji)}(h h]h }(hjdhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj)}(hinth]hint}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjRubj;)}(htilingh]htiling}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjRubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hunsigned int strideh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hstrideh]hstride}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjHhhhjphKUubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjDhhhjphKUubah}(h]j?ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjphKUhjAhhubj1)}(hhh]h)}(h)required global GTT alignment for a fenceh]h)required global GTT alignment for a fence}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKUhjhhubah}(h]h ]h"]h$]h&]uh1j0hjAhhhjphKUubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj!jSj!jTjUjVuh1j&hhhjhNhNubjX)}(hXD**Parameters** ``struct drm_i915_private *i915`` i915 device ``u32 size`` object size ``unsigned int tiling`` tiling mode ``unsigned int stride`` tiling stride **Description** Return the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.h](h)}(h**Parameters**h]jb)}(hj+h]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj)ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKYhj%ubjx)}(hhh](j})}(h.``struct drm_i915_private *i915`` i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjJh]hstruct drm_i915_private *i915}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKVhjDubj)}(hhh]h)}(h i915 deviceh]h i915 device}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKVhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j|hj_hKVhjAubj})}(h``u32 size`` object size h](j)}(h ``u32 size``h]j)}(hjh]hu32 size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKWhj}ubj)}(hhh]h)}(h object sizeh]h object size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKWhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j|hjhKWhjAubj})}(h$``unsigned int tiling`` tiling mode h](j)}(h``unsigned int tiling``h]j)}(hjh]hunsigned int tiling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKXhjubj)}(hhh]h)}(h tiling modeh]h tiling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKXhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKXhjAubj})}(h&``unsigned int stride`` tiling stride h](j)}(h``unsigned int stride``h]j)}(hjh]hunsigned int stride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKYhjubj)}(hhh]h)}(h tiling strideh]h tiling stride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKYhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hKYhjAubeh}(h]h ]h"]h$]h&]uh1jwhj%ubh)}(h**Description**h]jb)}(hj0h]h Description}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj.ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK[hj%ubh)}(hReturn the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.h]hReturn the required global GTT alignment for a fence (a view of a tiled object), taking into account potential fence register mapping.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK[hj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&i915_gem_set_tiling_ioctl (C function)c.i915_gem_set_tiling_ioctlhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hYint i915_gem_set_tiling_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j2)}(hXint i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *file)h](j)}(hinth]hint}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMHubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjqhhhjhMHubjz)}(hi915_gem_set_tiling_ioctlh]j;)}(hi915_gem_set_tiling_ioctlh]hi915_gem_set_tiling_ioctl}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjqhhhjhMHubj)}(h;(struct drm_device *dev, void *data, struct drm_file *file)h](j)}(hstruct drm_device *devh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h drm_deviceh]h drm_device}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.i915_gem_set_tiling_ioctlasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdevh]hdev}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h void *datah](j)}(hvoidh]hvoid}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj2hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hdatah]hdata}(hjMhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_file *fileh](j)}(hjh]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubji)}(h h]h }(hjshhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbubh)}(hhh]j;)}(hdrm_fileh]hdrm_file}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.i915_gem_set_tiling_ioctlasbuh1hhjbubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubj;)}(hfileh]hfile}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjbubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjqhhhjhMHubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjmhhhjhMHubah}(h]jhah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMHhjjhhubj1)}(hhh]h)}(h IOCTL handler to set tiling modeh]h IOCTL handler to set tiling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMHhjhhubah}(h]h ]h"]h$]h&]uh1j0hjjhhhjhMHubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXp**Parameters** ``struct drm_device *dev`` DRM device ``void *data`` data pointer for the ioctl ``struct drm_file *file`` DRM file for the ioctl call **Description** Sets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object. 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./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMJhj[ubj)}(hhh]h)}(hdata pointer for the ioctlh]hdata pointer for the ioctl}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMJhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hjvhMJhjubj})}(h6``struct drm_file *file`` DRM file for the ioctl call h](j)}(h``struct drm_file *file``h]j)}(hjh]hstruct drm_file *file}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMKhjubj)}(hhh]h)}(hDRM file for the ioctl callh]hDRM file for the ioctl call}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMKhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMMhjubh)}(hhSets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object.h]hhSets the tiling mode of an object, returning the required swizzling of bit 6 of addresses in the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMMhjubh)}(hCalled by the user via ioctl.h]hCalled by the user via ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMPhjubh)}(h **Return**h]jb)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMRhjubh)}(h+Zero on success, negative errno on failure.h]h+Zero on success, negative errno on failure.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMRhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"&i915_gem_get_tiling_ioctl (C function)c.i915_gem_get_tiling_ioctlhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hYint i915_gem_get_tiling_ioctl (struct drm_device *dev, void *data, struct drm_file *file)h]j2)}(hXint i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *file)h](j)}(hinth]hint}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMubji)}(h h]h }(hj_hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjLhhhj^hMubjz)}(hi915_gem_get_tiling_ioctlh]j;)}(hi915_gem_get_tiling_ioctlh]hi915_gem_get_tiling_ioctl}(hjqhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjmubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjLhhhj^hMubj)}(h;(struct drm_device *dev, void *data, struct drm_file *file)h](j)}(hstruct drm_device *devh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h drm_deviceh]h drm_device}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjssbc.i915_gem_get_tiling_ioctlasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdevh]hdev}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h void *datah](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hdatah]hdata}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct drm_file *fileh](j)}(hjh]hstruct}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubji)}(h h]h }(hjNhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj=ubh)}(hhh]j;)}(hdrm_fileh]hdrm_file}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj\ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjamodnameN classnameNjXj[)}j^]jc.i915_gem_get_tiling_ioctlasbuh1hhj=ubji)}(h h]h }(hj}hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj=ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubj;)}(hfileh]hfile}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj=ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjLhhhj^hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjHhhhj^hMubah}(h]jCah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj^hMhjEhhubj1)}(hhh]h)}(h IOCTL handler to get tiling modeh]h IOCTL handler to get tiling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:477: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjEhhhj^hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hXT**Parameters** ``struct drm_device *dev`` DRM device ``void *data`` data pointer for the ioctl ``struct drm_file *file`` DRM file for the ioctl call **Description** Returns the current tiling mode and required bit 6 swizzling for the object. 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There's two exceptions:h]hIn principle GEM doesn’t care at all about the internal data layout of an object, and hence it also doesn’t care about tiling or swizzling. There’s two exceptions:}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjhhubj:)}(hhh](j:)}(hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there's only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.h]h)}(hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there's only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.h]hXFor X and Y tiling the hardware provides detilers for CPU access, so called fences. Since there’s only a limited amount of them the kernel must manage these, and therefore userspace must tell the kernel the object tiling if it wants to use fences for detiling.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhj3ubah}(h]h ]h"]h$]h&]uh1j:hj0ubj:)}(hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely. h]h)}(hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely.h]hXOn gen3 and gen4 platforms have a swizzling pattern for tiled objects which depends upon the physical page frame number. When swapping such objects the page frame number might change and the kernel must be able to fix this up and hence now the tiling. Note that on a subset of platforms with asymmetric memory channel population the swizzling pattern changes in an unknown way, and for those the kernel simply forbids swapping completely.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chKhjLubah}(h]h ]h"]h$]h&]uh1j:hj0ubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjEhKhjhhubh)}(hSince neither of this applies for new tiling layouts on modern platforms like W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. Anything else can be handled in userspace entirely without the kernel's involvement.h]hSince neither of this applies for new tiling layouts on modern platforms like W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. Anything else can be handled in userspace entirely without the kernel’s involvement.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:480: ./drivers/gpu/drm/i915/gem/i915_gem_tiling.chK$hjhhubeh}(h]object-tiling-ioctlsah ]h"]object tiling ioctlsah$]h&]uh1hhjahhhhhMubh)}(hhh](h)}(hProtected Objectsh]hProtected Objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hPXP (Protected Xe Path) is a feature available in Gen12 and newer platforms. It allows execution and flip to display of protected (i.e. encrypted) objects. The SW support is enabled via the CONFIG_DRM_I915_PXP kconfig.h]hPXP (Protected Xe Path) is a feature available in Gen12 and newer platforms. It allows execution and flip to display of protected (i.e. encrypted) objects. The SW support is enabled via the CONFIG_DRM_I915_PXP kconfig.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:486: ./drivers/gpu/drm/i915/pxp/intel_pxp.chKhjhhubh)}(hXRObjects can opt-in to PXP encryption at creation time via the I915_GEM_CREATE_EXT_PROTECTED_CONTENT create_ext flag. For objects to be correctly protected they must be used in conjunction with a context created with the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. See the documentation of those two uapi flags for details and restrictions.h]hXRObjects can opt-in to PXP encryption at creation time via the I915_GEM_CREATE_EXT_PROTECTED_CONTENT create_ext flag. For objects to be correctly protected they must be used in conjunction with a context created with the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. See the documentation of those two uapi flags for details and restrictions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:486: ./drivers/gpu/drm/i915/pxp/intel_pxp.chKhjhhubh)}(hXHProtected objects are tied to a pxp session; currently we only support one session, which i915 manages and whose index is available in the uapi (I915_PROTECTED_CONTENT_DEFAULT_SESSION) for use in instructions targeting protected objects. The session is invalidated by the HW when certain events occur (e.g. suspend/resume). When this happens, all the objects that were used with the session are marked as invalid and all contexts marked as using protected content are banned. Any further attempt at using them in an execbuf call is rejected, while flips are converted to black frames.h]hXHProtected objects are tied to a pxp session; currently we only support one session, which i915 manages and whose index is available in the uapi (I915_PROTECTED_CONTENT_DEFAULT_SESSION) for use in instructions targeting protected objects. The session is invalidated by the HW when certain events occur (e.g. suspend/resume). When this happens, all the objects that were used with the session are marked as invalid and all contexts marked as using protected content are banned. Any further attempt at using them in an execbuf call is rejected, while flips are converted to black frames.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:486: ./drivers/gpu/drm/i915/pxp/intel_pxp.chK!hjhhubh)}(hSome of the PXP setup operations are performed by the Management Engine, which is handled by the mei driver; communication between i915 and mei is performed via the mei_pxp component module.h]hSome of the PXP setup operations are performed by the Management Engine, which is handled by the mei driver; communication between i915 and mei is performed via the mei_pxp component module.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/i915:486: ./drivers/gpu/drm/i915/pxp/intel_pxp.chK+hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_pxp (C struct) c.intel_pxphNtauh1jhjhhhNhNubj')}(hhh](j,)}(h intel_pxph]j2)}(hstruct intel_pxph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhKubjz)}(h intel_pxph]j;)}(hjh]h intel_pxp}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhKhjhhubj1)}(hhh]h)}(h pxp stateh]h pxp state}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhj'hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjBjSjBjTjUjVuh1j&hhhjhNhNubjX)}(hX **Definition**:: struct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); }; **Members** ``ctrl_gt`` pointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform) ``platform_cfg_is_bad`` used to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called. ``kcr_base`` base mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile. ``gsccs_res`` resources for request submission for platforms that have a GSC engine. ``pxp_component`` i915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`. ``dev_link`` Enforce module relationship for power management ordering. ``pxp_component_added`` track if the pxp component has been added. Set and cleared in tee init and fini functions respectively. ``ce`` kernel-owned context used for PXP operations ``arb_mutex`` protects arb session start ``arb_is_valid`` tracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW. ``key_instance`` tracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one. ``tee_mutex`` protects the tee channel binding and messaging. ``stream_cmd`` LMEM obj used to send stream PXP commands to the GSC ``hw_state_invalidated`` if the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required. ``irq_enabled`` tracks the status of the kcr irqs ``termination`` tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`. ``session_work`` worker that manages session events. ``session_events`` pending session events, protected with gt->irq_lock.h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjJubh:}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjFubj")}(hXstruct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); };h]hXstruct intel_pxp { struct intel_gt *ctrl_gt; bool platform_cfg_is_bad; u32 kcr_base; struct gsccs_session_resources { u64 host_session_handle; struct intel_context *ce; struct i915_vma *pkt_vma; void *pkt_vaddr; struct i915_vma *bb_vma; void *bb_vaddr; } gsccs_res; struct i915_pxp_component *pxp_component; struct device_link *dev_link; bool pxp_component_added; struct intel_context *ce; struct mutex arb_mutex; bool arb_is_valid; u32 key_instance; struct mutex tee_mutex; struct { struct drm_i915_gem_object *obj; void *vaddr; } stream_cmd; bool hw_state_invalidated; bool irq_enabled; struct completion termination; struct work_struct session_work; u32 session_events; #define PXP_TERMINATION_REQUEST BIT(0); #define PXP_TERMINATION_COMPLETE BIT(1); #define PXP_INVAL_REQUIRED BIT(2); #define PXP_EVENT_TYPE_IRQ BIT(3); };}hjgsbah}(h]h ]h"]h$]h&]jjuh1j"hd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjFubh)}(h **Members**h]jb)}(hjxh]hMembers}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjvubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK=hjFubjx)}(hhh](j})}(h``ctrl_gt`` pointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform) h](j)}(h ``ctrl_gt``h]j)}(hjh]hctrl_gt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(hpointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform)h]hpointer to the tile that owns the controls for PXP subsystem assets that the VDBOX, the KCR engine (and GSC CS depending on the platform)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hXf``platform_cfg_is_bad`` used to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called. h](j)}(h``platform_cfg_is_bad``h]j)}(hjh]hplatform_cfg_is_bad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK#hjubj)}(hhh]h)}(hXMused to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called.h]hXMused to track if any prior arb session creation resulted in a failure that was caused by a platform configuration issue, meaning that failure will not get resolved without a change to the platform (not kernel) such as BIOS configuration, firwmware update, etc. This bool gets reflected when GET_PARAM:I915_PARAM_PXP_STATUS is called.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK#hjubj})}(h``kcr_base`` base mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile. h](j)}(h ``kcr_base``h]j)}(hj h]hkcr_base}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK)hjubj)}(hhh]h)}(hbase mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile.h]hbase mmio offset for the KCR engine which is different on legacy platforms vs newer platforms where the KCR is inside the media-tile.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK(hj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hK)hjubj})}(hU``gsccs_res`` resources for request submission for platforms that have a GSC engine. h](j)}(h ``gsccs_res``h]j)}(hjEh]h gsccs_res}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK.hj?ubj)}(hhh]h)}(hFresources for request submission for platforms that have a GSC engine.h]hFresources for request submission for platforms that have a GSC engine.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhK.hj[ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j|hjZhK.hjubj})}(h``pxp_component`` i915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`. h](j)}(h``pxp_component``h]j)}(hj~h]h pxp_component}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK>hjxubj)}(hhh]h)}(hi915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by :c:type:`tee_mutex`.h](hi915_pxp_component struct of the bound mei_pxp module. Only set and cleared inside component bind/unbind functions, which are protected by }(hjhhhNhNubh)}(h:c:type:`tee_mutex`h]j)}(hjh]h tee_mutex}(hjhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjj tee_mutexuh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj})}(hH``dev_link`` Enforce module relationship for power management ordering. h](j)}(h ``dev_link``h]j)}(hjh]hdev_link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKChjubj)}(hhh]h)}(h:Enforce module relationship for power management ordering.h]h:Enforce module relationship for power management ordering.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKChjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKChjubj})}(h``pxp_component_added`` track if the pxp component has been added. Set and cleared in tee init and fini functions respectively. h](j)}(h``pxp_component_added``h]j)}(hjh]hpxp_component_added}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKHhjubj)}(hhh]h)}(hgtrack if the pxp component has been added. Set and cleared in tee init and fini functions respectively.h]hgtrack if the pxp component has been added. Set and cleared in tee init and fini functions respectively.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKGhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj)hKHhjubj})}(h4``ce`` kernel-owned context used for PXP operations h](j)}(h``ce``h]j)}(hjNh]hce}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjHubj)}(hhh]h)}(h,kernel-owned context used for PXP operationsh]h,kernel-owned context used for PXP operations}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchKhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1j|hjchKhjubj})}(h)``arb_mutex`` protects arb session start h](j)}(h ``arb_mutex``h]j)}(hjh]h arb_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(hprotects arb session starth]hprotects arb session start}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``arb_is_valid`` tracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW. h](j)}(h``arb_is_valid``h]j)}(hjh]h arb_is_valid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKUhjubj)}(hhh]h)}(htracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can't rely on the HW state of the session to know if it's valid and need to track the status in SW.h]htracks arb session status. After a teardown, the arb session can still be in play on the HW even if the keys are gone, so we can’t rely on the HW state of the session to know if it’s valid and need to track the status in SW.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKRhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKUhjubj})}(h``key_instance`` tracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one. h](j)}(h``key_instance``h]j)}(hjh]h key_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhK\hjubj)}(hhh]h)}(htracks which key instance we're on, so we can use it to determine if an object was created using the current key or a previous one.h]htracks which key instance we’re on, so we can use it to determine if an object was created using the current key or a previous one.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK\hjubj})}(h>``tee_mutex`` protects the tee channel binding and messaging. h](j)}(h ``tee_mutex``h]j)}(hj4h]h tee_mutex}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhj.ubj)}(hhh]h)}(h/protects the tee channel binding and messaging.h]h/protects the tee channel binding and messaging.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhKhjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j|hjIhKhjubj})}(hD``stream_cmd`` LMEM obj used to send stream PXP commands to the GSC h](j)}(h``stream_cmd``h]j)}(hjmh]h stream_cmd}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjgubj)}(hhh]h)}(h4LMEM obj used to send stream PXP commands to the GSCh]h4LMEM obj used to send stream PXP commands to the GSC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``hw_state_invalidated`` if the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required. h](j)}(h``hw_state_invalidated``h]j)}(hjh]hhw_state_invalidated}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKmhjubj)}(hhh]h)}(hif the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required.h]hif the HW perceives an attack on the integrity of the encryption it will invalidate the keys and expect SW to re-initialize the session. We keep track of this state to make sure we only re-start the arb session when required.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKjhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKmhjubj})}(h2``irq_enabled`` tracks the status of the kcr irqs h](j)}(h``irq_enabled``h]j)}(hjh]h irq_enabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(h!tracks the status of the kcr irqsh]h!tracks the status of the kcr irqs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``termination`` tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`. h](j)}(h``termination``h]j)}(hjh]h termination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKuhjubj)}(hhh]h)}(h{tracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in :c:type:`session_work`.h](hdtracks the status of a pending termination. Only re-initialized under gt->irq_lock and completed in }(hj2hhhNhNubh)}(h:c:type:`session_work`h]j)}(hj<h]h session_work}(hj>hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjj session_workuh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKthj2ubh.}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjYhKthj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj.hKuhjubj})}(h5``session_work`` worker that manages session events. h](j)}(h``session_work``h]j)}(hjvh]h session_work}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjpubj)}(hhh]h)}(h#worker that manages session events.h]h#worker that manages session events.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hG``session_events`` pending session events, protected with gt->irq_lock.h](j)}(h``session_events``h]j)}(hjh]hsession_events}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubj)}(hhh]h)}(h4pending session events, protected with gt->irq_lock.h]h4pending session events, protected with gt->irq_lock.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/gpu/i915:489: ./drivers/gpu/drm/i915/pxp/intel_pxp_types.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubeh}(h]h ]h"]h$]h&]uh1jwhjFubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]protected-objectsah ]h"]protected objectsah$]h&]uh1hhjahhhhhMubeh}(h](memory-management-and-command-submissionah ]h"](memory management and command submissionah$]h&]uh1hhhhhhhhM ubh)}(hhh](h)}(hMicrocontrollersh]hMicrocontrollers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hXyStarting from gen9, three microcontrollers are available on the HW: the graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the display microcontroller (DMC). The driver is responsible for loading the firmwares on the microcontrollers; the GuC and HuC firmwares are transferred to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.h]hXyStarting from gen9, three microcontrollers are available on the HW: the graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the display microcontroller (DMC). The driver is responsible for loading the firmwares on the microcontrollers; the GuC and HuC firmwares are transferred to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hWOPCMh]hWOPCM}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h WOPCM Layouth]h WOPCM Layout}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhhhMubh)}(hThe layout of the WOPCM will be fixed after writing to GuC WOPCM size and offset registers whose values are calculated and determined by HuC/GuC firmware size and set of hardware requirements/restrictions as shown below:h]hThe layout of the WOPCM will be fixed after writing to GuC WOPCM size and offset registers whose values are calculated and determined by HuC/GuC firmware size and set of hardware requirements/restrictions as shown below:}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:506: ./drivers/gpu/drm/i915/gt/intel_wopcm.chK hj0hhubj")}(hX +=========> +====================+ <== WOPCM Top ^ | HW contexts RSVD | | +===> +====================+ <== GuC WOPCM Top | ^ | | | | | | | | | | | GuC | | | WOPCM | | | Size +--------------------+ WOPCM | | GuC FW RSVD | | | +--------------------+ | | | GuC Stack RSVD | | | +------------------- + | v | GuC WOPCM RSVD | | +===> +====================+ <== GuC WOPCM base | | WOPCM RSVD | | +------------------- + <== HuC Firmware Top v | HuC FW | +=========> +====================+ <== WOPCM Baseh]hX +=========> +====================+ <== WOPCM Top ^ | HW contexts RSVD | | +===> +====================+ <== GuC WOPCM Top | ^ | | | | | | | | | | | GuC | | | WOPCM | | | Size +--------------------+ WOPCM | | GuC FW RSVD | | | +--------------------+ | | | GuC Stack RSVD | | | +------------------- + | v | GuC WOPCM RSVD | | +===> +====================+ <== GuC WOPCM base | | WOPCM RSVD | | +------------------- + <== HuC Firmware Top v | HuC FW | +=========> +====================+ <== WOPCM Base}hjPsbah}(h]h ]h"]h$]h&]jjuh1j"h_/var/lib/git/docbuild/linux/Documentation/gpu/i915:506: ./drivers/gpu/drm/i915/gt/intel_wopcm.chKhj0hhubh)}(hGuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 context).h]hGuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 context).}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/gpu/i915:506: ./drivers/gpu/drm/i915/gt/intel_wopcm.chK$hj0hhubeh}(h] wopcm-layoutah ]h"] wopcm layoutah$]h&]uh1hhjhhhhhMubeh}(h]wopcmah ]h"]wopcmah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hGuCh]hGuC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhhhMubh)}(hThe GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is designed to offload some of the functionality usually performed by the host driver; currently the main operations it can take care of are:h]hThe GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is designed to offload some of the functionality usually performed by the host driver; currently the main operations it can take care of are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhj~hhubj:)}(hhh](j:)}(hGAuthentication of the HuC, which is required to fully enable HuC usage.h]h)}(hjh]hGAuthentication of the HuC, which is required to fully enable HuC usage.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h@Low latency graphics context scheduling (a.k.a. GuC submission).h]h)}(hjh]h@Low latency graphics context scheduling (a.k.a. GuC submission).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hGT Power management. h]h)}(hGT Power management.h]hGT Power management.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhj~hhubh)}(hThe enable_guc module parameter can be used to select which of those operations to enable within GuC. Note that not all the operations are supported on all gen9+ platforms.h]hThe enable_guc module parameter can be used to select which of those operations to enable within GuC. Note that not all the operations are supported on all gen9+ platforms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chKhj~hhubh)}(hX Enabling the GuC is not mandatory and therefore the firmware is only loaded if at least one of the operations is selected. However, not loading the GuC might result in the loss of some features that do require the GuC (currently just the HuC, but more are expected to land in the future).h]hX Enabling the GuC is not mandatory and therefore the firmware is only loaded if at least one of the operations is selected. However, not loading the GuC might result in the loss of some features that do require the GuC (currently just the HuC, but more are expected to land in the future).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:512: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chK"hj~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_guc (C struct) c.intel_guchNtauh1jhj~hhhNhNubj')}(hhh](j,)}(h intel_guch]j2)}(hstruct intel_guch](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKubji)}(h h]h }(hj5hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj#hhhj4hKubjz)}(h intel_guch]j;)}(hj!h]h intel_guc}(hjGhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjCubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj#hhhj4hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj4hKubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj4hKhjhhubj1)}(hhh]h)}(hTop level structure of GuC.h]hTop level structure of GuC.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjfhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj4hKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhj~hNhNubjX)}(hX **Definition**:: struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; }; **Members** ``fw`` the GuC firmware ``log`` sub-structure containing GuC log related data and objects ``ct`` the command transport communication channel ``slpc`` sub-structure containing SLPC related data and objects ``capture`` the error-state-capture module's data and objects ``dbgfs_node`` debugfs node ``sched_engine`` Global engine used to submit requests to GuC ``stalled_request`` if GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed. ``submission_stall_reason`` reason why submission is stalled ``irq_lock`` protects GuC irq state ``msg_enabled_mask`` mask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message. ``outstanding_submission_g2h`` number of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle ``tlb_lookup`` xarray to store all pending TLB invalidation requests ``serial_slot`` id to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter. ``next_seqno`` the next id (sequence number) to allocate. ``interrupts`` pointers to GuC interrupt-managing functions. ``submission_state`` sub-structure for submission state protected by single lock ``submission_state.lock`` protects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero ``submission_state.guc_ids`` used to allocate new guc_ids, single-lrc ``submission_state.num_guc_ids`` Number of guc_ids, selftest feature to be able to reduce this number while testing. ``submission_state.guc_ids_bitmap`` used to allocate new guc_ids, multi-lrc ``submission_state.guc_id_list`` list of intel_context with valid guc_ids but no refs ``submission_state.guc_ids_in_use`` Number single-lrc guc_ids in use ``submission_state.destroyed_contexts`` list of contexts waiting to be destroyed (deregistered with the GuC) ``submission_state.destroyed_worker`` worker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping) ``submission_state.reset_fail_worker`` worker to trigger a GT reset after an engine reset fails ``submission_state.reset_fail_mask`` mask of engines that failed to reset ``submission_state.sched_disable_delay_ms`` schedule disable delay, in ms, for contexts ``submission_state.sched_disable_gucid_threshold`` threshold of min remaining available guc_ids before we start bypassing the schedule disable delay ``submission_supported`` tracks whether we support GuC submission on the current platform ``submission_selected`` tracks whether the user enabled GuC submission ``submission_initialized`` tracks whether GuC submission has been initialised ``submission_version`` Submission API version of the currently loaded firmware ``rc_supported`` tracks whether we support GuC rc on the current platform ``rc_selected`` tracks whether the user enabled GuC rc ``ads_vma`` object allocated to hold the GuC ADS ``ads_map`` contents of the GuC ADS ``ads_regset_size`` size of the save/restore regsets in the ADS ``ads_regset_count`` number of save/restore registers in the ADS for each engine ``ads_regset`` save/restore regsets in the ADS ``ads_golden_ctxt_size`` size of the golden contexts in the ADS ``ads_waklv_size`` size of workaround KLVs ``ads_capture_size`` size of register lists in the ADS used for error capture ``lrc_desc_pool_v69`` object allocated to hold the GuC LRC descriptor pool ``lrc_desc_pool_vaddr_v69`` contents of the GuC LRC descriptor pool ``context_lookup`` used to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC ``params`` Control params for fw initialization ``send_regs`` GuC's FW specific registers used for sending MMIO H2G ``notify_reg`` register used to send interrupts to the GuC FW ``mmio_msg`` notification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up. ``send_mutex`` used to serialize the intel_guc_send actions ``timestamp`` GT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker. ``timestamp.lock`` Lock protecting the below fields and the engine stats. ``timestamp.gt_stamp`` 64-bit extended value of the GT timestamp. ``timestamp.ping_delay`` Period for polling the GT timestamp for overflow. ``timestamp.work`` Periodic work to adjust GT timestamp, engine and context usage for overflows. ``timestamp.shift`` Right shift value for the gpm timestamp ``timestamp.last_stat_jiffies`` jiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required. ``dead_guc_worker`` Asynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker. ``last_dead_guc_jiffies`` timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC. ``number_guc_id_stolen`` The number of guc_ids that have been stolen ``fast_response_selftest`` Backdoor to CT handler for fast response selftesth](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK hjubj")}(hX struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; };h]hX struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; struct intel_guc_slpc slpc; struct intel_guc_state_capture *capture; struct dentry *dbgfs_node; struct i915_sched_engine *sched_engine; struct i915_request *stalled_request; enum { STALL_NONE, STALL_REGISTER_CONTEXT, STALL_MOVE_LRC_TAIL, STALL_ADD_REQUEST, } submission_stall_reason; spinlock_t irq_lock; unsigned int msg_enabled_mask; atomic_t outstanding_submission_g2h; struct xarray tlb_lookup; u32 serial_slot; u32 next_seqno; struct { bool enabled; void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); void (*disable)(struct intel_guc *guc); } interrupts; struct { spinlock_t lock; struct ida guc_ids; int num_guc_ids; unsigned long *guc_ids_bitmap; struct list_head guc_id_list; unsigned int guc_ids_in_use; struct list_head destroyed_contexts; struct work_struct destroyed_worker; struct work_struct reset_fail_worker; intel_engine_mask_t reset_fail_mask; unsigned int sched_disable_delay_ms; unsigned int sched_disable_gucid_threshold; } submission_state; bool submission_supported; bool submission_selected; bool submission_initialized; struct intel_uc_fw_ver submission_version; bool rc_supported; bool rc_selected; struct i915_vma *ads_vma; struct iosys_map ads_map; u32 ads_regset_size; u32 ads_regset_count[I915_NUM_ENGINES]; struct guc_mmio_reg *ads_regset; u32 ads_golden_ctxt_size; u32 ads_waklv_size; u32 ads_capture_size; struct i915_vma *lrc_desc_pool_v69; void *lrc_desc_pool_vaddr_v69; struct xarray context_lookup; u32 params[GUC_CTL_MAX_DWORDS]; struct { u32 base; unsigned int count; enum forcewake_domains fw_domains; } send_regs; i915_reg_t notify_reg; u32 mmio_msg; struct mutex send_mutex; struct { spinlock_t lock; u64 gt_stamp; unsigned long ping_delay; struct delayed_work work; u32 shift; unsigned long last_stat_jiffies; } timestamp; struct work_struct dead_guc_worker; unsigned long last_dead_guc_jiffies; #ifdef CONFIG_DRM_I915_SELFTEST; int number_guc_id_stolen; u32 fast_response_selftest; #endif; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j"h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK"hjubh)}(h **Members**h]jb)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKuhjubjx)}(hhh](j})}(h``fw`` the GuC firmware h](j)}(h``fw``h]j)}(hjh]hfw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK"hjubj)}(hhh]h)}(hthe GuC firmwareh]hthe GuC firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK"hjubj})}(hB``log`` sub-structure containing GuC log related data and objects h](j)}(h``log``h]j)}(hjh]hlog}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj ubj)}(hhh]h)}(h9sub-structure containing GuC log related data and objectsh]h9sub-structure containing GuC log related data and objects}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hKhj%ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj$hKhjubj})}(h3``ct`` the command transport communication channel h](j)}(h``ct``h]j)}(hjHh]hct}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjBubj)}(hhh]h)}(h+the command transport communication channelh]h+the command transport communication channel}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hKhj^ubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1j|hj]hKhjubj})}(h@``slpc`` sub-structure containing SLPC related data and objects h](j)}(h``slpc``h]j)}(hjh]hslpc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj{ubj)}(hhh]h)}(h6sub-structure containing SLPC related data and objectsh]h6sub-structure containing SLPC related data and objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h>``capture`` the error-state-capture module's data and objects h](j)}(h ``capture``h]j)}(hjh]hcapture}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h1the error-state-capture module's data and objectsh]h3the error-state-capture module’s data and objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``dbgfs_node`` debugfs node h](j)}(h``dbgfs_node``h]j)}(hjh]h dbgfs_node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h debugfs nodeh]h debugfs node}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h>``sched_engine`` Global engine used to submit requests to GuC h](j)}(h``sched_engine``h]j)}(hj,h]h sched_engine}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj&ubj)}(hhh]h)}(h,Global engine used to submit requests to GuCh]h,Global engine used to submit requests to GuC}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhKhjBubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j|hjAhKhjubj})}(h``stalled_request`` if GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed. h](j)}(h``stalled_request``h]j)}(hjeh]hstalled_request}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK6hj_ubj)}(hhh]h)}(hif GuC can't process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed.h]hif GuC can’t process a request for any reason, we save it until GuC restarts processing. No other request can be submitted until the stalled request is processed.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK4hj{ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j|hjzhK6hjubj})}(h=``submission_stall_reason`` reason why submission is stalled h](j)}(h``submission_stall_reason``h]j)}(hjh]hsubmission_stall_reason}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK:hjubj)}(hhh]h)}(h reason why submission is stalledh]h reason why submission is stalled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK:hjubj})}(h$``irq_lock`` protects GuC irq state h](j)}(h ``irq_lock``h]j)}(hjh]hirq_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hprotects GuC irq stateh]hprotects GuC irq state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(ho``msg_enabled_mask`` mask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message. h](j)}(h``msg_enabled_mask``h]j)}(hjh]hmsg_enabled_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKHhj ubj)}(hhh]h)}(hYmask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message.h]hYmask of events that are processed when receiving an INTEL_GUC_ACTION_DEFAULT G2H message.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKGhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj&hKHhjubj})}(h``outstanding_submission_g2h`` number of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle h](j)}(h``outstanding_submission_g2h``h]j)}(hjKh]houtstanding_submission_g2h}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKOhjEubj)}(hhh]h)}(hjnumber of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idleh]hjnumber of outstanding GuC to Host responses related to GuC submission, used to determine if the GT is idle}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKMhjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1j|hj`hKOhjubj})}(hE``tlb_lookup`` xarray to store all pending TLB invalidation requests h](j)}(h``tlb_lookup``h]j)}(hjh]h tlb_lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h5xarray to store all pending TLB invalidation requestsh]h5xarray to store all pending TLB invalidation requests}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hw``serial_slot`` id to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter. h](j)}(h``serial_slot``h]j)}(hjh]h serial_slot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKXhjubj)}(hhh]h)}(hfid to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter.h]hfid to the initial waiter created in tlb_lookup, which is used only when failed to allocate new waiter.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKXhjubj})}(h:``next_seqno`` the next id (sequence number) to allocate. h](j)}(h``next_seqno``h]j)}(hjh]h next_seqno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h*the next id (sequence number) to allocate.h]h*the next id (sequence number) to allocate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hKhjubj})}(h=``interrupts`` pointers to GuC interrupt-managing functions. h](j)}(h``interrupts``h]j)}(hj1h]h interrupts}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj+ubj)}(hhh]h)}(h-pointers to GuC interrupt-managing functions.h]h-pointers to GuC interrupt-managing functions.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhKhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1j|hjFhKhjubj})}(hQ``submission_state`` sub-structure for submission state protected by single lock h](j)}(h``submission_state``h]j)}(hjjh]hsubmission_state}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKihjdubj)}(hhh]h)}(h;sub-structure for submission state protected by single lockh]h;sub-structure for submission state protected by single lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1j|hjhKihjubj})}(h``submission_state.lock`` protects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero h](j)}(h``submission_state.lock``h]j)}(hjh]hsubmission_state.lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKohjubj)}(hhh]h)}(hpprotects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zeroh]hpprotects everything in submission_state, ce->guc_id.id, and ce->guc_id.ref when transitioning in and out of zero}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKmhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKohjubj})}(hF``submission_state.guc_ids`` used to allocate new guc_ids, single-lrc h](j)}(h``submission_state.guc_ids``h]j)}(hjh]hsubmission_state.guc_ids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKthjubj)}(hhh]h)}(h(used to allocate new guc_ids, single-lrch]h(used to allocate new guc_ids, single-lrc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKshjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKthjubj})}(hu``submission_state.num_guc_ids`` Number of guc_ids, selftest feature to be able to reduce this number while testing. h](j)}(h ``submission_state.num_guc_ids``h]j)}(hjh]hsubmission_state.num_guc_ids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKyhjubj)}(hhh]h)}(hSNumber of guc_ids, selftest feature to be able to reduce this number while testing.h]hSNumber of guc_ids, selftest feature to be able to reduce this number while testing.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKxhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj-hKyhjubj})}(hL``submission_state.guc_ids_bitmap`` used to allocate new guc_ids, multi-lrc h](j)}(h#``submission_state.guc_ids_bitmap``h]j)}(hjRh]hsubmission_state.guc_ids_bitmap}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK~hjLubj)}(hhh]h)}(h'used to allocate new guc_ids, multi-lrch]h'used to allocate new guc_ids, multi-lrc}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhK}hjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j|hjghK~hjubj})}(hV``submission_state.guc_id_list`` list of intel_context with valid guc_ids but no refs h](j)}(h ``submission_state.guc_id_list``h]j)}(hjh]hsubmission_state.guc_id_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h4list of intel_context with valid guc_ids but no refsh]h4list of intel_context with valid guc_ids but no refs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hE``submission_state.guc_ids_in_use`` Number single-lrc guc_ids in use h](j)}(h#``submission_state.guc_ids_in_use``h]j)}(hjh]hsubmission_state.guc_ids_in_use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h Number single-lrc guc_ids in useh]h Number single-lrc guc_ids in use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hm``submission_state.destroyed_contexts`` list of contexts waiting to be destroyed (deregistered with the GuC) h](j)}(h'``submission_state.destroyed_contexts``h]j)}(hjh]h#submission_state.destroyed_contexts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hDlist of contexts waiting to be destroyed (deregistered with the GuC)h]hDlist of contexts waiting to be destroyed (deregistered with the GuC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``submission_state.destroyed_worker`` worker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping) h](j)}(h%``submission_state.destroyed_worker``h]j)}(hj:h]h!submission_state.destroyed_worker}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj4ubj)}(hhh]h)}(hworker to deregister contexts, need as we need to take a GT PM reference and can't from destroy function as it might be in an atomic context (no sleeping)h]hworker to deregister contexts, need as we need to take a GT PM reference and can’t from destroy function as it might be in an atomic context (no sleeping)}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1j|hjOhKhjubj})}(h```submission_state.reset_fail_worker`` worker to trigger a GT reset after an engine reset fails h](j)}(h&``submission_state.reset_fail_worker``h]j)}(hjth]h"submission_state.reset_fail_worker}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjnubj)}(hhh]h)}(h8worker to trigger a GT reset after an engine reset failsh]h8worker to trigger a GT reset after an engine reset fails}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hJ``submission_state.reset_fail_mask`` mask of engines that failed to reset h](j)}(h$``submission_state.reset_fail_mask``h]j)}(hjh]h submission_state.reset_fail_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h$mask of engines that failed to reseth]h$mask of engines that failed to reset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hX``submission_state.sched_disable_delay_ms`` schedule disable delay, in ms, for contexts h](j)}(h+``submission_state.sched_disable_delay_ms``h]j)}(hjh]h'submission_state.sched_disable_delay_ms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h+schedule disable delay, in ms, for contextsh]h+schedule disable delay, in ms, for contexts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``submission_state.sched_disable_gucid_threshold`` threshold of min remaining available guc_ids before we start bypassing the schedule disable delay h](j)}(h2``submission_state.sched_disable_gucid_threshold``h]j)}(hj"h]h.submission_state.sched_disable_gucid_threshold}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 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current platform}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j|hjqhKhjubj})}(hG``submission_selected`` tracks whether the user enabled GuC submission h](j)}(h``submission_selected``h]j)}(hjh]hsubmission_selected}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h.tracks whether the user enabled GuC submissionh]h.tracks whether the user enabled GuC submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hN``submission_initialized`` tracks whether GuC submission has been initialised h](j)}(h``submission_initialized``h]j)}(hjh]hsubmission_initialized}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h2tracks whether GuC submission has been initialisedh]h2tracks whether GuC submission has been initialised}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hO``submission_version`` Submission API version of the currently loaded firmware h](j)}(h``submission_version``h]j)}(hjh]hsubmission_version}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h7Submission API version of the currently loaded firmwareh]h7Submission API version of the currently loaded firmware}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hJ``rc_supported`` tracks whether we support GuC rc on the current platform h](j)}(h``rc_supported``h]j)}(hjAh]h rc_supported}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj;ubj)}(hhh]h)}(h8tracks whether we support GuC rc on the current platformh]h8tracks whether we support GuC rc on the current platform}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhKhjWubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j|hjVhKhjubj})}(h7``rc_selected`` tracks whether the user enabled GuC rc h](j)}(h``rc_selected``h]j)}(hjzh]h rc_selected}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjtubj)}(hhh]h)}(h&tracks whether the user enabled GuC rch]h&tracks whether the user enabled GuC rc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h1``ads_vma`` object allocated to hold the GuC ADS h](j)}(h ``ads_vma``h]j)}(hjh]hads_vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h$object allocated to hold the GuC ADSh]h$object allocated to hold the GuC ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h$``ads_map`` contents of the GuC ADS h](j)}(h ``ads_map``h]j)}(hjh]hads_map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hcontents of the GuC ADSh]hcontents of the GuC ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h@``ads_regset_size`` size of the save/restore regsets in the ADS h](j)}(h``ads_regset_size``h]j)}(hj%h]hads_regset_size}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h+size of the save/restore regsets in the ADSh]h+size of the save/restore regsets in the ADS}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj;ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj:hKhjubj})}(hQ``ads_regset_count`` number of save/restore registers in the ADS for each engine h](j)}(h``ads_regset_count``h]j)}(hj^h]hads_regset_count}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjXubj)}(hhh]h)}(h;number of save/restore registers in the ADS for each engineh]h;number of save/restore registers in the ADS for each engine}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1j|hjshKhjubj})}(h/``ads_regset`` save/restore regsets in the ADS h](j)}(h``ads_regset``h]j)}(hjh]h ads_regset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hsave/restore regsets in the ADSh]hsave/restore regsets in the ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h@``ads_golden_ctxt_size`` size of the golden contexts in the ADS h](j)}(h``ads_golden_ctxt_size``h]j)}(hjh]hads_golden_ctxt_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h&size of the golden contexts in the ADSh]h&size of the golden contexts in the ADS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h+``ads_waklv_size`` size of workaround KLVs h](j)}(h``ads_waklv_size``h]j)}(hj h]hads_waklv_size}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hsize of workaround KLVsh]hsize of workaround KLVs}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hN``ads_capture_size`` size of register lists in the ADS used for error capture h](j)}(h``ads_capture_size``h]j)}(hjCh]hads_capture_size}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj=ubj)}(hhh]h)}(h8size of register lists in the ADS used for error captureh]h8size of register lists in the ADS used for error capture}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhKhjYubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1j|hjXhKhjubj})}(hK``lrc_desc_pool_v69`` object allocated to hold the GuC LRC descriptor pool h](j)}(h``lrc_desc_pool_v69``h]j)}(hj|h]hlrc_desc_pool_v69}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjvubj)}(hhh]h)}(h4object allocated to hold the GuC LRC descriptor poolh]h4object allocated to hold the GuC LRC descriptor pool}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hD``lrc_desc_pool_vaddr_v69`` contents of the GuC LRC descriptor pool h](j)}(h``lrc_desc_pool_vaddr_v69``h]j)}(hjh]hlrc_desc_pool_vaddr_v69}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h'contents of the GuC LRC descriptor poolh]h'contents of the GuC LRC descriptor pool}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``context_lookup`` used to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC h](j)}(h``context_lookup``h]j)}(hjh]hcontext_lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hrused to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuCh]hrused to resolve intel_context from guc_id, if a context is present in this structure it is registered with the GuC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h0``params`` Control params for fw initialization h](j)}(h ``params``h]j)}(hj(h]hparams}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj"ubj)}(hhh]h)}(h$Control params for fw initializationh]h$Control params for fw initialization}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKhj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1j|hj=hKhjubj})}(hD``send_regs`` GuC's FW specific registers used for sending MMIO H2G h](j)}(h ``send_regs``h]j)}(hjah]h send_regs}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj[ubj)}(hhh]h)}(h5GuC's FW specific registers used for sending MMIO H2Gh]h7GuC’s FW specific registers used for sending MMIO H2G}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhKhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hjvhKhjubj})}(h>``notify_reg`` register used to send interrupts to the GuC FW h](j)}(h``notify_reg``h]j)}(hjh]h notify_reg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h.register used to send interrupts to the GuC FWh]h.register used to send interrupts to the GuC FW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h``mmio_msg`` notification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up. h](j)}(h ``mmio_msg``h]j)}(hjh]hmmio_msg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(hnotification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up.h]hnotification bitmask that the GuC writes in one of its registers when the CT channel is disabled, to be processed when the channel is back up.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(h<``send_mutex`` used to serialize the intel_guc_send actions h](j)}(h``send_mutex``h]j)}(hj h]h send_mutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubj)}(hhh]h)}(h,used to serialize the intel_guc_send actionsh]h,used to serialize the intel_guc_send actions}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hKhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj"hKhjubj})}(hr``timestamp`` GT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker. h](j)}(h ``timestamp``h]j)}(hjFh]h timestamp}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj@ubj)}(hhh]h)}(hcGT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker.h]hcGT timestamp object that stores a copy of the timestamp and adjusts it for overflow using a worker.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1j|hj[hKhjubj})}(hJ``timestamp.lock`` Lock protecting the below fields and the engine stats. h](j)}(h``timestamp.lock``h]j)}(hjh]htimestamp.lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjzubj)}(hhh]h)}(h6Lock protecting the below fields and the engine stats.h]h6Lock protecting the below fields and the engine stats.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubj})}(hB``timestamp.gt_stamp`` 64-bit extended value of the GT timestamp. h](j)}(h``timestamp.gt_stamp``h]j)}(hjh]htimestamp.gt_stamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(h*64-bit extended value of the GT timestamp.h]h*64-bit extended value of the GT timestamp.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hK``timestamp.ping_delay`` Period for polling the GT timestamp for overflow. h](j)}(h``timestamp.ping_delay``h]j)}(hjh]htimestamp.ping_delay}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM hjubj)}(hhh]h)}(h1Period for polling the GT timestamp for overflow.h]h1Period for polling the GT timestamp for overflow.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj hM hjubj})}(ha``timestamp.work`` Periodic work to adjust GT timestamp, engine and context usage for overflows. h](j)}(h``timestamp.work``h]j)}(hj.h]htimestamp.work}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhj(ubj)}(hhh]h)}(hMPeriodic work to adjust GT timestamp, engine and context usage for overflows.h]hMPeriodic work to adjust GT timestamp, engine and context usage for overflows.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1j|hjChMhjubj})}(h<``timestamp.shift`` Right shift value for the gpm timestamp h](j)}(h``timestamp.shift``h]j)}(hjhh]htimestamp.shift}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjbubj)}(hhh]h)}(h'Right shift value for the gpm timestamph]h'Right shift value for the gpm timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj~ubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1j|hj}hMhjubj})}(h``timestamp.last_stat_jiffies`` jiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required. h](j)}(h``timestamp.last_stat_jiffies``h]j)}(hjh]htimestamp.last_stat_jiffies}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(hjiffies at last actual stats collection time. We use this timestamp to ensure we don't oversample the stats because runtime power management events can trigger stats collection at much higher rates than required.h]hjiffies at last actual stats collection time. We use this timestamp to ensure we don’t oversample the stats because runtime power management events can trigger stats collection at much higher rates than required.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(hX ``dead_guc_worker`` Asynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker. h](j)}(h``dead_guc_worker``h]j)}(hjh]hdead_guc_worker}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM'hjubj)}(hhh]h)}(hAsynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker.h]hAsynchronous worker thread for forcing a GuC reset. Specifically used when the G2H handler wants to issue a reset. Resets require flushing the G2H queue. So, the G2H processing itself must not trigger a reset directly. Instead, go via this worker.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM'hjubj})}(h``last_dead_guc_jiffies`` timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC. h](j)}(h``last_dead_guc_jiffies``h]j)}(hjh]hlast_dead_guc_jiffies}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM-hjubj)}(hhh]h)}(h~timestamp of previous 'dead guc' occurrence used to prevent a fundamentally broken system from continuously reloading the GuC.h]htimestamp of previous ‘dead guc’ occurrence used to prevent a fundamentally broken system from continuously reloading the GuC.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM+hj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj*hM-hjubj})}(hE``number_guc_id_stolen`` The number of guc_ids that have been stolen h](j)}(h``number_guc_id_stolen``h]j)}(hjOh]hnumber_guc_id_stolen}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM3hjIubj)}(hhh]h)}(h+The number of guc_ids that have been stolenh]h+The number of guc_ids that have been stolen}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhM3hjeubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1j|hjdhM3hjubj})}(hL``fast_response_selftest`` Backdoor to CT handler for fast response selftesth](j)}(h``fast_response_selftest``h]j)}(hjh]hfast_response_selftest}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM6hjubj)}(hhh]h)}(h1Backdoor to CT handler for fast response selftesth]h1Backdoor to CT handler for fast response selftest}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM6hjubeh}(h]h ]h"]h$]h&]uh1jwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj~hhhNhNubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhM:hj~hhubh)}(hhIt handles firmware loading and manages client pool. intel_guc owns an i915_sched_engine for submission.h]hhIt handles firmware loading and manages client pool. intel_guc owns an i915_sched_engine for submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhKhj~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j""intel_guc_ggtt_offset (C function)c.intel_guc_ggtt_offsethNtauh1jhj~hhhNhNubj')}(hhh](j,)}(hGu32 intel_guc_ggtt_offset (struct intel_guc *guc, struct i915_vma *vma)h]j2)}(hFu32 intel_guc_ggtt_offset(struct intel_guc *guc, struct i915_vma *vma)h](h)}(hhh]j;)}(hu32h]hu32}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTintel_guc_ggtt_offsetsbc.intel_guc_ggtt_offsetasbuh1hhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj-hMubjz)}(hintel_guc_ggtt_offseth]j;)}(hj*h]hintel_guc_ggtt_offset}(hj@hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj<ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj-hMubj)}(h-(struct intel_guc *guc, struct i915_vma *vma)h](j)}(hstruct intel_guc *guch](j)}(hjh]hstruct}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubji)}(h h]h }(hjhhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjWubh)}(hhh]j;)}(h intel_guch]h intel_guc}(hjyhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjvubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj{modnameN classnameNjXj[)}j^]j(c.intel_guc_ggtt_offsetasbuh1hhjWubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjWubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj;)}(hguch]hguc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjWubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjSubj)}(hstruct i915_vma *vmah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]j(c.intel_guc_ggtt_offsetasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hvmah]hvma}(hj"hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjSubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhj-hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj-hMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj-hMhjhhubj1)}(hhh]h)}(h+Get and validate the GGTT offset of **vma**h](h$Get and validate the GGTT offset of }(hjLhhhNhNubjb)}(h**vma**h]hvma}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jahjLubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjIhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhj-hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjrjSjrjTjUjVuh1j&hhhj~hNhNubjX)}(hX**Parameters** ``struct intel_guc *guc`` intel_guc structure. ``struct i915_vma *vma`` i915 graphics virtual memory area. **Description** GuC does not allow any gfx GGTT address that falls into range [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. **Return** GGTT offset of the **vma**.h](h)}(h**Parameters**h]jb)}(hj|h]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjzubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjvubjx)}(hhh](j})}(h/``struct intel_guc *guc`` intel_guc structure. h](j)}(h``struct intel_guc *guc``h]j)}(hjh]hstruct intel_guc *guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(hintel_guc structure.h]hintel_guc structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubj})}(h<``struct i915_vma *vma`` i915 graphics virtual memory area. h](j)}(h``struct i915_vma *vma``h]j)}(hjh]hstruct i915_vma *vma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjubj)}(hhh]h)}(h"i915 graphics virtual memory area.h]h"i915 graphics virtual memory area.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjvubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjvubh)}(hX[GuC does not allow any gfx GGTT address that falls into range [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.h]hX[GuC does not allow any gfx GGTT address that falls into range [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. Currently, in order to exclude [0, ggtt.pin_bias) address space from GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjvubh)}(h **Return**h]jb)}(hj6h]hReturn}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj4ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjvubh)}(hGGTT offset of the **vma**.h](hGGTT offset of the }(hjLhhhNhNubjb)}(h**vma**h]hvma}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jahjLubh.}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:515: ./drivers/gpu/drm/i915/gt/uc/intel_guc.hhMhjvubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj~hhhNhNubh)}(hhh](h)}(hGuC Firmware Layouth]hGuC Firmware Layout}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthhhhhMubh)}(h-The GuC/HuC firmware layout looks like this::h]h,The GuC/HuC firmware layout looks like this:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK hjthhubj")}(hX+======================================================================+ | Firmware blob | +===============+===============+============+============+============+ | CSS header | uCode | RSA key | modulus | exponent | +===============+===============+============+============+============+ <-header size-> <---header size continued -----------> <--- size -----------------------------------------------------------> <-key size-> <-mod size-> <-exp size->h]hX+======================================================================+ | Firmware blob | +===============+===============+============+============+============+ | CSS header | uCode | RSA key | modulus | exponent | +===============+===============+============+============+============+ <-header size-> <---header size continued -----------> <--- size -----------------------------------------------------------> <-key size-> <-mod size-> <-exp size->}hjsbah}(h]h ]h"]h$]h&]jjuh1j"hf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhKhjthhubh)}(hXbThe firmware may or may not have modulus key and exponent data. The header, uCode and RSA signature are must-have components that will be used by driver. Length of each components, which is all in dwords, can be found in header. In the case that modulus and exponent are not present in fw, a.k.a truncated image, the length value still appears in header.h]hXbThe firmware may or may not have modulus key and exponent data. The header, uCode and RSA signature are must-have components that will be used by driver. Length of each components, which is all in dwords, can be found in header. In the case that modulus and exponent are not present in fw, a.k.a truncated image, the length value still appears in header.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhKhjthhubh)}(hJDriver will do some basic fw size validation based on the following rules:h]hJDriver will do some basic fw size validation based on the following rules:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK hjthhubj:)}(hhh](j:)}(h/Header, uCode and RSA are must-have components.h]h)}(hjh]h/Header, uCode and RSA are must-have components.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK"hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.h]h)}(hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.h]hdAll firmware components, if they present, are in the sequence illustrated in the layout table above.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK#hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h@Length info of each component can be found in header, in dwords.h]h)}(hjh]h@Length info of each component can be found in header, in dwords.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK%hjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case. h]h)}(hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case.h]hModulus and exponent key are not required by driver. They may not appear in fw. So driver will load a truncated firmware in this case.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK&hj ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j1;j2;j3;hj4;j5;uh1j:hjthhhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhNubh)}(hXStarting from DG2, the HuC is loaded by the GSC instead of i915. The GSC firmware performs all the required integrity checks, we just need to check the version. Note that the header for GSC-managed blobs is different from the CSS used for dma-loaded firmwares.h]hXStarting from DG2, the HuC is loaded by the GSC instead of i915. The GSC firmware performs all the required integrity checks, we just need to check the version. Note that the header for GSC-managed blobs is different from the CSS used for dma-loaded firmwares.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/i915:520: ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.hhK)hjthhubeh}(h]guc-firmware-layoutah ]h"]guc firmware layoutah$]h&]uh1hhj~hhhhhMjKubh)}(hhh](h)}(hGuC Memory Managementh]hGuC Memory Management}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhM ubh)}(hXGuC can't allocate any memory for its own usage, so all the allocations must be handled by the host driver. GuC accesses the memory via the GGTT, with the exception of the top and bottom parts of the 4GB address space, which are instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM) or other parts of the HW. The driver must take care not to place objects that the GuC is going to access in these reserved ranges. The layout of the GuC address space is shown below:h]hXGuC can’t allocate any memory for its own usage, so all the allocations must be handled by the host driver. GuC accesses the memory via the GGTT, with the exception of the top and bottom parts of the 4GB address space, which are instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM) or other parts of the HW. The driver must take care not to place objects that the GuC is going to access in these reserved ranges. The layout of the GuC address space is shown below:}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:526: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjDhhubj")}(hX +===========> +====================+ <== FFFF_FFFF ^ | Reserved | | +====================+ <== GUC_GGTT_TOP | | | | | DRAM | GuC | | Address +===> +====================+ <== GuC ggtt_pin_bias Space ^ | | | | | | | GuC | GuC | | WOPCM | WOPCM | | Size | | | | | | v v | | +=======+===> +====================+ <== 0000_0000h]hX +===========> +====================+ <== FFFF_FFFF ^ | Reserved | | +====================+ <== GUC_GGTT_TOP | | | | | DRAM | GuC | | Address +===> +====================+ <== GuC ggtt_pin_bias Space ^ | | | | | | | GuC | GuC | | WOPCM | WOPCM | | Size | | | | | | v v | | +=======+===> +====================+ <== 0000_0000}hjdsbah}(h]h ]h"]h$]h&]jjuh1j"h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:526: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjDhhubh)}(hThe lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.h]hThe lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:526: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjDhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"#intel_guc_allocate_vma (C function)c.intel_guc_allocate_vmahNtauh1jhjDhhhNhNubj')}(hhh](j,)}(hJstruct i915_vma * intel_guc_allocate_vma (struct intel_guc *guc, u32 size)h]j2)}(hHstruct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubh)}(hhh]j;)}(hi915_vmah]hi915_vma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTintel_guc_allocate_vmasbc.intel_guc_allocate_vmaasbuh1hhjhhhjhMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubjz)}(hintel_guc_allocate_vmah]j;)}(hjh]hintel_guc_allocate_vma}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h!(struct intel_guc *guc, u32 size)h](j)}(hstruct intel_guc *guch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubji)}(h h]h }(hj"hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubh)}(hhh]j;)}(h intel_guch]h intel_guc}(hj3hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj0ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj5modnameN classnameNjXj[)}j^]jc.intel_guc_allocate_vmaasbuh1hhjubji)}(h h]h }(hjQhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj)}(hjh]h*}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj;)}(hguch]hguc}(hjlhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(hu32 sizeh](h)}(hhh]j;)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]jc.intel_guc_allocate_vmaasbuh1hhjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjubj;)}(hsizeh]hsize}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(h!Allocate a GGTT VMA for GuC usageh]h!Allocate a GGTT VMA for GuC usage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjDhNhNubjX)}(hX**Parameters** ``struct intel_guc *guc`` the guc ``u32 size`` size of area to allocate (both virtual space and memory) **Description** This is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC. **Return** A i915_vma if successful, otherwise an ERR_PTR.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubjx)}(hhh](j})}(h"``struct intel_guc *guc`` the guc h](j)}(h``struct intel_guc *guc``h]j)}(hjh]hstruct intel_guc *guc}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubj)}(hhh]h)}(hthe guch]hthe guc}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMhj5ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj4hMhjubj})}(hF``u32 size`` size of area to allocate (both virtual space and memory) h](j)}(h ``u32 size``h]j)}(hjXh]hu32 size}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjRubj)}(hhh]h)}(h8size of area to allocate (both virtual space and memory)h]h8size of area to allocate (both virtual space and memory)}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhMhjnubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j|hjmhMhjubeh}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubh)}(hXHThis is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC.h]hXHThis is a wrapper to create an object for use with the GuC. In order to use it inside the GuC, an object needs to be pinned lifetime, so we allocate both some backing storage and a range inside the Global GTT. We must pin it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that range is reserved inside GuC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubh)}(h/A i915_vma if successful, otherwise an ERR_PTR.h]h/A i915_vma if successful, otherwise an ERR_PTR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:528: ./drivers/gpu/drm/i915/gt/uc/intel_guc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjDhhhNhNubeh}(h]guc-memory-managementah ]h"]guc memory managementah$]h&]uh1hhj~hhhhhM ubh)}(hhh](h)}(hGuC-specific firmware loaderh]hGuC-specific firmware loader}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j" intel_guc_fw_upload (C function)c.intel_guc_fw_uploadhNtauh1jhjhhhNhNubj')}(hhh](j,)}(h/int intel_guc_fw_upload (struct intel_guc *guc)h]j2)}(h.int intel_guc_fw_upload(struct intel_guc *guc)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMubji)}(h h]h }(hj'hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhj&hMubjz)}(hintel_guc_fw_uploadh]j;)}(hintel_guc_fw_uploadh]hintel_guc_fw_upload}(hj9hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj5ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhj&hMubj)}(h(struct intel_guc *guc)h]j)}(hstruct intel_guc *guch](j)}(hjh]hstruct}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubji)}(h h]h }(hjbhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubh)}(hhh]j;)}(h intel_guch]h intel_guc}(hjshhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjpubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjumodnameN classnameNjXj[)}j^]ja)}jTj;sbc.intel_guc_fw_uploadasbuh1hhjQubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjQubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj;)}(hguch]hguc}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjQubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjMubah}(h]h ]h"]h$]h&]jjuh1jhjhhhj&hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhj&hMubah}(h]j ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj&hMhj hhubj1)}(hhh]h)}(hload GuC uCode to deviceh]hload GuC uCode to device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjhhubah}(h]h ]h"]h$]h&]uh1j0hj hhhj&hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjjSjjTjUjVuh1j&hhhjhNhNubjX)}(hX_**Parameters** ``struct intel_guc *guc`` intel_guc structure **Description** Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset. The firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w. **Return** non-zero code on errorh](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjubjx)}(hhh]j})}(h.``struct intel_guc *guc`` intel_guc structure h](j)}(h``struct intel_guc *guc``h]j)}(hjh]hstruct intel_guc *guc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjubj)}(hhh]h)}(hintel_guc structureh]hintel_guc structure}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj.hMhjubah}(h]h ]h"]h$]h&]uh1jwhjubh)}(h**Description**h]jb)}(hjTh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjRubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjubh)}(h[Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset.h]h[Called from intel_uc_init_hw() during driver load, resume from sleep and after a GPU reset.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjubh)}(hThe firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w.h]hThe firmware image should have already been fetched into memory, so only check that fetch succeeded, and then transfer the image to the h/w.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjubh)}(h **Return**h]jb)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjubh)}(hnon-zero code on errorh]hnon-zero code on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/gpu/i915:535: ./drivers/gpu/drm/i915/gt/uc/intel_guc_fw.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubeh}(h]guc-specific-firmware-loaderah ]h"]guc-specific firmware loaderah$]h&]uh1hhj~hhhhhMubh)}(hhh](h)}(hGuC-based command submissionh]hGuC-based command submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hXThe Scratch registers: There are 16 MMIO-based registers start from 0xC180. The kernel driver writes a value to the action register (SOFT_SCRATCH_0) along with any data. It then triggers an interrupt on the GuC via another register write (0xC4C8). Firmware writes a success/fail code back to the action register after processes the request. The kernel driver polls waiting for this update and then proceeds.h]hXThe Scratch registers: There are 16 MMIO-based registers start from 0xC180. The kernel driver writes a value to the action register (SOFT_SCRATCH_0) along with any data. It then triggers an interrupt on the GuC via another register write (0xC4C8). Firmware writes a success/fail code back to the action register after processes the request. The kernel driver polls waiting for this update and then proceeds.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK'hjhhubh)}(hCommand Transport buffers (CTBs): Covered in detail in other sections but CTBs (Host to GuC - H2G, GuC to Host - G2H) are a message interface between the i915 and GuC.h]hCommand Transport buffers (CTBs): Covered in detail in other sections but CTBs (Host to GuC - H2G, GuC to Host - G2H) are a message interface between the i915 and GuC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK/hjhhubh)}(hX#Context registration: Before a context can be submitted it must be registered with the GuC via a H2G. A unique guc_id is associated with each context. The context is either registered at request creation time (normal operation) or at submission time (abnormal operation, e.g. after a reset).h]hX#Context registration: Before a context can be submitted it must be registered with the GuC via a H2G. A unique guc_id is associated with each context. The context is either registered at request creation time (normal operation) or at submission time (abnormal operation, e.g. after a reset).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK3hjhhubh)}(hXContext submission: The i915 updates the LRC tail value in memory. The i915 must enable the scheduling of the context within the GuC for the GuC to actually consider it. Therefore, the first time a disabled context is submitted we use a schedule enable H2G, while follow up submissions are done via the context submit H2G, which informs the GuC that a previously enabled context has new work available.h]hXContext submission: The i915 updates the LRC tail value in memory. The i915 must enable the scheduling of the context within the GuC for the GuC to actually consider it. Therefore, the first time a disabled context is submitted we use a schedule enable H2G, while follow up submissions are done via the context submit H2G, which informs the GuC that a previously enabled context has new work available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK9hjhhubh)}(hX7Context unpin: To unpin a context a H2G is used to disable scheduling. When the corresponding G2H returns indicating the scheduling disable operation has completed it is safe to unpin the context. While a disable is in flight it isn't safe to resubmit the context so a fence is used to stall all future requests of that context until the G2H is returned. Because this interaction with the GuC takes a non-zero amount of time we delay the disabling of scheduling after the pin count goes to zero by a configurable period of time (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a window of time to resubmit something on the context before doing this costly operation. This delay is only done if the context isn't closed and the guc_id usage is less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).h]hX;Context unpin: To unpin a context a H2G is used to disable scheduling. When the corresponding G2H returns indicating the scheduling disable operation has completed it is safe to unpin the context. While a disable is in flight it isn’t safe to resubmit the context so a fence is used to stall all future requests of that context until the G2H is returned. Because this interaction with the GuC takes a non-zero amount of time we delay the disabling of scheduling after the pin count goes to zero by a configurable period of time (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a window of time to resubmit something on the context before doing this costly operation. This delay is only done if the context isn’t closed and the guc_id usage is less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKAhjhhubh)}(hXContext deregistration: Before a context can be destroyed or if we steal its guc_id we must deregister the context with the GuC via H2G. If stealing the guc_id it isn't safe to submit anything to this guc_id until the deregister completes so a fence is used to stall all requests associated with this guc_id until the corresponding G2H returns indicating the guc_id has been deregistered.h]hXContext deregistration: Before a context can be destroyed or if we steal its guc_id we must deregister the context with the GuC via H2G. If stealing the guc_id it isn’t safe to submit anything to this guc_id until the deregister completes so a fence is used to stall all requests associated with this guc_id until the corresponding G2H returns indicating the guc_id has been deregistered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKNhjhhubh)}(hsubmission_state.guc_ids: Unique number associated with private GuC context data passed in during context registration / submission / deregistration. 64k available. Simple ida is used for allocation.h]hsubmission_state.guc_ids: Unique number associated with private GuC context data passed in during context registration / submission / deregistration. 64k available. Simple ida is used for allocation.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKUhjhhubh)}(hX Stealing guc_ids: If no guc_ids are available they can be stolen from another context at request creation time if that context is unpinned. If a guc_id can't be found we punt this problem to the user as we believe this is near impossible to hit during normal use cases.h]hXStealing guc_ids: If no guc_ids are available they can be stolen from another context at request creation time if that context is unpinned. If a guc_id can’t be found we punt this problem to the user as we believe this is near impossible to hit during normal use cases.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKZhjhhubh)}(hrLocking: In the GuC submission code we have 3 basic spin locks which protect everything. Details about each below.h]hrLocking: In the GuC submission code we have 3 basic spin locks which protect everything. Details about each below.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chK`hjhhubh)}(hX/sched_engine->lock This is the submission lock for all contexts that share an i915 schedule engine (sched_engine), thus only one of the contexts which share a sched_engine can be submitting at a time. Currently only one sched_engine is used for all of GuC submission but that could change in the future.h]hX/sched_engine->lock This is the submission lock for all contexts that share an i915 schedule engine (sched_engine), thus only one of the contexts which share a sched_engine can be submitting at a time. Currently only one sched_engine is used for all of GuC submission but that could change in the future.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKdhjhhubh)}(hnguc->submission_state.lock Global lock for GuC submission state. Protects guc_ids and destroyed contexts list.h]hnguc->submission_state.lock Global lock for GuC submission state. Protects guc_ids and destroyed contexts list.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKjhjhhubh)}(hXce->guc_state.lock Protects everything under ce->guc_state. Ensures that a context is in the correct state before issuing a H2G. e.g. We don't issue a schedule disable on a disabled context (bad idea), we don't issue a schedule enable when a schedule disable is in flight, etc... Also protects list of inflight requests on the context and the priority management state. Lock is individual to each context.h]hXce->guc_state.lock Protects everything under ce->guc_state. Ensures that a context is in the correct state before issuing a H2G. e.g. We don’t issue a schedule disable on a disabled context (bad idea), we don’t issue a schedule enable when a schedule disable is in flight, etc... Also protects list of inflight requests on the context and the priority management state. Lock is individual to each context.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKnhjhhubh)}(hnLock ordering rules: sched_engine->lock -> ce->guc_state.lock guc->submission_state.lock -> ce->guc_state.lockh]hnLock ordering rules: sched_engine->lock -> ce->guc_state.lock guc->submission_state.lock -> ce->guc_state.lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKvhjhhubh)}(hXReset races: When a full GT reset is triggered it is assumed that some G2H responses to H2Gs can be lost as the GuC is also reset. Losing these G2H can prove to be fatal as we do certain operations upon receiving a G2H (e.g. destroy contexts, release guc_ids, etc...). When this occurs we can scrub the context state and cleanup appropriately, however this is quite racey. To avoid races, the reset code must disable submission before scrubbing for the missing G2H, while the submission code must check for submission being disabled and skip sending H2Gs and updating context states when it is. Both sides must also make sure to hold the relevant locks.h]hXReset races: When a full GT reset is triggered it is assumed that some G2H responses to H2Gs can be lost as the GuC is also reset. Losing these G2H can prove to be fatal as we do certain operations upon receiving a G2H (e.g. destroy contexts, release guc_ids, etc...). When this occurs we can scrub the context state and cleanup appropriately, however this is quite racey. To avoid races, the reset code must disable submission before scrubbing for the missing G2H, while the submission code must check for submission being disabled and skip sending H2Gs and updating context states when it is. Both sides must also make sure to hold the relevant locks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:541: ./drivers/gpu/drm/i915/gt/uc/intel_guc_submission.chKzhjhhubeh}(h]guc-based-command-submissionah ]h"]guc-based command submissionah$]h&]uh1hhj~hhhhhMubh)}(hhh](h)}(hGuC ABIh]hGuC ABI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM!ubhtarget)}(h.. _HXG Message:h]h}(h]h ]h"]h$]h&]j: hxg-messageuh1jhKhjhhhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hjKubh)}(h**HXG Message**h]jb)}(hjh]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"] hxg messageah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhexpect_referenced_by_name}jjsexpect_referenced_by_id}jjsjKubh)}(hAll messages exchanged with GuC are defined using 32 bit dwords. First dword is treated as a message header. Remaining dwords are optional.h]hAll messages exchanged with GuC are defined using 32 bit dwords. First dword is treated as a message header. Remaining dwords are optional.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK hjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | | | | | 0 | 31 | **ORIGIN** - originator of the message | | | | - _`GUC_HXG_ORIGIN_HOST` = 0 | | | | - _`GUC_HXG_ORIGIN_GUC` = 1 | | | | | | +-------+--------------------------------------------------------------+ | | 30:28 | **TYPE** - message type | | | | - _`GUC_HXG_TYPE_REQUEST` = 0 | | | | - _`GUC_HXG_TYPE_EVENT` = 1 | | | | - _`GUC_HXG_TYPE_FAST_REQUEST` = 2 | | | | - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3 | | | | - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5 | | | | - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6 | | | | - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7 | | +-------+--------------------------------------------------------------+ | | 27:0 | **AUX** - auxiliary data (depends on TYPE) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **PAYLOAD** - optional payload (depends on TYPE) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hj)ubj-)}(hhh]h)}(hBitsh]hBits}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj7ubah}(h]h ]h"]h$]h&]uh1j,hj)ubj-)}(hhh]h)}(h Descriptionh]h Description}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhKhjOubah}(h]h ]h"]h$]h&]uh1j,hj)ubeh}(h]h ]h"]h$]h&]uh1j'hj$ubah}(h]h ]h"]h$]h&]uh1j"hjubhtbody)}(hhh](j()}(hhh](j-)}(hhh]h)}(h0h]h0}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjzubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjwubj-)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjwubj-)}(hhh]jx)}(hhh]j})}(h`**ORIGIN** - originator of the message - _`GUC_HXG_ORIGIN_HOST` = 0 - _`GUC_HXG_ORIGIN_GUC` = 1 h](j)}(h&**ORIGIN** - originator of the messageh](jb)}(h **ORIGIN**h]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - originator of the message}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubj)}(hhh]j:)}(hhh](j:)}(h_`GUC_HXG_ORIGIN_HOST` = 0h]h)}(hjh](j)}(h_`GUC_HXG_ORIGIN_HOST`h]hGUC_HXG_ORIGIN_HOST}(hjhhhNhNubah}(h]guc-hxg-origin-hostah ]h"]guc_hxg_origin_hostah$]h&]uh1jhjjKubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h_`GUC_HXG_ORIGIN_GUC` = 1 h]h)}(h_`GUC_HXG_ORIGIN_GUC` = 1h](j)}(h_`GUC_HXG_ORIGIN_GUC`h]hGUC_HXG_ORIGIN_GUC}(hjhhhNhNubah}(h]guc-hxg-origin-gucah ]h"]guc_hxg_origin_gucah$]h&]uh1jhjjKubh = 1}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubah}(h]h ]h"]h$]h&]uh1jwhjubah}(h]h ]h"]h$]h&]uh1j,hjwubeh}(h]h ]h"]h$]h&]uh1j'hjtubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjNubah}(h]h ]h"]h$]h&]uh1j,hjKubj-)}(hhh]jx)}(hhh]j})}(hX**TYPE** - message type - _`GUC_HXG_TYPE_REQUEST` = 0 - _`GUC_HXG_TYPE_EVENT` = 1 - _`GUC_HXG_TYPE_FAST_REQUEST` = 2 - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3 - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5 - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6 - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7h](j)}(h**TYPE** - message typeh](jb)}(h**TYPE**h]hTYPE}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjpubh - message type}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjlubj)}(hhh]j:)}(hhh](j:)}(h_`GUC_HXG_TYPE_REQUEST` = 0h]h)}(hjh](j)}(h_`GUC_HXG_TYPE_REQUEST`h]hGUC_HXG_TYPE_REQUEST}(hjhhhNhNubah}(h]guc-hxg-type-requestah ]h"]guc_hxg_type_requestah$]h&]uh1jhjjKubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h_`GUC_HXG_TYPE_EVENT` = 1h]h)}(hjh](j)}(h_`GUC_HXG_TYPE_EVENT`h]hGUC_HXG_TYPE_EVENT}(hjhhhNhNubah}(h]guc-hxg-type-eventah ]h"]guc_hxg_type_eventah$]h&]uh1jhjjKubh = 1}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h _`GUC_HXG_TYPE_FAST_REQUEST` = 2h]h)}(hjh](j)}(h_`GUC_HXG_TYPE_FAST_REQUEST`h]hGUC_HXG_TYPE_FAST_REQUEST}(hjhhhNhNubah}(h]guc-hxg-type-fast-requestah ]h"]guc_hxg_type_fast_requestah$]h&]uh1jhjjKubh = 2}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h$_`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3h]h)}(hj h](j)}(h _`GUC_HXG_TYPE_NO_RESPONSE_BUSY`h]hGUC_HXG_TYPE_NO_RESPONSE_BUSY}(hjhhhNhNubah}(h]guc-hxg-type-no-response-busyah ]h"]guc_hxg_type_no_response_busyah$]h&]uh1jhjjKubh = 3}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h%_`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5h]h)}(hj5h](j)}(h!_`GUC_HXG_TYPE_NO_RESPONSE_RETRY`h]hGUC_HXG_TYPE_NO_RESPONSE_RETRY}(hj:hhhNhNubah}(h]guc-hxg-type-no-response-retryah ]h"]guc_hxg_type_no_response_retryah$]h&]uh1jhj7jKubh = 5}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj3ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h$_`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6h]h)}(hj]h](j)}(h _`GUC_HXG_TYPE_RESPONSE_FAILURE`h]hGUC_HXG_TYPE_RESPONSE_FAILURE}(hjbhhhNhNubah}(h]guc-hxg-type-response-failureah ]h"]guc_hxg_type_response_failureah$]h&]uh1jhj_jKubh = 6}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhj[ubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h$_`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7h]h)}(hjh](j)}(h _`GUC_HXG_TYPE_RESPONSE_SUCCESS`h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]guc-hxg-type-response-successah ]h"]guc_hxg_type_response_successah$]h&]uh1jhjjKubh = 7}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjiubah}(h]h ]h"]h$]h&]uh1jwhjfubah}(h]h ]h"]h$]h&]uh1j,hjKubeh}(h]h ]h"]h$]h&]uh1j'hjtubj()}(hhh](j-)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h***AUX** - auxiliary data (depends on TYPE)h](jb)}(h**AUX**h]hAUX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh# - auxiliary data (depends on TYPE)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjtubj()}(hhh](j-)}(hhh]h)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK!hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hK!hj/ubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h0**PAYLOAD** - optional payload (depends on TYPE)h](jb)}(h **PAYLOAD**h]hPAYLOAD}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjIubh% - optional payload (depends on TYPE)}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK#hjFubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjtubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehK#hjvubah}(h]h ]h"]h$]h&]uh1j,hjsubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjsubeh}(h]h ]h"]h$]h&]uh1j'hjtubj()}(hhh](j-)}(hhh]h)}(hjGh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK%hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK%hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjtubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK hjhhubj)}(h.. _HXG Request:h]h}(h]h ]h"]h$]h&]j: hxg-requestuh1jhK$hjhhhjjKubh)}(h**HXG Request**h]jb)}(hjh]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"] hxg requestah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK+hjhhj}j jsj}jjsjKubh)}(h}The `HXG Request`_ message should be used to initiate synchronous activity for which confirmation or return data is expected.h](hThe }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjj:Kubhk message should be used to initiate synchronous activity for which confirmation or return data is expected.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK;hjhhubh)}(hThe recipient of this message shall use `HXG Response`_, `HXG Failure`_ or `HXG Retry`_ message as a definite reply, and may use `HXG Busy`_ message as a intermediate reply.h](h(The recipient of this message shall use }(hj6hhhNhNubj!5)}(h`HXG Response`_h]h HXG Response}(hj>hhhNhNubah}(h]h ]h"]h$]h&]name HXG Responsej: hxg-responseuh1j 5hj6j:Kubh, }(hj6hhhNhNubj!5)}(h`HXG Failure`_h]h HXG Failure}(hjShhhNhNubah}(h]h ]h"]h$]h&]name HXG Failurej: hxg-failureuh1j 5hj6j:Kubh or }(hj6hhhNhNubj!5)}(h `HXG Retry`_h]h HXG Retry}(hjhhhhNhNubah}(h]h ]h"]h$]h&]name HXG Retryj: hxg-retryuh1j 5hj6j:Kubh* message as a definite reply, and may use }(hj6hhhNhNubj!5)}(h `HXG Busy`_h]hHXG Busy}(hj}hhhNhNubah}(h]h ]h"]h$]h&]nameHXG Busyj:hxg-busyuh1j 5hj6j:Kubh! message as a intermediate reply.}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK>hjhhubh)}(hLFormat of **DATA0** and all **DATAn** fields depends on the **ACTION** code.h](h Format of }(hjhhhNhNubjb)}(h **DATA0**h]hDATA0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and all }(hjhhhNhNubjb)}(h **DATAn**h]hDATAn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh fields depends on the }(hjhhhNhNubjb)}(h **ACTION**h]hACTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh code.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKBhjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **DATA0** - request data (depends on ACTION) | | +-------+--------------------------------------------------------------+ | | 15:0 | **ACTION** - requested action code | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - optional data (depends on ACTION) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKEhjubah}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(h Descriptionh]h Description}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKEhj-ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKGhjVubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjSubj-)}(hhh]h)}(h31h]h31}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhKGhjnubah}(h]h ]h"]h$]h&]uh1j,hjSubj-)}(hhh]h)}(hORIGINh]hORIGIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhKGhjubah}(h]h ]h"]h$]h&]uh1j,hjSubeh}(h]h ]h"]h$]h&]uh1j'hjPubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKIhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESTj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKIhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjPubj()}(hhh](j-)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h,**DATA0** - request data (depends on ACTION)h](jb)}(h **DATA0**h]hDATA0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh# - request data (depends on ACTION)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjPubj()}(hhh](j-)}(hhh]h)}(h15:0h]h15:0}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKMhj3ubah}(h]h ]h"]h$]h&]uh1j,hj0ubj-)}(hhh]h)}(h"**ACTION** - requested action codeh](jb)}(h **ACTION**h]hACTION}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNubh - requested action code}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjDhKMhjKubah}(h]h ]h"]h$]h&]uh1j,hj0ubeh}(h]h ]h"]h$]h&]uh1j'hjPubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKOhjyubah}(h]h ]h"]h$]h&]uh1j,hjvubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKOhjubah}(h]h ]h"]h$]h&]uh1j,hjvubj-)}(hhh]h)}(h-**DATAn** - optional data (depends on ACTION)h](jb)}(h **DATAn**h]hDATAn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh$ - optional data (depends on ACTION)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKQhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjvubeh}(h]h ]h"]h$]h&]uh1j'hjPubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKQhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjPubj()}(hhh](j-)}(hhh]h)}(hjGh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKShjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKShjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjPubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKDhjhhubj)}(h.. _HXG Fast Request:h]h}(h]h ]h"]h$]h&]j:hxg-fast-requestuh1jhKDhjhhhjjKubh)}(h**HXG Fast Request**h]jb)}(hj[h]hHXG Fast Request}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjYubah}(h]jXah ]h"]hxg fast requestah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKYhjhhj}jnjNsj}jXjNsjKubh)}(hThe `HXG Request`_ message should be used to initiate asynchronous activity for which confirmation or return data is not expected.h](hThe }(hjthhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hj|hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjtj:Kubhp message should be used to initiate asynchronous activity for which confirmation or return data is not expected.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK_hjhhubh)}(hFIf confirmation is required then `HXG Request`_ shall be used instead.h](h!If confirmation is required then }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjj:Kubh shall be used instead.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKbhjhhubh)}(h~The recipient of this message may only use `HXG Failure`_ message if it was unable to accept this request (like invalid data).h](h+The recipient of this message may only use }(hjhhhNhNubj!5)}(h`HXG Failure`_h]h HXG Failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Failurej:jcuh1j 5hjj:KubhE message if it was unable to accept this request (like invalid data).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKdhjhhubh)}(hPFormat of `HXG Fast Request`_ message is same as `HXG Request`_ except **TYPE**.h](h Format of }(hjhhhNhNubj!5)}(h`HXG Fast Request`_h]hHXG Fast Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameHXG Fast Requestj:jXuh1j 5hjj:Kubh message is same as }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjj:Kubh except }(hjhhhNhNubjb)}(h**TYPE**h]hTYPE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKghjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN - see `HXG Message`_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = `GUC_HXG_TYPE_FAST_REQUEST`_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 - see `HXG Request`_ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION - see `HXG Request`_ | +---+-------+--------------------------------------------------------------+ |...| | DATAn - see `HXG Request`_ | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj-ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj-ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj-ubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjQubj-)}(hhh]h)}(hBitsh]hBits}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKjhj]ubah}(h]h ]h"]h$]h&]uh1j,hjQubj-)}(hhh]h)}(h Descriptionh]h Description}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhKjhjuubah}(h]h ]h"]h$]h&]uh1j,hjQubeh}(h]h ]h"]h$]h&]uh1j'hjNubah}(h]h ]h"]h$]h&]uh1j"hj-ubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKlhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjubj-)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKlhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hORIGIN - see `HXG Message`_h](h ORIGIN - see }(hjhhhNhNubj!5)}(h`HXG Message`_h]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagej:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKlhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKnhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h#TYPE = `GUC_HXG_TYPE_FAST_REQUEST`_h](hTYPE = }(hjhhhNhNubj!5)}(h`GUC_HXG_TYPE_FAST_REQUEST`_h]hGUC_HXG_TYPE_FAST_REQUEST}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_FAST_REQUESTj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKnhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h27:16h]h27:16}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKphjEubah}(h]h ]h"]h$]h&]uh1j,hjBubj-)}(hhh]h)}(hDATA0 - see `HXG Request`_h](h DATA0 - see }(hj`hhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hj`j:Kubeh}(h]h ]h"]h$]h&]uh1hhjVhKphj]ubah}(h]h ]h"]h$]h&]uh1j,hjBubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKrhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hACTION - see `HXG Request`_h](h ACTION - see }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKrhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKthjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hDATAn - see `HXG Request`_h](h DATAn - see }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKthjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jrhj-ubeh}(h]h ]h"]h$]h&]colsKuh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKihjhhubj)}(h.. _HXG Event:h]h}(h]h ]h"]h$]h&]j: hxg-eventuh1jhKahjhhhjjKubh)}(h **HXG Event**h]jb)}(hjJh]h HXG Event}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjHubah}(h]jGah ]h"] hxg eventah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKzhjhhj}j]j=sj}jGj=sjKubh)}(hThe `HXG Event`_ message should be used to initiate asynchronous activity that does not involves immediate confirmation nor data.h](hThe }(hjchhhNhNubj!5)}(h `HXG Event`_h]h HXG Event}(hjkhhhNhNubah}(h]h ]h"]h$]h&]name HXG Eventj:jGuh1j 5hjcj:Kubhq message should be used to initiate asynchronous activity that does not involves immediate confirmation nor data.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK{hjhhubh)}(hLFormat of **DATA0** and all **DATAn** fields depends on the **ACTION** code.h](h Format of }(hjhhhNhNubjb)}(h **DATA0**h]hDATA0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh and all }(hjhhhNhNubjb)}(h **DATAn**h]hDATAn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh fields depends on the }(hjhhhNhNubjb)}(h **ACTION**h]hACTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh code.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhK~hjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_EVENT_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **DATA0** - event data (depends on ACTION) | | +-------+--------------------------------------------------------------+ | | 15:0 | **ACTION** - event action code | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - optional event data (depends on ACTION) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjCubah}(h]h ]h"]h$]h&]morerowsKuh1j,hj@ubj-)}(hhh]h)}(h31h]h31}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShKhj[ubah}(h]h ]h"]h$]h&]uh1j,hj@ubj-)}(hhh]h)}(hORIGINh]hORIGIN}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShKhjrubah}(h]h ]h"]h$]h&]uh1j,hj@ubeh}(h]h ]h"]h$]h&]uh1j'hj=ubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_EVENT_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_EVENT_h]hGUC_HXG_TYPE_EVENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_EVENTj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj=ubj()}(hhh](j-)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h***DATA0** - event data (depends on ACTION)h](jb)}(h **DATA0**h]hDATA0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh! - event data (depends on ACTION)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj=ubj()}(hhh](j-)}(hhh]h)}(h15:0h]h15:0}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj ubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h**ACTION** - event action codeh](jb)}(h **ACTION**h]hACTION}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj;ubh - event action code}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj1hKhj8ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj=ubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjfubah}(h]h ]h"]h$]h&]uh1j,hjcubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhKhj}ubah}(h]h ]h"]h$]h&]uh1j,hjcubj-)}(hhh]h)}(h4**DATAn** - optional event data (depends on ACTION)h](jb)}(h **DATAn**h]hDATAn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh+ - optional event data (depends on ACTION)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjcubeh}(h]h ]h"]h$]h&]uh1j'hj=ubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj=ubj()}(hhh](j-)}(hhh]h)}(hjGh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj=ubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(h .. _HXG Busy:h]h}(h]h ]h"]h$]h&]j:juh1jhK}hjhhhjjKubh)}(h **HXG Busy**h]jb)}(hjGh]hHXG Busy}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjEubah}(h]jah ]h"]hxg busyah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhj}jZj;sj}jj;sjKubh)}(hThe `HXG Busy`_ message may be used to acknowledge reception of the `HXG Request`_ message if the recipient expects that it processing will be longer than default timeout.h](hThe }(hj`hhhNhNubj!5)}(h `HXG Busy`_h]hHXG Busy}(hjhhhhNhNubah}(h]h ]h"]h$]h&]nameHXG Busyj:juh1j 5hj`j:Kubh5 message may be used to acknowledge reception of the }(hj`hhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hj|hhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hj`j:KubhY message if the recipient expects that it processing will be longer than default timeout.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubh)}(h:The **COUNTER** field may be used as a progress indicator.h](hThe }(hjhhhNhNubjb)}(h **COUNTER**h]hCOUNTER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh+ field may be used as a progress indicator.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_NO_RESPONSE_BUSY_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **COUNTER** - progress indicator | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj0ubah}(h]h ]h"]h$]h&]morerowsKuh1j,hj-ubj-)}(hhh]h)}(h31h]h31}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hKhjHubah}(h]h ]h"]h$]h&]uh1j,hj-ubj-)}(hhh]h)}(hORIGINh]hORIGIN}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hKhj_ubah}(h]h ]h"]h$]h&]uh1j,hj-ubeh}(h]h ]h"]h$]h&]uh1j'hj*ubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hj|ubj-)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_NO_RESPONSE_BUSY_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_NO_RESPONSE_BUSY_h]hGUC_HXG_TYPE_NO_RESPONSE_BUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_NO_RESPONSE_BUSYj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hj|ubeh}(h]h ]h"]h$]h&]uh1j'hj*ubj()}(hhh](j-)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h **COUNTER** - progress indicatorh](jb)}(h **COUNTER**h]hCOUNTER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - progress indicator}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj*ubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(h.. _HXG Retry:h]h}(h]h ]h"]h$]h&]j:jxuh1jhKhjhhhjjKubh)}(h **HXG Retry**h]jb)}(hj0h]h HXG Retry}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj.ubah}(h]jxah ]h"] hxg retryah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhj}jCj$sj}jxj$sjKubh)}(hThe `HXG Retry`_ message should be used by recipient to indicate that the `HXG Request`_ message was dropped and it should be resent again.h](hThe }(hjIhhhNhNubj!5)}(h `HXG Retry`_h]h HXG Retry}(hjQhhhNhNubah}(h]h ]h"]h$]h&]name HXG Retryj:jxuh1j 5hjIj:Kubh: message should be used by recipient to indicate that the }(hjIhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjehhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjIj:Kubh3 message was dropped and it should be resent again.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubh)}(hCThe **REASON** field may be used to provide additional information.h](hThe }(hjhhhNhNubjb)}(h **REASON**h]hREASON}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh5 field may be used to provide additional information.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_NO_RESPONSE_RETRY_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **REASON** - reason for retry | | | | - _`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0 | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjubj-)}(hhh]h)}(h31h]h31}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKhj1ubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hORIGINh]hORIGIN}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKhjHubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhubah}(h]h ]h"]h$]h&]uh1j,hjeubj-)}(hhh]h)}(h&TYPE = GUC_HXG_TYPE_NO_RESPONSE_RETRY_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_NO_RESPONSE_RETRY_h]hGUC_HXG_TYPE_NO_RESPONSE_RETRY}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_NO_RESPONSE_RETRYj:jDuh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjyhKhjubah}(h]h ]h"]h$]h&]uh1j,hjeubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]jx)}(hhh]j})}(hG**REASON** - reason for retry - _`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0h](j)}(h**REASON** - reason for retryh](jb)}(h **REASON**h]hREASON}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - reason for retry}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hhh]j:)}(hhh]j:)}(h'_`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0h]h)}(hjh](j)}(h#_`GUC_HXG_RETRY_REASON_UNSPECIFIED`h]h GUC_HXG_RETRY_REASON_UNSPECIFIED}(hjhhhNhNubah}(h] guc-hxg-retry-reason-unspecifiedah ]h"] guc_hxg_retry_reason_unspecifiedah$]h&]uh1jhjubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubah}(h]h ]h"]h$]h&]uh1jwhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(h.. _HXG Failure:h]h}(h]h ]h"]h$]h&]j:jcuh1jhKhjhhhjjKubh)}(h**HXG Failure**h]jb)}(hjfh]h HXG Failure}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjdubah}(h]jcah ]h"] hxg failureah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhj}jyjZsj}jcjZsjKubh)}(h~The `HXG Failure`_ message shall be used as a reply to the `HXG Request`_ message that could not be processed due to an error.h](hThe }(hjhhhNhNubj!5)}(h`HXG Failure`_h]h HXG Failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Failurej:jcuh1j 5hjj:Kubh) message shall be used as a reply to the }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjj:Kubh5 message that could not be processed due to an error.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(hXP+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_FAILURE_ | | +-------+--------------------------------------------------------------+ | | 27:16 | **HINT** - additional error hint | | +-------+--------------------------------------------------------------+ | | 15:0 | **ERROR** - error/result code | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj.ubah}(h]h ]h"]h$]h&]morerowsKuh1j,hj+ubj-)}(hhh]h)}(h31h]h31}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hKhjFubah}(h]h ]h"]h$]h&]uh1j,hj+ubj-)}(hhh]h)}(hORIGINh]hORIGIN}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hKhj]ubah}(h]h ]h"]h$]h&]uh1j,hj+ubeh}(h]h ]h"]h$]h&]uh1j'hj(ubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj}ubah}(h]h ]h"]h$]h&]uh1j,hjzubj-)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_FAILURE_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_RESPONSE_FAILURE_h]hGUC_HXG_TYPE_RESPONSE_FAILURE}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_FAILUREj:jluh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjzubeh}(h]h ]h"]h$]h&]uh1j'hj(ubj()}(hhh](j-)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h **HINT** - additional error hinth](jb)}(h**HINT**h]hHINT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - additional error hint}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj(ubj()}(hhh](j-)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj ubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h**ERROR** - error/result codeh](jb)}(h **ERROR**h]hERROR}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj&ubh - error/result code}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhj#ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj(ubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(h.. _HXG Response:h]h}(h]h ]h"]h$]h&]j:jNuh1jhKhjhhhjjKubh)}(h**HXG Response**h]jb)}(hjth]h HXG Response}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjrubah}(h]jNah ]h"] hxg responseah$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhj}jjhsj}jNjhsjKubh)}(hThe `HXG Response`_ message shall be used as a reply to the `HXG Request`_ message that was successfully processed without an error.h](hThe }(hjhhhNhNubj!5)}(h`HXG Response`_h]h HXG Response}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Responsej:jNuh1j 5hjj:Kubh) message shall be used as a reply to the }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjj:Kubh: message that was successfully processed without an error.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | **DATA0** - data (depends on ACTION from `HXG Request`_) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | **DATAn** - data (depends on ACTION from `HXG Request`_) | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj<ubah}(h]h ]h"]h$]h&]morerowsKuh1j,hj9ubj-)}(hhh]h)}(h31h]h31}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhKhjTubah}(h]h ]h"]h$]h&]uh1j,hj9ubj-)}(hhh]h)}(hORIGINh]hORIGIN}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhKhjkubah}(h]h ]h"]h$]h&]uh1j,hj9ubeh}(h]h ]h"]h$]h&]uh1j'hj6ubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESSj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj6ubj()}(hhh](j-)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h8**DATA0** - data (depends on ACTION from `HXG Request`_)h](jb)}(h **DATA0**h]hDATA0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - data (depends on ACTION from }(hjhhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hjj:Kubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj6ubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj-ubah}(h]h ]h"]h$]h&]uh1j,hj*ubj-)}(hhh]h)}(h31:0h]h31:0}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKhjDubah}(h]h ]h"]h$]h&]uh1j,hj*ubj-)}(hhh]h)}(h8**DATAn** - data (depends on ACTION from `HXG Request`_)h](jb)}(h **DATAn**h]hDATAn}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj^ubh - data (depends on ACTION from }(hj^hhhNhNubj!5)}(h`HXG Request`_h]h HXG Request}(hjthhhNhNubah}(h]h ]h"]h$]h&]name HXG Requestj:juh1j 5hj^j:Kubh)}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhj[ubah}(h]h ]h"]h$]h&]morerowsKuh1j,hj*ubeh}(h]h ]h"]h$]h&]uh1j'hj6ubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj6ubj()}(hhh](j-)}(hhh]h)}(hjGh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.hhKhjhhubj)}(h!.. _GuC MMIO based communication:h]h}(h]h ]h"]h$]h&]j:guc-mmio-based-communicationuh1jhKhjhhhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hubh)}(h **GuC MMIO based communication**h]jb)}(hj$h]hGuC MMIO based communication}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj"ubah}(h]j ah ]h"]guc mmio based communicationah$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhj}j7jsj}j jsubh)}(hThe MMIO based communication between Host and GuC relies on special hardware registers which format could be defined by the software (so called scratch registers).h]hThe MMIO based communication between Host and GuC relies on special hardware registers which format could be defined by the software (so called scratch registers).}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK hjhhubh)}(hEach MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) messages, which maximum length depends on number of available scratch registers, is directly written into those scratch registers.h]hEach MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) messages, which maximum length depends on number of available scratch registers, is directly written into those scratch registers.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhubh)}(hFor Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, but no H2G command takes more than 4 parameters and the GuC firmware itself uses an 4-element array to store the H2G message.h]hFor Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, but no H2G command takes more than 4 parameters and the GuC firmware itself uses an 4-element array to store the H2G message.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhubh)}(hFor Gen11+, there are additional 4 registers 0x190240-0x19024C, which are, regardless on lower count, preferred over legacy ones.h]hFor Gen11+, there are additional 4 registers 0x190240-0x19024C, which are, regardless on lower count, preferred over legacy ones.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhubh)}(hThe MMIO based communication is mainly used during driver initialization phase to setup the `CTB based communication`_ that will be used afterwards.h](h\The MMIO based communication is mainly used during driver initialization phase to setup the }(hjyhhhNhNubj!5)}(h`CTB based communication`_h]hCTB based communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameCTB based communicationj:ctb-based-communicationuh1j 5hjyj:Kubh that will be used afterwards.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhubj)}(h.. _MMIO HXG Message:h]h}(h]h ]h"]h$]h&]j:mmio-hxg-messageuh1jhKhjhhhj!jKubh)}(h**MMIO HXG Message**h]jb)}(hjh]hMMIO HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]mmio hxg messageah$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhKhjhhj}jjsj}jjsjKubh)}(hBFormat of the MMIO messages follows definitions of `HXG Message`_.h](h3Format of the MMIO messages follows definitions of }(hjhhhNhNubj!5)}(h`HXG Message`_h]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagej:juh1j 5hjj:Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK"hjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:0 | | +---+-------+ | |...| | [Embedded `HXG Message`_] | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK%hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hK%hj5ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK'hj^ubah}(h]h ]h"]h$]h&]uh1j,hj[ubj-)}(hhh]h)}(h31:0h]h31:0}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhK'hjuubah}(h]h ]h"]h$]h&]uh1j,hj[ubj-)}(hhh]h)}(h[Embedded `HXG Message`_]h](h [Embedded }(hjhhhNhNubj!5)}(h`HXG Message`_h]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagej:juh1j 5hjj:Kubh]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK)hjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hj[ubeh}(h]h ]h"]h$]h&]uh1j'hjXubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK)hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjXubj()}(hhh](j-)}(hhh]h)}(hjGh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK+hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK+hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjXubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.hhK$hjhhubj)}(h.. _CT Buffer:h]h}(h]h ]h"]h$]h&]j: ct-bufferuh1jhKhjhhhNjKubh)}(h **CT Buffer**h]jb)}(hjFh]h CT Buffer}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjDubah}(h]jCah ]h"] ct bufferah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhj}jYj9sj}jCj9sjKubh)}(h+Circular buffer used to send `CTB Message`_h](hCircular buffer used to send }(hj_hhhNhNubj!5)}(h`CTB Message`_h]h CTB Message}(hjghhhNhNubah}(h]h ]h"]h$]h&]name CTB Messagej: ctb-messageuh1j 5hj_j:Kubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubj)}(h.. _CTB Descriptor:h]h}(h]h ]h"]h$]h&]j:ctb-descriptoruh1jhKhjhhhNjKubh)}(h**CTB Descriptor**h]jb)}(hjh]hCTB Descriptor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]ctb descriptorah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhj}jjsj}jjsjKubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:0 | **HEAD** - offset (in dwords) to the last dword that was | | | | read from the `CT Buffer`_. | | | | It can only be updated by the receiver. | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **TAIL** - offset (in dwords) to the last dword that was | | | | written to the `CT Buffer`_. | | | | It can only be updated by the sender. | +---+-------+--------------------------------------------------------------+ | 2 | 31:0 | **STATUS** - status of the CTB | | | | | | | | - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation) | | | | - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large) | | | | - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message) | | | | - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified) | | | | - _`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use) | +---+-------+--------------------------------------------------------------+ |...| | RESERVED = MBZ | +---+-------+--------------------------------------------------------------+ | 15| 31:0 | RESERVED = MBZ | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hKhj4ubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h|**HEAD** - offset (in dwords) to the last dword that was read from the `CT Buffer`_. It can only be updated by the receiver.h](jb)}(h**HEAD**h]hHEAD}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNubh? - offset (in dwords) to the last dword that was read from the }(hjNhhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjdhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:jCuh1j 5hjNj:Kubh). It can only be updated by the receiver.}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj-hKhjKubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h{**TAIL** - offset (in dwords) to the last dword that was written to the `CT Buffer`_. It can only be updated by the sender.h](jb)}(h**TAIL**h]hTAIL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh@ - offset (in dwords) to the last dword that was written to the }(hjhhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:jCuh1j 5hjj:Kubh'. It can only be updated by the sender.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h2h]h2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh](h)}(h**STATUS** - status of the CTBh](jb)}(h **STATUS**h]hSTATUS}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj/ubh - status of the CTB}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK hj,ubj)}(hX - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation) - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large) - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message) - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified) - _`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use)h]j:)}(hhh](j:)}(h1_`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation)h]h)}(hjTh](j)}(h_`GUC_CTB_STATUS_NO_ERROR`h]hGUC_CTB_STATUS_NO_ERROR}(hjYhhhNhNubah}(h]guc-ctb-status-no-errorah ]h"]guc_ctb_status_no_errorah$]h&]uh1jhjVubh = 0 (normal operation)}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK"hjRubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h4_`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large)h]h)}(hj|h](j)}(h_`GUC_CTB_STATUS_OVERFLOW`h]hGUC_CTB_STATUS_OVERFLOW}(hjhhhNhNubah}(h]guc-ctb-status-overflowah ]h"]guc_ctb_status_overflowah$]h&]uh1jhj~ubh = 1 (head/tail too large)}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK#hjzubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h3_`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)h]h)}(hjh](j)}(h_`GUC_CTB_STATUS_UNDERFLOW`h]hGUC_CTB_STATUS_UNDERFLOW}(hjhhhNhNubah}(h]guc-ctb-status-underflowah ]h"]guc_ctb_status_underflowah$]h&]uh1jhjubh = 2 (truncated message)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK$hjubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h3_`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)h]h)}(hjh](j)}(h_`GUC_CTB_STATUS_MISMATCH`h]hGUC_CTB_STATUS_MISMATCH}(hjhhhNhNubah}(h]guc-ctb-status-mismatchah ]h"]guc_ctb_status_mismatchah$]h&]uh1jhjubh = 4 (head/tail modified)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK%hjubah}(h]h ]h"]h$]h&]uh1j:hjOubj:)}(h0_`GUC_CTB_STATUS_UNUSED` = 8 (CTB is not in use)h]h)}(hjh](j)}(h_`GUC_CTB_STATUS_UNUSED`h]hGUC_CTB_STATUS_UNUSED}(hjhhhNhNubah}(h]guc-ctb-status-unusedah ]h"]guc_ctb_status_unusedah$]h&]uh1jhjubh = 8 (CTB is not in use)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK&hjubah}(h]h ]h"]h$]h&]uh1j:hjOubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjshK"hjKubah}(h]h ]h"]h$]h&]uh1jhjshK"hj,ubeh}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK(hj5 ubah}(h]h ]h"]h$]h&]uh1j,hj2 ubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hj2 ubj-)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF hK(hjV ubah}(h]h ]h"]h$]h&]uh1j,hj2 ubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h15h]h15}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK*hjv ubah}(h]h ]h"]h$]h&]uh1j,hjs ubj-)}(hhh]h)}(h31:0h]h31:0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK*hj ubah}(h]h ]h"]h$]h&]uh1j,hjs ubj-)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK*hj ubah}(h]h ]h"]h$]h&]uh1j,hjs ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubj)}(h.. _CTB Message:h]h}(h]h ]h"]h$]h&]j:jwuh1jhK%hjhhhNjKubh)}(h**CTB Message**h]jb)}(hj h]h CTB Message}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]jwah ]h"] ctb messageah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK0hjhhj}j j sj}jwj sjKubj)}(hXk+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | **FENCE** - message identifier | | +-------+--------------------------------------------------------------+ | | 15:12 | **FORMAT** - format of the CTB message | | | | - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_ | | +-------+--------------------------------------------------------------+ | | 11:8 | **RESERVED** | | +-------+--------------------------------------------------------------+ | | 7:0 | **NUM_DWORDS** - length of the CTB message (w/o header) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | optional (depends on FORMAT) | +---+-------+ | |...| | | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj ubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hj, ubj-)}(hhh]h)}(hBitsh]hBits}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK?hj8 ubah}(h]h ]h"]h$]h&]uh1j,hj, ubj-)}(hhh]h)}(h Descriptionh]h Description}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI hK?hjP ubah}(h]h ]h"]h$]h&]uh1j,hj, ubeh}(h]h ]h"]h$]h&]uh1j'hj) ubah}(h]h ]h"]h$]h&]uh1j"hj ubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKAhjy ubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjv ubj-)}(hhh]h)}(h31:16h]h31:16}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKAhj ubah}(h]h ]h"]h$]h&]uh1j,hjv ubj-)}(hhh]h)}(h**FENCE** - message identifierh](jb)}(h **FENCE**h]hFENCE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh - message identifier}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj hKAhj ubah}(h]h ]h"]h$]h&]uh1j,hjv ubeh}(h]h ]h"]h$]h&]uh1j'hjs ubj()}(hhh](j-)}(hhh]h)}(h15:12h]h15:12}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKChj ubah}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]jx)}(hhh]j})}(h[**FORMAT** - format of the CTB message - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_h](j)}(h&**FORMAT** - format of the CTB messageh](jb)}(h **FORMAT**h]hFORMAT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh - format of the CTB message}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhj hKChj ubj)}(hhh]j:)}(hhh]j:)}(h2_`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_h]h)}(hj h](j)}(h_`GUC_CTB_FORMAT_HXG`h]hGUC_CTB_FORMAT_HXG}(hj! hhhNhNubah}(h]guc-ctb-format-hxgah ]h"]guc_ctb_format_hxgah$]h&]uh1jhj jKubh = 0 - see }(hj hhhNhNubj!5)}(h`CTB HXG Message`_h]hCTB HXG Message}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]nameCTB HXG Messagej:ctb-hxg-messageuh1j 5hj j:Kubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKDhj ubah}(h]h ]h"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&]j[;j\;uh1j:hjL hKDhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj hKChj ubah}(h]h ]h"]h$]h&]uh1jwhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j'hjs ubj()}(hhh](j-)}(hhh]h)}(h11:8h]h11:8}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKFhjz ubah}(h]h ]h"]h$]h&]uh1j,hjw ubj-)}(hhh]h)}(h **RESERVED**h]jb)}(hj h]hRESERVED}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1hhj hKFhj ubah}(h]h ]h"]h$]h&]uh1j,hjw ubeh}(h]h ]h"]h$]h&]uh1j'hjs ubj()}(hhh](j-)}(hhh]h)}(h7:0h]h7:0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKHhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(h7**NUM_DWORDS** - length of the CTB message (w/o header)h](jb)}(h**NUM_DWORDS**h]h NUM_DWORDS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubh) - length of the CTB message (w/o header)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj hKHhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j'hjs ubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKJhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(h31:0h]h31:0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKJhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(hoptional (depends on FORMAT)h]hoptional (depends on FORMAT)}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKJhj/ ubah}(h]h ]h"]h$]h&]morerowsKuh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j'hjs ubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKLhjP ubah}(h]h ]h"]h$]h&]uh1j,hjM ubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjM ubeh}(h]h ]h"]h$]h&]uh1j'hjs ubj()}(hhh](j-)}(hhh]h)}(hjGh]hn}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKNhjz ubah}(h]h ]h"]h$]h&]uh1j,hjw ubj-)}(hhh]h)}(h31:0h]h31:0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKNhj ubah}(h]h ]h"]h$]h&]uh1j,hjw ubeh}(h]h ]h"]h$]h&]uh1j'hjs ubeh}(h]h ]h"]h$]h&]uh1jrhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK>hjhhubj)}(h.. _CTB HXG Message:h]h}(h]h ]h"]h$]h&]j:jE uh1jhK=hjhhhNjKubh)}(h**CTB HXG Message**h]jb)}(hj h]hCTB HXG Message}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]jE ah ]h"]ctb hxg messageah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKThjhhj}j j sj}jE j sjKubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | FENCE | | +-------+--------------------------------------------------------------+ | | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_ | | +-------+--------------------------------------------------------------+ | | 11:8 | RESERVED = MBZ | | +-------+--------------------------------------------------------------+ | | 7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | | +---+-------+ | |...| | [Embedded `HXG Message`_] | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj ubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(hBitsh]hBits}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK_hj$ ubah}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(h Descriptionh]h Description}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5 hK_hj< ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j'hj ubah}(h]h ]h"]h$]h&]uh1j"hj ubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKahje ubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjb ubj-)}(hhh]h)}(h31:16h]h31:16}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju hKahj} ubah}(h]h ]h"]h$]h&]uh1j,hjb ubj-)}(hhh]h)}(hFENCEh]hFENCE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju hKahj ubah}(h]h ]h"]h$]h&]uh1j,hjb ubeh}(h]h ]h"]h$]h&]uh1j'hj_ ubj()}(hhh](j-)}(hhh]h)}(h15:12h]h15:12}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKchj ubah}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(hFORMAT = GUC_CTB_FORMAT_HXG_h](h FORMAT = }(hj hhhNhNubj!5)}(hGUC_CTB_FORMAT_HXG_h]hGUC_CTB_FORMAT_HXG}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_CTB_FORMAT_HXGj:j+ uh1j 5hj j:Kubeh}(h]h ]h"]h$]h&]uh1hhj hKchj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j'hj_ ubj()}(hhh](j-)}(hhh]h)}(h11:8h]h11:8}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKehj ubah}(h]h ]h"]h$]h&]uh1j,hj ubj-)}(hhh]h)}(hRESERVED = MBZh]hRESERVED = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKehjubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j'hj_ ubj()}(hhh](j-)}(hhh]h)}(h7:0h]h7:0}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKghj4ubah}(h]h ]h"]h$]h&]uh1j,hj1ubj-)}(hhh]h)}(h;NUM_DWORDS = length (in dwords) of the embedded HXG messageh]h;NUM_DWORDS = length (in dwords) of the embedded HXG message}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhKghjLubah}(h]h ]h"]h$]h&]uh1j,hj1ubeh}(h]h ]h"]h$]h&]uh1j'hj_ ubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKihjlubah}(h]h ]h"]h$]h&]uh1j,hjiubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hKihjubah}(h]h ]h"]h$]h&]uh1j,hjiubj-)}(hhh]h)}(h[Embedded `HXG Message`_]h](h [Embedded }(hjhhhNhNubj!5)}(h`HXG Message`_h]h HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]name HXG Messagej:juh1j 5hjj:Kubh]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKkhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjiubeh}(h]h ]h"]h$]h&]uh1j'hj_ ubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKkhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj_ ubj()}(hhh](j-)}(hhh]h)}(hjGh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKmhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKmhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj_ ubeh}(h]h ]h"]h$]h&]uh1jrhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK^hjhhubj)}(h.. _CTB based communication:h]h}(h]h ]h"]h$]h&]j:juh1jhKThjhhhNjKubh)}(h**CTB based communication**h]jb)}(hjSh]hCTB based communication}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjQubah}(h]jah ]h"]ctb based communicationah$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKshjhhj}jfjGsj}jjGsjKubh)}(hThe CTB (command transport buffer) communication between Host and GuC is based on u32 data stream written to the shared buffer. One buffer can be used to transmit data only in one direction (one-directional channel).h]hThe CTB (command transport buffer) communication between Host and GuC is based on u32 data stream written to the shared buffer. One buffer can be used to transmit data only in one direction (one-directional channel).}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKwhjhhubh)}(hX Current status of the each buffer is stored in the buffer descriptor. Buffer descriptor holds tail and head fields that represents active data stream. The tail field is updated by the data producer (sender), and head field is updated by the data consumer (receiver)::h]hX Current status of the each buffer is stored in the buffer descriptor. Buffer descriptor holds tail and head fields that represents active data stream. The tail field is updated by the data producer (sender), and head field is updated by the data consumer (receiver):}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhK{hjhhubj")}(hX+------------+ | DESCRIPTOR | +=================+============+========+ +============+ | | MESSAGE(s) | | | address |--------->+=================+============+========+ +------------+ | head | ^-----head--------^ +------------+ | tail | ^---------tail-----------------^ +------------+ | size | ^---------------size--------------------^ +------------+h]hX+------------+ | DESCRIPTOR | +=================+============+========+ +============+ | | MESSAGE(s) | | | address |--------->+=================+============+========+ +------------+ | head | ^-----head--------^ +------------+ | tail | ^---------tail-----------------^ +------------+ | size | ^---------------size--------------------^ +------------+}hjsbah}(h]h ]h"]h$]h&]jjuh1j"ht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubh)}(hEach message in data stream starts with the single u32 treated as a header, followed by optional set of u32 data that makes message specific payload::h]hEach message in data stream starts with the single u32 treated as a header, followed by optional set of u32 data that makes message specific payload:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubj")}(hX+------------+---------+---------+---------+ | MESSAGE | +------------+---------+---------+---------+ | msg[0] | [1] | ... | [n-1] | +------------+---------+---------+---------+ | MESSAGE | MESSAGE PAYLOAD | + HEADER +---------+---------+---------+ | | 0 | ... | n | +======+=====+=========+=========+=========+ | 31:16| code| | | | +------+-----+ | | | | 15:5|flags| | | | +------+-----+ | | | | 4:0| len| | | | +------+-----+---------+---------+---------+ ^-------------len-------------^h]hX+------------+---------+---------+---------+ | MESSAGE | +------------+---------+---------+---------+ | msg[0] | [1] | ... | [n-1] | +------------+---------+---------+---------+ | MESSAGE | MESSAGE PAYLOAD | + HEADER +---------+---------+---------+ | | 0 | ... | n | +======+=====+=========+=========+=========+ | 31:16| code| | | | +------+-----+ | | | | 15:5|flags| | | | +------+-----+ | | | | 4:0| len| | | | +------+-----+---------+---------+---------+ ^-------------len-------------^}hjsbah}(h]h ]h"]h$]h&]jjuh1j"ht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubh)}(hThe message header consists of:h]hThe message header consists of:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjhhubj:)}(hhh](j:)}(h9**len**, indicates length of the message payload (in u32)h]h)}(hjh](jb)}(h**len**h]hlen}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh2, indicates length of the message payload (in u32)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h **code**, indicates message codeh]h)}(hjh](jb)}(h**code**h]hcode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh, indicates message code}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h;**flags**, holds various bits to control message handling h]h)}(h9**flags**, holds various bits to control message handlingh](jb)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh0, holds various bits to control message handling}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hht/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjhhubj)}(h.. _HOST2GUC_SELF_CFG:h]h}(h]h ]h"]h$]h&]j:host2guc-self-cfguh1jhKhjhhhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hjKubh)}(h**HOST2GUC_SELF_CFG**h]jb)}(hjPh]hHOST2GUC_SELF_CFG}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjNubah}(h]jLah ]h"]host2guc_self_cfgah$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjhhj}jcjBsj}jLjBsjKubh)}(hIThis message is used by Host KMD to setup of the `GuC Self Config KLVs`_.h](h1This message is used by Host KMD to setup of the }(hjihhhNhNubj!5)}(h`GuC Self Config KLVs`_h]hGuC Self Config KLVs}(hjqhhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVsj:guc-self-config-klvsuh1j 5hjij:Kubh.}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjhhubh)}(h1This message must be sent as `MMIO HXG Message`_.h](hThis message must be sent as }(hjhhhNhNubj!5)}(h`MMIO HXG Message`_h]hMMIO HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameMMIO HXG Messagej:juh1j 5hjj:Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjhhubj)}(hXU +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 = MBZ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508 | +---+-------+--------------------------------------------------------------+ | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_ | | +-------+--------------------------------------------------------------+ | | 15:0 | **KLV_LEN** - KLV length | | | | | | | | - 32 bit KLV = 1 | | | | - 64 bit KLV = 2 | +---+-------+--------------------------------------------------------------+ | 2 | 31:0 | **VALUE32** - Bits 31-0 of the KLV value | +---+-------+--------------------------------------------------------------+ | 3 | 31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2) | +---+-------+--------------------------------------------------------------+ +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized | +---+-------+--------------------------------------------------------------+ h](j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhj(ubah}(h]h ]h"]h$]h&]morerowsKuh1j,hj%ubj-)}(hhh]h)}(h31h]h31}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hKhj@ubah}(h]h ]h"]h$]h&]uh1j,hj%ubj-)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_HOST_h](h ORIGIN = }(hjZhhhNhNubj!5)}(hGUC_HXG_ORIGIN_HOST_h]hGUC_HXG_ORIGIN_HOST}(hjbhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_HOSTj:juh1j 5hjZj:Kubeh}(h]h ]h"]h$]h&]uh1hhj8hKhjWubah}(h]h ]h"]h$]h&]uh1j,hj%ubeh}(h]h ]h"]h$]h&]uh1j'hj"ubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESTj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj"ubj()}(hhh](j-)}(hhh]h)}(h27:16h]h27:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj"ubj()}(hhh](j-)}(hhh]h)}(h15:0h]h15:0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h1ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508h](h ACTION = }(hj"hhhNhNubj)}(h_`GUC_ACTION_HOST2GUC_SELF_CFG`h]hGUC_ACTION_HOST2GUC_SELF_CFG}(hj*hhhNhNubah}(h]guc-action-host2guc-self-cfgah ]h"]guc_action_host2guc_self_cfgah$]h&]uh1jhj"ubh = 0x0508}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj"ubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjSubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjPubj-)}(hhh]h)}(h31:16h]h31:16}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchKhjkubah}(h]h ]h"]h$]h&]uh1j,hjPubj-)}(hhh]h)}(h2**KLV_KEY** - KLV key, see `GuC Self Config KLVs`_h](jb)}(h **KLV_KEY**h]hKLV_KEY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - KLV key, see }(hjhhhNhNubj!5)}(h`GuC Self Config KLVs`_h]hGuC Self Config KLVs}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVsj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjchKhjubah}(h]h ]h"]h$]h&]uh1j,hjPubeh}(h]h ]h"]h$]h&]uh1j'hj"ubj()}(hhh](j-)}(hhh]h)}(h15:0h]h15:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh](h)}(h**KLV_LEN** - KLV lengthh](jb)}(h **KLV_LEN**h]hKLV_LEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - KLV length}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubj)}(h!- 32 bit KLV = 1 - 64 bit KLV = 2h]j:)}(hhh](j:)}(h32 bit KLV = 1h]h)}(hjh]h32 bit KLV = 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h64 bit KLV = 2h]h)}(hjh]h64 bit KLV = 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj"ubj()}(hhh](j-)}(hhh]h)}(hjh]h2}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK hjIubah}(h]h ]h"]h$]h&]uh1j,hjFubj-)}(hhh]h)}(h31:0h]h31:0}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhK hj`ubah}(h]h ]h"]h$]h&]uh1j,hjFubj-)}(hhh]h)}(h(**VALUE32** - Bits 31-0 of the KLV valueh](jb)}(h **VALUE32**h]hVALUE32}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjzubh - Bits 31-0 of the KLV value}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjYhK hjwubah}(h]h ]h"]h$]h&]uh1j,hjFubeh}(h]h ]h"]h$]h&]uh1j'hj"ubj()}(hhh](j-)}(hhh]h)}(h3h]h3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK"hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK"hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h;**VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2)h](jb)}(h **VALUE64**h]hVALUE64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - Bits 63-32 of the KLV value (}(hjhhhNhNubjb)}(h **KLV_LEN**h]hKLV_LEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh = 2)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK"hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj"ubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj'ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj'ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj'ubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjKubj-)}(hhh]h)}(hBitsh]hBits}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK&hjWubah}(h]h ]h"]h$]h&]uh1j,hjKubj-)}(hhh]h)}(h Descriptionh]h Description}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhK&hjoubah}(h]h ]h"]h$]h&]uh1j,hjKubeh}(h]h ]h"]h$]h&]uh1j'hjHubah}(h]h ]h"]h$]h&]uh1j"hj'ubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK(hjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjubj-)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK(hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_GUC_h](h ORIGIN = }(hjhhhNhNubj!5)}(hGUC_HXG_ORIGIN_GUC_h]hGUC_HXG_ORIGIN_GUC}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_GUCj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhK(hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK*hjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESSj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhK*hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h27:0h]h27:0}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK,hj?ubah}(h]h ]h"]h$]h&]uh1j,hj<ubj-)}(hhh]h)}(h:DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognizedh](hDATA0 = }(hjZhhhNhNubjb)}(h**NUM**h]hNUM}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZubh+ - 1 if KLV was parsed, 0 if not recognized}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjPhK,hjWubah}(h]h ]h"]h$]h&]uh1j,hj<ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jrhj'ubeh}(h]h ]h"]h$]h&]colsKuh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKhjhhubj)}(h.. _HOST2GUC_CONTROL_CTB:h]h}(h]h ]h"]h$]h&]j:host2guc-control-ctbuh1jhK+hjhhhjMubh)}(h**HOST2GUC_CONTROL_CTB**h]jb)}(hjh]hHOST2GUC_CONTROL_CTB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]host2guc_control_ctbah$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK2hjhhj}jjsj}jjsubh)}(hMThis H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_.h](h@This H2G action allows Vf Host to enable or disable H2G and G2H }(hjhhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:jCuh1j 5hjj:Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK>hjhhubh)}(h1This message must be sent as `MMIO HXG Message`_.h](hThis message must be sent as }(hjhhhNhNubj!5)}(h`MMIO HXG Message`_h]hMMIO HXG Message}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameMMIO HXG Messagej:juh1j 5hjj:Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhK@hjhhubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | | +-------+--------------------------------------------------------------+ | | 27:16 | DATA0 = MBZ | | +-------+--------------------------------------------------------------+ | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509 | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **CONTROL** - control `CTB based communication`_ | | | | | | | | - _`GUC_CTB_CONTROL_DISABLE` = 0 | | | | - _`GUC_CTB_CONTROL_ENABLE` = 1 | +---+-------+--------------------------------------------------------------+ +---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ | | +-------+--------------------------------------------------------------+ | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | | +-------+--------------------------------------------------------------+ | | 27:0 | DATA0 = MBZ | +---+-------+--------------------------------------------------------------+ h](j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hj7ubj-)}(hhh]h)}(hBitsh]hBits}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKChjCubah}(h]h ]h"]h$]h&]uh1j,hj7ubj-)}(hhh]h)}(h Descriptionh]h Description}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThKChj[ubah}(h]h ]h"]h$]h&]uh1j,hj7ubeh}(h]h ]h"]h$]h&]uh1j'hj4ubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKEhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjubj-)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKEhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_HOST_h](h ORIGIN = }(hjhhhNhNubj!5)}(hGUC_HXG_ORIGIN_HOST_h]hGUC_HXG_ORIGIN_HOST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_HOSTj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKEhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj~ubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKGhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hTYPE = GUC_HXG_TYPE_REQUEST_h](hTYPE = }(hjhhhNhNubj!5)}(hGUC_HXG_TYPE_REQUEST_h]hGUC_HXG_TYPE_REQUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_REQUESTj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKGhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj~ubj()}(hhh](j-)}(hhh]h)}(h27:16h]h27:16}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKIhj+ubah}(h]h ]h"]h$]h&]uh1j,hj(ubj-)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hKIhjCubah}(h]h ]h"]h$]h&]uh1j,hj(ubeh}(h]h ]h"]h$]h&]uh1j'hj~ubj()}(hhh](j-)}(hhh]h)}(h15:0h]h15:0}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKKhjcubah}(h]h ]h"]h$]h&]uh1j,hj`ubj-)}(hhh]h)}(h4ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509h](h ACTION = }(hj~hhhNhNubj)}(h"_`GUC_ACTION_HOST2GUC_CONTROL_CTB`h]hGUC_ACTION_HOST2GUC_CONTROL_CTB}(hjhhhNhNubah}(h]guc-action-host2guc-control-ctbah ]h"]guc_action_host2guc_control_ctbah$]h&]uh1jhj~ubh = 0x4509}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjthKKhj{ubah}(h]h ]h"]h$]h&]uh1j,hj`ubeh}(h]h ]h"]h$]h&]uh1j'hj~ubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKMhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKMhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh](h)}(h0**CONTROL** - control `CTB based communication`_h](jb)}(h **CONTROL**h]hCONTROL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - control }(hjhhhNhNubj!5)}(h`CTB based communication`_h]hCTB based communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameCTB based communicationj:juh1j 5hjj:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKMhjubj)}(h@- _`GUC_CTB_CONTROL_DISABLE` = 0 - _`GUC_CTB_CONTROL_ENABLE` = 1h]j:)}(hhh](j:)}(h_`GUC_CTB_CONTROL_DISABLE` = 0h]h)}(hjh](j)}(h_`GUC_CTB_CONTROL_DISABLE`h]hGUC_CTB_CONTROL_DISABLE}(hjhhhNhNubah}(h]guc-ctb-control-disableah ]h"]guc_ctb_control_disableah$]h&]uh1jhjubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKOhjubah}(h]h ]h"]h$]h&]uh1j:hjubj:)}(h_`GUC_CTB_CONTROL_ENABLE` = 1h]h)}(hj=h](j)}(h_`GUC_CTB_CONTROL_ENABLE`h]hGUC_CTB_CONTROL_ENABLE}(hjBhhhNhNubah}(h]guc-ctb-control-enableah ]h"]guc_ctb_control_enableah$]h&]uh1jhj?ubh = 1}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKPhj;ubah}(h]h ]h"]h$]h&]uh1j:hjubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hj4hKOhj ubah}(h]h ]h"]h$]h&]uh1jhj4hKOhjubeh}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hj~ubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhjubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKThjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKThjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j"hjubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKVhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjubj-)}(hhh]h)}(h31h]h31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKVhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(hORIGIN = GUC_HXG_ORIGIN_GUC_h](h ORIGIN = }(hj4hhhNhNubj!5)}(hGUC_HXG_ORIGIN_GUC_h]hGUC_HXG_ORIGIN_GUC}(hj<hhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_ORIGIN_GUCj:juh1j 5hj4j:Kubeh}(h]h ]h"]h$]h&]uh1hhjhKVhj1ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h30:28h]h30:28}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKXhjaubah}(h]h ]h"]h$]h&]uh1j,hj^ubj-)}(hhh]h)}(h%TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_h](hTYPE = }(hj|hhhNhNubj!5)}(hGUC_HXG_TYPE_RESPONSE_SUCCESS_h]hGUC_HXG_TYPE_RESPONSE_SUCCESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGUC_HXG_TYPE_RESPONSE_SUCCESSj:juh1j 5hj|j:Kubeh}(h]h ]h"]h$]h&]uh1hhjrhKXhjyubah}(h]h ]h"]h$]h&]uh1j,hj^ubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h27:0h]h27:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKZhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h DATA0 = MBZh]h DATA0 = MBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKZhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/gpu/i915:550: ./drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.hhKBhjhhubj)}(h .. _GuC KLV:h]h}(h]h ]h"]h$]h&]j:guc-klvuh1jhKhjhhhNjKubh)}(h **GuC KLV**h]jb)}(hjh]hGuC KLV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]jah ]h"]guc klvah$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjhhj}jjsj}jjsjKubj)}(hX+---+-------+--------------------------------------------------------------+ | | Bits | Description | +===+=======+==============================================================+ | 0 | 31:16 | **KEY** - KLV key identifier | | | | - `GuC Self Config KLVs`_ | | | | | | +-------+--------------------------------------------------------------+ | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) | +---+-------+--------------------------------------------------------------+ | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) | +---+-------+ | |...| | | +---+-------+ | | n | 31:0 | | +---+-------+--------------------------------------------------------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj%ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj%ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jhj%ubj#)}(hhh]j()}(hhh](j-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjIubj-)}(hhh]h)}(hBitsh]hBits}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK hjUubah}(h]h ]h"]h$]h&]uh1j,hjIubj-)}(hhh]h)}(h Descriptionh]h Description}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhK hjmubah}(h]h ]h"]h$]h&]uh1j,hjIubeh}(h]h ]h"]h$]h&]uh1j'hjFubah}(h]h ]h"]h$]h&]uh1j"hj%ubjs)}(hhh](j()}(hhh](j-)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjubj-)}(hhh]h)}(h31:16h]h31:16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]jx)}(hhh]j})}(h7**KEY** - KLV key identifier - `GuC Self Config KLVs`_ h](j)}(h**KEY** - KLV key identifierh](jb)}(h**KEY**h]hKEY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh - KLV key identifier}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubj)}(hhh]j:)}(hhh]j:)}(h`GuC Self Config KLVs`_ h]h)}(h`GuC Self Config KLVs`_h]j!5)}(hjh]hGuC Self Config KLVs}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGuC Self Config KLVsj:juh1j 5hjj:Kubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&]j[;j\;uh1j:hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhKhjubah}(h]h ]h"]h$]h&]uh1jwhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h15:0h]h15:0}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhj<ubah}(h]h ]h"]h$]h&]uh1j,hj9ubj-)}(hhh]h)}(h+**LEN** - length of VALUE (in 32bit dwords)h](jb)}(h**LEN**h]hLEN}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjWubh$ - length of VALUE (in 32bit dwords)}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjMhKhjTubah}(h]h ]h"]h$]h&]uh1j,hj9ubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h;**VALUE** - actual value of the KLV (format depends on KEY)h](jb)}(h **VALUE**h]hVALUE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjubh2 - actual value of the KLV (format depends on KEY)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]morerowsKuh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubj()}(hhh](j-)}(hhh]h)}(hjGh]hn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhj ubah}(h]h ]h"]h$]h&]uh1j,hjubj-)}(hhh]h)}(h31:0h]h31:0}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhj ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jrhj%ubeh}(h]h ]h"]h$]h&]colsKuh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK hjhhubj)}(h.. _GuC Self Config KLVs:h]h}(h]h ]h"]h$]h&]j:juh1jhKhjhhhNjKubh)}(h**GuC Self Config KLVs**h]jb)}(hjch]hGuC Self Config KLVs}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jahjaubah}(h]jah ]h"]guc self config klvsah$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjhhj}jvjWsj}jjWsjKubh)}(h:`GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.h](j!5)}(h `GuC KLV`_h]hGuC KLV}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameGuC KLVj:juh1j 5hj|j:Kubh keys available for use with }(hj|hhhNhNubj!5)}(hHOST2GUC_SELF_CFG_h]hHOST2GUC_SELF_CFG}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameHOST2GUC_SELF_CFGj:jLuh1j 5hj|j:Kubh.}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK%hjhhubjx)}(hhh](j})}(h_`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902 Refers to 64 bit Global Gfx address of H2G `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode. h](j)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR`h](j)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR`h]hGUC_KLV_SELF_CFG_H2G_CTB_ADDR}(hjhhhNhNubah}(h]guc-klv-self-cfg-h2g-ctb-addrah ]h"]guc_klv_self_cfg_h2g_ctb_addrah$]h&]uh1jhjubhh}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK)hjubh classifier)}(h0x0902h]h0x0902}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhjubj)}(hhh]h)}(hRefers to 64 bit Global Gfx address of H2G `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of H2G }(hjhhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:jCuh1j 5hjj:KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK)hjubj})}(h_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR` : 0x0903 Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode. h](j)}(h+_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR`h](j)}(h+_`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR`h]h(GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR}(hjhhhNhNubah}(h](guc-klv-self-cfg-h2g-ctb-descriptor-addrah ]h"](guc_klv_self_cfg_h2g_ctb_descriptor_addrah$]h&]uh1jhjubhh}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK-hjubj)}(h0x0903h]h0x0903}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhj7ubj)}(hhh]h)}(hRefers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of H2G }(hjIhhhNhNubj!5)}(h`CTB Descriptor`_h]hCTB Descriptor}(hjQhhhNhNubah}(h]h ]h"]h$]h&]nameCTB Descriptorj:juh1j 5hjIj:KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK,hjFubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hj7hK-hjubj})}(hs_`GUC_KLV_SELF_CFG_H2G_CTB_SIZE` : 0x0904 Refers to size of H2G `CT Buffer`_ in bytes. Should be a multiple of 4K. h](j)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE`h](j)}(h _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE`h]hGUC_KLV_SELF_CFG_H2G_CTB_SIZE}(hjhhhNhNubah}(h]guc-klv-self-cfg-h2g-ctb-sizeah ]h"]guc_klv_self_cfg_h2g_ctb_sizeah$]h&]uh1jhj|ubhh}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK1hjxubj)}(h0x0904h]h0x0904}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxhjubj)}(hhh]h)}(hHRefers to size of H2G `CT Buffer`_ in bytes. Should be a multiple of 4K.h](hRefers to size of H2G }(hjhhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:jCuh1j 5hjj:Kubh& in bytes. Should be a multiple of 4K.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK0hjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1j|hjhK1hjubj})}(h_`GUC_KLV_SELF_CFG_G2H_CTB_ADDR` : 0x0905 Refers to 64 bit Global Gfx address of G2H `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode. h](j)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR`h](j)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR`h]hGUC_KLV_SELF_CFG_G2H_CTB_ADDR}(hjhhhNhNubah}(h]guc-klv-self-cfg-g2h-ctb-addrah ]h"]guc_klv_self_cfg_g2h_ctb_addrah$]h&]uh1jhjubhh}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK5hjubj)}(h0x0905h]h0x0905}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhjubj)}(hhh]h)}(hRefers to 64 bit Global Gfx address of G2H `CT Buffer`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of G2H }(hj hhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:jCuh1j 5hj j:KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK4hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhK5hjubj})}(h_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR` : 0x0906 Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode. h](j)}(h+_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR`h](j)}(h+_`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR`h]h(GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR}(hjDhhhNhNubah}(h](guc-klv-self-cfg-g2h-ctb-descriptor-addrah ]h"](guc_klv_self_cfg_g2h_ctb_descriptor_addrah$]h&]uh1jhj@ubhh}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK9hj<ubj)}(h0x0906h]h0x0906}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<hj]ubj)}(hhh]h)}(hRefers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. Should be above WOPCM address but below APIC base address for native mode.h](h+Refers to 64 bit Global Gfx address of G2H }(hjohhhNhNubj!5)}(h`CTB Descriptor`_h]hCTB Descriptor}(hjwhhhNhNubah}(h]h ]h"]h$]h&]nameCTB Descriptorj:juh1j 5hjoj:KubhL. Should be above WOPCM address but below APIC base address for native mode.}(hjohhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK8hjlubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1j|hj]hK9hjubj})}(ht_`GUC_KLV_SELF_CFG_G2H_CTB_SIZE` : 0x0907 Refers to size of G2H `CT Buffer`_ in bytes. Should be a multiple of 4K. h](j)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE`h](j)}(h _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE`h]hGUC_KLV_SELF_CFG_G2H_CTB_SIZE}(hjhhhNhNubah}(h]guc-klv-self-cfg-g2h-ctb-sizeah ]h"]guc_klv_self_cfg_g2h_ctb_sizeah$]h&]uh1jhjubhh}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhK>hjubj)}(h0x0907h]h0x0907}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhjubj)}(hhh]h)}(hHRefers to size of G2H `CT Buffer`_ in bytes. Should be a multiple of 4K.h](hRefers to size of G2H }(hjhhhNhNubj!5)}(h `CT Buffer`_h]h CT Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name CT Bufferj:jCuh1j 5hjj:Kubh& in bytes. Should be a multiple of 4K.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.hhKhjubeh}(h]h ]h"]h$]h&]uh1jwhjhhhNhNubeh}(h]guc-abiah ]h"]guc abiah$]h&]uh1hhj~hhhhhM!ubeh}(h]gucah ]h"]gucah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hHuCh]hHuC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM*ubh)}(hThe HuC is a dedicated microcontroller for usage in media HEVC (High Efficiency Video Coding) operations. Userspace can directly use the firmware capabilities by adding HuC specific commands to batch buffers.h]hThe HuC is a dedicated microcontroller for usage in media HEVC (High Efficiency Video Coding) operations. Userspace can directly use the firmware capabilities by adding HuC specific commands to batch buffers.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:555: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chKhjhhubh)}(hThe kernel driver is only responsible for loading the HuC firmware and triggering its security authentication. This is done differently depending on the platform:h]hThe kernel driver is only responsible for loading the HuC firmware and triggering its security authentication. This is done differently depending on the platform:}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:555: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chKhjhhubj:)}(hhh](j:)}(hholder platforms (from Gen9 to most Gen12s): the load is performed via DMA and the authentication via GuCh]h)}(hholder platforms (from Gen9 to most Gen12s): the load is performed via DMA and the authentication via GuCh]hholder platforms (from Gen9 to most Gen12s): the load is performed via DMA and the authentication via GuC}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:555: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chKhjHubah}(h]h ]h"]h$]h&]uh1j:hjEubj:)}(h8DG2: load and authentication are both performed via GSC.h]h)}(hjch]h8DG2: load and authentication are both performed via GSC.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:555: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chKhjaubah}(h]h ]h"]h$]h&]uh1j:hjEubj:)}(hMTL and newer platforms: the load is performed via DMA (same as with not-DG2 older platforms), while the authentication is done in 2-steps, a first auth for clear-media workloads via GuC and a second one for all workloads via GSC. h]h)}(hMTL and newer platforms: the load is performed via DMA (same as with not-DG2 older platforms), while the authentication is done in 2-steps, a first auth for clear-media workloads via GuC and a second one for all workloads via GSC.h]hMTL and newer platforms: the load is performed via DMA (same as with not-DG2 older platforms), while the authentication is done in 2-steps, a first auth for clear-media workloads via GuC and a second one for all workloads via GSC.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:555: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chK hjyubah}(h]h ]h"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hjZhKhjhhubh)}(hXOn platforms where the GuC does the authentication, to correctly do so the HuC binary must be loaded before the GuC one. Loading the HuC is optional; however, not using the HuC might negatively impact power usage and/or performance of media workloads, depending on the use-cases. HuC must be reloaded on events that cause the WOPCM to lose its contents (S3/S4, FLR); on older platforms the HuC must also be reloaded on GuC/GT reset, while on newer ones it will survive that.h]hXOn platforms where the GuC does the authentication, to correctly do so the HuC binary must be loaded before the GuC one. Loading the HuC is optional; however, not using the HuC might negatively impact power usage and/or performance of media workloads, depending on the use-cases. HuC must be reloaded on events that cause the WOPCM to lose its contents (S3/S4, FLR); on older platforms the HuC must also be reloaded on GuC/GT reset, while on newer ones it will survive that.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:555: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chK%hjhhubh)}(hVSee https://github.com/intel/media-driver for the latest details on HuC functionality.h](hSee }(hjhhhNhNubj!5)}(h%https://github.com/intel/media-driverh]h%https://github.com/intel/media-driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1j 5hjubh- for the latest details on HuC functionality.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:555: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chK.hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"intel_huc_auth (C function)c.intel_huc_authhNtauh1jhjhhhNhNubj')}(hhh](j,)}(hSint intel_huc_auth (struct intel_huc *huc, enum intel_huc_authentication_type type)h]j2)}(hRint intel_huc_auth(struct intel_huc *huc, enum intel_huc_authentication_type type)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:557: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chMubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMubjz)}(hintel_huc_authh]j;)}(hintel_huc_authh]hintel_huc_auth}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMubj)}(h@(struct intel_huc *huc, enum intel_huc_authentication_type type)h](j)}(hstruct intel_huc *huch](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj, hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(h intel_huch]h intel_huc}(hj= hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj: ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj? modnameN classnameNjXj[)}j^]ja)}jTj sbc.intel_huc_authasbuh1hhj ubji)}(h h]h }(hj] hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj)}(hjh]h*}(hjk hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj;)}(hhuch]hhuc}(hjx hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubj)}(h'enum intel_huc_authentication_type typeh](j)}(hjh]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubh)}(hhh]j;)}(hintel_huc_authentication_typeh]hintel_huc_authentication_type}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj modnameN classnameNjXj[)}j^]jY c.intel_huc_authasbuh1hhj ubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj ubj;)}(htypeh]htype}(hj hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMhjhhubj1)}(hhh]h)}(hAuthenticate HuC uCodeh]hAuthenticate HuC uCode}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:557: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chMhj!hhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj!jSj!jTjUjVuh1j&hhhjhNhNubjX)}(hX**Parameters** ``struct intel_huc *huc`` intel_huc structure ``enum intel_huc_authentication_type type`` authentication type (via GuC or via GSC) **Description** Called after HuC and GuC firmware loading during intel_uc_init_hw(). This function invokes the GuC action to authenticate the HuC firmware, passing the offset of the RSA signature to intel_guc_auth_huc(). It then waits for up to 50ms for firmware verification ACK.h](h)}(h**Parameters**h]jb)}(hj'!h]h Parameters}(hj)!hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj%!ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:557: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chM hj!!ubjx)}(hhh](j})}(h.``struct intel_huc *huc`` intel_huc structure h](j)}(h``struct intel_huc *huc``h]j)}(hjF!h]hstruct intel_huc *huc}(hjH!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD!ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:557: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chMhj@!ubj)}(hhh]h)}(hintel_huc structureh]hintel_huc structure}(hj_!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[!hMhj\!ubah}(h]h ]h"]h$]h&]uh1jhj@!ubeh}(h]h ]h"]h$]h&]uh1j|hj[!hMhj=!ubj})}(hU``enum intel_huc_authentication_type type`` authentication type (via GuC or via GSC) h](j)}(h+``enum intel_huc_authentication_type type``h]j)}(hj!h]h'enum intel_huc_authentication_type type}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}!ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:557: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chMhjy!ubj)}(hhh]h)}(h(authentication type (via GuC or via GSC)h]h(authentication type (via GuC or via GSC)}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMhj!ubah}(h]h ]h"]h$]h&]uh1jhjy!ubeh}(h]h ]h"]h$]h&]uh1j|hj!hMhj=!ubeh}(h]h ]h"]h$]h&]uh1jwhj!!ubh)}(h**Description**h]jb)}(hj!h]h Description}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj!ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:557: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chM hj!!ubh)}(hDCalled after HuC and GuC firmware loading during intel_uc_init_hw().h]hDCalled after HuC and GuC firmware loading during intel_uc_init_hw().}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:557: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chM hj!!ubh)}(hThis function invokes the GuC action to authenticate the HuC firmware, passing the offset of the RSA signature to intel_guc_auth_huc(). It then waits for up to 50ms for firmware verification ACK.h]hThis function invokes the GuC action to authenticate the HuC firmware, passing the offset of the RSA signature to intel_guc_auth_huc(). It then waits for up to 50ms for firmware verification ACK.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:557: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chM hj!!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjhhhNhNubh)}(hhh](h)}(hHuC Memory Managementh]hHuC Memory Management}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhhhM1ubh)}(hX?Similarly to the GuC, the HuC can't do any memory allocations on its own, with the difference being that the allocations for HuC usage are handled by the userspace driver instead of the kernel one. The HuC accesses the memory via the PPGTT belonging to the context loaded on the VCS executing the HuC-specific commands.h]hXASimilarly to the GuC, the HuC can’t do any memory allocations on its own, with the difference being that the allocations for HuC usage are handled by the userspace driver instead of the kernel one. The HuC accesses the memory via the PPGTT belonging to the context loaded on the VCS executing the HuC-specific commands.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:563: ./drivers/gpu/drm/i915/gt/uc/intel_huc.chK5hj!hhubeh}(h]huc-memory-managementah ]h"]huc memory managementah$]h&]uh1hhjhhhhhM1ubh)}(hhh](h)}(hHuC Firmware Layouth]hHuC Firmware Layout}(hj "hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhM7ubh)}(hHThe HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_h](h2The HuC FW layout is the same as the GuC one, see }(hj."hhhNhNubj!5)}(h`GuC Firmware Layout`_h]hGuC Firmware Layout}(hj6"hhhNhNubah}(h]h ]h"]h$]h&]nameGuC Firmware Layoutj:j>uh1j 5hj."j:Kubeh}(h]h ]h"]h$]h&]uh1hhhhM8hj"hhubeh}(h]huc-firmware-layoutah ]h"]huc firmware layoutah$]h&]uh1hhjhhhhhM7ubeh}(h]hucah ]h"]hucah$]h&]uh1hhjhhhhhM*ubh)}(hhh](h)}(hDMCh]hDMC}(hj_"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\"hhhhhM;ubh)}(hSee `DMC Firmware Support`_h](hSee }(hjm"hhhNhNubj!5)}(h`DMC Firmware Support`_h]hDMC Firmware Support}(hju"hhhNhNubah}(h]h ]h"]h$]h&]nameDMC Firmware Supportj:juh1j 5hjm"j:Kubeh}(h]h ]h"]h$]h&]uh1hhhhM<hj\"hhubeh}(h]dmcah ]h"]dmcah$]h&]uh1hhjhhhhhM;ubeh}(h]microcontrollersah ]h"]microcontrollersah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hTracingh]hTracing}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhM?ubh)}(hZThis sections covers all things related to the tracepoints implemented in the i915 driver.h]hZThis sections covers all things related to the tracepoints implemented in the i915 driver.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhj"hhubh)}(hhh](h)}(h(i915_ppgtt_create and i915_ppgtt_releaseh]h(i915_ppgtt_create and i915_ppgtt_release}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhMEubh)}(hXWith full ppgtt enabled each process using drm will allocate at least one translation table. With these traces it is possible to keep track of the allocation and of the lifetime of the tables; this can be used during testing/debug to verify that we are not leaking ppgtts. These traces identify the ppgtt through the vm pointer, which is also printed by the i915_vma_bind and i915_vma_unbind tracepoints.h]hXWith full ppgtt enabled each process using drm will allocate at least one translation table. With these traces it is possible to keep track of the allocation and of the lifetime of the tables; this can be used during testing/debug to verify that we are not leaking ppgtts. These traces identify the ppgtt through the vm pointer, which is also printed by the i915_vma_bind and i915_vma_unbind tracepoints.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/i915:583: ./drivers/gpu/drm/i915/i915_trace.hhMhj"hhubeh}(h](i915-ppgtt-create-and-i915-ppgtt-releaseah ]h"](i915_ppgtt_create and i915_ppgtt_releaseah$]h&]uh1hhj"hhhhhMEubh)}(hhh](h)}(h)i915_context_create and i915_context_freeh]h)i915_context_create and i915_context_free}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhMKubh)}(hThese tracepoints are used to track creation and deletion of contexts. If full ppgtt is enabled, they also print the address of the vm assigned to the context.h]hThese tracepoints are used to track creation and deletion of contexts. If full ppgtt is enabled, they also print the address of the vm assigned to the context.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/i915:589: ./drivers/gpu/drm/i915/i915_trace.hhMhj"hhubeh}(h])i915-context-create-and-i915-context-freeah ]h"])i915_context_create and i915_context_freeah$]h&]uh1hhj"hhhhhMKubeh}(h]tracingah ]h"]tracingah$]h&]uh1hhhhhhhhM?ubh)}(hhh](h)}(hPerfh]hPerf}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMQubh)}(hhh](h)}(hOverviewh]hOverview}(hj&#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj##hhhhhMTubh)}(hGen graphics supports a large number of performance counters that can help driver and application developers understand and optimize their use of the GPU.h]hGen graphics supports a large number of performance counters that can help driver and application developers understand and optimize their use of the GPU.}(hj4#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:597: ./drivers/gpu/drm/i915/i915_perf.chKhj##hhubh)}(hThis i915 perf interface enables userspace to configure and open a file descriptor representing a stream of GPU metrics which can then be read() as a stream of sample records.h]hThis i915 perf interface enables userspace to configure and open a file descriptor representing a stream of GPU metrics which can then be read() as a stream of sample records.}(hjC#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:597: ./drivers/gpu/drm/i915/i915_perf.chK!hj##hhubh)}(hThe interface is particularly suited to exposing buffered metrics that are captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.h]hThe interface is particularly suited to exposing buffered metrics that are captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.}(hjR#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:597: ./drivers/gpu/drm/i915/i915_perf.chK%hj##hhubh)}(hX7Streams representing a single context are accessible to applications with a corresponding drm file descriptor, such that OpenGL can use the interface without special privileges. Access to system-wide metrics requires root privileges by default, unless changed via the dev.i915.perf_event_paranoid sysctl option.h]hX7Streams representing a single context are accessible to applications with a corresponding drm file descriptor, such that OpenGL can use the interface without special privileges. Access to system-wide metrics requires root privileges by default, unless changed via the dev.i915.perf_event_paranoid sysctl option.}(hja#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:597: ./drivers/gpu/drm/i915/i915_perf.chK(hj##hhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhj#hhhhhMTubh)}(hhh](h)}(hComparison with Core Perfh]hComparison with Core Perf}(hj{#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx#hhhhhMYubh)}(hfThe interface was initially inspired by the core Perf infrastructure but some notable differences are:h]hfThe interface was initially inspired by the core Perf infrastructure but some notable differences are:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chK3hjx#hhubh)}(hXi915 perf file descriptors represent a "stream" instead of an "event"; where a perf event primarily corresponds to a single 64bit value, while a stream might sample sets of tightly-coupled counters, depending on the configuration. For example the Gen OA unit isn't designed to support orthogonal configurations of individual counters; it's configured for a set of related counters. Samples for an i915 perf stream capturing OA metrics will include a set of counter values packed in a compact HW specific format. The OA unit supports a number of different packing formats which can be selected by the user opening the stream. Perf has support for grouping events, but each event in the group is configured, validated and authenticated individually with separate system calls.h]hXi915 perf file descriptors represent a “stream” instead of an “event”; where a perf event primarily corresponds to a single 64bit value, while a stream might sample sets of tightly-coupled counters, depending on the configuration. For example the Gen OA unit isn’t designed to support orthogonal configurations of individual counters; it’s configured for a set of related counters. Samples for an i915 perf stream capturing OA metrics will include a set of counter values packed in a compact HW specific format. The OA unit supports a number of different packing formats which can be selected by the user opening the stream. Perf has support for grouping events, but each event in the group is configured, validated and authenticated individually with separate system calls.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chK6hjx#hhubh)}(hi915 perf stream configurations are provided as an array of u64 (key,value) pairs, instead of a fixed struct with multiple miscellaneous config members, interleaved with event-type specific members.h]hi915 perf stream configurations are provided as an array of u64 (key,value) pairs, instead of a fixed struct with multiple miscellaneous config members, interleaved with event-type specific members.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKBhjx#hhubh)}(hXLi915 perf doesn't support exposing metrics via an mmap'd circular buffer. The supported metrics are being written to memory by the GPU unsynchronized with the CPU, using HW specific packing formats for counter sets. Sometimes the constraints on HW configuration require reports to be filtered before it would be acceptable to expose them to unprivileged applications - to hide the metrics of other processes/contexts. For these use cases a read() based interface is a good fit, and provides an opportunity to filter data as it gets copied from the GPU mapped buffers to userspace buffers.h]hXPi915 perf doesn’t support exposing metrics via an mmap’d circular buffer. The supported metrics are being written to memory by the GPU unsynchronized with the CPU, using HW specific packing formats for counter sets. Sometimes the constraints on HW configuration require reports to be filtered before it would be acceptable to expose them to unprivileged applications - to hide the metrics of other processes/contexts. For these use cases a read() based interface is a good fit, and provides an opportunity to filter data as it gets copied from the GPU mapped buffers to userspace buffers.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKFhjx#hhubh)}(hhh](h)}(h2Issues hit with first prototype based on Core Perfh]h2Issues hit with first prototype based on Core Perf}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hNhNubh)}(hXThe first prototype of this driver was based on the core perf infrastructure, and while we did make that mostly work, with some changes to perf, we found we were breaking or working around too many assumptions baked into perf's currently cpu centric design.h]hXThe first prototype of this driver was based on the core perf infrastructure, and while we did make that mostly work, with some changes to perf, we found we were breaking or working around too many assumptions baked into perf’s currently cpu centric design.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKShj#ubh)}(hIn the end we didn't see a clear benefit to making perf's implementation and interface more complex by changing design assumptions while we knew we still wouldn't be able to use any existing perf based userspace tools.h]hIn the end we didn’t see a clear benefit to making perf’s implementation and interface more complex by changing design assumptions while we knew we still wouldn’t be able to use any existing perf based userspace tools.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKXhj#ubh)}(hXAlso considering the Gen specific nature of the Observability hardware and how userspace will sometimes need to combine i915 perf OA metrics with side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're expecting the interface to be used by a platform specific userspace such as OpenGL or tools. This is to say; we aren't inherently missing out on having a standard vendor/architecture agnostic interface by not using perf.h]hXAlso considering the Gen specific nature of the Observability hardware and how userspace will sometimes need to combine i915 perf OA metrics with side-band OA data captured via MI_REPORT_PERF_COUNT commands; we’re expecting the interface to be used by a platform specific userspace such as OpenGL or tools. This is to say; we aren’t inherently missing out on having a standard vendor/architecture agnostic interface by not using perf.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chK\hj#ubh)}(hFor posterity, in case we might re-visit trying to adapt core perf to be better suited to exposing i915 metrics these were the main pain points we hit:h]hFor posterity, in case we might re-visit trying to adapt core perf to be better suited to exposing i915 metrics these were the main pain points we hit:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKdhj#ubj:)}(hhh](j:)}(hXQThe perf based OA PMU driver broke some significant design assumptions: Existing perf pmus are used for profiling work on a cpu and we were introducing the idea of _IS_DEVICE pmus with different security implications, the need to fake cpu-related data (such as user/kernel registers) to fit with perf's current design, and adding _DEVICE records as a way to forward device-specific status records. The OA unit writes reports of counters into a circular buffer, without involvement from the CPU, making our PMU driver the first of a kind. Given the way we were periodically forward data from the GPU-mapped, OA buffer to perf's buffer, those bursts of sample writes looked to perf like we were sampling too fast and so we had to subvert its throttling checks. Perf supports groups of counters and allows those to be read via transactions internally but transactions currently seem designed to be explicitly initiated from the cpu (say in response to a userspace read()) and while we could pull a report out of the OA buffer we can't trigger a report from the cpu on demand. Related to being report based; the OA counters are configured in HW as a set while perf generally expects counter configurations to be orthogonal. Although counters can be associated with a group leader as they are opened, there's no clear precedent for being able to provide group-wide configuration attributes (for example we want to let userspace choose the OA unit report format used to capture all counters in a set, or specify a GPU context to filter metrics on). We avoided using perf's grouping feature and forwarded OA reports to userspace via perf's 'raw' sample field. This suited our userspace well considering how coupled the counters are when dealing with normalizing. It would be inconvenient to split counters up into separate events, only to require userspace to recombine them. For Mesa it's also convenient to be forwarded raw, periodic reports for combining with the side-band raw reports it captures using MI_REPORT_PERF_COUNT commands. - As a side note on perf's grouping feature; there was also some concern that using PERF_FORMAT_GROUP as a way to pack together counter values would quite drastically inflate our sample sizes, which would likely lower the effective sampling resolutions we could use when the available memory bandwidth is limited. With the OA unit's report formats, counters are packed together as 32 or 40bit values, with the largest report size being 256 bytes. PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a documented ordering to the values, implying PERF_FORMAT_ID must also be used to add a 64bit ID before each value; giving 16 bytes per counter. Related to counter orthogonality; we can't time share the OA unit, while event scheduling is a central design idea within perf for allowing userspace to open + enable more events than can be configured in HW at any one time. The OA unit is not designed to allow re-configuration while in use. We can't reconfigure the OA unit without losing internal OA unit state which we can't access explicitly to save and restore. Reconfiguring the OA unit is also relatively slow, involving ~100 register writes. From userspace Mesa also depends on a stable OA configuration when emitting MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be disabled while there are outstanding MI_RPC commands lest we hang the command streamer. The contents of sample records aren't extensible by device drivers (i.e. the sample_type bits). As an example; Sourab Gupta had been looking to attach GPU timestamps to our OA samples. We were shoehorning OA reports into sample records by using the 'raw' field, but it's tricky to pack more than one thing into this field because events/core.c currently only lets a pmu give a single raw data pointer plus len which will be copied into the ring buffer. To include more than the OA report we'd have to copy the report into an intermediate larger buffer. I'd been considering allowing a vector of data+len values to be specified for copying the raw data, but it felt like a kludge to being using the raw field for this purpose. h](h)}(hGThe perf based OA PMU driver broke some significant design assumptions:h]hGThe perf based OA PMU driver broke some significant design assumptions:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKhhj$ubh)}(hXEExisting perf pmus are used for profiling work on a cpu and we were introducing the idea of _IS_DEVICE pmus with different security implications, the need to fake cpu-related data (such as user/kernel registers) to fit with perf's current design, and adding _DEVICE records as a way to forward device-specific status records.h]hXGExisting perf pmus are used for profiling work on a cpu and we were introducing the idea of _IS_DEVICE pmus with different security implications, the need to fake cpu-related data (such as user/kernel registers) to fit with perf’s current design, and adding _DEVICE records as a way to forward device-specific status records.}(hj($hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKjhj$ubh)}(hThe OA unit writes reports of counters into a circular buffer, without involvement from the CPU, making our PMU driver the first of a kind.h]hThe OA unit writes reports of counters into a circular buffer, without involvement from the CPU, making our PMU driver the first of a kind.}(hj7$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKphj$ubh)}(hGiven the way we were periodically forward data from the GPU-mapped, OA buffer to perf's buffer, those bursts of sample writes looked to perf like we were sampling too fast and so we had to subvert its throttling checks.h]hGiven the way we were periodically forward data from the GPU-mapped, OA buffer to perf’s buffer, those bursts of sample writes looked to perf like we were sampling too fast and so we had to subvert its throttling checks.}(hjF$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKshj$ubh)}(hX9Perf supports groups of counters and allows those to be read via transactions internally but transactions currently seem designed to be explicitly initiated from the cpu (say in response to a userspace read()) and while we could pull a report out of the OA buffer we can't trigger a report from the cpu on demand.h]hX;Perf supports groups of counters and allows those to be read via transactions internally but transactions currently seem designed to be explicitly initiated from the cpu (say in response to a userspace read()) and while we could pull a report out of the OA buffer we can’t trigger a report from the cpu on demand.}(hjU$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKwhj$ubh)}(hXRelated to being report based; the OA counters are configured in HW as a set while perf generally expects counter configurations to be orthogonal. Although counters can be associated with a group leader as they are opened, there's no clear precedent for being able to provide group-wide configuration attributes (for example we want to let userspace choose the OA unit report format used to capture all counters in a set, or specify a GPU context to filter metrics on). We avoided using perf's grouping feature and forwarded OA reports to userspace via perf's 'raw' sample field. This suited our userspace well considering how coupled the counters are when dealing with normalizing. It would be inconvenient to split counters up into separate events, only to require userspace to recombine them. For Mesa it's also convenient to be forwarded raw, periodic reports for combining with the side-band raw reports it captures using MI_REPORT_PERF_COUNT commands.h]hXRelated to being report based; the OA counters are configured in HW as a set while perf generally expects counter configurations to be orthogonal. Although counters can be associated with a group leader as they are opened, there’s no clear precedent for being able to provide group-wide configuration attributes (for example we want to let userspace choose the OA unit report format used to capture all counters in a set, or specify a GPU context to filter metrics on). We avoided using perf’s grouping feature and forwarded OA reports to userspace via perf’s ‘raw’ sample field. This suited our userspace well considering how coupled the counters are when dealing with normalizing. It would be inconvenient to split counters up into separate events, only to require userspace to recombine them. For Mesa it’s also convenient to be forwarded raw, periodic reports for combining with the side-band raw reports it captures using MI_REPORT_PERF_COUNT commands.}(hjd$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chK}hj$ubj:)}(hhh]j:)}(hXAs a side note on perf's grouping feature; there was also some concern that using PERF_FORMAT_GROUP as a way to pack together counter values would quite drastically inflate our sample sizes, which would likely lower the effective sampling resolutions we could use when the available memory bandwidth is limited. With the OA unit's report formats, counters are packed together as 32 or 40bit values, with the largest report size being 256 bytes. PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a documented ordering to the values, implying PERF_FORMAT_ID must also be used to add a 64bit ID before each value; giving 16 bytes per counter. h](h)}(hX7As a side note on perf's grouping feature; there was also some concern that using PERF_FORMAT_GROUP as a way to pack together counter values would quite drastically inflate our sample sizes, which would likely lower the effective sampling resolutions we could use when the available memory bandwidth is limited.h]hX9As a side note on perf’s grouping feature; there was also some concern that using PERF_FORMAT_GROUP as a way to pack together counter values would quite drastically inflate our sample sizes, which would likely lower the effective sampling resolutions we could use when the available memory bandwidth is limited.}(hjz$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKhjv$ubh)}(hWith the OA unit's report formats, counters are packed together as 32 or 40bit values, with the largest report size being 256 bytes.h]hWith the OA unit’s report formats, counters are packed together as 32 or 40bit values, with the largest report size being 256 bytes.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKhjv$ubh)}(hPERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a documented ordering to the values, implying PERF_FORMAT_ID must also be used to add a 64bit ID before each value; giving 16 bytes per counter.h]hPERF_FORMAT_GROUP values are 64bit, but there doesn’t appear to be a documented ordering to the values, implying PERF_FORMAT_ID must also be used to add a 64bit ID before each value; giving 16 bytes per counter.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKhjv$ubeh}(h]h ]h"]h$]h&]uh1j:hjs$ubah}(h]h ]h"]h$]h&]j[;j\;uh1j:hj$hKhj$ubh)}(hXRelated to counter orthogonality; we can't time share the OA unit, while event scheduling is a central design idea within perf for allowing userspace to open + enable more events than can be configured in HW at any one time. The OA unit is not designed to allow re-configuration while in use. We can't reconfigure the OA unit without losing internal OA unit state which we can't access explicitly to save and restore. Reconfiguring the OA unit is also relatively slow, involving ~100 register writes. From userspace Mesa also depends on a stable OA configuration when emitting MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be disabled while there are outstanding MI_RPC commands lest we hang the command streamer.h]hXRelated to counter orthogonality; we can’t time share the OA unit, while event scheduling is a central design idea within perf for allowing userspace to open + enable more events than can be configured in HW at any one time. The OA unit is not designed to allow re-configuration while in use. We can’t reconfigure the OA unit without losing internal OA unit state which we can’t access explicitly to save and restore. Reconfiguring the OA unit is also relatively slow, involving ~100 register writes. From userspace Mesa also depends on a stable OA configuration when emitting MI_REPORT_PERF_COUNT commands and importantly the OA unit can’t be disabled while there are outstanding MI_RPC commands lest we hang the command streamer.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKhj$ubh)}(hXThe contents of sample records aren't extensible by device drivers (i.e. the sample_type bits). As an example; Sourab Gupta had been looking to attach GPU timestamps to our OA samples. We were shoehorning OA reports into sample records by using the 'raw' field, but it's tricky to pack more than one thing into this field because events/core.c currently only lets a pmu give a single raw data pointer plus len which will be copied into the ring buffer. To include more than the OA report we'd have to copy the report into an intermediate larger buffer. I'd been considering allowing a vector of data+len values to be specified for copying the raw data, but it felt like a kludge to being using the raw field for this purpose.h]hXThe contents of sample records aren’t extensible by device drivers (i.e. the sample_type bits). As an example; Sourab Gupta had been looking to attach GPU timestamps to our OA samples. We were shoehorning OA reports into sample records by using the ‘raw’ field, but it’s tricky to pack more than one thing into this field because events/core.c currently only lets a pmu give a single raw data pointer plus len which will be copied into the ring buffer. To include more than the OA report we’d have to copy the report into an intermediate larger buffer. I’d been considering allowing a vector of data+len values to be specified for copying the raw data, but it felt like a kludge to being using the raw field for this purpose.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKhj$ubeh}(h]h ]h"]h$]h&]uh1j:hj$ubj:)}(hX\It felt like our perf based PMU was making some technical compromises just for the sake of using perf: perf_event_open() requires events to either relate to a pid or a specific cpu core, while our device pmu related to neither. Events opened with a pid will be automatically enabled/disabled according to the scheduling of that process - so not appropriate for us. When an event is related to a cpu id, perf ensures pmu methods will be invoked via an inter process interrupt on that core. To avoid invasive changes our userspace opened OA perf events for a specific cpu. This was workable but it meant the majority of the OA driver ran in atomic context, including all OA report forwarding, which wasn't really necessary in our case and seems to make our locking requirements somewhat complex as we handled the interaction with the rest of the i915 driver. h](h)}(hfIt felt like our perf based PMU was making some technical compromises just for the sake of using perf:h]hfIt felt like our perf based PMU was making some technical compromises just for the sake of using perf:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKhj$ubh)}(hXperf_event_open() requires events to either relate to a pid or a specific cpu core, while our device pmu related to neither. Events opened with a pid will be automatically enabled/disabled according to the scheduling of that process - so not appropriate for us. When an event is related to a cpu id, perf ensures pmu methods will be invoked via an inter process interrupt on that core. To avoid invasive changes our userspace opened OA perf events for a specific cpu. This was workable but it meant the majority of the OA driver ran in atomic context, including all OA report forwarding, which wasn't really necessary in our case and seems to make our locking requirements somewhat complex as we handled the interaction with the rest of the i915 driver.h]hXperf_event_open() requires events to either relate to a pid or a specific cpu core, while our device pmu related to neither. Events opened with a pid will be automatically enabled/disabled according to the scheduling of that process - so not appropriate for us. When an event is related to a cpu id, perf ensures pmu methods will be invoked via an inter process interrupt on that core. To avoid invasive changes our userspace opened OA perf events for a specific cpu. This was workable but it meant the majority of the OA driver ran in atomic context, including all OA report forwarding, which wasn’t really necessary in our case and seems to make our locking requirements somewhat complex as we handled the interaction with the rest of the i915 driver.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:602: ./drivers/gpu/drm/i915/i915_perf.chKhj$ubeh}(h]h ]h"]h$]h&]uh1j:hj$ubeh}(h]h ]h"]h$]h&]j[;j\;uh1j:hj'$hKhhj#ubeh}(h]2issues-hit-with-first-prototype-based-on-core-perfah ]h"]2issues hit with first prototype based on core perfah$]h&]uh1hhjx#hhhNhNubeh}(h]comparison-with-core-perfah ]h"]comparison with core perfah$]h&]uh1hhj#hhhhhMYubh)}(hhh](h)}(hi915 Driver Entry Pointsh]hi915 Driver Entry Points}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhhhM^ubh)}(hThis section covers the entrypoints exported outside of i915_perf.c to integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.h](hqThis section covers the entrypoints exported outside of i915_perf.c to integrate with drm/i915 and to handle the }(hj&%hhhNhNubjb)}(h`DRM_I915_PERF_OPEN`h]hDRM_I915_PERF_OPEN}(hj.%hhhNhNubah}(h]h ]h"]h$]h&]uh1jbhj&%ubh ioctl.}(hj&%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM`hj%hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_perf_init (C function)c.i915_perf_inithNtauh1jhj%hhhNhNubj')}(hhh](j,)}(h2int i915_perf_init (struct drm_i915_private *i915)h]j2)}(h1int i915_perf_init(struct drm_i915_private *i915)h](j)}(hinth]hint}(hj_%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[%hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:611: ./drivers/gpu/drm/i915/i915_perf.chMubji)}(h h]h }(hjn%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj[%hhhjm%hMubjz)}(hi915_perf_inith]j;)}(hi915_perf_inith]hi915_perf_init}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj|%ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj[%hhhjm%hMubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubji)}(h h]h }(hj%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj%ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj%modnameN classnameNjXj[)}j^]ja)}jTj%sbc.i915_perf_initasbuh1hhj%ubji)}(h h]h }(hj%hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj%ubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj;)}(hi915h]hi915}(hj%hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj%ubah}(h]h ]h"]h$]h&]jjuh1jhj[%hhhjm%hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjW%hhhjm%hMubah}(h]jR%ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjm%hMhjT%hhubj1)}(hhh]h)}(h)initialize i915-perf state on module bindh]h)initialize i915-perf state on module bind}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:611: ./drivers/gpu/drm/i915/i915_perf.chMhj&hhubah}(h]h ]h"]h$]h&]uh1j0hjT%hhhjm%hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj7&jSj7&jTjUjVuh1j&hhhj%hNhNubjX)}(hX***Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** Initializes i915-perf state without exposing anything to userspace. **Note** i915-perf initialization is split into an 'init' and 'register' phase with the i915_perf_register() exposing state to userspace.h](h)}(h**Parameters**h]jb)}(hjA&h]h Parameters}(hjC&hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?&ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:611: ./drivers/gpu/drm/i915/i915_perf.chMhj;&ubjx)}(hhh]j})}(h7``struct drm_i915_private *i915`` i915 device instance h](j)}(h!``struct drm_i915_private *i915``h]j)}(hj`&h]hstruct drm_i915_private *i915}(hjb&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^&ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:611: ./drivers/gpu/drm/i915/i915_perf.chMhjZ&ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hjy&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju&hMhjv&ubah}(h]h ]h"]h$]h&]uh1jhjZ&ubeh}(h]h ]h"]h$]h&]uh1j|hju&hMhjW&ubah}(h]h ]h"]h$]h&]uh1jwhj;&ubh)}(h**Description**h]jb)}(hj&h]h Description}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj&ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:611: ./drivers/gpu/drm/i915/i915_perf.chMhj;&ubh)}(hCInitializes i915-perf state without exposing anything to userspace.h]hCInitializes i915-perf state without exposing anything to userspace.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:611: ./drivers/gpu/drm/i915/i915_perf.chMhj;&ubh)}(h**Note**h]jb)}(hj&h]hNote}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj&ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:611: ./drivers/gpu/drm/i915/i915_perf.chMhj;&ubh)}(hi915-perf initialization is split into an 'init' and 'register' phase with the i915_perf_register() exposing state to userspace.h]hi915-perf initialization is split into an ‘init’ and ‘register’ phase with the i915_perf_register() exposing state to userspace.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:611: ./drivers/gpu/drm/i915/i915_perf.chMhj;&ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_perf_fini (C function)c.i915_perf_finihNtauh1jhj%hhhNhNubj')}(hhh](j,)}(h3void i915_perf_fini (struct drm_i915_private *i915)h]j2)}(h2void i915_perf_fini(struct drm_i915_private *i915)h](j)}(hvoidh]hvoid}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:613: ./drivers/gpu/drm/i915/i915_perf.chMSubji)}(h h]h }(hj'hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj'hhhj'hMSubjz)}(hi915_perf_finih]j;)}(hi915_perf_finih]hi915_perf_fini}(hj('hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj$'ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj'hhhj'hMSubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hjD'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@'ubji)}(h h]h }(hjQ'hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@'ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjb'hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_'ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjd'modnameN classnameNjXj[)}j^]ja)}jTj*'sbc.i915_perf_finiasbuh1hhj@'ubji)}(h h]h }(hj'hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj@'ubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@'ubj;)}(hi915h]hi915}(hj'hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj@'ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj<'ubah}(h]h ]h"]h$]h&]jjuh1jhj'hhhj'hMSubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj&hhhj'hMSubah}(h]j&ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj'hMShj&hhubj1)}(hhh]h)}(h Counter part to i915_perf_init()h]h Counter part to i915_perf_init()}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:613: ./drivers/gpu/drm/i915/i915_perf.chMShj'hhubah}(h]h ]h"]h$]h&]uh1j0hj&hhhj'hMSubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj'jSj'jTjUjVuh1j&hhhj%hNhNubjX)}(hH**Parameters** ``struct drm_i915_private *i915`` i915 device instanceh](h)}(h**Parameters**h]jb)}(hj'h]h Parameters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj'ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:613: ./drivers/gpu/drm/i915/i915_perf.chMWhj'ubjx)}(hhh]j})}(h6``struct drm_i915_private *i915`` i915 device instanceh](j)}(h!``struct drm_i915_private *i915``h]j)}(hj(h]hstruct drm_i915_private *i915}(hj (hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:613: ./drivers/gpu/drm/i915/i915_perf.chMYhj(ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj!(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:613: ./drivers/gpu/drm/i915/i915_perf.chMThj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1j|hj(hMYhj'ubah}(h]h ]h"]h$]h&]uh1jwhj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_perf_register (C function)c.i915_perf_registerhNtauh1jhj%hhhNhNubj')}(hhh](j,)}(h7void i915_perf_register (struct drm_i915_private *i915)h]j2)}(h6void i915_perf_register(struct drm_i915_private *i915)h](j)}(hvoidh]hvoid}(hjb(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^(hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:615: ./drivers/gpu/drm/i915/i915_perf.chMubji)}(h h]h }(hjq(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj^(hhhjp(hMubjz)}(hi915_perf_registerh]j;)}(hi915_perf_registerh]hi915_perf_register}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj^(hhhjp(hMubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj(ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj(modnameN classnameNjXj[)}j^]ja)}jTj(sbc.i915_perf_registerasbuh1hhj(ubji)}(h h]h }(hj(hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj(ubj)}(hjh]h*}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubj;)}(hi915h]hi915}(hj(hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj(ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj(ubah}(h]h ]h"]h$]h&]jjuh1jhj^(hhhjp(hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjZ(hhhjp(hMubah}(h]jU(ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjp(hMhjW(hhubj1)}(hhh]h)}(hexposes i915-perf to userspaceh]hexposes i915-perf to userspace}(hj")hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:615: ./drivers/gpu/drm/i915/i915_perf.chMhj)hhubah}(h]h ]h"]h$]h&]uh1j0hjW(hhhjp(hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj:)jSj:)jTjUjVuh1j&hhhj%hNhNubjX)}(h**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** In particular OA metric sets are advertised under a sysfs metrics/ directory allowing userspace to enumerate valid IDs that can be used to open an i915-perf stream.h](h)}(h**Parameters**h]jb)}(hjD)h]h Parameters}(hjF)hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjB)ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:615: ./drivers/gpu/drm/i915/i915_perf.chMhj>)ubjx)}(hhh]j})}(h7``struct drm_i915_private *i915`` i915 device instance h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjc)h]hstruct drm_i915_private *i915}(hje)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja)ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:615: ./drivers/gpu/drm/i915/i915_perf.chMhj])ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj|)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx)hMhjy)ubah}(h]h ]h"]h$]h&]uh1jhj])ubeh}(h]h ]h"]h$]h&]uh1j|hjx)hMhjZ)ubah}(h]h ]h"]h$]h&]uh1jwhj>)ubh)}(h**Description**h]jb)}(hj)h]h Description}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj)ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:615: ./drivers/gpu/drm/i915/i915_perf.chMhj>)ubh)}(hIn particular OA metric sets are advertised under a sysfs metrics/ directory allowing userspace to enumerate valid IDs that can be used to open an i915-perf stream.h]hIn particular OA metric sets are advertised under a sysfs metrics/ directory allowing userspace to enumerate valid IDs that can be used to open an i915-perf stream.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:615: ./drivers/gpu/drm/i915/i915_perf.chMhj>)ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!i915_perf_unregister (C function)c.i915_perf_unregisterhNtauh1jhj%hhhNhNubj')}(hhh](j,)}(h9void i915_perf_unregister (struct drm_i915_private *i915)h]j2)}(h8void i915_perf_unregister(struct drm_i915_private *i915)h](j)}(hvoidh]hvoid}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:617: ./drivers/gpu/drm/i915/i915_perf.chMubji)}(h h]h }(hj)hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj)hhhj)hMubjz)}(hi915_perf_unregisterh]j;)}(hi915_perf_unregisterh]hi915_perf_unregister}(hj*hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj*ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj)hhhj)hMubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hj *hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubji)}(h h]h }(hj-*hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj*ubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hj>*hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj;*ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj@*modnameN classnameNjXj[)}j^]ja)}jTj*sbc.i915_perf_unregisterasbuh1hhj*ubji)}(h h]h }(hj^*hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj*ubj)}(hjh]h*}(hjl*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj;)}(hi915h]hi915}(hjy*hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj*ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj*ubah}(h]h ]h"]h$]h&]jjuh1jhj)hhhj)hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj)hhhj)hMubah}(h]j)ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj)hMhj)hhubj1)}(hhh]h)}(hhide i915-perf from userspaceh]hhide i915-perf from userspace}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:617: ./drivers/gpu/drm/i915/i915_perf.chMhj*hhubah}(h]h ]h"]h$]h&]uh1j0hj)hhhj)hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj*jSj*jTjUjVuh1j&hhhj%hNhNubjX)}(hX+**Parameters** ``struct drm_i915_private *i915`` i915 device instance **Description** i915-perf state cleanup is split up into an 'unregister' and 'deinit' phase where the interface is first hidden from userspace by i915_perf_unregister() before cleaning up remaining state in i915_perf_fini().h](h)}(h**Parameters**h]jb)}(hj*h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj*ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:617: ./drivers/gpu/drm/i915/i915_perf.chMhj*ubjx)}(hhh]j})}(h7``struct drm_i915_private *i915`` i915 device instance h](j)}(h!``struct drm_i915_private *i915``h]j)}(hj*h]hstruct drm_i915_private *i915}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:617: ./drivers/gpu/drm/i915/i915_perf.chMhj*ubj)}(hhh]h)}(hi915 device instanceh]hi915 device instance}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1j|hj*hMhj*ubah}(h]h ]h"]h$]h&]uh1jwhj*ubh)}(h**Description**h]jb)}(hj+h]h Description}(hj!+hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj+ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:617: ./drivers/gpu/drm/i915/i915_perf.chMhj*ubh)}(hi915-perf state cleanup is split up into an 'unregister' and 'deinit' phase where the interface is first hidden from userspace by i915_perf_unregister() before cleaning up remaining state in i915_perf_fini().h]hi915-perf state cleanup is split up into an ‘unregister’ and ‘deinit’ phase where the interface is first hidden from userspace by i915_perf_unregister() before cleaning up remaining state in i915_perf_fini().}(hj5+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:617: ./drivers/gpu/drm/i915/i915_perf.chMhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"!i915_perf_open_ioctl (C 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Very little is assumed up front about the nature of the stream being opened (for instance we don't assume it's for periodic OA unit metrics). An i915-perf stream is expected to be a suitable interface for other forms of buffered data written by the GPU besides periodic OA metrics. Note we copy the properties from userspace outside of the i915 perf mutex to avoid an awkward lockdep with mmap_lock. Most of the implementation details are handled by i915_perf_open_ioctl_locked() after taking the :c:type:`gt->perf `.lock mutex for serializing with any non-file-operation driver hooks. **Return** A newly opened i915 Perf stream file descriptor or negative error code on failure.h](h)}(h**Parameters**h]jb)}(hj,h]h Parameters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj,ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMehj,ubjx)}(hhh](j})}(h&``struct drm_device *dev`` drm device h](j)}(h``struct drm_device *dev``h]j)}(hj-h]hstruct drm_device *dev}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMbhj-ubj)}(hhh]h)}(h drm deviceh]h drm device}(hj0-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,-hMbhj--ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1j|hj,-hMbhj-ubj})}(h>``void *data`` ioctl data copied from userspace (unvalidated) h](j)}(h``void *data``h]j)}(hjP-h]h void *data}(hjR-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN-ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMchjJ-ubj)}(hhh]h)}(h.ioctl data copied from userspace (unvalidated)h]h.ioctl data copied from userspace (unvalidated)}(hji-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhje-hMchjf-ubah}(h]h ]h"]h$]h&]uh1jhjJ-ubeh}(h]h ]h"]h$]h&]uh1j|hje-hMchj-ubj})}(h#``struct drm_file *file`` drm file h](j)}(h``struct drm_file *file``h]j)}(hj-h]hstruct drm_file *file}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMdhj-ubj)}(hhh]h)}(hdrm fileh]hdrm file}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMdhj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1j|hj-hMdhj-ubeh}(h]h ]h"]h$]h&]uh1jwhj,ubh)}(h**Description**h]jb)}(hj-h]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj-ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMfhj,ubh)}(hwValidates the stream open parameters given by userspace including flags and an array of u64 key, value pair properties.h]hwValidates the stream open parameters given by userspace including flags and an array of u64 key, value pair properties.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMfhj,ubh)}(hXVery little is assumed up front about the nature of the stream being opened (for instance we don't assume it's for periodic OA unit metrics). An i915-perf stream is expected to be a suitable interface for other forms of buffered data written by the GPU besides periodic OA metrics.h]hXVery little is assumed up front about the nature of the stream being opened (for instance we don’t assume it’s for periodic OA unit metrics). An i915-perf stream is expected to be a suitable interface for other forms of buffered data written by the GPU besides periodic OA metrics.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMihj,ubh)}(huNote we copy the properties from userspace outside of the i915 perf mutex to avoid an awkward lockdep with mmap_lock.h]huNote we copy the properties from userspace outside of the i915 perf mutex to avoid an awkward lockdep with mmap_lock.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMnhj,ubh)}(hMost of the implementation details are handled by i915_perf_open_ioctl_locked() after taking the :c:type:`gt->perf `.lock mutex for serializing with any non-file-operation driver hooks.h](haMost of the implementation details are handled by i915_perf_open_ioctl_locked() after taking the }(hj.hhhNhNubh)}(h:c:type:`gt->perf `h]j)}(hj.h]hgt->perf}(hj.hhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjgtuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMqhj.ubhE.lock mutex for serializing with any non-file-operation driver hooks.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj..hMqhj,ubh)}(h **Return**h]jb)}(hj;.h]hReturn}(hj=.hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj9.ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMuhj,ubh)}(hRA newly opened i915 Perf stream file descriptor or negative error code on failure.h]hRA newly opened i915 Perf stream file descriptor or negative error code on failure.}(hjQ.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:619: ./drivers/gpu/drm/i915/i915_perf.chMuhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhj%hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_perf_release (C function)c.i915_perf_releasehNtauh1jhj%hhhNhNubj')}(hhh](j,)}(h>int i915_perf_release (struct inode *inode, struct file *file)h]j2)}(h=int i915_perf_release(struct inode *inode, struct file *file)h](j)}(hinth]hint}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|.hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:621: ./drivers/gpu/drm/i915/i915_perf.chMubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj|.hhhj.hMubjz)}(hi915_perf_releaseh]j;)}(hi915_perf_releaseh]hi915_perf_release}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj|.hhhj.hMubj)}(h((struct inode *inode, struct file *file)h](j)}(hstruct inode *inodeh](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubh)}(hhh]j;)}(hinodeh]hinode}(hj.hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj.modnameN classnameNjXj[)}j^]ja)}jTj.sbc.i915_perf_releaseasbuh1hhj.ubji)}(h h]h }(hj.hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj.ubj)}(hjh]h*}(hj /hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubj;)}(hinodeh]hinode}(hj/hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj.ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj.ubj)}(hstruct file *fileh](j)}(hjh]hstruct}(hj//hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+/ubji)}(h h]h }(hjA list of struct i915_oa_config_bo allocated lazily each time }(hjI:hhhNhNubjb)}(h **oa_config**h]h oa_config}(hjQ:hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjI:ubh changes.}(hjI:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhKhjF:ubah}(h]h ]h"]h$]h&]uh1jhj*:ubeh}(h]h ]h"]h$]h&]uh1j|hjE:hKhjF7ubj})}(h4``pinned_ctx`` The OA context specific information. h](j)}(h``pinned_ctx``h]j)}(hj|:h]h pinned_ctx}(hj~:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz:ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhKhjv:ubj)}(hhh]h)}(h$The OA context specific information.h]h$The OA context specific information.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj:ubah}(h]h ]h"]h$]h&]uh1jhjv:ubeh}(h]h ]h"]h$]h&]uh1j|hj:hKhjF7ubj})}(h4``specific_ctx_id`` The id of the specific context. h](j)}(h``specific_ctx_id``h]j)}(hj:h]hspecific_ctx_id}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj:ubj)}(hhh]h)}(hThe id of the specific context.h]hThe id of the specific context.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1j|hj:hKhjF7ubj})}(hH``specific_ctx_id_mask`` The mask used to masking specific_ctx_id bits. h](j)}(h``specific_ctx_id_mask``h]j)}(hj:h]hspecific_ctx_id_mask}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj:ubj)}(hhh]h)}(h.The mask used to masking specific_ctx_id bits.h]h.The mask used to masking specific_ctx_id bits.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hKhj;ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1j|hj;hKhjF7ubj})}(h``poll_check_timer`` High resolution timer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()). h](j)}(h``poll_check_timer``h]j)}(hj';h]hpoll_check_timer}(hj);hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%;ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj!;ubj)}(hhh]h)}(hHigh resolution timer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()).h]hHigh resolution timer that will periodically check for data in the circular OA buffer for notifying userspace (e.g. during a read() or poll()).}(hj@;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj=;ubah}(h]h ]h"]h$]h&]uh1jhj!;ubeh}(h]h ]h"]h$]h&]uh1j|hj<;hMhjF7ubj})}(hr``poll_wq`` The wait queue that hrtimer callback wakes when it sees data ready to read in the circular OA buffer. h](j)}(h ``poll_wq``h]j)}(hja;h]hpoll_wq}(hjc;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_;ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhM hj[;ubj)}(hhh]h)}(heThe wait queue that hrtimer callback wakes when it sees data ready to read in the circular OA buffer.h]heThe wait queue that hrtimer callback wakes when it sees data ready to read in the circular OA buffer.}(hjz;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMhjw;ubah}(h]h ]h"]h$]h&]uh1jhj[;ubeh}(h]h ]h"]h$]h&]uh1j|hjv;hM hjF7ubj})}(h4``pollin`` Whether there is data available to read. h](j)}(h ``pollin``h]j)}(hj;h]hpollin}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj;ubj)}(hhh]h)}(h(Whether there is data available to read.h]h(Whether there is data available to read.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j|hj;hMhjF7ubj})}(h=``periodic`` Whether periodic sampling is currently enabled. h](j)}(h ``periodic``h]j)}(hj;h]hperiodic}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj;ubj)}(hhh]h)}(h/Whether periodic sampling is currently enabled.h]h/Whether periodic sampling is currently enabled.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j|hj;hMhjF7ubj})}(hI``period_exponent`` The OA unit sampling frequency is derived from this. h](j)}(h``period_exponent``h]j)}(hj <h]hperiod_exponent}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj <ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj<ubj)}(hhh]h)}(h4The OA unit sampling frequency is derived from this.h]h4The OA unit sampling frequency is derived from this.}(hj&<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"<hMhj#<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1j|hj"<hMhjF7ubj})}(h&``oa_buffer`` State of the OA buffer. h](j)}(h ``oa_buffer``h]j)}(hjF<h]h oa_buffer}(hjH<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD<ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMhj@<ubj)}(hhh]h)}(hState of the OA buffer.h]hState of the OA buffer.}(hj_<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[<hMhj\<ubah}(h]h ]h"]h$]h&]uh1jhj@<ubeh}(h]h ]h"]h$]h&]uh1j|hj[<hMhjF7ubj})}(hX8``oa_buffer.ptr_lock`` Locks reads and writes to all head/tail state Consider: the head and tail pointer state needs to be read consistently from a hrtimer callback (atomic context) and read() fop (user context) with tail pointer updates happening in atomic context and head updates in user context and the (unlikely) possibility of read() errors needing to reset all head/tail state. Note: Contention/performance aren't currently a significant concern here considering the relatively low frequency of hrtimer callbacks (5ms period) and that reads typically only happen in response to a hrtimer event and likely complete before the next callback. Note: This lock is not held *while* reading and copying data to userspace so the value of head observed in htrimer callbacks won't represent any partial consumption of data. h](j)}(h``oa_buffer.ptr_lock``h]j)}(hj<h]hoa_buffer.ptr_lock}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}<ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhM8hjy<ubj)}(hhh](h)}(h-Locks reads and writes to all head/tail stateh]h-Locks reads and writes to all head/tail state}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhM&hj<ubh)}(hX;Consider: the head and tail pointer state needs to be read consistently from a hrtimer callback (atomic context) and read() fop (user context) with tail pointer updates happening in atomic context and head updates in user context and the (unlikely) possibility of read() errors needing to reset all head/tail state.h]hX;Consider: the head and tail pointer state needs to be read consistently from a hrtimer callback (atomic context) and read() fop (user context) with tail pointer updates happening in atomic context and head updates in user context and the (unlikely) possibility of read() errors needing to reset all head/tail state.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhM)hj<ubh)}(hXNote: Contention/performance aren't currently a significant concern here considering the relatively low frequency of hrtimer callbacks (5ms period) and that reads typically only happen in response to a hrtimer event and likely complete before the next callback.h]hXNote: Contention/performance aren’t currently a significant concern here considering the relatively low frequency of hrtimer callbacks (5ms period) and that reads typically only happen in response to a hrtimer event and likely complete before the next callback.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhM0hj<ubh)}(hNote: This lock is not held *while* reading and copying data to userspace so the value of head observed in htrimer callbacks won't represent any partial consumption of data.h](hNote: This lock is not held }(hj<hhhNhNubj->)}(h*while*h]hwhile}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j,>hj<ubh reading and copying data to userspace so the value of head observed in htrimer callbacks won’t represent any partial consumption of data.}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhM6hj<ubeh}(h]h ]h"]h$]h&]uh1jhjy<ubeh}(h]h ]h"]h$]h&]uh1j|hj<hM8hjF7ubj})}(hX ``oa_buffer.head`` Although we can always read back the head pointer register, we prefer to avoid trusting the HW state, just to avoid any risk that some hardware condition could * somehow bump the head pointer unpredictably and cause us to forward the wrong OA buffer data to userspace. h](j)}(h``oa_buffer.head``h]j)}(hj<h]hoa_buffer.head}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMBhj<ubj)}(hhh]h)}(hX Although we can always read back the head pointer register, we prefer to avoid trusting the HW state, just to avoid any risk that some hardware condition could * somehow bump the head pointer unpredictably and cause us to forward the wrong OA buffer data to userspace.h]hX Although we can always read back the head pointer register, we prefer to avoid trusting the HW state, just to avoid any risk that some hardware condition could * somehow bump the head pointer unpredictably and cause us to forward the wrong OA buffer data to userspace.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhM=hj=ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1j|hj =hMBhjF7ubj})}(hI``oa_buffer.tail`` The last verified tail that can be read by userspace. h](j)}(h``oa_buffer.tail``h]j)}(hj2=h]hoa_buffer.tail}(hj4=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0=ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMHhj,=ubj)}(hhh]h)}(h5The last verified tail that can be read by userspace.h]h5The last verified tail that can be read by userspace.}(hjK=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMGhjH=ubah}(h]h ]h"]h$]h&]uh1jhj,=ubeh}(h]h ]h"]h$]h&]uh1j|hjG=hMHhjF7ubj})}(hZ``noa_wait`` A batch buffer doing a wait on the GPU for the NOA logic to be reprogrammed. h](j)}(h ``noa_wait``h]j)}(hjl=h]hnoa_wait}(hjn=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj=ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMOhjf=ubj)}(hhh]h)}(hLA batch buffer doing a wait on the GPU for the NOA logic to be reprogrammed.h]hLA batch buffer doing a wait on the GPU for the NOA logic to be reprogrammed.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMNhj=ubah}(h]h ]h"]h$]h&]uh1jhjf=ubeh}(h]h ]h"]h$]h&]uh1j|hj=hMOhjF7ubj})}(hi``poll_oa_period`` The period in nanoseconds at which the OA buffer should be checked for available data.h](j)}(h``poll_oa_period``h]j)}(hj=h]hpoll_oa_period}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:634: ./drivers/gpu/drm/i915/i915_perf_types.hhMThj=ubj)}(hhh]h)}(hVThe period in nanoseconds at which the OA buffer should be checked for available data.h]hVThe period in nanoseconds at which the OA buffer should be checked for available data.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMThj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1j|hj=hMThjF7ubeh}(h]h ]h"]h$]h&]uh1jwhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjh6hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_perf_stream_ops (C struct)c.i915_perf_stream_opshNtauh1jhjh6hhhNhNubj')}(hhh](j,)}(hi915_perf_stream_opsh]j2)}(hstruct i915_perf_stream_opsh](j)}(hjh]hstruct}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKubji)}(h h]h }(hj >hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj=hhhj >hKubjz)}(hi915_perf_stream_opsh]j;)}(hj=h]hi915_perf_stream_ops}(hj>hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj>ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj=hhhj >hKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj=hhhj >hKubah}(h]j=ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj >hKhj=hhubj1)}(hhh]h)}(h)the OPs to support a specific stream typeh]h)the OPs to support a specific stream type}(hjA>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKehj>>hhubah}(h]h ]h"]h$]h&]uh1j0hj=hhhj >hKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjY>jSjY>jTjUjVuh1j&hhhjh6hNhNubjX)}(hX**Definition**:: struct i915_perf_stream_ops { void (*enable)(struct i915_perf_stream *stream); void (*disable)(struct i915_perf_stream *stream); void (*poll_wait)(struct i915_perf_stream *stream,struct file *file, poll_table *wait); int (*wait_unlocked)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream,char __user *buf,size_t count, size_t *offset); void (*destroy)(struct i915_perf_stream *stream); }; **Members** ``enable`` Enables the collection of HW samples, either in response to `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened without `I915_PERF_FLAG_DISABLED`. ``disable`` Disables the collection of HW samples, either in response to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying the stream. ``poll_wait`` Call poll_wait, passing a wait queue that will be woken once there is something ready to read() for the stream ``wait_unlocked`` For handling a blocking read, wait until there is something to ready to read() for the stream. E.g. wait on the same wait queue that would be passed to poll_wait(). ``read`` Copy buffered metrics as records to userspace **buf**: the userspace, destination buffer **count**: the number of bytes to copy, requested by userspace **offset**: zero at the start of the read, updated as the read proceeds, it represents how many bytes have been copied so far and the buffer offset for copying the next record. Copy as many buffered i915 perf samples and records for this stream to userspace as will fit in the given buffer. Only write complete records; returning -``ENOSPC`` if there isn't room for a complete record. Return any error condition that results in a short read such as -``ENOSPC`` or -``EFAULT``, even though these may be squashed before returning to userspace. ``destroy`` Cleanup any stream specific resources. The stream will always be disabled before this is called.h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hje>hhhNhNubah}(h]h ]h"]h$]h&]uh1jahja>ubh:}(hja>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKihj]>ubj")}(hXstruct i915_perf_stream_ops { void (*enable)(struct i915_perf_stream *stream); void (*disable)(struct i915_perf_stream *stream); void (*poll_wait)(struct i915_perf_stream *stream,struct file *file, poll_table *wait); int (*wait_unlocked)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream,char __user *buf,size_t count, size_t *offset); void (*destroy)(struct i915_perf_stream *stream); };h]hXstruct i915_perf_stream_ops { void (*enable)(struct i915_perf_stream *stream); void (*disable)(struct i915_perf_stream *stream); void (*poll_wait)(struct i915_perf_stream *stream,struct file *file, poll_table *wait); int (*wait_unlocked)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream,char __user *buf,size_t count, size_t *offset); void (*destroy)(struct i915_perf_stream *stream); };}hj~>sbah}(h]h ]h"]h$]h&]jjuh1j"h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKkhj]>ubh)}(h **Members**h]jb)}(hj>h]hMembers}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj>ubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKthj]>ubjx)}(hhh](j})}(h``enable`` Enables the collection of HW samples, either in response to `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened without `I915_PERF_FLAG_DISABLED`. h](j)}(h ``enable``h]j)}(hj>h]henable}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKlhj>ubj)}(hhh]h)}(hEnables the collection of HW samples, either in response to `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened without `I915_PERF_FLAG_DISABLED`.h](hhhhNhNubjb)}(h`I915_PERF_IOCTL_ENABLE`h]hI915_PERF_IOCTL_ENABLE}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jbhj>ubh4 or implicitly called when stream is opened without }(hj>hhhNhNubjb)}(h`I915_PERF_FLAG_DISABLED`h]hI915_PERF_FLAG_DISABLED}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jbhj>ubh.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKjhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1j|hj>hKlhj>ubj})}(h``disable`` Disables the collection of HW samples, either in response to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying the stream. h](j)}(h ``disable``h]j)}(hj ?h]hdisable}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKshj?ubj)}(hhh]h)}(hDisables the collection of HW samples, either in response to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying the stream.h](h=Disables the collection of HW samples, either in response to }(hj%?hhhNhNubjb)}(h`I915_PERF_IOCTL_DISABLE`h]hI915_PERF_IOCTL_DISABLE}(hj-?hhhNhNubah}(h]h ]h"]h$]h&]uh1jbhj%?ubh3 or implicitly called before destroying the stream.}(hj%?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKqhj"?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j|hj!?hKshj>ubj})}(h}``poll_wait`` Call poll_wait, passing a wait queue that will be woken once there is something ready to read() for the stream h](j)}(h ``poll_wait``h]j)}(hjX?h]h poll_wait}(hjZ?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjV?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKyhjR?ubj)}(hhh]h)}(hnCall poll_wait, passing a wait queue that will be woken once there is something ready to read() for the streamh]hnCall poll_wait, passing a wait queue that will be woken once there is something ready to read() for the stream}(hjq?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKxhjn?ubah}(h]h ]h"]h$]h&]uh1jhjR?ubeh}(h]h ]h"]h$]h&]uh1j|hjm?hKyhj>ubj})}(h``wait_unlocked`` For handling a blocking read, wait until there is something to ready to read() for the stream. E.g. wait on the same wait queue that would be passed to poll_wait(). h](j)}(h``wait_unlocked``h]j)}(hj?h]h wait_unlocked}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj?ubj)}(hhh]h)}(hFor handling a blocking read, wait until there is something to ready to read() for the stream. E.g. wait on the same wait queue that would be passed to poll_wait().h]hFor handling a blocking read, wait until there is something to ready to read() for the stream. E.g. wait on the same wait queue that would be passed to poll_wait().}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j|hj?hKhj>ubj})}(hX``read`` Copy buffered metrics as records to userspace **buf**: the userspace, destination buffer **count**: the number of bytes to copy, requested by userspace **offset**: zero at the start of the read, updated as the read proceeds, it represents how many bytes have been copied so far and the buffer offset for copying the next record. Copy as many buffered i915 perf samples and records for this stream to userspace as will fit in the given buffer. Only write complete records; returning -``ENOSPC`` if there isn't room for a complete record. Return any error condition that results in a short read such as -``ENOSPC`` or -``EFAULT``, even though these may be squashed before returning to userspace. h](j)}(h``read``h]j)}(hj?h]hread}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj?ubj)}(hhh](h)}(hXHCopy buffered metrics as records to userspace **buf**: the userspace, destination buffer **count**: the number of bytes to copy, requested by userspace **offset**: zero at the start of the read, updated as the read proceeds, it represents how many bytes have been copied so far and the buffer offset for copying the next record.h](h.Copy buffered metrics as records to userspace }(hj?hhhNhNubjb)}(h**buf**h]hbuf}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubh$: the userspace, destination buffer }(hj?hhhNhNubjb)}(h **count**h]hcount}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubh6: the number of bytes to copy, requested by userspace }(hj?hhhNhNubjb)}(h **offset**h]hoffset}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj?ubh: zero at the start of the read, updated as the read proceeds, it represents how many bytes have been copied so far and the buffer offset for copying the next record.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj?ubh)}(hqCopy as many buffered i915 perf samples and records for this stream to userspace as will fit in the given buffer.h]hqCopy as many buffered i915 perf samples and records for this stream to userspace as will fit in the given buffer.}(hj*@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj?ubh)}(h]Only write complete records; returning -``ENOSPC`` if there isn't room for a complete record.h](h(Only write complete records; returning -}(hj9@hhhNhNubj)}(h ``ENOSPC``h]hENOSPC}(hjA@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9@ubh- if there isn’t room for a complete record.}(hj9@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj?ubh)}(hReturn any error condition that results in a short read such as -``ENOSPC`` or -``EFAULT``, even though these may be squashed before returning to userspace.h](hAReturn any error condition that results in a short read such as -}(hjZ@hhhNhNubj)}(h ``ENOSPC``h]hENOSPC}(hjb@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ@ubh or -}(hjZ@hhhNhNubj)}(h ``EFAULT``h]hEFAULT}(hjt@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ@ubhB, even though these may be squashed before returning to userspace.}(hjZ@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj?ubeh}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j|hj?hKhj>ubj})}(hm``destroy`` Cleanup any stream specific resources. The stream will always be disabled before this is called.h](j)}(h ``destroy``h]j)}(hj@h]hdestroy}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj@ubj)}(hhh](h)}(h&Cleanup any stream specific resources.h]h&Cleanup any stream specific resources.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj@ubh)}(h9The stream will always be disabled before this is called.h]h9The stream will always be disabled before this is called.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:636: ./drivers/gpu/drm/i915/i915_perf_types.hhKhj@ubeh}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1j|hj@hKhj>ubeh}(h]h ]h"]h$]h&]uh1jwhj]>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjh6hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%read_properties_unlocked (C function)c.read_properties_unlockedhNtauh1jhjh6hhhNhNubj')}(hhh](j,)}(hzint read_properties_unlocked (struct i915_perf *perf, u64 __user *uprops, u32 n_props, struct perf_open_properties *props)h]j2)}(hyint read_properties_unlocked(struct i915_perf *perf, u64 __user *uprops, u32 n_props, struct perf_open_properties *props)h](j)}(hinth]hint}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMoubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAhhhjAhMoubjz)}(hread_properties_unlockedh]j;)}(hread_properties_unlockedh]hread_properties_unlocked}(hj)AhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj%Aubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjAhhhjAhMoubj)}(h](struct i915_perf *perf, u64 __user *uprops, u32 n_props, struct perf_open_properties *props)h](j)}(hstruct i915_perf *perfh](j)}(hjh]hstruct}(hjEAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAAubji)}(h h]h }(hjRAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAAubh)}(hhh]j;)}(h i915_perfh]h i915_perf}(hjcAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`Aubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjeAmodnameN classnameNjXj[)}j^]ja)}jTj+Asbc.read_properties_unlockedasbuh1hhjAAubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAAubj)}(hjh]h*}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAAubj;)}(hperfh]hperf}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAAubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Aubj)}(hu64 __user *upropsh](h)}(hhh]j;)}(hu64h]hu64}(hjAhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjAmodnameN classnameNjXj[)}j^]jAc.read_properties_unlockedasbuh1hhjAubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAubh__user}(hjAhhhNhNubji)}(h h]h }(hjAhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjAubj)}(hjh]h*}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubj;)}(hupropsh]huprops}(hjBhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjAubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Aubj)}(h u32 n_propsh](h)}(hhh]j;)}(hu32h]hu32}(hj!BhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjBubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj#BmodnameN classnameNjXj[)}j^]jAc.read_properties_unlockedasbuh1hhjBubji)}(h h]h }(hj?BhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjBubj;)}(hn_propsh]hn_props}(hjMBhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjBubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Aubj)}(h"struct perf_open_properties *propsh](j)}(hjh]hstruct}(hjfBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbBubji)}(h h]h }(hjsBhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbBubh)}(hhh]j;)}(hperf_open_propertiesh]hperf_open_properties}(hjBhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjBubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjBmodnameN classnameNjXj[)}j^]jAc.read_properties_unlockedasbuh1hhjbBubji)}(h h]h }(hjBhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjbBubj)}(hjh]h*}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbBubj;)}(hpropsh]hprops}(hjBhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjbBubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj=Aubeh}(h]h ]h"]h$]h&]jjuh1jhjAhhhjAhMoubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjAhhhjAhMoubah}(h]j@ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjAhMohj@hhubj1)}(hhh]h)}(h0validate + copy userspace stream open propertiesh]h0validate + copy userspace stream open properties}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMohjBhhubah}(h]h ]h"]h$]h&]uh1j0hj@hhhjAhMoubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjBjSjBjTjUjVuh1j&hhhjh6hNhNubjX)}(hX**Parameters** ``struct i915_perf *perf`` i915 perf instance ``u64 __user *uprops`` The array of u64 key value pairs given by userspace ``u32 n_props`` The number of key value pairs expected in **uprops** ``struct perf_open_properties *props`` The stream configuration built up while validating properties **Description** Note this function only validates properties in isolation it doesn't validate that the combination of properties makes sense or that all properties necessary for a particular kind of stream have been set. Note that there currently aren't any ordering requirements for properties so we shouldn't validate or assume anything about ordering here. This doesn't rule out defining new properties with ordering requirements in the future.h](h)}(h**Parameters**h]jb)}(hj Ch]h Parameters}(hj ChhhNhNubah}(h]h ]h"]h$]h&]uh1jahjCubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMshjCubjx)}(hhh](j})}(h.``struct i915_perf *perf`` i915 perf instance h](j)}(h``struct i915_perf *perf``h]j)}(hj(Ch]hstruct i915_perf *perf}(hj*ChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&Cubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMphj"Cubj)}(hhh]h)}(hi915 perf instanceh]hi915 perf instance}(hjAChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ChMphj>Cubah}(h]h ]h"]h$]h&]uh1jhj"Cubeh}(h]h ]h"]h$]h&]uh1j|hj=ChMphjCubj})}(hK``u64 __user *uprops`` The array of u64 key value pairs given by userspace h](j)}(h``u64 __user *uprops``h]j)}(hjaCh]hu64 __user *uprops}(hjcChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_Cubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMqhj[Cubj)}(hhh]h)}(h3The array of u64 key value pairs given by userspaceh]h3The array of u64 key value pairs given by userspace}(hjzChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvChMqhjwCubah}(h]h ]h"]h$]h&]uh1jhj[Cubeh}(h]h ]h"]h$]h&]uh1j|hjvChMqhjCubj})}(hE``u32 n_props`` The number of key value pairs expected in **uprops** h](j)}(h``u32 n_props``h]j)}(hjCh]h u32 n_props}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMrhjCubj)}(hhh]h)}(h4The number of key value pairs expected in **uprops**h](h*The number of key value pairs expected in }(hjChhhNhNubjb)}(h **uprops**h]huprops}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jahjCubeh}(h]h ]h"]h$]h&]uh1hhjChMrhjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1j|hjChMrhjCubj})}(he``struct perf_open_properties *props`` The stream configuration built up while validating properties h](j)}(h&``struct perf_open_properties *props``h]j)}(hjCh]h"struct perf_open_properties *props}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMshjCubj)}(hhh]h)}(h=The stream configuration built up while validating propertiesh]h=The stream configuration built up while validating properties}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMshjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1j|hjChMshjCubeh}(h]h ]h"]h$]h&]uh1jwhjCubh)}(h**Description**h]jb)}(hjDh]h Description}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjDubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMuhjCubh)}(hNote this function only validates properties in isolation it doesn't validate that the combination of properties makes sense or that all properties necessary for a particular kind of stream have been set.h]hNote this function only validates properties in isolation it doesn’t validate that the combination of properties makes sense or that all properties necessary for a particular kind of stream have been set.}(hj2DhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMuhjCubh)}(hNote that there currently aren't any ordering requirements for properties so we shouldn't validate or assume anything about ordering here. This doesn't rule out defining new properties with ordering requirements in the future.h]hNote that there currently aren’t any ordering requirements for properties so we shouldn’t validate or assume anything about ordering here. This doesn’t rule out defining new properties with ordering requirements in the future.}(hjADhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:639: ./drivers/gpu/drm/i915/i915_perf.chMyhjCubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjh6hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"(i915_perf_open_ioctl_locked (C function)c.i915_perf_open_ioctl_lockedhNtauh1jhjh6hhhNhNubj')}(hhh](j,)}(hint i915_perf_open_ioctl_locked (struct i915_perf *perf, struct drm_i915_perf_open_param *param, struct perf_open_properties *props, struct drm_file *file)h]j2)}(hint i915_perf_open_ioctl_locked(struct i915_perf *perf, struct drm_i915_perf_open_param *param, struct perf_open_properties *props, struct drm_file *file)h](j)}(hinth]hint}(hjpDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlDhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMubji)}(h h]h }(hjDhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjlDhhhj~DhMubjz)}(hi915_perf_open_ioctl_lockedh]j;)}(hi915_perf_open_ioctl_lockedh]hi915_perf_open_ioctl_locked}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjDubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjlDhhhj~DhMubj)}(h{(struct i915_perf *perf, struct drm_i915_perf_open_param *param, struct perf_open_properties *props, struct drm_file *file)h](j)}(hstruct i915_perf *perfh](j)}(hjh]hstruct}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDubji)}(h h]h }(hjDhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjDubh)}(hhh]j;)}(h i915_perfh]h i915_perf}(hjDhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjDubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjDmodnameN classnameNjXj[)}j^]ja)}jTjDsbc.i915_perf_open_ioctl_lockedasbuh1hhjDubji)}(h h]h }(hjDhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjDubj)}(hjh]h*}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDubj;)}(hperfh]hperf}(hjEhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjDubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjDubj)}(h&struct drm_i915_perf_open_param *paramh](j)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubji)}(h h]h }(hj,EhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubh)}(hhh]j;)}(hdrm_i915_perf_open_paramh]hdrm_i915_perf_open_param}(hj=EhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj:Eubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj?EmodnameN classnameNjXj[)}j^]jDc.i915_perf_open_ioctl_lockedasbuh1hhjEubji)}(h h]h }(hj[EhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubj)}(hjh]h*}(hjiEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj;)}(hparamh]hparam}(hjvEhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjDubj)}(h"struct perf_open_properties *propsh](j)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubji)}(h h]h }(hjEhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubh)}(hhh]j;)}(hperf_open_propertiesh]hperf_open_properties}(hjEhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjEmodnameN classnameNjXj[)}j^]jDc.i915_perf_open_ioctl_lockedasbuh1hhjEubji)}(h h]h }(hjEhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubj)}(hjh]h*}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj;)}(hpropsh]hprops}(hjEhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjDubj)}(hstruct drm_file *fileh](j)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubji)}(h h]h }(hj FhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubh)}(hhh]j;)}(hdrm_fileh]hdrm_file}(hjFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjFubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjFmodnameN classnameNjXj[)}j^]jDc.i915_perf_open_ioctl_lockedasbuh1hhjEubji)}(h h]h }(hj;FhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjEubj)}(hjh]h*}(hjIFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj;)}(hfileh]hfile}(hjVFhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjEubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjDubeh}(h]h ]h"]h$]h&]jjuh1jhjlDhhhj~DhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhDhhhj~DhMubah}(h]jcDah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj~DhMhjeDhhubj1)}(hhh]h)}(h-DRM ioctl() for userspace to open a stream FDh]h-DRM ioctl() for userspace to open a stream FD}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhj}Fhhubah}(h]h ]h"]h$]h&]uh1j0hjeDhhhj~DhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjFjSjFjTjUjVuh1j&hhhjh6hNhNubjX)}(hX **Parameters** ``struct i915_perf *perf`` i915 perf instance ``struct drm_i915_perf_open_param *param`` The open parameters passed to 'DRM_I915_PERF_OPEN` ``struct perf_open_properties *props`` individually validated u64 property value pairs ``struct drm_file *file`` drm file **Description** See i915_perf_ioctl_open() for interface details. Implements further stream config validation and stream initialization on behalf of i915_perf_open_ioctl() with the :c:type:`gt->perf `.lock mutex taken to serialize with any non-file-operation driver hooks. In the case where userspace is interested in OA unit metrics then further config validation and stream initialization details will be handled by i915_oa_stream_init(). The code here should only validate config state that will be relevant to all stream types / backends. **Note** at this point the **props** have only been validated in isolation and it's still necessary to validate that the combination of properties makes sense. **Return** zero on success or a negative error code.h](h)}(h**Parameters**h]jb)}(hjFh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjFubjx)}(hhh](j})}(h.``struct i915_perf *perf`` i915 perf instance h](j)}(h``struct i915_perf *perf``h]j)}(hjFh]hstruct i915_perf *perf}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjFubj)}(hhh]h)}(hi915 perf instanceh]hi915 perf instance}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhMhjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1j|hjFhMhjFubj})}(h^``struct drm_i915_perf_open_param *param`` The open parameters passed to 'DRM_I915_PERF_OPEN` h](j)}(h*``struct drm_i915_perf_open_param *param``h]j)}(hjFh]h&struct drm_i915_perf_open_param *param}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjFubj)}(hhh]h)}(h2The open parameters passed to 'DRM_I915_PERF_OPEN`h]h4The open parameters passed to ‘DRM_I915_PERF_OPEN`}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjGubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1j|hjGhMhjFubj})}(hW``struct perf_open_properties *props`` individually validated u64 property value pairs h](j)}(h&``struct perf_open_properties *props``h]j)}(hj3Gh]h"struct perf_open_properties *props}(hj5GhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1Gubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhj-Gubj)}(hhh]h)}(h/individually validated u64 property value pairsh]h/individually validated u64 property value pairs}(hjLGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHGhMhjIGubah}(h]h ]h"]h$]h&]uh1jhj-Gubeh}(h]h ]h"]h$]h&]uh1j|hjHGhMhjFubj})}(h#``struct drm_file *file`` drm file h](j)}(h``struct drm_file *file``h]j)}(hjlGh]hstruct drm_file *file}(hjnGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjGubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjfGubj)}(hhh]h)}(hdrm fileh]hdrm file}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjGubah}(h]h ]h"]h$]h&]uh1jhjfGubeh}(h]h ]h"]h$]h&]uh1j|hjGhMhjFubeh}(h]h ]h"]h$]h&]uh1jwhjFubh)}(h**Description**h]jb)}(hjGh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjGubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjFubh)}(h1See i915_perf_ioctl_open() for interface details.h]h1See i915_perf_ioctl_open() for interface details.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjFubh)}(hImplements further stream config validation and stream initialization on behalf of i915_perf_open_ioctl() with the :c:type:`gt->perf `.lock mutex taken to serialize with any non-file-operation driver hooks.h](hsImplements further stream config validation and stream initialization on behalf of i915_perf_open_ioctl() with the }(hjGhhhNhNubh)}(h:c:type:`gt->perf `h]j)}(hjGh]hgt->perf}(hjGhhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXjjjjgtuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjGubhH.lock mutex taken to serialize with any non-file-operation driver hooks.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjGhMhjFubh)}(hX In the case where userspace is interested in OA unit metrics then further config validation and stream initialization details will be handled by i915_oa_stream_init(). The code here should only validate config state that will be relevant to all stream types / backends.h]hX In the case where userspace is interested in OA unit metrics then further config validation and stream initialization details will be handled by i915_oa_stream_init(). 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**Return**h]jb)}(hjHHh]hReturn}(hjJHhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFHubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjFubh)}(h)zero on success or a negative error code.h]h)zero on success or a negative error code.}(hj^HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:641: ./drivers/gpu/drm/i915/i915_perf.chMhjFubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjh6hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"%i915_perf_destroy_locked (C function)c.i915_perf_destroy_lockedhNtauh1jhjh6hhhNhNubj')}(hhh](j,)}(h?void i915_perf_destroy_locked (struct i915_perf_stream *stream)h]j2)}(h>void i915_perf_destroy_locked(struct i915_perf_stream *stream)h](j)}(hvoidh]hvoid}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:643: ./drivers/gpu/drm/i915/i915_perf.chMrubji)}(h h]h }(hjHhhhNhNubah}(h]h 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streamh]hdestroy an i915 perf stream}(hjMIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:643: ./drivers/gpu/drm/i915/i915_perf.chMrhjJIhhubah}(h]h ]h"]h$]h&]uh1j0hjHhhhjHhMrubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjeIjSjeIjTjUjVuh1j&hhhjh6hNhNubjX)}(hXM**Parameters** ``struct i915_perf_stream *stream`` An i915 perf stream **Description** Frees all resources associated with the given i915 perf **stream**, disabling any associated data capture in the process. **Note** The :c:type:`gt->perf `.lock mutex has been taken to serialize with any non-file-operation driver hooks.h](h)}(h**Parameters**h]jb)}(hjoIh]h Parameters}(hjqIhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjmIubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:643: ./drivers/gpu/drm/i915/i915_perf.chMvhjiIubjx)}(hhh]j})}(h8``struct i915_perf_stream *stream`` An i915 perf stream h](j)}(h#``struct i915_perf_stream *stream``h]j)}(hjIh]hstruct i915_perf_stream *stream}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:643: ./drivers/gpu/drm/i915/i915_perf.chMshjIubj)}(hhh]h)}(hAn i915 perf streamh]hAn i915 perf stream}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMshjIubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1j|hjIhMshjIubah}(h]h ]h"]h$]h&]uh1jwhjiIubh)}(h**Description**h]jb)}(hjIh]h Description}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjIubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:643: ./drivers/gpu/drm/i915/i915_perf.chMuhjiIubh)}(hyFrees all resources associated with the given i915 perf **stream**, disabling any associated data capture in the process.h](h8Frees all resources associated with the given i915 perf }(hjIhhhNhNubjb)}(h **stream**h]hstream}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjIubh7, disabling any associated data capture in the process.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:643: 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kernelindentah"]h$]h&]uh1jWhjh6hhhNhNubeh}(h]i915-perf-streamah ]h"]i915 perf streamah$]h&]uh1hhj#hhhhhMuubh)}(hhh](h)}(h)i915 Perf Observation Architecture Streamh]h)i915 Perf Observation Architecture Stream}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhhhhhMubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_oa_ops (C struct) c.i915_oa_opshNtauh1jhjYhhhNhNubj')}(hhh](j,)}(h i915_oa_opsh]j2)}(hstruct i915_oa_opsh](j)}(hjh]hstruct}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYhhh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhKubji)}(h h]h }(hjYhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjYhhhjYhKubjz)}(h i915_oa_opsh]j;)}(hjYh]h i915_oa_ops}(hjYhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjYubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjYhhhjYhKubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjYhhhjYhKubah}(h]jYah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjYhKhjYhhubj1)}(hhh]h)}(h0Gen specific implementation of an OA unit streamh]h0Gen specific implementation of an OA unit stream}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhMZhjYhhubah}(h]h ]h"]h$]h&]uh1j0hjYhhhjYhKubeh}(h]h ](jRstructeh"]h$]h&]jQjRjRjZjSjZjTjUjVuh1j&hhhjYhNhNubjX)}(hX**Definition**:: struct i915_oa_ops { bool (*is_valid_b_counter_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_mux_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_flex_reg)(struct i915_perf *perf, u32 addr); int (*enable_metric_set)(struct i915_perf_stream *stream, struct i915_active *active); void (*disable_metric_set)(struct i915_perf_stream *stream); void (*oa_enable)(struct i915_perf_stream *stream); void (*oa_disable)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream,char __user *buf,size_t count, size_t *offset); u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream); }; **Members** ``is_valid_b_counter_reg`` Validates register's address for programming boolean counters for a particular platform. ``is_valid_mux_reg`` Validates register's address for programming mux for a particular platform. ``is_valid_flex_reg`` Validates register's address for programming flex EU filtering for a particular platform. ``enable_metric_set`` Selects and applies any MUX configuration to set up the Boolean and Custom (B/C) counters that are part of the counter reports being sampled. May apply system constraints such as disabling EU clock gating as required. ``disable_metric_set`` Remove system constraints associated with using the OA unit. ``oa_enable`` Enable periodic sampling ``oa_disable`` Disable periodic sampling ``read`` Copy data from the circular OA buffer into a given userspace buffer. ``oa_hw_tail_read`` read the OA tail pointer register In particular this enables us to share all the fiddly code for handling the OA unit tail pointer race that affects multiple generations.h](h)}(h**Definition**::h](jb)}(h**Definition**h]h Definition}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjZubh:}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhM^hjZubj")}(hXstruct i915_oa_ops { bool (*is_valid_b_counter_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_mux_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_flex_reg)(struct i915_perf *perf, u32 addr); int (*enable_metric_set)(struct i915_perf_stream *stream, struct i915_active *active); void (*disable_metric_set)(struct i915_perf_stream *stream); void (*oa_enable)(struct i915_perf_stream *stream); void (*oa_disable)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream,char __user *buf,size_t count, size_t *offset); u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream); };h]hXstruct i915_oa_ops { bool (*is_valid_b_counter_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_mux_reg)(struct i915_perf *perf, u32 addr); bool (*is_valid_flex_reg)(struct i915_perf *perf, u32 addr); int (*enable_metric_set)(struct i915_perf_stream *stream, struct i915_active *active); void (*disable_metric_set)(struct i915_perf_stream *stream); void (*oa_enable)(struct i915_perf_stream *stream); void (*oa_disable)(struct i915_perf_stream *stream); int (*read)(struct i915_perf_stream *stream,char __user *buf,size_t count, size_t *offset); u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream); };}hj7Zsbah}(h]h ]h"]h$]h&]jjuh1j"h`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhM`hjZubh)}(h **Members**h]jb)}(hjHZh]hMembers}(hjJZhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjFZubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhMlhjZubjx)}(hhh](j})}(ht``is_valid_b_counter_reg`` Validates register's address for programming boolean counters for a particular platform. h](j)}(h``is_valid_b_counter_reg``h]j)}(hjgZh]his_valid_b_counter_reg}(hjiZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeZubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhM`hjaZubj)}(hhh]h)}(hXValidates register's address for programming boolean counters for a particular platform.h]hZValidates register’s address for programming boolean counters for a particular platform.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhM_hj}Zubah}(h]h ]h"]h$]h&]uh1jhjaZubeh}(h]h ]h"]h$]h&]uh1j|hj|ZhM`hj^Zubj})}(ha``is_valid_mux_reg`` Validates register's address for programming mux for a particular platform. h](j)}(h``is_valid_mux_reg``h]j)}(hjZh]his_valid_mux_reg}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhMfhjZubj)}(hhh]h)}(hKValidates register's address for programming mux for a particular platform.h]hMValidates register’s address for programming mux for a particular platform.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhMehjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1j|hjZhMfhj^Zubj})}(hp``is_valid_flex_reg`` Validates register's address for programming flex EU filtering for a particular platform. h](j)}(h``is_valid_flex_reg``h]j)}(hjZh]his_valid_flex_reg}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhMlhjZubj)}(hhh]h)}(hYValidates register's address for programming flex EU filtering for a particular platform.h]h[Validates register’s address for programming flex EU filtering for a particular platform.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhMkhjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1j|hjZhMlhj^Zubj})}(h``enable_metric_set`` Selects and applies any MUX configuration to set up the Boolean and Custom (B/C) counters that are part of the counter reports being sampled. May apply system constraints such as disabling EU clock gating as required. h](j)}(h``enable_metric_set``h]j)}(hj[h]henable_metric_set}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhMthj[ubj)}(hhh]h)}(hSelects and applies any MUX configuration to set up the Boolean and Custom (B/C) counters that are part of the counter reports being sampled. May apply system constraints such as disabling EU clock gating as required.h]hSelects and applies any MUX configuration to set up the Boolean and Custom (B/C) counters that are part of the counter reports being sampled. May apply system constraints such as disabling EU clock gating as required.}(hj.[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhMqhj+[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j|hj*[hMthj^Zubj})}(hT``disable_metric_set`` Remove system constraints associated with using the OA unit. h](j)}(h``disable_metric_set``h]j)}(hjO[h]hdisable_metric_set}(hjQ[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM[ubah}(h]h ]h"]h$]h&]uh1jh`/var/lib/git/docbuild/linux/Documentation/gpu/i915:661: ./drivers/gpu/drm/i915/i915_perf_types.hhM{hjI[ubj)}(hhh]h)}(h^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:664: ./drivers/gpu/drm/i915/i915_perf.chM hj;^hhubah}(h]h ]h"]h$]h&]uh1j0hj\hhhj\hM ubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjV^jSjV^jTjUjVuh1j&hhhjYhNhNubjX)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915 perf stream ``struct drm_i915_perf_open_param *param`` The open parameters passed to `DRM_I915_PERF_OPEN` ``struct perf_open_properties *props`` The property state that configures stream (individually validated) **Description** While read_properties_unlocked() validates properties in isolation it doesn't ensure that the combination necessarily makes sense. At this point it has been determined that userspace wants a stream of OA metrics, but still we need to further validate the combined properties are OK. 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point it has been determined that userspace wants a stream of OA metrics, but still we need to further validate the combined properties are OK.}(hj__hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:664: ./drivers/gpu/drm/i915/i915_perf.chM hjZ^ubh)}(hIf the configuration makes sense then we can allocate memory for a circular OA buffer and apply the requested metric set configuration.h]hIf the configuration makes sense then we can allocate memory for a circular OA buffer and apply the requested metric set configuration.}(hjn_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:664: ./drivers/gpu/drm/i915/i915_perf.chM hjZ^ubh)}(h **Return**h]jb)}(hj_h]hReturn}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jahj}_ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:664: ./drivers/gpu/drm/i915/i915_perf.chM hjZ^ubh)}(h)zero on success or a negative error code.h]h)zero on success or a negative error code.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:664: ./drivers/gpu/drm/i915/i915_perf.chM hjZ^ubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjYhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"i915_oa_read (C function)c.i915_oa_readhNtauh1jhjYhhhNhNubj')}(hhh](j,)}(hbint i915_oa_read (struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h]j2)}(haint i915_oa_read(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h](j)}(hinth]hint}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:666: ./drivers/gpu/drm/i915/i915_perf.chMubji)}(h h]h }(hj_hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj_hhhj_hMubjz)}(h i915_oa_readh]j;)}(h i915_oa_readh]h i915_oa_read}(hj_hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj_ubah}(h]h ](jjeh"]h$]h&]jjuh1jyhj_hhhj_hMubj)}(hQ(struct i915_perf_stream *stream, char __user *buf, size_t count, size_t *offset)h](j)}(hstruct i915_perf_stream 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]jGah"]h$]h&]uh1j:hj`ubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetj`modnameN classnameNjXj[)}j^]j;`c.i915_oa_readasbuh1hhj`ubji)}(h h]h }(hj`hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj`ubj;)}(hcounth]hcount}(hj`hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj`ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj_ubj)}(hsize_t *offseth](h)}(hhh]j;)}(hsize_th]hsize_t}(hjahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjaubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjamodnameN classnameNjXj[)}j^]j;`c.i915_oa_readasbuh1hhj aubji)}(h h]h }(hj0ahhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj aubj)}(hjh]h*}(hj>ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj aubj;)}(hoffseth]hoffset}(hjKahhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj aubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj_ubeh}(h]h ]h"]h$]h&]jjuh1jhj_hhhj_hMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hj_hhhj_hMubah}(h]j_ah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hj_hMhj_hhubj1)}(hhh]h)}(h?just calls through to :c:type:`i915_oa_ops->read `h](hjust calls through to }(hjuahhhNhNubh)}(h):c:type:`i915_oa_ops->read `h]j)}(hjah]hi915_oa_ops->read}(hjahhhNhNubah}(h]h ](jjjRc-typeeh"]h$]h&]uh1jhj}aubah}(h]h ]h"]h$]h&]refdocj: refdomainjRreftypetype refexplicitrefwarnjXj[)}j^]j;`c.i915_oa_readasbjj i915_oa_opsuh1hhj_hMhjuaubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:666: ./drivers/gpu/drm/i915/i915_perf.chMhjrahhubah}(h]h ]h"]h$]h&]uh1j0hj_hhhj_hMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjajSjajTjUjVuh1j&hhhjYhNhNubjX)}(hX**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics ``char __user *buf`` destination buffer given by userspace ``size_t count`` the number of bytes userspace wants to read ``size_t *offset`` (inout): the current position for writing into **buf** **Description** Updates **offset** according to the number of bytes successfully copied into the userspace buffer. **Return** zero on success or a negative error codeh](h)}(h**Parameters**h]jb)}(hjah]h Parameters}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jahjaubah}(h]h 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hjYdubj)}(hhh]h)}(h)An i915 perf stream opened for OA metricsh]h)An i915 perf stream opened for OA metrics}(hjxdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjtdhM hjudubah}(h]h ]h"]h$]h&]uh1jhjYdubeh}(h]h ]h"]h$]h&]uh1j|hjtdhM hjVdubah}(h]h ]h"]h$]h&]uh1jwhj:dubh)}(h**Description**h]jb)}(hjdh]h Description}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjdubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:668: ./drivers/gpu/drm/i915/i915_perf.chM hj:dubh)}(h[Re]enables hardware periodic sampling according to the period configured when opening the stream. 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]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:674: ./drivers/gpu/drm/i915/i915_perf.chMhjsjubj)}(hhh]h)}(hpoll() state tableh]hpoll() state table}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMhjjubah}(h]h ]h"]h$]h&]uh1jhjsjubeh}(h]h ]h"]h$]h&]uh1j|hjjhMhjiubeh}(h]h ]h"]h$]h&]uh1jwhjiubh)}(h**Description**h]jb)}(hjjh]h Description}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:674: ./drivers/gpu/drm/i915/i915_perf.chMhjiubh)}(hFor handling userspace polling on an i915 perf stream opened for OA metrics, this starts a poll_wait with the wait queue that our hrtimer callback wakes when it sees data ready to read in the circular OA buffer.h]hFor handling userspace polling on an i915 perf stream opened for OA metrics, this starts a poll_wait with the wait queue that our hrtimer callback wakes when it sees data ready to read in the circular OA buffer.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:674: ./drivers/gpu/drm/i915/i915_perf.chMhjiubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjYhhhNhNubeh}(h])i915-perf-observation-architecture-streamah ]h"])i915 perf observation architecture streamah$]h&]uh1hhj#hhhhhMubh)}(hhh](h)}(hOther i915 Perf Internalsh]hOther i915 Perf Internals}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhhhhhMubh)}(hThis section simply includes all other currently documented i915 perf internals, in no particular order, but may include some more minor utilities or platform specific details than found in the more high-level sections.h]hThis section simply includes all other currently documented i915 perf internals, in no particular order, but may include some more minor utilities or platform specific details than found in the more high-level sections.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"perf_open_properties (C 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*streamh](j)}(hjh]hstruct}(hj.ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*oubji)}(h h]h }(hj;ohhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj*oubh)}(hhh]j;)}(hi915_perf_streamh]hi915_perf_stream}(hjLohhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjIoubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjNomodnameN classnameNjXj[)}j^]ja)}jTjosbc.oa_buffer_check_unlockedasbuh1hhj*oubji)}(h h]h }(hjlohhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhj*oubj)}(hjh]h*}(hjzohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*oubj;)}(hstreamh]hstream}(hjohhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hj*oubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj&oubah}(h]h ]h"]h$]h&]jjuh1jhjnhhhjnhMubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjnhhhjnhMubah}(h]jnah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjnhMhjnhhubj1)}(hhh]h)}(h(check for data and update tail ptr stateh]h(check for data and update tail ptr state}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMhjohhubah}(h]h ]h"]h$]h&]uh1j0hjnhhhjnhMubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjojSjojTjUjVuh1j&hhhjjhNhNubjX)}(hX**Parameters** ``struct i915_perf_stream *stream`` i915 stream instance **Description** This is either called via fops (for blocking reads in user ctx) or the poll check hrtimer (atomic ctx) to check the OA buffer tail pointer and check if there is data available for userspace to read. This function is central to providing a workaround for the OA unit tail pointer having a race with respect to what data is visible to the CPU. It is responsible for reading tail pointers from the hardware and giving the pointers time to 'age' before they are made available for reading. (See description of OA_TAIL_MARGIN_NSEC above for further details.) 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(See description of OA_TAIL_MARGIN_NSEC above for further details.)}(hjRphhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMhjoubh)}(hzBesides returning true when there is data available to read() this function also updates the tail in the oa_buffer object.h]hzBesides returning true when there is data available to read() this function also updates the tail in the oa_buffer object.}(hjaphhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMhjoubh)}(h**Note**h]jb)}(hjrph]hNote}(hjtphhhNhNubah}(h]h ]h"]h$]h&]uh1jahjppubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMhjoubh)}(hIt's safe to read OA config state here unlocked, assuming that this is only called while the stream is enabled, while the global OA configuration can't be modified.h]hIt’s safe to read OA config state here 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classnameNjXj[)}j^]jqqc.append_oa_statusasbuh1hhjrubji)}(h h]h }(hjrhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjrubj;)}(htypeh]htype}(hjrhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjrubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj/qubeh}(h]h ]h"]h$]h&]jjuh1jhjphhhjqhMeubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjphhhjqhMeubah}(h]jpah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjqhMehjphhubj1)}(hhh]h)}(h5Appends a status record to a userspace read() buffer.h]h5Appends a status record to a userspace read() buffer.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMehj shhubah}(h]h ]h"]h$]h&]uh1j0hjphhhjqhMeubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRj&sjSj&sjTjUjVuh1j&hhhjjhNhNubjX)}(hXn**Parameters** ``struct i915_perf_stream *stream`` An i915-perf stream opened for OA metrics ``char __user *buf`` destination buffer given by userspace ``size_t count`` the number of bytes userspace wants to read ``size_t *offset`` (inout): the current position for writing into **buf** ``enum drm_i915_perf_record_type type`` The kind of status to report to userspace **Description** Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`) into the userspace read() buffer. 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Returns -EINVAL for an unknown ioctl request.h](h)}(h**Parameters**h]jb)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj}ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMBhjyubjx)}(hhh](j})}(h8``struct i915_perf_stream *stream`` An i915 perf stream h](j)}(h#``struct i915_perf_stream *stream``h]j)}(hjh]hstruct i915_perf_stream *stream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chM?hjubj)}(hhh]h)}(hAn i915 perf streamh]hAn i915 perf stream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM?hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhM?hjubj})}(h'``unsigned int cmd`` the ioctl request h](j)}(h``unsigned int cmd``h]j)}(hj׌h]hunsigned int cmd}(hjٌhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjՌubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chM@hjьubj)}(hhh]h)}(hthe ioctl requesth]hthe ioctl request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM@hjubah}(h]h ]h"]h$]h&]uh1jhjьubeh}(h]h ]h"]h$]h&]uh1j|hjhM@hjubj})}(h%``unsigned long arg`` the ioctl data h](j)}(h``unsigned long arg``h]j)}(hjh]hunsigned long arg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMAhj ubj)}(hhh]h)}(hthe ioctl datah]hthe ioctl data}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMAhj&ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j|hj%hMAhjubeh}(h]h ]h"]h$]h&]uh1jwhjyubh)}(h **Return**h]jb)}(hjKh]hReturn}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjIubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMChjyubh)}(hWzero on success or a negative error code. Returns -EINVAL for an unknown ioctl request.h]hWzero on success or a negative error code. Returns -EINVAL for an unknown ioctl request.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMChjyubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"$i915_perf_ioctl_version (C function)c.i915_perf_ioctl_versionhNtauh1jhjjhhhNhNubj')}(hhh](j,)}(h;int i915_perf_ioctl_version (struct drm_i915_private *i915)h]j2)}(h:int i915_perf_ioctl_version(struct drm_i915_private *i915)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMjubji)}(h h]h }(hjhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjhhhjhMjubjz)}(hi915_perf_ioctl_versionh]j;)}(hi915_perf_ioctl_versionh]hi915_perf_ioctl_version}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ](jjeh"]h$]h&]jjuh1jyhjhhhjhMjubj)}(h(struct drm_i915_private *i915)h]j)}(hstruct drm_i915_private *i915h](j)}(hjh]hstruct}(hj͍hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjɍubji)}(h h]h }(hjڍhhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjɍubh)}(hhh]j;)}(hdrm_i915_privateh]hdrm_i915_private}(hjhhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjubah}(h]h ]h"]h$]h&] refdomainjRreftypejT reftargetjmodnameN classnameNjXj[)}j^]ja)}jTjsbc.i915_perf_ioctl_versionasbuh1hhjɍubji)}(h h]h }(hj hhhNhNubah}(h]h ]juah"]h$]h&]uh1jhhjɍubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjɍubj;)}(hi915h]hi915}(hj&hhhNhNubah}(h]h ]jGah"]h$]h&]uh1j:hjɍubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjōubah}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMjubeh}(h]h ]h"]h$]h&]jjj"uh1j1j#j$hjhhhjhMjubah}(h]jah ](j(j)eh"]h$]h&]j-j.)j/huh1j+hjhMjhjhhubj1)}(hhh]h)}(h"Version of the i915-perf subsystemh]h"Version of the i915-perf subsystem}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMjhjMhhubah}(h]h ]h"]h$]h&]uh1j0hjhhhjhMjubeh}(h]h ](jRfunctioneh"]h$]h&]jQjRjRjhjSjhjTjUjVuh1j&hhhjjhNhNubjX)}(h**Parameters** ``struct drm_i915_private *i915`` The i915 device **Description** This version number is used by userspace to detect available features.h](h)}(h**Parameters**h]jb)}(hjrh]h Parameters}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jahjpubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMnhjlubjx)}(hhh]j})}(h2``struct drm_i915_private *i915`` The i915 device h](j)}(h!``struct drm_i915_private *i915``h]j)}(hjh]hstruct drm_i915_private *i915}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMkhjubj)}(hhh]h)}(hThe i915 deviceh]hThe i915 device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMkhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j|hjhMkhjubah}(h]h ]h"]h$]h&]uh1jwhjlubh)}(h**Description**h]jb)}(hj̎h]h Description}(hjΎhhhNhNubah}(h]h ]h"]h$]h&]uh1jahjʎubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMmhjlubh)}(hFThis version number is used by userspace to detect available features.h]hFThis version number is used by userspace to detect available features.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/i915:684: ./drivers/gpu/drm/i915/i915_perf.chMmhjlubeh}(h]h ] kernelindentah"]h$]h&]uh1jWhjjhhhNhNubeh}(h]other-i915-perf-internalsah ]h"]other i915 perf internalsah$]h&]uh1hhj#hhhhhMubeh}(h]perfah ]h"]perfah$]h&]uh1hhhhhhhhMQubh)}(hhh](h)}(hStyleh]hStyle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h~The drm/i915 driver codebase has some style rules in addition to (and, in some cases, deviating from) the kernel coding style.h]h~The drm/i915 driver codebase has some style rules in addition to (and, in some cases, deviating from) the kernel coding style.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hRegister macro definition styleh]hRegister macro definition style}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhMubh)}(h#The style guide for ``i915_reg.h``.h](hThe style guide for }(hj8hhhNhNubj)}(h``i915_reg.h``h]h i915_reg.h}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj'hhubh)}(hFollow the style described here for new macros, and while changing existing macros. Do **not** mass change existing definitions just to update the style.h](hWFollow the style described here for new macros, and while changing existing macros. Do }(hjXhhhNhNubjb)}(h**not**h]hnot}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jahjXubh; mass change existing definitions just to update the style.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK hj'hhubh)}(hhh](h)}(h File Layouth]h File Layout}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhNhNubh)}(hBKeep helper macros near the top. For example, _PIPE() and friends.h]hBKeep helper macros near the top. For example, _PIPE() and friends.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK&hjyubh)}(hPrefix macros that generally should not be used outside of this file with underscore '_'. For example, _PIPE() and friends, single instances of registers that are defined solely for the use by function-like macros.h]hPrefix macros that generally should not be used outside of this file with underscore ‘_’. For example, _PIPE() and friends, single instances of registers that are defined solely for the use by function-like macros.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK(hjyubh)}(hrAvoid using the underscore prefixed macros outside of this file. There are exceptions, but keep them to a minimum.h]hrAvoid using the underscore prefixed macros outside of this file. There are exceptions, but keep them to a minimum.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK,hjyubh)}(hXThere are two basic types of register definitions: Single registers and register groups. Register groups are registers which have two or more instances, for example one per pipe, port, transcoder, etc. Register groups should be defined using function-like macros.h]hXThere are two basic types of register definitions: Single registers and register groups. Register groups are registers which have two or more instances, for example one per pipe, port, transcoder, etc. Register groups should be defined using function-like macros.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK/hjyubh)}(hVFor single registers, define the register offset first, followed by register contents.h]hVFor single registers, define the register offset first, followed by register contents.}(hjƏhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK4hjyubh)}(hFor register groups, define the register instance offsets first, prefixed with underscore, followed by a function-like macro choosing the right instance based on the parameter, followed by register contents.h]hFor register groups, define the register instance offsets first, prefixed with underscore, followed by a function-like macro choosing the right instance based on the parameter, followed by register contents.}(hjՏhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK7hjyubh)}(hDefine the register contents (i.e. bit and bit field macros) from most significant to least significant bit. Indent the register content macros using two extra spaces between ``#define`` and the macro name.h](hDefine the register contents (i.e. bit and bit field macros) from most significant to least significant bit. Indent the register content macros using two extra spaces between }(hjhhhNhNubj)}(h ``#define``h]h#define}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and the macro name.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK;hjyubh)}(hXnDefine bit fields using ``REG_GENMASK(h, l)``. Define bit field contents using ``REG_FIELD_PREP(mask, value)``. This will define the values already shifted in place, so they can be directly OR'd together. For convenience, function-like macros may be used to define bit fields, but do note that the macros may be needed to read as well as write the register contents.h](hDefine bit fields using }(hjhhhNhNubj)}(h``REG_GENMASK(h, l)``h]hREG_GENMASK(h, l)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh". Define bit field contents using }(hjhhhNhNubj)}(h``REG_FIELD_PREP(mask, value)``h]hREG_FIELD_PREP(mask, value)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX. This will define the values already shifted in place, so they can be directly OR’d together. For convenience, function-like macros may be used to define bit fields, but do note that the macros may be needed to read as well as write the register contents.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK?hjyubh)}(hMDefine bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.h](hDefine bits using }(hj8hhhNhNubj)}(h``REG_BIT(N)``h]h REG_BIT(N)}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh. Do }(hj8hhhNhNubjb)}(h**not**h]hnot}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jahj8ubh add }(hj8hhhNhNubj)}(h``_BIT``h]h_BIT}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh suffix to the name.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhKEhjyubh)}(hGroup the register and its contents together without blank lines, separate from other registers and their contents with one blank line.h]hGroup the register and its contents together without blank lines, separate from other registers and their contents with one blank line.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhKGhjyubh)}(hX Indent macro values from macro names using TABs. Align values vertically. Use braces in macro values as needed to avoid unintended precedence after macro substitution. Use spaces in macro values according to kernel coding style. Use lower case in hexadecimal values.h]hX Indent macro values from macro names using TABs. Align values vertically. Use braces in macro values as needed to avoid unintended precedence after macro substitution. Use spaces in macro values according to kernel coding style. Use lower case in hexadecimal values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhKJhjyubeh}(h] file-layoutah ]h"] file layoutah$]h&]uh1hhj'hhhNhNubh)}(hhh](h)}(hNamingh]hNaming}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhNhNubh)}(hTry to name registers according to the specs. If the register name changes in the specs from platform to another, stick to the original name.h]hTry to name registers according to the specs. If the register name changes in the specs from platform to another, stick to the original name.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhKRhjubh)}(hTry to reuse existing register macro definitions. Only add new macros for new register offsets, or when the register contents have changed enough to warrant a full redefinition.h]hTry to reuse existing register macro definitions. Only add new macros for new register offsets, or when the register contents have changed enough to warrant a full redefinition.}(hjÐhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhKUhjubh)}(hWhen a register macro changes for a new platform, prefix the new macro using the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The prefix signifies the start platform/generation using the register.h](h~When a register macro changes for a new platform, prefix the new macro using the platform acronym or generation. For example, }(hjҐhhhNhNubj)}(h``SKL_``h]hSKL_}(hjڐhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjҐubh or }(hjҐhhhNhNubj)}(h ``GEN8_``h]hGEN8_}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjҐubhH. The prefix signifies the start platform/generation using the register.}(hjҐhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhKYhjubh)}(hWhen a bit (field) macro changes or gets added for a new platform, while retaining the existing register macro, add a platform acronym or generation suffix to the name. For example, ``_SKL`` or ``_GEN8``.h](hWhen a bit (field) macro changes or gets added for a new platform, while retaining the existing register macro, add a platform acronym or generation suffix to the name. For example, }(hjhhhNhNubj)}(h``_SKL``h]h_SKL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh or }(hjhhhNhNubj)}(h ``_GEN8``h]h_GEN8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhK]hjubeh}(h]namingah ]h"]namingah$]h&]uh1hhj'hhhNhNubh)}(hhh](h)}(hExamplesh]hExamples}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hNhNubh)}(h(Note that the values in the example are indented using spaces instead of TABs to avoid misalignment in generated documentation. Use TABs in the definitions.)::h]h(Note that the values in the example are indented using spaces instead of TABs to avoid misalignment in generated documentation. Use TABs in the definitions.):}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhKdhj@ubj")}(hX6#define _FOO_A 0xf000 #define _FOO_B 0xf001 #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) #define FOO_ENABLE REG_BIT(31) #define FOO_MODE_MASK REG_GENMASK(19, 16) #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) #define BAR _MMIO(0xb000) #define GEN8_BAR _MMIO(0xb888)h]hX6#define _FOO_A 0xf000 #define _FOO_B 0xf001 #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) #define FOO_ENABLE REG_BIT(31) #define FOO_MODE_MASK REG_GENMASK(19, 16) #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) #define BAR _MMIO(0xb000) #define GEN8_BAR _MMIO(0xb888)}hj`sbah}(h]h ]h"]h$]h&]jjuh1j"hY/var/lib/git/docbuild/linux/Documentation/gpu/i915:719: ./drivers/gpu/drm/i915/i915_reg.hhKhhj@ubeh}(h]examplesah ]h"]examplesah$]h&]uh1hhj'hhhNhNubj)}(h.. _i915-usage-stats:h]h}(h]h ]h"]h$]h&]j:i915-usage-statsuh1jhMhj'hhhhubeh}(h]register-macro-definition-styleah ]h"]register macro definition styleah$]h&]uh1hhjhhhhhMubeh}(h]styleah ]h"]styleah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h*i915 DRM client usage stats implementationh]h*i915 DRM client usage stats implementation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hwThe drm/i915 driver implements the DRM client usage stats specification as documented in :ref:`drm-client-usage-stats`.h](hYThe drm/i915 driver implements the DRM client usage stats specification as documented in }(hjhhhNhNubh)}(h:ref:`drm-client-usage-stats`h]hinline)}(hjh]hdrm-client-usage-stats}(hjhhhNhNubah}(h]h ](jjstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj: refdomainjreftyperef refexplicitrefwarnjjdrm-client-usage-statsuh1hhhhMhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(htExample of the output showing the implemented key value pairs and entirety of the currently possible format options:h]htExample of the output showing the implemented key value pairs and entirety of the currently possible format options:}(hjבhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj")}(hXpos: 0 flags: 0100002 mnt_id: 21 drm-driver: i915 drm-pdev: 0000:00:02.0 drm-client-id: 7 drm-engine-render: 9288864723 ns drm-engine-copy: 2035071108 ns drm-engine-video: 0 ns drm-engine-capacity-video: 2 drm-engine-video-enhance: 0 nsh]hXpos: 0 flags: 0100002 mnt_id: 21 drm-driver: i915 drm-pdev: 0000:00:02.0 drm-client-id: 7 drm-engine-render: 9288864723 ns drm-engine-copy: 2035071108 ns drm-engine-video: 0 ns drm-engine-capacity-video: 2 drm-engine-video-enhance: 0 ns}hjsbah}(h]h ]h"]h$]h&]jjuh1j"hhhMhjhhubh)}(hTPossible `drm-engine-` key names are: `render`, `copy`, `video` and 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Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`lineKusourcek/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.huh1jEhjubjF)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`lineKsourcek/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.huh1jEhjubjF)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`lineKsourcek/var/lib/git/docbuild/linux/Documentation/gpu/i915:547: ./drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.huh1jEhjubjF)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjדhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjԓubah}(h]h ]h"]h$]h&]levelKtypej`lineK*sourceu/var/lib/git/docbuild/linux/Documentation/gpu/i915:548: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.huh1jEhjubjF)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`lineK)sourcet/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.huh1jEhj5 ubjF)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]levelKtypej`lineKMsourcet/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.huh1jEhjP ubjF)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubah}(h]h ]h"]h$]h&]levelKtypej`lineKlsourcet/var/lib/git/docbuild/linux/Documentation/gpu/i915:549: ./drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.huh1jEhjubjF)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDubah}(h]h ]h"]h$]h&]levelKtypej`lineKsourceg/var/lib/git/docbuild/linux/Documentation/gpu/i915:551: ./drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.huh1jEhjubetransform_messages](jF)}(hhh]h)}(hhh]hFHyperlink target "guc_hxg_retry_reason_unspecified" is not referenced.}hjesbah}(h]h ]h"]h$]h&]uh1hhjbubah}(h]h ]h"]h$]h&]levelKtypej`sourcejlineKuh1jEubjF)}(hhh]h)}(hhh]hBHyperlink target "guc-mmio-based-communication" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhj|ubah}(h]h ]h"]h$]h&]levelKtypej`sourcej!lineKuh1jEubjF)}(hhh]h)}(hhh]h=Hyperlink target "guc_ctb_status_no_error" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`sourcejslineK"uh1jEubjF)}(hhh]h)}(hhh]h=Hyperlink target "guc_ctb_status_overflow" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`sourcejlineK#uh1jEubjF)}(hhh]h)}(hhh]h>Hyperlink target "guc_ctb_status_underflow" is not referenced.}hj͔sbah}(h]h ]h"]h$]h&]uh1hhjʔubah}(h]h ]h"]h$]h&]levelKtypej`sourcejlineK$uh1jEubjF)}(hhh]h)}(hhh]h=Hyperlink target "guc_ctb_status_mismatch" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`sourcejlineK%uh1jEubjF)}(hhh]h)}(hhh]h;Hyperlink target "guc_ctb_status_unused" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`sourcej lineK&uh1jEubjF)}(hhh]h)}(hhh]hBHyperlink target "guc_action_host2guc_self_cfg" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej`sourcejlineKuh1jEubjF)}(hhh]h)}(hhh]h:Hyperlink target "host2guc-control-ctb" is not referenced.}hj5sbah}(h]h ]h"]h$]h&]uh1hhj2ubah}(h]h ]h"]h$]h&]levelKtypej`sourcejMlineK+uh1jEubjF)}(hhh]h)}(hhh]hEHyperlink target "guc_action_host2guc_control_ctb" is not referenced.}hjOsbah}(h]h ]h"]h$]h&]uh1hhjLubah}(h]h ]h"]h$]h&]levelKtypej`sourcejtlineKKuh1jEubjF)}(hhh]h)}(hhh]h=Hyperlink target "guc_ctb_control_disable" is not referenced.}hjisbah}(h]h ]h"]h$]h&]uh1hhjfubah}(h]h ]h"]h$]h&]levelKtypej`sourcej4lineKOuh1jEubjF)}(hhh]h)}(hhh]huh1jEubjF)}(hhh]h)}(hhh]h6Hyperlink target "i915-usage-stats" is not referenced.}hj9sbah}(h]h ]h"]h$]h&]uh1hhj6ubah}(h]h ]h"]h$]h&]levelKtypej`sourcehlineMuh1jEube transformerN include_log] decorationNhhub.