sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget#/translations/zh_CN/gpu/driver-uapimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/zh_TW/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/it_IT/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ja_JP/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ko_KR/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/pt_BR/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/sp_SP/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hDRM Driver uAPIh]hDRM Driver uAPI}(hhhhhNhNubah}(h]h ]h"]h$]h&]refidid1uh1hhhhhh=/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi.rsthKubhtopic)}(h Contents h](h)}(hContentsh]hContents}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh bullet_list)}(hhh]h list_item)}(hhh](h paragraph)}(hhh]h reference)}(hhh]hDRM Driver uAPI}(hhhhhNhNubah}(h]hah ]h"]h$]h&]refiddrm-driver-uapiuh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]h drm/i915 uAPI}(hjhhhNhNubah}(h]id2ah ]h"]h$]h&]refid drm-i915-uapiuh1hhj ubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh](h)}(hhh]h)}(hhh]hdrm/nouveau uAPI}(hj2hhhNhNubah}(h]id3ah ]h"]h$]h&]refiddrm-nouveau-uapiuh1hhj/ubah}(h]h ]h"]h$]h&]uh1hhj,ubh)}(hhh]h)}(hhh]h)}(hhh]h)}(hhh]hVM_BIND / EXEC uAPI}(hjQhhhNhNubah}(h]id4ah ]h"]h$]h&]refidvm-bind-exec-uapiuh1hhjNubah}(h]h ]h"]h$]h&]uh1hhjKubah}(h]h ]h"]h$]h&]uh1hhjHubah}(h]h ]h"]h$]h&]uh1hhj,ubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hdrm/panthor uAPI}(hjhhhNhNubah}(h]id5ah ]h"]h$]h&]refiddrm-panthor-uapiuh1hhj|ubah}(h]h ]h"]h$]h&]uh1hhjyubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh](h)}(hhh]h)}(hhh]h drm/xe uAPI}(hjhhhNhNubah}(h]id6ah ]h"]h$]h&]refid drm-xe-uapiuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]hNode Registration}(hjhhhNhNubah}(h]id7ah ]h"]h$]h&]refidnode-registrationuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hError Classification}(hjhhhNhNubah}(h]id8ah ]h"]h$]h&]refiderror-classificationuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hUser Interface}(hjhhhNhNubah}(h]id9ah ]h"]h$]h&]refiduser-interfaceuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hdrm/asahi uAPI}(hj2hhhNhNubah}(h]id10ah ]h"]h$]h&]refiddrm-asahi-uapiuh1hhj/ubah}(h]h ]h"]h$]h&]uh1hhj,ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubeh}(h]contentsah ]contentsah"]contentsah$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(h drm/i915 uAPIh]h drm/i915 uAPI}(hjlhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjihhhhhKubhtarget)}(h1.. _uevents generated by i915 on its device node:h]h}(h]h ]h"]h$]h&]hʌ,uevents-generated-by-i915-on-its-device-nodeuh1jzhKhjihhhNubh)}(h0**uevents generated by i915 on its device node**h]hstrong)}(hjh]h,uevents generated by i915 on its device node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"],uevents generated by i915 on its device nodeah$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjihhexpect_referenced_by_name}jj|sexpect_referenced_by_id}jj|subhdefinition_list)}(hhh](hdefinition_list_item)}(hXI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch event from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1. h](hterm)}(hLI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatchh]hLI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhK.hjubh definition)}(hhh]h)}(hXQevent from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1.h]hXQevent from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK.hjubj)}(hXI915_ERROR_UEVENT - Generated upon error detection, currently only via hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen. h](j)}(hFI915_ERROR_UEVENT - Generated upon error detection, currently only viah]hFI915_ERROR_UEVENT - Generated upon error detection, currently only via}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhK5hjubj)}(hhh]h)}(hX?hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen.h]hX?hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhK1hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK5hjubj)}(hI915_RESET_UEVENT - Event is generated just before an attempt to reset the GPU. The value supplied with the event is always 1. NOTE: Disable reset via module parameter will cause this event to not be seen. h](j)}(hJI915_RESET_UEVENT - Event is generated just before an attempt to reset theh]hJI915_RESET_UEVENT - Event is generated just before an attempt to reset the}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1j~hjhhhhj}hK>ubh desc_name)}(hi915_user_extensionh]h desc_sig_name)}(hjdh]hi915_user_extension}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhhj}hK>ubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jfsphinx_line_type declaratorhjbhhhj}hK>ubah}(h]jYah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j`hj}hK>hj]hhubh desc_content)}(hhh]h)}(h-Base class for defining a chain of extensionsh]h-Base class for defining a chain of extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKBhjhhubah}(h]h ]h"]h$]h&]uh1jhj]hhhj}hK>ubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j[hhhjihNhNubh container)}(hX**Definition**:: struct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; }; **Members** ``next_extension`` Pointer to the next struct i915_user_extension, or zero if the end. ``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension. ``flags`` MBZ All undefined bits must be zero. ``rsvd`` MBZ Reserved for future use; must be zero.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKFhjubh literal_block)}(hmstruct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; };h]hmstruct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKHhjubh)}(h **Members**h]j)}(hj!h]hMembers}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKOhjubj)}(hhh](j)}(hW``next_extension`` Pointer to the next struct i915_user_extension, or zero if the end. h](j)}(h``next_extension``h]hliteral)}(hj@h]hnext_extension}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKihj:ubj)}(hhh]h)}(hCPointer to the next struct i915_user_extension, or zero if the end.h]hCPointer to the next struct i915_user_extension, or zero if the end.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhKihjXubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhjWhKihj7ubj)}(hX``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension. h](j)}(h``name``h]jC)}(hj{h]hname}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjyubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKuhjuubj)}(hhh](h)}(hName of the extension.h]hName of the extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKohjubh)}(h-Note that the name here is just some integer.h]h-Note that the name here is just some integer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKqhjubh)}(hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension.h]hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKshjubeh}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjhKuhj7ubj)}(h0``flags`` MBZ All undefined bits must be zero. h](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhK{hjubj)}(hhh](h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKyhjubh)}(h All undefined bits must be zero.h]h All undefined bits must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK{hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK{hj7ubj)}(h4``rsvd`` MBZ Reserved for future use; must be zero.h](j)}(h``rsvd``h]jC)}(hjh]hrsvd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh](h)}(hMBZh]hMBZ}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhj1ubh)}(h&Reserved for future use; must be zero.h]h&Reserved for future use; must be zero.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhj1ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj0hKhj7ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjmh]h Description}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjihhubh)}(hX5Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan's approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.h]hX7Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan’s approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKChjihhubh)}(hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.h]hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKIhjihhubh)}(hExample chaining:h]hExample chaining:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKOhjihhubj)}(hX)struct i915_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct i915_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct i915_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };h]hX)struct i915_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct i915_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct i915_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };}hjsbah}(h]h ]h"]h$]h&]jjforcelanguageChighlight_args}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKQhjihhubh)}(hTypically the struct i915_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.h]hTypically the struct i915_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhK`hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_i915_gem_engine_class (C enum)c.drm_i915_gem_engine_classhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_engine_classh]jg)}(henum drm_i915_gem_engine_classh](jm)}(henumh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKgubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhKgubj)}(hdrm_i915_gem_engine_classh]j)}(hjh]hdrm_i915_gem_engine_class}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKgubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhKgubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhKghjhhubj)}(hhh]h)}(huapi engine type enumerationh]huapi engine type enumeration}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhj,hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKgubeh}(h]h ](jenumeh"]h$]h&]jjjjGjjGjjjuh1j[hhhjihNhNubj)}(hXN**Constants** ``I915_ENGINE_CLASS_RENDER`` Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs). ``I915_ENGINE_CLASS_COPY`` Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data. ``I915_ENGINE_CLASS_VIDEO`` Video engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode. ``I915_ENGINE_CLASS_VIDEO_ENHANCE`` Video enhancement engines (also referred to as "vebox") support instructions related to image enhancement. ``I915_ENGINE_CLASS_COMPUTE`` Compute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline. ``I915_ENGINE_CLASS_INVALID`` Placeholder value to represent an invalid engine class assignment.h](h)}(h **Constants**h]j)}(hjQh]h Constants}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjKubj)}(hhh](j)}(hXK``I915_ENGINE_CLASS_RENDER`` Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs). h](j)}(h``I915_ENGINE_CLASS_RENDER``h]jC)}(hjph]hI915_ENGINE_CLASS_RENDER}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjnubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjjubj)}(hhh]h)}(hX-Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs).h]hX7Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called “kernels” or “shaders”) on the GPU’s execution units (EUs).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjgubj)}(hXL``I915_ENGINE_CLASS_COPY`` Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data. h](j)}(h``I915_ENGINE_CLASS_COPY``h]jC)}(hjh]hI915_ENGINE_CLASS_COPY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hX0Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data.h]hX4Copy engines (also referred to as “blitters”) support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjgubj)}(h``I915_ENGINE_CLASS_VIDEO`` Video engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode. h](j)}(h``I915_ENGINE_CLASS_VIDEO``h]jC)}(hjh]hI915_ENGINE_CLASS_VIDEO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hVideo engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode.h]hVideo engines (also referred to as “bit stream decode” (BSD) or “vdbox”) support instructions that perform fixed-function media decode and encode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjgubj)}(h``I915_ENGINE_CLASS_VIDEO_ENHANCE`` Video enhancement engines (also referred to as "vebox") support instructions related to image enhancement. h](j)}(h#``I915_ENGINE_CLASS_VIDEO_ENHANCE``h]jC)}(hjh]hI915_ENGINE_CLASS_VIDEO_ENHANCE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hjVideo enhancement engines (also referred to as "vebox") support instructions related to image enhancement.h]hnVideo enhancement engines (also referred to as “vebox”) support instructions related to image enhancement.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj3hKhjgubj)}(h``I915_ENGINE_CLASS_COMPUTE`` Compute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline. h](j)}(h``I915_ENGINE_CLASS_COMPUTE``h]jC)}(hjXh]hI915_ENGINE_CLASS_COMPUTE}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjVubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjRubj)}(hhh]h)}(hCompute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline.h]hCompute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjnubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jhjmhKhjgubj)}(h```I915_ENGINE_CLASS_INVALID`` Placeholder value to represent an invalid engine class assignment.h](j)}(h``I915_ENGINE_CLASS_INVALID``h]jC)}(hjh]hI915_ENGINE_CLASS_INVALID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hBPlaceholder value to represent an invalid engine class assignment.h]hBPlaceholder value to represent an invalid engine class assignment.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjgubeh}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjihhubh)}(hX-Different engines serve different roles, and there may be more than one engine serving each role. This enum provides a classification of the role of the engine, which may be used when requesting operations to be performed on a certain subset of engines, or for providing information about that group.h]hX-Different engines serve different roles, and there may be more than one engine serving each role. This enum provides a classification of the role of the engine, which may be used when requesting operations to be performed on a certain subset of engines, or for providing information about that group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%i915_engine_class_instance (C struct)c.i915_engine_class_instancehNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hi915_engine_class_instanceh]jg)}(h!struct i915_engine_class_instanceh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhj hKubj)}(hi915_engine_class_instanceh]j)}(hj h]hi915_engine_class_instance}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj hKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj hhhj hKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hj hKhjhhubj)}(hhh]h)}(h Engine class/instance identifierh]h Engine class/instance identifier}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjRhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjjmjjmjjjuh1j[hhhjihNhNubj)}(hXJ**Definition**:: struct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; }; **Members** ``engine_class`` Engine class from enum drm_i915_gem_engine_class ``engine_instance`` Engine instance.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubh:}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjqubj)}(hstruct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; };h]hstruct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjqubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjqubj)}(hhh](j)}(hB``engine_class`` Engine class from enum drm_i915_gem_engine_class h](j)}(h``engine_class``h]jC)}(hjh]h engine_class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(h0Engine class from enum drm_i915_gem_engine_classh]h0Engine class from enum drm_i915_gem_engine_class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h$``engine_instance`` Engine instance.h](j)}(h``engine_instance``h]jC)}(hjh]hengine_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hEngine instance.h]hEngine instance.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubeh}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj> h]h Description}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj< ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjihhubh)}(hX@There may be more than one engine fulfilling any role within the system. Each engine of a class is given a unique instance number and therefore any engine can be specified by its class:instance tuplet. APIs that allow access to any engine in the system will use struct i915_engine_class_instance for this identification.h]hX@There may be more than one engine fulfilling any role within the system. Each engine of a class is given a unique instance number and therefore any engine can be specified by its class:instance tuplet. APIs that allow access to any engine in the system will use struct i915_engine_class_instance for this identification.}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjihhubj{)}(hL.. _perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915:h]h}(h]h ]h"]h$]h&]hʌFperf-events-exposed-by-i915-through-sys-bus-event-sources-drivers-i915uh1jzhKhjihhhNubh)}(hK**perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915**h]j)}(hjp h]hGperf_events exposed by i915 through /sys/bus/event_sources/drivers/i915}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjn ubah}(h]jm ah ]h"]Gperf_events exposed by i915 through /sys/bus/event_sources/drivers/i915ah$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjihhj}j jc sj}jm jc subjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_i915_getparam (C struct)c.drm_i915_getparamhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_getparamh]jg)}(hstruct drm_i915_getparamh](jm)}(hjph]hstruct}(hj hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj hhhj hMubj)}(hdrm_i915_getparamh]j)}(hj h]hdrm_i915_getparam}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj hhhj hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j`hj hMhj hhubj)}(hhh]h)}(h!Driver parameter query structure.h]h!Driver parameter query structure.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM2hj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j[hhhjihNhNubj)}(hXN**Definition**:: struct drm_i915_getparam { __s32 param; int __user *value; }; **Members** ``param`` Driver parameter to query. ``value`` Address of memory where queried value should be put. WARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM6hj ubj)}(hEstruct drm_i915_getparam { __s32 param; int __user *value; };h]hEstruct drm_i915_getparam { __s32 param; int __user *value; };}hj! sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM8hj ubh)}(h **Members**h]j)}(hj2 h]hMembers}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0 ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM=hj ubj)}(hhh](j)}(h%``param`` Driver parameter to query. h](j)}(h ``param``h]jC)}(hjQ h]hparam}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjO ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM6hjK ubj)}(hhh]h)}(hDriver parameter to query.h]hDriver parameter to query.}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf hM6hjg ubah}(h]h ]h"]h$]h&]uh1jhjK ubeh}(h]h ]h"]h$]h&]uh1jhjf hM6hjH ubj)}(h``value`` Address of memory where queried value should be put. WARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h](j)}(h ``value``h]jC)}(hj h]hvalue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM<hj ubj)}(hhh](h)}(h4Address of memory where queried value should be put.h]h4Address of memory where queried value should be put.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM:hj ubh)}(hrWARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h]htWARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don’t repeat this mistake.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM<hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hM<hjH ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_i915_getparam_t (C type)c.drm_i915_getparam_thNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_getparam_th]jg)}(htype drm_i915_getparam_th](jm)}(htypeh]htype}(hj hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMCubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj hhhj hMCubj)}(hdrm_i915_getparam_th]j)}(hj h]hdrm_i915_getparam_t}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMCubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj hhhj hMCubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j`hj hMChj hhubj)}(hhh]h)}(h?Driver parameter query structure. See struct drm_i915_getparam.h]h?Driver parameter query structure. See struct drm_i915_getparam.}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMBhj2 hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMCubeh}(h]h ](jtypeeh"]h$]h&]jjjjM jjM jjjuh1j[hhhjihNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_i915_gem_mmap_offset (C struct)c.drm_i915_gem_mmap_offsethNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_mmap_offseth]jg)}(hstruct drm_i915_gem_mmap_offseth](jm)}(hjph]hstruct}(hjj hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjf hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMGubj)}(h h]h }(hjx hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjf hhhjw hMGubj)}(hdrm_i915_gem_mmap_offseth]j)}(hjd h]hdrm_i915_gem_mmap_offset}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjf hhhjw hMGubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjb hhhjw hMGubah}(h]j] ah ](jjeh"]h$]h&]jj)jhuh1j`hjw hMGhj_ hhubj)}(hhh]h)}(h5Retrieve an offset so we can mmap this buffer object.h]h5Retrieve an offset so we can mmap this buffer object.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhj_ hhhjw hMGubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j[hhhjihNhNubj)}(hXh**Definition**:: struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; }; **Members** ``handle`` Handle for the object being mapped. ``pad`` Must be zero ``offset`` The fake offset to use for subsequent mmap call This is a fixed-size type for 32/64 compatibility. ``flags`` Flags for extended behaviour. It is mandatory that one of the `MMAP_OFFSET` types should be included: - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid. As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise. ``extensions`` Zero-terminated chain of extensions. No current extensions defined; mbz.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubj)}(hX-struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; };h]hX-struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; };}hj sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubj)}(hhh](j)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]jC)}(hj h]hhandle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubj)}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj. hMhj/ ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj. hMhj ubj)}(h``pad`` Must be zero h](j)}(h``pad``h]jC)}(hjR h]hpad}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjP ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjL ubj)}(hhh]h)}(h Must be zeroh]h Must be zero}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjg hMhjh ubah}(h]h ]h"]h$]h&]uh1jhjL ubeh}(h]h ]h"]h$]h&]uh1jhjg hMhj ubj)}(ho``offset`` The fake offset to use for subsequent mmap call This is a fixed-size type for 32/64 compatibility. h](j)}(h ``offset``h]jC)}(hj h]hoffset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubj)}(hhh](h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubh)}(h2This is a fixed-size type for 32/64 compatibility.h]h2This is a fixed-size type for 32/64 compatibility.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubj)}(hX``flags`` Flags for extended behaviour. It is mandatory that one of the `MMAP_OFFSET` types should be included: - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid. As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise. h](j)}(h ``flags``h]jC)}(hj h]hflags}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubj)}(hhh](h)}(hFlags for extended behaviour.h]hFlags for extended behaviour.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubh)}(hGIt is mandatory that one of the `MMAP_OFFSET` types should be included:h](h It is mandatory that one of the }(hj hhhNhNubhtitle_reference)}(h `MMAP_OFFSET`h]h MMAP_OFFSET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubh types should be included:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubh)}(hhh](h)}(hO`I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)h]h)}(hj# h](j )}(h`I915_MMAP_OFFSET_GTT`h]hI915_MMAP_OFFSET_GTT}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj% ubh9: Use mmap with the object bound to GTT. (Write-Combined)}(hj% hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj! ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(h2`I915_MMAP_OFFSET_WC`: Use Write-Combined caching.h]h)}(hjI h](j )}(h`I915_MMAP_OFFSET_WC`h]hI915_MMAP_OFFSET_WC}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjK ubh: Use Write-Combined caching.}(hjK hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjG ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(h.`I915_MMAP_OFFSET_WB`: Use Write-Back caching.h]h)}(hjo h](j )}(h`I915_MMAP_OFFSET_WB`h]hI915_MMAP_OFFSET_WB}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjq ubh: Use Write-Back caching.}(hjq hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjm ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(hE`I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. h]h)}(hD`I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.h](j )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubh,: Use object placement to determine caching.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]bullet-uh1hhj@ hMhj ubh)}(hOn devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid.h](hOn devices with local memory }(hj hhhNhNubj )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubhW is the only valid type. On devices without local memory, this caching mode is invalid.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj ubh)}(hAs caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise.h](h As caching mode when specifying }(hj hhhNhNubj )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubh, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubj)}(hX``extensions`` Zero-terminated chain of extensions. No current extensions defined; mbz.h](j)}(h``extensions``h]jC)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh](h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj,ubh)}(h#No current extensions defined; mbz.h]h#No current extensions defined; mbz.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj,ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj+hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjhh]h Description}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM"hjihhubh)}(hThis struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, and is used to retrieve the fake offset to mmap an object specified by :c:type:`handle`.h](h)This struct is passed as argument to the }(hj~hhhNhNubj )}(h `DRM_IOCTL_I915_GEM_MMAP_OFFSET`h]hDRM_IOCTL_I915_GEM_MMAP_OFFSET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj~ubhO ioctl, and is used to retrieve the fake offset to mmap an object specified by }(hj~hhhNhNubh)}(h:c:type:`handle`h]jC)}(hjh]hhandle}(hjhhhNhNubah}(h]h ](xrefjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocgpu/driver-uapi refdomainjreftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sb reftargethandleuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj~ubh.}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjihhubh)}(hThe legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave as setting the :c:type:`extensions` to 0, and :c:type:`flags` to `I915_MMAP_OFFSET_GTT`.h](hThe legacy way of using }(hjhhhNhNubj )}(h`DRM_IOCTL_I915_GEM_MMAP`h]hDRM_IOCTL_I915_GEM_MMAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh is removed on gen12+. }(hjhhhNhNubj )}(h`DRM_IOCTL_I915_GEM_MMAP_GTT`h]hDRM_IOCTL_I915_GEM_MMAP_GTT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubhL is an older supported alias to this struct, but will behave as setting the }(hjhhhNhNubh)}(h:c:type:`extensions`h]jC)}(hjh]h extensions}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj extensionsuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh to 0, and }(hjhhhNhNubh)}(h:c:type:`flags`h]jC)}(hjh]hflags}(hj!hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjflagsuh1hhjhMhjubh to }(hjhhhNhNubj )}(h`I915_MMAP_OFFSET_GTT`h]hI915_MMAP_OFFSET_GTT}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_i915_gem_set_domain (C struct)c.drm_i915_gem_set_domainhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_set_domainh]jg)}(hstruct drm_i915_gem_set_domainh](jm)}(hjph]hstruct}(hjqhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjmhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjmhhhj~hMubj)}(hdrm_i915_gem_set_domainh]j)}(hjkh]hdrm_i915_gem_set_domain}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjmhhhj~hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjihhhj~hMubah}(h]jdah ](jjeh"]h$]h&]jj)jhuh1j`hj~hMhjfhhubj)}(hhh]h)}(hdAdjust the objects write or read domain, in preparation for accessing the pages via some CPU domain.h]hdAdjust the objects write or read domain, in preparation for accessing the pages via some CPU domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM$hjhhubah}(h]h ]h"]h$]h&]uh1jhjfhhhj~hMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjihNhNubj)}(hXo**Definition**:: struct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; }; **Members** ``handle`` Handle for the object. ``read_domains`` New read domains. ``write_domain`` New write domain. Note that having something in the write domain implies it's in the read domain, and only that read domain.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM(hjubj)}(hestruct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; };h]hestruct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM*hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM0hjubj)}(hhh](j)}(h"``handle`` Handle for the object. h](j)}(h ``handle``h]jC)}(hj h]hhandle}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMKhjubj)}(hhh]h)}(hHandle for the object.h]hHandle for the object.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMKhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5hMKhjubj)}(h#``read_domains`` New read domains. h](j)}(h``read_domains``h]jC)}(hjYh]h read_domains}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjWubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMNhjSubj)}(hhh]h)}(hNew read domains.h]hNew read domains.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMNhjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhjnhMNhjubj)}(h``write_domain`` New write domain. Note that having something in the write domain implies it's in the read domain, and only that read domain.h](j)}(h``write_domain``h]jC)}(hjh]h write_domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMThjubj)}(hhh](h)}(hNew write domain.h]hNew write domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMRhjubh)}(hjNote that having something in the write domain implies it's in the read domain, and only that read domain.h]hlNote that having something in the write domain implies it’s in the read domain, and only that read domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMThjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMThjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMXhjihhubh)}(hSpecifying a new write or read domain will flush the object out of the previous domain(if required), before then updating the objects domain tracking with the new domain.h]hSpecifying a new write or read domain will flush the object out of the previous domain(if required), before then updating the objects domain tracking with the new domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM%hjihhubh)}(hVNote this might involve waiting for the object first if it is still active on the GPU.h]hVNote this might involve waiting for the object first if it is still active on the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM)hjihhubh)}(h;Supported values for **read_domains** and **write_domain**:h](hSupported values for }(hjhhhNhNubj)}(h**read_domains**h]h read_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and }(hjhhhNhNubj)}(h**write_domain**h]h write_domain}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM,hjihhubh block_quote)}(h- I915_GEM_DOMAIN_WC: Uncached write-combined domain - I915_GEM_DOMAIN_CPU: CPU cache domain - I915_GEM_DOMAIN_GTT: Mappable aperture domain h]h)}(hhh](h)}(h2I915_GEM_DOMAIN_WC: Uncached write-combined domainh]h)}(hjUh]h2I915_GEM_DOMAIN_WC: Uncached write-combined domain}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM.hjSubah}(h]h ]h"]h$]h&]uh1hhjPubh)}(h%I915_GEM_DOMAIN_CPU: CPU cache domainh]h)}(hjmh]h%I915_GEM_DOMAIN_CPU: CPU cache domain}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM/hjkubah}(h]h ]h"]h$]h&]uh1hhjPubh)}(h.I915_GEM_DOMAIN_GTT: Mappable aperture domain h]h)}(h-I915_GEM_DOMAIN_GTT: Mappable aperture domainh]h-I915_GEM_DOMAIN_GTT: Mappable aperture domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM0hjubah}(h]h ]h"]h$]h&]uh1hhjPubeh}(h]h ]h"]h$]h&]j j uh1hhjdhM.hjLubah}(h]h ]h"]h$]h&]uh1jJhjdhM.hjihhubh)}(hAll other domains are rejected.h]hAll other domains are rejected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM2hjihhubh)}(hXINote that for discrete, starting from DG1, this is no longer supported, and is instead rejected. On such platforms the CPU domain is effectively static, where we also only support a single :c:type:`drm_i915_gem_mmap_offset` cache mode, which can't be set explicitly and instead depends on the object placements, as per the below.h](hNote that for discrete, starting from DG1, this is no longer supported, and is instead rejected. On such platforms the CPU domain is effectively static, where we also only support a single }(hjhhhNhNubh)}(h":c:type:`drm_i915_gem_mmap_offset`h]jC)}(hjh]hdrm_i915_gem_mmap_offset}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_gem_mmap_offsetuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM4hjubhl cache mode, which can’t be set explicitly and instead depends on the object placements, as per the below.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM4hjihhubh)}(h*Implicit caching rules, starting from DG1:h]h*Implicit caching rules, starting from DG1:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM:hjihhubjK)}(hXH- If any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. - Everything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]h)}(hhh](h)}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. h]h)}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.h](h%If any of the object placements (see }(hjhhhNhNubh)}(h0:c:type:`drm_i915_gem_create_ext_memory_regions`h]jC)}(hj h]h&drm_i915_gem_create_ext_memory_regions}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj&drm_i915_gem_create_ext_memory_regionsuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM<hjubhg) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj*hM<hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]h)}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.h]hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM@hj;ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j j uh1hhj*hM<hjubah}(h]h ]h"]h$]h&]uh1jJhj*hM<hjihhubh)}(hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new :c:type:`drm_i915_gem_create_ext` extension is probable.h](hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new }(hj`hhhNhNubh)}(h!:c:type:`drm_i915_gem_create_ext`h]jC)}(hjjh]hdrm_i915_gem_create_ext}(hjlhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjhubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_gem_create_extuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMChj`ubh extension is probable.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMChjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_i915_gem_exec_fence (C struct)c.drm_i915_gem_exec_fencehNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_exec_fenceh]jg)}(hstruct drm_i915_gem_exec_fenceh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMJubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMJubj)}(hdrm_i915_gem_exec_fenceh]j)}(hjh]hdrm_i915_gem_exec_fence}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMJubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMJubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMJhjhhubj)}(hhh]h)}(h/An input or output fence for the execbuf ioctl.h]h/An input or output fence for the execbuf ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM'hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMJubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); }; **Members** ``handle`` User's handle for a drm_syncobj to wait on or signal. ``flags`` Supported flags are: I915_EXEC_FENCE_WAIT: Wait for the input fence before request submission. I915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM+hj ubj)}(hstruct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); };h]hstruct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); };}hj*sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM-hj ubh)}(h **Members**h]j)}(hj;h]hMembers}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM5hj ubj)}(hhh](j)}(hA``handle`` User's handle for a drm_syncobj to wait on or signal. h](j)}(h ``handle``h]jC)}(hjZh]hhandle}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjXubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM1hjTubj)}(hhh]h)}(h5User's handle for a drm_syncobj to wait on or signal.h]h7User’s handle for a drm_syncobj to wait on or signal.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohM1hjpubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jhjohM1hjQubj)}(h``flags`` Supported flags are: I915_EXEC_FENCE_WAIT: Wait for the input fence before request submission. I915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM:hjubj)}(hhh](h)}(hSupported flags are:h]hSupported flags are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM5hjubh)}(hII915_EXEC_FENCE_WAIT: Wait for the input fence before request submission.h]hII915_EXEC_FENCE_WAIT: Wait for the input fence before request submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM7hjubh)}(hAI915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh]hAI915_EXEC_FENCE_SIGNAL: Return request completion fence as output}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM:hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM:hjQubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM>hjihhubh)}(hBThe request will wait for input fence to signal before submission.h]hBThe request will wait for input fence to signal before submission.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM(hjihhubh)}(hOThe returned output fence will be signaled after the completion of the request.h]hOThe returned output fence will be signaled after the completion of the request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM*hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW6drm_i915_gem_execbuffer_ext_timeline_fences (C struct)-c.drm_i915_gem_execbuffer_ext_timeline_fenceshNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(h+drm_i915_gem_execbuffer_ext_timeline_fencesh]jg)}(h2struct drm_i915_gem_execbuffer_ext_timeline_fencesh](jm)}(hjph]hstruct}(hj@hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj<hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM0ubj)}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj<hhhjMhM0ubj)}(h+drm_i915_gem_execbuffer_ext_timeline_fencesh]j)}(hj:h]h+drm_i915_gem_execbuffer_ext_timeline_fences}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj<hhhjMhM0ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj8hhhjMhM0ubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1j`hjMhM0hj5hhubj)}(hhh]h)}(h"Timeline fences for execbuf ioctl.h]h"Timeline fences for execbuf ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMChjhhubah}(h]h ]h"]h$]h&]uh1jhj5hhhjMhM0ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``fence_count`` Number of elements in the **handles_ptr** & **value_ptr** arrays. ``handles_ptr`` Pointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**. ``values_ptr`` Pointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMGhjubj)}(hstruct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; };h]hstruct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMIhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMQhjubj)}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]jC)}(hjh]hbase}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMMhjubj)}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMMhjubj)}(hR``fence_count`` Number of elements in the **handles_ptr** & **value_ptr** arrays. h](j)}(h``fence_count``h]jC)}(hj(h]h fence_count}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj&ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMRhj"ubj)}(hhh]h)}(hANumber of elements in the **handles_ptr** & **value_ptr** arrays.h](hNumber of elements in the }(hjAhhhNhNubj)}(h**handles_ptr**h]h handles_ptr}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh & }(hjAhhhNhNubj)}(h **value_ptr**h]h value_ptr}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh arrays.}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMQhj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj=hMRhjubj)}(ha``handles_ptr`` Pointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**. h](j)}(h``handles_ptr``h]jC)}(hjh]h handles_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMXhjubj)}(hhh]h)}(hPPointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**.h](h@Pointer to an array of struct drm_i915_gem_exec_fence of length }(hjhhhNhNubj)}(h**fence_count**h]h fence_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMXhjubj)}(h``values_ptr`` Pointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](j)}(h``values_ptr``h]jC)}(hjh]h values_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM`hjubj)}(hhh]h)}(hPointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](h,Pointer to an array of u64 values of length }(hjhhhNhNubj)}(h**fence_count**h]h fence_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM]hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM`hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj'h]h Description}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMdhjihhubh)}(hThis structure describes an array of drm_syncobj and associated points for timeline variants of drm_syncobj. It is invalid to append this structure to the execbuf if I915_EXEC_FENCE_ARRAY is set.h]hThis structure describes an array of drm_syncobj and associated points for timeline variants of drm_syncobj. It is invalid to append this structure to the execbuf if I915_EXEC_FENCE_ARRAY is set.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMDhjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_i915_gem_execbuffer2 (C struct)c.drm_i915_gem_execbuffer2hNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_execbuffer2h]jg)}(hstruct drm_i915_gem_execbuffer2h](jm)}(hjph]hstruct}(hjehhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjahhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMKubj)}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjahhhjrhMKubj)}(hdrm_i915_gem_execbuffer2h]j)}(hj_h]hdrm_i915_gem_execbuffer2}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjahhhjrhMKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj]hhhjrhMKubah}(h]jXah ](jjeh"]h$]h&]jj)jhuh1j`hjrhMKhjZhhubj)}(hhh]h)}(h-Structure for DRM_I915_GEM_EXECBUFFER2 ioctl.h]h-Structure for DRM_I915_GEM_EXECBUFFER2 ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMfhjhhubah}(h]h ]h"]h$]h&]uh1jhjZhhhjrhMKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjihNhNubj)}(hX **Definition**:: struct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; }; **Members** ``buffers_ptr`` Pointer to a list of gem_exec_object2 structs ``buffer_count`` Number of elements in **buffers_ptr** array ``batch_start_offset`` Offset in the batchbuffer to start execution from. ``batch_len`` Length in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size. ``DR1`` deprecated ``DR4`` deprecated ``num_cliprects`` See **cliprects_ptr** ``cliprects_ptr`` Kernel clipping was a DRI1 misfeature. It is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set. If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array. If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0. ``flags`` Execbuf flags ``rsvd1`` Context id ``rsvd2`` in and out sync_file file descriptors. When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input). When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMjhjubj)}(hXstruct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; };h]hXstruct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMlhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh](j)}(h>``buffers_ptr`` Pointer to a list of gem_exec_object2 structs h](j)}(h``buffers_ptr``h]jC)}(hjh]h buffers_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMkhjubj)}(hhh]h)}(h-Pointer to a list of gem_exec_object2 structsh]h-Pointer to a list of gem_exec_object2 structs}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hMkhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj)hMkhj ubj)}(h=``buffer_count`` Number of elements in **buffers_ptr** array h](j)}(h``buffer_count``h]jC)}(hjMh]h buffer_count}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjKubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMnhjGubj)}(hhh]h)}(h+Number of elements in **buffers_ptr** arrayh](hNumber of elements in }(hjfhhhNhNubj)}(h**buffers_ptr**h]h buffers_ptr}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubh array}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjbhMnhjcubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjbhMnhj ubj)}(hJ``batch_start_offset`` Offset in the batchbuffer to start execution from. h](j)}(h``batch_start_offset``h]jC)}(hjh]hbatch_start_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMshjubj)}(hhh]h)}(h2Offset in the batchbuffer to start execution from.h]h2Offset in the batchbuffer to start execution from.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMrhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMshj ubj)}(h``batch_len`` Length in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size. h](j)}(h ``batch_len``h]jC)}(hjh]h batch_len}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMzhjubj)}(hhh]h)}(hLength in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size.h](h7Length in bytes of the batch buffer, starting from the }(hjhhhNhNubj)}(h**batch_start_offset**h]hbatch_start_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh=. If 0, length is assumed to be the batch buffer object size.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMxhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMzhj ubj)}(h``DR1`` deprecated h](j)}(h``DR1``h]jC)}(hjh]hDR1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM~hjubj)}(hhh]h)}(h deprecatedh]h deprecated}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hM~hj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj3hM~hj ubj)}(h``DR4`` deprecated h](j)}(h``DR4``h]jC)}(hjWh]hDR4}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjUubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjQubj)}(hhh]h)}(h deprecatedh]h deprecated}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMhjmubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjlhMhj ubj)}(h(``num_cliprects`` See **cliprects_ptr** h](j)}(h``num_cliprects``h]jC)}(hjh]h num_cliprects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh]h)}(hSee **cliprects_ptr**h](hSee }(hjhhhNhNubj)}(h**cliprects_ptr**h]h cliprects_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(hX``cliprects_ptr`` Kernel clipping was a DRI1 misfeature. It is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set. If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array. If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0. h](j)}(h``cliprects_ptr``h]jC)}(hjh]h cliprects_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh](h)}(h&Kernel clipping was a DRI1 misfeature.h]h&Kernel clipping was a DRI1 misfeature.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh)}(hgIt is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set.h]hgIt is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh)}(hIf I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array.h](hGIf I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of }(hjhhhNhNubh)}(h!:c:type:`drm_i915_gem_exec_fence`h]jC)}(hjh]hdrm_i915_gem_exec_fence}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_gem_exec_fenceuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh and }(hjhhhNhNubj)}(h**num_cliprects**h]h num_cliprects}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh is the length of the array.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj5hMhjubh)}(h|If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0.h](hGIf I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single }(hjRhhhNhNubh)}(h:c:type:`i915_user_extension`h]jC)}(hj\h]hi915_user_extension}(hj^hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjZubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjji915_user_extensionuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjRubh and num_cliprects is 0.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjyhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h``flags`` Execbuf flags h](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh]h)}(h Execbuf flagsh]h Execbuf flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h``rsvd1`` Context id h](j)}(h ``rsvd1``h]jC)}(hjh]hrsvd1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh]h)}(h Context idh]h Context id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(hX'``rsvd2`` in and out sync_file file descriptors. When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input). When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h](j)}(h ``rsvd2``h]jC)}(hjh]hrsvd2}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh](h)}(h&in and out sync_file file descriptors.h]h&in and out sync_file file descriptors.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh)}(hWhen I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input).h]hWhen I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input).}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh)}(hnWhen I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h]hnWhen I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_i915_gem_caching (C struct)c.drm_i915_gem_cachinghNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_cachingh]jg)}(hstruct drm_i915_gem_cachingh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj{hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM!ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj{hhhjhM!ubj)}(hdrm_i915_gem_cachingh]j)}(hjyh]hdrm_i915_gem_caching}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj{hhhjhM!ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjwhhhjhM!ubah}(h]jrah ](jjeh"]h$]h&]jj)jhuh1j`hjhM!hjthhubj)}(hhh]h)}(h/Set or get the caching for given object handle.h]h/Set or get the caching for given object handle.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMlhjhhubah}(h]h ]h"]h$]h&]uh1jhjthhhjhM!ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; }; **Members** ``handle`` Handle of the buffer to set/get the caching level. ``caching`` The GTT caching level to apply or possible return value. The supported **caching** values: I915_CACHING_NONE: GPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent. I915_CACHING_CACHED: GPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT. I915_CACHING_DISPLAY: Special GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMphjubj)}(hstruct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; };h]hstruct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMrhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMzhjubj)}(hhh](j)}(h>``handle`` Handle of the buffer to set/get the caching level. h](j)}(h ``handle``h]jC)}(hj.h]hhandle}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj(ubj)}(hhh]h)}(h2Handle of the buffer to set/get the caching level.h]h2Handle of the buffer to set/get the caching level.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjChMhj%ubj)}(hXm``caching`` The GTT caching level to apply or possible return value. The supported **caching** values: I915_CACHING_NONE: GPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent. I915_CACHING_CACHED: GPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT. I915_CACHING_DISPLAY: Special GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h](j)}(h ``caching``h]jC)}(hjgh]hcaching}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjeubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjaubj)}(hhh](h)}(h8The GTT caching level to apply or possible return value.h]h8The GTT caching level to apply or possible return value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(h!The supported **caching** values:h](hThe supported }(hjhhhNhNubj)}(h **caching**h]hcaching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh values:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(hI915_CACHING_NONE:h]hI915_CACHING_NONE:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(hGPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent.h]hGPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(hI915_CACHING_CACHED:h]hI915_CACHING_CACHED:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(hGPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT.h]hGPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(hI915_CACHING_DISPLAY:h]hI915_CACHING_DISPLAY:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(hXSpecial GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h]hXSpecial GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj}ubeh}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj|hMhj%ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj%h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hX?Allow userspace to control the GTT caching bits for a given object when the object is later mapped through the ppGTT(or GGTT on older platforms lacking ppGTT support, or if the object is used for scanout). Note that this might require unbinding the object from the GTT first, if its current caching value doesn't match.h]hXAAllow userspace to control the GTT caching bits for a given object when the object is later mapped through the ppGTT(or GGTT on older platforms lacking ppGTT support, or if the object is used for scanout). Note that this might require unbinding the object from the GTT first, if its current caching value doesn’t match.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMmhjihhubh)}(hXNote that this all changes on discrete platforms, starting from DG1, the set/get caching is no longer supported, and is now rejected. Instead the CPU caching attributes(WB vs WC) will become an immutable creation time property for the object, along with the GTT caching level. For now we don't expose any new uAPI for this, instead on DG1 this is all implicit, although this largely shouldn't matter since DG1 is coherent by default(without any way of controlling it).h]hXNote that this all changes on discrete platforms, starting from DG1, the set/get caching is no longer supported, and is now rejected. Instead the CPU caching attributes(WB vs WC) will become an immutable creation time property for the object, along with the GTT caching level. For now we don’t expose any new uAPI for this, instead on DG1 this is all implicit, although this largely shouldn’t matter since DG1 is coherent by default(without any way of controlling it).}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMshjihhubh)}(h*Implicit caching rules, starting from DG1:h]h*Implicit caching rules, starting from DG1:}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM{hjihhubjK)}(hXH- If any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. - Everything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]h)}(hhh](h)}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. h]h)}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.h](h%If any of the object placements (see }(hjshhhNhNubh)}(h0:c:type:`drm_i915_gem_create_ext_memory_regions`h]jC)}(hj}h]h&drm_i915_gem_create_ext_memory_regions}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj{ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj&drm_i915_gem_create_ext_memory_regionsuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM}hjsubhg) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM}hjoubah}(h]h ]h"]h$]h&]uh1hhjlubh)}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]h)}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.h]hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjlubeh}(h]h ]h"]h$]h&]j j uh1hhjhM}hjhubah}(h]h ]h"]h$]h&]uh1jJhjhM}hjihhubh)}(hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new :c:type:`drm_i915_gem_create_ext` extension is probable.h](hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new }(hjhhhNhNubh)}(h!:c:type:`drm_i915_gem_create_ext`h]jC)}(hjh]hdrm_i915_gem_create_ext}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_gem_create_extuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh extension is probable.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjihhubh)}(hXSide note: Part of the reason for this is that changing the at-allocation-time CPU caching attributes for the pages might be required(and is expensive) if we need to then CPU map the pages later with different caching attributes. This inconsistent caching behaviour, while supported on x86, is not universally supported on other architectures. So for simplicity we opt for setting everything at creation time, whilst also making it immutable, on discrete platforms.h]hXSide note: Part of the reason for this is that changing the at-allocation-time CPU caching attributes for the pages might be required(and is expensive) if we need to then CPU map the pages later with different caching attributes. This inconsistent caching behaviour, while supported on x86, is not universally supported on other architectures. So for simplicity we opt for setting everything at creation time, whilst also making it immutable, on discrete platforms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW*drm_i915_gem_context_create_ext (C struct)!c.drm_i915_gem_context_create_exthNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_context_create_exth]jg)}(h&struct drm_i915_gem_context_create_exth](jm)}(hjph]hstruct}(hj*hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj&hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj&hhhj7hMubj)}(hdrm_i915_gem_context_create_exth]j)}(hj$h]hdrm_i915_gem_context_create_ext}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ](jjeh"]h$]h&]jjuh1jhj&hhhj7hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj"hhhj7hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hj7hMhjhhubj)}(hhh]h)}(h Structure for creating contexts.h]h Structure for creating contexts.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubah}(h]h ]h"]h$]h&]uh1jhjhhhj7hMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; }; **Members** ``ctx_id`` Id of the created context (output) ``flags`` Supported flags are: I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS: Extensions may be appended to this structure and driver must check for those. See **extensions**. I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE Created context will have single timeline. ``extensions`` Zero-terminated chain of extensions. I915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam. I915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hXstruct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; };h]hXstruct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh](j)}(h.``ctx_id`` Id of the created context (output) h](j)}(h ``ctx_id``h]jC)}(hjh]hctx_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh]h)}(h"Id of the created context (output)h]h"Id of the created context (output)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hX``flags`` Supported flags are: I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS: Extensions may be appended to this structure and driver must check for those. See **extensions**. I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE Created context will have single timeline. h](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubj)}(hhh](h)}(hSupported flags are:h]hSupported flags are:}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj(ubh)}(h)I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS:h]h)I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS:}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj(ubh)}(haExtensions may be appended to this structure and driver must check for those. See **extensions**.h](hRExtensions may be appended to this structure and driver must check for those. See }(hjIhhhNhNubj)}(h**extensions**h]h extensions}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubh.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj(ubh)}(h)I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINEh]h)I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj(ubh)}(h*Created context will have single timeline.h]h*Created context will have single timeline.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hMhj(ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhjubj)}(hXh``extensions`` Zero-terminated chain of extensions. I915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam. I915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h](j)}(h``extensions``h]jC)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh](h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam.h]hI915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h]hI915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_i915_gem_context_param (C struct)c.drm_i915_gem_context_paramhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_context_paramh]jg)}(h!struct drm_i915_gem_context_paramh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj hhhjhMubj)}(hdrm_i915_gem_context_paramh]j)}(hj h]hdrm_i915_gem_context_param}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj hhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(h"Context parameter to set or query.h]h"Context parameter to set or query.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjPhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjkjjkjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; }; **Members** ``ctx_id`` Context id ``size`` Size of the parameter **value** ``param`` Parameter to set or query ``value`` Context parameter value to be set or queriedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubh:}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjoubj)}(hXstruct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; };h]hXstruct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjoubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjoubj)}(hhh](j)}(h``ctx_id`` Context id h](j)}(h ``ctx_id``h]jC)}(hjh]hctx_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh]h)}(h Context idh]h Context id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h)``size`` Size of the parameter **value** h](j)}(h``size``h]jC)}(hjh]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh]h)}(hSize of the parameter **value**h](hSize of the parameter }(hj hhhNhNubj)}(h **value**h]hvalue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(h$``param`` Parameter to set or query h](j)}(h ``param``h]jC)}(hj@ h]hparam}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj> ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj: ubj)}(hhh]h)}(hParameter to set or queryh]hParameter to set or query}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU hMhjV ubah}(h]h ]h"]h$]h&]uh1jhj: ubeh}(h]h ]h"]h$]h&]uh1jhjU hMhjubj)}(h6``value`` Context parameter value to be set or queriedh](j)}(h ``value``h]jC)}(hjy h]hvalue}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjw ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjs ubj)}(hhh]h)}(h,Context parameter value to be set or queriedh]h,Context parameter value to be set or queried}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhjs ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubeh}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubj{)}(h.. _Virtual Engine uAPI:h]h}(h]h ]h"]h$]h&]hʌvirtual-engine-uapiuh1jzhMhjihhhNubh)}(h**Virtual Engine uAPI**h]j)}(hj h]hVirtual Engine uAPI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]j ah ]h"]virtual engine uapiah$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhj}j j sj}j j subh)}(hVirtual engine is a concept where userspace is able to configure a set of physical engines, submit a batch buffer, and let the driver execute it on any engine from the set as it sees fit.h]hVirtual engine is a concept where userspace is able to configure a set of physical engines, submit a batch buffer, and let the driver execute it on any engine from the set as it sees fit.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hThis is primarily useful on parts which have multiple instances of a same class engine, like for example GT3+ Skylake parts with their two VCS engines.h]hThis is primarily useful on parts which have multiple instances of a same class engine, like for example GT3+ Skylake parts with their two VCS engines.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hXFor instance userspace can enumerate all engines of a certain class using the previously described `Engine Discovery uAPI`_. After that userspace can create a GEM context with a placeholder slot for the virtual engine (using `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class and instance respectively) and finally using the `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in the same reserved slot.h](hcFor instance userspace can enumerate all engines of a certain class using the previously described }(hj hhhNhNubh)}(h`Engine Discovery uAPI`_h]hEngine Discovery uAPI}(hj!hhhNhNubah}(h]h ]h"]h$]h&]nameEngine Discovery uAPIhʌengine-discovery-uapiuh1hhj resolvedKubhf. After that userspace can create a GEM context with a placeholder slot for the virtual engine (using }(hj hhhNhNubj )}(h`I915_ENGINE_CLASS_INVALID`h]hI915_ENGINE_CLASS_INVALID}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubh and }(hj hhhNhNubj )}(h `I915_ENGINE_CLASS_INVALID_NONE`h]hI915_ENGINE_CLASS_INVALID_NONE}(hj.!hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubh< for class and instance respectively) and finally using the }(hj hhhNhNubj )}(h'`I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE`h]h%I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE}(hj@!hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj ubh< extension place a virtual engine in the same reserved slot.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hIExample of creating a virtual engine and submitting a batch buffer to it:h]hIExample of creating a virtual engine and submitting a batch buffer to it:}(hjY!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubj)}(hX(I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, .engine_index = 0, // Place this virtual engine into engine map slot 0 .num_siblings = 2, .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, { I915_ENGINE_CLASS_VIDEO, 1 }, }, }; I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { .engines = { { I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE } }, .extensions = to_user_pointer(&virtual), // Chains after load_balance extension }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // Now we have created a GEM context with its engine map containing a // single virtual engine. Submissions to this slot can go either to // vcs0 or vcs1, depending on the load balancing algorithm used inside // the driver. The load balancing is dynamic from one batch buffer to // another and transparent to userspace. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0 which is the virtual engine gem_execbuf(drm_fd, &execbuf);h]hX(I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, .engine_index = 0, // Place this virtual engine into engine map slot 0 .num_siblings = 2, .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, { I915_ENGINE_CLASS_VIDEO, 1 }, }, }; I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { .engines = { { I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE } }, .extensions = to_user_pointer(&virtual), // Chains after load_balance extension }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // Now we have created a GEM context with its engine map containing a // single virtual engine. Submissions to this slot can go either to // vcs0 or vcs1, depending on the load balancing algorithm used inside // the driver. The load balancing is dynamic from one batch buffer to // another and transparent to userspace. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0 which is the virtual engine gem_execbuf(drm_fd, &execbuf);}hjh!sbah}(h]h ]h"]h$]h&]jjjjjj}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW/i915_context_engines_parallel_submit (C struct)&c.i915_context_engines_parallel_submithNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(h$i915_context_engines_parallel_submith]jg)}(h+struct i915_context_engines_parallel_submith](jm)}(hjph]hstruct}(hj!hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj!hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj!hhhj!hMubj)}(h$i915_context_engines_parallel_submith]j)}(hj!h]h$i915_context_engines_parallel_submit}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj!hhhj!hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj!hhhj!hMubah}(h]j!ah ](jjeh"]h$]h&]jj)jhuh1j`hj!hMhj!hhubj)}(hhh]h)}(h)Configure engine for parallel submission.h]h)Configure engine for parallel submission.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhML hj!hhubah}(h]h ]h"]h$]h&]uh1jhj!hhhj!hMubeh}(h]h ](jstructeh"]h$]h&]jjjj!jj!jjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; }; **Members** ``base`` base user extension. ``engine_index`` slot for parallel engine ``width`` number of contexts per parallel engine or in other words the number of batches in each submission ``num_siblings`` number of siblings per context or in other words the number of possible placements for each submission ``mbz16`` reserved for future use; must be zero ``flags`` all undefined flags must be zero, currently not defined flags ``mbz64`` reserved for future use; must be zero ``engines`` 2-d array of engine instances to configure parallel engine length = width (i) * num_siblings (j) index = j + i * num_siblingsh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubh:}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMP hj!ubj)}(hstruct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; };h]hstruct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; };}hj"sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMR hj!ubh)}(h **Members**h]j)}(hj!"h]hMembers}(hj#"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM] hj!ubj)}(hhh](j)}(h``base`` base user extension. h](j)}(h``base``h]jC)}(hj@"h]hbase}(hjB"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>"ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj:"ubj)}(hhh]h)}(hbase user extension.h]hbase user extension.}(hjY"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU"hM hjV"ubah}(h]h ]h"]h$]h&]uh1jhj:"ubeh}(h]h ]h"]h$]h&]uh1jhjU"hM hj7"ubj)}(h*``engine_index`` slot for parallel engine h](j)}(h``engine_index``h]jC)}(hjy"h]h engine_index}(hj{"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjw"ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjs"ubj)}(hhh]h)}(hslot for parallel engineh]hslot for parallel engine}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1jhjs"ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hj7"ubj)}(hl``width`` number of contexts per parallel engine or in other words the number of batches in each submission h](j)}(h ``width``h]jC)}(hj"h]hwidth}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj"ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj"ubj)}(hhh]h)}(hanumber of contexts per parallel engine or in other words the number of batches in each submissionh]hanumber of contexts per parallel engine or in other words the number of batches in each submission}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hj7"ubj)}(hx``num_siblings`` number of siblings per context or in other words the number of possible placements for each submission h](j)}(h``num_siblings``h]jC)}(hj"h]h num_siblings}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj"ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj"ubj)}(hhh]h)}(hfnumber of siblings per context or in other words the number of possible placements for each submissionh]hfnumber of siblings per context or in other words the number of possible placements for each submission}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj#ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj#hM hj7"ubj)}(h0``mbz16`` reserved for future use; must be zero h](j)}(h ``mbz16``h]jC)}(hj&#h]hmbz16}(hj(#hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$#ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj #ubj)}(hhh]h)}(h%reserved for future use; must be zeroh]h%reserved for future use; must be zero}(hj?#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;#hM hj<#ubah}(h]h ]h"]h$]h&]uh1jhj #ubeh}(h]h ]h"]h$]h&]uh1jhj;#hM hj7"ubj)}(hH``flags`` all undefined flags must be zero, currently not defined flags h](j)}(h ``flags``h]jC)}(hj_#h]hflags}(hja#hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]#ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjY#ubj)}(hhh]h)}(h=all undefined flags must be zero, currently not defined flagsh]h=all undefined flags must be zero, currently not defined flags}(hjx#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt#hM hju#ubah}(h]h ]h"]h$]h&]uh1jhjY#ubeh}(h]h ]h"]h$]h&]uh1jhjt#hM hj7"ubj)}(h0``mbz64`` reserved for future use; must be zero h](j)}(h ``mbz64``h]jC)}(hj#h]hmbz64}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj#ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj#ubj)}(hhh]h)}(h%reserved for future use; must be zeroh]h%reserved for future use; must be zero}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hM hj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hM hj7"ubj)}(h``engines`` 2-d array of engine instances to configure parallel engine length = width (i) * num_siblings (j) index = j + i * num_siblingsh](j)}(h ``engines``h]jC)}(hj#h]hengines}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj#ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj#ubj)}(hhh](h)}(h:2-d array of engine instances to configure parallel engineh]h:2-d array of engine instances to configure parallel engine}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj#ubh)}(hBlength = width (i) * num_siblings (j) index = j + i * num_siblingsh]hBlength = width (i) * num_siblings (j) index = j + i * num_siblings}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hM hj#ubeh}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hM hj7"ubeh}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj"$h]h Description}(hj$$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj $ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hXOSetup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot's configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.h]hXSSetup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn’t tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot’s configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.}(hj8$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMM hjihhubh)}(hX9The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.h]hX9The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.}(hjG$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMV hjihhubh)}(hReturns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn't supported on the platform / submission interface. Returns -ENODEV if extension isn't supported on the platform / submission interface.h]hReturns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn’t supported on the platform / submission interface. Returns -ENODEV if extension isn’t supported on the platform / submission interface.}(hjV$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM_ hjihhubj)}(hX3Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1]) Results in the following valid placement: CS[0], CS[1] Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3]) Results in the following valid placements: CS[0], CS[1] CS[2], CS[3] This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3] Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3]) Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVALh]hX3Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1]) Results in the following valid placement: CS[0], CS[1] Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3]) Results in the following valid placements: CS[0], CS[1] CS[2], CS[3] This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3] Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3]) Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVAL}hje$sbah}(h]h ]h"]h$]h&]jjjjnonej}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMe hjihhubj{)}(h.. _Context Engine Map uAPI:h]h}(h]h ]h"]h$]h&]hʌcontext-engine-map-uapiuh1jzhMhjihhhNubh)}(h**Context Engine Map uAPI**h]j)}(hj$h]hContext Engine Map uAPI}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]j$ah ]h"]context engine map uapiah$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhj}j$jv$sj}j$jv$subh)}(hContext engine map is a new way of addressing engines when submitting batch- buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` inside the flags field of `struct drm_i915_gem_execbuffer2`.h](hContext engine map is a new way of addressing engines when submitting batch- buffers, replacing the existing way of using identifiers like }(hj$hhhNhNubj )}(h`I915_EXEC_BLT`h]h I915_EXEC_BLT}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj$ubh inside the flags field of }(hj$hhhNhNubj )}(h!`struct drm_i915_gem_execbuffer2`h]hstruct drm_i915_gem_execbuffer2}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj$ubh.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hTo use it created GEM contexts need to be configured with a list of engines the user is intending to submit to. This is accomplished using the `I915_CONTEXT_PARAM_ENGINES` parameter and `struct i915_context_param_engines`.h](hTo use it created GEM contexts need to be configured with a list of engines the user is intending to submit to. This is accomplished using the }(hj$hhhNhNubj )}(h`I915_CONTEXT_PARAM_ENGINES`h]hI915_CONTEXT_PARAM_ENGINES}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj$ubh parameter and }(hj$hhhNhNubj )}(h#`struct i915_context_param_engines`h]h!struct i915_context_param_engines}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj$ubh.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(h[For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the configured map.h](hFor such contexts the }(hj%hhhNhNubj )}(h`I915_EXEC_RING_MASK`h]hI915_EXEC_RING_MASK}(hj %hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj%ubh0 field becomes an index into the configured map.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(h;Example of creating such context and submitting against it:h]h;Example of creating such context and submitting against it:}(hj#%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubj)}(hX}I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, { I915_ENGINE_CLASS_COPY, 0 } } }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // We have now created a GEM context with two engines in the map: // Index 0 points to rcs0 while index 1 points to bcs0. Other engines // will not be accessible from this context. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context gem_execbuf(drm_fd, &execbuf); ... execbuf.rsvd1 = ctx_id; execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context gem_execbuf(drm_fd, &execbuf);h]hX}I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, { I915_ENGINE_CLASS_COPY, 0 } } }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // We have now created a GEM context with two engines in the map: // Index 0 points to rcs0 while index 1 points to bcs0. Other engines // will not be accessible from this context. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context gem_execbuf(drm_fd, &execbuf); ... execbuf.rsvd1 = ctx_id; execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context gem_execbuf(drm_fd, &execbuf);}hj2%sbah}(h]h ]h"]h$]h&]jjjjjj}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW3drm_i915_gem_context_create_ext_setparam (C struct)*c.drm_i915_gem_context_create_ext_setparamhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(h(drm_i915_gem_context_create_ext_setparamh]jg)}(h/struct drm_i915_gem_context_create_ext_setparamh](jm)}(hjph]hstruct}(hj[%hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjW%hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hji%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjW%hhhjh%hM ubj)}(h(drm_i915_gem_context_create_ext_setparamh]j)}(hjU%h]h(drm_i915_gem_context_create_ext_setparam}(hj{%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw%ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjW%hhhjh%hM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjS%hhhjh%hM ubah}(h]jN%ah ](jjeh"]h$]h&]jj)jhuh1j`hjh%hM hjP%hhubj)}(hhh]h)}(h:Context parameter to set or query during context creation.h]h:Context parameter to set or query during context creation.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM# hj%hhubah}(h]h ]h"]h$]h&]uh1jhjP%hhhjh%hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj%jj%jjjuh1j[hhhjihNhNubj)}(hXB**Definition**:: struct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``param`` Context parameter to set or query. See struct drm_i915_gem_context_param.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubh:}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM' hj%ubj)}(hstruct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; };h]hstruct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; };}hj%sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM) hj%ubh)}(h **Members**h]j)}(hj%h]hMembers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM. hj%ubj)}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]jC)}(hj &h]hbase}(hj &hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj&ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM( hj&ubj)}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hj#&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hM( hj &ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hM( hj&ubj)}(hS``param`` Context parameter to set or query. See struct drm_i915_gem_context_param.h](j)}(h ``param``h]jC)}(hjC&h]hparam}(hjE&hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjA&ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM, hj=&ubj)}(hhh]h)}(hIContext parameter to set or query. See struct drm_i915_gem_context_param.h]hIContext parameter to set or query. See struct drm_i915_gem_context_param.}(hj\&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjX&hM, hjY&ubah}(h]h ]h"]h$]h&]uh1jhj=&ubeh}(h]h ]h"]h$]h&]uh1jhjX&hM, hj&ubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_i915_gem_vm_control (C struct)c.drm_i915_gem_vm_controlhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_vm_controlh]jg)}(hstruct drm_i915_gem_vm_controlh](jm)}(hjph]hstruct}(hj&hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj&hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM3 ubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj&hhhj&hM3 ubj)}(hdrm_i915_gem_vm_controlh]j)}(hj&h]hdrm_i915_gem_vm_control}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj&hhhj&hM3 ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj&hhhj&hM3 ubah}(h]j&ah ](jjeh"]h$]h&]jj)jhuh1j`hj&hM3 hj&hhubj)}(hhh]h)}(h"Structure to create or destroy VM.h]h"Structure to create or destroy VM.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM7 hj&hhubah}(h]h ]h"]h$]h&]uh1jhj&hhhj&hM3 ubeh}(h]h ](jstructeh"]h$]h&]jjjj&jj&jjjuh1j[hhhjihNhNubj)}(hX&**Definition**:: struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; }; **Members** ``extensions`` Zero-terminated chain of extensions. ``flags`` reserved for future usage, currently MBZ ``vm_id`` Id of the VM created or to be destroyedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubh:}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM; hj&ubj)}(h[struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; };h]h[struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; };}hj'sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM= hj&ubh)}(h **Members**h]j)}(hj,'h]hMembers}(hj.'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*'ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMC hj&ubj)}(hhh](j)}(h4``extensions`` Zero-terminated chain of extensions. h](j)}(h``extensions``h]jC)}(hjK'h]h extensions}(hjM'hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjI'ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMM hjE'ubj)}(hhh]h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hjd'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`'hMM hja'ubah}(h]h ]h"]h$]h&]uh1jhjE'ubeh}(h]h ]h"]h$]h&]uh1jhj`'hMM hjB'ubj)}(h3``flags`` reserved for future usage, currently MBZ h](j)}(h ``flags``h]jC)}(hj'h]hflags}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj'ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMP hj~'ubj)}(hhh]h)}(h(reserved for future usage, currently MBZh]h(reserved for future usage, currently MBZ}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hMP hj'ubah}(h]h ]h"]h$]h&]uh1jhj~'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMP hjB'ubj)}(h1``vm_id`` Id of the VM created or to be destroyedh](j)}(h ``vm_id``h]jC)}(hj'h]hvm_id}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj'ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMR hj'ubj)}(hhh]h)}(h'Id of the VM created or to be destroyedh]h'Id of the VM created or to be destroyed}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMS hj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMR hjB'ubeh}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj(h]h Description}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMV hjihhubh)}(hDRM_I915_GEM_VM_CREATE -h]hDRM_I915_GEM_VM_CREATE -}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM8 hjihhubh)}(hCreate a new virtual memory address space (ppGTT) for use within a context on the same file. Extensions can be provided to configure exactly how the address space is setup upon creation.h]hCreate a new virtual memory address space (ppGTT) for use within a context on the same file. Extensions can be provided to configure exactly how the address space is setup upon creation.}(hj%(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM: hjihhubh)}(hiThe id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is returned in the outparam **id**.h](hbThe id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is returned in the outparam }(hj4(hhhNhNubj)}(h**id**h]hid}(hj<(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4(ubh.}(hj4(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM> hjihhubh)}(hAn extension chain maybe provided, starting with **extensions**, and terminated by the **next_extension** being 0. Currently, no extensions are defined.h](h1An extension chain maybe provided, starting with }(hjU(hhhNhNubj)}(h**extensions**h]h extensions}(hj](hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU(ubh, and terminated by the }(hjU(hhhNhNubj)}(h**next_extension**h]hnext_extension}(hjo(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU(ubh/ being 0. Currently, no extensions are defined.}(hjU(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMA hjihhubh)}(hDRM_I915_GEM_VM_DESTROY -h]hDRM_I915_GEM_VM_DESTROY -}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMD hjihhubh)}(h)ubj)}(hstruct drm_i915_gem_userptr { __u64 user_ptr; __u64 user_size; __u32 flags; #define I915_USERPTR_READ_ONLY 0x1; #define I915_USERPTR_PROBE 0x2; #define I915_USERPTR_UNSYNCHRONIZED 0x80000000; __u32 handle; };h]hstruct drm_i915_gem_userptr { __u64 user_ptr; __u64 user_size; __u32 flags; #define I915_USERPTR_READ_ONLY 0x1; #define I915_USERPTR_PROBE 0x2; #define I915_USERPTR_UNSYNCHRONIZED 0x80000000; __u32 handle; };}hj_)sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj>)ubh)}(h **Members**h]j)}(hjp)h]hMembers}(hjr)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjn)ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj>)ubj)}(hhh](j)}(hU``user_ptr`` The pointer to the allocated memory. Needs to be aligned to PAGE_SIZE. h](j)}(h ``user_ptr``h]jC)}(hj)h]huser_ptr}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj)ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj)ubj)}(hhh](h)}(h$The pointer to the allocated memory.h]h$The pointer to the allocated memory.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj)ubh)}(h!Needs to be aligned to PAGE_SIZE.h]h!Needs to be aligned to PAGE_SIZE.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hM hj)ubeh}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhj)hM hj)ubj)}(h``user_size`` The size in bytes for the allocated memory. This will also become the object size. Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, or larger. h](j)}(h ``user_size``h]jC)}(hj)h]h user_size}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj)ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj)ubj)}(hhh](h)}(hRThe size in bytes for the allocated memory. This will also become the object size.h]hRThe size in bytes for the allocated memory. This will also become the object size.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj)ubh)}(hNNeeds to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, or larger.h]hNNeeds to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, or larger.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj)ubeh}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhj)hM hj)ubj)}(hXv``flags`` Supported flags: I915_USERPTR_READ_ONLY: Mark the object as readonly, this also means GPU access can only be readonly. This is only supported on HW which supports readonly access through the GTT. If the HW can't support readonly access, an error is returned. I915_USERPTR_PROBE: Probe the provided **user_ptr** range and validate that the **user_ptr** is indeed pointing to normal memory and that the range is also valid. For example if some garbage address is given to the kernel, then this should complain. Returns -EFAULT if the probe failed. Note that this doesn't populate the backing pages, and also doesn't guarantee that the object will remain valid when the object is eventually used. The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE returns a non-zero value. I915_USERPTR_UNSYNCHRONIZED: NOT USED. Setting this flag will result in an error. h](j)}(h ``flags``h]jC)}(hj *h]hflags}(hj"*hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj*ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj*ubj)}(hhh](h)}(hSupported flags:h]hSupported flags:}(hj9*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(hI915_USERPTR_READ_ONLY:h]hI915_USERPTR_READ_ONLY:}(hjH*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(hMark the object as readonly, this also means GPU access can only be readonly. This is only supported on HW which supports readonly access through the GTT. If the HW can't support readonly access, an error is returned.h]hMark the object as readonly, this also means GPU access can only be readonly. This is only supported on HW which supports readonly access through the GTT. If the HW can’t support readonly access, an error is returned.}(hjW*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(hI915_USERPTR_PROBE:h]hI915_USERPTR_PROBE:}(hjf*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(hProbe the provided **user_ptr** range and validate that the **user_ptr** is indeed pointing to normal memory and that the range is also valid. For example if some garbage address is given to the kernel, then this should complain.h](hProbe the provided }(hju*hhhNhNubj)}(h **user_ptr**h]huser_ptr}(hj}*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju*ubh range and validate that the }(hju*hhhNhNubj)}(h **user_ptr**h]huser_ptr}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju*ubh is indeed pointing to normal memory and that the range is also valid. For example if some garbage address is given to the kernel, then this should complain.}(hju*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(h$Returns -EFAULT if the probe failed.h]h$Returns -EFAULT if the probe failed.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(hNote that this doesn't populate the backing pages, and also doesn't guarantee that the object will remain valid when the object is eventually used.h]hNote that this doesn’t populate the backing pages, and also doesn’t guarantee that the object will remain valid when the object is eventually used.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(hZThe kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE returns a non-zero value.h]hZThe kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE returns a non-zero value.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(hI915_USERPTR_UNSYNCHRONIZED:h]hI915_USERPTR_UNSYNCHRONIZED:}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj6*ubh)}(h4NOT USED. Setting this flag will result in an error.h]h4NOT USED. Setting this flag will result in an error.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5*hM hj6*ubeh}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj5*hM hj)ubj)}(hG``handle`` Returned handle for the object. Object handles are nonzero.h](j)}(h ``handle``h]jC)}(hj+h]hhandle}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj+ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj*ubj)}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj+ubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hj,+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj+ubeh}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj+hM hj)ubeh}(h]h ]h"]h$]h&]uh1jhj>)ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjV+h]h Description}(hjX+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT+ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(h\Userptr objects have several restrictions on what ioctls can be used with the object handle.h]h\Userptr objects have several restrictions on what ioctls can be used with the object handle.}(hjl+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_i915_perf_oa_config (C struct)c.drm_i915_perf_oa_confighNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_perf_oa_configh]jg)}(hstruct drm_i915_perf_oa_configh](jm)}(hjph]hstruct}(hj+hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj+hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj+hhhj+hM ubj)}(hdrm_i915_perf_oa_configh]j)}(hj+h]hdrm_i915_perf_oa_config}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj+hhhj+hM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj+hhhj+hM ubah}(h]j+ah ](jjeh"]h$]h&]jj)jhuh1j`hj+hM hj+hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj+hhhj+hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj+jj+jjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_perf_oa_config { char uuid[36]; __u32 n_mux_regs; __u32 n_boolean_regs; __u32 n_flex_regs; __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; }; **Members** ``uuid`` String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" ``n_mux_regs`` Number of mux regs in :c:type:`mux_regs_ptr`. ``n_boolean_regs`` Number of boolean regs in :c:type:`boolean_regs_ptr`. ``n_flex_regs`` Number of flex regs in :c:type:`flex_regs_ptr`. ``mux_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_mux_regs`). ``boolean_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_boolean_regs`). ``flex_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_flex_regs`).h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubh:}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj+ubj)}(hstruct drm_i915_perf_oa_config { char uuid[36]; __u32 n_mux_regs; __u32 n_boolean_regs; __u32 n_flex_regs; __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; };h]hstruct drm_i915_perf_oa_config { char uuid[36]; __u32 n_mux_regs; __u32 n_boolean_regs; __u32 n_flex_regs; __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; };}hj,sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj+ubh)}(h **Members**h]j)}(hj,h]hMembers}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj+ubj)}(hhh](j)}(h@``uuid`` String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" h](j)}(h``uuid``h]jC)}(hj4,h]huuid}(hj6,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj2,ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj.,ubj)}(hhh]h)}(h6String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"h]h:String formatted like “%08x-%04x-%04x-%04x-%012x”}(hjM,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI,hM hjJ,ubah}(h]h ]h"]h$]h&]uh1jhj.,ubeh}(h]h ]h"]h$]h&]uh1jhjI,hM hj+,ubj)}(h=``n_mux_regs`` Number of mux regs in :c:type:`mux_regs_ptr`. h](j)}(h``n_mux_regs``h]jC)}(hjm,h]h n_mux_regs}(hjo,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjk,ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjg,ubj)}(hhh]h)}(h-Number of mux regs in :c:type:`mux_regs_ptr`.h](hNumber of mux regs in }(hj,hhhNhNubh)}(h:c:type:`mux_regs_ptr`h]jC)}(hj,h]h mux_regs_ptr}(hj,hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj mux_regs_ptruh1hhj,hM hj,ubh.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj,hM hj,ubah}(h]h ]h"]h$]h&]uh1jhjg,ubeh}(h]h ]h"]h$]h&]uh1jhj,hM hj+,ubj)}(hI``n_boolean_regs`` Number of boolean regs in :c:type:`boolean_regs_ptr`. h](j)}(h``n_boolean_regs``h]jC)}(hj,h]hn_boolean_regs}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj,ubj)}(hhh]h)}(h5Number of boolean regs in :c:type:`boolean_regs_ptr`.h](hNumber of boolean regs in }(hj,hhhNhNubh)}(h:c:type:`boolean_regs_ptr`h]jC)}(hj,h]hboolean_regs_ptr}(hj,hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjboolean_regs_ptruh1hhj,hM hj,ubh.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj,hM hj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj,hM hj+,ubj)}(h@``n_flex_regs`` Number of flex regs in :c:type:`flex_regs_ptr`. h](j)}(h``n_flex_regs``h]jC)}(hj%-h]h n_flex_regs}(hj'-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj#-ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj-ubj)}(hhh]h)}(h/Number of flex regs in :c:type:`flex_regs_ptr`.h](hNumber of flex regs in }(hj>-hhhNhNubh)}(h:c:type:`flex_regs_ptr`h]jC)}(hjH-h]h flex_regs_ptr}(hjJ-hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjF-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj flex_regs_ptruh1hhj:-hM hj>-ubh.}(hj>-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj:-hM hj;-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj:-hM hj+,ubj)}(h``mux_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_mux_regs`). h](j)}(h``mux_regs_ptr``h]jC)}(hj-h]h mux_regs_ptr}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj{-ubj)}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_mux_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hj-hhhNhNubh)}(h:c:type:`n_mux_regs`h]jC)}(hj-h]h n_mux_regs}(hj-hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj n_mux_regsuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj-ubh).}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj-hM hj-ubah}(h]h ]h"]h$]h&]uh1jhj{-ubeh}(h]h ]h"]h$]h&]uh1jhj-hM hj+,ubj)}(h``boolean_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_boolean_regs`). h](j)}(h``boolean_regs_ptr``h]jC)}(hj-h]hboolean_regs_ptr}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj-ubj)}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_boolean_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hj-hhhNhNubh)}(h:c:type:`n_boolean_regs`h]jC)}(hj.h]hn_boolean_regs}(hj.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjn_boolean_regsuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj-ubh).}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj.hM hj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hM hj+,ubj)}(h``flex_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_flex_regs`).h](j)}(h``flex_regs_ptr``h]jC)}(hj;.h]h flex_regs_ptr}(hj=.hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj9.ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj5.ubj)}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_flex_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hjT.hhhNhNubh)}(h:c:type:`n_flex_regs`h]jC)}(hj^.h]h n_flex_regs}(hj`.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj\.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj n_flex_regsuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjT.ubh).}(hjT.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj{.hM hjQ.ubah}(h]h ]h"]h$]h&]uh1jhj5.ubeh}(h]h ]h"]h$]h&]uh1jhjP.hM hj+,ubeh}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj.h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(h?Structure to upload perf dynamic configuration into the kernel.h]h?Structure to upload perf dynamic configuration into the kernel.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_i915_query_item (C struct)c.drm_i915_query_itemhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_query_itemh]jg)}(hstruct drm_i915_query_itemh](jm)}(hjph]hstruct}(hj.hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj.hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj.hhhj.hM ubj)}(hdrm_i915_query_itemh]j)}(hj.h]hdrm_i915_query_item}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj.hhhj.hM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj.hhhj.hM ubah}(h]j.ah ](jjeh"]h$]h&]jj)jhuh1j`hj.hM hj.hhubj)}(hhh]h)}(h.An individual query for the kernel to process.h]h.An individual query for the kernel to process.}(hj!/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj/hhubah}(h]h ]h"]h$]h&]uh1jhj.hhhj.hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj9/jj9/jjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; }; **Members** ``query_id`` The id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) ``length`` When set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item. ``flags`` When :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0. When :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following: - ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` When :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine. ``data_ptr`` Data will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjE/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA/ubh:}(hjA/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj=/ubj)}(hXkstruct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; };h]hXkstruct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; };}hj^/sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj=/ubh)}(h **Members**h]j)}(hjo/h]hMembers}(hjq/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm/ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj=/ubj)}(hhh](j)}(hXi``query_id`` The id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h](j)}(h ``query_id``h]jC)}(hj/h]hquery_id}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj/ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj/ubj)}(hhh]j)}(hhh]j)}(hXUThe id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h](j)}(h9The id for this query. Currently accepted query IDs are:h]h9The id for this query. Currently accepted query IDs are:}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/hM hj/ubj)}(hhh]h)}(hhh](h)}(hJ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info)h]h)}(hj/h](jC)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj/ubh* (see struct drm_i915_query_topology_info)}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj/ubah}(h]h ]h"]h$]h&]uh1hhj/ubh)}(h@``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info)h]h)}(hj/h](jC)}(h``DRM_I915_QUERY_ENGINE_INFO``h]hDRM_I915_QUERY_ENGINE_INFO}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj/ubh" (see struct drm_i915_engine_info)}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj/ubah}(h]h ]h"]h$]h&]uh1hhj/ubh)}(hF``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config)h]h)}(hj0h](jC)}(h``DRM_I915_QUERY_PERF_CONFIG``h]hDRM_I915_QUERY_PERF_CONFIG}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj0ubh( (see struct drm_i915_query_perf_config)}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj0ubah}(h]h ]h"]h$]h&]uh1hhj/ubh)}(hL``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions)h]h)}(hj60h](jC)}(h!``DRM_I915_QUERY_MEMORY_REGIONS``h]hDRM_I915_QUERY_MEMORY_REGIONS}(hj;0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj80ubh+ (see struct drm_i915_query_memory_regions)}(hj80hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj40ubah}(h]h ]h"]h$]h&]uh1hhj/ubh)}(h?``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`)h]h)}(hj\0h](jC)}(h ``DRM_I915_QUERY_HWCONFIG_BLOB``h]hDRM_I915_QUERY_HWCONFIG_BLOB}(hja0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj^0ubh (see }(hj^0hhhNhNubj )}(h`GuC HWCONFIG blob uAPI`h]hGuC HWCONFIG blob uAPI}(hjs0hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj^0ubh)}(hj^0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjZ0ubah}(h]h ]h"]h$]h&]uh1hhj/ubh)}(hO``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info)h]h)}(hj0h](jC)}(h%``DRM_I915_QUERY_GEOMETRY_SUBSLICES``h]h!DRM_I915_QUERY_GEOMETRY_SUBSLICES}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj0ubh* (see struct drm_i915_query_topology_info)}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj0ubah}(h]h ]h"]h$]h&]uh1hhj/ubh)}(h]``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h]h)}(h\``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version)h](jC)}(h)``DRM_I915_QUERY_GUC_SUBMISSION_VERSION``h]h%DRM_I915_QUERY_GUC_SUBMISSION_VERSION}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj0ubh3 (see struct drm_i915_query_guc_submission_version)}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/hM hj0ubah}(h]h ]h"]h$]h&]uh1hhj/ubeh}(h]h ]h"]h$]h&]j j uh1hhj/hM hj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hM hj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hM hj/ubj)}(h``length`` When set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item. h](j)}(h ``length``h]jC)}(hj1h]hlength}(hj 1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj1ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj1ubj)}(hhh]h)}(hWhen set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item.h](h]When set to zero by userspace, this is filled with the size of the data to be written at the }(hj!1hhhNhNubj)}(h **data_ptr**h]hdata_ptr}(hj)1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!1ubhg pointer. The kernel sets this value to a negative value to signal an error on a particular query item.}(hj!1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hM hj/ubj)}(hX``flags`` When :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0. When :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following: - ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` When :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine. h](j)}(h ``flags``h]jC)}(hjT1h]hflags}(hjV1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjR1ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjN1ubj)}(hhh](h)}(hGWhen :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0.h](hWhen }(hjm1hhhNhNubh)}(h:c:type:`query_id`h]jC)}(hjw1h]hquery_id}(hjy1hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhju1ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjquery_iduh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjm1ubh == }(hjm1hhhNhNubjC)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjm1ubh , must be 0.}(hjm1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj1hM hjj1ubh)}(hXWhen :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following:h](hWhen }(hj1hhhNhNubh)}(h:c:type:`query_id`h]jC)}(hj1h]hquery_id}(hj1hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj1ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjquery_iduh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj1ubh == }(hj1hhhNhNubjC)}(h``DRM_I915_QUERY_PERF_CONFIG``h]hDRM_I915_QUERY_PERF_CONFIG}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj1ubh, must be one of the following:}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj1hM hjj1ubjK)}(h- ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` h]h)}(hhh](h)}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]h)}(hj1h]jC)}(hj1h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj2ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj1ubah}(h]h ]h"]h$]h&]uh1hhj1ubh)}(h,``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``h]h)}(hj2h]jC)}(hj2h]h(DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID}(hj$2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj!2ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj2ubah}(h]h ]h"]h$]h&]uh1hhj1ubh)}(h(``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` h]h)}(h'``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID``h]jC)}(hjD2h]h#DRM_I915_QUERY_PERF_CONFIG_FOR_UUID}(hjF2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjB2ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj>2ubah}(h]h ]h"]h$]h&]uh1hhj1ubeh}(h]h ]h"]h$]h&]j j uh1hhj2hM hj1ubah}(h]h ]h"]h$]h&]uh1jJhj2hM hjj1ubh)}(hWhen :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine.h](hWhen }(hjl2hhhNhNubh)}(h:c:type:`query_id`h]jC)}(hjv2h]hquery_id}(hjx2hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjt2ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjquery_iduh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjl2ubh == }(hjl2hhhNhNubjC)}(h%``DRM_I915_QUERY_GEOMETRY_SUBSLICES``h]h!DRM_I915_QUERY_GEOMETRY_SUBSLICES}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjl2ubhR must contain a struct i915_engine_class_instance that references a render engine.}(hjl2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj2hM hjj1ubeh}(h]h ]h"]h$]h&]uh1jhjN1ubeh}(h]h ]h"]h$]h&]uh1jhji1hM hj/ubj)}(h``data_ptr`` Data will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](j)}(h ``data_ptr``h]jC)}(hj2h]hdata_ptr}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj2ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM) hj2ubj)}(hhh]h)}(hData will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](h0Data will be written at the location pointed by }(hj2hhhNhNubj)}(h **data_ptr**h]hdata_ptr}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubh when the value of }(hj2hhhNhNubj)}(h **length**h]hlength}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubh< matches the length of the data to be written by the kernel.}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM( hj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hM) hj/ubeh}(h]h ]h"]h$]h&]uh1jhj=/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj)3h]h Description}(hj+3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'3ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM- hjihhubh)}(hThe behaviour is determined by the **query_id**. Note that exactly what **data_ptr** is also depends on the specific **query_id**.h](h#The behaviour is determined by the }(hj?3hhhNhNubj)}(h **query_id**h]hquery_id}(hjG3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?3ubh. Note that exactly what }(hj?3hhhNhNubj)}(h **data_ptr**h]hdata_ptr}(hjY3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?3ubh! is also depends on the specific }(hj?3hhhNhNubj)}(h **query_id**h]hquery_id}(hjk3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?3ubh.}(hj?3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_i915_query (C struct)c.drm_i915_queryhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_queryh]jg)}(hstruct drm_i915_queryh](jm)}(hjph]hstruct}(hj3hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj3hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj3hhhj3hM ubj)}(hdrm_i915_queryh]j)}(hj3h]hdrm_i915_query}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj3hhhj3hM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj3hhhj3hM ubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1j`hj3hM hj3hhubj)}(hhh]h)}(hISupply an array of struct drm_i915_query_item for the kernel to fill out.h]hISupply an array of struct drm_i915_query_item for the kernel to fill out.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM1 hj3hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj3hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj3jj3jjjuh1j[hhhjihNhNubj)}(hXl**Definition**:: struct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; }; **Members** ``num_items`` The number of elements in the **items_ptr** array ``flags`` Unused for now. Must be cleared to zero. ``items_ptr`` Pointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubh:}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM5 hj3ubj)}(hUstruct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; };h]hUstruct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; };}hj4sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM7 hj3ubh)}(h **Members**h]j)}(hj-4h]hMembers}(hj/4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+4ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM= hj3ubj)}(hhh](j)}(h@``num_items`` The number of elements in the **items_ptr** array h](j)}(h ``num_items``h]jC)}(hjL4h]h num_items}(hjN4hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjJ4ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMI hjF4ubj)}(hhh]h)}(h1The number of elements in the **items_ptr** arrayh](hThe number of elements in the }(hje4hhhNhNubj)}(h **items_ptr**h]h items_ptr}(hjm4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje4ubh array}(hje4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhja4hMI hjb4ubah}(h]h ]h"]h$]h&]uh1jhjF4ubeh}(h]h ]h"]h$]h&]uh1jhja4hMI hjC4ubj)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]jC)}(hj4h]hflags}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj4ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMM hj4ubj)}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMM hj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMM hjC4ubj)}(ho``items_ptr`` Pointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](j)}(h ``items_ptr``h]jC)}(hj4h]h items_ptr}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj4ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMR hj4ubj)}(hhh]h)}(haPointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](hSPointer to an array of struct drm_i915_query_item. The number of array elements is }(hj4hhhNhNubj)}(h **num_items**h]h num_items}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh.}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj4hMR hj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMR hjC4ubeh}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj$5h]h Description}(hj&5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"5ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMV hjihhubh)}(h`Note that this is generally a two step process for each struct drm_i915_query_item in the array:h]h`Note that this is generally a two step process for each struct drm_i915_query_item in the array:}(hj:5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM2 hjihhubhenumerated_list)}(hhh](h)}(hX4Call the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with :c:type:`drm_i915_query_item.length ` set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties). h]h)}(hX3Call the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with :c:type:`drm_i915_query_item.length ` set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties).h](hWCall the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with }(hjR5hhhNhNubh)}(h::c:type:`drm_i915_query_item.length `h]jC)}(hj\5h]hdrm_i915_query_item.length}(hj^5hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjZ5ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM5 hjR5ubh set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties).}(hjR5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjy5hM5 hjN5ubah}(h]h ]h"]h$]h&]uh1hhjK5ubh)}(hXPNext we call DRM_IOCTL_I915_QUERY again, this time with the :c:type:`drm_i915_query_item.data_ptr ` equal to our newly allocated blob. Note that the :c:type:`drm_i915_query_item.length ` should still be the same as what the kernel previously set. At this point the kernel can fill in the blob. h]h)}(hXONext we call DRM_IOCTL_I915_QUERY again, this time with the :c:type:`drm_i915_query_item.data_ptr ` equal to our newly allocated blob. Note that the :c:type:`drm_i915_query_item.length ` should still be the same as what the kernel previously set. At this point the kernel can fill in the blob.h](h`h]jC)}(hj5h]hdrm_i915_query_item.data_ptr}(hj5hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj5ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM: hj5ubh2 equal to our newly allocated blob. Note that the }(hj5hhhNhNubh)}(h::c:type:`drm_i915_query_item.length `h]jC)}(hj5h]hdrm_i915_query_item.length}(hj5hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj5ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hhj5hM: hj5ubhk should still be the same as what the kernel previously set. At this point the kernel can fill in the blob.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj5hM: hj5ubah}(h]h ]h"]h$]h&]uh1hhjK5ubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jI5hjihhhNhNubh)}(hNote that for some query items it can make sense for userspace to just pass in a buffer/blob equal to or larger than the required size. In this case only a single ioctl call is needed. For some smaller query items this can work quite well.h]hNote that for some query items it can make sense for userspace to just pass in a buffer/blob equal to or larger than the required size. In this case only a single ioctl call is needed. For some smaller query items this can work quite well.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM? hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW'drm_i915_query_topology_info (C struct)c.drm_i915_query_topology_infohNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_query_topology_infoh]jg)}(h#struct drm_i915_query_topology_infoh](jm)}(hjph]hstruct}(hj6hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj6hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMG ubj)}(h h]h }(hj*6hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj6hhhj)6hMG ubj)}(hdrm_i915_query_topology_infoh]j)}(hj6h]hdrm_i915_query_topology_info}(hj<6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj86ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj6hhhj)6hMG ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj6hhhj)6hMG ubah}(h]j6ah ](jjeh"]h$]h&]jj)jhuh1j`hj)6hMG hj6hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj6hhhj)6hMG ubeh}(h]h ](jstructeh"]h$]h&]jjjjg6jjg6jjjuh1j[hhhjihNhNubj)}(hX? **Definition**:: struct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; }; **Members** ``flags`` Unused for now. Must be cleared to zero. ``max_slices`` The number of bits used to express the slice mask. ``max_subslices`` The number of bits used to express the subslice mask. ``max_eus_per_subslice`` The number of bits in the EU mask that correspond to a single subslice's EUs. ``subslice_offset`` Offset in data[] at which the subslice masks are stored. ``subslice_stride`` Stride at which each of the subslice masks for each slice are stored. ``eu_offset`` Offset in data[] at which the EU masks are stored. ``eu_stride`` Stride at which each of the EU masks for each subslice are stored. ``data`` Contains 3 pieces of information : - The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. - The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 - The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjs6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo6ubh:}(hjo6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM^ hjk6ubj)}(hstruct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; };h]hstruct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; };}hj6sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM` hjk6ubh)}(h **Members**h]j)}(hj6h]hMembers}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMl hjk6ubj)}(hhh](j)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]jC)}(hj6h]hflags}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj6ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMb hj6ubj)}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMb hj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMb hj6ubj)}(hB``max_slices`` The number of bits used to express the slice mask. h](j)}(h``max_slices``h]jC)}(hj6h]h max_slices}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj6ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMi hj6ubj)}(hhh]h)}(h2The number of bits used to express the slice mask.h]h2The number of bits used to express the slice mask.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 7hMi hj 7ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj 7hMi hj6ubj)}(hH``max_subslices`` The number of bits used to express the subslice mask. h](j)}(h``max_subslices``h]jC)}(hj.7h]h max_subslices}(hj07hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,7ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMp hj(7ubj)}(hhh]h)}(h5The number of bits used to express the subslice mask.h]h5The number of bits used to express the subslice mask.}(hjG7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC7hMp hjD7ubah}(h]h ]h"]h$]h&]uh1jhj(7ubeh}(h]h ]h"]h$]h&]uh1jhjC7hMp hj6ubj)}(hg``max_eus_per_subslice`` The number of bits in the EU mask that correspond to a single subslice's EUs. h](j)}(h``max_eus_per_subslice``h]jC)}(hjg7h]hmax_eus_per_subslice}(hji7hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhje7ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMx hja7ubj)}(hhh]h)}(hMThe number of bits in the EU mask that correspond to a single subslice's EUs.h]hOThe number of bits in the EU mask that correspond to a single subslice’s EUs.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMw hj}7ubah}(h]h ]h"]h$]h&]uh1jhja7ubeh}(h]h ]h"]h$]h&]uh1jhj|7hMx hj6ubj)}(hM``subslice_offset`` Offset in data[] at which the subslice masks are stored. h](j)}(h``subslice_offset``h]jC)}(hj7h]hsubslice_offset}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj7ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj7ubj)}(hhh]h)}(h8Offset in data[] at which the subslice masks are stored.h]h8Offset in data[] at which the subslice masks are stored.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hM hj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hM hj6ubj)}(hZ``subslice_stride`` Stride at which each of the subslice masks for each slice are stored. h](j)}(h``subslice_stride``h]jC)}(hj7h]hsubslice_stride}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj7ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj7ubj)}(hhh]h)}(hEStride at which each of the subslice masks for each slice are stored.h]hEStride at which each of the subslice masks for each slice are stored.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hM hj6ubj)}(hA``eu_offset`` Offset in data[] at which the EU masks are stored. h](j)}(h ``eu_offset``h]jC)}(hj8h]h eu_offset}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj8ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj8ubj)}(hhh]h)}(h2Offset in data[] at which the EU masks are stored.h]h2Offset in data[] at which the EU masks are stored.}(hj-8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)8hM hj*8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj)8hM hj6ubj)}(hQ``eu_stride`` Stride at which each of the EU masks for each subslice are stored. h](j)}(h ``eu_stride``h]jC)}(hjM8h]h eu_stride}(hjO8hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjK8ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjG8ubj)}(hhh]h)}(hBStride at which each of the EU masks for each subslice are stored.h]hBStride at which each of the EU masks for each subslice are stored.}(hjf8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb8hM hjc8ubah}(h]h ]h"]h$]h&]uh1jhjG8ubeh}(h]h ]h"]h$]h&]uh1jhjb8hM hj6ubj)}(hX```data`` Contains 3 pieces of information : - The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. - The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 - The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](j)}(h``data``h]jC)}(hj8h]hdata}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj8ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj8ubj)}(hhh](h)}(h"Contains 3 pieces of information :h]h"Contains 3 pieces of information :}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj8ubh)}(hhh](h)}(hX6The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. h](h)}(hThe slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula :h]hThe slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula :}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj8ubj)}(h(data[X / 8] >> (X % 8)) & 1h]h(data[X / 8] >> (X % 8)) & 1}hj8sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj8ubh)}(hXrStarting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask.h]hX|Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform’s subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as “gslices” or “cslices” since userspace is capable of inferring those from the subslice mask.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj8ubeh}(h]h ]h"]h$]h&]uh1hhj8ubh)}(hXThe subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 h](h)}(hX7The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula :h]hX?The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term “subslice” to refer to what the hardware documentation describes as a “dual-subslices.” The availability of subslice Y in slice X can be queried with the following formula :}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj8ubj)}(hD(data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1h]hD(data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1}hj8sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj8ubeh}(h]h ]h"]h$]h&]uh1hhj8ubh)}(hX9The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](h)}(hThe EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula :h]hThe EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula :}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj9ubj)}(h\(data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h]h\(data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1}hj)9sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj9ubeh}(h]h ]h"]h$]h&]uh1hhj8ubeh}(h]h ]h"]h$]h&]j j uh1hhj8hM hj8ubeh}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hM hj6ubeh}(h]h ]h"]h$]h&]uh1jhjk6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjb9h]h Description}(hjd9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`9ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hSDescribes slice/subslice/EU information queried by ``DRM_I915_QUERY_TOPOLOGY_INFO``h](h3Describes slice/subslice/EU information queried by }(hjx9hhhNhNubjC)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjx9ubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM[ hjihhubj{)}(h.. _Engine Discovery uAPI:h]h}(h]h ]h"]h$]h&]hj!uh1jzhMhjihhhN referencedKubh)}(h**Engine Discovery uAPI**h]j)}(hj9h]hEngine Discovery uAPI}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]j!ah ]h"]engine discovery uapiah$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMa hjihhj}j9j9sj}j!j9sj9Kubh)}(hEngine discovery uAPI is a way of enumerating physical engines present in a GPU associated with an open i915 DRM file descriptor. This supersedes the old way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like `I915_PARAM_HAS_BLT`.h](hEngine discovery uAPI is a way of enumerating physical engines present in a GPU associated with an open i915 DRM file descriptor. This supersedes the old way of using }(hj9hhhNhNubj )}(h`DRM_IOCTL_I915_GETPARAM`h]hDRM_IOCTL_I915_GETPARAM}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj9ubh and engine identifiers like }(hj9hhhNhNubj )}(h`I915_PARAM_HAS_BLT`h]hI915_PARAM_HAS_BLT}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj9ubh.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hThe need for this interface came starting with Icelake and newer GPUs, which started to establish a pattern of having multiple engines of a same class, where not all instances were always completely functionally equivalent.h]hThe need for this interface came starting with Icelake and newer GPUs, which started to establish a pattern of having multiple engines of a same class, where not all instances were always completely functionally equivalent.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hqEntry point for this uapi is `DRM_IOCTL_I915_QUERY` with the `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.h](hEntry point for this uapi is }(hj9hhhNhNubj )}(h`DRM_IOCTL_I915_QUERY`h]hDRM_IOCTL_I915_QUERY}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj9ubh with the }(hj9hhhNhNubj )}(h`DRM_I915_QUERY_ENGINE_INFO`h]hDRM_I915_QUERY_ENGINE_INFO}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj9ubh as the queried item id.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(h(Example for getting the list of engines:h]h(Example for getting the list of engines:}(hj0:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubj)}(hXstruct drm_i915_query_engine_info *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_ENGINE_INFO; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of engines. The kernel will fill out the // item.length for us, which is the number of bytes we need. // // Alternatively a large buffer can be allocated straightaway enabling // querying in one pass, in which case item.length should contain the // length of the provided buffer. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with info on all engines. item.data_ptr = (uintptr_t)&info; err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each engine in the array for (i = 0; i < info->num_engines; i++) { struct drm_i915_engine_info einfo = info->engines[i]; u16 class = einfo.engine.class; u16 instance = einfo.engine.instance; .... } free(info);h]hXstruct drm_i915_query_engine_info *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_ENGINE_INFO; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of engines. The kernel will fill out the // item.length for us, which is the number of bytes we need. // // Alternatively a large buffer can be allocated straightaway enabling // querying in one pass, in which case item.length should contain the // length of the provided buffer. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with info on all engines. item.data_ptr = (uintptr_t)&info; err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each engine in the array for (i = 0; i < info->num_engines; i++) { struct drm_i915_engine_info einfo = info->engines[i]; u16 class = einfo.engine.class; u16 instance = einfo.engine.instance; .... } free(info);}hj?:sbah}(h]h ]h"]h$]h&]jjjjjj}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hEach of the enumerated engines, apart from being defined by its class and instance (see `struct i915_engine_class_instance`), also can have flags and capabilities defined as documented in i915_drm.h.h](hXEach of the enumerated engines, apart from being defined by its class and instance (see }(hjO:hhhNhNubj )}(h#`struct i915_engine_class_instance`h]h!struct i915_engine_class_instance}(hjW:hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjO:ubhL), also can have flags and capabilities defined as documented in i915_drm.h.}(hjO:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(h{For instance video engines which support HEVC encoding will have the `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.h](hEFor instance video engines which support HEVC encoding will have the }(hjp:hhhNhNubj )}(h"`I915_VIDEO_CLASS_CAPABILITY_HEVC`h]h I915_VIDEO_CLASS_CAPABILITY_HEVC}(hjx:hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjp:ubh capability bit set.}(hjp:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hEngine discovery only fully comes to its own when combined with the new way of addressing engines when submitting batch buffers using contexts with engine maps configured.h]hEngine discovery only fully comes to its own when combined with the new way of addressing engines when submitting batch buffers using contexts with engine maps configured.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_i915_engine_info (C struct)c.drm_i915_engine_infohNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_engine_infoh]jg)}(hstruct drm_i915_engine_infoh](jm)}(hjph]hstruct}(hj:hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj:hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj:hhhj:hM ubj)}(hdrm_i915_engine_infoh]j)}(hj:h]hdrm_i915_engine_info}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj:hhhj:hM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj:hhhj:hM ubah}(h]j:ah ](jjeh"]h$]h&]jj)jhuh1j`hj:hM hj:hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj:hhhj:hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj;jj;jjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; }; **Members** ``engine`` Engine class and instance. ``rsvd0`` Reserved field. ``flags`` Engine flags. ``capabilities`` Capabilities of this engine. ``logical_instance`` Logical instance of engine ``rsvd1`` Reserved fields. ``rsvd2`` Reserved fields.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ;ubh:}(hj ;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj;ubj)}(hXstruct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; };h]hXstruct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; };}hj);sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj;ubh)}(h **Members**h]j)}(hj:;h]hMembers}(hj<;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8;ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj;ubj)}(hhh](j)}(h&``engine`` Engine class and instance. h](j)}(h ``engine``h]jC)}(hjY;h]hengine}(hj[;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjW;ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjS;ubj)}(hhh]h)}(hEngine class and instance.h]hEngine class and instance.}(hjr;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn;hM hjo;ubah}(h]h ]h"]h$]h&]uh1jhjS;ubeh}(h]h ]h"]h$]h&]uh1jhjn;hM hjP;ubj)}(h``rsvd0`` Reserved field. h](j)}(h ``rsvd0``h]jC)}(hj;h]hrsvd0}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj;ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj;ubj)}(hhh]h)}(hReserved field.h]hReserved field.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hM hj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hM hjP;ubj)}(h``flags`` Engine flags. h](j)}(h ``flags``h]jC)}(hj;h]hflags}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj;ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj;ubj)}(hhh]h)}(h Engine flags.h]h Engine flags.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hM hj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hM hjP;ubj)}(h.``capabilities`` Capabilities of this engine. h](j)}(h``capabilities``h]jC)}(hj<h]h capabilities}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj<ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj;ubj)}(hhh]h)}(hCapabilities of this engine.h]hCapabilities of this engine.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM hj<ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj<hM hjP;ubj)}(h0``logical_instance`` Logical instance of engine h](j)}(h``logical_instance``h]jC)}(hj=<h]hlogical_instance}(hj?<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj;<ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM" hj7<ubj)}(hhh]h)}(hLogical instance of engineh]hLogical instance of engine}(hjV<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR<hM" hjS<ubah}(h]h ]h"]h$]h&]uh1jhj7<ubeh}(h]h ]h"]h$]h&]uh1jhjR<hM" hjP;ubj)}(h``rsvd1`` Reserved fields. h](j)}(h ``rsvd1``h]jC)}(hjv<h]hrsvd1}(hjx<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjt<ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM% hjp<ubj)}(hhh]h)}(hReserved fields.h]hReserved fields.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM% hj<ubah}(h]h ]h"]h$]h&]uh1jhjp<ubeh}(h]h ]h"]h$]h&]uh1jhj<hM% hjP;ubj)}(h``rsvd2`` Reserved fields.h](j)}(h ``rsvd2``h]jC)}(hj<h]hrsvd2}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj<ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM& hj<ubj)}(hhh]h)}(hReserved fields.h]hReserved fields.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM' hj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hM& hjP;ubeh}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj<h]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM* hjihhubh)}(hADescribes one engine and its capabilities as known to the driver.h]hADescribes one engine and its capabilities as known to the driver.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_i915_query_engine_info (C struct)c.drm_i915_query_engine_infohNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_query_engine_infoh]jg)}(h!struct drm_i915_query_engine_infoh](jm)}(hjph]hstruct}(hj0=hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj,=hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj>=hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj,=hhhj==hM ubj)}(hdrm_i915_query_engine_infoh]j)}(hj*=h]hdrm_i915_query_engine_info}(hjP=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL=ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj,=hhhj==hM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj(=hhhj==hM ubah}(h]j#=ah ](jjeh"]h$]h&]jj)jhuh1j`hj==hM hj%=hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj%=hhhj==hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj{=jj{=jjjuh1j[hhhjihNhNubj)}(hX;**Definition**:: struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; }; **Members** ``num_engines`` Number of struct drm_i915_engine_info structs following. ``rsvd`` MBZ ``engines`` Marker for drm_i915_engine_info structures.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh:}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM/ hj=ubj)}(h{struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; };h]h{struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; };}hj=sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM1 hj=ubh)}(h **Members**h]j)}(hj=h]hMembers}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM7 hj=ubj)}(hhh](j)}(hI``num_engines`` Number of struct drm_i915_engine_info structs following. h](j)}(h``num_engines``h]jC)}(hj=h]h num_engines}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj=ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM2 hj=ubj)}(hhh]h)}(h8Number of struct drm_i915_engine_info structs following.h]h8Number of struct drm_i915_engine_info structs following.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hM2 hj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hM2 hj=ubj)}(h ``rsvd`` MBZ h](j)}(h``rsvd``h]jC)}(hj >h]hrsvd}(hj >hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM5 hj>ubj)}(hhh]h)}(hMBZh]hMBZ}(hj">hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hM5 hj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hM5 hj=ubj)}(h7``engines`` Marker for drm_i915_engine_info structures.h](j)}(h ``engines``h]jC)}(hjB>h]hengines}(hjD>hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@>ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM7 hj<>ubj)}(hhh]h)}(h+Marker for drm_i915_engine_info structures.h]h+Marker for drm_i915_engine_info structures.}(hj[>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM8 hjX>ubah}(h]h ]h"]h$]h&]uh1jhj<>ubeh}(h]h ]h"]h$]h&]uh1jhjW>hM7 hj=ubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj>h]h Description}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM; hjihhubh)}(h~Engine info query enumerates all engines known to the driver by filling in an array of struct drm_i915_engine_info structures.h]h~Engine info query enumerates all engines known to the driver by filling in an array of struct drm_i915_engine_info structures.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM, hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_i915_query_perf_config (C struct)c.drm_i915_query_perf_confighNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_query_perf_configh]jg)}(h!struct drm_i915_query_perf_configh](jm)}(hjph]hstruct}(hj>hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj>hhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM2 ubj)}(h h]h }(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj>hhhj>hM2 ubj)}(hdrm_i915_query_perf_configh]j)}(hj>h]hdrm_i915_query_perf_config}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj>hhhj>hM2 ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj>hhhj>hM2 ubah}(h]j>ah ](jjeh"]h$]h&]jj)jhuh1j`hj>hM2 hj>hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj>hhhj>hM2 ubeh}(h]h ](jstructeh"]h$]h&]jjjj?jj?jjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; }; **Members** ``{unnamed_union}`` anonymous ``n_configs`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available. ``config`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. ``uuid`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. String formatted like "``08x-````04x-````04x-````04x-````012x``" ``flags`` Unused for now. Must be cleared to zero. ``data`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers. When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created : - :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh:}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM@ hj?ubj)}(hstruct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; };h]hstruct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; };}hj3?sbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMB hj?ubh)}(h **Members**h]j)}(hjD?h]hMembers}(hjF?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB?ubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhML hj?ubj)}(hhh](j)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]jC)}(hjc?h]h{unnamed_union}}(hje?hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhja?ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhj]?ubj)}(hhh]h)}(h anonymoush]h anonymous}(hj|?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx?hKhjy?ubah}(h]h ]h"]h$]h&]uh1jhj]?ubeh}(h]h ]h"]h$]h&]uh1jhjx?hKhjZ?ubj)}(h``n_configs`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available. h](j)}(h ``n_configs``h]jC)}(hj?h]h n_configs}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj?ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMG hj?ubj)}(hhh]h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available.h](hWhen }(hj?hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]jC)}(hj?h]hdrm_i915_query_item.flags}(hj?hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj?ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhME hj?ubh == }(hj?hhhNhNubjC)}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj?ubhB, i915 sets this fields to the number of configurations available.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj?hME hj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMG hjZ?ubj)}(h``config`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. h](j)}(h ``config``h]jC)}(hj @h]hconfig}(hj @hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj @ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMQ hj@ubj)}(hhh]h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.h](hWhen }(hj$@hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]jC)}(hj.@h]hdrm_i915_query_item.flags}(hj0@hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj,@ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMN hj$@ubh == }(hj$@hhhNhNubjC)}(h*``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``h]h&DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID}(hjP@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$@ubhq, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.}(hj$@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjK@hMN hj!@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj @hMQ hjZ?ubj)}(hX+``uuid`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. String formatted like "``08x-````04x-````04x-````04x-````012x``" h](j)}(h``uuid``h]jC)}(hjz@h]huuid}(hj|@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjx@ubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM] hjt@ubj)}(hhh](h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.h](hWhen }(hj@hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]jC)}(hj@h]hdrm_i915_query_item.flags}(hj@hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj@ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMX hj@ubh == }(hj@hhhNhNubjC)}(h,``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``h]h(DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@ubhq, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj@hMX hj@ubh)}(h@String formatted like "``08x-````04x-````04x-````04x-````012x``"h](hString formatted like “}(hj@hhhNhNubjC)}(h(``08x-````04x-````04x-````04x-````012x``h]h$08x-````04x-````04x-````04x-````012x}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@ubh”}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj@hM] hj@ubeh}(h]h ]h"]h$]h&]uh1jhjt@ubeh}(h]h ]h"]h$]h&]uh1jhj@hM] hjZ?ubj)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]jC)}(hj Ah]hflags}(hj AhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjAubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMe hjAubj)}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hj"AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhMe hjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhjAhMe hjZ?ubj)}(hX``data`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers. When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created : - :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h](j)}(h``data``h]jC)}(hjBAh]hdata}(hjDAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@Aubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMv hj` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers.h](hWhen }(hj[AhhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]jC)}(hjeAh]hdrm_i915_query_item.flags}(hjgAhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjcAubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMl hj[Aubh == }(hj[AhhhNhNubjC)}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj[AubhA, i915 will write an array of __u64 of configuration identifiers.}(hj[AhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjAhMl hjXAubh)}(hXNWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created :h](hWhen }(hjAhhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]jC)}(hjAh]hdrm_i915_query_item.flags}(hjAhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjAubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMo hjAubh == }(hjAhhhNhNubjC)}(h#``DRM_I915_QUERY_PERF_CONFIG_DATA``h]hDRM_I915_QUERY_PERF_CONFIG_DATA}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjAubh, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created :}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjAhMo hjXAubjK)}(h- :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h]h)}(hhh](h)}(hF:c:type:`drm_i915_perf_oa_config.n_mux_regs `h]h)}(hjAh]h)}(hjAh]jC)}(hjAh]h"drm_i915_perf_oa_config.n_mux_regs}(hjAhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjAubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_perf_oa_configuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMu hjAubah}(h]h ]h"]h$]h&]uh1hhjBhMu hjAubah}(h]h ]h"]h$]h&]uh1hhjAubh)}(hJ:c:type:`drm_i915_perf_oa_config.n_boolean_regs `h]h)}(hjBh]h)}(hjBh]jC)}(hjBh]h&drm_i915_perf_oa_config.n_boolean_regs}(hj&BhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj#Bubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_perf_oa_configuh1hhjWAhMv hj Bubah}(h]h ]h"]h$]h&]uh1hhjWAhMv hjBubah}(h]h ]h"]h$]h&]uh1hhjAubh)}(hG:c:type:`drm_i915_perf_oa_config.n_flex_regs `h]h)}(hjOBh]h)}(hjOBh]jC)}(hjOBh]h#drm_i915_perf_oa_config.n_flex_regs}(hjWBhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjTBubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_perf_oa_configuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMw hjQBubah}(h]h ]h"]h$]h&]uh1hhjrBhMw hjMBubah}(h]h ]h"]h$]h&]uh1hhjAubeh}(h]h ]h"]h$]h&]j j uh1hhjBhMu hjAubah}(h]h ]h"]h$]h&]uh1jJhjBhMu hjXAubeh}(h]h ]h"]h$]h&]uh1jhjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:Dubah}(h]h ](jjeh"]h$]h&]jjuh1jhjDhhhj+DhM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjDhhhj+DhM ubah}(h]jDah ](jjeh"]h$]h&]jj)jhuh1j`hj+DhM hjDhhubj)}(hhh]h)}(h!Identify particular memory regionh]h!Identify particular memory region}(hj`DhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj]Dhhubah}(h]h ]h"]h$]h&]uh1jhjDhhhj+DhM ubeh}(h]h ](jstructeh"]h$]h&]jjjjxDjjxDjjjuh1j[hhhjihNhNubj)}(h**Definition**:: struct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; }; **Members** ``memory_class`` See enum drm_i915_gem_memory_class ``memory_instance`` Which instanceh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubh:}(hjDhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj|Dubj)}(hastruct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; };h]hastruct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; };}hjDsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj|Dubh)}(h **Members**h]j)}(hjDh]hMembers}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj|Dubj)}(hhh](j)}(h4``memory_class`` See enum drm_i915_gem_memory_class h](j)}(h``memory_class``h]jC)}(hjDh]h memory_class}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjDubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjDubj)}(hhh]h)}(h"See enum drm_i915_gem_memory_classh]h"See enum drm_i915_gem_memory_class}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhM hjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjDhM hjDubj)}(h"``memory_instance`` Which instanceh](j)}(h``memory_instance``h]jC)}(hjEh]hmemory_instance}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjEubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjEubj)}(hhh]h)}(hWhich instanceh]hWhich instance}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhjEhM hjDubeh}(h]h ]h"]h$]h&]uh1jhj|Dubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW&drm_i915_memory_region_info (C struct)c.drm_i915_memory_region_infohNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_memory_region_infoh]jg)}(h"struct drm_i915_memory_region_infoh](jm)}(hjph]hstruct}(hj`EhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj\Ehhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjnEhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj\EhhhjmEhM ubj)}(hdrm_i915_memory_region_infoh]j)}(hjZEh]hdrm_i915_memory_region_info}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|Eubah}(h]h ](jjeh"]h$]h&]jjuh1jhj\EhhhjmEhM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjXEhhhjmEhM ubah}(h]jSEah ](jjeh"]h$]h&]jj)jhuh1j`hjmEhM hjUEhhubj)}(hhh]h)}(h,Describes one region as known to the driver.h]h,Describes one region as known to the driver.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjEhhubah}(h]h ]h"]h$]h&]uh1jhjUEhhhjmEhM ubeh}(h]h ](jstructeh"]h$]h&]jjjjEjjEjjjuh1j[hhhjihNhNubj)}(hX **Definition**:: struct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; }; **Members** ``region`` The class:instance pair encoding ``rsvd0`` MBZ ``probed_size`` Memory probed by the driver Note that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields. ``unallocated_size`` Estimate of memory remaining Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the **probed_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). ``{unnamed_union}`` anonymous ``rsvd1`` MBZ ``{unnamed_struct}`` anonymous ``probed_cpu_visible_size`` Memory probed by the driver that is CPU accessible. This will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible. On systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). Note that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**. ``unallocated_cpu_visible_size`` Estimate of CPU visible memory remaining. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**). Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**). If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubh:}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjEubj)}(hXCstruct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; };h]hXCstruct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; };}hjEsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjEubh)}(h **Members**h]j)}(hjEh]hMembers}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjEubj)}(hhh](j)}(h,``region`` The class:instance pair encoding h](j)}(h ``region``h]jC)}(hjFh]hregion}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj Fubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj Fubj)}(hhh]h)}(h The class:instance pair encodingh]h The class:instance pair encoding}(hj(FhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$FhM hj%Fubah}(h]h ]h"]h$]h&]uh1jhj Fubeh}(h]h ]h"]h$]h&]uh1jhj$FhM hjFubj)}(h``rsvd0`` MBZ h](j)}(h ``rsvd0``h]jC)}(hjHFh]hrsvd0}(hjJFhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjFFubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjBFubj)}(hhh]h)}(hMBZh]hMBZ}(hjaFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]FhM hj^Fubah}(h]h ]h"]h$]h&]uh1jhjBFubeh}(h]h ]h"]h$]h&]uh1jhj]FhM hjFubj)}(hX ``probed_size`` Memory probed by the driver Note that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields. h](j)}(h``probed_size``h]jC)}(hjFh]h probed_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjFubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj{Fubj)}(hhh](h)}(hMemory probed by the driverh]hMemory probed by the driver}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjFubh)}(hNote that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields.h]hNote that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjFubeh}(h]h ]h"]h$]h&]uh1jhj{Fubeh}(h]h ]h"]h$]h&]uh1jhjFhM hjFubj)}(hXi``unallocated_size`` Estimate of memory remaining Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the **probed_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). h](j)}(h``unallocated_size``h]jC)}(hjFh]hunallocated_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjFubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjFubj)}(hhh](h)}(hEstimate of memory remainingh]hEstimate of memory remaining}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjFubh)}(hX5Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the **probed_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**).h](hRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the }(hjFhhhNhNubj)}(h**probed_size**h]h probed_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubh. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hjFhhhNhNubj)}(h**probed_size**h]h probed_size}(hj GhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubh).}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjFubeh}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhjFhM hjFubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]jC)}(hj7Gh]h{unnamed_union}}(hj9GhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj5Gubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhj1Gubj)}(hhh]h)}(h anonymoush]h anonymous}(hjPGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLGhKhjMGubah}(h]h ]h"]h$]h&]uh1jhj1Gubeh}(h]h ]h"]h$]h&]uh1jhjLGhKhjFubj)}(h``rsvd1`` MBZ h](j)}(h ``rsvd1``h]jC)}(hjpGh]hrsvd1}(hjrGhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjnGubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjjGubj)}(hhh]h)}(hMBZh]hMBZ}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhM hjGubah}(h]h ]h"]h$]h&]uh1jhjjGubeh}(h]h ]h"]h$]h&]uh1jhjGhM hjFubj)}(h``{unnamed_struct}`` anonymous h](j)}(h``{unnamed_struct}``h]jC)}(hjGh]h{unnamed_struct}}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjGubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhKhjGubj)}(hhh]h)}(h anonymoush]h anonymous}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhKhjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjGhKhjFubj)}(hXs``probed_cpu_visible_size`` Memory probed by the driver that is CPU accessible. This will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible. On systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). Note that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**. h](j)}(h``probed_cpu_visible_size``h]jC)}(hjGh]hprobed_cpu_visible_size}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjGubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjGubj)}(hhh](h)}(h3Memory probed by the driver that is CPU accessible.h]h3Memory probed by the driver that is CPU accessible.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjGubh)}(hjThis will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible.h](hThis will be always be <= }(hj HhhhNhNubj)}(h**probed_size**h]h probed_size}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj HubhA, and the remainder (if there is any) will not be CPU accessible.}(hj HhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjGubh)}(hOn systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible.h](h"On systems without small BAR, the }(hj+HhhhNhNubj)}(h**probed_size**h]h probed_size}(hj3HhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+Hubh will always equal the }(hj+HhhhNhNubj)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjEHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+Hubh), since all of it will be CPU accessible.}(hj+HhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjGubh)}(hNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**).h](huNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hj^HhhhNhNubj)}(h**probed_size**h]h probed_size}(hjfHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^Hubh).}(hj^HhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjGubh)}(hXNote that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**.h](hXpNote that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when }(hjHhhhNhNubj)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh == }(hjHhhhNhNubj)}(h**probed_size**h]h probed_size}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjGubeh}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjGhM hjFubj)}(hXr``unallocated_cpu_visible_size`` Estimate of CPU visible memory remaining. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**). Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**). If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](j)}(h ``unallocated_cpu_visible_size``h]jC)}(hjHh]hunallocated_cpu_visible_size}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjHubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjHubj)}(hhh](h)}(h)Estimate of CPU visible memory remaining.h]h)Estimate of CPU visible memory remaining.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjHubh)}(hNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**).h](huNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hjHhhhNhNubj)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh).}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjHubh)}(hX3Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**).h](huRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the }(hj IhhhNhNubj)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Iubh. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the }(hj IhhhNhNubj)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hj'IhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Iubh).}(hj IhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjHubh)}(h]If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](hAIf this is an older kernel the value here will be zero, see also }(hj@IhhhNhNubj)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjHIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@Iubh.}(hj@IhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjHhM hjHubeh}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhjHhM hjFubeh}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj{Ih]h Description}(hj}IhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyIubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hNote this is using both struct drm_i915_query_item and struct drm_i915_query. For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS at :c:type:`drm_i915_query_item.query_id `.h](hNote this is using both struct drm_i915_query_item and struct drm_i915_query. For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS at }(hjIhhhNhNubh)}(h<:c:type:`drm_i915_query_item.query_id `h]jC)}(hjIh]hdrm_i915_query_item.query_id}(hjIhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjIubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_query_itemuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjIubh.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjIhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW(drm_i915_query_memory_regions (C struct)c.drm_i915_query_memory_regionshNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_query_memory_regionsh]jg)}(h$struct drm_i915_query_memory_regionsh](jm)}(hjph]hstruct}(hjIhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjIhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjIhhhjIhM ubj)}(hdrm_i915_query_memory_regionsh]j)}(hjIh]hdrm_i915_query_memory_regions}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubah}(h]h ](jjeh"]h$]h&]jjuh1jhjIhhhjIhM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjIhhhjIhM ubah}(h]jIah ](jjeh"]h$]h&]jj)jhuh1j`hjIhM hjIhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjIhhhjIhM ubeh}(h]h ](jstructeh"]h$]h&]jjjj'Jjj'Jjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_query_memory_regions { __u32 num_regions; __u32 rsvd[3]; struct drm_i915_memory_region_info regions[]; }; **Members** ``num_regions`` Number of supported regions ``rsvd`` MBZ ``regions`` Info about each supported regionh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj3JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/Jubh:}(hj/JhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj+Jubj)}(hstruct drm_i915_query_memory_regions { __u32 num_regions; __u32 rsvd[3]; struct drm_i915_memory_region_info regions[]; };h]hstruct drm_i915_query_memory_regions { __u32 num_regions; __u32 rsvd[3]; struct drm_i915_memory_region_info regions[]; };}hjLJsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj+Jubh)}(h **Members**h]j)}(hj]Jh]hMembers}(hj_JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[Jubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hj+Jubj)}(hhh](j)}(h,``num_regions`` Number of supported regions h](j)}(h``num_regions``h]jC)}(hj|Jh]h num_regions}(hj~JhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjzJubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjvJubj)}(hhh]h)}(hNumber of supported regionsh]hNumber of supported regions}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMhjJubah}(h]h ]h"]h$]h&]uh1jhjvJubeh}(h]h ]h"]h$]h&]uh1jhjJhMhjsJubj)}(h ``rsvd`` MBZ h](j)}(h``rsvd``h]jC)}(hjJh]hrsvd}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjJubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM!hjJubj)}(hhh]h)}(hMBZh]hMBZ}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhM!hjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjJhM!hjsJubj)}(h,``regions`` Info about each supported regionh](j)}(h ``regions``h]jC)}(hjJh]hregions}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjJubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM#hjJubj)}(hhh]h)}(h Info about each supported regionh]h Info about each supported region}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM$hjKubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjKhM#hjsJubeh}(h]h ]h"]h$]h&]uh1jhj+Jubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hj1Kh]h Description}(hj3KhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/Kubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM'hjihhubh)}(hThe region info query enumerates all regions known to the driver by filling in an array of struct drm_i915_memory_region_info structures.h]hThe region info query enumerates all regions known to the driver by filling in an array of struct drm_i915_memory_region_info structures.}(hjGKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(h2Example for getting the list of supported regions:h]h2Example for getting the list of supported regions:}(hjVKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubj)}(hXVstruct drm_i915_query_memory_regions *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_MEMORY_REGIONS; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of regions. The kernel will fill out the // item.length for us, which is the number of bytes we need. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with the all the region info. item.data_ptr = (uintptr_t)&info, err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each region in the array for (i = 0; i < info->num_regions; i++) { struct drm_i915_memory_region_info mr = info->regions[i]; u16 class = mr.region.class; u16 instance = mr.region.instance; .... } free(info);h]hXVstruct drm_i915_query_memory_regions *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_MEMORY_REGIONS; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of regions. The kernel will fill out the // item.length for us, which is the number of bytes we need. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with the all the region info. item.data_ptr = (uintptr_t)&info, err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each region in the array for (i = 0; i < info->num_regions; i++) { struct drm_i915_memory_region_info mr = info->regions[i]; u16 class = mr.region.class; u16 instance = mr.region.instance; .... } free(info);}hjeKsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW0drm_i915_query_guc_submission_version (C struct)'c.drm_i915_query_guc_submission_versionhNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(h%drm_i915_query_guc_submission_versionh]jg)}(h,struct drm_i915_query_guc_submission_versionh](jm)}(hjph]hstruct}(hjKhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjKhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjKhhhjKhMubj)}(h%drm_i915_query_guc_submission_versionh]j)}(hjKh]h%drm_i915_query_guc_submission_version}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubah}(h]h ](jjeh"]h$]h&]jjuh1jhjKhhhjKhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjKhhhjKhMubah}(h]jKah ](jjeh"]h$]h&]jj)jhuh1j`hjKhMhjKhhubj)}(hhh]h)}(h&query GuC submission interface versionh]h&query GuC submission interface version}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM(hjKhhubah}(h]h ]h"]h$]h&]uh1jhjKhhhjKhMubeh}(h]h ](jstructeh"]h$]h&]jjjjKjjKjjjuh1j[hhhjihNhNubj)}(hX7**Definition**:: struct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; }; **Members** ``branch`` Firmware branch version. ``major`` Firmware major version. ``minor`` Firmware minor version. ``patch`` Firmware patch version.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubh:}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM,hjKubj)}(hvstruct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; };h]hvstruct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; };}hj Lsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM.hjKubh)}(h **Members**h]j)}(hjLh]hMembers}(hj LhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM5hjKubj)}(hhh](j)}(h$``branch`` Firmware branch version. h](j)}(h ``branch``h]jC)}(hj=Lh]hbranch}(hj?LhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj;Lubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM,hj7Lubj)}(hhh]h)}(hFirmware branch version.h]hFirmware branch version.}(hjVLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRLhM,hjSLubah}(h]h ]h"]h$]h&]uh1jhj7Lubeh}(h]h ]h"]h$]h&]uh1jhjRLhM,hj4Lubj)}(h"``major`` Firmware major version. h](j)}(h ``major``h]jC)}(hjvLh]hmajor}(hjxLhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjtLubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM.hjpLubj)}(hhh]h)}(hFirmware major version.h]hFirmware major version.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM.hjLubah}(h]h ]h"]h$]h&]uh1jhjpLubeh}(h]h ]h"]h$]h&]uh1jhjLhM.hj4Lubj)}(h"``minor`` Firmware minor version. h](j)}(h ``minor``h]jC)}(hjLh]hminor}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjLubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM0hjLubj)}(hhh]h)}(hFirmware minor version.h]hFirmware minor version.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM0hjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jhjLhM0hj4Lubj)}(h!``patch`` Firmware patch version.h](j)}(h ``patch``h]jC)}(hjLh]hpatch}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjLubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM1hjLubj)}(hhh]h)}(hFirmware patch version.h]hFirmware patch version.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM2hjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jhjLhM1hj4Lubeh}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubj{)}(h.. _GuC HWCONFIG blob uAPI:h]h}(h]h ]h"]h$]h&]hʌguc-hwconfig-blob-uapiuh1jzhMmhjihhhNubh)}(h**GuC HWCONFIG blob uAPI**h]j)}(hj6Mh]hGuC HWCONFIG blob uAPI}(hj8MhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4Mubah}(h]j3Mah ]h"]guc hwconfig blob uapiah$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM8hjihhj}jIMj)Msj}j3Mj)Msubh)}(hThe GuC produces a blob with information about the current device. i915 reads this blob from GuC and makes it available via this uAPI.h]hThe GuC produces a blob with information about the current device. i915 reads this blob from GuC and makes it available via this uAPI.}(hjOMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM6hjihhubh)}(h_The format and meaning of the blob content are documented in the Programmer's Reference Manual.h]haThe format and meaning of the blob content are documented in the Programmer’s Reference Manual.}(hj^MhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM9hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_i915_gem_create_ext (C struct)c.drm_i915_gem_create_exthNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_create_exth]jg)}(hstruct drm_i915_gem_create_exth](jm)}(hjph]hstruct}(hjMhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjMhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM?ubj)}(h h]h }(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjMhhhjMhM?ubj)}(hdrm_i915_gem_create_exth]j)}(hjMh]hdrm_i915_gem_create_ext}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubah}(h]h ](jjeh"]h$]h&]jjuh1jhjMhhhjMhM?ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj~MhhhjMhM?ubah}(h]jyMah ](jjeh"]h$]h&]jj)jhuh1j`hjMhM?hj{Mhhubj)}(hhh]h)}(h]Existing gem_create behaviour, with added extension support using struct i915_user_extension.h]h]Existing gem_create behaviour, with added extension support using struct i915_user_extension.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM@hjMhhubah}(h]h ]h"]h$]h&]uh1jhj{MhhhjMhM?ubeh}(h]h ](jstructeh"]h$]h&]jjjjMjjMjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; }; **Members** ``size`` Requested size for the object. The (page-aligned) allocated size for the object will be returned. On platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects. NOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications: 1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. However on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K. ``handle`` Returned handle for the object. Object handles are nonzero. ``flags`` Optional flags. Supported values: I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU. Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size ` for how to determine if this system applies. Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE. Also note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS. Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided. On older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed. ``extensions`` The chain of extensions to apply to this object. This will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension. If we don't supply any extensions then we get the same old gem_create behaviour. For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions. For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content. For I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubh:}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMDhjMubj)}(hX.struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; };h]hX.struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; };}hjNsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMFhjMubh)}(h **Members**h]j)}(hjNh]hMembers}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMQhjMubj)}(hhh](j)}(hX``size`` Requested size for the object. The (page-aligned) allocated size for the object will be returned. On platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects. NOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications: 1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. However on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K. h](j)}(h``size``h]jC)}(hj5Nh]hsize}(hj7NhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj3Nubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMbhj/Nubj)}(hhh](h)}(hRequested size for the object.h]hRequested size for the object.}(hjNNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMLhjKNubh)}(hBThe (page-aligned) allocated size for the object will be returned.h]hBThe (page-aligned) allocated size for the object will be returned.}(hj]NhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMNhjKNubh)}(hOn platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects.h]hOn platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects.}(hjlNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMPhjKNubh)}(hNOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications:h]hNOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications:}(hj{NhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMThjKNubjK)}(h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. h](h)}(h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware.h]h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMXhjNubh)}(hI2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects.h]hI2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM\hjNubeh}(h]h ]h"]h$]h&]uh1jJhjNhMXhjKNubh)}(hHowever on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K.h]hHowever on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM_hjKNubeh}(h]h ]h"]h$]h&]uh1jhj/Nubeh}(h]h ]h"]h$]h&]uh1jhjJNhMbhj,Nubj)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]jC)}(hjNh]hhandle}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjNubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMihjNubj)}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMghjNubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhMihjNubeh}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjNhMihj,Nubj)}(hX``flags`` Optional flags. Supported values: I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU. Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size ` for how to determine if this system applies. Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE. Also note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS. Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided. On older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed. h](j)}(h ``flags``h]jC)}(hjOh]hflags}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjOubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjOubj)}(hhh](h)}(hOptional flags.h]hOptional flags.}(hj4OhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMnhj1Oubh)}(hSupported values:h]hSupported values:}(hjCOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMphj1Oubh)}(hvI915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU.h]hvI915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU.}(hjROhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMrhj1Oubh)}(hXOnly valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size ` for how to determine if this system applies.h](hXOnly valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it’s something we can expect to see in the wild. See }(hjaOhhhNhNubh)}(h[:c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `h]jC)}(hjkOh]h3drm_i915_memory_region_info.probed_cpu_visible_size}(hjmOhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjiOubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_memory_region_infouh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMuhjaOubh- for how to determine if this system applies.}(hjaOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjOhMuhj1Oubh)}(hNote that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE.h]hNote that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can’t be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM~hj1Oubh)}(hAlso note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS.h](hKAlso note that since the kernel only supports flat-CCS on objects that can }(hjOhhhNhNubhemphasis)}(h*only*h]honly}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjOubh be placed in I915_MEMORY_CLASS_DEVICE, we therefore don’t support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS.}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj1Oubh)}(hX5Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided.h]hX5Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj1Oubh)}(hXOn older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed.h](hJOn older kernels which lack the relevant small-bar uAPI support (see also }(hjOhhhNhNubh)}(h[:c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `h]jC)}(hjOh]h3drm_i915_memory_region_info.probed_cpu_visible_size}(hjOhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjOubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_memory_region_infouh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjOubhXR), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed.}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjOhMhj1Oubeh}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhj0OhMhj,Nubj)}(hXb``extensions`` The chain of extensions to apply to this object. This will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension. If we don't supply any extensions then we get the same old gem_create behaviour. For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions. For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content. For I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h](j)}(h``extensions``h]jC)}(hjPh]h extensions}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjPubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjPubj)}(hhh](h)}(h0The chain of extensions to apply to this object.h]h0The chain of extensions to apply to this object.}(hj1PhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj.Pubh)}(hThis will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension.h]hThis will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension.}(hj@PhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj.Pubh)}(hPIf we don't supply any extensions then we get the same old gem_create behaviour.h]hRIf we don’t supply any extensions then we get the same old gem_create behaviour.}(hjOPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj.Pubh)}(h_For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions.h]h_For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions.}(hj^PhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj.Pubh)}(heFor I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content.h]heFor I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content.}(hjmPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj.Pubh)}(hQFor I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h]hQFor I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.}(hj|PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-PhMhj.Pubeh}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhj-PhMhj,Nubeh}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjPh]h Description}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hXcNote that new buffer flags should be added here, at least for the stuff that is immutable. Previously we would have two ioctls, one to create the object with gem_create, and another to apply various parameters, however this creates some ambiguity for the params which are considered immutable. Also in general we're phasing out the various SET/GET ioctls.h]hXeNote that new buffer flags should be added here, at least for the stuff that is immutable. Previously we would have two ioctls, one to create the object with gem_create, and another to apply various parameters, however this creates some ambiguity for the params which are considered immutable. Also in general we’re phasing out the various SET/GET ioctls.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMAhjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW1drm_i915_gem_create_ext_memory_regions (C struct)(c.drm_i915_gem_create_ext_memory_regionshNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(h&drm_i915_gem_create_ext_memory_regionsh]jg)}(h-struct drm_i915_gem_create_ext_memory_regionsh](jm)}(hjph]hstruct}(hjPhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjPhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMJubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjPhhhjPhMJubj)}(h&drm_i915_gem_create_ext_memory_regionsh]j)}(hjPh]h&drm_i915_gem_create_ext_memory_regions}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubah}(h]h ](jjeh"]h$]h&]jjuh1jhjPhhhjPhMJubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjPhhhjPhMJubah}(h]jPah ](jjeh"]h$]h&]jj)jhuh1j`hjPhMJhjPhhubj)}(hhh]h)}(h1The I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.h]h1The I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.}(hj%QhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj"Qhhubah}(h]h ]h"]h$]h&]uh1jhjPhhhjPhMJubeh}(h]h ](jstructeh"]h$]h&]jjjj=Qjj=Qjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``pad`` MBZ ``num_regions`` Number of elements in the **regions** array. ``regions`` The regions/placements array. An array of struct drm_i915_gem_memory_class_instance.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjIQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEQubh:}(hjEQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjAQubj)}(hstruct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; };h]hstruct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; };}hjbQsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjAQubh)}(h **Members**h]j)}(hjsQh]hMembers}(hjuQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqQubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjAQubj)}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]jC)}(hjQh]hbase}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjQubj)}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhMhjQubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjQhMhjQubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjQh]hpad}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjQubj)}(hhh]h)}(hMBZh]hMBZ}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhMhjQubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjQhMhjQubj)}(h=``num_regions`` Number of elements in the **regions** array. h](j)}(h``num_regions``h]jC)}(hjRh]h num_regions}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjRubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjQubj)}(hhh]h)}(h,Number of elements in the **regions** array.h](hNumber of elements in the }(hjRhhhNhNubj)}(h **regions**h]hregions}(hj%RhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubh array.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjRhMhjRubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjRhMhjQubj)}(ha``regions`` The regions/placements array. An array of struct drm_i915_gem_memory_class_instance.h](j)}(h ``regions``h]jC)}(hjORh]hregions}(hjQRhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjMRubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjIRubj)}(hhh](h)}(hThe regions/placements array.h]hThe regions/placements array.}(hjhRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjeRubh)}(h6An array of struct drm_i915_gem_memory_class_instance.h]h6An array of struct drm_i915_gem_memory_class_instance.}(hjwRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjeRubeh}(h]h ]h"]h$]h&]uh1jhjIRubeh}(h]h ]h"]h$]h&]uh1jhjdRhMhjQubeh}(h]h ]h"]h$]h&]uh1jhjAQubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjRh]h Description}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hSet the object with the desired set of placements/regions in priority order. Each entry must be unique and supported by the device.h]hSet the object with the desired set of placements/regions in priority order. Each entry must be unique and supported by the device.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hXThis is provided as an array of struct drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance pair encodings. See struct drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to query the supported regions for a device.h]hXThis is provided as an array of struct drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance pair encodings. See struct drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to query the supported regions for a device.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(htAs an example, on discrete devices, if we wish to set the placement as device local-memory we can do something like:h]htAs an example, on discrete devices, if we wish to set the placement as device local-memory we can do something like:}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubj)}(hXstruct drm_i915_gem_memory_class_instance region_lmem = { .memory_class = I915_MEMORY_CLASS_DEVICE, .memory_instance = 0, }; struct drm_i915_gem_create_ext_memory_regions regions = { .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, .regions = (uintptr_t)®ion_lmem, .num_regions = 1, }; struct drm_i915_gem_create_ext create_ext = { .size = 16 * PAGE_SIZE, .extensions = (uintptr_t)®ions, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...h]hXstruct drm_i915_gem_memory_class_instance region_lmem = { .memory_class = I915_MEMORY_CLASS_DEVICE, .memory_instance = 0, }; struct drm_i915_gem_create_ext_memory_regions regions = { .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, .regions = (uintptr_t)®ion_lmem, .num_regions = 1, }; struct drm_i915_gem_create_ext create_ext = { .size = 16 * PAGE_SIZE, .extensions = (uintptr_t)®ions, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...}hjRsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hX At which point we get the object handle in :c:type:`drm_i915_gem_create_ext.handle `, along with the final object size in :c:type:`drm_i915_gem_create_ext.size `, which should account for any rounding up, if required.h](h+At which point we get the object handle in }(hjRhhhNhNubh)}(hB:c:type:`drm_i915_gem_create_ext.handle `h]jC)}(hjRh]hdrm_i915_gem_create_ext.handle}(hjShhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjRubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_gem_create_extuh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjRubh&, along with the final object size in }(hjRhhhNhNubh)}(h@:c:type:`drm_i915_gem_create_ext.size `h]jC)}(hj"Sh]hdrm_i915_gem_create_ext.size}(hj$ShhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj Subah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_i915_gem_create_extuh1hhjShMhjRubh8, which should account for any rounding up, if required.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjShMhjihhubh)}(hX4Note that userspace has no means of knowing the current backing region for objects where **num_regions** is larger than one. The kernel will only ensure that the priority order of the **regions** array is honoured, either when initially placing the object, or when moving memory around due to memory pressureh](hYNote that userspace has no means of knowing the current backing region for objects where }(hjIShhhNhNubj)}(h**num_regions**h]h num_regions}(hjQShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjISubhP is larger than one. The kernel will only ensure that the priority order of the }(hjIShhhNhNubj)}(h **regions**h]hregions}(hjcShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjISubhq array is honoured, either when initially placing the object, or when moving memory around due to memory pressure}(hjIShhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hXOn Flat-CCS capable HW, compression is supported for the objects residing in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other memory class in **regions** and migrated (by i915, due to memory constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to decompress the content. But i915 doesn't have the required information to decompress the userspace compressed objects.h](hOn Flat-CCS capable HW, compression is supported for the objects residing in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other memory class in }(hj|ShhhNhNubj)}(h **regions**h]hregions}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|Subh and migrated (by i915, due to memory constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to decompress the content. But i915 doesn’t have the required information to decompress the userspace compressed objects.}(hj|ShhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hdSo i915 supports Flat-CCS, on the objects which can reside only on I915_MEMORY_CLASS_DEVICE regions.h]hdSo i915 supports Flat-CCS, on the objects which can reside only on I915_MEMORY_CLASS_DEVICE regions.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW4drm_i915_gem_create_ext_protected_content (C struct)+c.drm_i915_gem_create_ext_protected_contenthNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(h)drm_i915_gem_create_ext_protected_contenth]jg)}(h0struct drm_i915_gem_create_ext_protected_contenth](jm)}(hjph]hstruct}(hjShhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjShhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjShhhjShMubj)}(h)drm_i915_gem_create_ext_protected_contenth]j)}(hjSh]h)drm_i915_gem_create_ext_protected_content}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ](jjeh"]h$]h&]jjuh1jhjShhhjShMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjShhhjShMubah}(h]jSah ](jjeh"]h$]h&]jj)jhuh1j`hjShMhjShhubj)}(hhh]h)}(h2The I915_OBJECT_PARAM_PROTECTED_CONTENT extension.h]h2The I915_OBJECT_PARAM_PROTECTED_CONTENT extension.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjThhubah}(h]h ]h"]h$]h&]uh1jhjShhhjShMubeh}(h]h ](jstructeh"]h$]h&]jjjjTjjTjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_create_ext_protected_content { struct i915_user_extension base; __u32 flags; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``flags`` reserved for future usage, currently MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj+ThhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'Tubh:}(hj'ThhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj#Tubj)}(hkstruct drm_i915_gem_create_ext_protected_content { struct i915_user_extension base; __u32 flags; };h]hkstruct drm_i915_gem_create_ext_protected_content { struct i915_user_extension base; __u32 flags; };}hjDTsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj#Tubh)}(h **Members**h]j)}(hjUTh]hMembers}(hjWThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSTubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhj#Tubj)}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]jC)}(hjtTh]hbase}(hjvThhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjrTubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjnTubj)}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThMhjTubah}(h]h ]h"]h$]h&]uh1jhjnTubeh}(h]h ]h"]h$]h&]uh1jhjThMhjkTubj)}(h2``flags`` reserved for future usage, currently MBZh](j)}(h ``flags``h]jC)}(hjTh]hflags}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjTubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjTubj)}(hhh]h)}(h(reserved for future usage, currently MBZh]h(reserved for future usage, currently MBZ}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jhjThMhjkTubeh}(h]h ]h"]h$]h&]uh1jhj#Tubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjTh]h Description}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubh)}(hXIf this extension is provided, buffer contents are expected to be protected by PXP encryption and require decryption for scan out and processing. This is only possible on platforms that have PXP enabled, on all other scenarios using this extension will cause the ioctl to fail and return -ENODEV. The flags parameter is reserved for future expansion and must currently be set to zero.h]hXIf this extension is provided, buffer contents are expected to be protected by PXP encryption and require decryption for scan out and processing. This is only possible on platforms that have PXP enabled, on all other scenarios using this extension will cause the ioctl to fail and return -ENODEV. The flags parameter is reserved for future expansion and must currently be set to zero.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hHThe buffer contents are considered invalid after a PXP session teardown.h]hHThe buffer contents are considered invalid after a PXP session teardown./}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(hXThe encryption is guaranteed to be processed correctly only if the object is submitted with a context created using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks at submission time on the validity of the objects involved.h]hXThe encryption is guaranteed to be processed correctly only if the object is submitted with a context created using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks at submission time on the validity of the objects involved.}(hj$UhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubh)}(h8Below is an example on how to create a protected object:h]h8Below is an example on how to create a protected object:}(hj3UhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMhjihhubj)}(hXhstruct drm_i915_gem_create_ext_protected_content protected_ext = { .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT }, .flags = 0, }; struct drm_i915_gem_create_ext create_ext = { .size = PAGE_SIZE, .extensions = (uintptr_t)&protected_ext, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...h]hXhstruct drm_i915_gem_create_ext_protected_content protected_ext = { .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT }, .flags = 0, }; struct drm_i915_gem_create_ext create_ext = { .size = PAGE_SIZE, .extensions = (uintptr_t)&protected_ext, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...}hjBUsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM hjihhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW*drm_i915_gem_create_ext_set_pat (C struct)!c.drm_i915_gem_create_ext_set_pathNtauh1jJhjihhhNhNubj\)}(hhh](ja)}(hdrm_i915_gem_create_ext_set_path]jg)}(h&struct drm_i915_gem_create_ext_set_path](jm)}(hjph]hstruct}(hjkUhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjgUhhh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjyUhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjgUhhhjxUhMubj)}(hdrm_i915_gem_create_ext_set_path]j)}(hjeUh]hdrm_i915_gem_create_ext_set_pat}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubah}(h]h ](jjeh"]h$]h&]jjuh1jhjgUhhhjxUhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjcUhhhjxUhMubah}(h]j^Uah ](jjeh"]h$]h&]jj)jhuh1j`hjxUhMhj`Uhhubj)}(hhh]h)}(h*The I915_GEM_CREATE_EXT_SET_PAT extension.h]h*The I915_GEM_CREATE_EXT_SET_PAT extension.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM!hjUhhubah}(h]h ]h"]h$]h&]uh1jhj`UhhhjxUhMubeh}(h]h ](jstructeh"]h$]h&]jjjjUjjUjjjuh1j[hhhjihNhNubj)}(hX**Definition**:: struct drm_i915_gem_create_ext_set_pat { struct i915_user_extension base; __u32 pat_index; __u32 rsvd; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``pat_index`` PAT index to be set PAT index is a bit field in Page Table Entry to control caching behaviors for GPU accesses. The definition of PAT index is platform dependent and can be found in hardware specifications, ``rsvd`` reserved for future useh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubh:}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM%hjUubj)}(hustruct drm_i915_gem_create_ext_set_pat { struct i915_user_extension base; __u32 pat_index; __u32 rsvd; };h]hustruct drm_i915_gem_create_ext_set_pat { struct i915_user_extension base; __u32 pat_index; __u32 rsvd; };}hjUsbah}(h]h ]h"]h$]h&]jjuh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM'hjUubh)}(h **Members**h]j)}(hjUh]hMembers}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM-hjUubj)}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]jC)}(hjVh]hbase}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjVubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM9hjVubj)}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hj3VhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/VhM9hj0Vubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhj/VhM9hjVubj)}(h``pat_index`` PAT index to be set PAT index is a bit field in Page Table Entry to control caching behaviors for GPU accesses. The definition of PAT index is platform dependent and can be found in hardware specifications, h](j)}(h ``pat_index``h]jC)}(hjSVh]h pat_index}(hjUVhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQVubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM?hjMVubj)}(hhh]h)}(hPAT index to be set PAT index is a bit field in Page Table Entry to control caching behaviors for GPU accesses. The definition of PAT index is platform dependent and can be found in hardware specifications,h]hPAT index to be set PAT index is a bit field in Page Table Entry to control caching behaviors for GPU accesses. The definition of PAT index is platform dependent and can be found in hardware specifications,}(hjlVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM<hjiVubah}(h]h ]h"]h$]h&]uh1jhjMVubeh}(h]h ]h"]h$]h&]uh1jhjhVhM?hjVubj)}(h ``rsvd`` reserved for future useh](j)}(h``rsvd``h]jC)}(hjVh]hrsvd}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjVubah}(h]h ]h"]h$]h&]uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMAhjVubj)}(hhh]h)}(hreserved for future useh]hreserved for future use}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMBhjVubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjVhMAhjVubeh}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjihhhNhNubh)}(h**Description**h]j)}(hjVh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhMEhjihhubh)}(hhIf this extension is provided, the specified caching policy (PAT index) is applied to the buffer object.h]hhIf this extension is provided, the specified caching policy (PAT index) is applied to the buffer object.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM"hjihhubh)}(hLBelow is an example on how to create an object with specific caching policy:h]hLBelow is an example on how to create an object with specific caching policy:}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM%hjihhubj)}(hXTstruct drm_i915_gem_create_ext_set_pat set_pat_ext = { .base = { .name = I915_GEM_CREATE_EXT_SET_PAT }, .pat_index = 0, }; struct drm_i915_gem_create_ext create_ext = { .size = PAGE_SIZE, .extensions = (uintptr_t)&set_pat_ext, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...h]hXTstruct drm_i915_gem_create_ext_set_pat set_pat_ext = { .base = { .name = I915_GEM_CREATE_EXT_SET_PAT }, .pat_index = 0, }; struct drm_i915_gem_create_ext create_ext = { .size = PAGE_SIZE, .extensions = (uintptr_t)&set_pat_ext, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...}hjWsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jh[/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:10: ./include/uapi/drm/i915_drm.hhM'hjihhubeh}(h]jah ]h"] drm/i915 uapiah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hdrm/nouveau uAPIh]hdrm/nouveau uAPI}(hjWhhhNhNubah}(h]h ]h"]h$]h&]hj;uh1hhjWhhhhhK ubh)}(hhh](h)}(hVM_BIND / EXEC uAPIh]hVM_BIND / EXEC uAPI}(hj/WhhhNhNubah}(h]h ]h"]h$]h&]hjZuh1hhj,WhhhhhKubh)}(hvNouveau's VM_BIND / EXEC UAPI consists of three ioctls: DRM_NOUVEAU_VM_INIT, DRM_NOUVEAU_VM_BIND and DRM_NOUVEAU_EXEC.h]hxNouveau’s VM_BIND / EXEC UAPI consists of three ioctls: DRM_NOUVEAU_VM_INIT, DRM_NOUVEAU_VM_BIND and DRM_NOUVEAU_EXEC.}(hj=WhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chKhj,Whhubh)}(hIn order to use the UAPI firstly a user client must initialize the VA space using the DRM_NOUVEAU_VM_INIT ioctl specifying which region of the VA space should be managed by the kernel and which by the UMD.h]hIn order to use the UAPI firstly a user client must initialize the VA space using the DRM_NOUVEAU_VM_INIT ioctl specifying which region of the VA space should be managed by the kernel and which by the UMD.}(hjLWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chKhj,Whhubh)}(hXDThe DRM_NOUVEAU_VM_BIND ioctl provides clients an interface to manage the userspace-managable portion of the VA space. It provides operations to map and unmap memory. Mappings may be flagged as sparse. Sparse mappings are not backed by a GEM object and the kernel will ignore GEM handles provided alongside a sparse mapping.h]hXDThe DRM_NOUVEAU_VM_BIND ioctl provides clients an interface to manage the userspace-managable portion of the VA space. It provides operations to map and unmap memory. Mappings may be flagged as sparse. Sparse mappings are not backed by a GEM object and the kernel will ignore GEM handles provided alongside a sparse mapping.}(hj[WhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chKhj,Whhubh)}(hXBUserspace may request memory backed mappings either within or outside of the bounds (but not crossing those bounds) of a previously mapped sparse mapping. Subsequently requested memory backed mappings within a sparse mapping will take precedence over the corresponding range of the sparse mapping. If such memory backed mappings are unmapped the kernel will make sure that the corresponding sparse mapping will take their place again. Requests to unmap a sparse mapping that still contains memory backed mappings will result in those memory backed mappings being unmapped first.h]hXBUserspace may request memory backed mappings either within or outside of the bounds (but not crossing those bounds) of a previously mapped sparse mapping. Subsequently requested memory backed mappings within a sparse mapping will take precedence over the corresponding range of the sparse mapping. If such memory backed mappings are unmapped the kernel will make sure that the corresponding sparse mapping will take their place again. Requests to unmap a sparse mapping that still contains memory backed mappings will result in those memory backed mappings being unmapped first.}(hjjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chKhj,Whhubh)}(hXUnmap requests are not bound to the range of existing mappings and can even overlap the bounds of sparse mappings. For such a request the kernel will make sure to unmap all memory backed mappings within the given range, splitting up memory backed mappings which are only partially contained within the given range. Unmap requests with the sparse flag set must match the range of a previously mapped sparse mapping exactly though.h]hXUnmap requests are not bound to the range of existing mappings and can even overlap the bounds of sparse mappings. For such a request the kernel will make sure to unmap all memory backed mappings within the given range, splitting up memory backed mappings which are only partially contained within the given range. Unmap requests with the sparse flag set must match the range of a previously mapped sparse mapping exactly though.}(hjyWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chK&hj,Whhubh)}(hWhile the kernel generally permits arbitrary sequences and ranges of memory backed mappings being mapped and unmapped, either within a single or multiple VM_BIND ioctl calls, there are some restrictions for sparse mappings.h]hWhile the kernel generally permits arbitrary sequences and ranges of memory backed mappings being mapped and unmapped, either within a single or multiple VM_BIND ioctl calls, there are some restrictions for sparse mappings.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chK-hj,Whhubj)}(hhh]j)}(hXxThe kernel does not permit to: - unmap non-existent sparse mappings - unmap a sparse mapping and map a new sparse mapping overlapping the range of the previously unmapped sparse mapping within the same VM_BIND ioctl - unmap a sparse mapping and map new memory backed mappings overlapping the range of the previously unmapped sparse mapping within the same VM_BIND ioctl h](j)}(hThe kernel does not permit to:h]hThe kernel does not permit to:}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chK7hjWubj)}(hhh]h)}(hhh](h)}(h"unmap non-existent sparse mappingsh]h)}(hjWh]h"unmap non-existent sparse mappings}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chK2hjWubah}(h]h ]h"]h$]h&]uh1hhjWubh)}(hunmap a sparse mapping and map a new sparse mapping overlapping the range of the previously unmapped sparse mapping within the same VM_BIND ioctlh]h)}(hunmap a sparse mapping and map a new sparse mapping overlapping the range of the previously unmapped sparse mapping within the same VM_BIND ioctlh]hunmap a sparse mapping and map a new sparse mapping overlapping the range of the previously unmapped sparse mapping within the same VM_BIND ioctl}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chK3hjWubah}(h]h ]h"]h$]h&]uh1hhjWubh)}(hunmap a sparse mapping and map new memory backed mappings overlapping the range of the previously unmapped sparse mapping within the same VM_BIND ioctl h]h)}(hunmap a sparse mapping and map new memory backed mappings overlapping the range of the previously unmapped sparse mapping within the same VM_BIND ioctlh]hunmap a sparse mapping and map new memory backed mappings overlapping the range of the previously unmapped sparse mapping within the same VM_BIND ioctl}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chK5hjWubah}(h]h ]h"]h$]h&]uh1hhjWubeh}(h]h ]h"]h$]h&]j j uh1hhjWhK2hjWubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jhjWhK7hjWubah}(h]h ]h"]h$]h&]uh1jhj,Whhhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chNubh)}(hXWhen using the VM_BIND ioctl to request the kernel to map memory to a given virtual address in the GPU's VA space there is no guarantee that the actual mappings are created in the GPU's MMU. If the given memory is swapped out at the time the bind operation is executed the kernel will stash the mapping details into it's internal allocator and create the actual MMU mappings once the memory is swapped back in. While this is transparent for userspace, it is guaranteed that all the backing memory is swapped back in and all the memory mappings, as requested by userspace previously, are actually mapped once the DRM_NOUVEAU_EXEC ioctl is called to submit an exec job.h]hXWhen using the VM_BIND ioctl to request the kernel to map memory to a given virtual address in the GPU’s VA space there is no guarantee that the actual mappings are created in the GPU’s MMU. If the given memory is swapped out at the time the bind operation is executed the kernel will stash the mapping details into it’s internal allocator and create the actual MMU mappings once the memory is swapped back in. While this is transparent for userspace, it is guaranteed that all the backing memory is swapped back in and all the memory mappings, as requested by userspace previously, are actually mapped once the DRM_NOUVEAU_EXEC ioctl is called to submit an exec job.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chK9hj,Whhubh)}(hXA VM_BIND job can be executed either synchronously or asynchronously. If executed asynchronously, userspace may provide a list of syncobjs this job will wait for and/or a list of syncobj the kernel will signal once the VM_BIND job finished execution. If executed synchronously the ioctl will block until the bind job is finished. For synchronous jobs the kernel will not permit any syncobjs submitted to the kernel.h]hXA VM_BIND job can be executed either synchronously or asynchronously. If executed asynchronously, userspace may provide a list of syncobjs this job will wait for and/or a list of syncobj the kernel will signal once the VM_BIND job finished execution. If executed synchronously the ioctl will block until the bind job is finished. For synchronous jobs the kernel will not permit any syncobjs submitted to the kernel.}(hj%XhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chKChj,Whhubh)}(hTo execute a push buffer the UAPI provides the DRM_NOUVEAU_EXEC ioctl. EXEC jobs are always executed asynchronously, and, equal to VM_BIND jobs, provide the option to synchronize them with syncobjs.h]hTo execute a push buffer the UAPI provides the DRM_NOUVEAU_EXEC ioctl. EXEC jobs are always executed asynchronously, and, equal to VM_BIND jobs, provide the option to synchronize them with syncobjs.}(hj4XhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chKJhj,Whhubh)}(hOBesides that, EXEC jobs can be scheduled for a specified channel to execute on.h]hOBesides that, EXEC jobs can be scheduled for a specified channel to execute on.}(hjCXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chKNhj,Whhubh)}(hX$Since VM_BIND jobs update the GPU's VA space on job submit, EXEC jobs do have an up to date view of the VA space. However, the actual mappings might still be pending. Hence, EXEC jobs require to have the particular fences - of the corresponding VM_BIND jobs they depend on - attached to them.h]hX&Since VM_BIND jobs update the GPU’s VA space on job submit, EXEC jobs do have an up to date view of the VA space. However, the actual mappings might still be pending. Hence, EXEC jobs require to have the particular fences - of the corresponding VM_BIND jobs they depend on - attached to them.}(hjRXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:18: ./drivers/gpu/drm/nouveau/nouveau_exec.chKPhj,WhhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_nouveau_sync (C struct)c.drm_nouveau_synchNtauh1jJhj,WhhhNhNubj\)}(hhh](ja)}(hdrm_nouveau_synch]jg)}(hstruct drm_nouveau_synch](jm)}(hjph]hstruct}(hjzXhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjvXhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKubj)}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjvXhhhjXhKubj)}(hdrm_nouveau_synch]j)}(hjtXh]hdrm_nouveau_sync}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubah}(h]h ](jjeh"]h$]h&]jjuh1jhjvXhhhjXhKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjrXhhhjXhKubah}(h]jmXah ](jjeh"]h$]h&]jj)jhuh1j`hjXhKhjoXhhubj)}(hhh]h)}(h sync objecth]h sync object}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhjXhhubah}(h]h ]h"]h$]h&]uh1jhjoXhhhjXhKubeh}(h]h ](jstructeh"]h$]h&]jjjjXjjXjjjuh1j[hhhj,WhNhNubj)}(hX!**Definition**:: struct drm_nouveau_sync { __u32 flags; #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0; #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1; #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf; __u32 handle; __u64 timeline_value; }; **Members** ``flags`` the flags for a sync object The first 8 bits are used to determine the type of the sync object. ``handle`` the handle of the sync object ``timeline_value`` The timeline point of the sync object in case the syncobj is of type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh:}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhjXubj)}(hstruct drm_nouveau_sync { __u32 flags; #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0; #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1; #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf; __u32 handle; __u64 timeline_value; };h]hstruct drm_nouveau_sync { __u32 flags; #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0; #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1; #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf; __u32 handle; __u64 timeline_value; };}hjXsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhjXubh)}(h **Members**h]j)}(hj Yh]hMembers}(hj YhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhjXubj)}(hhh](j)}(hk``flags`` the flags for a sync object The first 8 bits are used to determine the type of the sync object. h](j)}(h ``flags``h]jC)}(hj)Yh]hflags}(hj+YhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj'Yubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhj#Yubj)}(hhh](h)}(hthe flags for a sync objecth]hthe flags for a sync object}(hjBYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhj?Yubh)}(hCThe first 8 bits are used to determine the type of the sync object.h]hCThe first 8 bits are used to determine the type of the sync object.}(hjQYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>YhKhj?Yubeh}(h]h ]h"]h$]h&]uh1jhj#Yubeh}(h]h ]h"]h$]h&]uh1jhj>YhKhj Yubj)}(h)``handle`` the handle of the sync object h](j)}(h ``handle``h]jC)}(hjqYh]hhandle}(hjsYhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjoYubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhjkYubj)}(hhh]h)}(hthe handle of the sync objecth]hthe handle of the sync object}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhKhjYubah}(h]h ]h"]h$]h&]uh1jhjkYubeh}(h]h ]h"]h$]h&]uh1jhjYhKhj Yubj)}(hz``timeline_value`` The timeline point of the sync object in case the syncobj is of type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.h](j)}(h``timeline_value``h]jC)}(hjYh]htimeline_value}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjYubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhjYubj)}(hhh]h)}(hgThe timeline point of the sync object in case the syncobj is of type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.h]hgThe timeline point of the sync object in case the syncobj is of type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhKhjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jhjYhKhj Yubeh}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj,WhhhNhNubh)}(h**Description**h]j)}(hjYh]h Description}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhj,Whhubh)}(huThis structure serves as synchronization mechanism for (potentially) asynchronous operations such as EXEC or VM_BIND.h]huThis structure serves as synchronization mechanism for (potentially) asynchronous operations such as EXEC or VM_BIND.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhj,WhhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_nouveau_vm_init (C struct)c.drm_nouveau_vm_inithNtauh1jJhj,WhhhNhNubj\)}(hhh](ja)}(hdrm_nouveau_vm_inith]jg)}(hstruct drm_nouveau_vm_inith](jm)}(hjph]hstruct}(hj*ZhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj&Zhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKubj)}(h h]h }(hj8ZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj&Zhhhj7ZhKubj)}(hdrm_nouveau_vm_inith]j)}(hj$Zh]hdrm_nouveau_vm_init}(hjJZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFZubah}(h]h ](jjeh"]h$]h&]jjuh1jhj&Zhhhj7ZhKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj"Zhhhj7ZhKubah}(h]jZah ](jjeh"]h$]h&]jj)jhuh1j`hj7ZhKhjZhhubj)}(hhh]h)}(hGPU VA space init structureh]hGPU VA space init structure}(hjlZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhjiZhhubah}(h]h ]h"]h$]h&]uh1jhjZhhhj7ZhKubeh}(h]h ](jstructeh"]h$]h&]jjjjZjjZjjjuh1j[hhhj,WhNhNubj)}(hX&**Definition**:: struct drm_nouveau_vm_init { __u64 kernel_managed_addr; __u64 kernel_managed_size; }; **Members** ``kernel_managed_addr`` start address of the kernel managed VA space region ``kernel_managed_size`` size of the kernel managed VA space region in bytesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubh:}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjZubj)}(h]struct drm_nouveau_vm_init { __u64 kernel_managed_addr; __u64 kernel_managed_size; };h]h]struct drm_nouveau_vm_init { __u64 kernel_managed_addr; __u64 kernel_managed_size; };}hjZsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjZubh)}(h **Members**h]j)}(hjZh]hMembers}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM hjZubj)}(hhh](j)}(hL``kernel_managed_addr`` start address of the kernel managed VA space region h](j)}(h``kernel_managed_addr``h]jC)}(hjZh]hkernel_managed_addr}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjZubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM hjZubj)}(hhh]h)}(h3start address of the kernel managed VA space regionh]h3start address of the kernel managed VA space region}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM hjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjZhM hjZubj)}(hK``kernel_managed_size`` size of the kernel managed VA space region in bytesh](j)}(h``kernel_managed_size``h]jC)}(hj[h]hkernel_managed_size}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj[ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj [ubj)}(hhh]h)}(h3size of the kernel managed VA space region in bytesh]h3size of the kernel managed VA space region in bytes}(hj,[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj([hMhj)[ubah}(h]h ]h"]h$]h&]uh1jhj [ubeh}(h]h ]h"]h$]h&]uh1jhj([hMhjZubeh}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj,WhhhNhNubh)}(h**Description**h]j)}(hjU[h]h Description}(hjW[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjS[ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj,Whhubh)}(hUsed to initialize the GPU's VA space for a user client, telling the kernel which portion of the VA space is managed by the UMD and kernel respectively.h]hUsed to initialize the GPU’s VA space for a user client, telling the kernel which portion of the VA space is managed by the UMD and kernel respectively.}(hjk[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhKhj,Whhubh)}(hFor the UMD to use the VM_BIND uAPI, this must be called before any BOs or channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails with -ENOSYS.h]hFor the UMD to use the VM_BIND uAPI, this must be called before any BOs or channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails with -ENOSYS.}(hjz[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj,WhhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW!drm_nouveau_vm_bind_op (C struct)c.drm_nouveau_vm_bind_ophNtauh1jJhj,WhhhNhNubj\)}(hhh](ja)}(hdrm_nouveau_vm_bind_oph]jg)}(hstruct drm_nouveau_vm_bind_oph](jm)}(hjph]hstruct}(hj[hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj[hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM ubj)}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj[hhhj[hM ubj)}(hdrm_nouveau_vm_bind_oph]j)}(hj[h]hdrm_nouveau_vm_bind_op}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj[hhhj[hM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj[hhhj[hM ubah}(h]j[ah ](jjeh"]h$]h&]jj)jhuh1j`hj[hM hj[hhubj)}(hhh]h)}(hVM_BIND operationh]hVM_BIND operation}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj[hhubah}(h]h ]h"]h$]h&]uh1jhj[hhhj[hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj[jj[jjjuh1j[hhhj,WhNhNubj)}(hX**Definition**:: struct drm_nouveau_vm_bind_op { __u32 op; #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0; #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1; __u32 flags; #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8); __u32 handle; __u32 pad; __u64 addr; __u64 bo_offset; __u64 range; }; **Members** ``op`` the operation type Supported values: ``DRM_NOUVEAU_VM_BIND_OP_MAP`` - Map a GEM object to the GPU's VA space. Optionally, the :c:type:`DRM_NOUVEAU_VM_BIND_SPARSE` flag can be passed to instruct the kernel to create sparse mappings for the given range. ``DRM_NOUVEAU_VM_BIND_OP_UNMAP`` - Unmap an existing mapping in the GPU's VA space. If the region the mapping is located in is a sparse region, new sparse mappings are created where the unmapped (memory backed) mapping was mapped previously. To remove a sparse region the :c:type:`DRM_NOUVEAU_VM_BIND_SPARSE` must be set. ``flags`` the flags for a :c:type:`drm_nouveau_vm_bind_op` Supported values: ``DRM_NOUVEAU_VM_BIND_SPARSE`` - Indicates that an allocated VA space region should be sparse. ``handle`` the handle of the DRM GEM object to map ``pad`` 32 bit padding, should be 0 ``addr`` the address the VA space region or (memory backed) mapping should be mapped to ``bo_offset`` the offset within the BO backing the mapping ``range`` the size of the requested mapping in bytesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh:}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj\ubj)}(hXstruct drm_nouveau_vm_bind_op { __u32 op; #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0; #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1; __u32 flags; #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8); __u32 handle; __u32 pad; __u64 addr; __u64 bo_offset; __u64 range; };h]hXstruct drm_nouveau_vm_bind_op { __u32 op; #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0; #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1; __u32 flags; #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8); __u32 handle; __u32 pad; __u64 addr; __u64 bo_offset; __u64 range; };}hj!\sbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj\ubh)}(h **Members**h]j)}(hj2\h]hMembers}(hj4\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0\ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM(hj\ubj)}(hhh](j)}(hXH``op`` the operation type Supported values: ``DRM_NOUVEAU_VM_BIND_OP_MAP`` - Map a GEM object to the GPU's VA space. Optionally, the :c:type:`DRM_NOUVEAU_VM_BIND_SPARSE` flag can be passed to instruct the kernel to create sparse mappings for the given range. ``DRM_NOUVEAU_VM_BIND_OP_UNMAP`` - Unmap an existing mapping in the GPU's VA space. If the region the mapping is located in is a sparse region, new sparse mappings are created where the unmapped (memory backed) mapping was mapped previously. To remove a sparse region the :c:type:`DRM_NOUVEAU_VM_BIND_SPARSE` must be set. h](j)}(h``op``h]jC)}(hjQ\h]hop}(hjS\hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjO\ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM*hjK\ubj)}(hhh](h)}(hthe operation typeh]hthe operation type}(hjj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjg\ubh)}(hSupported values:h]hSupported values:}(hjy\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjg\ubh)}(h``DRM_NOUVEAU_VM_BIND_OP_MAP`` - Map a GEM object to the GPU's VA space. Optionally, the :c:type:`DRM_NOUVEAU_VM_BIND_SPARSE` flag can be passed to instruct the kernel to create sparse mappings for the given range.h](jC)}(h``DRM_NOUVEAU_VM_BIND_OP_MAP``h]hDRM_NOUVEAU_VM_BIND_OP_MAP}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj\ubh= - Map a GEM object to the GPU’s VA space. Optionally, the }(hj\hhhNhNubh)}(h$:c:type:`DRM_NOUVEAU_VM_BIND_SPARSE`h]jC)}(hj\h]hDRM_NOUVEAU_VM_BIND_SPARSE}(hj\hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj\ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_NOUVEAU_VM_BIND_SPARSEuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM!hj\ubhY flag can be passed to instruct the kernel to create sparse mappings for the given range.}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj\hM!hjg\ubh)}(hXA``DRM_NOUVEAU_VM_BIND_OP_UNMAP`` - Unmap an existing mapping in the GPU's VA space. If the region the mapping is located in is a sparse region, new sparse mappings are created where the unmapped (memory backed) mapping was mapped previously. To remove a sparse region the :c:type:`DRM_NOUVEAU_VM_BIND_SPARSE` must be set.h](jC)}(h ``DRM_NOUVEAU_VM_BIND_OP_UNMAP``h]hDRM_NOUVEAU_VM_BIND_OP_UNMAP}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj\ubh - Unmap an existing mapping in the GPU’s VA space. If the region the mapping is located in is a sparse region, new sparse mappings are created where the unmapped (memory backed) mapping was mapped previously. To remove a sparse region the }(hj\hhhNhNubh)}(h$:c:type:`DRM_NOUVEAU_VM_BIND_SPARSE`h]jC)}(hj\h]hDRM_NOUVEAU_VM_BIND_SPARSE}(hj\hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj\ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_NOUVEAU_VM_BIND_SPARSEuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM&hj\ubh must be set.}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj\hM&hjg\ubeh}(h]h ]h"]h$]h&]uh1jhjK\ubeh}(h]h ]h"]h$]h&]uh1jhjf\hM*hjH\ubj)}(h``flags`` the flags for a :c:type:`drm_nouveau_vm_bind_op` Supported values: ``DRM_NOUVEAU_VM_BIND_SPARSE`` - Indicates that an allocated VA space region should be sparse. h](j)}(h ``flags``h]jC)}(hj]h]hflags}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM5hj]ubj)}(hhh](h)}(h0the flags for a :c:type:`drm_nouveau_vm_bind_op`h](hthe flags for a }(hj3]hhhNhNubh)}(h :c:type:`drm_nouveau_vm_bind_op`h]jC)}(hj=]h]hdrm_nouveau_vm_bind_op}(hj?]hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj;]ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_vm_bind_opuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM0hj3]ubeh}(h]h ]h"]h$]h&]uh1hhjZ]hM0hj0]ubh)}(hSupported values:h]hSupported values:}(hja]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM2hj0]ubh)}(h^``DRM_NOUVEAU_VM_BIND_SPARSE`` - Indicates that an allocated VA space region should be sparse.h](jC)}(h``DRM_NOUVEAU_VM_BIND_SPARSE``h]hDRM_NOUVEAU_VM_BIND_SPARSE}(hjt]hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjp]ubh@ - Indicates that an allocated VA space region should be sparse.}(hjp]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM4hj0]ubeh}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhj/]hM5hjH\ubj)}(h3``handle`` the handle of the DRM GEM object to map h](j)}(h ``handle``h]jC)}(hj]h]hhandle}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM:hj]ubj)}(hhh]h)}(h'the handle of the DRM GEM object to maph]h'the handle of the DRM GEM object to map}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hM:hj]ubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhj]hM:hjH\ubj)}(h$``pad`` 32 bit padding, should be 0 h](j)}(h``pad``h]jC)}(hj]h]hpad}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM>hj]ubj)}(hhh]h)}(h32 bit padding, should be 0h]h32 bit padding, should be 0}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hM>hj]ubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhj]hM>hjH\ubj)}(hX``addr`` the address the VA space region or (memory backed) mapping should be mapped to h](j)}(h``addr``h]jC)}(hj^h]haddr}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMBhj ^ubj)}(hhh]h)}(hNthe address the VA space region or (memory backed) mapping should be mapped toh]hNthe address the VA space region or (memory backed) mapping should be mapped to}(hj*^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&^hMBhj'^ubah}(h]h ]h"]h$]h&]uh1jhj ^ubeh}(h]h ]h"]h$]h&]uh1jhj&^hMBhjH\ubj)}(h;``bo_offset`` the offset within the BO backing the mapping h](j)}(h ``bo_offset``h]jC)}(hjJ^h]h bo_offset}(hjL^hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjH^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMHhjD^ubj)}(hhh]h)}(h,the offset within the BO backing the mappingh]h,the offset within the BO backing the mapping}(hjc^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_^hMHhj`^ubah}(h]h ]h"]h$]h&]uh1jhjD^ubeh}(h]h ]h"]h$]h&]uh1jhj_^hMHhjH\ubj)}(h4``range`` the size of the requested mapping in bytesh](j)}(h ``range``h]jC)}(hj^h]hrange}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMKhj}^ubj)}(hhh]h)}(h*the size of the requested mapping in bytesh]h*the size of the requested mapping in bytes}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMLhj^ubah}(h]h ]h"]h$]h&]uh1jhj}^ubeh}(h]h ]h"]h$]h&]uh1jhj^hMKhjH\ubeh}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj,WhhhNhNubh)}(h**Description**h]j)}(hj^h]h Description}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMOhj,Whhubh)}(hThis structure represents a single VM_BIND operation. UMDs should pass an array of this structure via struct drm_nouveau_vm_bind's :c:type:`op_ptr` field.h](hThis structure represents a single VM_BIND operation. UMDs should pass an array of this structure via struct drm_nouveau_vm_bind’s }(hj^hhhNhNubh)}(h:c:type:`op_ptr`h]jC)}(hj^h]hop_ptr}(hj^hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj^ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjop_ptruh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj^ubh field.}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj_hMhj,WhhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_nouveau_vm_bind (C struct)c.drm_nouveau_vm_bindhNtauh1jJhj,WhhhNhNubj\)}(hhh](ja)}(hdrm_nouveau_vm_bindh]jg)}(hstruct drm_nouveau_vm_bindh](jm)}(hjph]hstruct}(hj'_hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj#_hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMubj)}(h h]h }(hj5_hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj#_hhhj4_hMubj)}(hdrm_nouveau_vm_bindh]j)}(hj!_h]hdrm_nouveau_vm_bind}(hjG_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjC_ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj#_hhhj4_hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj_hhhj4_hMubah}(h]j_ah ](jjeh"]h$]h&]jj)jhuh1j`hj4_hMhj_hhubj)}(hhh]h)}(h'structure for DRM_IOCTL_NOUVEAU_VM_BINDh]h'structure for DRM_IOCTL_NOUVEAU_VM_BIND}(hji_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMQhjf_hhubah}(h]h ]h"]h$]h&]uh1jhj_hhhj4_hMubeh}(h]h ](jstructeh"]h$]h&]jjjj_jj_jjjuh1j[hhhj,WhNhNubj)}(hX***Definition**:: struct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; }; **Members** ``op_count`` the number of :c:type:`drm_nouveau_vm_bind_op` ``flags`` the flags for a :c:type:`drm_nouveau_vm_bind` ioctl Supported values: ``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel. If this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects. ``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` ``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished ``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for ``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished ``op_ptr`` pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubh:}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMUhj_ubj)}(hstruct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; };h]hstruct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; };}hj_sbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMWhj_ubh)}(h **Members**h]j)}(hj_h]hMembers}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMbhj_ubj)}(hhh](j)}(h<``op_count`` the number of :c:type:`drm_nouveau_vm_bind_op` h](j)}(h ``op_count``h]jC)}(hj_h]hop_count}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj_ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMVhj_ubj)}(hhh]h)}(h.the number of :c:type:`drm_nouveau_vm_bind_op`h](hthe number of }(hj_hhhNhNubh)}(h :c:type:`drm_nouveau_vm_bind_op`h]jC)}(hj_h]hdrm_nouveau_vm_bind_op}(hj_hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj_ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_vm_bind_opuh1hhj_hMVhj_ubeh}(h]h ]h"]h$]h&]uh1hhj_hMVhj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hMVhj_ubj)}(hXg``flags`` the flags for a :c:type:`drm_nouveau_vm_bind` ioctl Supported values: ``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel. If this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects. h](j)}(h ``flags``h]jC)}(hj.`h]hflags}(hj0`hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMchj(`ubj)}(hhh](h)}(h3the flags for a :c:type:`drm_nouveau_vm_bind` ioctlh](hthe flags for a }(hjG`hhhNhNubh)}(h:c:type:`drm_nouveau_vm_bind`h]jC)}(hjQ`h]hdrm_nouveau_vm_bind}(hjS`hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjO`ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_vm_binduh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMZhjG`ubh ioctl}(hjG`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjn`hMZhjD`ubh)}(hSupported values:h]hSupported values:}(hjy`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM\hjD`ubh)}(h``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel.h](jC)}(h!``DRM_NOUVEAU_VM_BIND_RUN_ASYNC``h]hDRM_NOUVEAU_VM_BIND_RUN_ASYNC}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubh^ - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM^hjD`ubh)}(hIf this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects.h](hrIf this flag is not supplied the kernel executes the associated operations synchronously and doesn’t accept any }(hj`hhhNhNubh)}(h:c:type:`drm_nouveau_sync`h]jC)}(hj`h]hdrm_nouveau_sync}(hj`hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj`ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMahj`ubh objects.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj`hMahjD`ubeh}(h]h ]h"]h$]h&]uh1jhj(`ubeh}(h]h ]h"]h$]h&]uh1jhjC`hMchj_ubj)}(h>``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` h](j)}(h``wait_count``h]jC)}(hj`h]h wait_count}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhhj`ubj)}(hhh]h)}(h.the number of wait :c:type:`drm_nouveau_syncs`h](hthe number of wait }(hjahhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]jC)}(hj ah]hdrm_nouveau_syncs}(hjahhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj aubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncsuh1hhj`hMhhjaubeh}(h]h ]h"]h$]h&]uh1hhj`hMhhj`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hMhhj_ubj)}(hP``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_count``h]jC)}(hjAah]h sig_count}(hjCahhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj?aubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMlhj;aubj)}(hhh]h)}(hAthe number of :c:type:`drm_nouveau_syncs` to signal when finishedh](hthe number of }(hjZahhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]jC)}(hjdah]hdrm_nouveau_syncs}(hjfahhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjbaubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncsuh1hhjVahMlhjZaubh to signal when finished}(hjZahhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjVahMlhjWaubah}(h]h ]h"]h$]h&]uh1jhj;aubeh}(h]h ]h"]h$]h&]uh1jhjVahMlhj_ubj)}(h@``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for h](j)}(h ``wait_ptr``h]jC)}(hjah]hwait_ptr}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjaubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMphjaubj)}(hhh]h)}(h2pointer to :c:type:`drm_nouveau_syncs` to wait forh](h pointer to }(hjahhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]jC)}(hjah]hdrm_nouveau_syncs}(hjahhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjaubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncsuh1hhjahMphjaubh to wait for}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjahMphjaubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhjahMphj_ubj)}(hK``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_ptr``h]jC)}(hjah]hsig_ptr}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjaubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMthjaubj)}(hhh]h)}(h>pointer to :c:type:`drm_nouveau_syncs` to signal when finishedh](h pointer to }(hjbhhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]jC)}(hjbh]hdrm_nouveau_syncs}(hjbhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjbubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncsuh1hhjbhMthjbubh to signal when finished}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjbhMthjbubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhjbhMthj_ubj)}(hF``op_ptr`` pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](j)}(h ``op_ptr``h]jC)}(hjUbh]hop_ptr}(hjWbhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjSbubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMwhjObubj)}(hhh]h)}(h;pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](hpointer to the }(hjnbhhhNhNubh)}(h!:c:type:`drm_nouveau_vm_bind_ops`h]jC)}(hjxbh]hdrm_nouveau_vm_bind_ops}(hjzbhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjvbubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_vm_bind_opsuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMxhjnbubh to execute}(hjnbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjbhMxhjkbubah}(h]h ]h"]h$]h&]uh1jhjObubeh}(h]h ]h"]h$]h&]uh1jhjjbhMwhj_ubeh}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj,WhhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_nouveau_exec_push (C struct)c.drm_nouveau_exec_pushhNtauh1jJhj,WhhhNhNubj\)}(hhh](ja)}(hdrm_nouveau_exec_pushh]jg)}(hstruct drm_nouveau_exec_pushh](jm)}(hjph]hstruct}(hjbhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjbhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM~ubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjbhhhjbhM~ubj)}(hdrm_nouveau_exec_pushh]j)}(hjbh]hdrm_nouveau_exec_push}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubah}(h]h ](jjeh"]h$]h&]jjuh1jhjbhhhjbhM~ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjbhhhjbhM~ubah}(h]jbah ](jjeh"]h$]h&]jj)jhuh1j`hjbhM~hjbhhubj)}(hhh]h)}(hEXEC push operationh]hEXEC push operation}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM}hjchhubah}(h]h ]h"]h$]h&]uh1jhjbhhhjbhM~ubeh}(h]h ](jstructeh"]h$]h&]jjjj,cjj,cjjjuh1j[hhhj,WhNhNubj)}(hXM**Definition**:: struct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; }; **Members** ``va`` the virtual address of the push buffer mapping ``va_len`` the length of the push buffer mapping ``flags`` the flags for this push buffer mappingh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj8chhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4cubh:}(hj4chhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj0cubj)}(hstruct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; };h]hstruct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; };}hjQcsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj0cubh)}(h **Members**h]j)}(hjbch]hMembers}(hjdchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`cubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj0cubj)}(hhh](j)}(h6``va`` the virtual address of the push buffer mapping h](j)}(h``va``h]jC)}(hjch]hva}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjcubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj{cubj)}(hhh]h)}(h.the virtual address of the push buffer mappingh]h.the virtual address of the push buffer mapping}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjcubah}(h]h ]h"]h$]h&]uh1jhj{cubeh}(h]h ]h"]h$]h&]uh1jhjchMhjxcubj)}(h1``va_len`` the length of the push buffer mapping h](j)}(h ``va_len``h]jC)}(hjch]hva_len}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjcubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjcubj)}(hhh]h)}(h%the length of the push buffer mappingh]h%the length of the push buffer mapping}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjcubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhjchMhjxcubj)}(h0``flags`` the flags for this push buffer mappingh](j)}(h ``flags``h]jC)}(hjch]hflags}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjcubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjcubj)}(hhh]h)}(h&the flags for this push buffer mappingh]h&the flags for this push buffer mapping}(hj dhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj dubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhjdhMhjxcubeh}(h]h ]h"]h$]h&]uh1jhj0cubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj,WhhhNhNubh)}(h**Description**h]j)}(hj6dh]h Description}(hj8dhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4dubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj,Whhubh)}(hThis structure represents a single EXEC push operation. UMDs should pass an array of this structure via struct drm_nouveau_exec's :c:type:`push_ptr` field.h](hThis structure represents a single EXEC push operation. UMDs should pass an array of this structure via struct drm_nouveau_exec’s }(hjLdhhhNhNubh)}(h:c:type:`push_ptr`h]jC)}(hjVdh]hpush_ptr}(hjXdhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjTdubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjpush_ptruh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhM~hjLdubh field.}(hjLdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjsdhM~hj,WhhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_nouveau_exec (C struct)c.drm_nouveau_exechNtauh1jJhj,WhhhNhNubj\)}(hhh](ja)}(hdrm_nouveau_exech]jg)}(hstruct drm_nouveau_exech](jm)}(hjph]hstruct}(hjdhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjdhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMubj)}(h h]h }(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjdhhhjdhMubj)}(hdrm_nouveau_exech]j)}(hjdh]hdrm_nouveau_exec}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubah}(h]h ](jjeh"]h$]h&]jjuh1jhjdhhhjdhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjdhhhjdhMubah}(h]jdah ](jjeh"]h$]h&]jj)jhuh1j`hjdhMhjdhhubj)}(hhh]h)}(h$structure for DRM_IOCTL_NOUVEAU_EXECh]h$structure for DRM_IOCTL_NOUVEAU_EXEC}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjdhhubah}(h]h ]h"]h$]h&]uh1jhjdhhhjdhMubeh}(h]h ](jstructeh"]h$]h&]jjjjdjjdjjjuh1j[hhhj,WhNhNubj)}(hX**Definition**:: struct drm_nouveau_exec { __u32 channel; __u32 push_count; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 push_ptr; }; **Members** ``channel`` the channel to execute the push buffer in ``push_count`` the number of :c:type:`drm_nouveau_exec_push` ops ``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` ``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished ``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for ``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished ``push_ptr`` pointer to :c:type:`drm_nouveau_exec_push` opsh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubh:}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjdubj)}(hstruct drm_nouveau_exec { __u32 channel; __u32 push_count; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 push_ptr; };h]hstruct drm_nouveau_exec { __u32 channel; __u32 push_count; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 push_ptr; };}hjesbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjdubh)}(h **Members**h]j)}(hj'eh]hMembers}(hj)ehhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%eubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjdubj)}(hhh](j)}(h6``channel`` the channel to execute the push buffer in h](j)}(h ``channel``h]jC)}(hjFeh]hchannel}(hjHehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjDeubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj@eubj)}(hhh]h)}(h)the channel to execute the push buffer inh]h)the channel to execute the push buffer in}(hj_ehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[ehMhj\eubah}(h]h ]h"]h$]h&]uh1jhj@eubeh}(h]h ]h"]h$]h&]uh1jhj[ehMhj=eubj)}(hA``push_count`` the number of :c:type:`drm_nouveau_exec_push` ops h](j)}(h``push_count``h]jC)}(hjeh]h push_count}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj}eubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjyeubj)}(hhh]h)}(h1the number of :c:type:`drm_nouveau_exec_push` opsh](hthe number of }(hjehhhNhNubh)}(h:c:type:`drm_nouveau_exec_push`h]jC)}(hjeh]hdrm_nouveau_exec_push}(hjehhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjeubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_exec_pushuh1hhjehMhjeubh ops}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjehMhjeubah}(h]h ]h"]h$]h&]uh1jhjyeubeh}(h]h ]h"]h$]h&]uh1jhjehMhj=eubj)}(h>``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` h](j)}(h``wait_count``h]jC)}(hjeh]h wait_count}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjeubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjeubj)}(hhh]h)}(h.the number of wait :c:type:`drm_nouveau_syncs`h](hthe number of wait }(hjehhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]jC)}(hjeh]hdrm_nouveau_syncs}(hjfhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjeubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncsuh1hhjehMhjeubeh}(h]h ]h"]h$]h&]uh1hhjehMhjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjehMhj=eubj)}(hP``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_count``h]jC)}(hj3fh]h sig_count}(hj5fhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj1fubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj-fubj)}(hhh]h)}(hAthe number of :c:type:`drm_nouveau_syncs` to signal when finishedh](hthe number of }(hjLfhhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]jC)}(hjVfh]hdrm_nouveau_syncs}(hjXfhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjTfubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncsuh1hhjHfhMhjLfubh to signal when finished}(hjLfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjHfhMhjIfubah}(h]h ]h"]h$]h&]uh1jhj-fubeh}(h]h ]h"]h$]h&]uh1jhjHfhMhj=eubj)}(h@``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for h](j)}(h ``wait_ptr``h]jC)}(hjfh]hwait_ptr}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjfubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjfubj)}(hhh]h)}(h2pointer to :c:type:`drm_nouveau_syncs` to wait forh](h pointer to }(hjfhhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]jC)}(hjfh]hdrm_nouveau_syncs}(hjfhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjfubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncsuh1hhjfhMhjfubh to wait for}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjfhMhjfubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjfhMhj=eubj)}(hK``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_ptr``h]jC)}(hjfh]hsig_ptr}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjfubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjfubj)}(hhh]h)}(h>pointer to :c:type:`drm_nouveau_syncs` to signal when finishedh](h pointer to }(hjghhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]jC)}(hjgh]hdrm_nouveau_syncs}(hjghhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj gubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_syncsuh1hhjghMhjgubh to signal when finished}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjghMhjgubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjghMhj=eubj)}(h;``push_ptr`` pointer to :c:type:`drm_nouveau_exec_push` opsh](j)}(h ``push_ptr``h]jC)}(hjGgh]hpush_ptr}(hjIghhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjEgubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhjAgubj)}(hhh]h)}(h.pointer to :c:type:`drm_nouveau_exec_push` opsh](h pointer to }(hj`ghhhNhNubh)}(h:c:type:`drm_nouveau_exec_push`h]jC)}(hjjgh]hdrm_nouveau_exec_push}(hjlghhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjhgubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_nouveau_exec_pushuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:21: ./include/uapi/drm/nouveau_drm.hhMhj`gubh ops}(hj`ghhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjghMhj]gubah}(h]h ]h"]h$]h&]uh1jhjAgubeh}(h]h ]h"]h$]h&]uh1jhj\ghMhj=eubeh}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj,WhhhNhNubeh}(h]j`ah ]h"]vm_bind / exec uapiah$]h&]uh1hhjWhhhhhKubeh}(h]jAah ]h"]drm/nouveau uapiah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hdrm/panthor uAPIh]hdrm/panthor uAPI}(hjghhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjghhhhhKubj{)}(h.. _Introduction:h]h}(h]h ]h"]h$]h&]hʌ introductionuh1jzhKhjghhhNubh)}(h**Introduction**h]j)}(hjgh]h Introduction}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]jgah ]h"] introductionah$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhKhjghhj}jgjgsj}jgjgsubh)}(h0This documentation describes the Panthor IOCTLs.h]h0This documentation describes the Panthor IOCTLs.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK hjghhubh)}(hEJust a few generic rules about the data passed to the Panthor IOCTLs:h]hEJust a few generic rules about the data passed to the Panthor IOCTLs:}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhKhjghhubh)}(hhh](h)}(hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.h]h)}(hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.h]hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhKhjhubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]h)}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.}(hj.hhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhKhj*hubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]h)}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]hNAll padding fields will be checked by the driver to make sure they are zeroed.}(hjGhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhKhjChubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(h-Flags can be added, but not removed/replaced.h]h)}(hj^hh]h-Flags can be added, but not removed/replaced.}(hj`hhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhKhj\hubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]h)}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.}(hjxhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhKhjthubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).h]h)}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).h]hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhKhjhubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]h)}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK!hjhubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h)}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK#hjhubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to trial and error to know which flags are supported.h]h)}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to trial and error to know which flags are supported.h]hEach new flag/field addition must come with a driver version update so the userspace driver doesn’t have to trial and error to know which flags are supported.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK%hjhubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h)}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h`Structures should not contain unions, as this would defeat the extensibility of such structures.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK(hjhubah}(h]h ]h"]h$]h&]uh1hhjhubh)}(hrIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum. h]h)}(hpIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum.h]hrIOCTLs can’t be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK*hj iubah}(h]h ]h"]h$]h&]uh1hhjhubeh}(h]h ]h"]h$]h&]j j uh1hhj#hhKhjghhubj{)}(h'.. _MMIO regions exposed to userspace.:h]h}(h]h ]h"]h$]h&]hʌ!mmio-regions-exposed-to-userspaceuh1jzhK&hjghhhNubh)}(h&**MMIO regions exposed to userspace.**h]j)}(hj6ih]h"MMIO regions exposed to userspace.}(hj8ihhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4iubah}(h]j3iah ]h"]"mmio regions exposed to userspace.ah$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK0hjghhj}jIij)isj}j3ij)isubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW&DRM_PANTHOR_USER_MMIO_OFFSET (C macro)c.DRM_PANTHOR_USER_MMIO_OFFSEThNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]jg)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]j)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]j)}(hjbih]hDRM_PANTHOR_USER_MMIO_OFFSET}(hjlihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhiubah}(h]h ](jjeh"]h$]h&]jjuh1jhjdihhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK1ubah}(h]h ]h"]h$]h&]jjjuh1jfjjhj`ihhhjihK1ubah}(h]j[iah ](jjeh"]h$]h&]jj)jhuh1j`hjihK1hj]ihhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj]ihhhjihK1ubeh}(h]h ](jmacroeh"]h$]h&]jjjjijjijjjuh1j[hhhjghNhNubh)}(hXFile offset for all MMIO regions being exposed to userspace. Don't use this value directly, use DRM_PANTHOR_USER__OFFSET values instead. pgoffset passed to mmap2() is an unsigned long, which forces us to use a different offset on 32-bit and 64-bit systems.h]hXFile offset for all MMIO regions being exposed to userspace. Don’t use this value directly, use DRM_PANTHOR_USER__OFFSET values instead. pgoffset passed to mmap2() is an unsigned long, which forces us to use a different offset on 32-bit and 64-bit systems.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK3hjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW/DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET (C macro)'c.DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSEThNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]jg)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]j)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]j)}(hjih]h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubah}(h]h ](jjeh"]h$]h&]jjuh1jhjihhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK8ubah}(h]h ]h"]h$]h&]jjjuh1jfjjhjihhhjihK8ubah}(h]jiah ](jjeh"]h$]h&]jj)jhuh1j`hjihK8hjihhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjihhhjihK8ubeh}(h]h ](jmacroeh"]h$]h&]jjjjijjijjjuh1j[hhhjghNhNubh)}(hXFile offset for the LATEST_FLUSH_ID register. The Userspace driver controls GPU cache flushing through CS instructions, but the flush reduction mechanism requires a flush_id. This flush_id could be queried with an ioctl, but Arm provides a well-isolated register page containing only this read-only register, so let's expose this page through a static mmap offset and allow direct mapping of this MMIO region so we can avoid the user <-> kernel round-trip.h]hXFile offset for the LATEST_FLUSH_ID register. The Userspace driver controls GPU cache flushing through CS instructions, but the flush reduction mechanism requires a flush_id. This flush_id could be queried with an ioctl, but Arm provides a well-isolated register page containing only this read-only register, so let’s expose this page through a static mmap offset and allow direct mapping of this MMIO region so we can avoid the user <-> kernel round-trip.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhK:hjghhubj{)}(h.. _IOCTL IDs:h]h}(h]h ]h"]h$]h&]hʌ ioctl-idsuh1jzhK> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u32 selected_coherency; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; __u64 gpu_features; }; **Members** ``gpu_id`` GPU ID. ``gpu_rev`` GPU revision. ``csf_id`` Command stream frontend ID. ``l2_features`` L2-cache features. ``tiler_features`` Tiler features. ``mem_features`` Memory features. ``mmu_features`` MMU features. ``thread_features`` Thread features. ``max_threads`` Maximum number of threads. ``thread_max_workgroup_size`` Maximum workgroup size. ``thread_max_barrier_size`` Maximum number of threads that can wait simultaneously on a barrier. ``coherency_features`` Coherency features. Combination of drm_panthor_gpu_coherency flags. Note that this is just what the coherency protocols supported by the GPU, but the actual coherency in place depends on the SoC integration and is reflected by drm_panthor_gpu_info::selected_coherency. ``texture_features`` Texture features. ``as_present`` Bitmask encoding the number of address-space exposed by the MMU. ``selected_coherency`` Coherency selected for this device. One of drm_panthor_gpu_coherency. ``shader_present`` Bitmask encoding the shader cores exposed by the GPU. ``l2_present`` Bitmask encoding the L2 caches exposed by the GPU. ``tiler_present`` Bitmask encoding the tiler units exposed by the GPU. ``core_features`` Used to discriminate core variants when they exist. ``pad`` MBZ. ``gpu_features`` Bitmask describing supported GPU-wide featuresh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjgthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjctubh:}(hjcthhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj_tubj)}(hXstruct drm_panthor_gpu_info { __u32 gpu_id; #define DRM_PANTHOR_ARCH_MAJOR(x) ((x) >> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u32 selected_coherency; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; __u64 gpu_features; };h]hXstruct drm_panthor_gpu_info { __u32 gpu_id; #define DRM_PANTHOR_ARCH_MAJOR(x) ((x) >> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u32 selected_coherency; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; __u64 gpu_features; };}hjtsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hj_tubh)}(h **Members**h]j)}(hjth]hMembers}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMFhj_tubj)}(hhh](j)}(h``gpu_id`` GPU ID. h](j)}(h ``gpu_id``h]jC)}(hjth]hgpu_id}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hjtubj)}(hhh]h)}(hGPU ID.h]hGPU ID.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthM hjtubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjthM hjtubj)}(h``gpu_rev`` GPU revision. h](j)}(h ``gpu_rev``h]jC)}(hjth]hgpu_rev}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM*hjtubj)}(hhh]h)}(h GPU revision.h]h GPU revision.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthM*hjtubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjthM*hjtubj)}(h'``csf_id`` Command stream frontend ID. h](j)}(h ``csf_id``h]jC)}(hj"uh]hcsf_id}(hj$uhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj uubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM-hjuubj)}(hhh]h)}(hCommand stream frontend ID.h]hCommand stream frontend ID.}(hj;uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7uhM-hj8uubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhj7uhM-hjtubj)}(h#``l2_features`` L2-cache features. h](j)}(h``l2_features``h]jC)}(hj[uh]h l2_features}(hj]uhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjYuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM6hjUuubj)}(hhh]h)}(hL2-cache features.h]hL2-cache features.}(hjtuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpuhM6hjquubah}(h]h ]h"]h$]h&]uh1jhjUuubeh}(h]h ]h"]h$]h&]uh1jhjpuhM6hjtubj)}(h#``tiler_features`` Tiler features. h](j)}(h``tiler_features``h]jC)}(hjuh]htiler_features}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM9hjuubj)}(hhh]h)}(hTiler features.h]hTiler features.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhM9hjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjuhM9hjtubj)}(h"``mem_features`` Memory features. h](j)}(h``mem_features``h]jC)}(hjuh]h mem_features}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM<hjuubj)}(hhh]h)}(hMemory features.h]hMemory features.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhM<hjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjuhM<hjtubj)}(h``mmu_features`` MMU features. h](j)}(h``mmu_features``h]jC)}(hjvh]h mmu_features}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM?hjvubj)}(hhh]h)}(h MMU features.h]h MMU features.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhM?hjvubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhjvhM?hjtubj)}(h%``thread_features`` Thread features. h](j)}(h``thread_features``h]jC)}(hj?vh]hthread_features}(hjAvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj=vubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMChj9vubj)}(hhh]h)}(hThread features.h]hThread features.}(hjXvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTvhMChjUvubah}(h]h ]h"]h$]h&]uh1jhj9vubeh}(h]h ]h"]h$]h&]uh1jhjTvhMChjtubj)}(h+``max_threads`` Maximum number of threads. h](j)}(h``max_threads``h]jC)}(hjxvh]h max_threads}(hjzvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvvubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMFhjrvubj)}(hhh]h)}(hMaximum number of threads.h]hMaximum number of threads.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMFhjvubah}(h]h ]h"]h$]h&]uh1jhjrvubeh}(h]h ]h"]h$]h&]uh1jhjvhMFhjtubj)}(h6``thread_max_workgroup_size`` Maximum workgroup size. h](j)}(h``thread_max_workgroup_size``h]jC)}(hjvh]hthread_max_workgroup_size}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMIhjvubj)}(hhh]h)}(hMaximum workgroup size.h]hMaximum workgroup size.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMIhjvubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhjvhMIhjtubj)}(ha``thread_max_barrier_size`` Maximum number of threads that can wait simultaneously on a barrier. h](j)}(h``thread_max_barrier_size``h]jC)}(hjvh]hthread_max_barrier_size}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMNhjvubj)}(hhh]h)}(hDMaximum number of threads that can wait simultaneously on a barrier.h]hDMaximum number of threads that can wait simultaneously on a barrier.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMMhjwubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhjvhMNhjtubj)}(hX&``coherency_features`` Coherency features. Combination of drm_panthor_gpu_coherency flags. Note that this is just what the coherency protocols supported by the GPU, but the actual coherency in place depends on the SoC integration and is reflected by drm_panthor_gpu_info::selected_coherency. h](j)}(h``coherency_features``h]jC)}(hj$wh]hcoherency_features}(hj&whhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj"wubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMZhjwubj)}(hhh](h)}(hCoherency features.h]hCoherency features.}(hj=whhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMShj:wubh)}(h/Combination of drm_panthor_gpu_coherency flags.h]h/Combination of drm_panthor_gpu_coherency flags.}(hjLwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMUhj:wubh)}(hNote that this is just what the coherency protocols supported by the GPU, but the actual coherency in place depends on the SoC integration and is reflected by drm_panthor_gpu_info::selected_coherency.h]hNote that this is just what the coherency protocols supported by the GPU, but the actual coherency in place depends on the SoC integration and is reflected by drm_panthor_gpu_info::selected_coherency.}(hj[whhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMWhj:wubeh}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhj9whMZhjtubj)}(h'``texture_features`` Texture features. h](j)}(h``texture_features``h]jC)}(hj|wh]htexture_features}(hj~whhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjzwubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM^hjvwubj)}(hhh]h)}(hTexture features.h]hTexture features.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhM^hjwubah}(h]h ]h"]h$]h&]uh1jhjvwubeh}(h]h ]h"]h$]h&]uh1jhjwhM^hjtubj)}(hP``as_present`` Bitmask encoding the number of address-space exposed by the MMU. h](j)}(h``as_present``h]jC)}(hjwh]h as_present}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjwubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMahjwubj)}(hhh]h)}(h@Bitmask encoding the number of address-space exposed by the MMU.h]h@Bitmask encoding the number of address-space exposed by the MMU.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMahjwubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjwhMahjtubj)}(h^``selected_coherency`` Coherency selected for this device. One of drm_panthor_gpu_coherency. h](j)}(h``selected_coherency``h]jC)}(hjwh]hselected_coherency}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjwubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMghjwubj)}(hhh](h)}(h#Coherency selected for this device.h]h#Coherency selected for this device.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMehjxubh)}(h!One of drm_panthor_gpu_coherency.h]h!One of drm_panthor_gpu_coherency.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMghjxubeh}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjxhMghjtubj)}(hI``shader_present`` Bitmask encoding the shader cores exposed by the GPU. h](j)}(h``shader_present``h]jC)}(hj6xh]hshader_present}(hj8xhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj4xubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMkhj0xubj)}(hhh]h)}(h5Bitmask encoding the shader cores exposed by the GPU.h]h5Bitmask encoding the shader cores exposed by the GPU.}(hjOxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKxhMkhjLxubah}(h]h ]h"]h$]h&]uh1jhj0xubeh}(h]h ]h"]h$]h&]uh1jhjKxhMkhjtubj)}(hB``l2_present`` Bitmask encoding the L2 caches exposed by the GPU. h](j)}(h``l2_present``h]jC)}(hjoxh]h l2_present}(hjqxhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjmxubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMnhjixubj)}(hhh]h)}(h2Bitmask encoding the L2 caches exposed by the GPU.h]h2Bitmask encoding the L2 caches exposed by the GPU.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMnhjxubah}(h]h ]h"]h$]h&]uh1jhjixubeh}(h]h ]h"]h$]h&]uh1jhjxhMnhjtubj)}(hG``tiler_present`` Bitmask encoding the tiler units exposed by the GPU. h](j)}(h``tiler_present``h]jC)}(hjxh]h tiler_present}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjxubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMqhjxubj)}(hhh]h)}(h4Bitmask encoding the tiler units exposed by the GPU.h]h4Bitmask encoding the tiler units exposed by the GPU.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMqhjxubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjxhMqhjtubj)}(hF``core_features`` Used to discriminate core variants when they exist. h](j)}(h``core_features``h]jC)}(hjxh]h core_features}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjxubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMthjxubj)}(hhh]h)}(h3Used to discriminate core variants when they exist.h]h3Used to discriminate core variants when they exist.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMthjxubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjxhMthjtubj)}(h ``pad`` MBZ. h](j)}(h``pad``h]jC)}(hjyh]hpad}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjyubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMwhjyubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hj3yhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/yhMwhj0yubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jhj/yhMwhjtubj)}(h?``gpu_features`` Bitmask describing supported GPU-wide featuresh](j)}(h``gpu_features``h]jC)}(hjSyh]h gpu_features}(hjUyhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQyubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMyhjMyubj)}(hhh]h)}(h.Bitmask describing supported GPU-wide featuresh]h.Bitmask describing supported GPU-wide features}(hjlyhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMzhjiyubah}(h]h ]h"]h$]h&]uh1jhjMyubeh}(h]h ]h"]h$]h&]uh1jhjhyhMyhjtubeh}(h]h ]h"]h$]h&]uh1jhj_tubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hjyh]h Description}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM}hjghhubh)}(hAStructure grouping all queryable information relating to the GPU.h]hAStructure grouping all queryable information relating to the GPU.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_panthor_csif_info (C struct)c.drm_panthor_csif_infohNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_csif_infoh]jg)}(hstruct drm_panthor_csif_infoh](jm)}(hjph]hstruct}(hjyhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjyhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM ubj)}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjyhhhjyhM ubj)}(hdrm_panthor_csif_infoh]j)}(hjyh]hdrm_panthor_csif_info}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubah}(h]h ](jjeh"]h$]h&]jjuh1jhjyhhhjyhM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjyhhhjyhM ubah}(h]jyah ](jjeh"]h$]h&]jj)jhuh1j`hjyhM hjyhhubj)}(hhh]h)}(h$Command stream interface informationh]h$Command stream interface information}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM~hjzhhubah}(h]h ]h"]h$]h&]uh1jhjyhhhjyhM ubeh}(h]h ](jstructeh"]h$]h&]jjjj.zjj.zjjjuh1j[hhhjghNhNubj)}(hXu**Definition**:: struct drm_panthor_csif_info { __u32 csg_slot_count; __u32 cs_slot_count; __u32 cs_reg_count; __u32 scoreboard_slot_count; __u32 unpreserved_cs_reg_count; __u32 pad; }; **Members** ``csg_slot_count`` Number of command stream group slots exposed by the firmware. ``cs_slot_count`` Number of command stream slots per group. ``cs_reg_count`` Number of command stream registers. ``scoreboard_slot_count`` Number of scoreboard slots. ``unpreserved_cs_reg_count`` Number of command stream registers reserved by the kernel driver to call a userspace command stream. All registers can be used by a userspace command stream, but the [cs_slot_count - unpreserved_cs_reg_count .. cs_slot_count] registers are used by the kernel when DRM_PANTHOR_IOCTL_GROUP_SUBMIT is called. ``pad`` Padding field, set to zero.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj:zhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6zubh:}(hj6zhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj2zubj)}(hstruct drm_panthor_csif_info { __u32 csg_slot_count; __u32 cs_slot_count; __u32 cs_reg_count; __u32 scoreboard_slot_count; __u32 unpreserved_cs_reg_count; __u32 pad; };h]hstruct drm_panthor_csif_info { __u32 csg_slot_count; __u32 cs_slot_count; __u32 cs_reg_count; __u32 scoreboard_slot_count; __u32 unpreserved_cs_reg_count; __u32 pad; };}hjSzsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj2zubh)}(h **Members**h]j)}(hjdzh]hMembers}(hjfzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbzubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj2zubj)}(hhh](j)}(hQ``csg_slot_count`` Number of command stream group slots exposed by the firmware. h](j)}(h``csg_slot_count``h]jC)}(hjzh]hcsg_slot_count}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjzubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj}zubj)}(hhh]h)}(h=Number of command stream group slots exposed by the firmware.h]h=Number of command stream group slots exposed by the firmware.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMhjzubah}(h]h ]h"]h$]h&]uh1jhj}zubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjzzubj)}(h<``cs_slot_count`` Number of command stream slots per group. h](j)}(h``cs_slot_count``h]jC)}(hjzh]h cs_slot_count}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjzubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjzubj)}(hhh]h)}(h)Number of command stream slots per group.h]h)Number of command stream slots per group.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMhjzubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjzzubj)}(h5``cs_reg_count`` Number of command stream registers. h](j)}(h``cs_reg_count``h]jC)}(hjzh]h cs_reg_count}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjzubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjzubj)}(hhh]h)}(h#Number of command stream registers.h]h#Number of command stream registers.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj {hMhj {ubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jhj {hMhjzzubj)}(h6``scoreboard_slot_count`` Number of scoreboard slots. h](j)}(h``scoreboard_slot_count``h]jC)}(hj.{h]hscoreboard_slot_count}(hj0{hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,{ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj({ubj)}(hhh]h)}(hNumber of scoreboard slots.h]hNumber of scoreboard slots.}(hjG{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC{hMhjD{ubah}(h]h ]h"]h$]h&]uh1jhj({ubeh}(h]h ]h"]h$]h&]uh1jhjC{hMhjzzubj)}(hXP``unpreserved_cs_reg_count`` Number of command stream registers reserved by the kernel driver to call a userspace command stream. All registers can be used by a userspace command stream, but the [cs_slot_count - unpreserved_cs_reg_count .. cs_slot_count] registers are used by the kernel when DRM_PANTHOR_IOCTL_GROUP_SUBMIT is called. h](j)}(h``unpreserved_cs_reg_count``h]jC)}(hjg{h]hunpreserved_cs_reg_count}(hji{hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhje{ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhja{ubj)}(hhh](h)}(hdNumber of command stream registers reserved by the kernel driver to call a userspace command stream.h]hdNumber of command stream registers reserved by the kernel driver to call a userspace command stream.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj}{ubh)}(hAll registers can be used by a userspace command stream, but the [cs_slot_count - unpreserved_cs_reg_count .. cs_slot_count] registers are used by the kernel when DRM_PANTHOR_IOCTL_GROUP_SUBMIT is called.h]hAll registers can be used by a userspace command stream, but the [cs_slot_count - unpreserved_cs_reg_count .. cs_slot_count] registers are used by the kernel when DRM_PANTHOR_IOCTL_GROUP_SUBMIT is called.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj}{ubeh}(h]h ]h"]h$]h&]uh1jhja{ubeh}(h]h ]h"]h$]h&]uh1jhj|{hMhjzzubj)}(h#``pad`` Padding field, set to zero.h](j)}(h``pad``h]jC)}(hj{h]hpad}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj{ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj{ubj)}(hhh]h)}(hPadding field, set to zero.h]hPadding field, set to zero.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jhj{hMhjzzubeh}(h]h ]h"]h$]h&]uh1jhj2zubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hj{h]h Description}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubh)}(hVStructure grouping all queryable information relating to the command stream interface.h]hVStructure grouping all queryable information relating to the command stream interface.}(hj |hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW)drm_panthor_timestamp_info_flags (C enum)"c.drm_panthor_timestamp_info_flagshNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(h drm_panthor_timestamp_info_flagsh]jg)}(h%enum drm_panthor_timestamp_info_flagsh](jm)}(hjh]henum}(hj1|hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj-|hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj?|hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj-|hhhj>|hMubj)}(h drm_panthor_timestamp_info_flagsh]j)}(hj+|h]h drm_panthor_timestamp_info_flags}(hjQ|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjM|ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj-|hhhj>|hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj)|hhhj>|hMubah}(h]j$|ah ](jjeh"]h$]h&]jj)jhuh1j`hj>|hMhj&|hhubj)}(hhh]h)}(h drm_panthor_timestamp_info.flagsh]h drm_panthor_timestamp_info.flags}(hjs|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjp|hhubah}(h]h ]h"]h$]h&]uh1jhj&|hhhj>|hMubeh}(h]h ](jenumeh"]h$]h&]jjjj|jj|jjjuh1j[hhhjghNhNubj)}(hXr**Constants** ``DRM_PANTHOR_TIMESTAMP_GPU`` Query GPU time. ``DRM_PANTHOR_TIMESTAMP_CPU_NONE`` Don't query CPU time. ``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC`` Query CPU time using CLOCK_MONOTONIC. ``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW`` Query CPU time using CLOCK_MONOTONIC_RAW. ``DRM_PANTHOR_TIMESTAMP_CPU_TYPE_MASK`` Space reserved for CPU clock type. ``DRM_PANTHOR_TIMESTAMP_GPU_OFFSET`` Query GPU offset. ``DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT`` Query GPU cycle count. ``DRM_PANTHOR_TIMESTAMP_FREQ`` Query timestamp frequency. ``DRM_PANTHOR_TIMESTAMP_DURATION`` Return duration of time query.h](h)}(h **Constants**h]j)}(hj|h]h Constants}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj|ubj)}(hhh](j)}(h.``DRM_PANTHOR_TIMESTAMP_GPU`` Query GPU time. h](j)}(h``DRM_PANTHOR_TIMESTAMP_GPU``h]jC)}(hj|h]hDRM_PANTHOR_TIMESTAMP_GPU}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj|ubj)}(hhh]h)}(hQuery GPU time.h]hQuery GPU time.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMhj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hMhj|ubj)}(h9``DRM_PANTHOR_TIMESTAMP_CPU_NONE`` Don't query CPU time. h](j)}(h"``DRM_PANTHOR_TIMESTAMP_CPU_NONE``h]jC)}(hj|h]hDRM_PANTHOR_TIMESTAMP_CPU_NONE}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj|ubj)}(hhh]h)}(hDon't query CPU time.h]hDon’t query CPU time.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj}ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj|ubj)}(hN``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC`` Query CPU time using CLOCK_MONOTONIC. h](j)}(h'``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC``h]jC)}(hj&}h]h#DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC}(hj(}hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj }ubj)}(hhh]h)}(h%Query CPU time using CLOCK_MONOTONIC.h]h%Query CPU time using CLOCK_MONOTONIC.}(hj?}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;}hMhj<}ubah}(h]h ]h"]h$]h&]uh1jhj }ubeh}(h]h ]h"]h$]h&]uh1jhj;}hMhj|ubj)}(hV``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW`` Query CPU time using CLOCK_MONOTONIC_RAW. h](j)}(h+``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW``h]jC)}(hj_}h]h'DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW}(hja}hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjY}ubj)}(hhh]h)}(h)Query CPU time using CLOCK_MONOTONIC_RAW.h]h)Query CPU time using CLOCK_MONOTONIC_RAW.}(hjx}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt}hMhju}ubah}(h]h ]h"]h$]h&]uh1jhjY}ubeh}(h]h ]h"]h$]h&]uh1jhjt}hMhj|ubj)}(hK``DRM_PANTHOR_TIMESTAMP_CPU_TYPE_MASK`` Space reserved for CPU clock type. h](j)}(h'``DRM_PANTHOR_TIMESTAMP_CPU_TYPE_MASK``h]jC)}(hj}h]h#DRM_PANTHOR_TIMESTAMP_CPU_TYPE_MASK}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj}ubj)}(hhh]h)}(h"Space reserved for CPU clock type.h]h"Space reserved for CPU clock type.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj|ubj)}(h7``DRM_PANTHOR_TIMESTAMP_GPU_OFFSET`` Query GPU offset. h](j)}(h$``DRM_PANTHOR_TIMESTAMP_GPU_OFFSET``h]jC)}(hj}h]h DRM_PANTHOR_TIMESTAMP_GPU_OFFSET}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj}ubj)}(hhh]h)}(hQuery GPU offset.h]hQuery GPU offset.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj|ubj)}(hA``DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT`` Query GPU cycle count. h](j)}(h)``DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT``h]jC)}(hj ~h]h%DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT}(hj ~hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj~ubj)}(hhh]h)}(hQuery GPU cycle count.h]hQuery GPU cycle count.}(hj#~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hMhj ~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hMhj|ubj)}(h:``DRM_PANTHOR_TIMESTAMP_FREQ`` Query timestamp frequency. h](j)}(h``DRM_PANTHOR_TIMESTAMP_FREQ``h]jC)}(hjC~h]hDRM_PANTHOR_TIMESTAMP_FREQ}(hjE~hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjA~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj=~ubj)}(hhh]h)}(hQuery timestamp frequency.h]hQuery timestamp frequency.}(hj\~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjX~hMhjY~ubah}(h]h ]h"]h$]h&]uh1jhj=~ubeh}(h]h ]h"]h$]h&]uh1jhjX~hMhj|ubj)}(hA``DRM_PANTHOR_TIMESTAMP_DURATION`` Return duration of time query.h](j)}(h"``DRM_PANTHOR_TIMESTAMP_DURATION``h]jC)}(hj|~h]hDRM_PANTHOR_TIMESTAMP_DURATION}(hj~~hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjz~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjv~ubj)}(hhh]h)}(hReturn duration of time query.h]hReturn duration of time query.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj~ubah}(h]h ]h"]h$]h&]uh1jhjv~ubeh}(h]h ]h"]h$]h&]uh1jhj~hMhj|ubeh}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_panthor_timestamp_info (C struct)c.drm_panthor_timestamp_infohNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_timestamp_infoh]jg)}(h!struct drm_panthor_timestamp_infoh](jm)}(hjph]hstruct}(hj~hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj~hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj~hhhj~hMubj)}(hdrm_panthor_timestamp_infoh]j)}(hj~h]hdrm_panthor_timestamp_info}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj~hhhj~hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj~hhhj~hMubah}(h]j~ah ](jjeh"]h$]h&]jj)jhuh1j`hj~hMhj~hhubj)}(hhh]h)}(hTimestamp informationh]hTimestamp information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj~hhhj~hMubeh}(h]h ](jstructeh"]h$]h&]jjjj0jj0jjjuh1j[hhhjghNhNubj)}(hXI**Definition**:: struct drm_panthor_timestamp_info { __u64 timestamp_frequency; __u64 current_timestamp; __u64 timestamp_offset; __u32 flags; __u32 duration_nsec; __u64 cycle_count; __u64 cpu_timestamp_sec; __u64 cpu_timestamp_nsec; }; **Members** ``timestamp_frequency`` The frequency of the timestamp timer or 0 if unknown. ``current_timestamp`` The current GPU timestamp. ``timestamp_offset`` The offset of the GPU timestamp timer. ``flags`` Bitmask of drm_panthor_timestamp_info_flags. If set to 0, then it is interpreted as: DRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQ Note: these flags are exclusive to each other (only one can be used): - DRM_PANTHOR_TIMESTAMP_CPU_NONE - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW ``duration_nsec`` Duration of time query. ``cycle_count`` Value of GPU_CYCLE_COUNT. ``cpu_timestamp_sec`` Seconds part of CPU timestamp. ``cpu_timestamp_nsec`` Nanseconds part of CPU timestamp.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubh:}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj4ubj)}(hstruct drm_panthor_timestamp_info { __u64 timestamp_frequency; __u64 current_timestamp; __u64 timestamp_offset; __u32 flags; __u32 duration_nsec; __u64 cycle_count; __u64 cpu_timestamp_sec; __u64 cpu_timestamp_nsec; };h]hstruct drm_panthor_timestamp_info { __u64 timestamp_frequency; __u64 current_timestamp; __u64 timestamp_offset; __u32 flags; __u32 duration_nsec; __u64 cycle_count; __u64 cpu_timestamp_sec; __u64 cpu_timestamp_nsec; };}hjUsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj4ubh)}(h **Members**h]j)}(hjfh]hMembers}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj4ubj)}(hhh](j)}(hN``timestamp_frequency`` The frequency of the timestamp timer or 0 if unknown. h](j)}(h``timestamp_frequency``h]jC)}(hjh]htimestamp_frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h5The frequency of the timestamp timer or 0 if unknown.h]h5The frequency of the timestamp timer or 0 if unknown.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj|ubj)}(h1``current_timestamp`` The current GPU timestamp. h](j)}(h``current_timestamp``h]jC)}(hjh]hcurrent_timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hThe current GPU timestamp.h]hThe current GPU timestamp.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj|ubj)}(h<``timestamp_offset`` The offset of the GPU timestamp timer. h](j)}(h``timestamp_offset``h]jC)}(hjh]htimestamp_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h&The offset of the GPU timestamp timer.h]h&The offset of the GPU timestamp timer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhj|ubj)}(hXu``flags`` Bitmask of drm_panthor_timestamp_info_flags. If set to 0, then it is interpreted as: DRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQ Note: these flags are exclusive to each other (only one can be used): - DRM_PANTHOR_TIMESTAMP_CPU_NONE - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW h](j)}(h ``flags``h]jC)}(hj1h]hflags}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj+ubj)}(hhh](h)}(h,Bitmask of drm_panthor_timestamp_info_flags.h]h,Bitmask of drm_panthor_timestamp_info_flags.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjGubj)}(hhh]j)}(hIf set to 0, then it is interpreted as: DRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQ h](j)}(h'If set to 0, then it is interpreted as:h]h'If set to 0, then it is interpreted as:}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj\ubj)}(hhh]h)}(hYDRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQh]hYDRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQ}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjoubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjYubah}(h]h ]h"]h$]h&]uh1jhjGubh)}(hNote: these flags are exclusive to each other (only one can be used): - DRM_PANTHOR_TIMESTAMP_CPU_NONE - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAWh]hNote: these flags are exclusive to each other (only one can be used): - DRM_PANTHOR_TIMESTAMP_CPU_NONE - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjGubeh}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjFhMhj|ubj)}(h*``duration_nsec`` Duration of time query. h](j)}(h``duration_nsec``h]jC)}(hjh]h duration_nsec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hDuration of time query.h]hDuration of time query.}(hj̀hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjɀhMhjʀubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjɀhMhj|ubj)}(h*``cycle_count`` Value of GPU_CYCLE_COUNT. h](j)}(h``cycle_count``h]jC)}(hjh]h cycle_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hValue of GPU_CYCLE_COUNT.h]hValue of GPU_CYCLE_COUNT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj|ubj)}(h5``cpu_timestamp_sec`` Seconds part of CPU timestamp. h](j)}(h``cpu_timestamp_sec``h]jC)}(hj&h]hcpu_timestamp_sec}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj ubj)}(hhh]h)}(hSeconds part of CPU timestamp.h]hSeconds part of CPU timestamp.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj|ubj)}(h8``cpu_timestamp_nsec`` Nanseconds part of CPU timestamp.h](j)}(h``cpu_timestamp_nsec``h]jC)}(hj_h]hcpu_timestamp_nsec}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjYubj)}(hhh]h)}(h!Nanseconds part of CPU timestamp.h]h!Nanseconds part of CPU timestamp.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjuubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jhjthMhj|ubeh}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubh)}(hKStructure grouping all queryable information relating to the GPU timestamp.h]hKStructure grouping all queryable information relating to the GPU timestamp.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_panthor_mmu_info (C struct)c.drm_panthor_mmu_infohNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_mmu_infoh]jg)}(hstruct drm_panthor_mmu_infoh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj܁hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj܁hhhjhMubj)}(hdrm_panthor_mmu_infoh]j)}(hjځh]hdrm_panthor_mmu_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj܁hhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj؁hhhjhMubah}(h]jӁah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjՁhhubj)}(hhh]h)}(hMMU informationh]hMMU information}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjՁhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj:jj:jjjuh1j[hhhjghNhNubj)}(h**Definition**:: struct drm_panthor_mmu_info { __u64 page_size_bitmap; }; **Members** ``page_size_bitmap`` Allowed page sizesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubh:}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj>ubj)}(hubh)}(h **Members**h]j)}(hjph]hMembers}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj>ubj)}(hhh]j)}(h'``page_size_bitmap`` Allowed page sizesh](j)}(h``page_size_bitmap``h]jC)}(hjh]hpage_size_bitmap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hAllowed page sizesh]hAllowed page sizes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hj҂h]h Description}(hjԂhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjЂubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubh)}(hAStructure grouping all queryable information relating to the MMU.h]hAStructure grouping all queryable information relating to the MMU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW,drm_panthor_group_priorities_info (C struct)#c.drm_panthor_group_priorities_infohNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(h!drm_panthor_group_priorities_infoh]jg)}(h(struct drm_panthor_group_priorities_infoh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj hhhjhMubj)}(h!drm_panthor_group_priorities_infoh]j)}(hj h]h!drm_panthor_group_priorities_info}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(hGroup priorities informationh]hGroup priorities information}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjOhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjjjuh1j[hhhjghNhNubj)}(hX"**Definition**:: struct drm_panthor_group_priorities_info { __u8 allowed_mask; __u8 pad[3]; }; **Members** ``allowed_mask`` Bitmask of the allowed group priorities. Each bit represents a variant of the enum drm_panthor_group_priority. ``pad`` Padding fields, MBZ.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubh:}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjnubj)}(hUstruct drm_panthor_group_priorities_info { __u8 allowed_mask; __u8 pad[3]; };h]hUstruct drm_panthor_group_priorities_info { __u8 allowed_mask; __u8 pad[3]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjnubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjnubj)}(hhh](j)}(h``allowed_mask`` Bitmask of the allowed group priorities. Each bit represents a variant of the enum drm_panthor_group_priority. h](j)}(h``allowed_mask``h]jC)}(hjh]h allowed_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h(Bitmask of the allowed group priorities.h]h(Bitmask of the allowed group priorities.}(hj؃hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjՃubh)}(hEEach bit represents a variant of the enum drm_panthor_group_priority.h]hEEach bit represents a variant of the enum drm_panthor_group_priority.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjԃhMhjՃubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjԃhMhjubj)}(h``pad`` Padding fields, MBZ.h](j)}(h``pad``h]jC)}(hjh]hpad}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hPadding fields, MBZ.h]hPadding fields, MBZ.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hjJh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubh)}(hVStructure grouping all queryable information relating to the allowed group priorities.h]hVStructure grouping all queryable information relating to the allowed group priorities.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_panthor_dev_query (C struct)c.drm_panthor_dev_queryhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_dev_queryh]jg)}(hstruct drm_panthor_dev_queryh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_panthor_dev_queryh]j)}(hjh]hdrm_panthor_dev_query}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]j{ah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhj}hhubj)}(hhh]h)}(h/Arguments passed to DRM_PANTHOR_IOCTL_DEV_QUERYh]h/Arguments passed to DRM_PANTHOR_IOCTL_DEV_QUERY}(hjʄhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hjDŽhhubah}(h]h ]h"]h$]h&]uh1jhj}hhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; }; **Members** ``type`` the query type (see drm_panthor_dev_query_type). ``size`` size of the type being queried. If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace. ``pointer`` user pointer to a query type struct. Pointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hjubj)}(hTstruct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; };h]hTstruct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](j)}(h:``type`` the query type (see drm_panthor_dev_query_type). h](j)}(h``type``h]jC)}(hj7h]htype}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj5ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hj1ubj)}(hhh]h)}(h0the query type (see drm_panthor_dev_query_type).h]h0the query type (see drm_panthor_dev_query_type).}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM hjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhM hj.ubj)}(hXM``size`` size of the type being queried. If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace. h](j)}(h``size``h]jC)}(hjph]hsize}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjnubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjjubj)}(hhh](h)}(hsize of the type being queried.h]hsize of the type being queried.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hX"If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace.h]hX"If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj.ubj)}(h``pointer`` user pointer to a query type struct. Pointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h](j)}(h ``pointer``h]jC)}(hjh]hpointer:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h$user pointer to a query type struct.h]h$user pointer to a query type struct.}(hj҅hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjυubh)}(hPointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h]hPointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that’s large enough to hold size bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjυubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj΅hMhj.ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_panthor_vm_create (C struct)c.drm_panthor_vm_createhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_vm_createh]jg)}(hstruct drm_panthor_vm_createh](jm)}(hjph]hstruct}(hj"hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM&ubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhj/hM&ubj)}(hdrm_panthor_vm_createh]j)}(hjh]hdrm_panthor_vm_create}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj/hM&ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhj/hM&ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hj/hM&hjhhubj)}(hhh]h)}(h/Arguments passed to DRM_PANTHOR_IOCTL_VM_CREATEh]h/Arguments passed to DRM_PANTHOR_IOCTL_VM_CREATE}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM%hjahhubah}(h]h ]h"]h$]h&]uh1jhjhhhj/hM&ubeh}(h]h ](jstructeh"]h$]h&]jjjj|jj|jjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; }; **Members** ``flags`` VM flags, MBZ. ``id`` Returned VM ID. ``user_va_range`` Size of the VA space reserved for user objects. The kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel. If user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**. User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM)hjubj)}(hYstruct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; };h]hYstruct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM+hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM1hjubj)}(hhh](j)}(h``flags`` VM flags, MBZ. h](j)}(h ``flags``h]jC)}(hjцh]hflags}(hjӆhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjφubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM)hjˆubj)}(hhh]h)}(hVM flags, MBZ.h]hVM flags, MBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM)hjubah}(h]h ]h"]h$]h&]uh1jhjˆubeh}(h]h ]h"]h$]h&]uh1jhjhM)hjȆubj)}(h``id`` Returned VM ID. h](j)}(h``id``h]jC)}(hj h]hid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM,hjubj)}(hhh]h)}(hReturned VM ID.h]hReturned VM ID.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM,hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM,hjȆubj)}(hX``user_va_range`` Size of the VA space reserved for user objects. The kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel. If user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**. User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h](j)}(h``user_va_range``h]jC)}(hjCh]h user_va_range}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjAubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM@hj=ubj)}(hhh](h)}(h/Size of the VA space reserved for user objects.h]h/Size of the VA space reserved for user objects.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM0hjYubh)}(hXThe kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel.h]hXThe kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM2hjYubh)}(hXIf user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**.h](hXoIf user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in }(hjzhhhNhNubj)}(h**user_va_range**h]h user_va_range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubh.}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM9hjYubh)}(h]User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h]h]User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhM@hjYubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhjXhM@hjȆubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW!drm_panthor_vm_destroy (C struct)c.drm_panthor_vm_destroyhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_vm_destroyh]jg)}(hstruct drm_panthor_vm_destroyh](jm)}(hjph]hstruct}(hjۇhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjׇhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMGubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjׇhhhjhMGubj)}(hdrm_panthor_vm_destroyh]j)}(hjՇh]hdrm_panthor_vm_destroy}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjׇhhhjhMGubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjӇhhhjhMGubah}(h]j·ah ](jjeh"]h$]h&]jj)jhuh1j`hjhMGhjЇhhubj)}(hhh]h)}(h0Arguments passed to DRM_PANTHOR_IOCTL_VM_DESTROYh]h0Arguments passed to DRM_PANTHOR_IOCTL_VM_DESTROY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMFhjhhubah}(h]h ]h"]h$]h&]uh1jhjЇhhhjhMGubeh}(h]h ](jstructeh"]h$]h&]jjjj5jj5jjjuh1j[hhhjghNhNubj)}(h**Definition**:: struct drm_panthor_vm_destroy { __u32 id; __u32 pad; }; **Members** ``id`` ID of the VM to destroy. ``pad`` MBZ.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh:}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMJhj9ubj)}(h?struct drm_panthor_vm_destroy { __u32 id; __u32 pad; };h]h?struct drm_panthor_vm_destroy { __u32 id; __u32 pad; };}hjZsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMLhj9ubh)}(h **Members**h]j)}(hjkh]hMembers}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMQhj9ubj)}(hhh](j)}(h ``id`` ID of the VM to destroy. h](j)}(h``id``h]jC)}(hjh]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMJhjubj)}(hhh]h)}(hID of the VM to destroy.h]hID of the VM to destroy.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMJhjubj)}(h ``pad`` MBZ.h](j)}(h``pad``h]jC)}(hjÈh]hpad}(hjňhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMLhjubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hj܈hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMMhjوubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj؈hMLhjubeh}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_panthor_vm_bind_op_flags (C enum)c.drm_panthor_vm_bind_op_flagshNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_vm_bind_op_flagsh]jg)}(h!enum drm_panthor_vm_bind_op_flagsh](jm)}(hjh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMSubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhj*hMSubj)}(hdrm_panthor_vm_bind_op_flagsh]j)}(hjh]hdrm_panthor_vm_bind_op_flags}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj*hMSubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhj*hMSubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hj*hMShjhhubj)}(hhh]h)}(hVM bind operation flagsh]hVM bind operation flags}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMQhj\hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj*hMSubeh}(h]h ](jenumeh"]h$]h&]jjjjwjjwjjjuh1j[hhhjghNhNubj)}(hX/**Constants** ``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY`` Map the memory read-only. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC`` Map the memory not-executable. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED`` Map the memory uncached. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_MAP_SPARSE`` Sparsely map a virtual memory range Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. When this flag is set, the whole vm_bind range is mapped over a dummy object in a cyclic fashion, and all GPU reads from addresses in the range return undefined values. This flag being set means drm_panthor_vm_bind_op::bo_offset and drm_panthor_vm_bind_op::bo_handle must both be set to 0. DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC must also be set. ``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK`` Mask used to determine the type of operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP`` Map operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP`` Unmap operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY`` No VM operation. Just serves as a synchronization point on a VM queue. Only valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMUhj{ubj)}(hhh](j)}(ht``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY`` Map the memory read-only. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h'``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY``h]jC)}(hjh]h#DRM_PANTHOR_VM_BIND_OP_MAP_READONLY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMZhjubj)}(hhh](h)}(hMap the memory read-only.h]hMap the memory read-only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMXhjubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hjȉhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMZhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMZhjubj)}(hw``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC`` Map the memory not-executable. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h%``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC``h]jC)}(hjh]h!DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM_hjubj)}(hhh](h)}(hMap the memory not-executable.h]hMap the memory not-executable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM]hjubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM_hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM_hjubj)}(hs``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED`` Map the memory uncached. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h'``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED``h]jC)}(hj0h]h#DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj.ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMdhj*ubj)}(hhh](h)}(hMap the memory uncached.h]hMap the memory uncached.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMbhjFubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMdhjFubeh}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhjEhMdhjubj)}(hX``DRM_PANTHOR_VM_BIND_OP_MAP_SPARSE`` Sparsely map a virtual memory range Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. When this flag is set, the whole vm_bind range is mapped over a dummy object in a cyclic fashion, and all GPU reads from addresses in the range return undefined values. This flag being set means drm_panthor_vm_bind_op::bo_offset and drm_panthor_vm_bind_op::bo_handle must both be set to 0. DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC must also be set. h](j)}(h%``DRM_PANTHOR_VM_BIND_OP_MAP_SPARSE``h]jC)}(hjxh]h!DRM_PANTHOR_VM_BIND_OP_MAP_SPARSE}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMnhjrubj)}(hhh](h)}(h#Sparsely map a virtual memory rangeh]h#Sparsely map a virtual memory range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMghjubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMihjubh)}(hXUWhen this flag is set, the whole vm_bind range is mapped over a dummy object in a cyclic fashion, and all GPU reads from addresses in the range return undefined values. This flag being set means drm_panthor_vm_bind_op::bo_offset and drm_panthor_vm_bind_op::bo_handle must both be set to 0. DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC must also be set.h]hXUWhen this flag is set, the whole vm_bind range is mapped over a dummy object in a cyclic fashion, and all GPU reads from addresses in the range return undefined values. This flag being set means drm_panthor_vm_bind_op::bo_offset and drm_panthor_vm_bind_op::bo_handle must both be set to 0. DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC must also be set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMkhjubeh}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jhjhMnhjubj)}(hS``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK`` Mask used to determine the type of operation. h](j)}(h$``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK``h]jC)}(hjЊh]h DRM_PANTHOR_VM_BIND_OP_TYPE_MASK}(hjҊhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjΊubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMqhjʊubj)}(hhh]h)}(h-Mask used to determine the type of operation.h]h-Mask used to determine the type of operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMqhjubah}(h]h ]h"]h$]h&]uh1jhjʊubeh}(h]h ]h"]h$]h&]uh1jhjhMqhjubj)}(h3``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP`` Map operation. h](j)}(h#``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP``h]jC)}(hj h]hDRM_PANTHOR_VM_BIND_OP_TYPE_MAP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMthjubj)}(hhh]h)}(hMap operation.h]hMap operation.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMthjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMthjubj)}(h7``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP`` Unmap operation. h](j)}(h%``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP``h]jC)}(hjBh]h!DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMwhj<ubj)}(hhh]h)}(hUnmap operation.h]hUnmap operation.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhMwhjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhMwhjubj)}(hX``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY`` No VM operation. Just serves as a synchronization point on a VM queue. Only valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](j)}(h)``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY``h]jC)}(hj{h]h%DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjyubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM~hjuubj)}(hhh](h)}(hNo VM operation.h]hNo VM operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMzhjubh)}(h5Just serves as a synchronization point on a VM queue.h]h5Just serves as a synchronization point on a VM queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM|hjubh)}(hOnly valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](hOnly valid if }(hjhhhNhNubjC)}(h``DRM_PANTHOR_VM_BIND_ASYNC``h]hDRM_PANTHOR_VM_BIND_ASYNC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhg is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM~hjubeh}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjhM~hjubeh}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW!drm_panthor_vm_bind_op (C struct)c.drm_panthor_vm_bind_ophNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_vm_bind_oph]jg)}(hstruct drm_panthor_vm_bind_oph](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_panthor_vm_bind_oph]j)}(hjh]hdrm_panthor_vm_bind_op}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(hVM bind operationh]hVM bind operation}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjChhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj^jj^jjjuh1j[hhhjghNhNubj)}(hX`**Definition**:: struct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; }; **Members** ``flags`` Combination of drm_panthor_vm_bind_op_flags flags. ``bo_handle`` Handle of the buffer object to map. MBZ for unmap or sync-only operations. ``bo_offset`` Buffer object offset. MBZ for unmap or sync-only operations. ``va`` Virtual address to map/unmap. MBZ for sync-only operations. ``size`` Size to map/unmap. MBZ for sync-only operations. ``syncs`` Array of struct drm_panthor_sync_op synchronization operations. This array must be empty if ``DRM_PANTHOR_VM_BIND_ASYNC`` is not set on the drm_panthor_vm_bind object containing this VM bind operation. This array shall not be empty for sync-only operations.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubh:}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjbubj)}(hstruct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; };h]hstruct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjbubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjbubj)}(hhh](j)}(h=``flags`` Combination of drm_panthor_vm_bind_op_flags flags. h](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h2Combination of drm_panthor_vm_bind_op_flags flags.h]h2Combination of drm_panthor_vm_bind_op_flags flags.}(hǰhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjȌhMhjɌubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjȌhMhjubj)}(hY``bo_handle`` Handle of the buffer object to map. MBZ for unmap or sync-only operations. h](j)}(h ``bo_handle``h]jC)}(hjh]h bo_handle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hJHandle of the buffer object to map. MBZ for unmap or sync-only operations.h]hJHandle of the buffer object to map. MBZ for unmap or sync-only operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hK``bo_offset`` Buffer object offset. MBZ for unmap or sync-only operations. h](j)}(h ``bo_offset``h]jC)}(hj&h]h bo_offset}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj ubj)}(hhh]h)}(h**Definition**:: struct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; }; **Members** ``vm_id`` VM targeted by the bind request. ``flags`` Combination of drm_panthor_vm_bind_flags flags. ``ops`` Array of struct drm_panthor_vm_bind_op bind operations.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hgstruct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; };h]hgstruct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]j)}(hjʏh]hMembers}(hj̏hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȏubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](j)}(h+``vm_id`` VM targeted by the bind request. h](j)}(h ``vm_id``h]jC)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h VM targeted by the bind request.h]h VM targeted by the bind request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h:``flags`` Combination of drm_panthor_vm_bind_flags flags. h](j)}(h ``flags``h]jC)}(hj"h]hflags}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h/Combination of drm_panthor_vm_bind_flags flags.h]h/Combination of drm_panthor_vm_bind_flags flags.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj7hMhjubj)}(h?``ops`` Array of struct drm_panthor_vm_bind_op bind operations.h](j)}(h``ops``h]jC)}(hj[h]hops}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjYubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjUubj)}(hhh]h)}(h7Array of struct drm_panthor_vm_bind_op bind operations.h]h7Array of struct drm_panthor_vm_bind_op bind operations.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjphMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_panthor_vm_state (C enum)c.drm_panthor_vm_statehNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_vm_stateh]jg)}(henum drm_panthor_vm_stateh](jm)}(hjh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjÐhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_panthor_vm_stateh]j)}(hjh]hdrm_panthor_vm_state}(hjՐhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjѐubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(h VM states.h]h VM states.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX**Constants** ``DRM_PANTHOR_VM_STATE_USABLE`` VM is usable. New VM operations will be accepted on this VM. ``DRM_PANTHOR_VM_STATE_UNUSABLE`` VM is unusable. Something put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason). Once the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted. The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](j)}(h^``DRM_PANTHOR_VM_STATE_USABLE`` VM is usable. New VM operations will be accepted on this VM. h](j)}(h``DRM_PANTHOR_VM_STATE_USABLE``h]jC)}(hj8h]hDRM_PANTHOR_VM_STATE_USABLE}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj6ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj2ubj)}(hhh](h)}(h VM is usable.h]h VM is usable.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjNubh)}(h.New VM operations will be accepted on this VM.h]h.New VM operations will be accepted on this VM.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhMhjNubeh}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhjMhMhj/ubj)}(hX``DRM_PANTHOR_VM_STATE_UNUSABLE`` VM is unusable. Something put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason). Once the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted. The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h](j)}(h!``DRM_PANTHOR_VM_STATE_UNUSABLE``h]jC)}(hjh]hDRM_PANTHOR_VM_STATE_UNUSABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjzubj)}(hhh](h)}(hVM is unusable.h]hVM is unusable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hhSomething put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason).h]hhSomething put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hOnce the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted.h]hOnce the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h[The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h]h[The only way to recover from an unusable VM is to create a new VM, and destroy the old one.}(hjƑhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jhjhMhj/ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_panthor_vm_get_state (C struct)c.drm_panthor_vm_get_statehNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_vm_get_stateh]jg)}(hstruct drm_panthor_vm_get_stateh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_panthor_vm_get_stateh]j)}(hjh]hdrm_panthor_vm_get_state}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(h Get VM state.h]h Get VM state.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjEhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj`jj`jjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; }; **Members** ``vm_id`` VM targeted by the get_state request. ``state`` state returned by the driver. Must be one of the enum drm_panthor_vm_state values.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubh:}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjdubj)}(hFstruct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; };h]hFstruct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjdubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjdubj)}(hhh](j)}(h0``vm_id`` VM targeted by the get_state request. h](j)}(h ``vm_id``h]jC)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h%VM targeted by the get_state request.h]h%VM targeted by the get_state request.}(hjΒhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjʒhMhj˒ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjʒhMhjubj)}(h]``state`` state returned by the driver. Must be one of the enum drm_panthor_vm_state values.h](j)}(h ``state``h]jC)}(hjh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(hstate returned by the driver.h]hstate returned by the driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h4Must be one of the enum drm_panthor_vm_state values.h]h4Must be one of the enum drm_panthor_vm_state values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_panthor_bo_flags (C enum)c.drm_panthor_bo_flagshNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_flagsh]jg)}(henum drm_panthor_bo_flagsh](jm)}(hjh]henum}(hjWhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjShhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjShhhjdhMubj)}(hdrm_panthor_bo_flagsh]j)}(hjQh]hdrm_panthor_bo_flags}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ](jjeh"]h$]h&]jjuh1jhjShhhjdhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjOhhhjdhMubah}(h]jJah ](jjeh"]h$]h&]jj)jhuh1j`hjdhMhjLhhubj)}(hhh]h)}(h-Buffer object flags, passed at creation time.h]h-Buffer object flags, passed at creation time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjLhhhjdhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hXp**Constants** ``DRM_PANTHOR_BO_NO_MMAP`` The buffer object will never be CPU-mapped in userspace. ``DRM_PANTHOR_BO_WB_MMAP`` Force "Write-Back Cacheable" CPU mapping. CPU map the buffer object in userspace by forcing the "Write-Back Cacheable" cacheability attribute. The mapping otherwise uses the "Non-Cacheable" attribute if the GPU is not IO coherent.h](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](j)}(hT``DRM_PANTHOR_BO_NO_MMAP`` The buffer object will never be CPU-mapped in userspace. h](j)}(h``DRM_PANTHOR_BO_NO_MMAP``h]jC)}(hjړh]hDRM_PANTHOR_BO_NO_MMAP}(hjܓhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjؓubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjԓubj)}(hhh]h)}(h8The buffer object will never be CPU-mapped in userspace.h]h8The buffer object will never be CPU-mapped in userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjԓubeh}(h]h ]h"]h$]h&]uh1jhjhMhjѓubj)}(hX``DRM_PANTHOR_BO_WB_MMAP`` Force "Write-Back Cacheable" CPU mapping. CPU map the buffer object in userspace by forcing the "Write-Back Cacheable" cacheability attribute. The mapping otherwise uses the "Non-Cacheable" attribute if the GPU is not IO coherent.h](j)}(h``DRM_PANTHOR_BO_WB_MMAP``h]jC)}(hjh]hDRM_PANTHOR_BO_WB_MMAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj ubj)}(hhh](h)}(h)Force "Write-Back Cacheable" CPU mapping.h]h-Force “Write-Back Cacheable” CPU mapping.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj)ubh)}(hCPU map the buffer object in userspace by forcing the "Write-Back Cacheable" cacheability attribute. The mapping otherwise uses the "Non-Cacheable" attribute if the GPU is not IO coherent.h]hCPU map the buffer object in userspace by forcing the “Write-Back Cacheable” cacheability attribute. The mapping otherwise uses the “Non-Cacheable” attribute if the GPU is not IO coherent.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj)ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhjѓubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_panthor_bo_create (C struct)c.drm_panthor_bo_createhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_createh]jg)}(hstruct drm_panthor_bo_createh](jm)}(hjph]hstruct}(hj|hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjxhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjxhhhjhM ubj)}(hdrm_panthor_bo_createh]j)}(hjvh]hdrm_panthor_bo_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjxhhhjhM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjthhhjhM ubah}(h]joah ](jjeh"]h$]h&]jj)jhuh1j`hjhM hjqhhubj)}(hhh]h)}(h0Arguments passed to DRM_IOCTL_PANTHOR_BO_CREATE.h]h0Arguments passed to DRM_IOCTL_PANTHOR_BO_CREATE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hjhhubah}(h]h ]h"]h$]h&]uh1jhjqhhhjhM ubeh}(h]h ](jstructeh"]h$]h&]jjjj֔jj֔jjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; }; **Members** ``size`` Requested size for the object The (page-aligned) allocated size for the object will be returned. ``flags`` Flags. Must be a combination of drm_panthor_bo_flags flags. ``exclusive_vm_id`` Exclusive VM this buffer object will be mapped to. If not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd ``handle`` Returned handle for the object. Object handles are nonzero. ``pad`` MBZ.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjޔubh:}(hjޔhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjڔubj)}(h~struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; };h]h~struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjڔubh)}(h **Members**h]j)}(hj h]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjڔubj)}(hhh](j)}(hk``size`` Requested size for the object The (page-aligned) allocated size for the object will be returned. h](j)}(h``size``h]jC)}(hj+h]hsize}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj)ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj%ubj)}(hhh](h)}(hRequested size for the objecth]hRequested size for the object}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjAubh)}(hBThe (page-aligned) allocated size for the object will be returned.h]hBThe (page-aligned) allocated size for the object will be returned.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhjAubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj"ubj)}(hF``flags`` Flags. Must be a combination of drm_panthor_bo_flags flags. h](j)}(h ``flags``h]jC)}(hjsh]hflags}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjqubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjmubj)}(hhh]h)}(h;Flags. Must be a combination of drm_panthor_bo_flags flags.h]h;Flags. Must be a combination of drm_panthor_bo_flags flags.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjhMhj"ubj)}(h``exclusive_vm_id`` Exclusive VM this buffer object will be mapped to. If not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd h](j)}(h``exclusive_vm_id``h]jC)}(hjh]hexclusive_vm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hjubj)}(hhh](h)}(h2Exclusive VM this buffer object will be mapped to.h]h2Exclusive VM this buffer object will be mapped to.}(hjŕhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj•ubj)}(hhh]j)}(hIf not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd h](j)}(hEIf not zero, the field must refer to a valid VM ID, and implies that:h]hEIf not zero, the field must refer to a valid VM ID, and implies that:}(hjەhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjוubj)}(hhh]h)}(hhh](h)}(h4the buffer object will only ever be bound to that VMh]h)}(hjh]h4the buffer object will only ever be bound to that VM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.h;hMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h!cannot be exported as a PRIME fd h]h)}(h cannot be exported as a PRIME fdh]h cannot be exported as a PRIME fd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j j uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjוubeh}(h]h ]h"]h$]h&]uh1jhjhM hjԕubah}(h]h ]h"]h$]h&]uh1jhj•ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hj"ubj)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]jC)}(hjIh]hhandle}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjGubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM'hjCubj)}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM%hj_ubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hM'hj_ubeh}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhj^hM'hj"ubj)}(h ``pad`` MBZ.h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM*hjubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM+hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM*hj"ubeh}(h]h ]h"]h$]h&]uh1jhjڔubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_panthor_bo_mmap_offset (C struct)c.drm_panthor_bo_mmap_offsethNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_mmap_offseth]jg)}(h!struct drm_panthor_bo_mmap_offseth](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM1ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhM1ubj)}(hdrm_panthor_bo_mmap_offseth]j)}(hjh]hdrm_panthor_bo_mmap_offset}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM1ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhM1ubah}(h]jޖah ](jjeh"]h$]h&]jj)jhuh1j`hjhM1hjhhubj)}(hhh]h)}(h5Arguments passed to DRM_IOCTL_PANTHOR_BO_MMAP_OFFSET.h]h5Arguments passed to DRM_IOCTL_PANTHOR_BO_MMAP_OFFSET.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM/hj*hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM1ubeh}(h]h ](jstructeh"]h$]h&]jjjjEjjEjjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; }; **Members** ``handle`` Handle of the object we want an mmap offset for. ``pad`` MBZ. ``offset`` The fake offset to use for subsequent mmap calls.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubh:}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM3hjIubj)}(hYstruct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; };h]hYstruct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; };}hjjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM5hjIubh)}(h **Members**h]j)}(hj{h]hMembers}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM;hjIubj)}(hhh](j)}(h<``handle`` Handle of the object we want an mmap offset for. h](j)}(h ``handle``h]jC)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM3hjubj)}(hhh]h)}(h0Handle of the object we want an mmap offset for.h]h0Handle of the object we want an mmap offset for.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM3hjubj)}(h ``pad`` MBZ. h](j)}(h``pad``h]jC)}(hjӗh]hpad}(hj՗hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjїubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM6hj͗ubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM6hjubah}(h]h ]h"]h$]h&]uh1jhj͗ubeh}(h]h ]h"]h$]h&]uh1jhjhM6hjubj)}(h<``offset`` The fake offset to use for subsequent mmap calls.h](j)}(h ``offset``h]jC)}(hj h]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM8hjubj)}(hhh]h)}(h1The fake offset to use for subsequent mmap calls.h]h1The fake offset to use for subsequent mmap calls.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM9hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj!hM8hjubeh}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_panthor_queue_create (C struct)c.drm_panthor_queue_createhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_queue_createh]jg)}(hstruct drm_panthor_queue_createh](jm)}(hjph]hstruct}(hjfhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjbhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM?ubj)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjbhhhjshM?ubj)}(hdrm_panthor_queue_createh]j)}(hj`h]hdrm_panthor_queue_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjbhhhjshM?ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj^hhhjshM?ubah}(h]jYah ](jjeh"]h$]h&]jj)jhuh1j`hjshM?hj[hhubj)}(hhh]h)}(hQueue creation arguments.h]hQueue creation arguments.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM=hjhhubah}(h]h ]h"]h$]h&]uh1jhj[hhhjshM?ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hXc**Definition**:: struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; }; **Members** ``priority`` Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority. ``pad`` Padding fields, MBZ. ``ringbuf_size`` Size of the ring buffer to allocate to this queue.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj̘hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȘubh:}(hjȘhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMAhjĘubj)}(h`struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; };h]h`struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMChjĘubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMIhjĘubj)}(hhh](j)}(hn``priority`` Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority. h](j)}(h ``priority``h]jC)}(hjh]hpriority}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMChjubj)}(hhh]h)}(h`Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority.h]h`Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMBhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hMChj ubj)}(h``pad`` Padding fields, MBZ. h](j)}(h``pad``h]jC)}(hjOh]hpad}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjMubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMGhjIubj)}(hhh]h)}(hPadding fields, MBZ.h]hPadding fields, MBZ.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMGhjeubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhjdhMGhj ubj)}(hC``ringbuf_size`` Size of the ring buffer to allocate to this queue.h](j)}(h``ringbuf_size``h]jC)}(hjh]h ringbuf_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMIhjubj)}(hhh]h)}(h2Size of the ring buffer to allocate to this queue.h]h2Size of the ring buffer to allocate to this queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMIhj ubeh}(h]h ]h"]h$]h&]uh1jhjĘubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_panthor_group_priority (C enum)c.drm_panthor_group_priorityhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_group_priorityh]jg)}(henum drm_panthor_group_priorityh](jm)}(hjh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjޙhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMPubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjޙhhhjhMPubj)}(hdrm_panthor_group_priorityh]j)}(hjܙh]hdrm_panthor_group_priority}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjޙhhhjhMPubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjڙhhhjhMPubah}(h]jՙah ](jjeh"]h$]h&]jj)jhuh1j`hjhMPhjיhhubj)}(hhh]h)}(hScheduling group priorityh]hScheduling group priority}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMNhj!hhubah}(h]h ]h"]h$]h&]uh1jhjיhhhjhMPubeh}(h]h ](jenumeh"]h$]h&]jjjj<jj<jjjuh1j[hhhjghNhNubj)}(hXG**Constants** ``PANTHOR_GROUP_PRIORITY_LOW`` Low priority group. ``PANTHOR_GROUP_PRIORITY_MEDIUM`` Medium priority group. ``PANTHOR_GROUP_PRIORITY_HIGH`` High priority group. Requires CAP_SYS_NICE or DRM_MASTER. ``PANTHOR_GROUP_PRIORITY_REALTIME`` Realtime priority group. Requires CAP_SYS_NICE or DRM_MASTER.h](h)}(h **Constants**h]j)}(hjFh]h Constants}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMRhj@ubj)}(hhh](j)}(h3``PANTHOR_GROUP_PRIORITY_LOW`` Low priority group. h](j)}(h``PANTHOR_GROUP_PRIORITY_LOW``h]jC)}(hjeh]hPANTHOR_GROUP_PRIORITY_LOW}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjcubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMUhj_ubj)}(hhh]h)}(hLow priority group.h]hLow priority group.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMUhj{ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jhjzhMUhj\ubj)}(h9``PANTHOR_GROUP_PRIORITY_MEDIUM`` Medium priority group. h](j)}(h!``PANTHOR_GROUP_PRIORITY_MEDIUM``h]jC)}(hjh]hPANTHOR_GROUP_PRIORITY_MEDIUM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMXhjubj)}(hhh]h)}(hMedium priority group.h]hMedium priority group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMXhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMXhj\ubj)}(h[``PANTHOR_GROUP_PRIORITY_HIGH`` High priority group. Requires CAP_SYS_NICE or DRM_MASTER. h](j)}(h``PANTHOR_GROUP_PRIORITY_HIGH``h]jC)}(hjךh]hPANTHOR_GROUP_PRIORITY_HIGH}(hjٚhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj՚ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM]hjњubj)}(hhh](h)}(hHigh priority group.h]hHigh priority group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM[hjubh)}(h$Requires CAP_SYS_NICE or DRM_MASTER.h]h$Requires CAP_SYS_NICE or DRM_MASTER.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM]hjubeh}(h]h ]h"]h$]h&]uh1jhjњubeh}(h]h ]h"]h$]h&]uh1jhjhM]hj\ubj)}(hb``PANTHOR_GROUP_PRIORITY_REALTIME`` Realtime priority group. Requires CAP_SYS_NICE or DRM_MASTER.h](j)}(h#``PANTHOR_GROUP_PRIORITY_REALTIME``h]jC)}(hjh]hPANTHOR_GROUP_PRIORITY_REALTIME}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMahjubj)}(hhh](h)}(hRealtime priority group.h]hRealtime priority group.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM`hj5ubh)}(h$Requires CAP_SYS_NICE or DRM_MASTER.h]h$Requires CAP_SYS_NICE or DRM_MASTER.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMbhj5ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj4hMahj\ubeh}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_panthor_group_create (C struct)c.drm_panthor_group_createhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_group_createh]jg)}(hstruct drm_panthor_group_createh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMgubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMgubj)}(hdrm_panthor_group_createh]j)}(hjh]hdrm_panthor_group_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMgubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMgubah}(h]j{ah ](jjeh"]h$]h&]jj)jhuh1j`hjhMghj}hhubj)}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_CREATEh]h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_CREATE}(hjʛhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMghjǛhhubah}(h]h ]h"]h$]h&]uh1jhj}hhhjhMgubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; }; **Members** ``queues`` Array of drm_panthor_queue_create elements. ``max_compute_cores`` Maximum number of cores that can be used by compute jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **compute_core_mask**. ``max_fragment_cores`` Maximum number of cores that can be used by fragment jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **fragment_core_mask**. ``max_tiler_cores`` Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **tiler_core_mask**. ``priority`` Group priority (see enum drm_panthor_group_priority). ``pad`` Padding field, MBZ. ``compute_core_mask`` Mask encoding cores that can be used for compute jobs. This field must have at least **max_compute_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. ``fragment_core_mask`` Mask encoding cores that can be used for fragment jobs. This field must have at least **max_fragment_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. ``tiler_core_mask`` Mask encoding cores that can be used for tiler jobs. This field must have at least **max_tiler_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::tiler_present. ``vm_id`` VM ID to bind this group to. All submission to queues bound to this group will use this VM. ``group_handle`` Returned group handle. Passed back when submitting jobs or destroying a group.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMkhjubj)}(hXAstruct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; };h]hXAstruct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMmhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM{hjubj)}(hhh](j)}(h7``queues`` Array of drm_panthor_queue_create elements. h](j)}(h ``queues``h]jC)}(hj7h]hqueues}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj5ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMkhj1ubj)}(hhh]h)}(h+Array of drm_panthor_queue_create elements.h]h+Array of drm_panthor_queue_create elements.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhMkhjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhMkhj.ubj)}(h``max_compute_cores`` Maximum number of cores that can be used by compute jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **compute_core_mask**. h](j)}(h``max_compute_cores``h]jC)}(hjph]hmax_compute_cores}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjnubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMrhjjubj)}(hhh](h)}(h^Maximum number of cores that can be used by compute jobs across CS queues bound to this group.h]h^Maximum number of cores that can be used by compute jobs across CS queues bound to this group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMohjubh)}(hIMust be less or equal to the number of bits set in **compute_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjhhhNhNubj)}(h**compute_core_mask**h]hcompute_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMrhjubeh}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjhMrhj.ubj)}(h``max_fragment_cores`` Maximum number of cores that can be used by fragment jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **fragment_core_mask**. h](j)}(h``max_fragment_cores``h]jC)}(hjʜh]hmax_fragment_cores}(hj̜hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjȜubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMzhjĜubj)}(hhh](h)}(h_Maximum number of cores that can be used by fragment jobs across CS queues bound to this group.h]h_Maximum number of cores that can be used by fragment jobs across CS queues bound to this group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMwhjubh)}(hJMust be less or equal to the number of bits set in **fragment_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjhhhNhNubj)}(h**fragment_core_mask**h]hfragment_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjߜhMzhjubeh}(h]h ]h"]h$]h&]uh1jhjĜubeh}(h]h ]h"]h$]h&]uh1jhjߜhMzhj.ubj)}(h``max_tiler_cores`` Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **tiler_core_mask**. h](j)}(h``max_tiler_cores``h]jC)}(hj$h]hmax_tiler_cores}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj"ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h]Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group.h]h]Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj:ubh)}(hGMust be less or equal to the number of bits set in **tiler_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjLhhhNhNubj)}(h**tiler_core_mask**h]htiler_core_mask}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubh.}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj9hMhj:ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj.ubj)}(hC``priority`` Group priority (see enum drm_panthor_group_priority). h](j)}(h ``priority``h]jC)}(hj~h]hpriority}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjxubj)}(hhh]h)}(h5Group priority (see enum drm_panthor_group_priority).h]h5Group priority (see enum drm_panthor_group_priority).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjhMhj.ubj)}(h``pad`` Padding field, MBZ. h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hjНhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj̝hMhj͝ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj̝hMhj.ubj)}(h``compute_core_mask`` Mask encoding cores that can be used for compute jobs. This field must have at least **max_compute_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. h](j)}(h``compute_core_mask``h]jC)}(hjh]hcompute_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h6Mask encoding cores that can be used for compute jobs.h]h6Mask encoding cores that can be used for compute jobs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h=This field must have at least **max_compute_cores** bits set.h](hThis field must have at least }(hjhhhNhNubj)}(h**max_compute_cores**h]hmax_compute_cores}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh bits set.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.h]hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj.ubj)}(h``fragment_core_mask`` Mask encoding cores that can be used for fragment jobs. This field must have at least **max_fragment_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. h](j)}(h``fragment_core_mask``h]jC)}(hjYh]hfragment_core_mask}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjWubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjSubj)}(hhh](h)}(h7Mask encoding cores that can be used for fragment jobs.h]h7Mask encoding cores that can be used for fragment jobs.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjoubh)}(h>This field must have at least **max_fragment_cores** bits set.h](hThis field must have at least }(hjhhhNhNubj)}(h**max_fragment_cores**h]hmax_fragment_cores}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh bits set.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjoubh)}(hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.h]hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjoubeh}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhjnhMhj.ubj)}(h``tiler_core_mask`` Mask encoding cores that can be used for tiler jobs. This field must have at least **max_tiler_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::tiler_present. h](j)}(h``tiler_core_mask``h]jC)}(hjžh]htiler_core_mask}(hjĞhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h4Mask encoding cores that can be used for tiler jobs.h]h4Mask encoding cores that can be used for tiler jobs.}(hj۞hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj؞ubh)}(h;This field must have at least **max_tiler_cores** bits set.h](hThis field must have at least }(hjhhhNhNubj)}(h**max_tiler_cores**h]hmax_tiler_cores}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh bits set.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj؞ubh)}(hLThe bits set here should also be set in drm_panthor_gpu_info::tiler_present.h]hLThe bits set here should also be set in drm_panthor_gpu_info::tiler_present.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjמhMhj؞ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjמhMhj.ubj)}(hg``vm_id`` VM ID to bind this group to. All submission to queues bound to this group will use this VM. h](j)}(h ``vm_id``h]jC)}(hj+h]hvm_id}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj)ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj%ubj)}(hhh](h)}(hVM ID to bind this group to.h]hVM ID to bind this group to.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjAubh)}(h>All submission to queues bound to this group will use this VM.h]h>All submission to queues bound to this group will use this VM.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhjAubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj.ubj)}(h_``group_handle`` Returned group handle. Passed back when submitting jobs or destroying a group.h](j)}(h``group_handle``h]jC)}(hjsh]h group_handle}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjqubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjmubj)}(hhh]h)}(hNReturned group handle. Passed back when submitting jobs or destroying a group.h]hNReturned group handle. Passed back when submitting jobs or destroying a group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjhMhj.ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW$drm_panthor_group_destroy (C struct)c.drm_panthor_group_destroyhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_group_destroyh]jg)}(h struct drm_panthor_group_destroyh](jm)}(hjph]hstruct}(hj̟hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjȟhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjڟhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjȟhhhjٟhMubj)}(hdrm_panthor_group_destroyh]j)}(hjƟh]hdrm_panthor_group_destroy}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjȟhhhjٟhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjğhhhjٟhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjٟhMhjhhubj)}(hhh]h)}(h3Arguments passed to DRM_IOCTL_PANTHOR_GROUP_DESTROYh]h3Arguments passed to DRM_IOCTL_PANTHOR_GROUP_DESTROY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjٟhMubeh}(h]h ](jstructeh"]h$]h&]jjjj&jj&jjjuh1j[hhhjghNhNubj)}(h**Definition**:: struct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; }; **Members** ``group_handle`` Group to destroy ``pad`` Padding field, MBZ.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh:}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj*ubj)}(hLstruct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; };h]hLstruct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; };}hjKsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj*ubh)}(h **Members**h]j)}(hj\h]hMembers}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj*ubj)}(hhh](j)}(h"``group_handle`` Group to destroy h](j)}(h``group_handle``h]jC)}(hj{h]h group_handle}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjyubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjuubj)}(hhh]h)}(hGroup to destroyh]hGroup to destroy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjhMhjrubj)}(h``pad`` Padding field, MBZ.h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hj͠hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjʠubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjɠhMhjrubeh}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_panthor_queue_submit (C struct)c.drm_panthor_queue_submithNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_queue_submith]jg)}(hstruct drm_panthor_queue_submith](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj hhhjhMubj)}(hdrm_panthor_queue_submith]j)}(hjh]hdrm_panthor_queue_submit}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(hJob submission arguments.h]hJob submission arguments.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjMhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjhjjhjjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; }; **Members** ``queue_index`` Index of the queue inside a group. ``stream_size`` Size of the command stream to execute. Must be 64-bit/8-byte aligned (the size of a CS instruction) Can be zero if stream_addr is zero too. When the stream size is zero, the queue submit serves as a synchronization point. ``stream_addr`` GPU address of the command stream to execute. Must be aligned on 64-byte. Can be zero is stream_size is zero too. ``latest_flush`` FLUSH_ID read at the time the stream was built. This allows cache flush elimination for the automatic flush+invalidate(all) done at submission time, which is needed to ensure the GPU doesn't get garbage when reading the indirect command stream buffers. If you want the cache flush to happen unconditionally, pass a zero here. Ignored when stream_size is zero. ``pad`` MBZ. ``syncs`` Array of struct drm_panthor_sync_op sync operations.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubh:}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjlubj)}(hstruct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; };h]hstruct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjlubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjlubj)}(hhh](j)}(h3``queue_index`` Index of the queue inside a group. h](j)}(h``queue_index``h]jC)}(hjh]h queue_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h"Index of the queue inside a group.h]h"Index of the queue inside a group.}(hj֡hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjҡhMhjӡubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjҡhMhjubj)}(h``stream_size`` Size of the command stream to execute. Must be 64-bit/8-byte aligned (the size of a CS instruction) Can be zero if stream_addr is zero too. When the stream size is zero, the queue submit serves as a synchronization point. h](j)}(h``stream_size``h]jC)}(hjh]h stream_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h&Size of the command stream to execute.h]h&Size of the command stream to execute.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj ubh)}(h``syncs`` Array of struct drm_panthor_sync_op sync operations.h](j)}(h ``syncs``h]jC)}(hjDh]hsyncs}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjBubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj>ubj)}(hhh]h)}(h4Array of struct drm_panthor_sync_op sync operations.h]h4Array of struct drm_panthor_sync_op sync operations.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhMhjubeh}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubh)}(hThis is describing the userspace command stream to call from the kernel command stream ring-buffer. Queue submission is always part of a group submission, taking one or more jobs to submit to the underlying queues.h]hThis is describing the userspace command stream to call from the kernel command stream ring-buffer. Queue submission is always part of a group submission, taking one or more jobs to submit to the underlying queues.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_panthor_group_submit (C struct)c.drm_panthor_group_submithNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_group_submith]jg)}(hstruct drm_panthor_group_submith](jm)}(hjph]hstruct}(hjţhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjӣhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjңhMubj)}(hdrm_panthor_group_submith]j)}(hjh]hdrm_panthor_group_submit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjңhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjңhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjңhMhjhhubj)}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_SUBMITh]h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_SUBMIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjңhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX.**Definition**:: struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; }; **Members** ``group_handle`` Handle of the group to queue jobs to. ``pad`` MBZ. ``queue_submits`` Array of drm_panthor_queue_submit objects.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubh:}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj#ubj)}(h{struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; };h]h{struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; };}hjDsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj#ubh)}(h **Members**h]j)}(hjUh]hMembers}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj#ubj)}(hhh](j)}(h7``group_handle`` Handle of the group to queue jobs to. h](j)}(h``group_handle``h]jC)}(hjth]h group_handle}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjrubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjnubj)}(hhh]h)}(h%Handle of the group to queue jobs to.h]h%Handle of the group to queue jobs to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjhMhjkubj)}(h ``pad`` MBZ. h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjƤhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj¤hMhjäubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj¤hMhjkubj)}(h<``queue_submits`` Array of drm_panthor_queue_submit objects.h](j)}(h``queue_submits``h]jC)}(hjh]h queue_submits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h*Array of drm_panthor_queue_submit objects.h]h*Array of drm_panthor_queue_submit objects.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjkubeh}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW&drm_panthor_group_state_flags (C enum)c.drm_panthor_group_state_flagshNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_group_state_flagsh]jg)}(h"enum drm_panthor_group_state_flagsh](jm)}(hjh]henum}(hj@hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj<hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj<hhhjMhMubj)}(hdrm_panthor_group_state_flagsh]j)}(hj:h]hdrm_panthor_group_state_flags}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj<hhhjMhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj8hhhjMhMubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1j`hjMhMhj5hhubj)}(hhh]h)}(hGroup state flagsh]hGroup state flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj5hhhjMhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX**Constants** ``DRM_PANTHOR_GROUP_STATE_TIMEDOUT`` Group had unfinished jobs. When a group ends up with this flag set, no jobs can be submitted to its queues. ``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT`` Group had fatal faults. When a group ends up with this flag set, no jobs can be submitted to its queues. ``DRM_PANTHOR_GROUP_STATE_INNOCENT`` Group was killed during a reset caused by other groups. This flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](j)}(h``DRM_PANTHOR_GROUP_STATE_TIMEDOUT`` Group had unfinished jobs. When a group ends up with this flag set, no jobs can be submitted to its queues. h](j)}(h$``DRM_PANTHOR_GROUP_STATE_TIMEDOUT``h]jC)}(hjåh]h DRM_PANTHOR_GROUP_STATE_TIMEDOUT}(hjťhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hjubj)}(hhh](h)}(hGroup had unfinished jobs.h]hGroup had unfinished jobs.}(hjܥhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM hj٥ubh)}(hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.h]hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjإhM hj٥ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjإhM hjubj)}(h``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT`` Group had fatal faults. When a group ends up with this flag set, no jobs can be submitted to its queues. h](j)}(h'``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT``h]jC)}(hj h]h#DRM_PANTHOR_GROUP_STATE_FATAL_FAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(hGroup had fatal faults.h]hGroup had fatal faults.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj!ubh)}(hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.h]hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj!ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(h``DRM_PANTHOR_GROUP_STATE_INNOCENT`` Group was killed during a reset caused by other groups. This flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h](j)}(h$``DRM_PANTHOR_GROUP_STATE_INNOCENT``h]jC)}(hjSh]h DRM_PANTHOR_GROUP_STATE_INNOCENT}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjMubj)}(hhh](h)}(h7Group was killed during a reset caused by other groups.h]h7Group was killed during a reset caused by other groups.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjiubh)}(htThis flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h]htThis flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMhjiubeh}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW&drm_panthor_group_get_state (C struct)c.drm_panthor_group_get_statehNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_group_get_stateh]jg)}(h"struct drm_panthor_group_get_stateh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjɦhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjȦhMubj)}(hdrm_panthor_group_get_stateh]j)}(hjh]hdrm_panthor_group_get_state}(hjۦhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjצubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjȦhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjȦhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjȦhMhjhhubj)}(hhh]h)}(h5Arguments passed to DRM_IOCTL_PANTHOR_GROUP_GET_STATEh]h5Arguments passed to DRM_IOCTL_PANTHOR_GROUP_GET_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjȦhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; }; **Members** ``group_handle`` Handle of the group to query state on ``state`` Combination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state. ``fatal_queues`` Bitmask of queues that faced fatal faults. ``pad`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM"hjubj)}(hwstruct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; };h]hwstruct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; };}hj:sbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM$hjubh)}(h **Members**h]j)}(hjKh]hMembers}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM+hjubj)}(hhh](j)}(h7``group_handle`` Handle of the group to query state on h](j)}(h``group_handle``h]jC)}(hjjh]h group_handle}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjhubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM%hjdubj)}(hhh]h)}(h%Handle of the group to query state onh]h%Handle of the group to query state on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM%hjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjhM%hjaubj)}(hS``state`` Combination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state. h](j)}(h ``state``h]jC)}(hjh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM*hjubj)}(hhh]h)}(hHCombination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state.h]hHCombination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM*hjaubj)}(h<``fatal_queues`` Bitmask of queues that faced fatal faults. h](j)}(h``fatal_queues``h]jC)}(hjݧh]h fatal_queues}(hjߧhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjۧubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM.hjקubj)}(hhh]h)}(h*Bitmask of queues that faced fatal faults.h]h*Bitmask of queues that faced fatal faults.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM.hjubah}(h]h ]h"]h$]h&]uh1jhjקubeh}(h]h ]h"]h$]h&]uh1jhjhM.hjaubj)}(h ``pad`` MBZh](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM0hjubj)}(hhh]h)}(hMBZh]hMBZ}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM1hj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj+hM0hjaubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hjYh]h Description}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM4hjghhubh)}(hbUsed to query the state of a group and decide whether a new group should be created to replace it.h]hbUsed to query the state of a group and decide whether a new group should be created to replace it.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW(drm_panthor_tiler_heap_create (C struct)c.drm_panthor_tiler_heap_createhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_tiler_heap_createh]jg)}(h$struct drm_panthor_tiler_heap_createh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM%ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhM%ubj)}(hdrm_panthor_tiler_heap_createh]j)}(hjh]hdrm_panthor_tiler_heap_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM%ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhM%ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhM%hjhhubj)}(hhh]h)}(h7Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_CREATEh]h7Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE}(hj٨hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM5hj֨hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM%ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hXp**Definition**:: struct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; }; **Members** ``vm_id`` VM ID the tiler heap should be mapped to ``initial_chunk_count`` Initial number of chunks to allocate. Must be at least one. ``chunk_size`` Chunk size. Must be page-aligned and lie in the [128k:8M] range. ``max_chunks`` Maximum number of chunks that can be allocated. Must be at least **initial_chunk_count**. ``target_in_flight`` Maximum number of in-flight render passes. If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs. ``handle`` Returned heap handle. Passed back to DESTROY_TILER_HEAP. ``tiler_heap_ctx_gpu_va`` Returned heap GPU virtual address returned ``first_heap_chunk_gpu_va`` First heap chunk. The tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM9hjubj)}(hstruct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; };h]hstruct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM;hjubh)}(h **Members**h]j)}(hj'h]hMembers}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMFhjubj)}(hhh](j)}(h3``vm_id`` VM ID the tiler heap should be mapped to h](j)}(h ``vm_id``h]jC)}(hjFh]hvm_id}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjDubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM9hj@ubj)}(hhh]h)}(h(VM ID the tiler heap should be mapped toh]h(VM ID the tiler heap should be mapped to}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hM9hj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj[hM9hj=ubj)}(hT``initial_chunk_count`` Initial number of chunks to allocate. Must be at least one. h](j)}(h``initial_chunk_count``h]jC)}(hjh]hinitial_chunk_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM<hjyubj)}(hhh]h)}(h;Initial number of chunks to allocate. Must be at least one.h]h;Initial number of chunks to allocate. Must be at least one.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM<hjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jhjhM<hj=ubj)}(hQ``chunk_size`` Chunk size. Must be page-aligned and lie in the [128k:8M] range. h](j)}(h``chunk_size``h]jC)}(hjh]h chunk_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMBhjubj)}(hhh](h)}(h Chunk size.h]h Chunk size.}(hjѩhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM@hjΩubh)}(h4Must be page-aligned and lie in the [128k:8M] range.h]h4Must be page-aligned and lie in the [128k:8M] range.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjͩhMBhjΩubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjͩhMBhj=ubj)}(hj``max_chunks`` Maximum number of chunks that can be allocated. Must be at least **initial_chunk_count**. h](j)}(h``max_chunks``h]jC)}(hjh]h max_chunks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMIhjubj)}(hhh](h)}(h/Maximum number of chunks that can be allocated.h]h/Maximum number of chunks that can be allocated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMGhjubh)}(h)Must be at least **initial_chunk_count**.h](hMust be at least }(hj(hhhNhNubj)}(h**initial_chunk_count**h]hinitial_chunk_count}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubh.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMIhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMIhj=ubj)}(h``target_in_flight`` Maximum number of in-flight render passes. If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs. h](j)}(h``target_in_flight``h]jC)}(hjZh]htarget_in_flight}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjXubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMQhjTubj)}(hhh](h)}(h*Maximum number of in-flight render passes.h]h*Maximum number of in-flight render passes.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMNhjpubh)}(h{If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs.h]h{If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMPhjpubeh}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jhjohMQhj=ubj)}(hD``handle`` Returned heap handle. Passed back to DESTROY_TILER_HEAP. h](j)}(h ``handle``h]jC)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMUhjubj)}(hhh]h)}(h8Returned heap handle. Passed back to DESTROY_TILER_HEAP.h]h8Returned heap handle. Passed back to DESTROY_TILER_HEAP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMUhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMUhj=ubj)}(hE``tiler_heap_ctx_gpu_va`` Returned heap GPU virtual address returned h](j)}(h``tiler_heap_ctx_gpu_va``h]jC)}(hjܪh]htiler_heap_ctx_gpu_va}(hjުhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjڪubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMXhj֪ubj)}(hhh]h)}(h*Returned heap GPU virtual address returnedh]h*Returned heap GPU virtual address returned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMXhjubah}(h]h ]h"]h$]h&]uh1jhj֪ubeh}(h]h ]h"]h$]h&]uh1jhjhMXhj=ubj)}(h``first_heap_chunk_gpu_va`` First heap chunk. The tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h](j)}(h``first_heap_chunk_gpu_va``h]jC)}(hjh]hfirst_heap_chunk_gpu_va}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM^hjubj)}(hhh](h)}(hFirst heap chunk.h]hFirst heap chunk.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM\hj+ubh)}(hjThe tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h]hjThe tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM^hj+ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hM^hj=ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW)drm_panthor_tiler_heap_destroy (C struct) c.drm_panthor_tiler_heap_destroyhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_tiler_heap_destroyh]jg)}(h%struct drm_panthor_tiler_heap_destroyh](jm)}(hjph]hstruct}(hj}hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjyhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMeubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjyhhhjhMeubj)}(hdrm_panthor_tiler_heap_destroyh]j)}(hjwh]hdrm_panthor_tiler_heap_destroy}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjyhhhjhMeubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjuhhhjhMeubah}(h]jpah ](jjeh"]h$]h&]jj)jhuh1j`hjhMehjrhhubj)}(hhh]h)}(h8Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROYh]h8Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMdhjhhubah}(h]h ]h"]h$]h&]uh1jhjrhhhjhMeubeh}(h]h ](jstructeh"]h$]h&]jjjj׫jj׫jjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; }; **Members** ``handle`` Handle of the tiler heap to destroy. Must be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE. ``pad`` Padding field, MBZ.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj߫ubh:}(hj߫hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhhj۫ubj)}(hKstruct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; };h]hKstruct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMjhj۫ubh)}(h **Members**h]j)}(hj h]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMohj۫ubj)}(hhh](j)}(h~``handle`` Handle of the tiler heap to destroy. Must be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE. h](j)}(h ``handle``h]jC)}(hj,h]hhandle}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj*ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMkhj&ubj)}(hhh](h)}(h$Handle of the tiler heap to destroy.h]h$Handle of the tiler heap to destroy.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMihjBubh)}(hLMust be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE.h]hLMust be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhMkhjBubeh}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhjAhMkhj#ubj)}(h``pad`` Padding field, MBZ.h](j)}(h``pad``h]jC)}(hjth]hpad}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjrubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMnhjnubj)}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMohjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjhMnhj#ubeh}(h]h ]h"]h$]h&]uh1jhj۫ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_panthor_bo_set_label (C struct)c.drm_panthor_bo_set_labelhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_set_labelh]jg)}(hstruct drm_panthor_bo_set_labelh](jm)}(hjph]hstruct}(hjάhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjʬhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMuubj)}(h h]h }(hjܬhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjʬhhhj۬hMuubj)}(hdrm_panthor_bo_set_labelh]j)}(hjȬh]hdrm_panthor_bo_set_label}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjʬhhhj۬hMuubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjƬhhhj۬hMuubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hj۬hMuhjìhhubj)}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_BO_SET_LABELh]h2Arguments passed to DRM_IOCTL_PANTHOR_BO_SET_LABEL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMshj hhubah}(h]h ]h"]h$]h&]uh1jhjìhhhj۬hMuubeh}(h]h ](jstructeh"]h$]h&]jjjj(jj(jjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; }; **Members** ``handle`` Handle of the buffer object to label. ``pad`` MBZ. ``label`` User pointer to a NUL-terminated string Length cannot be greater than 4096h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMwhj,ubj)}(hVstruct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; };h]hVstruct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; };}hjMsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMyhj,ubh)}(h **Members**h]j)}(hj^h]hMembers}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj,ubj)}(hhh](j)}(h1``handle`` Handle of the buffer object to label. h](j)}(h ``handle``h]jC)}(hj}h]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj{ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMwhjwubj)}(hhh]h)}(h%Handle of the buffer object to label.h]h%Handle of the buffer object to label.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMwhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjhMwhjtubj)}(h ``pad`` MBZ. h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMzhjubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjϭhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj˭hMzhj̭ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj˭hMzhjtubj)}(hU``label`` User pointer to a NUL-terminated string Length cannot be greater than 4096h](j)}(h ``label``h]jC)}(hjh]hlabel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h'User pointer to a NUL-terminated stringh]h'User pointer to a NUL-terminated string}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhM~hjubh)}(h"Length cannot be greater than 4096h]h"Length cannot be greater than 4096}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubeh}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW+drm_panthor_set_user_mmio_offset (C struct)"c.drm_panthor_set_user_mmio_offsethNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(h drm_panthor_set_user_mmio_offseth]jg)}(h'struct drm_panthor_set_user_mmio_offseth](jm)}(hjph]hstruct}(hjXhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjThhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjThhhjehMubj)}(h drm_panthor_set_user_mmio_offseth]j)}(hjRh]h drm_panthor_set_user_mmio_offset}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubah}(h]h ](jjeh"]h$]h&]jjuh1jhjThhhjehMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjPhhhjehMubah}(h]jKah ](jjeh"]h$]h&]jj)jhuh1j`hjehMhjMhhubj)}(hhh]h)}(h:Arguments passed to DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSETh]h:Arguments passed to DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjMhhhjehMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_set_user_mmio_offset { __u64 offset; }; **Members** ``offset`` User MMIO offset to use. Must be either DRM_PANTHOR_USER_MMIO_OFFSET_32BIT or DRM_PANTHOR_USER_MMIO_OFFSET_64BIT. Use DRM_PANTHOR_USER_MMIO_OFFSET (which selects OFFSET_32BIT or OFFSET_64BIT based on the size of an unsigned long) unless you have a very good reason to overrule this decision.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(h>struct drm_panthor_set_user_mmio_offset { __u64 offset; };h]h>struct drm_panthor_set_user_mmio_offset { __u64 offset; };}hj׮sbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]j)}(hX0``offset`` User MMIO offset to use. Must be either DRM_PANTHOR_USER_MMIO_OFFSET_32BIT or DRM_PANTHOR_USER_MMIO_OFFSET_64BIT. Use DRM_PANTHOR_USER_MMIO_OFFSET (which selects OFFSET_32BIT or OFFSET_64BIT based on the size of an unsigned long) unless you have a very good reason to overrule this decision.h](j)}(h ``offset``h]jC)}(hjh]hoffset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(hUser MMIO offset to use.h]hUser MMIO offset to use.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hXMust be either DRM_PANTHOR_USER_MMIO_OFFSET_32BIT or DRM_PANTHOR_USER_MMIO_OFFSET_64BIT.h]hXMust be either DRM_PANTHOR_USER_MMIO_OFFSET_32BIT or DRM_PANTHOR_USER_MMIO_OFFSET_64BIT.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hUse DRM_PANTHOR_USER_MMIO_OFFSET (which selects OFFSET_32BIT or OFFSET_64BIT based on the size of an unsigned long) unless you have a very good reason to overrule this decision.h]hUse DRM_PANTHOR_USER_MMIO_OFFSET (which selects OFFSET_32BIT or OFFSET_64BIT based on the size of an unsigned long) unless you have a very good reason to overrule this decision.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hjhh]h Description}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubh)}(hThis ioctl is only really useful if you want to support userspace CPU emulation environments where the size of an unsigned long differs between the host and the guest architectures.h]hThis ioctl is only really useful if you want to support userspace CPU emulation environments where the size of an unsigned long differs between the host and the guest architectures.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW$drm_panthor_bo_sync_op_type (C enum)c.drm_panthor_bo_sync_op_typehNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_sync_op_typeh]jg)}(h enum drm_panthor_bo_sync_op_typeh](jm)}(hjh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_panthor_bo_sync_op_typeh]j)}(hjh]hdrm_panthor_bo_sync_op_type}(hjƯhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj¯ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(h BO sync typeh]h BO sync type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(h**Constants** ``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH`` Flush CPU caches. ``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE`` Flush and invalidate CPU caches.h](h)}(h **Constants**h]j)}(hj h]h Constants}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](j)}(h:``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH`` Flush CPU caches. h](j)}(h'``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH``h]jC)}(hj)h]h#DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj#ubj)}(hhh]h)}(hFlush CPU caches.h]hFlush CPU caches.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhj ubj)}(hW``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE`` Flush and invalidate CPU caches.h](j)}(h6``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE``h]jC)}(hjbh]h2DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj\ubj)}(hhh]h)}(h Flush and invalidate CPU caches.h]h Flush and invalidate CPU caches.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jhjwhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW!drm_panthor_bo_sync_op (C struct)c.drm_panthor_bo_sync_ophNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_sync_oph]jg)}(hstruct drm_panthor_bo_sync_oph](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjʰhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjɰhMubj)}(hdrm_panthor_bo_sync_oph]j)}(hjh]hdrm_panthor_bo_sync_op}(hjܰhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjذubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjɰhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjɰhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjɰhMhjhhubj)}(hhh]h)}(hBO map sync oph]hBO map sync op}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjɰhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_bo_sync_op { __u32 handle; __u32 type; __u64 offset; __u64 size; }; **Members** ``handle`` Handle of the buffer object to sync. ``type`` Type of operation. ``offset`` Offset into the BO at which the sync range starts. This will be rounded down to the nearest cache line as needed. ``size`` Size of the range to sync **size** + **offset** will be rounded up to the nearest cache line as needed.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hfstruct drm_panthor_bo_sync_op { __u32 handle; __u32 type; __u64 offset; __u64 size; };h]hfstruct drm_panthor_bo_sync_op { __u32 handle; __u32 type; __u64 offset; __u64 size; };}hj;sbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]j)}(hjLh]hMembers}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](j)}(h0``handle`` Handle of the buffer object to sync. h](j)}(h ``handle``h]jC)}(hjkh]hhandle}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjiubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjeubj)}(hhh]h)}(h$Handle of the buffer object to sync.h]h$Handle of the buffer object to sync.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjhMhjbubj)}(h``type`` Type of operation. h](j)}(h``type``h]jC)}(hjh]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hType of operation.h]hType of operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjbubj)}(h~``offset`` Offset into the BO at which the sync range starts. This will be rounded down to the nearest cache line as needed. h](j)}(h ``offset``h]jC)}(hjݱh]hoffset}(hj߱hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj۱ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjױubj)}(hhh](h)}(h2Offset into the BO at which the sync range starts.h]h2Offset into the BO at which the sync range starts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h>This will be rounded down to the nearest cache line as needed.h]h>This will be rounded down to the nearest cache line as needed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjױubeh}(h]h ]h"]h$]h&]uh1jhjhMhjbubj)}(hq``size`` Size of the range to sync **size** + **offset** will be rounded up to the nearest cache line as needed.h](j)}(h``size``h]jC)}(hj%h]hsize}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj#ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(hSize of the range to synch]hSize of the range to sync}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj;ubh)}(hM**size** + **offset** will be rounded up to the nearest cache line as needed.h](j)}(h**size**h]hsize}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubh + }(hjMhhhNhNubj)}(h **offset**h]hoffset}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubh8 will be rounded up to the nearest cache line as needed.}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj:hMhj;ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj:hMhjbubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_panthor_bo_sync (C struct)c.drm_panthor_bo_synchNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_synch]jg)}(hstruct drm_panthor_bo_synch](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_panthor_bo_synch]j)}(hjh]hdrm_panthor_bo_sync}(hjͲhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjɲubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(hBO map sync requesth]hBO map sync request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(h**Definition**:: struct drm_panthor_bo_sync { struct drm_panthor_obj_array ops; }; **Members** ``ops`` Array of struct drm_panthor_bo_sync_op sync operations.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj ubj)}(hEstruct drm_panthor_bo_sync { struct drm_panthor_obj_array ops; };h]hEstruct drm_panthor_bo_sync { struct drm_panthor_obj_array ops; };}hj,sbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj ubh)}(h **Members**h]j)}(hj=h]hMembers}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj ubj)}(hhh]j)}(h?``ops`` Array of struct drm_panthor_bo_sync_op sync operations.h](j)}(h``ops``h]jC)}(hj\h]hops}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjZubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjVubj)}(hhh]h)}(h7Array of struct drm_panthor_bo_sync_op sync operations.h]h7Array of struct drm_panthor_bo_sync_op sync operations.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjqhMhjSubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_panthor_bo_extra_flags (C enum)c.drm_panthor_bo_extra_flagshNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_extra_flagsh]jg)}(henum drm_panthor_bo_extra_flagsh](jm)}(hjh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjijhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjóhMubj)}(hdrm_panthor_bo_extra_flagsh]j)}(hjh]hdrm_panthor_bo_extra_flags}(hjֳhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҳubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjóhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjóhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjóhMhjhhubj)}(hhh]h)}(h0Set of flags returned on a BO_QUERY_INFO requesth]h0Set of flags returned on a BO_QUERY_INFO request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjóhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhjghNhNubj)}(hX**Constants** ``DRM_PANTHOR_BO_IS_IMPORTED`` BO has been imported from an external driver. Note that imported dma-buf handles are not flagged as imported if they where exported by panthor. Only buffers that are coming from other drivers (dma heaps, other GPUs, display controllers, V4L, ...). It's also important to note that all imported BOs are mapped cached and can't be considered IO-coherent even if the GPU is. This means they require explicit syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache maintenance is not allowed in that case, because extra operations might be needed to make changes visible to the CPU/device, like buffer migration when the exporter is a GPU with its own VRAM).h](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]j)}(hX``DRM_PANTHOR_BO_IS_IMPORTED`` BO has been imported from an external driver. Note that imported dma-buf handles are not flagged as imported if they where exported by panthor. Only buffers that are coming from other drivers (dma heaps, other GPUs, display controllers, V4L, ...). It's also important to note that all imported BOs are mapped cached and can't be considered IO-coherent even if the GPU is. This means they require explicit syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache maintenance is not allowed in that case, because extra operations might be needed to make changes visible to the CPU/device, like buffer migration when the exporter is a GPU with its own VRAM).h](j)}(h``DRM_PANTHOR_BO_IS_IMPORTED``h]jC)}(hj9h]hDRM_PANTHOR_BO_IS_IMPORTED}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj7ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj3ubj)}(hhh](h)}(h-BO has been imported from an external driver.h]h-BO has been imported from an external driver.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjOubh)}(hNote that imported dma-buf handles are not flagged as imported if they where exported by panthor. Only buffers that are coming from other drivers (dma heaps, other GPUs, display controllers, V4L, ...).h]hNote that imported dma-buf handles are not flagged as imported if they where exported by panthor. Only buffers that are coming from other drivers (dma heaps, other GPUs, display controllers, V4L, ...).}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjOubh)}(hXIt's also important to note that all imported BOs are mapped cached and can't be considered IO-coherent even if the GPU is. This means they require explicit syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache maintenance is not allowed in that case, because extra operations might be needed to make changes visible to the CPU/device, like buffer migration when the exporter is a GPU with its own VRAM).h]hXIt’s also important to note that all imported BOs are mapped cached and can’t be considered IO-coherent even if the GPU is. This means they require explicit syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache maintenance is not allowed in that case, because extra operations might be needed to make changes visible to the CPU/device, like buffer migration when the exporter is a GPU with its own VRAM).}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjOubeh}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhMhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubh)}(hThose are flags reflecting BO properties that are not directly coming from the flags passed are creation time, or information on BOs that were imported from other drivers.h]hThose are flags reflecting BO properties that are not directly coming from the flags passed are creation time, or information on BOs that were imported from other drivers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW$drm_panthor_bo_query_info (C struct)c.drm_panthor_bo_query_infohNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hdrm_panthor_bo_query_infoh]jg)}(h struct drm_panthor_bo_query_infoh](jm)}(hjph]hstruct}(hjشhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjԴhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjԴhhhjhMubj)}(hdrm_panthor_bo_query_infoh]j)}(hjҴh]hdrm_panthor_bo_query_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjԴhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjдhhhjhMubah}(h]j˴ah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjʹhhubj)}(hhh]h)}(h Query BO infoh]h Query BO info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjʹhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj2jj2jjjuh1j[hhhjghNhNubj)}(hX**Definition**:: struct drm_panthor_bo_query_info { __u32 handle; __u32 extra_flags; __u32 create_flags; __u32 pad; }; **Members** ``handle`` Handle of the buffer object to query flags on. ``extra_flags`` Combination of enum drm_panthor_bo_extra_flags flags. ``create_flags`` Flags passed at creation time. Combination of enum drm_panthor_bo_flags flags. Will be zero if the buffer comes from a different driver. ``pad`` Will be zero on return.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubh:}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj6ubj)}(hustruct drm_panthor_bo_query_info { __u32 handle; __u32 extra_flags; __u32 create_flags; __u32 pad; };h]hustruct drm_panthor_bo_query_info { __u32 handle; __u32 extra_flags; __u32 create_flags; __u32 pad; };}hjWsbah}(h]h ]h"]h$]h&]jjuh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj6ubh)}(h **Members**h]j)}(hjhh]hMembers}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj6ubj)}(hhh](j)}(h:``handle`` Handle of the buffer object to query flags on. h](j)}(h ``handle``h]jC)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h.Handle of the buffer object to query flags on.h]h.Handle of the buffer object to query flags on.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj~ubj)}(hF``extra_flags`` Combination of enum drm_panthor_bo_extra_flags flags. h](j)}(h``extra_flags``h]jC)}(hjh]h extra_flags}(hjµhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h5Combination of enum drm_panthor_bo_extra_flags flags.h]h5Combination of enum drm_panthor_bo_extra_flags flags.}(hjٵhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjյhMhjֵubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjյhMhj~ubj)}(h``create_flags`` Flags passed at creation time. Combination of enum drm_panthor_bo_flags flags. Will be zero if the buffer comes from a different driver. h](j)}(h``create_flags``h]jC)}(hjh]h create_flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(hFlags passed at creation time.h]hFlags passed at creation time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hiCombination of enum drm_panthor_bo_flags flags. Will be zero if the buffer comes from a different driver.h]hiCombination of enum drm_panthor_bo_flags flags. Will be zero if the buffer comes from a different driver.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj~ubj)}(h``pad`` Will be zero on return.h](j)}(h``pad``h]jC)}(hjBh]hpad}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj<ubj)}(hhh]h)}(hWill be zero on return.h]hWill be zero on return.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhMhj~ubeh}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWDRM_IOCTL_PANTHOR (C macro)c.DRM_IOCTL_PANTHORhNtauh1jJhjghhhNhNubj\)}(hhh](ja)}(hDRM_IOCTL_PANTHORh]jg)}(hDRM_IOCTL_PANTHORh]j)}(hDRM_IOCTL_PANTHORh]j)}(hjh]hDRM_IOCTL_PANTHOR}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMubah}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jmacroeh"]h$]h&]jjjj̶jj̶jjjuh1j[hhhjghNhNubh)}(h.``DRM_IOCTL_PANTHOR (__access, __id, __type)``h]jC)}(hjҶh]h*DRM_IOCTL_PANTHOR (__access, __id, __type)}(hjԶhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjжubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjghhubjK)}(hBuild a Panthor IOCTL number h]h)}(hBuild a Panthor IOCTL numberh]hBuild a Panthor IOCTL number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jJhjhMhjghhubj)}(hXJ**Parameters** ``__access`` Access type. Must be R, W or RW. ``__id`` One of the DRM_PANTHOR_xxx id. ``__type`` Suffix of the type being passed to the IOCTL. **Description** Don't use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead. **Return** An IOCTL number to be passed to ioctl() from userspace.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](j)}(h.``__access`` Access type. Must be R, W or RW. h](j)}(h ``__access``h]jC)}(hj&h]h__access}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhj ubj)}(hhh]h)}(h Access type. Must be R, W or RW.h]h Access type. Must be R, W or RW.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhjubj)}(h(``__id`` One of the DRM_PANTHOR_xxx id. h](j)}(h``__id``h]jC)}(hj_h]h__id}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjYubj)}(hhh]h)}(hOne of the DRM_PANTHOR_xxx id.h]hOne of the DRM_PANTHOR_xxx id.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMhjuubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jhjthMhjubj)}(h9``__type`` Suffix of the type being passed to the IOCTL. h](j)}(h ``__type``h]jC)}(hjh]h__type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h-Suffix of the type being passed to the IOCTL.h]h-Suffix of the type being passed to the IOCTL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjӷh]h Description}(hjշhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjѷubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hLDon't use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead.h]hNDon’t use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h7An IOCTL number to be passed to ioctl() from userspace.h]h7An IOCTL number to be passed to ioctl() from userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:26: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjghhhNhNubeh}(h]jah ]h"]drm/panthor uapiah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h drm/xe uAPIh]h drm/xe uAPI}(hj0hhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj-hhhhhKubj{)}(h.. _Xe Device Block Diagram:h]h}(h]h ]h"]h$]h&]hʌxe-device-block-diagramuh1jzhKhj-hhhNubh)}(h**Xe Device Block Diagram**h]j)}(hjKh]hXe Device Block Diagram}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]jHah ]h"]xe device block diagramah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhj}j^j>sj}jHj>subh)}(hXThe diagram below represents a high-level simplification of a discrete GPU supported by the Xe driver. It shows some device components which are necessary to understand this API, as well as how their relations to each other. This diagram does not represent real hardware::h]hXThe diagram below represents a high-level simplification of a discrete GPU supported by the Xe driver. It shows some device components which are necessary to understand this API, as well as how their relations to each other. This diagram does not represent real hardware:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubj)}(hX┌──────────────────────────────────────────────────────────────────┐ │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ └─────────────────────────────Device0───────┬──────────────────────┘ │ ───────────────────────┴────────── PCI bus h]hX┌──────────────────────────────────────────────────────────────────┐ │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ └─────────────────────────────Device0───────┬──────────────────────┘ │ ───────────────────────┴────────── PCI bus}hjssbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubj{)}(h.. _Xe uAPI Overview:h]h}(h]h ]h"]h$]h&]hʌxe-uapi-overviewuh1jzhK)hj-hhhNubh)}(h**Xe uAPI Overview**h]j)}(hjh]hXe uAPI Overview}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"]xe uapi overviewah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhK@hj-hhj}jjsj}jjsubh)}(hThis section aims to describe the Xe's IOCTL entries, its structs, and other Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related entries and usage.h]hThis section aims to describe the Xe’s IOCTL entries, its structs, and other Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related entries and usage.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKAhj-hhubj)}(hhh]j)}(hXList of supported IOCTLs: - :c:type:`DRM_IOCTL_XE_DEVICE_QUERY` - :c:type:`DRM_IOCTL_XE_GEM_CREATE` - :c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET` - :c:type:`DRM_IOCTL_XE_VM_CREATE` - :c:type:`DRM_IOCTL_XE_VM_DESTROY` - :c:type:`DRM_IOCTL_XE_VM_BIND` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY` - :c:type:`DRM_IOCTL_XE_EXEC` - :c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE` - :c:type:`DRM_IOCTL_XE_OBSERVATION` - :c:type:`DRM_IOCTL_XE_MADVISE` - :c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY` - :c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY` h](j)}(hList of supported IOCTLs:h]hList of supported IOCTLs:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKVhjubj)}(hhh]h)}(hhh](h)}(h#:c:type:`DRM_IOCTL_XE_DEVICE_QUERY`h]h)}(hjոh]h)}(hjոh]jC)}(hjոh]hDRM_IOCTL_XE_DEVICE_QUERY}(hjݸhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjڸubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_DEVICE_QUERYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKFhj׸ubah}(h]h ]h"]h$]h&]uh1hhjhKFhjӸubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]h)}(hjh]h)}(hjh]jC)}(hjh]hDRM_IOCTL_XE_GEM_CREATE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_GEM_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKGhj ubah}(h]h ]h"]h$]h&]uh1hhj*hKGhjubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h&:c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET`h]h)}(hj9h]h)}(hj9h]jC)}(hj9h]hDRM_IOCTL_XE_GEM_MMAP_OFFSET}(hjAhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj>ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_GEM_MMAP_OFFSETuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKHhj;ubah}(h]h ]h"]h$]h&]uh1hhj\hKHhj7ubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h :c:type:`DRM_IOCTL_XE_VM_CREATE`h]h)}(hjkh]h)}(hjkh]jC)}(hjkh]hDRM_IOCTL_XE_VM_CREATE}(hjshhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjpubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_VM_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKIhjmubah}(h]h ]h"]h$]h&]uh1hhjhKIhjiubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h!:c:type:`DRM_IOCTL_XE_VM_DESTROY`h]h)}(hjh]h)}(hjh]jC)}(hjh]hDRM_IOCTL_XE_VM_DESTROY}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_VM_DESTROYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKJhjubah}(h]h ]h"]h$]h&]uh1hhjhKJhjubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]h)}(hjϹh]h)}(hjϹh]jC)}(hjϹh]hDRM_IOCTL_XE_VM_BIND}(hj׹hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjԹubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_VM_BINDuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKKhjѹubah}(h]h ]h"]h$]h&]uh1hhjhKKhj͹ubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h(:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h]h)}(hjh]h)}(hjh]jC)}(hjh]hDRM_IOCTL_XE_EXEC_QUEUE_CREATE}(hj hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_EXEC_QUEUE_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKLhjubah}(h]h ]h"]h$]h&]uh1hhj$hKLhjubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h):c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY`h]h)}(hj3h]h)}(hj3h]jC)}(hj3h]hDRM_IOCTL_XE_EXEC_QUEUE_DESTROY}(hj;hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj8ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_EXEC_QUEUE_DESTROYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKMhj5ubah}(h]h ]h"]h$]h&]uh1hhjVhKMhj1ubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h.:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY`h]h)}(hjeh]h)}(hjeh]jC)}(hjeh]h$DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY}(hjmhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj$DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKNhjgubah}(h]h ]h"]h$]h&]uh1hhjhKNhjcubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h:c:type:`DRM_IOCTL_XE_EXEC`h]h)}(hjh]h)}(hjh]jC)}(hjh]hDRM_IOCTL_XE_EXEC}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_EXECuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKOhjubah}(h]h ]h"]h$]h&]uh1hhjhKOhjubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h&:c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE`h]h)}(hjɺh]h)}(hjɺh]jC)}(hjɺh]hDRM_IOCTL_XE_WAIT_USER_FENCE}(hjѺhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjκubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_WAIT_USER_FENCEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKPhj˺ubah}(h]h ]h"]h$]h&]uh1hhjhKPhjǺubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h":c:type:`DRM_IOCTL_XE_OBSERVATION`h]h)}(hjh]h)}(hjh]jC)}(hjh]hDRM_IOCTL_XE_OBSERVATION}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_OBSERVATIONuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKQhjubah}(h]h ]h"]h$]h&]uh1hhjhKQhjubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h:c:type:`DRM_IOCTL_XE_MADVISE`h]h)}(hj-h]h)}(hj-h]jC)}(hj-h]hDRM_IOCTL_XE_MADVISE}(hj5hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj2ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_MADVISEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKRhj/ubah}(h]h ]h"]h$]h&]uh1hhjPhKRhj+ubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h/:c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS`h]h)}(hj_h]h)}(hj_h]jC)}(hj_h]h%DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS}(hjghhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjdubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj%DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRSuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKShjaubah}(h]h ]h"]h$]h&]uh1hhjhKShj]ubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h.:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY`h]h)}(hjh]h)}(hjh]jC)}(hjh]h$DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj$DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKThjubah}(h]h ]h"]h$]h&]uh1hhjhKThjubah}(h]h ]h"]h$]h&]uh1hhjиubh)}(h(:c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY` h]h)}(h&:c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY`h]h)}(hjǻh]jC)}(hjǻh]hDRM_IOCTL_XE_VM_GET_PROPERTY}(hj̻hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjɻubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_VM_GET_PROPERTYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKUhjŻubah}(h]h ]h"]h$]h&]uh1hhjhKUhjubah}(h]h ]h"]h$]h&]uh1hhjиubeh}(h]h ]h"]h$]h&]j j uh1hhjhKFhj͸ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj̸hKVhjubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubj{)}(h.. _Xe IOCTL Extensions:h]h}(h]h ]h"]h$]h&]hʌxe-ioctl-extensionsuh1jzhKDhj-hhhNubh)}(h**Xe IOCTL Extensions**h]j)}(hjh]hXe IOCTL Extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]jah ]h"]xe ioctl extensionsah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKZhj-hhj}j,j sj}jj subh)}(hoBefore detailing the IOCTLs and its structs, it is important to highlight that every IOCTL in Xe is extensible.h]hoBefore detailing the IOCTLs and its structs, it is important to highlight that every IOCTL in Xe is extensible.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubh)}(hX5Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan's approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.h]hX7Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan’s approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubh)}(hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.h]hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubh)}(hExample chaining:h]hExample chaining:}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubj)}(hX/struct drm_xe_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct drm_xe_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct drm_xe_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };h]hX/struct drm_xe_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct drm_xe_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct drm_xe_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };}hjnsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubh)}(hTypically the struct drm_xe_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.h]hTypically the struct drm_xe_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_xe_user_extension (C struct)c.drm_xe_user_extensionhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_user_extensionh]jg)}(hstruct drm_xe_user_extensionh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhKubj)}(hdrm_xe_user_extensionh]j)}(hjh]hdrm_xe_user_extension}(hjƼhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj¼ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhKhjhhubj)}(hhh]h)}(h-Base class for defining a chain of extensionsh]h-Base class for defining a chain of extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX3**Definition**:: struct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; }; **Members** ``next_extension`` Pointer to the next struct drm_xe_user_extension, or zero if the end. ``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension. ``pad`` MBZ All undefined bits must be zero.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hZstruct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; };h]hZstruct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; };}hj%sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubh)}(h **Members**h]j)}(hj6h]hMembers}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh](j)}(hY``next_extension`` Pointer to the next struct drm_xe_user_extension, or zero if the end. h](j)}(h``next_extension``h]jC)}(hjUh]hnext_extension}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjSubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjOubj)}(hhh]h)}(hEPointer to the next struct drm_xe_user_extension, or zero if the end.h]hEPointer to the next struct drm_xe_user_extension, or zero if the end.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhKhjkubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhjjhKhjLubj)}(hX``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension. h](j)}(h``name``h]jC)}(hjh]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh](h)}(hName of the extension.h]hName of the extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubh)}(h-Note that the name here is just some integer.h]h-Note that the name here is just some integer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubh)}(hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension.h]hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension.}(hjŽhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjLubj)}(h-``pad`` MBZ All undefined bits must be zero.h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh](h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubh)}(h All undefined bits must be zero.h]h All undefined bits must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjLubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_xe_ext_set_property (C struct)c.drm_xe_ext_set_propertyhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_ext_set_propertyh]jg)}(hstruct drm_xe_ext_set_propertyh](jm)}(hjph]hstruct}(hjOhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjKhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjKhhhj\hKubj)}(hdrm_xe_ext_set_propertyh]j)}(hjIh]hdrm_xe_ext_set_property}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubah}(h]h ](jjeh"]h$]h&]jjuh1jhjKhhhj\hKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjGhhhj\hKubah}(h]jBah ](jjeh"]h$]h&]jj)jhuh1j`hj\hKhjDhhubj)}(hhh]h)}(hGeneric set property extensionh]hGeneric set property extension}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjDhhhj\hKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; union { __u64 value; __u64 ptr; }; __u64 reserved[2]; }; **Members** ``base`` base user extension ``property`` property to set ``pad`` MBZ ``{unnamed_union}`` anonymous ``value`` property value ``ptr`` pointer to user value ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hstruct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; union { __u64 value; __u64 ptr; }; __u64 reserved[2]; };h]hstruct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; union { __u64 value; __u64 ptr; }; __u64 reserved[2]; };}hjξsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubh)}(h **Members**h]j)}(hj߾h]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjݾubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh](j)}(h``base`` base user extension h](j)}(h``base``h]jC)}(hjh]hbase}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hbase user extensionh]hbase user extension}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``property`` property to set h](j)}(h ``property``h]jC)}(hj7h]hproperty}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj5ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj1ubj)}(hhh]h)}(hproperty to seth]hproperty to set}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhKhjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhKhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjph]hpad}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjnubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]jC)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h anonymoush]h anonymous}(hj¿hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``value`` property value h](j)}(h ``value``h]jC)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjܿubj)}(hhh]h)}(hproperty valueh]hproperty value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjܿubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``ptr`` pointer to user value h](j)}(h``ptr``h]jC)}(hjh]hptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hpointer to user valueh]hpointer to user value}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hKhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj0hKhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjTh]hreserved}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjRubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjNubj)}(hhh]h)}(hReservedh]hReserved}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjihKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubh)}(h`A generic struct that allows any of the Xe's IOCTL to be extended with a set_property operation.h]hbA generic struct that allows any of the Xe’s IOCTL to be extended with a set_property operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW'drm_xe_engine_class_instance (C struct)c.drm_xe_engine_class_instancehNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_engine_class_instanceh]jg)}(h#struct drm_xe_engine_class_instanceh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhKubj)}(hdrm_xe_engine_class_instanceh]j)}(hjh]hdrm_xe_engine_class_instance}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhKhjhhubj)}(hhh]h)}(hinstance of an engine classh]hinstance of an engine class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjj/jj/jjjuh1j[hhhj-hNhNubj)}(hXy**Definition**:: struct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0; #define DRM_XE_ENGINE_CLASS_COPY 1; #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2; #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; }; **Members** ``engine_class`` engine class id ``engine_instance`` engine instance id ``gt_id`` Unique ID of this GT within the PCI Device ``pad`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubh:}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj3ubj)}(hXstruct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0; #define DRM_XE_ENGINE_CLASS_COPY 1; #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2; #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; };h]hXstruct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0; #define DRM_XE_ENGINE_CLASS_COPY 1; #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2; #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; };}hjTsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj3ubh)}(h **Members**h]j)}(hjeh]hMembers}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj3ubj)}(hhh](j)}(h!``engine_class`` engine class id h](j)}(h``engine_class``h]jC)}(hjh]h engine_class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj~ubj)}(hhh]h)}(hengine class idh]hengine class id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhjhKhj{ubj)}(h'``engine_instance`` engine instance id h](j)}(h``engine_instance``h]jC)}(hjh]hengine_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hengine instance idh]hengine instance id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj{ubj)}(h5``gt_id`` Unique ID of this GT within the PCI Device h](j)}(h ``gt_id``h]jC)}(hjh]hgt_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h*Unique ID of this GT within the PCI Deviceh]h*Unique ID of this GT within the PCI Device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhj{ubj)}(h ``pad`` MBZh](j)}(h``pad``h]jC)}(hj/h]hpad}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj)ubj)}(hhh]h)}(hMBZh]hMBZ}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjEubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhjDhMhj{ubeh}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjrh]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hXIt is returned as part of the :c:type:`struct drm_xe_engine `, but it also is used as the input of engine selection for both :c:type:`struct drm_xe_exec_queue_create ` and :c:type:`struct drm_xe_query_engine_cycles `h](hIt is returned as part of the }(hjhhhNhNubh)}(h.:c:type:`struct drm_xe_engine `h]jC)}(hjh]hstruct drm_xe_engine}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_xe_engineuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubh@, but it also is used as the input of engine selection for both }(hjhhhNhNubh)}(hD:c:type:`struct drm_xe_exec_queue_create `h]jC)}(hjh]hstruct drm_xe_exec_queue_create}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_exec_queue_createuh1hhjhKhjubh and }(hjhhhNhNubh)}(hH:c:type:`struct drm_xe_query_engine_cycles `h]jC)}(hjh]h!struct drm_xe_query_engine_cycles}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_query_engine_cyclesuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj-hhubj)}(hhh]j)}(hXiThe **engine_class** can be: - ``DRM_XE_ENGINE_CLASS_RENDER`` - ``DRM_XE_ENGINE_CLASS_COPY`` - ``DRM_XE_ENGINE_CLASS_VIDEO_DECODE`` - ``DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE`` - ``DRM_XE_ENGINE_CLASS_COMPUTE`` - ``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations. h](j)}(hThe **engine_class** can be:h](hThe }(hjhhhNhNubj)}(h**engine_class**h]h engine_class}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hhh](h)}(h``DRM_XE_ENGINE_CLASS_RENDER``h]h)}(hj,h]jC)}(hj,h]hDRM_XE_ENGINE_CLASS_RENDER}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj.ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj*ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h``DRM_XE_ENGINE_CLASS_COPY``h]h)}(hjMh]jC)}(hjMh]hDRM_XE_ENGINE_CLASS_COPY}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjOubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjKubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h$``DRM_XE_ENGINE_CLASS_VIDEO_DECODE``h]h)}(hjnh]jC)}(hjnh]h DRM_XE_ENGINE_CLASS_VIDEO_DECODE}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjpubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjlubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h%``DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE``h]h)}(hjh]jC)}(hjh]h!DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h``DRM_XE_ENGINE_CLASS_COMPUTE``h]h)}(hjh]jC)}(hjh]hDRM_XE_ENGINE_CLASS_COMPUTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations. h]h)}(h``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations.h](jC)}(h``DRM_XE_ENGINE_CLASS_VM_BIND``h]hDRM_XE_ENGINE_CLASS_VM_BIND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhr - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1hhj'ubeh}(h]h ]h"]h$]h&]j j uh1hhjDhKhj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj#hKhjubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_engine (C struct)c.drm_xe_enginehNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(h drm_xe_engineh]jg)}(hstruct drm_xe_engineh](jm)}(hjph]hstruct}(hj'hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj#hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj#hhhj4hKubj)}(h drm_xe_engineh]j)}(hj!h]h drm_xe_engine}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ](jjeh"]h$]h&]jjuh1jhj#hhhj4hKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhj4hKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hj4hKhjhhubj)}(hhh]h)}(hdescribe hardware engineh]hdescribe hardware engine}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjfhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj4hKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; }; **Members** ``instance`` The :c:type:`struct drm_xe_engine_class_instance ` ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjubj)}(hbstruct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; };h]hbstruct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h^``instance`` The :c:type:`struct drm_xe_engine_class_instance ` h](j)}(h ``instance``h]jC)}(hjh]hinstance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjubj)}(hhh]h)}(hPThe :c:type:`struct drm_xe_engine_class_instance `h](hThe }(hjhhhNhNubh)}(hL:c:type:`struct drm_xe_engine_class_instance `h]jC)}(hjh]h#struct drm_xe_engine_class_instance}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_engine_class_instanceuh1hhjhM hjubeh}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hj.h]hreserved}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj(ubj)}(hhh]h)}(hReservedh]hReserved}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjChMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_query_engines (C struct)c.drm_xe_query_engineshNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_enginesh]jg)}(hstruct drm_xe_query_enginesh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_xe_query_enginesh]j)}(hjh]hdrm_xe_query_engines}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]j{ah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhj}hhubj)}(hhh]h)}(hdescribe enginesh]hdescribe engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj}hhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; }; **Members** ``num_engines`` number of engines returned in **engines** ``pad`` MBZ ``engines`` The returned engines for this deviceh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hjstruct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; };h]hjstruct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjubj)}(hhh](j)}(h:``num_engines`` number of engines returned in **engines** h](j)}(h``num_engines``h]jC)}(hj7h]h num_engines}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj5ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj1ubj)}(hhh]h)}(h)number of engines returned in **engines**h](hnumber of engines returned in }(hjPhhhNhNubj)}(h **engines**h]hengines}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1hhjLhMhjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhMhj.ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hj~h]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj|ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjxubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjhMhj.ubj)}(h0``engines`` The returned engines for this deviceh](j)}(h ``engines``h]jC)}(hjh]hengines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h$The returned engines for this deviceh]h$The returned engines for this device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj.ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM#hj-hhubh)}(hIf a query is made with a :c:type:`struct drm_xe_device_query ` where .query is equal to ``DRM_XE_DEVICE_QUERY_ENGINES``, then the reply uses an array of :c:type:`struct drm_xe_query_engines ` in .data.h](hIf a query is made with a }(hjhhhNhNubh)}(h::c:type:`struct drm_xe_device_query `h]jC)}(hjh]hstruct drm_xe_device_query}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_device_queryuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh where .query is equal to }(hjhhhNhNubjC)}(h``DRM_XE_DEVICE_QUERY_ENGINES``h]hDRM_XE_DEVICE_QUERY_ENGINES}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh", then the reply uses an array of }(hjhhhNhNubh)}(h<:c:type:`struct drm_xe_query_engines `h]jC)}(hjPh]hstruct drm_xe_query_engines}(hjRhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjNubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_query_enginesuh1hhj7hMhjubh in .data.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj7hMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_memory_class (C enum)c.drm_xe_memory_classhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_memory_classh]jg)}(henum drm_xe_memory_classh](jm)}(hjh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_xe_memory_classh]j)}(hjh]hdrm_xe_memory_class}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(hSupported memory classes.h]hSupported memory classes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM$hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(h**Constants** ``DRM_XE_MEM_REGION_CLASS_SYSMEM`` Represents system memory. ``DRM_XE_MEM_REGION_CLASS_VRAM`` On discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM(hjubj)}(hhh](j)}(h=``DRM_XE_MEM_REGION_CLASS_SYSMEM`` Represents system memory. h](j)}(h"``DRM_XE_MEM_REGION_CLASS_SYSMEM``h]jC)}(hjh]hDRM_XE_MEM_REGION_CLASS_SYSMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM+hj ubj)}(hhh]h)}(hRepresents system memory.h]hRepresents system memory.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hM+hj)ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj(hM+hj ubj)}(h``DRM_XE_MEM_REGION_CLASS_VRAM`` On discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h](j)}(h ``DRM_XE_MEM_REGION_CLASS_VRAM``h]jC)}(hjLh]hDRM_XE_MEM_REGION_CLASS_VRAM}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjJubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM/hjFubj)}(hhh]h)}(hOn discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h]hOn discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM.hjbubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhjahM/hj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_mem_region (C struct)c.drm_xe_mem_regionhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_mem_regionh]jg)}(hstruct drm_xe_mem_regionh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM5ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhM5ubj)}(hdrm_xe_mem_regionh]j)}(hjh]hdrm_xe_mem_region}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM5ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhM5ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhM5hjhhubj)}(hhh]h)}(h-Describes some region as known to the driver.h]h-Describes some region as known to the driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM2hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM5ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; }; **Members** ``mem_class`` The memory class describing this region. See enum drm_xe_memory_class for supported values. ``instance`` The unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE` ``min_page_size`` Min page-size in bytes for this region. When the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met. ``total_size`` The usable size in bytes for this region. ``used`` Estimate of the memory used in bytes for this region. ``cpu_visible_size`` How much of this region can be CPU accessed, in bytes. This will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system. On systems without small BAR (full BAR), the **cpu_visible_size** will always equal the **total_size**, since all of it will be CPU accessible. Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero). ``cpu_visible_used`` Estimate of CPU visible memory used, in bytes. Note this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero). ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM6hjubj)}(hstruct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; };h]hstruct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; };}hj%sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM8hjubh)}(h **Members**h]j)}(hj6h]hMembers}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMChjubj)}(hhh](j)}(hk``mem_class`` The memory class describing this region. See enum drm_xe_memory_class for supported values. h](j)}(h ``mem_class``h]jC)}(hjUh]h mem_class}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjSubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM:hjOubj)}(hhh](h)}(h(The memory class describing this region.h]h(The memory class describing this region.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM8hjkubh)}(h2See enum drm_xe_memory_class for supported values.h]h2See enum drm_xe_memory_class for supported values.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhM:hjkubeh}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhjjhM:hjLubj)}(h``instance`` The unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE` h](j)}(h ``instance``h]jC)}(hjh]hinstance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM@hjubj)}(hhh]h)}(hThe unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE`h](hgThe unique ID for this region, which serves as the index in the placement bitmask used as argument for }(hjhhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]jC)}(hjh]hDRM_IOCTL_XE_GEM_CREATE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_GEM_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM>hjubeh}(h]h ]h"]h$]h&]uh1hhjhM>hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM@hjLubj)}(hX``min_page_size`` Min page-size in bytes for this region. When the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met. h](j)}(h``min_page_size``h]jC)}(hjh]h min_page_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMNhjubj)}(hhh](h)}(h'Min page-size in bytes for this region.h]h'Min page-size in bytes for this region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMDhj ubh)}(hXWhen the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met.h](hXWhen the kernel allocates memory for this region, the underlying pages will be at least }(hjhhhNhNubj)}(h**min_page_size**h]h min_page_size}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX9 in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return }(hjhhhNhNubjC)}(h ``-EINVAL``h]h-EINVAL}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh' if alignment restrictions are not met.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMFhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMNhjLubj)}(h9``total_size`` The usable size in bytes for this region. h](j)}(h``total_size``h]jC)}(hjch]h total_size}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjaubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMRhj]ubj)}(hhh]h)}(h)The usable size in bytes for this region.h]h)The usable size in bytes for this region.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMRhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhMRhjLubj)}(h?``used`` Estimate of the memory used in bytes for this region. h](j)}(h``used``h]jC)}(hjh]hused}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMVhjubj)}(hhh]h)}(h5Estimate of the memory used in bytes for this region.h]h5Estimate of the memory used in bytes for this region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMVhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMVhjLubj)}(hX#``cpu_visible_size`` How much of this region can be CPU accessed, in bytes. This will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system. On systems without small BAR (full BAR), the **cpu_visible_size** will always equal the **total_size**, since all of it will be CPU accessible. Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero). h](j)}(h``cpu_visible_size``h]jC)}(hjh]hcpu_visible_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhhjubj)}(hhh](h)}(h6How much of this region can be CPU accessed, in bytes.h]h6How much of this region can be CPU accessed, in bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMZhjubh)}(hThis will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system.h](hThis will always be <= }(hjhhhNhNubj)}(h**total_size**h]h total_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhd, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than }(hjhhhNhNubj)}(h**total_size**h]h total_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh0 then this is referred to as a small BAR system.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM]hjubh)}(hOn systems without small BAR (full BAR), the **cpu_visible_size** will always equal the **total_size**, since all of it will be CPU accessible.h](h-On systems without small BAR (full BAR), the }(hj0hhhNhNubj)}(h**cpu_visible_size**h]hcpu_visible_size}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh will always equal the }(hj0hhhNhNubj)}(h**total_size**h]h total_size}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh), since all of it will be CPU accessible.}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMbhjubh)}(h{Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero).h]h{Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero).}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMfhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhhjLubj)}(h``cpu_visible_used`` Estimate of CPU visible memory used, in bytes. Note this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero). h](j)}(h``cpu_visible_used``h]jC)}(hjh]hcpu_visible_used}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMqhj~ubj)}(hhh](h)}(h.Estimate of CPU visible memory used, in bytes.h]h.Estimate of CPU visible memory used, in bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMlhjubh)}(hNote this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero).h]hNote this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMohjubeh}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhjhMqhjLubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMshjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMthjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMshjLubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_xe_query_mem_regions (C struct)c.drm_xe_query_mem_regionshNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_mem_regionsh]jg)}(hstruct drm_xe_query_mem_regionsh](jm)}(hjph]hstruct}(hj'hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj#hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMzubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj#hhhj4hMzubj)}(hdrm_xe_query_mem_regionsh]j)}(hj!h]hdrm_xe_query_mem_regions}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ](jjeh"]h$]h&]jjuh1jhj#hhhj4hMzubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhj4hMzubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hj4hMzhjhhubj)}(hhh]h)}(hdescribe memory regionsh]hdescribe memory regions}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMxhjfhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj4hMzubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX=**Definition**:: struct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; }; **Members** ``num_mem_regions`` number of memory regions returned in **mem_regions** ``pad`` MBZ ``mem_regions`` The returned memory regions for this deviceh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM|hjubj)}(hzstruct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; };h]hzstruct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM~hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(hI``num_mem_regions`` number of memory regions returned in **mem_regions** h](j)}(h``num_mem_regions``h]jC)}(hjh]hnum_mem_regions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h4number of memory regions returned in **mem_regions**h](h%number of memory regions returned in }(hjhhhNhNubj)}(h**mem_regions**h]h mem_regions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMhj3ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj2hMhjubj)}(h;``mem_regions`` The returned memory regions for this deviceh](j)}(h``mem_regions``h]jC)}(hjVh]h mem_regions}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjTubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjPubj)}(hhh]h)}(h+The returned memory regions for this deviceh]h+The returned memory regions for this device}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhjkhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses struct drm_xe_query_mem_regions in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses struct drm_xe_query_mem_regions in .data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMyhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_query_config (C struct)c.drm_xe_query_confighNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_configh]jg)}(hstruct drm_xe_query_configh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_xe_query_configh]j)}(hjh]hdrm_xe_query_config}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(h!describe the device configurationh]h!describe the device configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj1jj1jjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; }; **Members** ``num_params`` number of parameters returned in info ``pad`` MBZ ``info`` array of elements containing the config infoh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubh:}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj5ubj)}(hX struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; };h]hX struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; };}hjVsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj5ubh)}(h **Members**h]j)}(hjgh]hMembers}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj5ubj)}(hhh](j)}(h5``num_params`` number of parameters returned in info h](j)}(h``num_params``h]jC)}(hjh]h num_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h%number of parameters returned in infoh]h%number of parameters returned in info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj}ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj}ubj)}(h5``info`` array of elements containing the config infoh](j)}(h``info``h]jC)}(hjh]hinfo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h,array of elements containing the config infoh]h,array of elements containing the config info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhj}ubeh}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj;h]h Description}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses struct drm_xe_query_config in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses struct drm_xe_query_config in .data.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hhh]j)}(hXThe index in **info** can be: - ``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits) - ``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list below - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAM - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT`` - Flag is set if the device supports the userspace hint ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``. This is exposed only on Xe2+. - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX`` - Flag is set if a queue can be created with ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX`` - ``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64K - ``DRM_XE_QUERY_CONFIG_VA_BITS`` - Maximum bits of a virtual address - ``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priority h](j)}(hThe index in **info** can be:h](h The index in }(hjghhhNhNubj)}(h**info**h]hinfo}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubh can be:}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjcubj)}(hhh]h)}(hhh](h)}(hk``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits)h]h)}(hk``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits)h](jC)}(h)``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID``h]h%DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhB - Device ID (lower 16 bits) and the device revision (next 8 bits)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hX``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list below - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAM - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT`` - Flag is set if the device supports the userspace hint ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``. This is exposed only on Xe2+. - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX`` - Flag is set if a queue can be created with ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h](h)}(hY``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list belowh](jC)}(h``DRM_XE_QUERY_CONFIG_FLAGS``h]hDRM_XE_QUERY_CONFIG_FLAGS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh< - Flags describing the device configuration, see list below}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(hQ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAMh]h)}(hQ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAMh](jC)}(h%``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM``h]h!DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh, - Flag is set if the device has usable VRAM}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(he``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint supporth]h)}(he``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint supporth](jC)}(h,``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY``h]h(DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh9 - Flag is set if the device has low latency hint support}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hn``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring supporth]h)}(hn``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring supporth](jC)}(h0``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR``h]h,DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj+ubh> - Flag is set if the device has CPU address mirroring support}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj'ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT`` - Flag is set if the device supports the userspace hint ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``. This is exposed only on Xe2+.h]h)}(h``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT`` - Flag is set if the device supports the userspace hint ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``. This is exposed only on Xe2+.h](jC)}(h4``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT``h]h0DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjRubh9 - Flag is set if the device supports the userspace hint }(hjRhhhNhNubjC)}(h)``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``h]h%DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjRubh. This is exposed only on Xe2+.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjNubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX`` - Flag is set if a queue can be created with ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h]h)}(h``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX`` - Flag is set if a queue can be created with ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h](jC)}(h=``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX``h]h9DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh. - Flag is set if a queue can be created with }(hjhhhNhNubjC)}(h6``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h]h2DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j j uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(hs``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64Kh]h)}(hs``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64Kh](jC)}(h%``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT``h]h!DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhN - Minimal memory alignment required by this device, typically SZ_4K or SZ_64K}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hC``DRM_XE_QUERY_CONFIG_VA_BITS`` - Maximum bits of a virtual addressh]h)}(hjh](jC)}(h``DRM_XE_QUERY_CONFIG_VA_BITS``h]hDRM_XE_QUERY_CONFIG_VA_BITS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh$ - Maximum bits of a virtual address}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hh``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priority h]h)}(hd``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priorityh](jC)}(h/``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY``h]h+DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh5 - Value of the highest available exec queue priority}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j j uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhjhMhj`ubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_gt (C struct) c.drm_xe_gthNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(h drm_xe_gth]jg)}(hstruct drm_xe_gth](jm)}(hjph]hstruct}(hjmhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjihhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjihhhjzhMubj)}(h drm_xe_gth]j)}(hjgh]h drm_xe_gt}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjihhhjzhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjehhhjzhMubah}(h]j`ah ](jjeh"]h$]h&]jj)jhuh1j`hjzhMhjbhhubj)}(hhh]h)}(hdescribe an individual GT.h]hdescribe an individual GT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjbhhhjzhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; }; **Members** ``type`` GT type: Main or Media ``tile_id`` Tile ID where this GT lives (Information only) ``gt_id`` Unique ID of this GT within the PCI Device ``pad`` MBZ ``reference_clock`` A clock frequency for timestamp ``near_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``far_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``ip_ver_major`` Graphics/media IP major version on GMD_ID platforms ``ip_ver_minor`` Graphics/media IP minor version on GMD_ID platforms ``ip_ver_rev`` Graphics/media IP revision version on GMD_ID platforms ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hXstruct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; };h]hXstruct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h ``type`` GT type: Main or Media h](j)}(h``type``h]jC)}(hjh]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hGT type: Main or Mediah]hGT type: Main or Media}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj1hMhjubj)}(h;``tile_id`` Tile ID where this GT lives (Information only) h](j)}(h ``tile_id``h]jC)}(hjUh]htile_id}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjSubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjOubj)}(hhh]h)}(h.Tile ID where this GT lives (Information only)h]h.Tile ID where this GT lives (Information only)}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMhjkubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhjjhMhjubj)}(h5``gt_id`` Unique ID of this GT within the PCI Device h](j)}(h ``gt_id``h]jC)}(hjh]hgt_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h*Unique ID of this GT within the PCI Deviceh]h*Unique ID of this GT within the PCI Device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h4``reference_clock`` A clock frequency for timestamp h](j)}(h``reference_clock``h]jC)}(hjh]hreference_clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hA clock frequency for timestamph]hA clock frequency for timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hXV``near_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h``near_mem_regions``h]jC)}(hj9h]hnear_mem_regions}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj7ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj3ubj)}(hhh]h)}(hX@Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h]hXDBit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhMhjubj)}(hX``far_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h``far_mem_regions``h]jC)}(hjsh]hfar_mem_regions}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjqubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjmubj)}(hhh]h)}(hXBit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h](hBit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the }(hjhhhNhNubj)}(h**near_mem_regions**h]hnear_mem_regions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX9. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hE``ip_ver_major`` Graphics/media IP major version on GMD_ID platforms h](j)}(h``ip_ver_major``h]jC)}(hjh]h ip_ver_major}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h3Graphics/media IP major version on GMD_ID platformsh]h3Graphics/media IP major version on GMD_ID platforms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hE``ip_ver_minor`` Graphics/media IP minor version on GMD_ID platforms h](j)}(h``ip_ver_minor``h]jC)}(hjh]h ip_ver_minor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h3Graphics/media IP minor version on GMD_ID platformsh]h3Graphics/media IP minor version on GMD_ID platforms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(hF``ip_ver_rev`` Graphics/media IP revision version on GMD_ID platforms h](j)}(h``ip_ver_rev``h]jC)}(hj1h]h ip_ver_rev}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj/ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj+ubj)}(hhh]h)}(h6Graphics/media IP revision version on GMD_ID platformsh]h6Graphics/media IP revision version on GMD_ID platforms}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhMhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjFhMhjubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]jC)}(hjjh]hpad2}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjhubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjdubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hTo be used with drm_xe_query_gt_list, which will return a list with all the existing GT individual descriptions. Graphics Technology (GT) is a subset of a GPU/tile that is responsible for implementing graphics and/or media operations.h]hTo be used with drm_xe_query_gt_list, which will return a list with all the existing GT individual descriptions. Graphics Technology (GT) is a subset of a GPU/tile that is responsible for implementing graphics and/or media operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hhh]j)}(hbThe index in **type** can be: - ``DRM_XE_QUERY_GT_TYPE_MAIN`` - ``DRM_XE_QUERY_GT_TYPE_MEDIA`` h](j)}(hThe index in **type** can be:h](h The index in }(hjhhhNhNubj)}(h**type**h]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hhh](h)}(h``DRM_XE_QUERY_GT_TYPE_MAIN``h]h)}(hj;h]jC)}(hj;h]hDRM_XE_QUERY_GT_TYPE_MAIN}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj=ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj9ubah}(h]h ]h"]h$]h&]uh1hhj6ubh)}(h"``DRM_XE_QUERY_GT_TYPE_MEDIA`` h]h)}(h``DRM_XE_QUERY_GT_TYPE_MEDIA``h]jC)}(hj`h]hDRM_XE_QUERY_GT_TYPE_MEDIA}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj^ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjZubah}(h]h ]h"]h$]h&]uh1hhj6ubeh}(h]h ]h"]h$]h&]j j uh1hhjShMhj3ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj2hMhj ubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_query_gt_list (C struct)c.drm_xe_query_gt_listhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_gt_listh]jg)}(hstruct drm_xe_query_gt_listh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_xe_query_gt_listh]j)}(hjh]hdrm_xe_query_gt_list}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(h!A list with GT description items.h]h!A list with GT description items.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; }; **Members** ``num_gt`` number of GT items returned in gt_list ``pad`` MBZ ``gt_list`` The GT list returned for this deviceh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hastruct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; };h]hastruct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; };}hj,sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubh)}(h **Members**h]j)}(hj=h]hMembers}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh](j)}(h2``num_gt`` number of GT items returned in gt_list h](j)}(h ``num_gt``h]jC)}(hj\h]hnum_gt}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjZubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjVubj)}(hhh]h)}(h&number of GT items returned in gt_listh]h&number of GT items returned in gt_list}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhMhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjqhMhjSubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjSubj)}(h0``gt_list`` The GT list returned for this deviceh](j)}(h ``gt_list``h]jC)}(hjh]hgt_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h$The GT list returned for this deviceh]h$The GT list returned for this device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjSubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct drm_xe_query_gt_list in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct drm_xe_query_gt_list in .data.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_xe_query_topology_mask (C struct)c.drm_xe_query_topology_maskhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_topology_maskh]jg)}(h!struct drm_xe_query_topology_maskh](jm)}(hjph]hstruct}(hjOhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjKhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjKhhhj\hMubj)}(hdrm_xe_query_topology_maskh]j)}(hjIh]hdrm_xe_query_topology_mask}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubah}(h]h ](jjeh"]h$]h&]jjuh1jhjKhhhj\hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjGhhhj\hMubah}(h]jBah ](jjeh"]h$]h&]jj)jhuh1j`hj\hMhjDhhubj)}(hhh]h)}(h"describe the topology mask of a GTh]h"describe the topology mask of a GT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjDhhhj\hMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX$**Definition**:: struct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; }; **Members** ``gt_id`` GT ID the mask is associated with ``type`` type of mask ``num_bytes`` number of bytes in requested mask ``mask`` little-endian mask of **num_bytes**h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjubj)}(hXDstruct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; };h]hXDstruct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h,``gt_id`` GT ID the mask is associated with h](j)}(h ``gt_id``h]jC)}(hjh]hgt_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM.hjubj)}(hhh]h)}(h!GT ID the mask is associated withh]h!GT ID the mask is associated with}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM.hjubj)}(h``type`` type of mask h](j)}(h``type``h]jC)}(hj7h]htype}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj5ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM6hj1ubj)}(hhh]h)}(h type of maskh]h type of mask}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM6hjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhM6hjubj)}(h0``num_bytes`` number of bytes in requested mask h](j)}(h ``num_bytes``h]jC)}(hjph]h num_bytes}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjnubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM9hjjubj)}(hhh]h)}(h!number of bytes in requested maskh]h!number of bytes in requested mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM9hjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjhM9hjubj)}(h,``mask`` little-endian mask of **num_bytes**h](j)}(h``mask``h]jC)}(hjh]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM;hjubj)}(hhh]h)}(h#little-endian mask of **num_bytes**h](hlittle-endian mask of }(hjhhhNhNubj)}(h **num_bytes**h]h num_bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM<hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM;hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM?hj-hhubh)}(hXThis is the hardware topology which reflects the internal physical structure of the GPU.h]hXThis is the hardware topology which reflects the internal physical structure of the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj-hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses struct drm_xe_query_topology_mask in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses struct drm_xe_query_topology_mask in .data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj-hhubj)}(hhh]j)}(hXYThe **type** can be: - ``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry. - ``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute. - ``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware. - ``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs. - ``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs. h](j)}(hThe **type** can be:h](hThe }(hj5hhhNhNubj)}(h**type**h]htype}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh can be:}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM,hj1ubj)}(hhh]h)}(hhh](h)}(hX``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry.h]h)}(hX``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry.h](jC)}(h``DRM_XE_TOPO_DSS_GEOMETRY``h]hDRM_XE_TOPO_DSS_GEOMETRY}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubh - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: }(hj`hhhNhNubjC)}(h+``DSS_GEOMETRY ff ff ff ff 00 00 00 00``h]h'DSS_GEOMETRY ff ff ff ff 00 00 00 00}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubh) means 32 DSS are available for geometry.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj\ubah}(h]h ]h"]h$]h&]uh1hhjYubh)}(h``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute.h]h)}(h``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute.h](jC)}(h``DRM_XE_TOPO_DSS_COMPUTE``h]hDRM_XE_TOPO_DSS_COMPUTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: }(hjhhhNhNubjC)}(h*``DSS_COMPUTE ff ff ff ff 00 00 00 00``h]h&DSS_COMPUTE ff ff ff ff 00 00 00 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh( means 32 DSS are available for compute.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjYubh)}(h``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.h]h)}(h``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.h](jC)}(h``DRM_XE_TOPO_L3_BANK``h]hDRM_XE_TOPO_L3_BANK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjYubh)}(hX0``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs.h]h)}(hX0``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs.h](jC)}(h``DRM_XE_TOPO_EU_PER_DSS``h]hDRM_XE_TOPO_EU_PER_DSS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: }(hjhhhNhNubjC)}(h)``EU_PER_DSS ff ff 00 00 00 00 00 00``h]h%EU_PER_DSS ff ff 00 00 00 00 00 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh^ means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn’t have SIMD8 EUs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjYubh)}(hXK``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs. h]h)}(hXG``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs.h](jC)}(h!``DRM_XE_TOPO_SIMD16_EU_PER_DSS``h]hDRM_XE_TOPO_SIMD16_EU_PER_DSS}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj2ubh - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: }(hj2hhhNhNubjC)}(h0``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00``h]h,SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj2ubh` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn’t have SIMD16 EUs.}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM$hj.ubah}(h]h ]h"]h$]h&]uh1hhjYubeh}(h]h ]h"]h$]h&]j j uh1hhjhMhjVubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhjUhM,hj.ubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_xe_query_engine_cycles (C struct)c.drm_xe_query_engine_cycleshNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_engine_cyclesh]jg)}(h!struct drm_xe_query_engine_cyclesh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM.ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhM.ubj)}(hdrm_xe_query_engine_cyclesh]j)}(hjh]hdrm_xe_query_engine_cycles}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM.ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhM.ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhM.hjhhubj)}(hhh]h)}(h correlate CPU and GPU timestampsh]h correlate CPU and GPU timestamps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM@hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM.ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; }; **Members** ``eci`` This is input by the user and is the engine for which command streamer cycles is queried. ``clockid`` This is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. ``width`` Width of the engine cycle counter in bits. ``engine_cycles`` Engine cycles as read from its register at 0x358 offset. ``cpu_timestamp`` CPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user. ``cpu_delta`` Time delta in ns captured around reading the lower dword of the engine_cycles register.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMDhjubj)}(hstruct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; };h]hstruct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMFhjubh)}(h **Members**h]j)}(hj(h]hMembers}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMOhjubj)}(hhh](j)}(hb``eci`` This is input by the user and is the engine for which command streamer cycles is queried. h](j)}(h``eci``h]jC)}(hjGh]heci}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjEubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMPhjAubj)}(hhh]h)}(hYThis is input by the user and is the engine for which command streamer cycles is queried.h]hYThis is input by the user and is the engine for which command streamer cycles is queried.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMOhj]ubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhj\hMPhj>ubj)}(h``clockid`` This is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. h](j)}(h ``clockid``h]jC)}(hjh]hclockid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMXhj{ubj)}(hhh]h)}(hThis is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.h]hThis is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMUhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jhjhMXhj>ubj)}(h5``width`` Width of the engine cycle counter in bits. h](j)}(h ``width``h]jC)}(hjh]hwidth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM\hjubj)}(hhh]h)}(h*Width of the engine cycle counter in bits.h]h*Width of the engine cycle counter in bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM\hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM\hj>ubj)}(hK``engine_cycles`` Engine cycles as read from its register at 0x358 offset. h](j)}(h``engine_cycles``h]jC)}(hjh]h engine_cycles}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMahjubj)}(hhh]h)}(h8Engine cycles as read from its register at 0x358 offset.h]h8Engine cycles as read from its register at 0x358 offset.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM`hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMahj>ubj)}(h``cpu_timestamp`` CPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user. h](j)}(h``cpu_timestamp``h]jC)}(hj.h]h cpu_timestamp}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhhj(ubj)}(hhh]h)}(hCPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user.h]hCPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMfhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjChMhhj>ubj)}(he``cpu_delta`` Time delta in ns captured around reading the lower dword of the engine_cycles register.h](j)}(h ``cpu_delta``h]jC)}(hjhh]h cpu_delta}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjfubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMmhjbubj)}(hhh]h)}(hWTime delta in ns captured around reading the lower dword of the engine_cycles register.h]hWTime delta in ns captured around reading the lower dword of the engine_cycles register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMmhj~ubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jhj}hMmhj>ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMqhj-hhubh)}(hXIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles in .data. struct drm_xe_query_engine_cycles is allocated by the user and .data points to this allocated structure.h]hXIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles in .data. struct drm_xe_query_engine_cycles is allocated by the user and .data points to this allocated structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMAhj-hhubh)}(hThe query returns the engine cycles, which along with GT's **reference_clock**, can be used to calculate the engine timestamp. In addition the query returns a set of cpu timestamps that indicate when the command streamer cycle count was captured.h](h=The query returns the engine cycles, which along with GT’s }(hjhhhNhNubj)}(h**reference_clock**h]hreference_clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, can be used to calculate the engine timestamp. In addition the query returns a set of cpu timestamps that indicate when the command streamer cycle count was captured.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMFhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW%drm_xe_query_uc_fw_version (C struct)c.drm_xe_query_uc_fw_versionhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_uc_fw_versionh]jg)}(h!struct drm_xe_query_uc_fw_versionh](jm)}(hjph]hstruct}(hj hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMNubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMNubj)}(hdrm_xe_query_uc_fw_versionh]j)}(hjh]hdrm_xe_query_uc_fw_version}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMNubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMNubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMNhjhhubj)}(hhh]h)}(h)query a micro-controller firmware versionh]h)query a micro-controller firmware version}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMshjHhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMNubeh}(h]h ](jstructeh"]h$]h&]jjjjcjjcjjjuh1j[hhhj-hNhNubj)}(hXT**Definition**:: struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; }; **Members** ``uc_type`` The micro-controller type to query firmware version ``pad`` MBZ ``branch_ver`` branch uc fw version ``major_ver`` major uc fw version ``minor_ver`` minor uc fw version ``patch_ver`` patch uc fw version ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubh:}(hjkhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMwhjgubj)}(hX struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; };h]hX struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMyhjgubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjgubj)}(hhh](j)}(h@``uc_type`` The micro-controller type to query firmware version h](j)}(h ``uc_type``h]jC)}(hjh]huc_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMzhjubj)}(hhh]h)}(h3The micro-controller type to query firmware versionh]h3The micro-controller type to query firmware version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMzhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMzhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h$``branch_ver`` branch uc fw version h](j)}(h``branch_ver``h]jC)}(hj*h]h branch_ver}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj(ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj$ubj)}(hhh]h)}(hbranch uc fw versionh]hbranch uc fw version}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhjubj)}(h"``major_ver`` major uc fw version h](j)}(h ``major_ver``h]jC)}(hjch]h major_ver}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjaubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj]ubj)}(hhh]h)}(hmajor uc fw versionh]hmajor uc fw version}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhMhjubj)}(h"``minor_ver`` minor uc fw version h](j)}(h ``minor_ver``h]jC)}(hjh]h minor_ver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hminor uc fw versionh]hminor uc fw version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h"``patch_ver`` patch uc fw version h](j)}(h ``patch_ver``h]jC)}(hjh]h patch_ver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hpatch uc fw versionh]hpatch uc fw version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]jC)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMhj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj#hMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjGh]hreserved}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjEubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjAubj)}(hhh]h)}(hReservedh]hReserved}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj]ubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhj\hMhjubeh}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hmGiven a uc_type this will return the branch, major, minor and patch version of the micro-controller firmware.h]hmGiven a uc_type this will return the branch, major, minor and patch version of the micro-controller firmware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMthj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_xe_query_pxp_status (C struct)c.drm_xe_query_pxp_statushNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_pxp_statush]jg)}(hstruct drm_xe_query_pxp_statush](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMzubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMzubj)}(hdrm_xe_query_pxp_statush]j)}(hjh]hdrm_xe_query_pxp_status}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMzubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMzubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMzhjhhubj)}(hhh]h)}(hquery if PXP is readyh]hquery if PXP is ready}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMzubeh}(h]h ](jstructeh"]h$]h&]jjjj"jj"jjjuh1j[hhhj-hNhNubj)}(h**Definition**:: struct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; }; **Members** ``status`` current PXP status ``supported_session_types`` bitmask of supported PXP session typesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubh:}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj&ubj)}(hXstruct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; };h]hXstruct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; };}hjGsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj&ubh)}(h **Members**h]j)}(hjXh]hMembers}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj&ubj)}(hhh](j)}(h``status`` current PXP status h](j)}(h ``status``h]jC)}(hjwh]hstatus}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjuubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjqubj)}(hhh]h)}(hcurrent PXP statush]hcurrent PXP status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhjhMhjnubj)}(hB``supported_session_types`` bitmask of supported PXP session typesh](j)}(h``supported_session_types``h]jC)}(hjh]hsupported_session_types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h&bitmask of supported PXP session typesh]h&bitmask of supported PXP session types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjnubeh}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hIf PXP is enabled and no fatal error has occurred, the status will be set to one of the following values: 0: PXP init still in progress 1: PXP init completeh]hIf PXP is enabled and no fatal error has occurred, the status will be set to one of the following values: 0: PXP init still in progress 1: PXP init complete}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hXXIf PXP is not enabled or something has gone wrong, the query will be failed with one of the following error codes: -ENODEV: PXP not supported or disabled; -EIO: fatal error occurred during init, so PXP will never be enabled; -EINVAL: incorrect value provided as part of the query; -EFAULT: error copying the memory between kernel and userspace.h]hXXIf PXP is not enabled or something has gone wrong, the query will be failed with one of the following error codes: -ENODEV: PXP not supported or disabled; -EIO: fatal error occurred during init, so PXP will never be enabled; -EINVAL: incorrect value provided as part of the query; -EFAULT: error copying the memory between kernel and userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hX.The status can only be 0 in the first few seconds after driver load. If everything works as expected, the status will transition to init complete in less than 1 second, while in case of errors the driver might take longer to start returning an error code, but it should still take less than 10 seconds.h]hX.The status can only be 0 in the first few seconds after driver load. If everything works as expected, the status will transition to init complete in less than 1 second, while in case of errors the driver might take longer to start returning an error code, but it should still take less than 10 seconds.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hThe supported session type bitmask is based on the values in enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore is not reported in the bitmask.h]hThe supported session type bitmask is based on the values in enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore is not reported in the bitmask.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_device_query (C struct)c.drm_xe_device_queryhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_device_queryh]jg)}(hstruct drm_xe_device_queryh](jm)}(hjph]hstruct}(hj^hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjZhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjZhhhjkhMubj)}(hdrm_xe_device_queryh]j)}(hjXh]hdrm_xe_device_query}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ](jjeh"]h$]h&]jjuh1jhjZhhhjkhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjVhhhjkhMubah}(h]jQah ](jjeh"]h$]h&]jj)jhuh1j`hjkhMhjShhubj)}(hhh]h)}(hYInput of :c:type:`DRM_IOCTL_XE_DEVICE_QUERY` - main structure to query device informationh](h Input of }(hjhhhNhNubh)}(h#:c:type:`DRM_IOCTL_XE_DEVICE_QUERY`h]jC)}(hjh]hDRM_IOCTL_XE_DEVICE_QUERY}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j ASTIdentifier)} identifierjXsbc.drm_xe_device_queryasbjDRM_IOCTL_XE_DEVICE_QUERYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubh- - main structure to query device information}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjShhhjkhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``query`` The type of data to query ``size`` Size of the queried data ``data`` Queried data is placed here ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hXstruct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; };h]hXstruct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; };}hj sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj;h]h extensions}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj5ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhMhj2ubj)}(h$``query`` The type of data to query h](j)}(h ``query``h]jC)}(hjth]hquery}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjrubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjnubj)}(hhh]h)}(hThe type of data to queryh]hThe type of data to query}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjhMhj2ubj)}(h"``size`` Size of the queried data h](j)}(h``size``h]jC)}(hjh]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hSize of the queried datah]hSize of the queried data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj2ubj)}(h%``data`` Queried data is placed here h](j)}(h``data``h]jC)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hQueried data is placed hereh]hQueried data is placed here}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj2ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReservedh]hReserved}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj5ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj4hMhj2ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjbh]h Description}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj-hhubh)}(hThe user selects the type of data to query among DRM_XE_DEVICE_QUERY_* and sets the value in the query member. This determines the type of the structure provided by the driver in data, among struct drm_xe_query_*.h]hThe user selects the type of data to query among DRM_XE_DEVICE_QUERY_* and sets the value in the query member. This determines the type of the structure provided by the driver in data, among struct drm_xe_query_*.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hhh]j)}(hX\The **query** can be: - ``DRM_XE_DEVICE_QUERY_ENGINES`` - ``DRM_XE_DEVICE_QUERY_MEM_REGIONS`` - ``DRM_XE_DEVICE_QUERY_CONFIG`` - ``DRM_XE_DEVICE_QUERY_GT_LIST`` - ``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes. - ``DRM_XE_DEVICE_QUERY_GT_TOPOLOGY`` - ``DRM_XE_DEVICE_QUERY_ENGINE_CYCLES`` - ``DRM_XE_DEVICE_QUERY_UC_FW_VERSION`` - ``DRM_XE_DEVICE_QUERY_OA_UNITS`` - ``DRM_XE_DEVICE_QUERY_PXP_STATUS`` - ``DRM_XE_DEVICE_QUERY_EU_STALL`` h](j)}(hThe **query** can be:h](hThe }(hjhhhNhNubj)}(h **query**h]hquery}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hhh](h)}(h``DRM_XE_DEVICE_QUERY_ENGINES``h]h)}(hjh]jC)}(hjh]hDRM_XE_DEVICE_QUERY_ENGINES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h#``DRM_XE_DEVICE_QUERY_MEM_REGIONS``h]h)}(hjh]jC)}(hjh]hDRM_XE_DEVICE_QUERY_MEM_REGIONS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_DEVICE_QUERY_CONFIG``h]h)}(hjh]jC)}(hjh]hDRM_XE_DEVICE_QUERY_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_DEVICE_QUERY_GT_LIST``h]h)}(hjh]jC)}(hjh]hDRM_XE_DEVICE_QUERY_GT_LIST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.h]h)}(h``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.h](jC)}(h ``DRM_XE_DEVICE_QUERY_HWCONFIG``h]hDRM_XE_DEVICE_QUERY_HWCONFIG}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj=ubh - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj9ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h#``DRM_XE_DEVICE_QUERY_GT_TOPOLOGY``h]h)}(hjbh]jC)}(hjbh]hDRM_XE_DEVICE_QUERY_GT_TOPOLOGY}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjdubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj`ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h%``DRM_XE_DEVICE_QUERY_ENGINE_CYCLES``h]h)}(hjh]jC)}(hjh]h!DRM_XE_DEVICE_QUERY_ENGINE_CYCLES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h%``DRM_XE_DEVICE_QUERY_UC_FW_VERSION``h]h)}(hjh]jC)}(hjh]h!DRM_XE_DEVICE_QUERY_UC_FW_VERSION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h ``DRM_XE_DEVICE_QUERY_OA_UNITS``h]h)}(hjh]jC)}(hjh]hDRM_XE_DEVICE_QUERY_OA_UNITS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h"``DRM_XE_DEVICE_QUERY_PXP_STATUS``h]h)}(hjh]jC)}(hjh]hDRM_XE_DEVICE_QUERY_PXP_STATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h!``DRM_XE_DEVICE_QUERY_EU_STALL`` h]h)}(h ``DRM_XE_DEVICE_QUERY_EU_STALL``h]jC)}(hj h]hDRM_XE_DEVICE_QUERY_EU_STALL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j j uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubh)}(hX-If size is set to 0, the driver fills it with the required size for the requested type of data to query. If size is equal to the required size, the queried information is copied into data. If size is set to a value different from 0 and different from the required size, the IOCTL call returns -EINVAL.h]hX-If size is set to 0, the driver fills it with the required size for the requested type of data to query. If size is equal to the required size, the queried information is copied into data. If size is set to a value different from 0 and different from the required size, the IOCTL call returns -EINVAL.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hFor example the following code snippet allows retrieving and printing information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:h]hFor example the following code snippet allows retrieving and printing information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hXstruct drm_xe_query_engines *engines; struct drm_xe_device_query query = { .extensions = 0, .query = DRM_XE_DEVICE_QUERY_ENGINES, .size = 0, .data = 0, }; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); engines = malloc(query.size); query.data = (uintptr_t)engines; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); for (int i = 0; i < engines->num_engines; i++) { printf("Engine %d: %s\n", i, engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": "UNKNOWN"); } free(engines);h]hXstruct drm_xe_query_engines *engines; struct drm_xe_device_query query = { .extensions = 0, .query = DRM_XE_DEVICE_QUERY_ENGINES, .size = 0, .data = 0, }; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); engines = malloc(query.size); query.data = (uintptr_t)engines; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); for (int i = 0; i < engines->num_engines; i++) { printf("Engine %d: %s\n", i, engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": "UNKNOWN"); } free(engines);}hj\sbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_gem_create (C struct)c.drm_xe_gem_createhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_gem_createh]jg)}(hstruct drm_xe_gem_createh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_xe_gem_createh]j)}(hjh]hdrm_xe_gem_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj}hhhjhMubah}(h]jxah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjzhhubj)}(hhh]h)}(hIInput of :c:type:`DRM_IOCTL_XE_GEM_CREATE` - A structure for gem creationh](h Input of }(hjhhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]jC)}(hjh]hDRM_IOCTL_XE_GEM_CREATE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjsbc.drm_xe_gem_createasbjDRM_IOCTL_XE_GEM_CREATEuh1hhjhKhjubh - A structure for gem creation}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjhhubah}(h]h ]h"]h$]h&]uh1jhjzhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j[hhhj-hNhNubj)}(hX **Definition**:: struct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``size`` Size of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`). ``placement`` A mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``flags`` Flags for the GEM object, see DRM_XE_GEM_CREATE_FLAG_* ``vm_id`` Attached VM, if any If a VM is specified, this BO must: 1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. ``handle`` Returned handle for the object. Object handles are nonzero. ``cpu_caching`` The CPU caching mode to select for this object. If mmapping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients. ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hXstruct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; };h]hXstruct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; };}hj.sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubh)}(h **Members**h]j)}(hj?h]hMembers}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM'hj ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj^h]h extensions}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj\ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMOhjXubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMOhjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jhjshMOhjUubj)}(h{``size`` Size of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`). h](j)}(h``size``h]jC)}(hjh]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMThjubj)}(hhh]h)}(hqSize of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`).h](hXSize of the object to be created, must match region (system or vram) minimum alignment (}(hjhhhNhNubh)}(h:c:type:`min_page_size`h]jC)}(hjh]h min_page_size}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj min_page_sizeuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMShjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMShjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMThjUubj)}(hX``placement`` A mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h ``placement``h]jC)}(hjh]h placement}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM]hjubj)}(hhh]h)}(hXA mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h]hXA mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMYhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hM]hjUubj)}(hA``flags`` Flags for the GEM object, see DRM_XE_GEM_CREATE_FLAG_* h](j)}(h ``flags``h]jC)}(hj.h]hflags}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMfhj(ubj)}(hhh]h)}(h6Flags for the GEM object, see DRM_XE_GEM_CREATE_FLAG_*h]h6Flags for the GEM object, see DRM_XE_GEM_CREATE_FLAG_*}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMfhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjChMfhjUubj)}(h``vm_id`` Attached VM, if any If a VM is specified, this BO must: 1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. h](j)}(h ``vm_id``h]jC)}(hjgh]hvm_id}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjeubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMphjaubj)}(hhh](h)}(hAttached VM, if anyh]hAttached VM, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMkhj}ubh)}(h#If a VM is specified, this BO must:h]h#If a VM is specified, this BO must:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMmhj}ubjK)}(hG1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. h]jJ5)}(hhh](h)}(hOnly ever be bound to that VM.h]h)}(hjh]hOnly ever be bound to that VM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMohjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h"Cannot be exported as a PRIME fd. h]h)}(h!Cannot be exported as a PRIME fd.h]h!Cannot be exported as a PRIME fd.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMphjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j5j5j5hj5j5uh1jI5hjubah}(h]h ]h"]h$]h&]uh1jJhjhMohj}ubeh}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj|hMphjUubj)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]jC)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMwhjubj)}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMuhj ubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMwhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMwhjUubj)}(hX``cpu_caching`` The CPU caching mode to select for this object. If mmapping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients. h](j)}(h``cpu_caching``h]jC)}(hj;h]h cpu_caching}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj5ubj)}(hhh]h)}(hXThe CPU caching mode to select for this object. If mmapping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients.h]hXThe CPU caching mode to select for this object. If mmapping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM~hjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjUubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjuh]hpad}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjsubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjoubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjhMhjUubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjUubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hhh]j)}(hX'The **flags** can be: - ``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING`` - Modify the GEM object allocation strategy by deferring physical memory allocation until the object is either bound to a virtual memory region via VM_BIND or accessed by the CPU. As a result, no backing memory is reserved at the time of GEM object creation. - ``DRM_XE_GEM_CREATE_FLAG_SCANOUT`` - Indicates that the GEM object is intended for scanout via the display engine. When set, kernel ensures that the allocation is placed in a memory region compatible with the display engine requirements. This may impose restrictions on tiling, alignment, and memory placement to guarantee proper display functionality. - ``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems. - ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION`` - Allows userspace to hint that compression (CCS) should be disabled for the buffer being created. This can avoid unnecessary memory operations and CCS state management. On pre-Xe2 platforms, this flag is currently rejected as compression control is not supported via PAT index. On Xe2+ platforms, compression is controlled via PAT entries. If this flag is set, the driver will reject any VM bind that requests a PAT index enabling compression for this BO. h](j)}(hThe **flags** can be:h](hThe }(hjhhhNhNubj)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM/hj ubj)}(hhh]h)}(hhh](h)}(hX+``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING`` - Modify the GEM object allocation strategy by deferring physical memory allocation until the object is either bound to a virtual memory region via VM_BIND or accessed by the CPU. As a result, no backing memory is reserved at the time of GEM object creation.h]h)}(hX+``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING`` - Modify the GEM object allocation strategy by deferring physical memory allocation until the object is either bound to a virtual memory region via VM_BIND or accessed by the CPU. As a result, no backing memory is reserved at the time of GEM object creation.h](jC)}(h(``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING``h]h$DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj9ubhX - Modify the GEM object allocation strategy by deferring physical memory allocation until the object is either bound to a virtual memory region via VM_BIND or accessed by the CPU. As a result, no backing memory is reserved at the time of GEM object creation.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj5ubah}(h]h ]h"]h$]h&]uh1hhj2ubh)}(hX```DRM_XE_GEM_CREATE_FLAG_SCANOUT`` - Indicates that the GEM object is intended for scanout via the display engine. When set, kernel ensures that the allocation is placed in a memory region compatible with the display engine requirements. This may impose restrictions on tiling, alignment, and memory placement to guarantee proper display functionality.h]h)}(hX```DRM_XE_GEM_CREATE_FLAG_SCANOUT`` - Indicates that the GEM object is intended for scanout via the display engine. When set, kernel ensures that the allocation is placed in a memory region compatible with the display engine requirements. This may impose restrictions on tiling, alignment, and memory placement to guarantee proper display functionality.h](jC)}(h"``DRM_XE_GEM_CREATE_FLAG_SCANOUT``h]hDRM_XE_GEM_CREATE_FLAG_SCANOUT}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubhX> - Indicates that the GEM object is intended for scanout via the display engine. When set, kernel ensures that the allocation is placed in a memory region compatible with the display engine requirements. This may impose restrictions on tiling, alignment, and memory placement to guarantee proper display functionality.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj\ubah}(h]h ]h"]h$]h&]uh1hhj2ubh)}(hXN``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems.h]h)}(hXN``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems.h](jC)}(h-``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM``h]h)DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhX# - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can’t be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhj2ubh)}(hX``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION`` - Allows userspace to hint that compression (CCS) should be disabled for the buffer being created. This can avoid unnecessary memory operations and CCS state management. On pre-Xe2 platforms, this flag is currently rejected as compression control is not supported via PAT index. On Xe2+ platforms, compression is controlled via PAT entries. If this flag is set, the driver will reject any VM bind that requests a PAT index enabling compression for this BO. h]h)}(hX``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION`` - Allows userspace to hint that compression (CCS) should be disabled for the buffer being created. This can avoid unnecessary memory operations and CCS state management. On pre-Xe2 platforms, this flag is currently rejected as compression control is not supported via PAT index. On Xe2+ platforms, compression is controlled via PAT entries. If this flag is set, the driver will reject any VM bind that requests a PAT index enabling compression for this BO.h](jC)}(h)``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``h]h%DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhX - Allows userspace to hint that compression (CCS) should be disabled for the buffer being created. This can avoid unnecessary memory operations and CCS state management. On pre-Xe2 platforms, this flag is currently rejected as compression control is not supported via PAT index. On Xe2+ platforms, compression is controlled via PAT entries. If this flag is set, the driver will reject any VM bind that requests a PAT index enabling compression for this BO.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM(hjubah}(h]h ]h"]h$]h&]uh1hhj2ubeh}(h]h ]h"]h$]h&]j j uh1hhjUhMhj/ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj.hM/hjubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubh)}(h**Note**h]j)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM1hj-hhubj)}(hhh](j)}(hOn dGPU platforms, there is currently no change in behavior with this flag, but future improvements may leverage it. The current benefit is primarily applicable to iGPU platforms. h](j)}(h@On dGPU platforms, there is currently no change in behavior withh]h@On dGPU platforms, there is currently no change in behavior with}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM4hjubj)}(hhh]h)}(hrthis flag, but future improvements may leverage it. The current benefit is primarily applicable to iGPU platforms.h]hrthis flag, but future improvements may leverage it. The current benefit is primarily applicable to iGPU platforms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM4hjubj)}(hX**cpu_caching** supports the following values: - ``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM. - ``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this. h](j)}(h.**cpu_caching** supports the following values:h](j)}(h**cpu_caching**h]h cpu_caching}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubh supports the following values:}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM<hj5ubj)}(hhh]h)}(hhh](h)}(h``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM.h]h)}(h``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM.h](jC)}(h``DRM_XE_GEM_CPU_CACHING_WB``h]hDRM_XE_GEM_CPU_CACHING_WB}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubh - Allocate the pages with write-back caching. On iGPU this can’t be used for scanout surfaces. Currently not allowed for objects placed in VRAM.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM7hj\ubah}(h]h ]h"]h$]h&]uh1hhjYubh)}(h``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this. h]h)}(h``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this.h](jC)}(h``DRM_XE_GEM_CPU_CACHING_WC``h]hDRM_XE_GEM_CPU_CACHING_WC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM:hjubah}(h]h ]h"]h$]h&]uh1hhjYubeh}(h]h ]h"]h$]h&]j j uh1hhj|hM7hjVubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhjUhM<hjubeh}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubh)}(hThis ioctl supports setting the following properties via the ``DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY`` extension, which uses the generic :c:type:`struct drm_xe_ext_set_property `:h](h=This ioctl supports setting the following properties via the }(hjhhhNhNubjC)}(h,``DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY``h]h(DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh# extension, which uses the generic }(hjhhhNhNubh)}(hB:c:type:`struct drm_xe_ext_set_property `h]jC)}(hjh]hstruct drm_xe_ext_set_property}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_ext_set_propertyuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM>hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM>hj-hhubjK)}(hX=- ``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected. h]h)}(hhh]h)}(hX-``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected. h]h)}(hX)``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected.h](jC)}(h+``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE``h]h'DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhw - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. }(hjhhhNhNubjC)}(h``DRM_XE_PXP_TYPE_NONE``h]hDRM_XE_PXP_TYPE_NONE}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhh is the default behavior, so there is no need to explicitly set that. Objects used with session of type }(hjhhhNhNubjC)}(h``DRM_XE_PXP_TYPE_HWDRM``h]hDRM_XE_PXP_TYPE_HWDRM}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMBhj ubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]j j uh1hhjQhMBhjubah}(h]h ]h"]h$]h&]uh1jJhjQhMBhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW!drm_xe_gem_mmap_offset (C struct)c.drm_xe_gem_mmap_offsethNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_gem_mmap_offseth]jg)}(hstruct drm_xe_gem_mmap_offseth](jm)}(hjph]hstruct}(hj}hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjyhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMNubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjyhhhjhMNubj)}(hdrm_xe_gem_mmap_offseth]j)}(hjwh]hdrm_xe_gem_mmap_offset}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjyhhhjhMNubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjuhhhjhMNubah}(h]jpah ](jjeh"]h$]h&]jj)jhuh1j`hjhMNhjrhhubj)}(hhh]h)}(h/Input of :c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET`h](h Input of }(hjhhhNhNubh)}(h&:c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET`h]jC)}(hjh]hDRM_IOCTL_XE_GEM_MMAP_OFFSET}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjwsbc.drm_xe_gem_mmap_offsetasbjDRM_IOCTL_XE_GEM_MMAP_OFFSETuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjrhhhjhMNubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``handle`` Handle for the object being mapped. ``flags`` Flags ``offset`` The fake offset to use for subsequent mmap call ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hstruct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; };h]hstruct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; };}hj"sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hj3h]hMembers}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjRh]h extensions}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjPubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjLubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMhjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jhjghMhjIubj)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]jC)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjIubj)}(h``flags`` Flags h](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hFlagsh]hFlags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjIubj)}(h;``offset`` The fake offset to use for subsequent mmap call h](j)}(h ``offset``h]jC)}(hjh]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjIubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hj6h]hreserved}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj4ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj0ubj)}(hhh]h)}(hReservedh]hReserved}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjLubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMhjIubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjyh]h Description}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hhh]j)}(hXUThe **flags** can be: - ``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction. h](j)}(hThe **flags** can be:h](hThe }(hjhhhNhNubj)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hhh]h)}(hX5``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction. h]h)}(hX4``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction.h](jC)}(h'``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER``h]h#DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhX  - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]j j uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubh)}(h**Note**h]j)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hX5The mmap size can be at most 4K, due to HW limitations. As a result this interface is only supported on CPU architectures that support 4K page size. The mmap_offset ioctl will detect this and gracefully return an error, where userspace is expected to have a different fallback method for triggering a barrier.h]hX5The mmap size can be at most 4K, due to HW limitations. As a result this interface is only supported on CPU architectures that support 4K page size. The mmap_offset ioctl will detect this and gracefully return an error, where userspace is expected to have a different fallback method for triggering a barrier.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(h&Roughly the usage would be as follows:h]h&Roughly the usage would be as follows:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hXstruct drm_xe_gem_mmap_offset mmo = { .handle = 0, // must be set to 0 .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, }; err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); map[i] = 0xdeadbeef; // issue barrierh]hXstruct drm_xe_gem_mmap_offset mmo = { .handle = 0, // must be set to 0 .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, }; err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); map[i] = 0xdeadbeef; // issue barrier}hj2sbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_vm_create (C struct)c.drm_xe_vm_createhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_vm_createh]jg)}(hstruct drm_xe_vm_createh](jm)}(hjph]hstruct}(hj[hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjWhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjWhhhjhhMubj)}(hdrm_xe_vm_createh]j)}(hjUh]hdrm_xe_vm_create}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubah}(h]h ](jjeh"]h$]h&]jjuh1jhjWhhhjhhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjShhhjhhMubah}(h]jNah ](jjeh"]h$]h&]jj)jhuh1j`hjhhMhjPhhubj)}(hhh]h)}(h)Input of :c:type:`DRM_IOCTL_XE_VM_CREATE`h](h Input of }(hjhhhNhNubh)}(h :c:type:`DRM_IOCTL_XE_VM_CREATE`h]jC)}(hjh]hDRM_IOCTL_XE_VM_CREATE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjUsbc.drm_xe_vm_createasbjDRM_IOCTL_XE_VM_CREATEuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjPhhhjhhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3); __u32 flags; __u32 vm_id; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``flags`` Flags ``vm_id`` Returned VM ID ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hXSstruct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3); __u32 flags; __u32 vm_id; __u64 reserved[2]; };h]hXSstruct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3); __u32 flags; __u32 vm_id; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj0h]h extensions}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj.ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj*ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhjEhMhj'ubj)}(h``flags`` Flags h](j)}(h ``flags``h]jC)}(hjih]hflags}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjgubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjcubj)}(hhh]h)}(hFlagsh]hFlags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hMhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhj~hMhj'ubj)}(h``vm_id`` Returned VM ID h](j)}(h ``vm_id``h]jC)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReturned VM IDh]hReturned VM ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj'ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj'ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hhh]j)}(hXThe **flags** can be: - ``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception on Xe2 and Xe3 platforms. - ``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device. - ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this. - ``DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT`` - Requires also DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit but only during a :c:type:`DRM_IOCTL_XE_VM_BIND` operation with the ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` flag set. This may be useful for user-space naively probing the amount of available memory. h](j)}(hThe **flags** can be:h](hThe }(hj;hhhNhNubj)}(h **flags**h]hflags}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubh can be:}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj7ubj)}(hhh]h)}(hhh](h)}(hX``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception on Xe2 and Xe3 platforms.h]h)}(hX``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception on Xe2 and Xe3 platforms.h](jC)}(h&``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE``h]h"DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjfubh - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the }(hjfhhhNhNubjC)}(h$``DRM_XE_VM_CREATE_FLAG_FAULT_MODE``h]h DRM_XE_VM_CREATE_FLAG_FAULT_MODE}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjfubh2 flag, with an exception on Xe2 and Xe3 platforms.}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjbubah}(h]h ]h"]h$]h&]uh1hhj_ubh)}(hX``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.h]h)}(hX``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.h](jC)}(h!``DRM_XE_VM_CREATE_FLAG_LR_MODE``h]hDRM_XE_VM_CREATE_FLAG_LR_MODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhX - An LR, or Long Running VM accepts exec submissions to its exec_queues that don’t have an upper time limit on the job execution time. But exec submissions to these don’t allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhj_ubh)}(hX``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this.h]h)}(hX``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this.h](jC)}(h$``DRM_XE_VM_CREATE_FLAG_FAULT_MODE``h]h DRM_XE_VM_CREATE_FLAG_FAULT_MODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhj_ubh)}(hXC``DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT`` - Requires also DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit but only during a :c:type:`DRM_IOCTL_XE_VM_BIND` operation with the ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` flag set. This may be useful for user-space naively probing the amount of available memory. h]h)}(hX?``DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT`` - Requires also DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit but only during a :c:type:`DRM_IOCTL_XE_VM_BIND` operation with the ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` flag set. This may be useful for user-space naively probing the amount of available memory.h](jC)}(h*``DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT``h]h&DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhf - Requires also DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit but only during a }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]jC)}(hjh]hDRM_IOCTL_XE_VM_BIND}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_VM_BINDuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh operation with the }(hjhhhNhNubjC)}(h!``DRM_XE_VM_BIND_FLAG_IMMEDIATE``h]hDRM_XE_VM_BIND_FLAG_IMMEDIATE}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh\ flag set. This may be useful for user-space naively probing the amount of available memory.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj"hMhjubah}(h]h ]h"]h$]h&]uh1hhj_ubeh}(h]h ]h"]h$]h&]j j uh1hhjhMhj\ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj[hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_vm_destroy (C struct)c.drm_xe_vm_destroyhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_vm_destroyh]jg)}(hstruct drm_xe_vm_destroyh](jm)}(hjph]hstruct}(hjvhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjrhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjrhhhjhMubj)}(hdrm_xe_vm_destroyh]j)}(hjph]hdrm_xe_vm_destroy}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjrhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjnhhhjhMubah}(h]jiah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjkhhubj)}(hhh]h)}(h*Input of :c:type:`DRM_IOCTL_XE_VM_DESTROY`h](h Input of }(hjhhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_VM_DESTROY`h]jC)}(hjh]hDRM_IOCTL_XE_VM_DESTROY}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjpsbc.drm_xe_vm_destroyasbjDRM_IOCTL_XE_VM_DESTROYuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjkhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(h**Definition**:: struct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; }; **Members** ``vm_id`` VM ID ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hTstruct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; };h]hTstruct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hj,h]hMembers}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h``vm_id`` VM ID h](j)}(h ``vm_id``h]jC)}(hjKh]hvm_id}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjIubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjEubj)}(hhh]h)}(hVM IDh]hVM ID}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hMhjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhj`hMhjBubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj~ubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhjhMhjBubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjBubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_vm_bind_op (C struct)c.drm_xe_vm_bind_ophNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_vm_bind_oph]jg)}(hstruct drm_xe_vm_bind_oph](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhj$hMubj)}(hdrm_xe_vm_bind_oph]j)}(hjh]hdrm_xe_vm_bind_op}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj$hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhj$hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j`hj$hMhj hhubj)}(hhh]h)}(hrun bind operationsh]hrun bind operations}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjVhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj$hMubeh}(h]h ](jstructeh"]h$]h&]jjjjqjjqjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6); #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7); __u32 flags; #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``obj`` GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP ``pat_index`` The platform defined **pat_index** to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE. For coherency the **pat_index** needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the **pat_index** and reject if there is a mismatch (see note below for pre-MTL platforms). Note: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It's only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms: ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY In practice UC/WC/WT should only ever be used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible. Note: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**. Starting from NVL-P, for userptr, svm, madvise and externally imported dma-buf the kernel expects either 2WAY or 1WAY and XA **pat_index**. For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped. ``pad`` MBZ ``{unnamed_union}`` anonymous ``obj_offset`` Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind ``userptr`` user pointer to bind on ``cpu_addr_mirror_offset`` Offset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported). ``range`` Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL ``addr`` Address to operate on, MBZ for UNMAP_ALL ``op`` Bind operation to perform ``flags`` Bind flags ``prefetch_mem_region_instance`` Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation. ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubh:}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjuubj)}(hXstruct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6); #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7); __u32 flags; #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; };h]hXstruct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6); #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7); __u32 flags; #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; };%}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjuubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM%hjuubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM:hjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM:hjubj)}(hE``obj`` GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP h](j)}(h``obj``h]jC)}(hjh]hobj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM>hjubj)}(hhh]h)}(hhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM>hjubj)}(hXg ``pat_index`` The platform defined **pat_index** to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE. For coherency the **pat_index** needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the **pat_index** and reject if there is a mismatch (see note below for pre-MTL platforms). Note: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It's only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms: ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY In practice UC/WC/WT should only ever be used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible. Note: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**. Starting from NVL-P, for userptr, svm, madvise and externally imported dma-buf the kernel expects either 2WAY or 1WAY and XA **pat_index**. For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped. h](j)}(h ``pat_index``h]jC)}(hj8h]h pat_index}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMphj2ubj)}(hhh](h)}(hXaThe platform defined **pat_index** to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE.h](hThe platform defined }(hjQhhhNhNubj)}(h **pat_index**h]h pat_index}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubhX? to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMChjNubh)}(hX For coherency the **pat_index** needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the **pat_index** and reject if there is a mismatch (see note below for pre-MTL platforms).h](hFor coherency the }(hjrhhhNhNubj)}(h **pat_index**h]h pat_index}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubh needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the }(hjrhhhNhNubj)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubhJ and reject if there is a mismatch (see note below for pre-MTL platforms).}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMJhjNubh)}(hXNote: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It's only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms:h]hXNote: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It’s only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMOhjNubjK)}(h]ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY h]h)}(h\ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAYh]h\ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMXhjubah}(h]h ]h"]h$]h&]uh1jJhjhMXhjNubh)}(hXIn practice UC/WC/WT should only ever be used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible.h](hXxIn practice UC/WC/WT should only ever be used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the }(hjhhhNhNubj)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh), where incoherent GT access is possible.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM]hjNubh)}(hNote: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**. Starting from NVL-P, for userptr, svm, madvise and externally imported dma-buf the kernel expects either 2WAY or 1WAY and XA **pat_index**.h](haNote: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the }(hjhhhNhNubj)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh. Starting from NVL-P, for userptr, svm, madvise and externally imported dma-buf the kernel expects either 2WAY or 1WAY and XA }(hjhhhNhNubj)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMehjNubh)}(hXFor DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped.h](hKFor DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the }(hj!hhhNhNubj)}(h **pat_index**h]h pat_index}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubhXS. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped.}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMjhjNubeh}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhjMhMphjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjTh]hpad}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjRubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMthjNubj)}(hhh]h)}(hMBZh]hMBZ}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMthjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjihMthjubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]jC)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hO``obj_offset`` Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind h](j)}(h``obj_offset``h]jC)}(hjh]h obj_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMzhjubj)}(hhh]h)}(h?Offset into the object, MBZ for CLEAR_RANGE, ignored for unbindh]h?Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMyhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMzhjubj)}(h$``userptr`` user pointer to bind on h](j)}(h ``userptr``h]jC)}(hjh]huserptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM~hjubj)}(hhh]h)}(huser pointer to bind onh]huser pointer to bind on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM~hjubj)}(h``cpu_addr_mirror_offset`` Offset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported). h](j)}(h``cpu_addr_mirror_offset``h]jC)}(hj9h]hcpu_addr_mirror_offset}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj7ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj3ubj)}(hhh]h)}(hOffset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported).h](hOffset from GPU }(hjRhhhNhNubj)}(h**addr**h]haddr}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubh to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported).}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhMhjubj)}(hM``range`` Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL h](j)}(h ``range``h]jC)}(hjh]hrange}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hBNumber of bytes from the object to bind to addr, MBZ for UNMAP_ALLh]hBNumber of bytes from the object to bind to addr, MBZ for UNMAP_ALL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h2``addr`` Address to operate on, MBZ for UNMAP_ALL h](j)}(h``addr``h]jC)}(hjh]haddr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h(Address to operate on, MBZ for UNMAP_ALLh]h(Address to operate on, MBZ for UNMAP_ALL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h!``op`` Bind operation to perform h](j)}(h``op``h]jC)}(hjh]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hBind operation to performh]hBind operation to perform}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(h``flags`` Bind flags h](j)}(h ``flags``h]jC)}(hj0h]hflags}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj.ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj*ubj)}(hhh]h)}(h Bind flagsh]h Bind flags}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhjEhMhjubj)}(h``prefetch_mem_region_instance`` Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation. h](j)}(h ``prefetch_mem_region_instance``h]jC)}(hjih]hprefetch_mem_region_instance}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjgubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjcubj)}(hhh]h)}(hMemory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation.h](h\Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with }(hjhhhNhNubjC)}(h``DRM_XE_VM_BIND_OP_PREFETCH``h]hDRM_XE_VM_BIND_OP_PREFETCH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh operation.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhj~hMhjubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]jC)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj1h]h Description}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hhh](j)}(hThe **op** can be: - ``DRM_XE_VM_BIND_OP_MAP`` - ``DRM_XE_VM_BIND_OP_UNMAP`` - ``DRM_XE_VM_BIND_OP_MAP_USERPTR`` - ``DRM_XE_VM_BIND_OP_UNMAP_ALL`` - ``DRM_XE_VM_BIND_OP_PREFETCH`` h](j)}(hThe **op** can be:h](hThe }(hjNhhhNhNubj)}(h**op**h]hop}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubh can be:}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjJubj)}(hhh]h)}(hhh](h)}(h``DRM_XE_VM_BIND_OP_MAP``h]h)}(hjwh]jC)}(hjwh]hDRM_XE_VM_BIND_OP_MAP}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjyubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjuubah}(h]h ]h"]h$]h&]uh1hhjrubh)}(h``DRM_XE_VM_BIND_OP_UNMAP``h]h)}(hjh]jC)}(hjh]hDRM_XE_VM_BIND_OP_UNMAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjrubh)}(h!``DRM_XE_VM_BIND_OP_MAP_USERPTR``h]h)}(hjh]jC)}(hjh]hDRM_XE_VM_BIND_OP_MAP_USERPTR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjrubh)}(h``DRM_XE_VM_BIND_OP_UNMAP_ALL``h]h)}(hjh]jC)}(hjh]hDRM_XE_VM_BIND_OP_UNMAP_ALL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjrubh)}(h``DRM_XE_VM_BIND_OP_PREFETCH`` h]h)}(h``DRM_XE_VM_BIND_OP_PREFETCH``h]jC)}(hjh]hDRM_XE_VM_BIND_OP_PREFETCH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhjnhMhjubah}(h]h ]h"]h$]h&]uh1hhjrubeh}(h]h ]h"]h$]h&]j j uh1hhjhMhjoubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjGubj)}(hXand the **flags** can be: - ``DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protection - ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to. - ``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings. - ``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP. - ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag is only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. - ``DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET`` - Can be used in combination with ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` to reset madvises when the underlying CPU address space range is unmapped (typically with munmap(2) or brk(2)). The madvise values set with :c:type:`DRM_IOCTL_XE_MADVISE` are reset to the values that were present immediately after the :c:type:`DRM_IOCTL_XE_VM_BIND`. The reset GPU virtual address range is the intersection of the range bound using :c:type:`DRM_IOCTL_XE_VM_BIND` and the virtual CPU address space range unmapped. This functionality is present to mimic the behaviour of CPU address space madvises set using madvise(2), which are typically reset on unmap. h](j)}(hand the **flags** can be:h](hand the }(hj0hhhNhNubj)}(h **flags**h]hflags}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh can be:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM%hj,ubj)}(hhh]h)}(hhh](h)}(h```DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protectionh]h)}(h```DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protectionh](jC)}(h ``DRM_XE_VM_BIND_FLAG_READONLY``h]hDRM_XE_VM_BIND_FLAG_READONLY}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj[ubh@ - Setup the page tables as read-only to ensure write protection}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjWubah}(h]h ]h"]h$]h&]uh1hhjTubh)}(h``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.h]h)}(h``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.h](jC)}(h!``DRM_XE_VM_BIND_FLAG_IMMEDIATE``h]hDRM_XE_VM_BIND_FLAG_IMMEDIATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj~ubah}(h]h ]h"]h$]h&]uh1hhjTubh)}(hX\``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.h]h)}(hX\``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.h](jC)}(h``DRM_XE_VM_BIND_FLAG_NULL``h]hDRM_XE_VM_BIND_FLAG_NULL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhX@ - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjubah}(h]h ]h"]h$]h&]uh1hhjTubh)}(h``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.h]h)}(h``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.h](jC)}(h!``DRM_XE_VM_BIND_FLAG_CHECK_PXP``h]hDRM_XE_VM_BIND_FLAG_CHECK_PXP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjTubh)}(hX``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag is only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ.h]h)}(hX``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag is only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ.h](jC)}(h'``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR``h]h#DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhXk - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag is only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjTubh)}(hX``DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET`` - Can be used in combination with ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` to reset madvises when the underlying CPU address space range is unmapped (typically with munmap(2) or brk(2)). The madvise values set with :c:type:`DRM_IOCTL_XE_MADVISE` are reset to the values that were present immediately after the :c:type:`DRM_IOCTL_XE_VM_BIND`. The reset GPU virtual address range is the intersection of the range bound using :c:type:`DRM_IOCTL_XE_VM_BIND` and the virtual CPU address space range unmapped. This functionality is present to mimic the behaviour of CPU address space madvises set using madvise(2), which are typically reset on unmap. h]h)}(hX``DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET`` - Can be used in combination with ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` to reset madvises when the underlying CPU address space range is unmapped (typically with munmap(2) or brk(2)). The madvise values set with :c:type:`DRM_IOCTL_XE_MADVISE` are reset to the values that were present immediately after the :c:type:`DRM_IOCTL_XE_VM_BIND`. The reset GPU virtual address range is the intersection of the range bound using :c:type:`DRM_IOCTL_XE_VM_BIND` and the virtual CPU address space range unmapped. This functionality is present to mimic the behaviour of CPU address space madvises set using madvise(2), which are typically reset on unmap.h](jC)}(h)``DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET``h]h%DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh# - Can be used in combination with }(hjhhhNhNubjC)}(h'``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR``h]h#DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh to reset madvises when the underlying CPU address space range is unmapped (typically with munmap(2) or brk(2)). The madvise values set with }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_MADVISE`h]jC)}(hjHh]hDRM_IOCTL_XE_MADVISE}(hjJhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjFubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_MADVISEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubhA are reset to the values that were present immediately after the }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]jC)}(hjlh]hDRM_IOCTL_XE_VM_BIND}(hjnhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_VM_BINDuh1hhjehMhjubhS. The reset GPU virtual address range is the intersection of the range bound using }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]jC)}(hjh]hDRM_IOCTL_XE_VM_BIND}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_VM_BINDuh1hhjehMhjubh and the virtual CPU address space range unmapped. This functionality is present to mimic the behaviour of CPU address space madvises set using madvise(2), which are typically reset on unmap.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjehMhjubah}(h]h ]h"]h$]h&]uh1hhjTubeh}(h]h ]h"]h$]h&]j j uh1hhjwhMhjQubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhjPhM%hjGubeh}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubh)}(h**Note**h]j)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM'hj-hhubj)}(hhh](j)}(hX(free(3) may or may not call munmap(2) and/or brk(2), and may thus not invoke autoreset. Neither will stack variables going out of scope. Therefore it's recommended to always explicitly reset the madvises when freeing the memory backing a region used in a :c:type:`DRM_IOCTL_XE_MADVISE` call. - ``DRM_XE_VM_BIND_FLAG_DECOMPRESS`` - Request on-device decompression for a MAP. When set on a MAP bind operation, request the driver schedule an on-device in-place decompression (via the migrate/resolve path) for the GPU mapping created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on other ops is rejected. The bind's pat_index must select the device's "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that support Flat CCS and the required HW generation XE2+. h](j)}(hAfree(3) may or may not call munmap(2) and/or brk(2), and may thush]hAfree(3) may or may not call munmap(2) and/or brk(2), and may thus}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM2hjubj)}(hhh](jK)}(hnot invoke autoreset. Neither will stack variables going out of scope. Therefore it's recommended to always explicitly reset the madvises when freeing the memory backing a region used in a :c:type:`DRM_IOCTL_XE_MADVISE` call. h]h)}(hnot invoke autoreset. Neither will stack variables going out of scope. Therefore it's recommended to always explicitly reset the madvises when freeing the memory backing a region used in a :c:type:`DRM_IOCTL_XE_MADVISE` call.h](hnot invoke autoreset. Neither will stack variables going out of scope. Therefore it’s recommended to always explicitly reset the madvises when freeing the memory backing a region used in a }(hj hhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_MADVISE`h]jC)}(hjh]hDRM_IOCTL_XE_MADVISE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjDRM_IOCTL_XE_MADVISEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM(hj ubh call.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj0hM(hjubah}(h]h ]h"]h$]h&]uh1jJhj0hM(hjubh)}(hhh]h)}(hX``DRM_XE_VM_BIND_FLAG_DECOMPRESS`` - Request on-device decompression for a MAP. When set on a MAP bind operation, request the driver schedule an on-device in-place decompression (via the migrate/resolve path) for the GPU mapping created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on other ops is rejected. The bind's pat_index must select the device's "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that support Flat CCS and the required HW generation XE2+. h]h)}(hX``DRM_XE_VM_BIND_FLAG_DECOMPRESS`` - Request on-device decompression for a MAP. When set on a MAP bind operation, request the driver schedule an on-device in-place decompression (via the migrate/resolve path) for the GPU mapping created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on other ops is rejected. The bind's pat_index must select the device's "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that support Flat CCS and the required HW generation XE2+.h](jC)}(h"``DRM_XE_VM_BIND_FLAG_DECOMPRESS``h]hDRM_XE_VM_BIND_FLAG_DECOMPRESS}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjHubhX - Request on-device decompression for a MAP. When set on a MAP bind operation, request the driver schedule an on-device in-place decompression (via the migrate/resolve path) for the GPU mapping created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on other ops is rejected. The bind’s pat_index must select the device’s “no-compression” PAT. Only meaningful for VRAM-backed BOs on devices that support Flat CCS and the required HW generation XE2+.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM,hjDubah}(h]h ]h"]h$]h&]uh1hhjAubah}(h]h ]h"]h$]h&]j j uh1hhjdhM,hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM2hjubj)}(hThe **prefetch_mem_region_instance** for ``DRM_XE_VM_BIND_OP_PREFETCH`` can also be: - ``DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC``, which ensures prefetching occurs in the memory region advised by madvise. h](j)}(hTThe **prefetch_mem_region_instance** for ``DRM_XE_VM_BIND_OP_PREFETCH`` can also be:h](hThe }(hjhhhNhNubj)}(h **prefetch_mem_region_instance**h]hprefetch_mem_region_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh for }(hjhhhNhNubjC)}(h``DRM_XE_VM_BIND_OP_PREFETCH``h]hDRM_XE_VM_BIND_OP_PREFETCH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh can also be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM9hj}ubj)}(hhh]h)}(hhh]h)}(hu``DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC``, which ensures prefetching occurs in the memory region advised by madvise. h]h)}(hq``DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC``, which ensures prefetching occurs in the memory region advised by madvise.h](jC)}(h&``DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC``h]h"DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhK, which ensures prefetching occurs in the memory region advised by madvise.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM5hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]j j uh1hhjhM5hjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhjhM9hjubeh}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_vm_bind (C struct)c.drm_xe_vm_bindhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_vm_bindh]jg)}(hstruct drm_xe_vm_bindh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM;ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhM;ubj)}(hdrm_xe_vm_bindh]j)}(hj h]hdrm_xe_vm_bind}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM;ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj hhhjhM;ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhM;hjhhubj)}(hhh]h)}(h'Input of :c:type:`DRM_IOCTL_XE_VM_BIND`h](h Input of }(hjThhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]jC)}(hj^h]hDRM_IOCTL_XE_VM_BIND}(hj`hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj\ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jj sbc.drm_xe_vm_bindasbjDRM_IOCTL_XE_VM_BINDuh1hhjhKhjTubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjQhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM;ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``vm_id`` The ID of the VM to bind to ``exec_queue_id`` exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used. ``pad`` MBZ ``num_binds`` number of binds in this IOCTL ``{unnamed_union}`` anonymous ``bind`` used if num_binds == 1 ``vector_of_binds`` userptr to array of struct drm_xe_vm_bind_op if num_binds > 1 ``pad2`` MBZ ``num_syncs`` amount of syncs to wait on ``syncs`` pointer to struct drm_xe_sync array ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hX$struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; };h]hX$struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h&``vm_id`` The ID of the VM to bind to h](j)}(h ``vm_id``h]jC)}(hj h]hvm_id}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hThe ID of the VM to bind toh]hThe ID of the VM to bind to}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5hMhjubj)}(h``exec_queue_id`` exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used. h](j)}(h``exec_queue_id``h]jC)}(hjYh]h exec_queue_id}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjWubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjSubj)}(hhh]h)}(hexec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used.h]hexec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h,``num_binds`` number of binds in this IOCTL h](j)}(h ``num_binds``h]jC)}(hjh]h num_binds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hnumber of binds in this IOCTLh]hnumber of binds in this IOCTL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]jC)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h ``bind`` used if num_binds == 1 h](j)}(h``bind``h]jC)}(hj>h]hbind}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj<ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj8ubj)}(hhh]h)}(hused if num_binds == 1h]hused if num_binds == 1}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMhjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhjShMhjubj)}(hR``vector_of_binds`` userptr to array of struct drm_xe_vm_bind_op if num_binds > 1 h](j)}(h``vector_of_binds``h]jC)}(hjwh]hvector_of_binds}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjuubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjqubj)}(hhh]h)}(h=userptr to array of struct drm_xe_vm_bind_op if num_binds > 1h]h=userptr to array of struct drm_xe_vm_bind_op if num_binds > 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]jC)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h)``num_syncs`` amount of syncs to wait on h](j)}(h ``num_syncs``h]jC)}(hjh]h num_syncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hamount of syncs to wait onh]hamount of syncs to wait on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h.``syncs`` pointer to struct drm_xe_sync array h](j)}(h ``syncs``h]jC)}(hj#h]hsyncs}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj!ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h#pointer to struct drm_xe_sync arrayh]h#pointer to struct drm_xe_sync array}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj8hMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hj\h]hreserved}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjZubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjVubj)}(hhh]h)}(hReservedh]hReserved}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjqhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hXBelow is an example of a minimal use of :c:type:`struct drm_xe_vm_bind ` to asynchronously bind the buffer `data` at address `BIND_ADDRESS` to illustrate `userptr`. It can be synchronized by using the example provided for :c:type:`struct drm_xe_sync `.h](h(Below is an example of a minimal use of }(hjhhhNhNubh)}(h0:c:type:`struct drm_xe_vm_bind `h]jC)}(hjh]hstruct drm_xe_vm_bind}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_vm_binduh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh# to asynchronously bind the buffer }(hjhhhNhNubj )}(h`data`h]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh at address }(hjhhhNhNubj )}(h`BIND_ADDRESS`h]h BIND_ADDRESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh to illustrate }(hjhhhNhNubj )}(h `userptr`h]huserptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh;. It can be synchronized by using the example provided for }(hjhhhNhNubh)}(h*:c:type:`struct drm_xe_sync `h]jC)}(hjh]hstruct drm_xe_sync}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_xe_syncuh1hhjhMhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhj-hhubj)}(hXdata = aligned_alloc(ALIGNMENT, BO_SIZE); struct drm_xe_vm_bind bind = { .vm_id = vm, .num_binds = 1, .bind.obj = 0, .bind.obj_offset = to_user_pointer(data), .bind.range = BO_SIZE, .bind.addr = BIND_ADDRESS, .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, .bind.flags = 0, .num_syncs = 1, .syncs = &sync, .exec_queue_id = 0, }; ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);h]hXdata = aligned_alloc(ALIGNMENT, BO_SIZE); struct drm_xe_vm_bind bind = { .vm_id = vm, .num_binds = 1, .bind.obj = 0, .bind.obj_offset = to_user_pointer(data), .bind.range = BO_SIZE, .bind.addr = BIND_ADDRESS, .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, .bind.flags = 0, .num_syncs = 1, .syncs = &sync, .exec_queue_id = 0, }; ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);}hj@sbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW!drm_xe_vm_get_property (C struct)c.drm_xe_vm_get_propertyhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_vm_get_propertyh]jg)}(hstruct drm_xe_vm_get_propertyh](jm)}(hjph]hstruct}(hjihhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjehhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjehhhjvhMubj)}(hdrm_xe_vm_get_propertyh]j)}(hjch]hdrm_xe_vm_get_property}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjehhhjvhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjahhhjvhMubah}(h]j\ah ](jjeh"]h$]h&]jj)jhuh1j`hjvhMhj^hhubj)}(hhh]h)}(h/Input of :c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY`h](h Input of }(hjhhhNhNubh)}(h&:c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY`h]jC)}(hjh]hDRM_IOCTL_XE_VM_GET_PROPERTY}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjcsbc.drm_xe_vm_get_propertyasbjDRM_IOCTL_XE_VM_GET_PROPERTYuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj^hhhjvhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_vm_get_property { __u64 extensions; __u32 vm_id; #define DRM_XE_VM_GET_PROPERTY_FAULTS 0; __u32 property; __u32 size; __u32 pad; union { __u64 data; __u64 value; }; __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``vm_id`` The ID of the VM to query the properties of ``property`` property to get ``size`` Size to allocate for **data** ``pad`` MBZ ``{unnamed_union}`` anonymous ``data`` Pointer to user-defined array of flexible size and type ``value`` Return value for scalar queries ``reserved`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hXstruct drm_xe_vm_get_property { __u64 extensions; __u32 vm_id; #define DRM_XE_VM_GET_PROPERTY_FAULTS 0; __u32 property; __u32 size; __u32 pad; union { __u64 data; __u64 value; }; __u64 reserved[3]; };h]hXstruct drm_xe_vm_get_property { __u64 extensions; __u32 vm_id; #define DRM_XE_VM_GET_PROPERTY_FAULTS 0; __u32 property; __u32 size; __u32 pad; union { __u64 data; __u64 value; }; __u64 reserved[3]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM,hjubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj>h]h extensions}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj<ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM3hj8ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShM3hjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhjShM3hj5ubj)}(h6``vm_id`` The ID of the VM to query the properties of h](j)}(h ``vm_id``h]jC)}(hjwh]hvm_id}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjuubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM6hjqubj)}(hhh]h)}(h+The ID of the VM to query the properties ofh]h+The ID of the VM to query the properties of}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM6hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhjhM6hj5ubj)}(h``property`` property to get h](j)}(h ``property``h]jC)}(hjh]hproperty}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM:hjubj)}(hhh]h)}(hproperty to geth]hproperty to get}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM:hj5ubj)}(h'``size`` Size to allocate for **data** h](j)}(h``size``h]jC)}(hjh]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM=hjubj)}(hhh]h)}(hSize to allocate for **data**h](hSize to allocate for }(hjhhhNhNubj)}(h**data**h]hdata}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM=hj5ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hj0h]hpad}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj.ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM@hj*ubj)}(hhh]h)}(hMBZh]hMBZ}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhM@hjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhjEhM@hj5ubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]jC)}(hjih]h{unnamed_union}}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjgubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjcubj)}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhj~hKhj5ubj)}(hA``data`` Pointer to user-defined array of flexible size and type h](j)}(h``data``h]jC)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMDhjubj)}(hhh]h)}(h7Pointer to user-defined array of flexible size and typeh]h7Pointer to user-defined array of flexible size and type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMDhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMDhj5ubj)}(h*``value`` Return value for scalar queries h](j)}(h ``value``h]jC)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMFhjubj)}(hhh]h)}(hReturn value for scalar queriesh]hReturn value for scalar queries}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMFhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMFhj5ubj)}(h``reserved`` MBZh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMIhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMJhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj)hMIhj5ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjWh]h Description}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMMhj-hhubh)}(hThe user provides a VM and a property to query among DRM_XE_VM_GET_PROPERTY_*, and sets the values in the vm_id and property members, respectively. This determines both the VM to get the property of, as well as the property to report.h]hThe user provides a VM and a property to query among DRM_XE_VM_GET_PROPERTY_*, and sets the values in the vm_id and property members, respectively. This determines both the VM to get the property of, as well as the property to report.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hXIf size is set to 0, the driver fills it with the required size for the requested property. The user is expected here to allocate memory for the property structure and to provide a pointer to the allocated memory using the data member. For some properties, this may be zero, in which case, the value of the property will be saved to the value member and size will remain zero on return.h]hXIf size is set to 0, the driver fills it with the required size for the requested property. The user is expected here to allocate memory for the property structure and to provide a pointer to the allocated memory using the data member. For some properties, this may be zero, in which case, the value of the property will be saved to the value member and size will remain zero on return.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(heIf size is not zero, then the IOCTL will attempt to copy the requested property into the data member.h]heIf size is not zero, then the IOCTL will attempt to copy the requested property into the data member.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM%hj-hhubh)}(hXThe IOCTL will return -ENOENT if the VM could not be identified from the provided VM ID, or -EINVAL if the IOCTL fails for any other reason, such as providing an invalid size for the given property or if the property data could not be copied to the memory allocated to the data member.h]hXThe IOCTL will return -ENOENT if the VM could not be identified from the provided VM ID, or -EINVAL if the IOCTL fails for any other reason, such as providing an invalid size for the given property or if the property data could not be copied to the memory allocated to the data member.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM(hj-hhubj)}(hhh]j)}(hCThe property member can be: - ``DRM_XE_VM_GET_PROPERTY_FAULTS`` h](j)}(hThe property member can be:h]hThe property member can be:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM1hjubj)}(hhh]h)}(hhh]h)}(h%``DRM_XE_VM_GET_PROPERTY_FAULTS`` h]h)}(h!``DRM_XE_VM_GET_PROPERTY_FAULTS``h]jC)}(hjh]hDRM_XE_VM_GET_PROPERTY_FAULTS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM.hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]j j uh1hhjhM.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM1hjubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_xe_exec_queue_create (C struct)c.drm_xe_exec_queue_createhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_exec_queue_createh]jg)}(hstruct drm_xe_exec_queue_createh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM3ubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhj%hM3ubj)}(hdrm_xe_exec_queue_createh]j)}(hjh]hdrm_xe_exec_queue_create}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj%hM3ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhj%hM3ubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j`hj%hM3hj hhubj)}(hhh]h)}(h1Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h](h Input of }(hjZhhhNhNubh)}(h(:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h]jC)}(hjdh]hDRM_IOCTL_XE_EXEC_QUEUE_CREATE}(hjfhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjbubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjsbc.drm_xe_exec_queue_createasbjDRM_IOCTL_XE_EXEC_QUEUE_CREATEuh1hhjhKhjZubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMNhjWhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj%hM3ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4; #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63); #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5; #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``width`` submission width (number BB per exec) for this exec queue ``num_placements`` number of valid placements for this exec queue ``vm_id`` VM to use for this exec queue ``flags`` flags to use for this exec queue ``exec_queue_id`` Returned exec queue ID ``instances`` user pointer to a 2-d array of struct drm_xe_engine_class_instance length = width (i) * num_placements (j) index = j + i * width ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMRhjubj)}(hXZstruct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4; #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63); #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5; #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; };h]hXZstruct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4; #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63); #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5; #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMThjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMihjubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hD``width`` submission width (number BB per exec) for this exec queue h](j)}(h ``width``h]jC)}(hj&h]hwidth}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(h9submission width (number BB per exec) for this exec queueh]h9submission width (number BB per exec) for this exec queue}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhjubj)}(hB``num_placements`` number of valid placements for this exec queue h](j)}(h``num_placements``h]jC)}(hj_h]hnum_placements}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjYubj)}(hhh]h)}(h.number of valid placements for this exec queueh]h.number of valid placements for this exec queue}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMhjuubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jhjthMhjubj)}(h(``vm_id`` VM to use for this exec queue h](j)}(h ``vm_id``h]jC)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hVM to use for this exec queueh]hVM to use for this exec queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h+``flags`` flags to use for this exec queue h](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h flags to use for this exec queueh]h flags to use for this exec queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h)``exec_queue_id`` Returned exec queue ID h](j)}(h``exec_queue_id``h]jC)}(hj h]h exec_queue_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReturned exec queue IDh]hReturned exec queue ID}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``instances`` user pointer to a 2-d array of struct drm_xe_engine_class_instance length = width (i) * num_placements (j) index = j + i * width h](j)}(h ``instances``h]jC)}(hjCh]h instances}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj=ubj)}(hhh](h)}(hBuser pointer to a 2-d array of struct drm_xe_engine_class_instanceh]hBuser pointer to a 2-d array of struct drm_xe_engine_class_instance}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjYubh)}(h=length = width (i) * num_placements (j) index = j + i * widthh]h=length = width (i) * num_placements (j) index = j + i * width}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjYubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhjXhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hThis ioctl supports setting the following properties via the ``DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY`` extension, which uses the generic :c:type:`struct drm_xe_ext_set_property `:h](h=This ioctl supports setting the following properties via the }(hjhhhNhNubjC)}(h,``DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY``h]h(DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh# extension, which uses the generic }(hjhhhNhNubh)}(hB:c:type:`struct drm_xe_ext_set_property `h]jC)}(hjh]hstruct drm_xe_ext_set_property}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_ext_set_propertyuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMOhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMOhj-hhubjK)}(hX- ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``DRM_XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if it isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP`` - Create a multi-queue group or add secondary queues to a multi-queue group. If the extension's 'value' field has ``DRM_XE_MULTI_GROUP_CREATE`` flag set, then a new multi-queue group is created with this queue as the primary queue (Q0). Otherwise, the queue gets added to the multi-queue group whose primary queue's exec_queue_id is specified in the lower 32 bits of the 'value' field. All the other non-relevant bits of extension's 'value' field while adding the primary or the secondary queues of the group must be set to 0. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY`` - Set the queue priority within the multi-queue group. Current valid priority values are 0–2 (default is 1), with higher values indicating higher priority. - ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX`` - Set the queue to enable render color cache keying on BTP+BTI instead of just BTI (only valid for render queues). h]h)}(hhh](h)}(h{``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal.h]h)}(h{``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal.h](jC)}(h+``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY``h]h'DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj4ubhP - set the queue priority. CAP_SYS_NICE is required to set a value above normal.}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMShj0ubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(h```DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds.h]h)}(h```DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds.h](jC)}(h,``DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE``h]h(DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj[ubh4 - set the queue timeslice duration in microseconds.}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMUhjWubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(hX``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``DRM_XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if it isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs.h]h)}(hX``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``DRM_XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if it isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs.h](jC)}(h+``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE``h]h'DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhv - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. }(hjhhhNhNubjC)}(h``DRM_XE_PXP_TYPE_NONE``h]hDRM_XE_PXP_TYPE_NONE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh[ is the default behavior, so there is no need to explicitly set that. When a queue of type }(hjhhhNhNubjC)}(h``DRM_XE_PXP_TYPE_HWDRM``h]hDRM_XE_PXP_TYPE_HWDRM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh, is created, the PXP default HWDRM session (}(hjhhhNhNubjC)}(h$``DRM_XE_PXP_HWDRM_DEFAULT_SESSION``h]h DRM_XE_PXP_HWDRM_DEFAULT_SESSION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhx) will be started, if it isn’t already running. The user is expected to query the PXP status via the query ioctl (see }(hjhhhNhNubjC)}(h"``DRM_XE_DEVICE_QUERY_PXP_STATUS``h]hDRM_XE_DEVICE_QUERY_PXP_STATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhX) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMWhj~ubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(hX=``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP`` - Create a multi-queue group or add secondary queues to a multi-queue group. If the extension's 'value' field has ``DRM_XE_MULTI_GROUP_CREATE`` flag set, then a new multi-queue group is created with this queue as the primary queue (Q0). Otherwise, the queue gets added to the multi-queue group whose primary queue's exec_queue_id is specified in the lower 32 bits of the 'value' field. All the other non-relevant bits of extension's 'value' field while adding the primary or the secondary queues of the group must be set to 0.h]h)}(hX=``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP`` - Create a multi-queue group or add secondary queues to a multi-queue group. If the extension's 'value' field has ``DRM_XE_MULTI_GROUP_CREATE`` flag set, then a new multi-queue group is created with this queue as the primary queue (Q0). Otherwise, the queue gets added to the multi-queue group whose primary queue's exec_queue_id is specified in the lower 32 bits of the 'value' field. All the other non-relevant bits of extension's 'value' field while adding the primary or the secondary queues of the group must be set to 0.h](jC)}(h.``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP``h]h*DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhy - Create a multi-queue group or add secondary queues to a multi-queue group. If the extension’s ‘value’ field has }(hjhhhNhNubjC)}(h``DRM_XE_MULTI_GROUP_CREATE``h]hDRM_XE_MULTI_GROUP_CREATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubhX flag set, then a new multi-queue group is created with this queue as the primary queue (Q0). Otherwise, the queue gets added to the multi-queue group whose primary queue’s exec_queue_id is specified in the lower 32 bits of the ‘value’ field. All the other non-relevant bits of extension’s ‘value’ field while adding the primary or the secondary queues of the group must be set to 0.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMehjubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(h``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY`` - Set the queue priority within the multi-queue group. Current valid priority values are 0–2 (default is 1), with higher values indicating higher priority.h]h)}(h``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY`` - Set the queue priority within the multi-queue group. Current valid priority values are 0–2 (default is 1), with higher values indicating higher priority.h](jC)}(h7``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY``h]h3DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj*ubh - Set the queue priority within the multi-queue group. Current valid priority values are 0–2 (default is 1), with higher values indicating higher priority.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMmhj&ubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(h``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX`` - Set the queue to enable render color cache keying on BTP+BTI instead of just BTI (only valid for render queues). h]h)}(h``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX`` - Set the queue to enable render color cache keying on BTP+BTI instead of just BTI (only valid for render queues).h](jC)}(h6``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h]h2DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQubhs - Set the queue to enable render color cache keying on BTP+BTI instead of just BTI (only valid for render queues).}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMphjMubah}(h]h ]h"]h$]h&]uh1hhj-ubeh}(h]h ]h"]h$]h&]j j uh1hhjPhMShj)ubah}(h]h ]h"]h$]h&]uh1jJhjPhMShj-hhubh)}(hThe example below shows how to use :c:type:`struct drm_xe_exec_queue_create ` to create a simple exec_queue (no parallel submission) of class ``DRM_XE_ENGINE_CLASS_RENDER``.h](h#The example below shows how to use }(hjhhhNhNubh)}(hD:c:type:`struct drm_xe_exec_queue_create `h]jC)}(hjh]hstruct drm_xe_exec_queue_create}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_exec_queue_createuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMthjubhA to create a simple exec_queue (no parallel submission) of class }(hjhhhNhNubjC)}(h``DRM_XE_ENGINE_CLASS_RENDER``h]hDRM_XE_ENGINE_CLASS_RENDER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMthj-hhubj)}(hX\struct drm_xe_engine_class_instance instance = { .engine_class = DRM_XE_ENGINE_CLASS_RENDER, }; struct drm_xe_exec_queue_create exec_queue_create = { .extensions = 0, .vm_id = vm, .width = 1, .num_placements = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);h]hX\struct drm_xe_engine_class_instance instance = { .engine_class = DRM_XE_ENGINE_CLASS_RENDER, }; struct drm_xe_exec_queue_create exec_queue_create = { .extensions = 0, .vm_id = vm, .width = 1, .num_placements = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMxhj-hhubh)}(hAllow users to provide a hint to kernel for cases demanding low latency profile. Please note it will have impact on power consumption. User can indicate low latency hint with flag while creating exec queue as mentioned below:h]hAllow users to provide a hint to kernel for cases demanding low latency profile. Please note it will have impact on power consumption. User can indicate low latency hint with flag while creating exec queue as mentioned below:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hX*struct drm_xe_exec_queue_create exec_queue_create = { .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, .extensions = 0, .vm_id = vm, .width = 1, .num_placements = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);h]hX*struct drm_xe_exec_queue_create exec_queue_create = { .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, .extensions = 0, .vm_id = vm, .width = 1, .num_placements = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW$drm_xe_exec_queue_destroy (C struct)c.drm_xe_exec_queue_destroyhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_exec_queue_destroyh]jg)}(h struct drm_xe_exec_queue_destroyh](jm)}(hjph]hstruct}(hj hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj hhhj hMubj)}(hdrm_xe_exec_queue_destroyh]j)}(hj h]hdrm_xe_exec_queue_destroy}(hj, hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj( ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj hhhj hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hj hMhj hhubj)}(hhh]h)}(h2Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY`h](h Input of }(hjN hhhNhNubh)}(h):c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY`h]jC)}(hjX h]hDRM_IOCTL_XE_EXEC_QUEUE_DESTROY}(hjZ hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjV ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jj sbc.drm_xe_exec_queue_destroyasbjDRM_IOCTL_XE_EXEC_QUEUE_DESTROYuh1hhjhKhjN ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjK hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j[hhhj-hNhNubj)}(h**Definition**:: struct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; }; **Members** ``exec_queue_id`` Exec queue ID ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hdstruct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; };h]hdstruct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; };}hj sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh](j)}(h ``exec_queue_id`` Exec queue ID h](j)}(h``exec_queue_id``h]jC)}(hj h]h exec_queue_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(h Exec queue IDh]h Exec queue ID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hj h]hpad}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hMBZh]hMBZ}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/ hMhj0 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj/ hMhj ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjS h]hreserved}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQ ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjM ubj)}(hhh]h)}(hReservedh]hReserved}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhji ubah}(h]h ]h"]h$]h&]uh1jhjM ubeh}(h]h ]h"]h$]h&]uh1jhjh hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW)drm_xe_exec_queue_get_property (C struct) c.drm_xe_exec_queue_get_propertyhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_exec_queue_get_propertyh]jg)}(h%struct drm_xe_exec_queue_get_propertyh](jm)}(hjph]hstruct}(hj hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj hhhj hMubj)}(hdrm_xe_exec_queue_get_propertyh]j)}(hj h]hdrm_xe_exec_queue_get_property}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj hhhj hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j`hj hMhj hhubj)}(hhh]h)}(h7Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY`h](h Input of }(hj hhhNhNubh)}(h.:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY`h]jC)}(hj h]h$DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY}(hj hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jj sb c.drm_xe_exec_queue_get_propertyasbj$DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTYuh1hhjhKhj ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jstructeh"]h$]h&]jjjj- jj- jjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``exec_queue_id`` Exec queue ID ``property`` property to get ``value`` property value ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5 ubh:}(hj5 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj1 ubj)}(hstruct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; };h]hstruct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; };}hjR sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj1 ubh)}(h **Members**h]j)}(hjc h]hMembers}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj1 ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj h]h extensions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj| ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj| ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjy ubj)}(h ``exec_queue_id`` Exec queue ID h](j)}(h``exec_queue_id``h]jC)}(hj h]h exec_queue_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(h Exec queue IDh]h Exec queue ID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjy ubj)}(h``property`` property to get h](j)}(h ``property``h]jC)}(hj h]hproperty}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hproperty to geth]hproperty to get}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjy ubj)}(h``value`` property value h](j)}(h ``value``h]jC)}(hj- h]hvalue}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj+ ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj' ubj)}(hhh]h)}(hproperty valueh]hproperty value}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB hMhjC ubah}(h]h ]h"]h$]h&]uh1jhj' ubeh}(h]h ]h"]h$]h&]uh1jhjB hMhjy ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjf h]hreserved}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjd ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj` ubj)}(hhh]h)}(hReservedh]hReserved}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj| ubah}(h]h ]h"]h$]h&]uh1jhj` ubeh}(h]h ]h"]h$]h&]uh1jhj{ hMhjy ubeh}(h]h ]h"]h$]h&]uh1jhj1 ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hhh]j)}(hEThe **property** can be: - ``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN`` h](j)}(hThe **property** can be:h](hThe }(hj hhhNhNubj)}(h **property**h]hproperty}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh can be:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hhh]h)}(h*``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN`` h]h)}(h&``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN``h]jC)}(hj h]h"DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]j j uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_sync (C struct) c.drm_xe_synchNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(h drm_xe_synch]jg)}(hstruct drm_xe_synch](jm)}(hjph]hstruct}(hj@ hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj< hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjN hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj< hhhjM hMubj)}(h drm_xe_synch]j)}(hj: h]h drm_xe_sync}(hj` hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj< hhhjM hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj8 hhhjM hMubah}(h]j3 ah ](jjeh"]h$]h&]jj)jhuh1j`hjM hMhj5 hhubj)}(hhh]h)}(h sync objecth]h sync object}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhj5 hhhjM hMubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j[hhhj-hNhNubj)}(hXr**Definition**:: struct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``type`` Type of this sync object ``flags`` Sync Flags ``{unnamed_union}`` anonymous ``handle`` Handle for the object ``addr`` Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync is passed in via VM bind IOCTL this is a user pointer. In either case, it is the user's responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned. ``timeline_value`` Input for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``. ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hXstruct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; };h]hXstruct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; };}hj sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj h]h extensions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h"``type`` Type of this sync object h](j)}(h``type``h]jC)}(hj(h]htype}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj&ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj"ubj)}(hhh]h)}(hType of this sync objecth]hType of this sync object}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMhj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj ubj)}(h``flags`` Sync Flags h](j)}(h ``flags``h]jC)}(hjah]hflags}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj_ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj[ubj)}(hhh]h)}(h Sync Flagsh]h Sync Flags}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhjvhMhj ubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]jC)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj ubj)}(h!``handle`` Handle for the object h](j)}(h ``handle``h]jC)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hHandle for the objecth]hHandle for the object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(hX9``addr`` Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync is passed in via VM bind IOCTL this is a user pointer. In either case, it is the user's responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned. h](j)}(h``addr``h]jC)}(hj h]haddr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM%hjubj)}(hhh]h)}(hX/Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync is passed in via VM bind IOCTL this is a user pointer. In either case, it is the user's responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned.h]hX1Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync is passed in via VM bind IOCTL this is a user pointer. In either case, it is the user’s responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj!hM%hj ubj)}(h``timeline_value`` Input for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``. h](j)}(h``timeline_value``h]jC)}(hjFh]htimeline_value}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjDubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM,hj@ubj)}(hhh]h)}(hvInput for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``.h](hPInput for the timeline sync object. Needs to be different than 0 when used with }(hj_hhhNhNubjC)}(h%``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``h]h!DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj_ubh.}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM+hj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj[hM,hj ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM/hjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM/hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM3hj-hhubj)}(hhh](j)}(h~The **type** can be: - ``DRM_XE_SYNC_TYPE_SYNCOBJ`` - ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ`` - ``DRM_XE_SYNC_TYPE_USER_FENCE`` h](j)}(hThe **type** can be:h](hThe }(hjhhhNhNubj)}(h**type**h]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hhh](h)}(h``DRM_XE_SYNC_TYPE_SYNCOBJ``h]h)}(hjh]jC)}(hjh]hDRM_XE_SYNC_TYPE_SYNCOBJ}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h%``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``h]h)}(hj<h]jC)}(hj<h]h!DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj:ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h ``DRM_XE_SYNC_TYPE_USER_FENCE`` h]h)}(h``DRM_XE_SYNC_TYPE_USER_FENCE``h]jC)}(hjah]hDRM_XE_SYNC_TYPE_USER_FENCE}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj_ubah}(h]h ]h"]h$]h&]uh1hhjhMhj[ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j j uh1hhj3hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h8and the **flags** can be: - ``DRM_XE_SYNC_FLAG_SIGNAL`` h](j)}(hand the **flags** can be:h](hand the }(hjhhhNhNubj)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hhh]h)}(h``DRM_XE_SYNC_FLAG_SIGNAL`` h]h)}(h``DRM_XE_SYNC_FLAG_SIGNAL``h]jC)}(hjh]hDRM_XE_SYNC_FLAG_SIGNAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]j j uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubh)}(hLA minimal use of :c:type:`struct drm_xe_sync ` looks like this:h](hA minimal use of }(hjhhhNhNubh)}(h*:c:type:`struct drm_xe_sync `h]jC)}(hjh]hstruct drm_xe_sync}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_xe_syncuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh looks like this:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhj-hhubj)}(hXstruct drm_xe_sync sync = { .flags = DRM_XE_SYNC_FLAG_SIGNAL, .type = DRM_XE_SYNC_TYPE_SYNCOBJ, }; struct drm_syncobj_create syncobj_create = { 0 }; ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); sync.handle = syncobj_create.handle; ... use of &sync in drm_xe_exec or drm_xe_vm_bind ... struct drm_syncobj_wait wait = { .handles = &sync.handle, .timeout_nsec = INT64_MAX, .count_handles = 1, .flags = 0, .first_signaled = 0, .pad = 0, }; ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);h]hXstruct drm_xe_sync sync = { .flags = DRM_XE_SYNC_FLAG_SIGNAL, .type = DRM_XE_SYNC_TYPE_SYNCOBJ, }; struct drm_syncobj_create syncobj_create = { 0 }; ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); sync.handle = syncobj_create.handle; ... use of &sync in drm_xe_exec or drm_xe_vm_bind ... struct drm_syncobj_wait wait = { .handles = &sync.handle, .timeout_nsec = INT64_MAX, .count_handles = 1, .flags = 0, .first_signaled = 0, .pad = 0, }; ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);}hj$sbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_exec (C struct) c.drm_xe_exechNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(h drm_xe_exech]jg)}(hstruct drm_xe_exech](jm)}(hjph]hstruct}(hjMhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjIhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjIhhhjZhMubj)}(h drm_xe_exech]j)}(hjGh]h drm_xe_exec}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubah}(h]h ](jjeh"]h$]h&]jjuh1jhjIhhhjZhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjEhhhjZhMubah}(h]j@ah ](jjeh"]h$]h&]jj)jhuh1j`hjZhMhjBhhubj)}(hhh]h)}(h$Input of :c:type:`DRM_IOCTL_XE_EXEC`h](h Input of }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_EXEC`h]jC)}(hjh]hDRM_IOCTL_XE_EXEC}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjGsb c.drm_xe_execasbjDRM_IOCTL_XE_EXECuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM4hjhhubah}(h]h ]h"]h$]h&]uh1jhjBhhhjZhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_MAX_SYNCS 1024; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``exec_queue_id`` Exec queue ID for the batch buffer ``num_syncs`` Amount of struct drm_xe_sync in array. ``syncs`` Pointer to struct drm_xe_sync array. ``address`` address of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses ``num_batch_buffer`` number of batch buffer in this exec, must match the width of the engine ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM8hjubj)}(hstruct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_MAX_SYNCS 1024; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; };h]hstruct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_MAX_SYNCS 1024; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM:hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMFhjubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj"h]h extensions}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMIhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMIhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj7hMIhjubj)}(h5``exec_queue_id`` Exec queue ID for the batch buffer h](j)}(h``exec_queue_id``h]jC)}(hj[h]h exec_queue_id}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjYubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMLhjUubj)}(hhh]h)}(h"Exec queue ID for the batch bufferh]h"Exec queue ID for the batch buffer}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphMLhjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjphMLhjubj)}(h5``num_syncs`` Amount of struct drm_xe_sync in array. h](j)}(h ``num_syncs``h]jC)}(hjh]h num_syncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMPhjubj)}(hhh]h)}(h&Amount of struct drm_xe_sync in array.h]h&Amount of struct drm_xe_sync in array.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMPhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMPhjubj)}(h/``syncs`` Pointer to struct drm_xe_sync array. h](j)}(h ``syncs``h]jC)}(hjh]hsyncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMShjubj)}(hhh]h)}(h$Pointer to struct drm_xe_sync array.h]h$Pointer to struct drm_xe_sync array.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMShjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMShjubj)}(hc``address`` address of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses h](j)}(h ``address``h]jC)}(hjh]haddress}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMXhjubj)}(hhh]h)}(hVaddress of batch buffer if num_batch_buffer == 1 or an array of batch buffer addressesh]hVaddress of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMXhjubj)}(h]``num_batch_buffer`` number of batch buffer in this exec, must match the width of the engine h](j)}(h``num_batch_buffer``h]jC)}(hj@h]hnum_batch_buffer}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM^hj:ubj)}(hhh]h)}(hGnumber of batch buffer in this exec, must match the width of the engineh]hGnumber of batch buffer in this exec, must match the width of the engine}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM]hjVubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhjUhM^hjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjzh]hpad}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjxubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMbhjtubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMbhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjhMbhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMdhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMehjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMdhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhhj-hhubh)}(hXThis is an example to use :c:type:`struct drm_xe_exec ` for execution of the object at BIND_ADDRESS (see example in :c:type:`struct drm_xe_vm_bind `) by an exec_queue (see example in :c:type:`struct drm_xe_exec_queue_create `). It can be synchronized by using the example provided for :c:type:`struct drm_xe_sync `.h](hThis is an example to use }(hj hhhNhNubh)}(h*:c:type:`struct drm_xe_exec `h]jC)}(hjh]hstruct drm_xe_exec}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_xe_execuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM5hj ubh= for execution of the object at BIND_ADDRESS (see example in }(hj hhhNhNubh)}(h0:c:type:`struct drm_xe_vm_bind `h]jC)}(hj:h]hstruct drm_xe_vm_bind}(hj<hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj8ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_vm_binduh1hhj3hM5hj ubh#) by an exec_queue (see example in }(hj hhhNhNubh)}(hD:c:type:`struct drm_xe_exec_queue_create `h]jC)}(hj]h]hstruct drm_xe_exec_queue_create}(hj_hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj[ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_exec_queue_createuh1hhj3hM5hj ubh<). It can be synchronized by using the example provided for }(hj hhhNhNubh)}(h*:c:type:`struct drm_xe_sync `h]jC)}(hjh]hstruct drm_xe_sync}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj~ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_xe_syncuh1hhj3hM5hj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj3hM5hj-hhubj)}(hstruct drm_xe_exec exec = { .exec_queue_id = exec_queue, .syncs = &sync, .num_syncs = 1, .address = BIND_ADDRESS, .num_batch_buffer = 1, }; ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);h]hstruct drm_xe_exec exec = { .exec_queue_id = exec_queue, .syncs = &sync, .num_syncs = 1, .address = BIND_ADDRESS, .num_batch_buffer = 1, }; ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM:hj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW!drm_xe_wait_user_fence (C struct)c.drm_xe_wait_user_fencehNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_wait_user_fenceh]jg)}(hstruct drm_xe_wait_user_fenceh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMHubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMHubj)}(hdrm_xe_wait_user_fenceh]j)}(hjh]hdrm_xe_wait_user_fence}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMHubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMHubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMHhjhhubj)}(hhh]h)}(h/Input of :c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE`h](h Input of }(hjhhhNhNubh)}(h&:c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE`h]jC)}(hjh]hDRM_IOCTL_XE_WAIT_USER_FENCE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjsbc.drm_xe_wait_user_fenceasbjDRM_IOCTL_XE_WAIT_USER_FENCEuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMihjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMHubeh}(h]h ](jstructeh"]h$]h&]jjjjPjjPjjjuh1j[hhhj-hNhNubj)}(hXy**Definition**:: struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``addr`` user pointer address to wait on, must be qword aligned ``op`` wait operation (type of comparison) ``flags`` wait flags ``pad`` MBZ ``value`` compare value ``mask`` comparison mask ``timeout`` how long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag is set (absolute timeout) wait will end at timeout (uses system CLOCK_MONOTONIC). Passing negative timeout leads to never ending wait. On relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time). ``exec_queue_id`` exec_queue_id returned from xe_exec_queue_create_ioctl ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh:}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMmhjTubj)}(hX*struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; };h]hX*struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; };}hjusbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMohjTubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjTubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h@``addr`` user pointer address to wait on, must be qword aligned h](j)}(h``addr``h]jC)}(hjh]haddr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h6user pointer address to wait on, must be qword alignedh]h6user pointer address to wait on, must be qword aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h+``op`` wait operation (type of comparison) h](j)}(h``op``h]jC)}(hjh]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h#wait operation (type of comparison)h]h#wait operation (type of comparison)}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj,hMhjubj)}(h``flags`` wait flags h](j)}(h ``flags``h]jC)}(hjPh]hflags}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjJubj)}(hhh]h)}(h wait flagsh]h wait flags}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMhjfubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjehMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``value`` compare value h](j)}(h ``value``h]jC)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h compare valueh]h compare value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``mask`` comparison mask h](j)}(h``mask``h]jC)}(hjh]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hcomparison maskh]hcomparison mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hXm``timeout`` how long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag is set (absolute timeout) wait will end at timeout (uses system CLOCK_MONOTONIC). Passing negative timeout leads to never ending wait. On relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time). h](j)}(h ``timeout``h]jC)}(hj4h]htimeout}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj2ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj.ubj)}(hhh](h)}(hXhow long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag is set (absolute timeout) wait will end at timeout (uses system CLOCK_MONOTONIC). Passing negative timeout leads to never ending wait.h]hXhow long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag is set (absolute timeout) wait will end at timeout (uses system CLOCK_MONOTONIC). Passing negative timeout leads to never ending wait.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjJubh)}(hOn relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time).h]hOn relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time).}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjJubeh}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhjIhMhjubj)}(hI``exec_queue_id`` exec_queue_id returned from xe_exec_queue_create_ioctl h](j)}(h``exec_queue_id``h]jC)}(hj}h]h exec_queue_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj{ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjwubj)}(hhh]h)}(h6exec_queue_id returned from xe_exec_queue_create_ioctlh]h6exec_queue_id returned from xe_exec_queue_create_ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]jC)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj2h]h Description}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(h|Wait on user fence, XE will wake-up on every HW engine interrupt in the instances list and check if user fence is complete::h]h{Wait on user fence, XE will wake-up on every HW engine interrupt in the instances list and check if user fence is complete:}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMjhj-hhubj)}(h (*addr & MASK) OP (VALUE & MASK)h]h (*addr & MASK) OP (VALUE & MASK)}hjWsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMmhj-hhubh)}(h4Returns to user on user fence completion or timeout.h]h4Returns to user on user fence completion or timeout.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMohj-hhubj)}(hhh](j)}(hThe **op** can be: - ``DRM_XE_UFENCE_WAIT_OP_EQ`` - ``DRM_XE_UFENCE_WAIT_OP_NEQ`` - ``DRM_XE_UFENCE_WAIT_OP_GT`` - ``DRM_XE_UFENCE_WAIT_OP_GTE`` - ``DRM_XE_UFENCE_WAIT_OP_LT`` - ``DRM_XE_UFENCE_WAIT_OP_LTE`` h](j)}(hThe **op** can be:h](hThe }(hj|hhhNhNubj)}(h**op**h]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh can be:}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMwhjxubj)}(hhh]h)}(hhh](h)}(h``DRM_XE_UFENCE_WAIT_OP_EQ``h]h)}(hjh]jC)}(hjh]hDRM_XE_UFENCE_WAIT_OP_EQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMrhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_UFENCE_WAIT_OP_NEQ``h]h)}(hjh]jC)}(hjh]hDRM_XE_UFENCE_WAIT_OP_NEQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMshjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_UFENCE_WAIT_OP_GT``h]h)}(hjh]jC)}(hjh]hDRM_XE_UFENCE_WAIT_OP_GT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMthjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_UFENCE_WAIT_OP_GTE``h]h)}(hjh]jC)}(hjh]hDRM_XE_UFENCE_WAIT_OP_GTE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMuhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_UFENCE_WAIT_OP_LT``h]h)}(hj)h]jC)}(hj)h]hDRM_XE_UFENCE_WAIT_OP_LT}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj+ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMvhj'ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h``DRM_XE_UFENCE_WAIT_OP_LTE`` h]h)}(h``DRM_XE_UFENCE_WAIT_OP_LTE``h]jC)}(hjNh]hDRM_XE_UFENCE_WAIT_OP_LTE}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjLubah}(h]h ]h"]h$]h&]uh1hhjhMwhjHubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j j uh1hhjhMrhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjhMwhjuubj)}(h@and the **flags** can be: - ``DRM_XE_UFENCE_WAIT_FLAG_ABSTIME`` h](j)}(hand the **flags** can be:h](hand the }(hjhhhNhNubj)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMzhj{ubj)}(hhh]h)}(hhh]h)}(h$``DRM_XE_UFENCE_WAIT_FLAG_ABSTIME`` h]h)}(h#``DRM_XE_UFENCE_WAIT_FLAG_ABSTIME``h]jC)}(hjh]hDRM_XE_UFENCE_WAIT_FLAG_ABSTIME}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hhjhMzhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]j j uh1hhjhMzhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jhjhMzhjuubj)}(hThe **mask** values can be for example: - 0xffu for u8 - 0xffffu for u16 - 0xffffffffu for u32 - 0xffffffffffffffffu for u64 h](j)}(h'The **mask** values can be for example:h](hThe }(hjhhhNhNubj)}(h**mask**h]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh values can be for example:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hhh](h)}(h 0xffu for u8h]h)}(hjh]h 0xffu for u8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM}hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h0xffffu for u16h]h)}(hjh]h0xffffu for u16}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM~hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h0xffffffffu for u32h]h)}(hj6h]h0xffffffffu for u32}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj4ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h0xffffffffffffffffu for u64 h]h)}(h0xffffffffffffffffu for u64h]h0xffffffffffffffffu for u64}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjLubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]j j uh1hhjhM}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjuubeh}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_xe_observation_type (C enum)c.drm_xe_observation_typehNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_observation_typeh]jg)}(henum drm_xe_observation_typeh](jm)}(hjh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_xe_observation_typeh]j)}(hjh]hdrm_xe_observation_type}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(hObservation stream typesh]hObservation stream types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(h**Constants** ``DRM_XE_OBSERVATION_TYPE_OA`` OA observation stream type ``DRM_XE_OBSERVATION_TYPE_EU_STALL`` EU stall sampling observation stream typeh](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h:``DRM_XE_OBSERVATION_TYPE_OA`` OA observation stream type h](j)}(h``DRM_XE_OBSERVATION_TYPE_OA``h]jC)}(hjh]hDRM_XE_OBSERVATION_TYPE_OA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hOA observation stream typeh]hOA observation stream type}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj.hMhjubj)}(hN``DRM_XE_OBSERVATION_TYPE_EU_STALL`` EU stall sampling observation stream typeh](j)}(h$``DRM_XE_OBSERVATION_TYPE_EU_STALL``h]jC)}(hjRh]h DRM_XE_OBSERVATION_TYPE_EU_STALL}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjPubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjLubj)}(hhh]h)}(h)EU stall sampling observation stream typeh]h)EU stall sampling observation stream type}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jhjghMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_observation_op (C enum)c.drm_xe_observation_ophNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_observation_oph]jg)}(henum drm_xe_observation_oph](jm)}(hjh]henum}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_xe_observation_oph]j)}(hjh]hdrm_xe_observation_op}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(hObservation stream opsh]hObservation stream ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(h**Constants** ``DRM_XE_OBSERVATION_OP_STREAM_OPEN`` Open an observation stream ``DRM_XE_OBSERVATION_OP_ADD_CONFIG`` Add observation stream config ``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG`` Remove observation stream configh](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh](j)}(hA``DRM_XE_OBSERVATION_OP_STREAM_OPEN`` Open an observation stream h](j)}(h%``DRM_XE_OBSERVATION_OP_STREAM_OPEN``h]jC)}(hj/h]h!DRM_XE_OBSERVATION_OP_STREAM_OPEN}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj)ubj)}(hhh]h)}(hOpen an observation streamh]hOpen an observation stream}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjEubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhjDhMhj&ubj)}(hC``DRM_XE_OBSERVATION_OP_ADD_CONFIG`` Add observation stream config h](j)}(h$``DRM_XE_OBSERVATION_OP_ADD_CONFIG``h]jC)}(hjhh]h DRM_XE_OBSERVATION_OP_ADD_CONFIG}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjfubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjbubj)}(hhh]h)}(hAdd observation stream configh]hAdd observation stream config}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj~ubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj&ubj)}(hH``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG`` Remove observation stream configh](j)}(h'``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG``h]jC)}(hjh]h#DRM_XE_OBSERVATION_OP_REMOVE_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h Remove observation stream configh]h Remove observation stream config}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj&ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_xe_observation_param (C struct)c.drm_xe_observation_paramhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_observation_paramh]jg)}(hstruct drm_xe_observation_paramh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_xe_observation_paramh]j)}(hjh]hdrm_xe_observation_param}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(h+Input of :c:type:`DRM_IOCTL_XE_OBSERVATION`h](h Input of }(hj=hhhNhNubh)}(h":c:type:`DRM_IOCTL_XE_OBSERVATION`h]jC)}(hjGh]hDRM_IOCTL_XE_OBSERVATION}(hjIhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjEubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjsbc.drm_xe_observation_paramasbjDRM_IOCTL_XE_OBSERVATIONuh1hhjhKhj=ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj:hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj{jj{jjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``observation_type`` observation stream type, of :c:type:`enum drm_xe_observation_type ` ``observation_op`` observation stream op, of :c:type:`enum drm_xe_observation_op ` ``param`` Pointer to actual stream paramsh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hstruct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; };h]hstruct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hr``observation_type`` observation stream type, of :c:type:`enum drm_xe_observation_type ` h](j)}(h``observation_type``h]jC)}(hj h]hobservation_type}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h\observation stream type, of :c:type:`enum drm_xe_observation_type `h](hobservation stream type, of }(hj"hhhNhNubh)}(h@:c:type:`enum drm_xe_observation_type `h]jC)}(hj,h]henum drm_xe_observation_type}(hj.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj*ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_observation_typeuh1hhjhMhj"ubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hj``observation_op`` observation stream op, of :c:type:`enum drm_xe_observation_op ` h](j)}(h``observation_op``h]jC)}(hjah]hobservation_op}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj_ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj[ubj)}(hhh]h)}(hVobservation stream op, of :c:type:`enum drm_xe_observation_op `h](hobservation stream op, of }(hjzhhhNhNubh)}(h<:c:type:`enum drm_xe_observation_op `h]jC)}(hjh]henum drm_xe_observation_op}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_observation_opuh1hhjvhMhjzubeh}(h]h ]h"]h$]h&]uh1hhjvhMhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhjvhMhjubj)}(h)``param`` Pointer to actual stream paramsh](j)}(h ``param``h]jC)}(hjh]hparam}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hPointer to actual stream paramsh]hPointer to actual stream params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hThe observation layer enables multiplexing observation streams of multiple types. The actual params for a particular stream operation are supplied via the **param** pointer (use __copy_from_user to get these params).h](hThe observation layer enables multiplexing observation streams of multiple types. The actual params for a particular stream operation are supplied via the }(hjhhhNhNubj)}(h **param**h]hparam}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh4 pointer (use __copy_from_user to get these params).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_xe_observation_ioctls (C enum)c.drm_xe_observation_ioctlshNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_observation_ioctlsh]jg)}(henum drm_xe_observation_ioctlsh](jm)}(hjh]henum}(hjLhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjHhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjHhhhjYhMubj)}(hdrm_xe_observation_ioctlsh]j)}(hjFh]hdrm_xe_observation_ioctls}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubah}(h]h ](jjeh"]h$]h&]jjuh1jhjHhhhjYhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjDhhhjYhMubah}(h]j?ah ](jjeh"]h$]h&]jj)jhuh1j`hjYhMhjAhhubj)}(hhh]h)}(hObservation stream fd ioctlsh]hObservation stream fd ioctls}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjAhhhjYhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j[hhhj-hNhNubj)}(hX**Constants** ``DRM_XE_OBSERVATION_IOCTL_ENABLE`` Enable data capture for an observation stream ``DRM_XE_OBSERVATION_IOCTL_DISABLE`` Disable data capture for an observation stream ``DRM_XE_OBSERVATION_IOCTL_CONFIG`` Change observation stream configuration ``DRM_XE_OBSERVATION_IOCTL_STATUS`` Return observation stream status ``DRM_XE_OBSERVATION_IOCTL_INFO`` Return observation stream infoh](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh](j)}(hR``DRM_XE_OBSERVATION_IOCTL_ENABLE`` Enable data capture for an observation stream h](j)}(h#``DRM_XE_OBSERVATION_IOCTL_ENABLE``h]jC)}(hjh]hDRM_XE_OBSERVATION_IOCTL_ENABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h-Enable data capture for an observation streamh]h-Enable data capture for an observation stream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hT``DRM_XE_OBSERVATION_IOCTL_DISABLE`` Disable data capture for an observation stream h](j)}(h$``DRM_XE_OBSERVATION_IOCTL_DISABLE``h]jC)}(hj h]h DRM_XE_OBSERVATION_IOCTL_DISABLE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(h.Disable data capture for an observation streamh]h.Disable data capture for an observation stream}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(hL``DRM_XE_OBSERVATION_IOCTL_CONFIG`` Change observation stream configuration h](j)}(h#``DRM_XE_OBSERVATION_IOCTL_CONFIG``h]jC)}(hjA h]hDRM_XE_OBSERVATION_IOCTL_CONFIG}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj? ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj; ubj)}(hhh]h)}(h'Change observation stream configurationh]h'Change observation stream configuration}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV hMhjW ubah}(h]h ]h"]h$]h&]uh1jhj; ubeh}(h]h ]h"]h$]h&]uh1jhjV hMhjubj)}(hE``DRM_XE_OBSERVATION_IOCTL_STATUS`` Return observation stream status h](j)}(h#``DRM_XE_OBSERVATION_IOCTL_STATUS``h]jC)}(hjz h]hDRM_XE_OBSERVATION_IOCTL_STATUS}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjx ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjt ubj)}(hhh]h)}(h Return observation stream statush]h Return observation stream status}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjt ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(h@``DRM_XE_OBSERVATION_IOCTL_INFO`` Return observation stream infoh](j)}(h!``DRM_XE_OBSERVATION_IOCTL_INFO``h]jC)}(hj h]hDRM_XE_OBSERVATION_IOCTL_INFO}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hReturn observation stream infoh]hReturn observation stream info}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hdInformation exchanged between userspace and kernel for observation fd ioctls is stream type specifich]hdInformation exchanged between userspace and kernel for observation fd ioctls is stream type specific}(hj !hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_oa_unit_type (C enum)c.drm_xe_oa_unit_typehNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_oa_unit_typeh]jg)}(henum drm_xe_oa_unit_typeh](jm)}(hjh]henum}(hj4!hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj0!hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjB!hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj0!hhhjA!hMubj)}(hdrm_xe_oa_unit_typeh]j)}(hj.!h]hdrm_xe_oa_unit_type}(hjT!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP!ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj0!hhhjA!hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj,!hhhjA!hMubah}(h]j'!ah ](jjeh"]h$]h&]jj)jhuh1j`hjA!hMhj)!hhubj)}(hhh]h)}(h OA unit typesh]h OA unit types}(hjv!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjs!hhubah}(h]h ]h"]h$]h&]uh1jhj)!hhhjA!hMubeh}(h]h ](jenumeh"]h$]h&]jjjj!jj!jjjuh1j[hhhj-hNhNubj)}(hX**Constants** ``DRM_XE_OA_UNIT_TYPE_OAG`` OAG OA unit. OAR/OAC are considered sub-types of OAG. For OAR/OAC, use OAG. ``DRM_XE_OA_UNIT_TYPE_OAM`` OAM OA unit ``DRM_XE_OA_UNIT_TYPE_OAM_SAG`` OAM_SAG OA unit ``DRM_XE_OA_UNIT_TYPE_MERT`` MERT OA unith](h)}(h **Constants**h]j)}(hj!h]h Constants}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj!ubj)}(hhh](j)}(hh``DRM_XE_OA_UNIT_TYPE_OAG`` OAG OA unit. OAR/OAC are considered sub-types of OAG. For OAR/OAC, use OAG. h](j)}(h``DRM_XE_OA_UNIT_TYPE_OAG``h]jC)}(hj!h]hDRM_XE_OA_UNIT_TYPE_OAG}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj!ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj!ubj)}(hhh]h)}(hKOAG OA unit. OAR/OAC are considered sub-types of OAG. For OAR/OAC, use OAG.h]hKOAG OA unit. OAR/OAC are considered sub-types of OAG. For OAR/OAC, use OAG.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMhj!ubj)}(h(``DRM_XE_OA_UNIT_TYPE_OAM`` OAM OA unit h](j)}(h``DRM_XE_OA_UNIT_TYPE_OAM``h]jC)}(hj!h]hDRM_XE_OA_UNIT_TYPE_OAM}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj!ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj!ubj)}(hhh]h)}(h OAM OA unith]h OAM OA unit}(hj "hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hj!ubj)}(h0``DRM_XE_OA_UNIT_TYPE_OAM_SAG`` OAM_SAG OA unit h](j)}(h``DRM_XE_OA_UNIT_TYPE_OAM_SAG``h]jC)}(hj*"h]hDRM_XE_OA_UNIT_TYPE_OAM_SAG}(hj,"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj("ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj$"ubj)}(hhh]h)}(hOAM_SAG OA unith]hOAM_SAG OA unit}(hjC"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?"hM hj@"ubah}(h]h ]h"]h$]h&]uh1jhj$"ubeh}(h]h ]h"]h$]h&]uh1jhj?"hM hj!ubj)}(h)``DRM_XE_OA_UNIT_TYPE_MERT`` MERT OA unith](j)}(h``DRM_XE_OA_UNIT_TYPE_MERT``h]jC)}(hjc"h]hDRM_XE_OA_UNIT_TYPE_MERT}(hje"hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhja"ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj]"ubj)}(hhh]h)}(h MERT OA unith]h MERT OA unit}(hj|"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjy"ubah}(h]h ]h"]h$]h&]uh1jhj]"ubeh}(h]h ]h"]h$]h&]uh1jhjx"hMhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_oa_unit (C struct)c.drm_xe_oa_unithNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_oa_unith]jg)}(hstruct drm_xe_oa_unith](jm)}(hjph]hstruct}(hj"hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj"hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj"hhhj"hMubj)}(hdrm_xe_oa_unith]j)}(hj"h]hdrm_xe_oa_unit}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj"hhhj"hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj"hhhj"hMubah}(h]j"ah ](jjeh"]h$]h&]jj)jhuh1j`hj"hMhj"hhubj)}(hhh]h)}(hdescribe OA unith]hdescribe OA unit}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj"hhubah}(h]h ]h"]h$]h&]uh1jhj"hhhj"hMubeh}(h]h ](jstructeh"]h$]h&]jjjj#jj#jjjuh1j[hhhj-hNhNubj)}(hXI**Definition**:: struct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); #define DRM_XE_OA_CAPS_OAM (1 << 4); #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5); __u64 oa_timestamp_freq; __u16 gt_id; __u16 reserved1[3]; __u64 reserved[3]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``oa_unit_id`` OA unit ID ``oa_unit_type`` OA unit type of :c:type:`enum drm_xe_oa_unit_type ` ``capabilities`` OA capabilities bit-mask ``oa_timestamp_freq`` OA timestamp freq ``gt_id`` gt id for this OA unit ``reserved1`` MBZ ``reserved`` MBZ ``num_engines`` number of engines in **eci** array ``eci`` engines attached to this OA unith](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj##hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubh:}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj#ubj)}(hXEstruct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); #define DRM_XE_OA_CAPS_OAM (1 << 4); #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5); __u64 oa_timestamp_freq; __u16 gt_id; __u16 reserved1[3]; __u64 reserved[3]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; };h]hXEstruct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); #define DRM_XE_OA_CAPS_OAM (1 << 4); #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5); __u64 oa_timestamp_freq; __u16 gt_id; __u16 reserved1[3]; __u64 reserved[3]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; };}hj<#sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj#ubh)}(h **Members**h]j)}(hjM#h]hMembers}(hjO#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK#ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM,hj#ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjl#h]h extensions}(hjn#hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjj#ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjf#ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMhj#ubah}(h]h ]h"]h$]h&]uh1jhjf#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMhjc#ubj)}(h``oa_unit_id`` OA unit ID h](j)}(h``oa_unit_id``h]jC)}(hj#h]h oa_unit_id}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj#ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj#ubj)}(hhh]h)}(h OA unit IDh]h OA unit ID}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMhjc#ubj)}(hZ``oa_unit_type`` OA unit type of :c:type:`enum drm_xe_oa_unit_type ` h](j)}(h``oa_unit_type``h]jC)}(hj#h]h oa_unit_type}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj#ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj#ubj)}(hhh]h)}(hHOA unit type of :c:type:`enum drm_xe_oa_unit_type `h](hOA unit type of }(hj#hhhNhNubh)}(h8:c:type:`enum drm_xe_oa_unit_type `h]jC)}(hj$h]henum drm_xe_oa_unit_type}(hj$hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj#ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_oa_unit_typeuh1hhj#hMhj#ubeh}(h]h ]h"]h$]h&]uh1hhj#hMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMhjc#ubj)}(h*``capabilities`` OA capabilities bit-mask h](j)}(h``capabilities``h]jC)}(hj6$h]h capabilities}(hj8$hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj4$ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj0$ubj)}(hhh]h)}(hOA capabilities bit-maskh]hOA capabilities bit-mask}(hjO$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjK$hM hjL$ubah}(h]h ]h"]h$]h&]uh1jhj0$ubeh}(h]h ]h"]h$]h&]uh1jhjK$hM hjc#ubj)}(h(``oa_timestamp_freq`` OA timestamp freq h](j)}(h``oa_timestamp_freq``h]jC)}(hjo$h]hoa_timestamp_freq}(hjq$hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjm$ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM)hji$ubj)}(hhh]h)}(hOA timestamp freqh]hOA timestamp freq}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM)hj$ubah}(h]h ]h"]h$]h&]uh1jhji$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM)hjc#ubj)}(h!``gt_id`` gt id for this OA unit h](j)}(h ``gt_id``h]jC)}(hj$h]hgt_id}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM,hj$ubj)}(hhh]h)}(hgt id for this OA unith]hgt id for this OA unit}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM,hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM,hjc#ubj)}(h``reserved1`` MBZ h](j)}(h ``reserved1``h]jC)}(hj$h]h reserved1}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj$ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM/hj$ubj)}(hhh]h)}(hMBZh]hMBZ}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM/hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM/hjc#ubj)}(h``reserved`` MBZ h](j)}(h ``reserved``h]jC)}(hj%h]hreserved}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj%ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM2hj%ubj)}(hhh]h)}(hMBZh]hMBZ}(hj3%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/%hM2hj0%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj/%hM2hjc#ubj)}(h3``num_engines`` number of engines in **eci** array h](j)}(h``num_engines``h]jC)}(hjS%h]h num_engines}(hjU%hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQ%ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM5hjM%ubj)}(hhh]h)}(h"number of engines in **eci** arrayh](hnumber of engines in }(hjl%hhhNhNubj)}(h**eci**h]heci}(hjt%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl%ubh array}(hjl%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjh%hM5hji%ubah}(h]h ]h"]h$]h&]uh1jhjM%ubeh}(h]h ]h"]h$]h&]uh1jhjh%hM5hjc#ubj)}(h(``eci`` engines attached to this OA unith](j)}(h``eci``h]jC)}(hj%h]heci}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj%ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM7hj%ubj)}(hhh]h)}(h engines attached to this OA unith]h engines attached to this OA unit}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM8hj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hM7hjc#ubeh}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_xe_query_oa_units (C struct)c.drm_xe_query_oa_unitshNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_oa_unitsh]jg)}(hstruct drm_xe_query_oa_unitsh](jm)}(hjph]hstruct}(hj%hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj%hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM>ubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj%hhhj&hM>ubj)}(hdrm_xe_query_oa_unitsh]j)}(hj%h]hdrm_xe_query_oa_units}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj%hhhj&hM>ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj%hhhj&hM>ubah}(h]j%ah ](jjeh"]h$]h&]jj)jhuh1j`hj&hM>hj%hhubj)}(hhh]h)}(hdescribe OA unitsh]hdescribe OA units}(hj:&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM<hj7&hhubah}(h]h ]h"]h$]h&]uh1jhj%hhhj&hM>ubeh}(h]h ](jstructeh"]h$]h&]jjjjR&jjR&jjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``num_oa_units`` number of OA units returned in oau[] ``pad`` MBZ ``oa_units`` :c:type:`struct drm_xe_oa_unit ` array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj^&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ&ubh:}(hjZ&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM@hjV&ubj)}(htstruct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; };h]htstruct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; };}hjw&sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMBhjV&ubh)}(h **Members**h]j)}(hj&h]hMembers}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMIhjV&ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj&h]h extensions}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj&ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMUhj&ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hMUhj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMUhj&ubj)}(h6``num_oa_units`` number of OA units returned in oau[] h](j)}(h``num_oa_units``h]jC)}(hj&h]h num_oa_units}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj&ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMWhj&ubj)}(hhh]h)}(h$number of OA units returned in oau[]h]h$number of OA units returned in oau[]}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hMWhj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMWhj&ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hj'h]hpad}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj'ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMYhj'ubj)}(hhh]h)}(hMBZh]hMBZ}(hj2'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.'hMYhj/'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj.'hMYhj&ubj)}(h``oa_units`` :c:type:`struct drm_xe_oa_unit ` array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](j)}(h ``oa_units``h]jC)}(hjR'h]hoa_units}(hjT'hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjP'ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM]hjL'ubj)}(hhh]h)}(h:c:type:`struct drm_xe_oa_unit ` array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](h)}(h0:c:type:`struct drm_xe_oa_unit `h]jC)}(hjq'h]hstruct drm_xe_oa_unit}(hjs'hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjo'ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_oa_unituh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM\hjk'ubh array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilers}(hjk'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj'hM\hjh'ubah}(h]h ]h"]h$]h&]uh1jhjL'ubeh}(h]h ]h"]h$]h&]uh1jhjg'hM]hj&ubeh}(h]h ]h"]h$]h&]uh1jhjV&ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj'h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMahj-hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct drm_xe_query_oa_units in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct drm_xe_query_oa_units in .data.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM=hj-hhubh)}(h]OA unit properties for all OA units can be accessed using a code block such as the one below:h]h]OA unit properties for all OA units can be accessed using a code block such as the one below:}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMAhj-hhubj)}(hXstruct drm_xe_query_oa_units *qoa; struct drm_xe_oa_unit *oau; u8 *poau; // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: poau = (u8 *)&qoa->oa_units[0]; for (int i = 0; i < qoa->num_oa_units; i++) { oau = (struct drm_xe_oa_unit *)poau; // Access 'struct drm_xe_oa_unit' fields here poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); }h]hXstruct drm_xe_query_oa_units *qoa; struct drm_xe_oa_unit *oau; u8 *poau; // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: poau = (u8 *)&qoa->oa_units[0]; for (int i = 0; i < qoa->num_oa_units; i++) { oau = (struct drm_xe_oa_unit *)poau; // Access 'struct drm_xe_oa_unit' fields here poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); }}hj'sbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMDhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_oa_format_type (C enum)c.drm_xe_oa_format_typehNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_oa_format_typeh]jg)}(henum drm_xe_oa_format_typeh](jm)}(hjh]henum}(hj(hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj (hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMUubj)}(h h]h }(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj (hhhj(hMUubj)}(hdrm_xe_oa_format_typeh]j)}(hj (h]hdrm_xe_oa_format_type}(hj1(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-(ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj (hhhj(hMUubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj (hhhj(hMUubah}(h]j(ah ](jjeh"]h$]h&]jj)jhuh1j`hj(hMUhj(hhubj)}(hhh]h)}(h5OA format types as specified in PRM/Bspec 52198/60942h]h5OA format types as specified in PRM/Bspec 52198/60942}(hjS(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMchjP(hhubah}(h]h ]h"]h$]h&]uh1jhj(hhhj(hMUubeh}(h]h ](jenumeh"]h$]h&]jjjjk(jjk(jjjuh1j[hhhj-hNhNubj)}(hXF**Constants** ``DRM_XE_OA_FMT_TYPE_OAG`` OAG report format ``DRM_XE_OA_FMT_TYPE_OAR`` OAR report format ``DRM_XE_OA_FMT_TYPE_OAM`` OAM report format ``DRM_XE_OA_FMT_TYPE_OAC`` OAC report format ``DRM_XE_OA_FMT_TYPE_OAM_MPEC`` OAM SAMEDIA or OAM MPEC report format ``DRM_XE_OA_FMT_TYPE_PEC`` PEC report formath](h)}(h **Constants**h]j)}(hju(h]h Constants}(hjw(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs(ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMghjo(ubj)}(hhh](j)}(h-``DRM_XE_OA_FMT_TYPE_OAG`` OAG report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAG``h]jC)}(hj(h]hDRM_XE_OA_FMT_TYPE_OAG}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj(ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMjhj(ubj)}(hhh]h)}(hOAG report formath]hOAG report format}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hMjhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMjhj(ubj)}(h-``DRM_XE_OA_FMT_TYPE_OAR`` OAR report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAR``h]jC)}(hj(h]hDRM_XE_OA_FMT_TYPE_OAR}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj(ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMmhj(ubj)}(hhh]h)}(hOAR report formath]hOAR report format}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hMmhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMmhj(ubj)}(h-``DRM_XE_OA_FMT_TYPE_OAM`` OAM report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAM``h]jC)}(hj)h]hDRM_XE_OA_FMT_TYPE_OAM}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj)ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMphj)ubj)}(hhh]h)}(hOAM report formath]hOAM report format}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hMphj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMphj(ubj)}(h-``DRM_XE_OA_FMT_TYPE_OAC`` OAC report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAC``h]jC)}(hj?)h]hDRM_XE_OA_FMT_TYPE_OAC}(hjA)hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj=)ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMshj9)ubj)}(hhh]h)}(hOAC report formath]hOAC report format}(hjX)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT)hMshjU)ubah}(h]h ]h"]h$]h&]uh1jhj9)ubeh}(h]h ]h"]h$]h&]uh1jhjT)hMshj(ubj)}(hF``DRM_XE_OA_FMT_TYPE_OAM_MPEC`` OAM SAMEDIA or OAM MPEC report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAM_MPEC``h]jC)}(hjx)h]hDRM_XE_OA_FMT_TYPE_OAM_MPEC}(hjz)hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjv)ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMvhjr)ubj)}(hhh]h)}(h%OAM SAMEDIA or OAM MPEC report formath]h%OAM SAMEDIA or OAM MPEC report format}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hMvhj)ubah}(h]h ]h"]h$]h&]uh1jhjr)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMvhj(ubj)}(h,``DRM_XE_OA_FMT_TYPE_PEC`` PEC report formath](j)}(h``DRM_XE_OA_FMT_TYPE_PEC``h]jC)}(hj)h]hDRM_XE_OA_FMT_TYPE_PEC}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj)ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMxhj)ubj)}(hhh]h)}(hPEC report formath]hPEC report format}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMyhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMxhj(ubeh}(h]h ]h"]h$]h&]uh1jhjo(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_oa_property_id (C enum)c.drm_xe_oa_property_idhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_oa_property_idh]jg)}(henum drm_xe_oa_property_idh](jm)}(hjh]henum}(hj *hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj*hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM~ubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj*hhhj*hM~ubj)}(hdrm_xe_oa_property_idh]j)}(hj*h]hdrm_xe_oa_property_id}(hj+*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'*ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj*hhhj*hM~ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj*hhhj*hM~ubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1j`hj*hM~hj*hhubj)}(hhh]h)}(hOA stream property IDsh]hOA stream property IDs}(hjM*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMvhjJ*hhubah}(h]h ]h"]h$]h&]uh1jhj*hhhj*hM~ubeh}(h]h ](jenumeh"]h$]h&]jjjje*jje*jjjuh1j[hhhj-hNhNubj)}(hX**Constants** ``DRM_XE_OA_PROPERTY_OA_UNIT_ID`` ID of the OA unit on which to open the OA stream, see oa_unit_id in :c:type:`struct drm_xe_oa_unit `. Defaults to 0 if not provided. ``DRM_XE_OA_PROPERTY_SAMPLE_OA`` A value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit. ``DRM_XE_OA_PROPERTY_OA_METRIC_SET`` OA metrics defining contents of OA reports, previously added via ``DRM_XE_OBSERVATION_OP_ADD_CONFIG``. ``DRM_XE_OA_PROPERTY_OA_FORMAT`` OA counter report format ``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT`` Requests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1) ``DRM_XE_OA_PROPERTY_OA_DISABLED`` A value of 1 will open the OA stream in a DISABLED state (see ``DRM_XE_OBSERVATION_IOCTL_ENABLE``). ``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` Open the stream for a specific exec_queue_id. OA queries can be executed on this exec queue. ``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE`` Optional engine instance to pass along with ``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` or will default to 0. ``DRM_XE_OA_PROPERTY_NO_PREEMPT`` Allow preemption and timeslicing to be disabled for the stream exec queue. ``DRM_XE_OA_PROPERTY_NUM_SYNCS`` Number of syncs in the sync array specified in ``DRM_XE_OA_PROPERTY_SYNCS`` ``DRM_XE_OA_PROPERTY_SYNCS`` Pointer to :c:type:`struct drm_xe_sync ` array with array size specified via ``DRM_XE_OA_PROPERTY_NUM_SYNCS``. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For ``DRM_XE_SYNC_TYPE_USER_FENCE``, addr is a user pointer, similar to the VM bind case. ``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE`` Size of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default. ``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS`` Number of reports to wait for before unblocking poll or readh](h)}(h **Constants**h]j)}(hjo*h]h Constants}(hjq*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm*ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMzhji*ubj)}(hhh](j)}(h``DRM_XE_OA_PROPERTY_OA_UNIT_ID`` ID of the OA unit on which to open the OA stream, see oa_unit_id in :c:type:`struct drm_xe_oa_unit `. Defaults to 0 if not provided. h](j)}(h!``DRM_XE_OA_PROPERTY_OA_UNIT_ID``h]jC)}(hj*h]hDRM_XE_OA_PROPERTY_OA_UNIT_ID}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj*ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj*ubj)}(hhh]h)}(hID of the OA unit on which to open the OA stream, see oa_unit_id in :c:type:`struct drm_xe_oa_unit `. Defaults to 0 if not provided.h](hDID of the OA unit on which to open the OA stream, see oa_unit_id in }(hj*hhhNhNubh)}(h0:c:type:`struct drm_xe_oa_unit `h]jC)}(hj*h]hstruct drm_xe_oa_unit}(hj*hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj*ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_oa_unituh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM}hj*ubh . Defaults to 0 if not provided.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj*hM}hj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hMhj*ubj)}(h``DRM_XE_OA_PROPERTY_SAMPLE_OA`` A value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit. h](j)}(h ``DRM_XE_OA_PROPERTY_SAMPLE_OA``h]jC)}(hj*h]hDRM_XE_OA_PROPERTY_SAMPLE_OA}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj*ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj*ubj)}(hhh]h)}(hsA value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit.h]hsA value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj+hMhj*ubj)}(h``DRM_XE_OA_PROPERTY_OA_METRIC_SET`` OA metrics defining contents of OA reports, previously added via ``DRM_XE_OBSERVATION_OP_ADD_CONFIG``. h](j)}(h$``DRM_XE_OA_PROPERTY_OA_METRIC_SET``h]jC)}(hj%+h]h DRM_XE_OA_PROPERTY_OA_METRIC_SET}(hj'+hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj#+ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj+ubj)}(hhh]h)}(hfOA metrics defining contents of OA reports, previously added via ``DRM_XE_OBSERVATION_OP_ADD_CONFIG``.h](hAOA metrics defining contents of OA reports, previously added via }(hj>+hhhNhNubjC)}(h$``DRM_XE_OBSERVATION_OP_ADD_CONFIG``h]h DRM_XE_OBSERVATION_OP_ADD_CONFIG}(hjF+hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>+ubh.}(hj>+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj;+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj:+hMhj*ubj)}(h:``DRM_XE_OA_PROPERTY_OA_FORMAT`` OA counter report format h](j)}(h ``DRM_XE_OA_PROPERTY_OA_FORMAT``h]jC)}(hjq+h]hDRM_XE_OA_PROPERTY_OA_FORMAT}(hjs+hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjo+ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjk+ubj)}(hhh]h)}(hOA counter report formath]hOA counter report format}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hMhj+ubah}(h]h ]h"]h$]h&]uh1jhjk+ubeh}(h]h ]h"]h$]h&]uh1jhj+hMhj*ubj)}(h``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT`` Requests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1) h](j)}(h)``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT``h]jC)}(hj+h]h%DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj+ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj+ubj)}(hhh]h)}(hbRequests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1)h]hbRequests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1)}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hMhj*ubj)}(h``DRM_XE_OA_PROPERTY_OA_DISABLED`` A value of 1 will open the OA stream in a DISABLED state (see ``DRM_XE_OBSERVATION_IOCTL_ENABLE``). h](j)}(h"``DRM_XE_OA_PROPERTY_OA_DISABLED``h]jC)}(hj+h]hDRM_XE_OA_PROPERTY_OA_DISABLED}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj+ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj+ubj)}(hhh]h)}(hcA value of 1 will open the OA stream in a DISABLED state (see ``DRM_XE_OBSERVATION_IOCTL_ENABLE``).h](h>A value of 1 will open the OA stream in a DISABLED state (see }(hj+hhhNhNubjC)}(h#``DRM_XE_OBSERVATION_IOCTL_ENABLE``h]hDRM_XE_OBSERVATION_IOCTL_ENABLE}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj+ubh).}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hMhj*ubj)}(h``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` Open the stream for a specific exec_queue_id. OA queries can be executed on this exec queue. h](j)}(h$``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID``h]jC)}(hj0,h]h DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID}(hj2,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj.,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj*,ubj)}(hhh]h)}(h\Open the stream for a specific exec_queue_id. OA queries can be executed on this exec queue.h]h\Open the stream for a specific exec_queue_id. OA queries can be executed on this exec queue.}(hjI,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjF,ubah}(h]h ]h"]h$]h&]uh1jhj*,ubeh}(h]h ]h"]h$]h&]uh1jhjE,hMhj*ubj)}(h``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE`` Optional engine instance to pass along with ``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` or will default to 0. h](j)}(h)``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE``h]jC)}(hjj,h]h%DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE}(hjl,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjh,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjd,ubj)}(hhh]h)}(hfOptional engine instance to pass along with ``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` or will default to 0.h](h,Optional engine instance to pass along with }(hj,hhhNhNubjC)}(h$``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID``h]h DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,ubh or will default to 0.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj,ubah}(h]h ]h"]h$]h&]uh1jhjd,ubeh}(h]h ]h"]h$]h&]uh1jhj,hMhj*ubj)}(hm``DRM_XE_OA_PROPERTY_NO_PREEMPT`` Allow preemption and timeslicing to be disabled for the stream exec queue. h](j)}(h!``DRM_XE_OA_PROPERTY_NO_PREEMPT``h]jC)}(hj,h]hDRM_XE_OA_PROPERTY_NO_PREEMPT}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj,ubj)}(hhh]h)}(hJAllow preemption and timeslicing to be disabled for the stream exec queue.h]hJAllow preemption and timeslicing to be disabled for the stream exec queue.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj,hMhj*ubj)}(hm``DRM_XE_OA_PROPERTY_NUM_SYNCS`` Number of syncs in the sync array specified in ``DRM_XE_OA_PROPERTY_SYNCS`` h](j)}(h ``DRM_XE_OA_PROPERTY_NUM_SYNCS``h]jC)}(hj,h]hDRM_XE_OA_PROPERTY_NUM_SYNCS}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj,ubj)}(hhh]h)}(hKNumber of syncs in the sync array specified in ``DRM_XE_OA_PROPERTY_SYNCS``h](h/Number of syncs in the sync array specified in }(hj -hhhNhNubjC)}(h``DRM_XE_OA_PROPERTY_SYNCS``h]hDRM_XE_OA_PROPERTY_SYNCS}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj -ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj-hMhj*ubj)}(hXo``DRM_XE_OA_PROPERTY_SYNCS`` Pointer to :c:type:`struct drm_xe_sync ` array with array size specified via ``DRM_XE_OA_PROPERTY_NUM_SYNCS``. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For ``DRM_XE_SYNC_TYPE_USER_FENCE``, addr is a user pointer, similar to the VM bind case. h](j)}(h``DRM_XE_OA_PROPERTY_SYNCS``h]jC)}(hj8-h]hDRM_XE_OA_PROPERTY_SYNCS}(hj:-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj6-ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj2-ubj)}(hhh]h)}(hXQPointer to :c:type:`struct drm_xe_sync ` array with array size specified via ``DRM_XE_OA_PROPERTY_NUM_SYNCS``. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For ``DRM_XE_SYNC_TYPE_USER_FENCE``, addr is a user pointer, similar to the VM bind case.h](h Pointer to }(hjQ-hhhNhNubh)}(h*:c:type:`struct drm_xe_sync `h]jC)}(hj[-h]hstruct drm_xe_sync}(hj]-hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjY-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_xe_syncuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjQ-ubh% array with array size specified via }(hjQ-hhhNhNubjC)}(h ``DRM_XE_OA_PROPERTY_NUM_SYNCS``h]hDRM_XE_OA_PROPERTY_NUM_SYNCS}(hj}-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQ-ubh. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For }(hjQ-hhhNhNubjC)}(h``DRM_XE_SYNC_TYPE_USER_FENCE``h]hDRM_XE_SYNC_TYPE_USER_FENCE}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQ-ubh6, addr is a user pointer, similar to the VM bind case.}(hjQ-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjx-hMhjN-ubah}(h]h ]h"]h$]h&]uh1jhj2-ubeh}(h]h ]h"]h$]h&]uh1jhjM-hMhj*ubj)}(h``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE`` Size of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default. h](j)}(h%``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE``h]jC)}(hj-h]h!DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-ubj)}(hhh]h)}(hSize of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default.h]hSize of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hMhj*ubj)}(hd``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS`` Number of reports to wait for before unblocking poll or readh](j)}(h'``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS``h]jC)}(hj-h]h#DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-ubj)}(hhh]h)}(h` structs, with property values from :c:type:`enum drm_xe_oa_property_id ` and :c:type:`struct drm_xe_user_extension ` base.name set to ``DRM_XE_OA_EXTENSION_SET_PROPERTY``. The param field in :c:type:`struct drm_xe_observation_param ` points to the first :c:type:`struct drm_xe_ext_set_property ` struct.h](h*Stream params are specified as a chain of }(hjK.hhhNhNubh)}(hB:c:type:`struct drm_xe_ext_set_property `h]jC)}(hjU.h]hstruct drm_xe_ext_set_property}(hjW.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjS.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_ext_set_propertyuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMwhjK.ubh$ structs, with property values from }(hjK.hhhNhNubh)}(h<:c:type:`enum drm_xe_oa_property_id `h]jC)}(hjy.h]henum drm_xe_oa_property_id}(hj{.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjw.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_oa_property_iduh1hhjr.hMwhjK.ubh and }(hjK.hhhNhNubh)}(h>:c:type:`struct drm_xe_user_extension `h]jC)}(hj.h]hstruct drm_xe_user_extension}(hj.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_user_extensionuh1hhjr.hMwhjK.ubh base.name set to }(hjK.hhhNhNubjC)}(h$``DRM_XE_OA_EXTENSION_SET_PROPERTY``h]h DRM_XE_OA_EXTENSION_SET_PROPERTY}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjK.ubh. The param field in }(hjK.hhhNhNubh)}(hD:c:type:`struct drm_xe_observation_param `h]jC)}(hj.h]hstruct drm_xe_observation_param}(hj.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_observation_paramuh1hhjr.hMwhjK.ubh points to the first }(hjK.hhhNhNubh)}(hB:c:type:`struct drm_xe_ext_set_property `h]jC)}(hj.h]hstruct drm_xe_ext_set_property}(hj.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_ext_set_propertyuh1hhjr.hMwhjK.ubh struct.}(hjK.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjr.hMwhj-hhubh)}(hExactly the same mechanism is also used for stream reconfiguration using the ``DRM_XE_OBSERVATION_IOCTL_CONFIG`` observation stream fd ioctl, though only a subset of properties below can be specified for stream reconfiguration.h](hMExactly the same mechanism is also used for stream reconfiguration using the }(hj/hhhNhNubjC)}(h#``DRM_XE_OBSERVATION_IOCTL_CONFIG``h]hDRM_XE_OBSERVATION_IOCTL_CONFIG}(hj#/hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj/ubhs observation stream fd ioctl, though only a subset of properties below can be specified for stream reconfiguration.}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM}hj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_oa_config (C struct)c.drm_xe_oa_confighNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_oa_configh]jg)}(hstruct drm_xe_oa_configh](jm)}(hjph]hstruct}(hjU/hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjQ/hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjc/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjQ/hhhjb/hMubj)}(hdrm_xe_oa_configh]j)}(hjO/h]hdrm_xe_oa_config}(hju/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjq/ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjQ/hhhjb/hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjM/hhhjb/hMubah}(h]jH/ah ](jjeh"]h$]h&]jj)jhuh1j`hjb/hMhjJ/hhubj)}(hhh]h)}(hOA metric configurationh]hOA metric configuration}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj/hhubah}(h]h ]h"]h$]h&]uh1jhjJ/hhhjb/hMubeh}(h]h ](jstructeh"]h$]h&]jjjj/jj/jjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_oa_config { __u64 extensions; char uuid[36]; __u32 n_regs; __u64 regs_ptr; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``uuid`` String formatted like "``08x-````04x-````04x-````04x-````012x``" ``n_regs`` Number of regs in **regs_ptr** ``regs_ptr`` Pointer to (register address, value) pairs for OA config registers. Expected length of buffer is: (2 * sizeof(u32) * **n_regs**).h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubh:}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj/ubj)}(hkstruct drm_xe_oa_config { __u64 extensions; char uuid[36]; __u32 n_regs; __u64 regs_ptr; };h]hkstruct drm_xe_oa_config { __u64 extensions; char uuid[36]; __u32 n_regs; __u64 regs_ptr; };}hj/sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj/ubh)}(h **Members**h]j)}(hj/h]hMembers}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj/ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj0h]h extensions}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj0ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj/ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhj0hMhj/ubj)}(hJ``uuid`` String formatted like "``08x-````04x-````04x-````04x-````012x``" h](j)}(h``uuid``h]jC)}(hj=0h]huuid}(hj?0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj;0ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj70ubj)}(hhh]h)}(h@String formatted like "``08x-````04x-````04x-````04x-````012x``"h](hString formatted like “}(hjV0hhhNhNubjC)}(h(``08x-````04x-````04x-````04x-````012x``h]h$08x-````04x-````04x-````04x-````012x}(hj^0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjV0ubh”}(hjV0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjR0hMhjS0ubah}(h]h ]h"]h$]h&]uh1jhj70ubeh}(h]h ]h"]h$]h&]uh1jhjR0hMhj/ubj)}(h*``n_regs`` Number of regs in **regs_ptr** h](j)}(h ``n_regs``h]jC)}(hj0h]hn_regs}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj0ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj0ubj)}(hhh]h)}(hNumber of regs in **regs_ptr**h](hNumber of regs in }(hj0hhhNhNubj)}(h **regs_ptr**h]hregs_ptr}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1hhj0hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhj0hMhj/ubj)}(h``regs_ptr`` Pointer to (register address, value) pairs for OA config registers. Expected length of buffer is: (2 * sizeof(u32) * **n_regs**).h](j)}(h ``regs_ptr``h]jC)}(hj0h]hregs_ptr}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj0ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj0ubj)}(hhh]h)}(hPointer to (register address, value) pairs for OA config registers. Expected length of buffer is: (2 * sizeof(u32) * **n_regs**).h](huPointer to (register address, value) pairs for OA config registers. Expected length of buffer is: (2 * sizeof(u32) * }(hj0hhhNhNubj)}(h **n_regs**h]hn_regs}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh).}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj0hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhj0hMhj/ubeh}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj#1h]h Description}(hj%1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!1ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubh)}(hMultiple OA configs can be added using ``DRM_XE_OBSERVATION_OP_ADD_CONFIG``. A particular config can be specified when opening an OA stream using ``DRM_XE_OA_PROPERTY_OA_METRIC_SET`` property.h](h'Multiple OA configs can be added using }(hj91hhhNhNubjC)}(h$``DRM_XE_OBSERVATION_OP_ADD_CONFIG``h]h DRM_XE_OBSERVATION_OP_ADD_CONFIG}(hjA1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj91ubhG. A particular config can be specified when opening an OA stream using }(hj91hhhNhNubjC)}(h$``DRM_XE_OA_PROPERTY_OA_METRIC_SET``h]h DRM_XE_OA_PROPERTY_OA_METRIC_SET}(hjS1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj91ubh property.}(hj91hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_xe_oa_stream_status (C struct)c.drm_xe_oa_stream_statushNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_oa_stream_statush]jg)}(hstruct drm_xe_oa_stream_statush](jm)}(hjph]hstruct}(hj1hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj1hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj1hhhj1hMubj)}(hdrm_xe_oa_stream_statush]j)}(hj1h]hdrm_xe_oa_stream_status}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj1hhhj1hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj}1hhhj1hMubah}(h]jx1ah ](jjeh"]h$]h&]jj)jhuh1j`hj1hMhjz1hhubj)}(hhh]h)}(hOA stream status returned from ``DRM_XE_OBSERVATION_IOCTL_STATUS`` observation stream fd ioctl. Userspace can call the ioctl to query stream status in response to EIO errno from observation fd read().h](hOA stream status returned from }(hj1hhhNhNubjC)}(h#``DRM_XE_OBSERVATION_IOCTL_STATUS``h]hDRM_XE_OBSERVATION_IOCTL_STATUS}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj1ubh observation stream fd ioctl. Userspace can call the ioctl to query stream status in response to EIO errno from observation fd read().}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj1hhubah}(h]h ]h"]h$]h&]uh1jhjz1hhhj1hMubeh}(h]h ](jstructeh"]h$]h&]jjjj1jj1jjjuh1j[hhhj-hNhNubj)}(hX **Definition**:: struct drm_xe_oa_stream_status { __u64 extensions; __u64 oa_status; #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3); #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2); #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1); #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0); __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``oa_status`` OA stream status (see Bspec 46717/61226) ``reserved`` reserved for future useh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubh:}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj1ubj)}(hXMstruct drm_xe_oa_stream_status { __u64 extensions; __u64 oa_status; #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3); #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2); #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1); #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0); __u64 reserved[3]; };h]hXMstruct drm_xe_oa_stream_status { __u64 extensions; __u64 oa_status; #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3); #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2); #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1); #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0); __u64 reserved[3]; };}hj2sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj1ubh)}(h **Members**h]j)}(hj'2h]hMembers}(hj)2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%2ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj1ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjF2h]h extensions}(hjH2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjD2ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj@2ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj_2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[2hMhj\2ubah}(h]h ]h"]h$]h&]uh1jhj@2ubeh}(h]h ]h"]h$]h&]uh1jhj[2hMhj=2ubj)}(h7``oa_status`` OA stream status (see Bspec 46717/61226) h](j)}(h ``oa_status``h]jC)}(hj2h]h oa_status}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj}2ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjy2ubj)}(hhh]h)}(h(OA stream status (see Bspec 46717/61226)h]h(OA stream status (see Bspec 46717/61226)}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMhj2ubah}(h]h ]h"]h$]h&]uh1jhjy2ubeh}(h]h ]h"]h$]h&]uh1jhj2hMhj=2ubj)}(h$``reserved`` reserved for future useh](j)}(h ``reserved``h]jC)}(hj2h]hreserved}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj2ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj2ubj)}(hhh]h)}(hreserved for future useh]hreserved for future use}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hM hj=2ubeh}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_xe_oa_stream_info (C struct)c.drm_xe_oa_stream_infohNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_oa_stream_infoh]jg)}(hstruct drm_xe_oa_stream_infoh](jm)}(hjph]hstruct}(hj3hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj3hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj 3hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj3hhhj3hMubj)}(hdrm_xe_oa_stream_infoh]j)}(hj 3h]hdrm_xe_oa_stream_info}(hj23hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.3ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj3hhhj3hMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj 3hhhj3hMubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1j`hj3hMhj3hhubj)}(hhh]h)}(hZOA stream info returned from ``DRM_XE_OBSERVATION_IOCTL_INFO`` observation stream fd ioctlh](hOA stream info returned from }(hjT3hhhNhNubjC)}(h!``DRM_XE_OBSERVATION_IOCTL_INFO``h]hDRM_XE_OBSERVATION_IOCTL_INFO}(hj\3hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjT3ubh observation stream fd ioctl}(hjT3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjQ3hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj3hMubeh}(h]h ](jstructeh"]h$]h&]jjjj~3jj~3jjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_oa_stream_info { __u64 extensions; __u64 oa_buf_size; __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``oa_buf_size`` OA buffer size ``reserved`` reserved for future useh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubh:}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj3ubj)}(hestruct drm_xe_oa_stream_info { __u64 extensions; __u64 oa_buf_size; __u64 reserved[3]; };h]hestruct drm_xe_oa_stream_info { __u64 extensions; __u64 oa_buf_size; __u64 reserved[3]; };}hj3sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj3ubh)}(h **Members**h]j)}(hj3h]hMembers}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj3ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj3h]h extensions}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj3ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj3ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhj3ubj)}(h``oa_buf_size`` OA buffer size h](j)}(h``oa_buf_size``h]jC)}(hj 4h]h oa_buf_size}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj 4ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj4ubj)}(hhh]h)}(hOA buffer sizeh]hOA buffer size}(hj%4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!4hMhj"4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj!4hMhj3ubj)}(h$``reserved`` reserved for future useh](j)}(h ``reserved``h]jC)}(hjE4h]hreserved}(hjG4hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjC4ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj?4ubj)}(hhh]h)}(hreserved for future useh]hreserved for future use}(hj^4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj[4ubah}(h]h ]h"]h$]h&]uh1jhj?4ubeh}(h]h ]h"]h$]h&]uh1jhjZ4hMhj3ubeh}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_xe_pxp_session_type (C enum)c.drm_xe_pxp_session_typehNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_pxp_session_typeh]jg)}(henum drm_xe_pxp_session_typeh](jm)}(hjh]henum}(hj4hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj4hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM!ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj4hhhj4hM!ubj)}(hdrm_xe_pxp_session_typeh]j)}(hj4h]hdrm_xe_pxp_session_type}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj4hhhj4hM!ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj4hhhj4hM!ubah}(h]j4ah ](jjeh"]h$]h&]jj)jhuh1j`hj4hM!hj4hhubj)}(hhh]h)}(hSupported PXP session types.h]hSupported PXP session types.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj4hhubah}(h]h ]h"]h$]h&]uh1jhj4hhhj4hM!ubeh}(h]h ](jenumeh"]h$]h&]jjjj4jj4jjjuh1j[hhhj-hNhNubj)}(h**Constants** ``DRM_XE_PXP_TYPE_NONE`` PXP not used ``DRM_XE_PXP_TYPE_HWDRM`` HWDRM sessions are used for content that ends up on the display.h](h)}(h **Constants**h]j)}(hj5h]h Constants}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM#hj4ubj)}(hhh](j)}(h&``DRM_XE_PXP_TYPE_NONE`` PXP not used h](j)}(h``DRM_XE_PXP_TYPE_NONE``h]jC)}(hj"5h]hDRM_XE_PXP_TYPE_NONE}(hj$5hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj 5ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM&hj5ubj)}(hhh]h)}(h PXP not usedh]h PXP not used}(hj;5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj75hM&hj85ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj75hM&hj5ubj)}(hZ``DRM_XE_PXP_TYPE_HWDRM`` HWDRM sessions are used for content that ends up on the display.h](j)}(h``DRM_XE_PXP_TYPE_HWDRM``h]jC)}(hj[5h]hDRM_XE_PXP_TYPE_HWDRM}(hj]5hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjY5ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM)hjU5ubj)}(hhh]h)}(h@HWDRM sessions are used for content that ends up on the display.h]h@HWDRM sessions are used for content that ends up on the display.}(hjt5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp5hM)hjq5ubah}(h]h ]h"]h$]h&]uh1jhjU5ubeh}(h]h ]h"]h$]h&]uh1jhjp5hM)hj5ubeh}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj5h]h Description}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM,hj-hhubh)}(hWe currently only support HWDRM sessions, which are used for protected content that ends up being displayed, but the HW supports multiple types, so we might extend support in the future.h]hWe currently only support HWDRM sessions, which are used for protected content that ends up being displayed, but the HW supports multiple types, so we might extend support in the future.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]udh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW$drm_xe_eu_stall_property_id (C enum)c.drm_xe_eu_stall_property_idhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_eu_stall_property_idh]jg)}(h enum drm_xe_eu_stall_property_idh](jm)}(hjh]henum}(hj5hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj5hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM'ubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj5hhhj5hM'ubj)}(hdrm_xe_eu_stall_property_idh]j)}(hj5h]hdrm_xe_eu_stall_property_id}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj5hhhj5hM'ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj5hhhj5hM'ubah}(h]j5ah ](jjeh"]h$]h&]jj)jhuh1j`hj5hM'hj5hhubj)}(hhh]h)}(h%EU stall sampling input property ids.h]h%EU stall sampling input property ids.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM3hj6hhubah}(h]h ]h"]h$]h&]uh1jhj5hhhj5hM'ubeh}(h]h ](jenumeh"]h$]h&]jjjj56jj56jjjuh1j[hhhj-hNhNubj)}(hX**Constants** ``DRM_XE_EU_STALL_PROP_GT_ID`` gt_id of the GT on which EU stall data will be captured. ``DRM_XE_EU_STALL_PROP_SAMPLE_RATE`` Sampling rate in GPU cycles from sampling_rates in :c:type:`struct drm_xe_query_eu_stall ` ``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS`` Minimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h](h)}(h **Constants**h]j)}(hj?6h]h Constants}(hjA6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=6ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM7hj96ubj)}(hhh](j)}(hX``DRM_XE_EU_STALL_PROP_GT_ID`` gt_id of the GT on which EU stall data will be captured. h](j)}(h``DRM_XE_EU_STALL_PROP_GT_ID``h]jC)}(hj^6h]hDRM_XE_EU_STALL_PROP_GT_ID}(hj`6hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj\6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM;hjX6ubj)}(hhh]h)}(h8gt_id of the GT on which EU stall data will be captured.h]h8gt_id of the GT on which EU stall data will be captured.}(hjw6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM:hjt6ubah}(h]h ]h"]h$]h&]uh1jhjX6ubeh}(h]h ]h"]h$]h&]uh1jhjs6hM;hjU6ubj)}(h``DRM_XE_EU_STALL_PROP_SAMPLE_RATE`` Sampling rate in GPU cycles from sampling_rates in :c:type:`struct drm_xe_query_eu_stall ` h](j)}(h$``DRM_XE_EU_STALL_PROP_SAMPLE_RATE``h]jC)}(hj6h]h DRM_XE_EU_STALL_PROP_SAMPLE_RATE}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM?hj6ubj)}(hhh]h)}(hqSampling rate in GPU cycles from sampling_rates in :c:type:`struct drm_xe_query_eu_stall `h](h3Sampling rate in GPU cycles from sampling_rates in }(hj6hhhNhNubh)}(h>:c:type:`struct drm_xe_query_eu_stall `h]jC)}(hj6h]hstruct drm_xe_query_eu_stall}(hj6hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj6ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_query_eu_stalluh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM>hj6ubeh}(h]h ]h"]h$]h&]uh1hhj6hM>hj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hM?hjU6ubj)}(h``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS`` Minimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h](j)}(h)``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS``h]jC)}(hj6h]h%DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMChj6ubj)}(hhh]h)}(htMinimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h]htMinimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.}(hj 7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMBhj7ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj7hMChjU6ubeh}(h]h ]h"]h$]h&]uh1jhj96ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hj47h]h Description}(hj67hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj27ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMFhj-hhubh)}(hXThese properties are passed to the driver at open as a chain of :c:type:`struct drm_xe_ext_set_property ` structures with property set to these properties' enums and value set to the corresponding values of these properties. :c:type:`struct drm_xe_user_extension ` base.name should be set to ``DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY``.h](h@These properties are passed to the driver at open as a chain of }(hjJ7hhhNhNubh)}(hB:c:type:`struct drm_xe_ext_set_property `h]jC)}(hjT7h]hstruct drm_xe_ext_set_property}(hjV7hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjR7ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_ext_set_propertyuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM4hjJ7ubhz structures with property set to these properties’ enums and value set to the corresponding values of these properties. }(hjJ7hhhNhNubh)}(h>:c:type:`struct drm_xe_user_extension `h]jC)}(hjx7h]hstruct drm_xe_user_extension}(hjz7hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjv7ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_user_extensionuh1hhjq7hM4hjJ7ubh base.name should be set to }(hjJ7hhhNhNubjC)}(h*``DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY``h]h&DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjJ7ubh.}(hjJ7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjq7hM4hj-hhubh)}(hWith the file descriptor obtained from open, user space must enable the EU stall stream fd with ``DRM_XE_OBSERVATION_IOCTL_ENABLE`` before calling read(). EIO errno from read() indicates HW dropped data due to full buffer.h](h`With the file descriptor obtained from open, user space must enable the EU stall stream fd with }(hj7hhhNhNubjC)}(h#``DRM_XE_OBSERVATION_IOCTL_ENABLE``h]hDRM_XE_OBSERVATION_IOCTL_ENABLE}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj7ubh[ before calling read(). EIO errno from read() indicates HW dropped data due to full buffer.}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM:hj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_xe_query_eu_stall (C struct)c.drm_xe_query_eu_stallhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_query_eu_stallh]jg)}(hstruct drm_xe_query_eu_stallh](jm)}(hjph]hstruct}(hj7hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj7hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMBubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj7hhhj7hMBubj)}(hdrm_xe_query_eu_stallh]j)}(hj7h]hdrm_xe_query_eu_stall}(hj 8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj7hhhj7hMBubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj7hhhj7hMBubah}(h]j7ah ](jjeh"]h$]h&]jj)jhuh1j`hj7hMBhj7hhubj)}(hhh]h)}(h$Information about EU stall sampling.h]h$Information about EU stall sampling.}(hj-8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMWhj*8hhubah}(h]h ]h"]h$]h&]uh1jhj7hhhj7hMBubeh}(h]h ](jstructeh"]h$]h&]jjjjE8jjE8jjjuh1j[hhhj-hNhNubj)}(hX#**Definition**:: struct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``capabilities`` EU stall capabilities bit-mask ``record_size`` size of each EU stall data record ``per_xecore_buf_size`` internal per XeCore buffer size ``reserved`` Reserved ``num_sampling_rates`` Number of sampling rates in **sampling_rates** array ``sampling_rates`` Flexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjQ8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM8ubh:}(hjM8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM[hjI8ubj)}(hXstruct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; };h]hXstruct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; };}hjj8sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM]hjI8ubh)}(h **Members**h]j)}(hj{8h]hMembers}(hj}8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy8ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhhjI8ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj8h]h extensions}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj8ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM_hj8ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hM_hj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hM_hj8ubj)}(h0``capabilities`` EU stall capabilities bit-mask h](j)}(h``capabilities``h]jC)}(hj8h]h capabilities}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj8ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMbhj8ubj)}(hhh]h)}(hEU stall capabilities bit-maskh]hEU stall capabilities bit-mask}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMbhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMbhj8ubj)}(h2``record_size`` size of each EU stall data record h](j)}(h``record_size``h]jC)}(hj 9h]h record_size}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj 9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMfhj9ubj)}(hhh]h)}(h!size of each EU stall data recordh]h!size of each EU stall data record}(hj%9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!9hMfhj"9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj!9hMfhj8ubj)}(h8``per_xecore_buf_size`` internal per XeCore buffer size h](j)}(h``per_xecore_buf_size``h]jC)}(hjE9h]hper_xecore_buf_size}(hjG9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjC9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMihj?9ubj)}(hhh]h)}(hinternal per XeCore buffer sizeh]hinternal per XeCore buffer size}(hj^9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ9hMihj[9ubah}(h]h ]h"]h$]h&]uh1jhj?9ubeh}(h]h ]h"]h$]h&]uh1jhjZ9hMihj8ubj)}(h``reserved`` Reserved h](j)}(h ``reserved``h]jC)}(hj~9h]hreserved}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj|9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMlhjx9ubj)}(hhh]h)}(hReservedh]hReserved}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMlhj9ubah}(h]h ]h"]h$]h&]uh1jhjx9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMlhj8ubj)}(hL``num_sampling_rates`` Number of sampling rates in **sampling_rates** array h](j)}(h``num_sampling_rates``h]jC)}(hj9h]hnum_sampling_rates}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMohj9ubj)}(hhh]h)}(h4Number of sampling rates in **sampling_rates** arrayh](hNumber of sampling rates in }(hj9hhhNhNubj)}(h**sampling_rates**h]hsampling_rates}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubh array}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj9hMohj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMohj8ubj)}(h``sampling_rates`` Flexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h](j)}(h``sampling_rates``h]jC)}(hj:h]hsampling_rates}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj:ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMthj9ubj)}(hhh]h)}(hzFlexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h]hzFlexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMshj:ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj:hMthj8ubeh}(h]h ]h"]h$]h&]uh1jhjI8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjE:h]h Description}(hjG:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC:ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMxhj-hhubh)}(hIf a query is made with a :c:type:`struct drm_xe_device_query ` where .query is equal to ``DRM_XE_DEVICE_QUERY_EU_STALL``, then the reply uses :c:type:`struct drm_xe_query_eu_stall ` in .data.h](hIf a query is made with a }(hj[:hhhNhNubh)}(h::c:type:`struct drm_xe_device_query `h]jC)}(hje:h]hstruct drm_xe_device_query}(hjg:hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjc:ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_device_queryuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMXhj[:ubh where .query is equal to }(hj[:hhhNhNubjC)}(h ``DRM_XE_DEVICE_QUERY_EU_STALL``h]hDRM_XE_DEVICE_QUERY_EU_STALL}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj[:ubh, then the reply uses }(hj[:hhhNhNubh)}(h>:c:type:`struct drm_xe_query_eu_stall `h]jC)}(hj:h]hstruct drm_xe_query_eu_stall}(hj:hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj:ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_xe_query_eu_stalluh1hhj:hMXhj[:ubh in .data.}(hj[:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj:hMXhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_xe_madvise (C struct)c.drm_xe_madvisehNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_madviseh]jg)}(hstruct drm_xe_madviseh](jm)}(hjph]hstruct}(hj:hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj:hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM_ubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj:hhhj:hM_ubj)}(hdrm_xe_madviseh]j)}(hj:h]hdrm_xe_madvise}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj:hhhj:hM_ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj:hhhj:hM_ubah}(h]j:ah ](jjeh"]h$]h&]jj)jhuh1j`hj:hM_hj:hhubj)}(hhh]h)}(h'Input of :c:type:`DRM_IOCTL_XE_MADVISE`h](h Input of }(hj;hhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_MADVISE`h]jC)}(hj';h]hDRM_IOCTL_XE_MADVISE}(hj);hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj%;ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jj:sbc.drm_xe_madviseasbjDRM_IOCTL_XE_MADVISEuh1hhjhKhj;ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMzhj;hhubah}(h]h ]h"]h$]h&]uh1jhj:hhhj:hM_ubeh}(h]h ](jstructeh"]h$]h&]jjjj[;jj[;jjjuh1j[hhhj-hNhNubj)}(hX **Definition**:: struct drm_xe_madvise { __u64 extensions; __u64 start; __u64 range; __u32 vm_id; #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0; #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1; #define DRM_XE_MEM_RANGE_ATTR_PAT 2; #define DRM_XE_VMA_ATTR_PURGEABLE_STATE 3; __u32 type; union { struct { #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0; #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1; __u32 devmem_fd; #define DRM_XE_MIGRATE_ALL_PAGES 0; #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1; __u16 migration_policy; __u16 region_instance; __u64 reserved; } preferred_mem_loc; struct { #define DRM_XE_ATOMIC_UNDEFINED 0; #define DRM_XE_ATOMIC_DEVICE 1; #define DRM_XE_ATOMIC_GLOBAL 2; #define DRM_XE_ATOMIC_CPU 3; __u32 val; __u32 pad; __u64 reserved; } atomic; struct { __u32 val; __u32 pad; __u64 reserved; } pat_index; struct { #define DRM_XE_VMA_PURGEABLE_STATE_WILLNEED 0; #define DRM_XE_VMA_PURGEABLE_STATE_DONTNEED 1; __u32 val; __u32 pad; __u64 retained_ptr; } purge_state_val; }; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``start`` start of the virtual address range ``range`` size of the virtual address range ``vm_id`` vm_id of the virtual range ``type`` type of attribute ``{unnamed_union}`` anonymous ``preferred_mem_loc`` preferred memory location Used when **type** == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC Supported values for **preferred_mem_loc.devmem_fd**: - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc Supported values for **preferred_mem_loc.migration_policy**: - DRM_XE_MIGRATE_ALL_PAGES - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES ``preferred_mem_loc.devmem_fd`` Device file-descriptor of the device where the preferred memory is located, or one of the above special values. Please also see **preferred_mem_loc.region_instance** below. ``preferred_mem_loc.migration_policy`` Page migration policy ``preferred_mem_loc.region_instance`` Region instance. MBZ if **devmem_fd** <= ``DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE``. Otherwise should point to the desired device VRAM instance of the device indicated by **preferred_mem_loc.devmem_fd**. ``preferred_mem_loc.reserved`` Reserved ``atomic`` Atomic access policy Used when **type** == DRM_XE_MEM_RANGE_ATTR_ATOMIC. Supported values for **atomic.val**: - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. Support both GPU and CPU atomic operations for system allocator. Support GPU atomic operations for normal(bo) allocator. - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations. - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations. - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported. ``atomic.val`` value of atomic operation ``atomic.pad`` MBZ ``atomic.reserved`` Reserved ``pat_index`` Page attribute table index Used when **type** == DRM_XE_MEM_RANGE_ATTR_PAT. ``pat_index.val`` PAT index value ``pat_index.pad`` MBZ ``pat_index.reserved`` Reserved ``purge_state_val`` Purgeable state configuration Used when **type** == DRM_XE_VMA_ATTR_PURGEABLE_STATE. Configures the purgeable state of buffer objects in the specified virtual address range. This allows applications to hint to the kernel about bo's usage patterns for better memory management. By default all VMAs are in WILLNEED state. Supported values for **purge_state_val.val**: - DRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed. If the BO was previously purged, the kernel sets the __u32 at **retained_ptr** to 0 (backing store lost) so the application knows it must recreate the BO. - DRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at **retained_ptr** to 1 if the backing store still exists (not yet purged), or 0 if it was already purged. Important: Once marked as DONTNEED, touching the BO's memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state. To transition back: use WILLNEED and check **retained_ptr** — if 0, backing store was lost and the BO must be recreated. The following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCES ``purge_state_val.val`` value for DRM_XE_VMA_ATTR_PURGEABLE_STATE ``purge_state_val.pad`` MBZ ``purge_state_val.retained_ptr`` Pointer to a __u32 output field for backing store status. Userspace must initialize the __u32 value at this address to 0 before the ioctl. Kernel writes a __u32 after the operation: - 1 if backing store exists (not purged) - 0 if backing store was purged If userspace fails to initialize to 0, ioctl returns -EINVAL. This ensures a safe default (0 = assume purged) if kernel cannot write the result. Similar to i915's drm_i915_gem_madvise.retained field. ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjg;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc;ubh:}(hjc;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM~hj_;ubj)}(hX-struct drm_xe_madvise { __u64 extensions; __u64 start; __u64 range; __u32 vm_id; #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0; #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1; #define DRM_XE_MEM_RANGE_ATTR_PAT 2; #define DRM_XE_VMA_ATTR_PURGEABLE_STATE 3; __u32 type; union { struct { #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0; #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1; __u32 devmem_fd; #define DRM_XE_MIGRATE_ALL_PAGES 0; #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1; __u16 migration_policy; __u16 region_instance; __u64 reserved; } preferred_mem_loc; struct { #define DRM_XE_ATOMIC_UNDEFINED 0; #define DRM_XE_ATOMIC_DEVICE 1; #define DRM_XE_ATOMIC_GLOBAL 2; #define DRM_XE_ATOMIC_CPU 3; __u32 val; __u32 pad; __u64 reserved; } atomic; struct { __u32 val; __u32 pad; __u64 reserved; } pat_index; struct { #define DRM_XE_VMA_PURGEABLE_STATE_WILLNEED 0; #define DRM_XE_VMA_PURGEABLE_STATE_DONTNEED 1; __u32 val; __u32 pad; __u64 retained_ptr; } purge_state_val; }; __u64 reserved[2]; };h]hX-struct drm_xe_madvise { __u64 extensions; __u64 start; __u64 range; __u32 vm_id; #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0; #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1; #define DRM_XE_MEM_RANGE_ATTR_PAT 2; #define DRM_XE_VMA_ATTR_PURGEABLE_STATE 3; __u32 type; union { struct { #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0; #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1; __u32 devmem_fd; #define DRM_XE_MIGRATE_ALL_PAGES 0; #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1; __u16 migration_policy; __u16 region_instance; __u64 reserved; } preferred_mem_loc; struct { #define DRM_XE_ATOMIC_UNDEFINED 0; #define DRM_XE_ATOMIC_DEVICE 1; #define DRM_XE_ATOMIC_GLOBAL 2; #define DRM_XE_ATOMIC_CPU 3; __u32 val; __u32 pad; __u64 reserved; } atomic; struct { __u32 val; __u32 pad; __u64 reserved; } pat_index; struct { #define DRM_XE_VMA_PURGEABLE_STATE_WILLNEED 0; #define DRM_XE_VMA_PURGEABLE_STATE_DONTNEED 1; __u32 val; __u32 pad; __u64 retained_ptr; } purge_state_val; }; __u64 reserved[2]; };}hj;sbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj_;ubh)}(h **Members**h]j)}(hj;h]hMembers}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj_;ubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hj;h]h extensions}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj;ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj;ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj;ubj)}(h-``start`` start of the virtual address range h](j)}(h ``start``h]jC)}(hj;h]hstart}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj;ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj;ubj)}(hhh]h)}(h"start of the virtual address rangeh]h"start of the virtual address range}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj;ubj)}(h,``range`` size of the virtual address range h](j)}(h ``range``h]jC)}(hj"<h]hrange}(hj$<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj <ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj<ubj)}(hhh]h)}(h!size of the virtual address rangeh]h!size of the virtual address range}(hj;<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7<hMhj8<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj7<hMhj;ubj)}(h%``vm_id`` vm_id of the virtual range h](j)}(h ``vm_id``h]jC)}(hj[<h]hvm_id}(hj]<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjY<ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjU<ubj)}(hhh]h)}(hvm_id of the virtual rangeh]hvm_id of the virtual range}(hjt<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp<hMhjq<ubah}(h]h ]h"]h$]h&]uh1jhjU<ubeh}(h]h ]h"]h$]h&]uh1jhjp<hMhj;ubj)}(h``type`` type of attribute h](j)}(h``type``h]jC)}(hj<h]htype}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj<ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj<ubj)}(hhh]h)}(htype of attributeh]htype of attribute}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj;ubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]jC)}(hj<h]h{unnamed_union}}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj<ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhKhj<ubj)}(hhh]h)}(h anonymoush]h anonymous}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hKhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hKhj;ubj)}(hX``preferred_mem_loc`` preferred memory location Used when **type** == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC Supported values for **preferred_mem_loc.devmem_fd**: - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc Supported values for **preferred_mem_loc.migration_policy**: - DRM_XE_MIGRATE_ALL_PAGES - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES h](j)}(h``preferred_mem_loc``h]jC)}(hj=h]hpreferred_mem_loc}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj=ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj=ubj)}(hhh](h)}(hpreferred memory locationh]hpreferred memory location}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj=ubh)}(h9Used when **type** == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOCh](h Used when }(hj.=hhhNhNubj)}(h**type**h]htype}(hj6=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.=ubh' == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC}(hj.=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj=ubj)}(hhh](j)}(hSupported values for **preferred_mem_loc.devmem_fd**: - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc h](j)}(h5Supported values for **preferred_mem_loc.devmem_fd**:h](hSupported values for }(hjV=hhhNhNubj)}(h**preferred_mem_loc.devmem_fd**h]hpreferred_mem_loc.devmem_fd}(hj^=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjV=ubh:}(hjV=hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjR=ubj)}(hhh]h)}(hhh](h)}(hLDRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loch]h)}(hj=h]hLDRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj}=ubah}(h]h ]h"]h$]h&]uh1hhjz=ubh)}(h?DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc h]h)}(h>DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loch]h>DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv=hMhj=ubah}(h]h ]h"]h$]h&]uh1hhjz=ubeh}(h]h ]h"]h$]h&]j j uh1hhj=hMhjw=ubah}(h]h ]h"]h$]h&]uh1jhjR=ubeh}(h]h ]h"]h$]h&]uh1jhjv=hMhjO=ubj)}(h{Supported values for **preferred_mem_loc.migration_policy**: - DRM_XE_MIGRATE_ALL_PAGES - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES h](j)}(hhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMhj>ubah}(h]h ]h"]h$]h&]uh1hhj=ubeh}(h]h ]h"]h$]h&]j j uh1hhj=hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhjO=ubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj;ubj)}(h``preferred_mem_loc.devmem_fd`` Device file-descriptor of the device where the preferred memory is located, or one of the above special values. Please also see **preferred_mem_loc.region_instance** below. h](j)}(h``preferred_mem_loc.devmem_fd``h]jC)}(hjC>h]hpreferred_mem_loc.devmem_fd}(hjE>hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjA>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj=>ubj)}(hhh]h)}(hDevice file-descriptor of the device where the preferred memory is located, or one of the above special values. Please also see **preferred_mem_loc.region_instance** below.h](hDevice file-descriptor of the device where the preferred memory is located, or one of the above special values. Please also see }(hj\>hhhNhNubj)}(h%**preferred_mem_loc.region_instance**h]h!preferred_mem_loc.region_instance}(hjd>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\>ubh below.}(hj\>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjY>ubah}(h]h ]h"]h$]h&]uh1jhj=>ubeh}(h]h ]h"]h$]h&]uh1jhjX>hMhj;ubj)}(h=``preferred_mem_loc.migration_policy`` Page migration policy h](j)}(h&``preferred_mem_loc.migration_policy``h]jC)}(hj>h]h"preferred_mem_loc.migration_policy}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj>ubj)}(hhh]h)}(hPage migration policyh]hPage migration policy}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhj;ubj)}(h``preferred_mem_loc.region_instance`` Region instance. MBZ if **devmem_fd** <= ``DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE``. Otherwise should point to the desired device VRAM instance of the device indicated by **preferred_mem_loc.devmem_fd**. h](j)}(h%``preferred_mem_loc.region_instance``h]jC)}(hj>h]h!preferred_mem_loc.region_instance}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj>ubj)}(hhh]h)}(hRegion instance. MBZ if **devmem_fd** <= ``DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE``. Otherwise should point to the desired device VRAM instance of the device indicated by **preferred_mem_loc.devmem_fd**.h](hRegion instance. MBZ if }(hj>hhhNhNubj)}(h **devmem_fd**h]h devmem_fd}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubh <= }(hj>hhhNhNubjC)}(h'``DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE``h]h#DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj>ubhX. Otherwise should point to the desired device VRAM instance of the device indicated by }(hj>hhhNhNubj)}(h**preferred_mem_loc.devmem_fd**h]hpreferred_mem_loc.devmem_fd}(hj ?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubh.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhj;ubj)}(h(``preferred_mem_loc.reserved`` Reserved h](j)}(h``preferred_mem_loc.reserved``h]jC)}(hj8?h]hpreferred_mem_loc.reserved}(hj:?hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj6?ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj2?ubj)}(hhh]h)}(hReservedh]hReserved}(hjQ?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM?hMhjN?ubah}(h]h ]h"]h$]h&]uh1jhj2?ubeh}(h]h ]h"]h$]h&]uh1jhjM?hMhj;ubj)}(hX``atomic`` Atomic access policy Used when **type** == DRM_XE_MEM_RANGE_ATTR_ATOMIC. Supported values for **atomic.val**: - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. Support both GPU and CPU atomic operations for system allocator. Support GPU atomic operations for normal(bo) allocator. - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations. - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations. - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported. h](j)}(h ``atomic``h]jC)}(hjq?h]hatomic}(hjs?hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjo?ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjk?ubj)}(hhh](h)}(hAtomic access policyh]hAtomic access policy}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj?ubh)}(h3Used when **type** == DRM_XE_MEM_RANGE_ATTR_ATOMIC.h](h Used when }(hj?hhhNhNubj)}(h**type**h]htype}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh! == DRM_XE_MEM_RANGE_ATTR_ATOMIC.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj?ubj)}(hhh]j)}(hXSupported values for **atomic.val**: - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. Support both GPU and CPU atomic operations for system allocator. Support GPU atomic operations for normal(bo) allocator. - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations. - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations. - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported. h](j)}(h$Supported values for **atomic.val**:h](hSupported values for }(hj?hhhNhNubj)}(h**atomic.val**h]h atomic.val}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh:}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj?ubj)}(hhh]h)}(hhh](h)}(hDRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. Support both GPU and CPU atomic operations for system allocator. Support GPU atomic operations for normal(bo) allocator.h]h)}(hDRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. Support both GPU and CPU atomic operations for system allocator. Support GPU atomic operations for normal(bo) allocator.h]hDRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. Support both GPU and CPU atomic operations for system allocator. Support GPU atomic operations for normal(bo) allocator.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj?ubah}(h]h ]h"]h$]h&]uh1hhj?ubh)}(h4DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations.h]h)}(hj@h]h4DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj@ubah}(h]h ]h"]h$]h&]uh1hhj?ubh)}(hADRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations.h]h)}(hj@h]hADRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj@ubah}(h]h ]h"]h$]h&]uh1hhj?ubh)}(hFDRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported. h]h)}(hEDRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported.h]hEDRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported.}(hj4@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj0@ubah}(h]h ]h"]h$]h&]uh1hhj?ubeh}(h]h ]h"]h$]h&]j j uh1hhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhjk?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj;ubj)}(h)``atomic.val`` value of atomic operation h](j)}(h``atomic.val``h]jC)}(hjr@h]h atomic.val}(hjt@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjp@ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjl@ubj)}(hhh]h)}(hvalue of atomic operationh]hvalue of atomic operation}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhjl@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj;ubj)}(h``atomic.pad`` MBZ h](j)}(h``atomic.pad``h]jC)}(hj@h]h atomic.pad}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj@ubj)}(hhh]h)}(hMBZh]hMBZ}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj;ubj)}(h``atomic.reserved`` Reserved h](j)}(h``atomic.reserved``h]jC)}(hj@h]hatomic.reserved}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj@ubj)}(hhh]h)}(hReservedh]hReserved}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj;ubj)}(h[``pat_index`` Page attribute table index Used when **type** == DRM_XE_MEM_RANGE_ATTR_PAT. h](j)}(h ``pat_index``h]jC)}(hjAh]h pat_index}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjAubj)}(hhh](h)}(hPage attribute table indexh]hPage attribute table index}(hj6AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj3Aubh)}(h0Used when **type** == DRM_XE_MEM_RANGE_ATTR_PAT.h](h Used when }(hjEAhhhNhNubj)}(h**type**h]htype}(hjMAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEAubh == DRM_XE_MEM_RANGE_ATTR_PAT.}(hjEAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj2AhMhj3Aubeh}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhj2AhMhj;ubj)}(h"``pat_index.val`` PAT index value h](j)}(h``pat_index.val``h]jC)}(hjwAh]h pat_index.val}(hjyAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjuAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjqAubj)}(hhh]h)}(hPAT index valueh]hPAT index value}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhMhjAubah}(h]h ]h"]h$]h&]uh1jhjqAubeh}(h]h ]h"]h$]h&]uh1jhjAhMhj;ubj)}(h``pat_index.pad`` MBZ h](j)}(h``pat_index.pad``h]jC)}(hjAh]h pat_index.pad}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjAubj)}(hhh]h)}(hMBZh]hMBZ}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhMhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhjAhMhj;ubj)}(h ``pat_index.reserved`` Reserved h](j)}(h``pat_index.reserved``h]jC)}(hjAh]hpat_index.reserved}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjAubj)}(hhh]h)}(hReservedh]hReserved}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhMhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhjAhMhj;ubj)}(hXt``purge_state_val`` Purgeable state configuration Used when **type** == DRM_XE_VMA_ATTR_PURGEABLE_STATE. Configures the purgeable state of buffer objects in the specified virtual address range. This allows applications to hint to the kernel about bo's usage patterns for better memory management. By default all VMAs are in WILLNEED state. Supported values for **purge_state_val.val**: - DRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed. If the BO was previously purged, the kernel sets the __u32 at **retained_ptr** to 0 (backing store lost) so the application knows it must recreate the BO. - DRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at **retained_ptr** to 1 if the backing store still exists (not yet purged), or 0 if it was already purged. Important: Once marked as DONTNEED, touching the BO's memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state. To transition back: use WILLNEED and check **retained_ptr** — if 0, backing store was lost and the BO must be recreated. The following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCES h](j)}(h``purge_state_val``h]jC)}(hj"Bh]hpurge_state_val}(hj$BhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj Bubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM' hjBubj)}(hhh](h)}(hPurgeable state configurationh]hPurgeable state configuration}(hj;BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj8Bubh)}(h6Used when **type** == DRM_XE_VMA_ATTR_PURGEABLE_STATE.h](h Used when }(hjJBhhhNhNubj)}(h**type**h]htype}(hjRBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJBubh$ == DRM_XE_VMA_ATTR_PURGEABLE_STATE.}(hjJBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj8Bubh)}(hConfigures the purgeable state of buffer objects in the specified virtual address range. This allows applications to hint to the kernel about bo's usage patterns for better memory management.h]hConfigures the purgeable state of buffer objects in the specified virtual address range. This allows applications to hint to the kernel about bo’s usage patterns for better memory management.}(hjkBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj8Bubh)}(h*By default all VMAs are in WILLNEED state.h]h*By default all VMAs are in WILLNEED state.}(hjzBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj8Bubj)}(hhh]j)}(hXSupported values for **purge_state_val.val**: - DRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed. If the BO was previously purged, the kernel sets the __u32 at **retained_ptr** to 0 (backing store lost) so the application knows it must recreate the BO. - DRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at **retained_ptr** to 1 if the backing store still exists (not yet purged), or 0 if it was already purged. Important: Once marked as DONTNEED, touching the BO's memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state. To transition back: use WILLNEED and check **retained_ptr** — if 0, backing store was lost and the BO must be recreated. The following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCES h](j)}(h-Supported values for **purge_state_val.val**:h](hSupported values for }(hjBhhhNhNubj)}(h**purge_state_val.val**h]hpurge_state_val.val}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubh:}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhj7BhM' hjBubj)}(hhh]h)}(hhh](h)}(hDRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed. If the BO was previously purged, the kernel sets the __u32 at **retained_ptr** to 0 (backing store lost) so the application knows it must recreate the BO. h]h)}(hDRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed. If the BO was previously purged, the kernel sets the __u32 at **retained_ptr** to 0 (backing store lost) so the application knows it must recreate the BO.h](h{DRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed. If the BO was previously purged, the kernel sets the __u32 at }(hjBhhhNhNubj)}(h**retained_ptr**h]h retained_ptr}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubhL to 0 (backing store lost) so the application knows it must recreate the BO.}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjBubah}(h]h ]h"]h$]h&]uh1hhjBubh)}(hXDRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at **retained_ptr** to 1 if the backing store still exists (not yet purged), or 0 if it was already purged. Important: Once marked as DONTNEED, touching the BO's memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state. To transition back: use WILLNEED and check **retained_ptr** — if 0, backing store was lost and the BO must be recreated. The following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCES h](h)}(hX-DRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at **retained_ptr** to 1 if the backing store still exists (not yet purged), or 0 if it was already purged.h](hDRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at }(hjBhhhNhNubj)}(h**retained_ptr**h]h retained_ptr}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubhX to 1 if the backing store still exists (not yet purged), or 0 if it was already purged.}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjBubh)}(hImportant: Once marked as DONTNEED, touching the BO's memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state.h]hImportant: Once marked as DONTNEED, touching the BO’s memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjBubh)}(hzTo transition back: use WILLNEED and check **retained_ptr** — if 0, backing store was lost and the BO must be recreated.h](h+To transition back: use WILLNEED and check }(hjChhhNhNubj)}(h**retained_ptr**h]h retained_ptr}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubh? — if 0, backing store was lost and the BO must be recreated.}(hjChhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjBubh)}(hXJThe following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCESh]hXJThe following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCES}(hj6ChhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM! hjBubeh}(h]h ]h"]h$]h&]uh1hhjBubeh}(h]h ]h"]h$]h&]j j uh1hhjBhM hjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhj7BhM' hjBubah}(h]h ]h"]h$]h&]uh1jhj8Bubeh}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhj7BhM' hj;ubj)}(hB``purge_state_val.val`` value for DRM_XE_VMA_ATTR_PURGEABLE_STATE h](j)}(h``purge_state_val.val``h]jC)}(hjuCh]hpurge_state_val.val}(hjwChhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjsCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM, hjoCubj)}(hhh]h)}(h)value for DRM_XE_VMA_ATTR_PURGEABLE_STATEh]h)value for DRM_XE_VMA_ATTR_PURGEABLE_STATE}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChM, hjCubah}(h]h ]h"]h$]h&]uh1jhjoCubeh}(h]h ]h"]h$]h&]uh1jhjChM, hj;ubj)}(h``purge_state_val.pad`` MBZ h](j)}(h``purge_state_val.pad``h]jC)}(hjCh]hpurge_state_val.pad}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM/ hjCubj)}(hhh]h)}(hMBZh]hMBZ}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChM/ hjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhjChM/ hj;ubj)}(hX``purge_state_val.retained_ptr`` Pointer to a __u32 output field for backing store status. Userspace must initialize the __u32 value at this address to 0 before the ioctl. Kernel writes a __u32 after the operation: - 1 if backing store exists (not purged) - 0 if backing store was purged If userspace fails to initialize to 0, ioctl returns -EINVAL. This ensures a safe default (0 = assume purged) if kernel cannot write the result. Similar to i915's drm_i915_gem_madvise.retained field. h](j)}(h ``purge_state_val.retained_ptr``h]jC)}(hjCh]hpurge_state_val.retained_ptr}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM? hjCubj)}(hhh](h)}(h9Pointer to a __u32 output field for backing store status.h]h9Pointer to a __u32 output field for backing store status.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM2 hjCubh)}(hUserspace must initialize the __u32 value at this address to 0 before the ioctl. Kernel writes a __u32 after the operation: - 1 if backing store exists (not purged) - 0 if backing store was purgedh]hUserspace must initialize the __u32 value at this address to 0 before the ioctl. Kernel writes a __u32 after the operation: - 1 if backing store exists (not purged) - 0 if backing store was purged}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM5 hjCubh)}(hIf userspace fails to initialize to 0, ioctl returns -EINVAL. This ensures a safe default (0 = assume purged) if kernel cannot write the result.2h]hIf userspace fails to initialize to 0, ioctl returns -EINVAL. This ensures a safe default (0 = assume purged) if kernel cannot write the result.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM; hjCubh)}(h6Similar to i915's drm_i915_gem_madvise.retained field.h]h8Similar to i915’s drm_i915_gem_madvise.retained field.}(hj-DhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChM? hjCubeh}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhjChM? hj;ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hjMDh]hreserved}(hjODhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjKDubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMD hjGDubj)}(hhh]h)}(hReservedh]hReserved}(hjfDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhME hjcDubah}(h]h ]h"]h$]h&]uh1jhjGDubeh}(h]h ]h"]h$]h&]uh1jhjbDhMD hj;ubeh}(h]h ]h"]h$]h&]uh1jhj_;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjDh]h Description}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMH hj-hhubh)}(hThis structure is used to set memory attributes for a virtual address range in a VM. The type of attribute is specified by **type**, and the corresponding union member is used to provide additional parameters for **type**.h](h{This structure is used to set memory attributes for a virtual address range in a VM. The type of attribute is specified by }(hjDhhhNhNubj)}(h**type**h]htype}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubhR, and the corresponding union member is used to provide additional parameters for }(hjDhhhNhNubj)}(h**type**h]htype}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubh.}(hjDhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM{hj-hhubj)}(hhh]j)}(hXSupported attribute types: - DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location. - DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy. - DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index. - DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs. h](j)}(hSupported attribute types:h]hSupported attribute types:}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjDubj)}(hhh]h)}(hhh](h)}(hCDRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location.h]h)}(hjDh]hCDRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhjDubah}(h]h ]h"]h$]h&]uh1hhjDubh)}(h7DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy.h]h)}(hjEh]h7DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj Eubah}(h]h ]h"]h$]h&]uh1hhjDubh)}(h:DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index.h]h)}(hj'Eh]h:DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index.}(hj)EhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj%Eubah}(h]h ]h"]h$]h&]uh1hhjDubh)}(h>DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs. h]h)}(h=DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs.h]h=DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs.}(hjAEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhj=Eubah}(h]h ]h"]h$]h&]uh1hhjDubeh}(h]h ]h"]h$]h&]j j uh1hhjEhMhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjDubah}(h]h ]h"]h$]h&]uh1jhj-hhhNhNubh)}(h **Example**h]j)}(hjoEh]hExample}(hjqEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmEubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubj)}(hstruct drm_xe_madvise madvise = { .vm_id = vm_id, .start = 0x100000, .range = 0x2000, .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC, .atomic.val = DRM_XE_ATOMIC_DEVICE, }; ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise);h]hstruct drm_xe_madvise madvise = { .vm_id = vm_id, .start = 0x100000, .range = 0x2000, .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC, .atomic.val = DRM_XE_ATOMIC_DEVICE, }; ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise);}hjEsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMhj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_xe_mem_range_attr (C struct)c.drm_xe_mem_range_attrhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_mem_range_attrh]jg)}(hstruct drm_xe_mem_range_attrh](jm)}(hjph]hstruct}(hjEhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjEhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjEhhhjEhMubj)}(hdrm_xe_mem_range_attrh]j)}(hjEh]hdrm_xe_mem_range_attr}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ](jjeh"]h$]h&]jjuh1jhjEhhhjEhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjEhhhjEhMubah}(h]jEah ](jjeh"]h$]h&]jj)jhuh1j`hjEhMhjEhhubj)}(hhh]h)}(h9Output of :c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS`h](h Output of }(hjEhhhNhNubh)}(h/:c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS`h]jC)}(hjEh]h%DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS}(hjEhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhjEubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjEsbc.drm_xe_mem_range_attrasbj%DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRSuh1hhjhKhjEubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMI hjEhhubah}(h]h ]h"]h$]h&]uh1jhjEhhhjEhMubeh}(h]h ](jstructeh"]h$]h&]jjjj.Fjj.Fjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_mem_range_attr { __u64 extensions; __u64 start; __u64 end; struct { __u32 devmem_fd; __u32 migration_policy; } preferred_mem_loc; struct { __u32 val; __u32 reserved; } atomic; struct { __u32 val; __u32 reserved; } pat_index; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``start`` start of the memory range ``end`` end of the memory range ``preferred_mem_loc`` preferred memory location ``preferred_mem_loc.devmem_fd`` fd for preferred loc ``preferred_mem_loc.migration_policy`` Page migration policy ``atomic`` Atomic access policy ``atomic.val`` atomic attribute ``atomic.reserved`` Reserved ``pat_index`` Page attribute table index ``pat_index.val`` PAT index ``pat_index.reserved`` Reserved ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj:FhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6Fubh:}(hj6FhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMM hj2Fubj)}(hX\struct drm_xe_mem_range_attr { __u64 extensions; __u64 start; __u64 end; struct { __u32 devmem_fd; __u32 migration_policy; } preferred_mem_loc; struct { __u32 val; __u32 reserved; } atomic; struct { __u32 val; __u32 reserved; } pat_index; __u64 reserved[2]; };h]hX\struct drm_xe_mem_range_attr { __u64 extensions; __u64 start; __u64 end; struct { __u32 devmem_fd; __u32 migration_policy; } preferred_mem_loc; struct { __u32 val; __u32 reserved; } atomic; struct { __u32 val; __u32 reserved; } pat_index; __u64 reserved[2]; };}hjSFsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMO hj2Fubh)}(h **Members**h]j)}(hjdFh]hMembers}(hjfFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbFubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMb hj2Fubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjFh]h extensions}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjFubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMV hj}Fubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhMV hjFubah}(h]h ]h"]h$]h&]uh1jhj}Fubeh}(h]h ]h"]h$]h&]uh1jhjFhMV hjzFubj)}(h$``start`` start of the memory range h](j)}(h ``start``h]jC)}(hjFh]hstart}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjFubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMY hjFubj)}(hhh]h)}(hstart of the memory rangeh]hstart of the memory range}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhMY hjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhjFhMY hjzFubj)}(h ``end`` end of the memory range h](j)}(h``end``h]jC)}(hjFh]hend}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjFubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM\ hjFubj)}(hhh]h)}(hend of the memory rangeh]hend of the memory range}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj GhM\ hj Gubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhj GhM\ hjzFubj)}(h0``preferred_mem_loc`` preferred memory location h](j)}(h``preferred_mem_loc``h]jC)}(hj.Gh]hpreferred_mem_loc}(hj0GhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,Gubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM_ hj(Gubj)}(hhh]h)}(hpreferred memory locationh]hpreferred memory location}(hjGGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCGhM_ hjDGubah}(h]h ]h"]h$]h&]uh1jhj(Gubeh}(h]h ]h"]h$]h&]uh1jhjCGhM_ hjzFubj)}(h5``preferred_mem_loc.devmem_fd`` fd for preferred loc h](j)}(h``preferred_mem_loc.devmem_fd``h]jC)}(hjgGh]hpreferred_mem_loc.devmem_fd}(hjiGhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjeGubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMa hjaGubj)}(hhh]h)}(hfd for preferred loch]hfd for preferred loc}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|GhMa hj}Gubah}(h]h ]h"]h$]h&]uh1jhjaGubeh}(h]h ]h"]h$]h&]uh1jhj|GhMa hjzFubj)}(h=``preferred_mem_loc.migration_policy`` Page migration policy h](j)}(h&``preferred_mem_loc.migration_policy``h]jC)}(hjGh]h"preferred_mem_loc.migration_policy}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjGubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMd hjGubj)}(hhh]h)}(hPage migration policyh]hPage migration policy}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMd hjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjGhMd hjzFubj)}(h ``atomic`` Atomic access policy h](j)}(h ``atomic``h]jC)}(hjGh]hatomic}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjGubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMh hjGubj)}(hhh]h)}(hAtomic access policyh]hAtomic access policy}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMh hjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjGhMh hjzFubj)}(h ``atomic.val`` atomic attribute h](j)}(h``atomic.val``h]jC)}(hjHh]h atomic.val}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMj hj Hubj)}(hhh]h)}(hatomic attributeh]hatomic attribute}(hj+HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'HhMj hj(Hubah}(h]h ]h"]h$]h&]uh1jhj Hubeh}(h]h ]h"]h$]h&]uh1jhj'HhMj hjzFubj)}(h``atomic.reserved`` Reserved h](j)}(h``atomic.reserved``h]jC)}(hjKHh]hatomic.reserved}(hjMHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjIHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMm hjEHubj)}(hhh]h)}(hReservedh]hReserved}(hjdHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`HhMm hjaHubah}(h]h ]h"]h$]h&]uh1jhjEHubeh}(h]h ]h"]h$]h&]uh1jhj`HhMm hjzFubj)}(h)``pat_index`` Page attribute table index h](j)}(h ``pat_index``h]jC)}(hjHh]h pat_index}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMq hj~Hubj)}(hhh]h)}(hPage attribute table indexh]hPage attribute table index}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMq hjHubah}(h]h ]h"]h$]h&]uh1jhj~Hubeh}(h]h ]h"]h$]h&]uh1jhjHhMq hjzFubj)}(h``pat_index.val`` PAT index h](j)}(h``pat_index.val``h]jC)}(hjHh]h pat_index.val}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMs hjHubj)}(hhh]h)}(h PAT indexh]h PAT index}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMs hjHubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhjHhMs hjzFubj)}(h ``pat_index.reserved`` Reserved h](j)}(h``pat_index.reserved``h]jC)}(hjHh]hpat_index.reserved}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMv hjHubj)}(hhh]h)}(hReservedh]hReserved}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj IhMv hj Iubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhj IhMv hjzFubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hj/Ih]hreserved}(hj1IhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj-Iubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMy hj)Iubj)}(hhh]h)}(hReservedh]hReserved}(hjHIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMz hjEIubah}(h]h ]h"]h$]h&]uh1jhj)Iubeh}(h]h ]h"]h$]h&]uh1jhjDIhMy hjzFubeh}(h]h ]h"]h$]h&]uh1jhj2Fubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubh)}(h**Description**h]j)}(hjrIh]h Description}(hjtIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpIubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM} hj-hhubh)}(hThis structure is provided by userspace and filled by KMD in response to the DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS ioctl. It describes memory attributes of memory ranges within a user specified address range in a VM.h]hThis structure is provided by userspace and filled by KMD in response to the DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS ioctl. It describes memory attributes of memory ranges within a user specified address range in a VM.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMJ hj-hhubh)}(hXThe structure includes information such as atomic access policy, page attribute table (PAT) index, and preferred memory location. Userspace allocates an array of these structures and passes a pointer to the ioctl to retrieve attributes for each memory range.h]hXThe structure includes information such as atomic access policy, page attribute table (PAT) index, and preferred memory location. Userspace allocates an array of these structures and passes a pointer to the ioctl to retrieve attributes for each memory range.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMN hj-hhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW)drm_xe_vm_query_mem_range_attr (C struct) c.drm_xe_vm_query_mem_range_attrhNtauh1jJhj-hhhNhNubj\)}(hhh](ja)}(hdrm_xe_vm_query_mem_range_attrh]jg)}(h%struct drm_xe_vm_query_mem_range_attrh](jm)}(hjph]hstruct}(hjIhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjIhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhMV ubj)}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjIhhhjIhMV ubj)}(hdrm_xe_vm_query_mem_range_attrh]j)}(hjIh]hdrm_xe_vm_query_mem_range_attr}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubah}(h]h ](jjeh"]h$]h&]jjuh1jhjIhhhjIhMV ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjIhhhjIhMV ubah}(h]jIah ](jjeh"]h$]h&]jj)jhuh1j`hjIhMV hjIhhubj)}(hhh]h)}(h8Input of :c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS`h](h Input of }(hjJhhhNhNubh)}(h/:c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS`h]jC)}(hj Jh]h%DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS}(hj JhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jBhj Jubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj)}j]j)}jjIsb c.drm_xe_vm_query_mem_range_attrasbj%DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRSuh1hhjhKhjJubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM~ hjIhhubah}(h]h ]h"]h$]h&]uh1jhjIhhhjIhMV ubeh}(h]h ](jstructeh"]h$]h&]jjjj?Jjj?Jjjjuh1j[hhhj-hNhNubj)}(hX**Definition**:: struct drm_xe_vm_query_mem_range_attr { __u64 extensions; __u32 vm_id; __u32 num_mem_ranges; __u64 start; __u64 range; __u64 sizeof_mem_range_attr; __u64 vector_of_mem_attr; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``vm_id`` vm_id of the virtual range ``num_mem_ranges`` number of mem_ranges in range ``start`` start of the virtual address range ``range`` size of the virtual address range ``sizeof_mem_range_attr`` size of struct drm_xe_mem_range_attr ``vector_of_mem_attr`` userptr to array of struct drm_xe_mem_range_attr ``reserved`` Reservedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjKJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGJubh:}(hjGJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjCJubj)}(hstruct drm_xe_vm_query_mem_range_attr { __u64 extensions; __u32 vm_id; __u32 num_mem_ranges; __u64 start; __u64 range; __u64 sizeof_mem_range_attr; __u64 vector_of_mem_attr; __u64 reserved[2]; };h]hstruct drm_xe_vm_query_mem_range_attr { __u64 extensions; __u32 vm_id; __u32 num_mem_ranges; __u64 start; __u64 range; __u64 sizeof_mem_range_attr; __u64 vector_of_mem_attr; __u64 reserved[2]; };}hjdJsbah}(h]h ]h"]h$]h&]jjuh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjCJubh)}(h **Members**h]j)}(hjuJh]hMembers}(hjwJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsJubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjCJubj)}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]jC)}(hjJh]h extensions}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjJubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjJubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhM hjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjJhM hjJubj)}(h%``vm_id`` vm_id of the virtual range h](j)}(h ``vm_id``h]jC)}(hjJh]hvm_id}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjJubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjJubj)}(hhh]h)}(hvm_id of the virtual rangeh]hvm_id of the virtual range}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhM hjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjJhM hjJubj)}(h1``num_mem_ranges`` number of mem_ranges in range h](j)}(h``num_mem_ranges``h]jC)}(hjKh]hnum_mem_ranges}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjKubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjKubj)}(hhh]h)}(hnumber of mem_ranges in rangeh]hnumber of mem_ranges in range}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM hjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjKhM hjJubj)}(h-``start`` start of the virtual address range h](j)}(h ``start``h]jC)}(hj?Kh]hstart}(hjAKhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj=Kubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj9Kubj)}(hhh]h)}(h"start of the virtual address rangeh]h"start of the virtual address range}(hjXKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTKhM hjUKubah}(h]h ]h"]h$]h&]uh1jhj9Kubeh}(h]h ]h"]h$]h&]uh1jhjTKhM hjJubj)}(h,``range`` size of the virtual address range h](j)}(h ``range``h]jC)}(hjxKh]hrange}(hjzKhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvKubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjrKubj)}(hhh]h)}(h!size of the virtual address rangeh]h!size of the virtual address range}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM hjKubah}(h]h ]h"]h$]h&]uh1jhjrKubeh}(h]h ]h"]h$]h&]uh1jhjKhM hjJubj)}(h?``sizeof_mem_range_attr`` size of struct drm_xe_mem_range_attr h](j)}(h``sizeof_mem_range_attr``h]jC)}(hjKh]hsizeof_mem_range_attr}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjKubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjKubj)}(hhh]h)}(h$size of struct drm_xe_mem_range_attrh]h$size of struct drm_xe_mem_range_attr}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM hjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjKhM hjJubj)}(hH``vector_of_mem_attr`` userptr to array of struct drm_xe_mem_range_attr h](j)}(h``vector_of_mem_attr``h]jC)}(hjKh]hvector_of_mem_attr}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjKubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjKubj)}(hhh]h)}(h0userptr to array of struct drm_xe_mem_range_attrh]h0userptr to array of struct drm_xe_mem_range_attr}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM hjLubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjKhM hjJubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]jC)}(hj#Lh]hreserved}(hj%LhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj!Lubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjLubj)}(hhh]h)}(hReservedh]hReserved}(hjNh]h exec_queue_id}(hj@NhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjUse command GET_ERROR_COUNTERS to list errors of specific nodeh]h)}(hj;Ph]h>Use command GET_ERROR_COUNTERS to list errors of specific node}(hj=PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj9Pubah}(h]h ]h"]h$]h&]uh1hhjPubh)}(h@Query specific error values using either error-id or error-name h]h)}(h?Query specific error values using either error-id or error-nameh]h?Query specific error values using either error-id or error-name}(hjUPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjQPubah}(h]h ]h"]h$]h&]uh1hhjPubeh}(h]h ]h"]h$]h&]j5j5j5hj5j5uh1jI5hjOubj)}(h// Lookup tables for ID-to-name resolution static const char *nodes[] = DRM_XE_RAS_ERROR_SEVERITY_NAMES; static const char *errors[] = DRM_XE_RAS_ERROR_COMPONENT_NAMES;h]h// Lookup tables for ID-to-name resolution static const char *nodes[] = DRM_XE_RAS_ERROR_SEVERITY_NAMES; static const char *errors[] = DRM_XE_RAS_ERROR_COMPONENT_NAMES;}hjpPsbah}(h]h ]h"]h$]h&]jjjjjj}uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjOubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_xe_ras_error_severity (C enum)c.drm_xe_ras_error_severityhNtauh1jJhjOubj\)}(hhh](ja)}(hdrm_xe_ras_error_severityh]jg)}(henum drm_xe_ras_error_severityh](jm)}(hjh]henum}(hjPhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjPhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM ubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjPhhhjPhM ubj)}(hdrm_xe_ras_error_severityh]j)}(hjPh]hdrm_xe_ras_error_severity}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubah}(h]h ](jjeh"]h$]h&]jjuh1jhjPhhhjPhM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjPhhhjPhM ubah}(h]jPah ](jjeh"]h$]h&]jj)jhuh1j`hjPhM hjPhhubj)}(hhh]h)}(hDRM RAS error severity.h]hDRM RAS error severity.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjPhhubah}(h]h ]h"]h$]h&]uh1jhjPhhhjPhM ubeh}(h]h ](jenumeh"]h$]h&]jjjjPjjPjjjuh1j[hhhjOubj)}(h**Constants** ``DRM_XE_RAS_ERR_SEV_CORRECTABLE`` Correctable Error ``DRM_XE_RAS_ERR_SEV_UNCORRECTABLE`` Uncorrectable Error ``DRM_XE_RAS_ERR_SEV_MAX`` Max severityh](h)}(h **Constants**h]j)}(hjPh]h Constants}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjPubj)}(hhh](j)}(h5``DRM_XE_RAS_ERR_SEV_CORRECTABLE`` Correctable Error h](j)}(h"``DRM_XE_RAS_ERR_SEV_CORRECTABLE``h]jC)}(hjQh]hDRM_XE_RAS_ERR_SEV_CORRECTABLE}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjQubj)}(hhh]h)}(hCorrectable Errorh]hCorrectable Error}(hj5QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1QhM hj2Qubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhj1QhM hjQubj)}(h9``DRM_XE_RAS_ERR_SEV_UNCORRECTABLE`` Uncorrectable Error h](j)}(h$``DRM_XE_RAS_ERR_SEV_UNCORRECTABLE``h]jC)}(hjUQh]h DRM_XE_RAS_ERR_SEV_UNCORRECTABLE}(hjWQhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjSQubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjOQubj)}(hhh]h)}(hUncorrectable Errorh]hUncorrectable Error}(hjnQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjQhM hjkQubah}(h]h ]h"]h$]h&]uh1jhjOQubeh}(h]h ]h"]h$]h&]uh1jhjjQhM hjQubj)}(h'``DRM_XE_RAS_ERR_SEV_MAX`` Max severityh](j)}(h``DRM_XE_RAS_ERR_SEV_MAX``h]jC)}(hjQh]hDRM_XE_RAS_ERR_SEV_MAX}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjQubj)}(hhh]h)}(h Max severityh]h Max severity}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjQubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjQhM hjQubeh}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_xe_ras_error_component (C enum)c.drm_xe_ras_error_componenthNtauh1jJhjOubj\)}(hhh](ja)}(hdrm_xe_ras_error_componenth]jg)}(henum drm_xe_ras_error_componenth](jm)}(hjh]henum}(hjQhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjQhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM ubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjQhhhjQhM ubj)}(hdrm_xe_ras_error_componenth]j)}(hjQh]hdrm_xe_ras_error_component}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ](jjeh"]h$]h&]jjuh1jhjQhhhjQhM ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjQhhhjQhM ubah}(h]jQah ](jjeh"]h$]h&]jj)jhuh1j`hjQhM hjQhhubj)}(hhh]h)}(hDRM RAS error component.h]hDRM RAS error component.}(hj*RhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hj'Rhhubah}(h]h ]h"]h$]h&]uh1jhjQhhhjQhM ubeh}(h]h ](jenumeh"]h$]h&]jjjjBRjjBRjjjuh1j[hhhjOubj)}(hXW**Constants** ``DRM_XE_RAS_ERR_COMP_CORE_COMPUTE`` Core Compute Error ``DRM_XE_RAS_ERR_COMP_SOC_INTERNAL`` SoC Internal Error ``DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY`` Device Memory Error ``DRM_XE_RAS_ERR_COMP_PCIE`` PCIe Subsystem Error ``DRM_XE_RAS_ERR_COMP_FABRIC`` Fabric Subsystem Error ``DRM_XE_RAS_ERR_COMP_MAX`` Max Errorh](h)}(h **Constants**h]j)}(hjLRh]h Constants}(hjNRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJRubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjFRubj)}(hhh](j)}(h8``DRM_XE_RAS_ERR_COMP_CORE_COMPUTE`` Core Compute Error h](j)}(h$``DRM_XE_RAS_ERR_COMP_CORE_COMPUTE``h]jC)}(hjkRh]h DRM_XE_RAS_ERR_COMP_CORE_COMPUTE}(hjmRhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjiRubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM hjeRubj)}(hhh]h)}(hCore Compute Errorh]hCore Compute Error}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhM hjRubah}(h]h ]h"]h$]h&]uh1jhjeRubeh}(h]h ]h"]h$]h&]uh1jhjRhM hjbRubj)}(h8``DRM_XE_RAS_ERR_COMP_SOC_INTERNAL`` SoC Internal Error h](j)}(h$``DRM_XE_RAS_ERR_COMP_SOC_INTERNAL``h]jC)}(hjRh]h DRM_XE_RAS_ERR_COMP_SOC_INTERNAL}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjRubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM# hjRubj)}(hhh]h)}(hSoC Internal Errorh]hSoC Internal Error}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhM# hjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jhjRhM# hjbRubj)}(h:``DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY`` Device Memory Error h](j)}(h%``DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY``h]jC)}(hjRh]h!DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjRubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM& hjRubj)}(hhh]h)}(hDevice Memory Errorh]hDevice Memory Error}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhM& hjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jhjRhM& hjbRubj)}(h2``DRM_XE_RAS_ERR_COMP_PCIE`` PCIe Subsystem Error h](j)}(h``DRM_XE_RAS_ERR_COMP_PCIE``h]jC)}(hjSh]hDRM_XE_RAS_ERR_COMP_PCIE}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjSubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM) hjSubj)}(hhh]h)}(hPCIe Subsystem Errorh]hPCIe Subsystem Error}(hj/ShhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+ShM) hj,Subah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhj+ShM) hjbRubj)}(h6``DRM_XE_RAS_ERR_COMP_FABRIC`` Fabric Subsystem Error h](j)}(h``DRM_XE_RAS_ERR_COMP_FABRIC``h]jC)}(hjOSh]hDRM_XE_RAS_ERR_COMP_FABRIC}(hjQShhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjMSubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM, hjISubj)}(hhh]h)}(hFabric Subsystem Errorh]hFabric Subsystem Error}(hjhShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdShM, hjeSubah}(h]h ]h"]h$]h&]uh1jhjISubeh}(h]h ]h"]h$]h&]uh1jhjdShM, hjbRubj)}(h%``DRM_XE_RAS_ERR_COMP_MAX`` Max Errorh](j)}(h``DRM_XE_RAS_ERR_COMP_MAX``h]jC)}(hjSh]hDRM_XE_RAS_ERR_COMP_MAX}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjSubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM. hjSubj)}(hhh]h)}(h Max Errorh]h Max Error}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:31: ./include/uapi/drm/xe_drm.hhM/ hjSubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhjShM. hjbRubeh}(h]h ]h"]h$]h&]uh1jhjFRubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOubeh}(h]jah ]h"]user interfaceah$]h&]uh1hhj-hhhNhNubeh}(h]jah ]h"] drm/xe uapiah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hdrm/asahi uAPIh]hdrm/asahi uAPI}(hjShhhNhNubah}(h]h ]h"]h$]h&]hj;uh1hhjShhhhhK"ubj{)}(h#.. _Introduction to the Asahi UAPI:h]h}(h]h ]h"]h$]h&]hʌintroduction-to-the-asahi-uapiuh1jzhKhjShhhNubh)}(h"**Introduction to the Asahi UAPI**h]j)}(hjSh]hIntroduction to the Asahi UAPI}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]jSah ]h"]introduction to the asahi uapiah$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjShhj}jTjSsj}jSjSsubh)}(h.This documentation describes the Asahi IOCTLs.h]h.This documentation describes the Asahi IOCTLs.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjShhubh)}(hZJust a few generic rules about the data passed to the Asahi IOCTLs (cribbed from Panthor):h]hZJust a few generic rules about the data passed to the Asahi IOCTLs (cribbed from Panthor):}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjShhubh)}(hhh](h)}(hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.h]h)}(hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.h]hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.}(hj3ThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj/Tubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]h)}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.}(hjLThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjHTubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]h)}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]hNAll padding fields will be checked by the driver to make sure they are zeroed.}(hjeThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjaTubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(h-Flags can be added, but not removed/replaced.h]h)}(hj|Th]h-Flags can be added, but not removed/replaced.}(hj~ThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjzTubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]h)}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjTubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_asahi_cmd_header::size).h]h)}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_asahi_cmd_header::size).h]hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_asahi_cmd_header::size).}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK"hjTubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]h)}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK&hjTubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h)}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK(hjTubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to guess which flags are supported.h]h)}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to guess which flags are supported.h]hEach new flag/field addition must come with a driver version update so the userspace driver doesn’t have to guess which flags are supported.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK*hjTubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h)}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h`Structures should not contain unions, as this would defeat the extensibility of such structures.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK,hjUubah}(h]h ]h"]h$]h&]uh1hhj,Tubh)}(hrIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_asahi_ioctl_id enum. h]h)}(hnIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_asahi_ioctl_id enum.4h]hpIOCTLs can’t be removed or replaced. New IOCTL IDs should be placed at the end of the drm_asahi_ioctl_id enum.}(hj,UhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK.hj(Uubah}(h]h ]h"]h$]h&]uh1hhj,Tubeh}(h]h ]h"]h$]h&]j j uh1hhjAThKhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_ioctl_id (C enum)c.drm_asahi_ioctl_idhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_ioctl_idh]jg)}(henum drm_asahi_ioctl_idh](jm)}(hjh]henum}(hj`UhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj\Uhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK4ubj)}(h h]h }(hjnUhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj\UhhhjmUhK4ubj)}(hdrm_asahi_ioctl_idh]j)}(hjZUh]hdrm_asahi_ioctl_id}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|Uubah}(h]h ](jjeh"]h$]h&]jjuh1jhj\UhhhjmUhK4ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjXUhhhjmUhK4ubah}(h]jSUah ](jjeh"]h$]h&]jj)jhuh1j`hjmUhK4hjUUhhubj)}(hhh]h)}(h IOCTL IDsh]h IOCTL IDs}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK5hjUhhubah}(h]h ]h"]h$]h&]uh1jhjUUhhhjmUhK4ubeh}(h]h ](jenumeh"]h$]h&]jjjjUjjUjjjuh1j[hhhjShNhNubj)}(hX**Constants** ``DRM_ASAHI_GET_PARAMS`` Query device properties. ``DRM_ASAHI_GET_TIME`` Query device time. ``DRM_ASAHI_VM_CREATE`` Create a GPU VM address space. ``DRM_ASAHI_VM_DESTROY`` Destroy a VM. ``DRM_ASAHI_VM_BIND`` Bind/unbind memory to a VM. ``DRM_ASAHI_GEM_CREATE`` Create a buffer object. ``DRM_ASAHI_GEM_MMAP_OFFSET`` Get offset to pass to mmap() to map a given GEM handle. ``DRM_ASAHI_GEM_BIND_OBJECT`` Bind memory as a special object ``DRM_ASAHI_QUEUE_CREATE`` Create a scheduling queue. ``DRM_ASAHI_QUEUE_DESTROY`` Destroy a scheduling queue. ``DRM_ASAHI_SUBMIT`` Submit commands to a queue.h](h)}(h **Constants**h]j)}(hjUh]h Constants}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK9hjUubj)}(hhh](j)}(h2``DRM_ASAHI_GET_PARAMS`` Query device properties. h](j)}(h``DRM_ASAHI_GET_PARAMS``h]jC)}(hjUh]hDRM_ASAHI_GET_PARAMS}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjUubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK``DRM_ASAHI_GEM_BIND_OBJECT`` Bind memory as a special object h](j)}(h``DRM_ASAHI_GEM_BIND_OBJECT``h]jC)}(hjsWh]hDRM_ASAHI_GEM_BIND_OBJECT}(hjuWhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjqWubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKRhjmWubj)}(hhh]h)}(hBind memory as a special objecth]hBind memory as a special object}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhKRhjWubah}(h]h ]h"]h$]h&]uh1jhjmWubeh}(h]h ]h"]h$]h&]uh1jhjWhKRhjUubj)}(h6``DRM_ASAHI_QUEUE_CREATE`` Create a scheduling queue. h](j)}(h``DRM_ASAHI_QUEUE_CREATE``h]jC)}(hjWh]hDRM_ASAHI_QUEUE_CREATE}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjWubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKUhjWubj)}(hhh]h)}(hCreate a scheduling queue.h]hCreate a scheduling queue.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhKUhjWubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jhjWhKUhjUubj)}(h8``DRM_ASAHI_QUEUE_DESTROY`` Destroy a scheduling queue. h](j)}(h``DRM_ASAHI_QUEUE_DESTROY``h]jC)}(hjWh]hDRM_ASAHI_QUEUE_DESTROY}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjWubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKXhjWubj)}(hhh]h)}(hDestroy a scheduling queue.h]hDestroy a scheduling queue.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhKXhjWubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jhjWhKXhjUubj)}(h0``DRM_ASAHI_SUBMIT`` Submit commands to a queue.h](j)}(h``DRM_ASAHI_SUBMIT``h]jC)}(hjXh]hDRM_ASAHI_SUBMIT}(hj XhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjXubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKZhjXubj)}(hhh]h)}(hSubmit commands to a queue.h]hSubmit commands to a queue.}(hj7XhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK[hj4Xubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jhj3XhKZhjUubeh}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hjaXh]h Description}(hjcXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_Xubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK]hjShhubh)}(hMPlace new ioctls at the end, don't re-order, don't replace or remove entries.h]hQPlace new ioctls at the end, don’t re-order, don’t replace or remove entries.}(hjwXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK6hjShhubh)}(h]These IDs are not meant to be used directly. Use the DRM_IOCTL_ASAHI_xxx definitions instead.h]h]These IDs are not meant to be used directly. Use the DRM_IOCTL_ASAHI_xxx definitions instead.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK8hjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_asahi_params_global (C struct)c.drm_asahi_params_globalhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_params_globalh]jg)}(hstruct drm_asahi_params_globalh](jm)}(hjph]hstruct}(hjXhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjXhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhK>ubj)}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjXhhhjXhK>ubj)}(hdrm_asahi_params_globalh]j)}(hjXh]hdrm_asahi_params_global}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubah}(h]h ](jjeh"]h$]h&]jjuh1jhjXhhhjXhK>ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjXhhhjXhK>ubah}(h]jXah ](jjeh"]h$]h&]jj)jhuh1j`hjXhK>hjXhhubj)}(hhh]h)}(hGlobal parameters.h]hGlobal parameters.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKehjXhhubah}(h]h ]h"]h$]h&]uh1jhjXhhhjXhK>ubeh}(h]h ](jstructeh"]h$]h&]jjjjYjjYjjjuh1j[hhhjShNhNubj)}(hX **Definition**:: struct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; }; **Members** ``features`` Feature bits from drm_asahi_feature ``gpu_generation`` GPU generation, e.g. 13 for G13G ``gpu_variant`` GPU variant as a character, e.g. 'C' for G13C ``gpu_revision`` GPU revision in BCD, e.g. 0x00 for 'A0' or 0x21 for 'C1' ``chip_id`` Chip ID in BCD, e.g. 0x8103 for T8103 ``num_dies`` Number of dies in the SoC ``num_clusters_total`` Number of GPU clusters (across all dies) ``num_cores_per_cluster`` Number of logical cores per cluster (including inactive/nonexistent) ``max_frequency_khz`` Maximum GPU core clock frequency ``core_masks`` Bitmask of present/enabled cores per cluster ``vm_start`` VM range start VMA. Together with **vm_end**, this defines the window of valid GPU VAs. Userspace is expected to subdivide VAs out of this window. This window contains all virtual addresses that userspace needs to know about. There may be kernel-internal GPU VAs outside this range, but that detail is not relevant here. ``vm_end`` VM range end VMA ``vm_kernel_min_size`` Minimum kernel VMA window size. When creating a VM, userspace is required to carve out a section of virtual addresses (within the range given by **vm_start** and **vm_end**). The kernel will allocate various internal structures within the specified VA range. Allowing userspace to choose the VA range for the kernel, rather than the kernel reserving VAs and requiring userspace to cope, can assist in implementing SVM. ``max_commands_per_submission`` Maximum number of supported commands per submission. This mirrors firmware limits. Userspace must split up larger command buffers, which may require inserting additional synchronization. ``max_attachments`` Maximum number of drm_asahi_attachment's per command ``command_timestamp_frequency_hz`` Timebase frequency for timestamps written during command execution, specified via drm_asahi_timestamp structures. As this rate is controlled by the firmware, it is a queryable parameter. Userspace must divide by this frequency to convert timestamps to seconds, rather than hardcoding a particular firmware's rate.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubh:}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKihj Yubj)}(hXstruct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; };h]hXstruct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; };}hj-Ysbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKkhj Yubh)}(h **Members**h]j)}(hj>Yh]hMembers}(hj@YhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj``gpu_variant`` GPU variant as a character, e.g. 'C' for G13C h](j)}(h``gpu_variant``h]jC)}(hjYh]h gpu_variant}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjYubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKqhjYubj)}(hhh]h)}(h-GPU variant as a character, e.g. 'C' for G13Ch]h1GPU variant as a character, e.g. ‘C’ for G13C}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhKqhjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jhjYhKqhjTYubj)}(hJ``gpu_revision`` GPU revision in BCD, e.g. 0x00 for 'A0' or 0x21 for 'C1' h](j)}(h``gpu_revision``h]jC)}(hjZh]h gpu_revision}(hj ZhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjZubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKvhjZubj)}(hhh]h)}(h8GPU revision in BCD, e.g. 0x00 for 'A0' or 0x21 for 'C1'h]h@GPU revision in BCD, e.g. 0x00 for ‘A0’ or 0x21 for ‘C1’}(hj!ZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKuhjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjZhKvhjTYubj)}(h2``chip_id`` Chip ID in BCD, e.g. 0x8103 for T8103 h](j)}(h ``chip_id``h]jC)}(hjBZh]hchip_id}(hjDZhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj@Zubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKzhj_sbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj_ubh)}(h **Members**h]j)}(hjO_h]hMembers}(hjQ_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM_ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj_ubj)}(hhh](j)}(h/``param_group`` Parameter group to fetch (MBZ) h](j)}(h``param_group``h]jC)}(hjn_h]h param_group}(hjp_hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjl_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjh_ubj)}(hhh]h)}(hParameter group to fetch (MBZ)h]hParameter group to fetch (MBZ)}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj_ubah}(h]h ]h"]h$]h&]uh1jhjh_ubeh}(h]h ]h"]h$]h&]uh1jhj_hKhje_ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hj_h]hpad}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj_ubj)}(hhh]h)}(hMBZh]hMBZ}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hKhje_ubj)}(h3``pointer`` User pointer to write parameter struct h](j)}(h ``pointer``h]jC)}(hj_h]hpointer}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj_ubj)}(hhh]h)}(h&User pointer to write parameter structh]h&User pointer to write parameter struct}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hKhje_ubj)}(h``size`` Size of the user buffer. In case of older userspace, this may be less than sizeof(struct drm_asahi_params_global). The kernel will not write past the length specified here, allowing extensibility.h](j)}(h``size``h]jC)}(hj`h]hsize}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj`ubj)}(hhh]h)}(hSize of the user buffer. In case of older userspace, this may be less than sizeof(struct drm_asahi_params_global). The kernel will not write past the length specified here, allowing extensibility.h]hSize of the user buffer. In case of older userspace, this may be less than sizeof(struct drm_asahi_params_global). The kernel will not write past the length specified here, allowing extensibility.}(hj2`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj/`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhj.`hKhje_ubeh}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_vm_create (C struct)c.drm_asahi_vm_createhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_vm_createh]jg)}(hstruct drm_asahi_vm_createh](jm)}(hjph]hstruct}(hjs`hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjo`hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjo`hhhj`hKubj)}(hdrm_asahi_vm_createh]j)}(hjm`h]hdrm_asahi_vm_create}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjo`hhhj`hKubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjk`hhhj`hKubah}(h]jf`ah ](jjeh"]h$]h&]jj)jhuh1j`hj`hKhjh`hhubj)}(hhh]h)}(h-Arguments passed to DRM_IOCTL_ASAHI_VM_CREATEh]h-Arguments passed to DRM_IOCTL_ASAHI_VM_CREATE}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj`hhubah}(h]h ]h"]h$]h&]uh1jhjh`hhhj`hKubeh}(h]h ](jstructeh"]h$]h&]jjjj`jj`jjjuh1j[hhhjShNhNubj)}(hX**Definition**:: struct drm_asahi_vm_create { __u64 kernel_start; __u64 kernel_end; __u32 vm_id; __u32 pad; }; **Members** ``kernel_start`` Start of the kernel-reserved address range. See drm_asahi_params_global::vm_kernel_min_size. Both **kernel_start** and **kernel_end** must be within the range of valid VAs given by drm_asahi_params_global::vm_start and drm_asahi_params_global::vm_end. The size of the kernel range (**kernel_end** - **kernel_start**) must be at least drm_asahi_params_global::vm_kernel_min_size. Userspace must not bind any memory on this VM into this reserved range, it is for kernel use only. ``kernel_end`` End of the kernel-reserved address range. See **kernel_start**. ``vm_id`` Returned VM ID ``pad`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubh:}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj`ubj)}(hmstruct drm_asahi_vm_create { __u64 kernel_start; __u64 kernel_end; __u32 vm_id; __u32 pad; };h]hmstruct drm_asahi_vm_create { __u64 kernel_start; __u64 kernel_end; __u32 vm_id; __u32 pad; };}hj`sbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj`ubh)}(h **Members**h]j)}(hjah]hMembers}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj`ubj)}(hhh](j)}(hX``kernel_start`` Start of the kernel-reserved address range. See drm_asahi_params_global::vm_kernel_min_size. Both **kernel_start** and **kernel_end** must be within the range of valid VAs given by drm_asahi_params_global::vm_start and drm_asahi_params_global::vm_end. The size of the kernel range (**kernel_end** - **kernel_start**) must be at least drm_asahi_params_global::vm_kernel_min_size. Userspace must not bind any memory on this VM into this reserved range, it is for kernel use only. h](j)}(h``kernel_start``h]jC)}(hj"ah]h kernel_start}(hj$ahhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj aubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhjaubj)}(hhh](h)}(h\Start of the kernel-reserved address range. See drm_asahi_params_global::vm_kernel_min_size.h]h\Start of the kernel-reserved address range. See drm_asahi_params_global::vm_kernel_min_size.}(hj;ahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj8aubh)}(hXBoth **kernel_start** and **kernel_end** must be within the range of valid VAs given by drm_asahi_params_global::vm_start and drm_asahi_params_global::vm_end. The size of the kernel range (**kernel_end** - **kernel_start**) must be at least drm_asahi_params_global::vm_kernel_min_size.h](hBoth }(hjJahhhNhNubj)}(h**kernel_start**h]h kernel_start}(hjRahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJaubh and }(hjJahhhNhNubj)}(h**kernel_end**h]h kernel_end}(hjdahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJaubh must be within the range of valid VAs given by drm_asahi_params_global::vm_start and drm_asahi_params_global::vm_end. The size of the kernel range (}(hjJahhhNhNubj)}(h**kernel_end**h]h kernel_end}(hjvahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJaubh - }(hjJahhhNhNubj)}(h**kernel_start**h]h kernel_start}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJaubh?) must be at least drm_asahi_params_global::vm_kernel_min_size.}(hjJahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj8aubh)}(hbUserspace must not bind any memory on this VM into this reserved range, it is for kernel use only.h]hbUserspace must not bind any memory on this VM into this reserved range, it is for kernel use only.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhKhj8aubeh}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj7ahKhjaubj)}(hO``kernel_end`` End of the kernel-reserved address range. See **kernel_start**. h](j)}(h``kernel_end``h]jC)}(hjah]h kernel_end}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjaubj)}(hhh]h)}(h?End of the kernel-reserved address range. See **kernel_start**.h](h.End of the kernel-reserved address range. See }(hjahhhNhNubj)}(h**kernel_start**h]h kernel_start}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubh.}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjaubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhjahMhjaubj)}(h``vm_id`` Returned VM ID h](j)}(h ``vm_id``h]jC)}(hjbh]hvm_id}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj bubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM hjbubj)}(hhh]h)}(hReturned VM IDh]hReturned VM ID}(hj'bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#bhM hj$bubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jhj#bhM hjaubj)}(h ``pad`` MBZh](j)}(h``pad``h]jC)}(hjGbh]hpad}(hjIbhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjEbubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM hjAbubj)}(hhh]h)}(hMBZh]hMBZ}(hj`bhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM hj]bubah}(h]h ]h"]h$]h&]uh1jhjAbubeh}(h]h ]h"]h$]h&]uh1jhj\bhM hjaubeh}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_vm_destroy (C struct)c.drm_asahi_vm_destroyhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_vm_destroyh]jg)}(hstruct drm_asahi_vm_destroyh](jm)}(hjph]hstruct}(hjbhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjbhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjbhhhjbhMubj)}(hdrm_asahi_vm_destroyh]j)}(hjbh]hdrm_asahi_vm_destroy}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubah}(h]h ](jjeh"]h$]h&]jjuh1jhjbhhhjbhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjbhhhjbhMubah}(h]jbah ](jjeh"]h$]h&]jj)jhuh1j`hjbhMhjbhhubj)}(hhh]h)}(h.Arguments passed to DRM_IOCTL_ASAHI_VM_DESTROYh]h.Arguments passed to DRM_IOCTL_ASAHI_VM_DESTROY}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjbhhubah}(h]h ]h"]h$]h&]uh1jhjbhhhjbhMubeh}(h]h ](jstructeh"]h$]h&]jjjjbjjbjjjuh1j[hhhjShNhNubj)}(h**Definition**:: struct drm_asahi_vm_destroy { __u32 vm_id; __u32 pad; }; **Members** ``vm_id`` VM ID to be destroyed ``pad`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubh:}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjbubj)}(h@struct drm_asahi_vm_destroy { __u32 vm_id; __u32 pad; };h]h@struct drm_asahi_vm_destroy { __u32 vm_id; __u32 pad; };}hj csbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjbubh)}(h **Members**h]j)}(hj1ch]hMembers}(hj3chhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/cubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjbubj)}(hhh](j)}(h ``vm_id`` VM ID to be destroyed h](j)}(h ``vm_id``h]jC)}(hjPch]hvm_id}(hjRchhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjNcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjJcubj)}(hhh]h)}(hVM ID to be destroyedh]hVM ID to be destroyed}(hjichhhNhNubah}(h]h ]h"]h$]h&]uh1hhjechMhjfcubah}(h]h ]h"]h$]h&]uh1jhjJcubeh}(h]h ]h"]h$]h&]uh1jhjechMhjGcubj)}(h ``pad`` MBZh](j)}(h``pad``h]jC)}(hjch]hpad}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjcubj)}(hhh]h)}(hMBZh]hMBZ}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjcubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhjchMhjGcubeh}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_gem_flags (C enum)c.drm_asahi_gem_flagshNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_gem_flagsh]jg)}(henum drm_asahi_gem_flagsh](jm)}(hjh]henum}(hjchhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjchhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjchhhjchMubj)}(hdrm_asahi_gem_flagsh]j)}(hjch]hdrm_asahi_gem_flags}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubah}(h]h ](jjeh"]h$]h&]jjuh1jhjchhhjchMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjchhhjchMubah}(h]jcah ](jjeh"]h$]h&]jj)jhuh1j`hjchMhjchhubj)}(hhh]h)}(hFlags for GEM creationh]hFlags for GEM creation}(hj%dhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj"dhhubah}(h]h ]h"]h$]h&]uh1jhjchhhjchMubeh}(h]h ](jenumeh"]h$]h&]jjjj=djj=djjjuh1j[hhhjShNhNubj)}(h**Constants** ``DRM_ASAHI_GEM_WRITEBACK`` BO should be CPU-mapped as writeback. Map as writeback instead of write-combine. This optimizes for CPU reads. ``DRM_ASAHI_GEM_VM_PRIVATE`` BO is private to this GPU VM (no exports).h](h)}(h **Constants**h]j)}(hjGdh]h Constants}(hjIdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEdubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjAdubj)}(hhh](j)}(h``DRM_ASAHI_GEM_WRITEBACK`` BO should be CPU-mapped as writeback. Map as writeback instead of write-combine. This optimizes for CPU reads. h](j)}(h``DRM_ASAHI_GEM_WRITEBACK``h]jC)}(hjfdh]hDRM_ASAHI_GEM_WRITEBACK}(hjhdhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjddubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM%hj`dubj)}(hhh](h)}(h%BO should be CPU-mapped as writeback.h]h%BO should be CPU-mapped as writeback.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM"hj|dubh)}(hHMap as writeback instead of write-combine. This optimizes for CPU reads.h]hHMap as writeback instead of write-combine. This optimizes for CPU reads.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM$hj|dubeh}(h]h ]h"]h$]h&]uh1jhj`dubeh}(h]h ]h"]h$]h&]uh1jhj{dhM%hj]dubj)}(hG``DRM_ASAHI_GEM_VM_PRIVATE`` BO is private to this GPU VM (no exports).h](j)}(h``DRM_ASAHI_GEM_VM_PRIVATE``h]jC)}(hjdh]hDRM_ASAHI_GEM_VM_PRIVATE}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjdubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM'hjdubj)}(hhh]h)}(h*BO is private to this GPU VM (no exports).h]h*BO is private to this GPU VM (no exports).}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM(hjdubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjdhM'hj]dubeh}(h]h ]h"]h$]h&]uh1jhjAdubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_gem_create (C struct)c.drm_asahi_gem_createhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_gem_createh]jg)}(hstruct drm_asahi_gem_createh](jm)}(hjph]hstruct}(hj ehhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjehhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM-ubj)}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjehhhjehM-ubj)}(hdrm_asahi_gem_createh]j)}(hjeh]hdrm_asahi_gem_create}(hj)ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%eubah}(h]h ](jjeh"]h$]h&]jjuh1jhjehhhjehM-ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjehhhjehM-ubah}(h]jdah ](jjeh"]h$]h&]jj)jhuh1j`hjehM-hjdhhubj)}(hhh]h)}(h.Arguments passed to DRM_IOCTL_ASAHI_GEM_CREATEh]h.Arguments passed to DRM_IOCTL_ASAHI_GEM_CREATE}(hjKehhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM-hjHehhubah}(h]h ]h"]h$]h&]uh1jhjdhhhjehM-ubeh}(h]h ](jstructeh"]h$]h&]jjjjcejjcejjjuh1j[hhhjShNhNubj)}(hXy**Definition**:: struct drm_asahi_gem_create { __u64 size; __u32 flags; __u32 vm_id; __u32 handle; __u32 pad; }; **Members** ``size`` Size of the BO ``flags`` Combination of drm_asahi_gem_flags flags. ``vm_id`` VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is set ``handle`` Returned GEM handle for the BO ``pad`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjoehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkeubh:}(hjkehhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM1hjgeubj)}(hsstruct drm_asahi_gem_create { __u64 size; __u32 flags; __u32 vm_id; __u32 handle; __u32 pad; };h]hsstruct drm_asahi_gem_create { __u64 size; __u32 flags; __u32 vm_id; __u32 handle; __u32 pad; };}hjesbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM3hjgeubh)}(h **Members**h]j)}(hjeh]hMembers}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM;hjgeubj)}(hhh](j)}(h``size`` Size of the BO h](j)}(h``size``h]jC)}(hjeh]hsize}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjeubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM1hjeubj)}(hhh]h)}(hSize of the BOh]hSize of the BO}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehM1hjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjehM1hjeubj)}(h4``flags`` Combination of drm_asahi_gem_flags flags. h](j)}(h ``flags``h]jC)}(hjeh]hflags}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjeubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.h8hM4hjeubj)}(hhh]h)}(h)Combination of drm_asahi_gem_flags flags.h]h)Combination of drm_asahi_gem_flags flags.}(hj fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhM4hjfubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjfhM4hjeubj)}(hH``vm_id`` VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is set h](j)}(h ``vm_id``h]jC)}(hj*fh]hvm_id}(hj,fhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj(fubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM8hj$fubj)}(hhh]h)}(h=VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is seth]h=VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is set}(hjCfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?fhM8hj@fubah}(h]h ]h"]h$]h&]uh1jhj$fubeh}(h]h ]h"]h$]h&]uh1jhj?fhM8hjeubj)}(h*``handle`` Returned GEM handle for the BO h](j)}(h ``handle``h]jC)}(hjcfh]hhandle}(hjefhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjafubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM<hj]fubj)}(hhh]h)}(hReturned GEM handle for the BOh]hReturned GEM handle for the BO}(hj|fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxfhM<hjyfubah}(h]h ]h"]h$]h&]uh1jhj]fubeh}(h]h ]h"]h$]h&]uh1jhjxfhM<hjeubj)}(h ``pad`` MBZh](j)}(h``pad``h]jC)}(hjfh]hpad}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM>hjfubj)}(hhh]h)}(hMBZh]hMBZ}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM?hjfubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjfhM>hjeubeh}(h]h ]h"]h$]h&]uh1jhjgeubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW$drm_asahi_gem_mmap_offset (C struct)c.drm_asahi_gem_mmap_offsethNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_gem_mmap_offseth]jg)}(h struct drm_asahi_gem_mmap_offseth](jm)}(hjph]hstruct}(hjfhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjfhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMEubj)}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjfhhhjghMEubj)}(hdrm_asahi_gem_mmap_offseth]j)}(hjfh]hdrm_asahi_gem_mmap_offset}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubah}(h]h ](jjeh"]h$]h&]jjuh1jhjfhhhjghMEubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjfhhhjghMEubah}(h]jfah ](jjeh"]h$]h&]jj)jhuh1j`hjghMEhjfhhubj)}(hhh]h)}(h3Arguments passed to DRM_IOCTL_ASAHI_GEM_MMAP_OFFSETh]h3Arguments passed to DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET}(hj8ghhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMChj5ghhubah}(h]h ]h"]h$]h&]uh1jhjfhhhjghMEubeh}(h]h ](jstructeh"]h$]h&]jjjjPgjjPgjjjuh1j[hhhjShNhNubj)}(hX **Definition**:: struct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; }; **Members** ``handle`` Handle for the object being mapped. ``flags`` Must be zero ``offset`` The fake offset to use for subsequent mmap callh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj\ghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXgubh:}(hjXghhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMGhjTgubj)}(hZstruct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; };h]hZstruct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; };}hjugsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMIhjTgubh)}(h **Members**h]j)}(hjgh]hMembers}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMOhjTgubj)}(hhh](j)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]jC)}(hjgh]hhandle}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMHhjgubj)}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMHhjgubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jhjghMHhjgubj)}(h``flags`` Must be zero h](j)}(h ``flags``h]jC)}(hjgh]hflags}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMKhjgubj)}(hhh]h)}(h Must be zeroh]h Must be zero}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMKhjgubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jhjghMKhjgubj)}(h:``offset`` The fake offset to use for subsequent mmap callh](j)}(h ``offset``h]jC)}(hjhh]hoffset}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMMhjhubj)}(hhh]h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hj0hhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMNhj-hubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhj,hhMMhjgubeh}(h]h ]h"]h$]h&]uh1jhjTgubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_bind_flags (C enum)c.drm_asahi_bind_flagshNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_bind_flagsh]jg)}(henum drm_asahi_bind_flagsh](jm)}(hjh]henum}(hjqhhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjmhhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMTubj)}(h h]h }(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjmhhhhj~hhMTubj)}(hdrm_asahi_bind_flagsh]j)}(hjkhh]hdrm_asahi_bind_flags}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubah}(h]h ](jjeh"]h$]h&]jjuh1jhjmhhhhj~hhMTubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjihhhhj~hhMTubah}(h]jdhah ](jjeh"]h$]h&]jj)jhuh1j`hj~hhMThjfhhhubj)}(hhh]h)}(hFlags for GEM bindingh]hFlags for GEM binding}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMRhjhhhubah}(h]h ]h"]h$]h&]uh1jhjfhhhhj~hhMTubeh}(h]h ](jenumeh"]h$]h&]jjjjhjjhjjjuh1j[hhhjShNhNubj)}(hX**Constants** ``DRM_ASAHI_BIND_UNBIND`` Instead of binding a GEM object to the range, simply unbind the GPU VMA range. ``DRM_ASAHI_BIND_READ`` Map BO with GPU read permission ``DRM_ASAHI_BIND_WRITE`` Map BO with GPU write permission ``DRM_ASAHI_BIND_SINGLE_PAGE`` Map a single page of the BO repeatedly across the VA range. This is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h](h)}(h **Constants**h]j)}(hjhh]h Constants}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMVhjhubj)}(hhh](j)}(hi``DRM_ASAHI_BIND_UNBIND`` Instead of binding a GEM object to the range, simply unbind the GPU VMA range. h](j)}(h``DRM_ASAHI_BIND_UNBIND``h]jC)}(hjhh]hDRM_ASAHI_BIND_UNBIND}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMZhjhubj)}(hhh]h)}(hNInstead of binding a GEM object to the range, simply unbind the GPU VMA range.h]hNInstead of binding a GEM object to the range, simply unbind the GPU VMA range.}(hj ihhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMYhj iubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhj ihMZhjhubj)}(h8``DRM_ASAHI_BIND_READ`` Map BO with GPU read permission h](j)}(h``DRM_ASAHI_BIND_READ``h]jC)}(hj.ih]hDRM_ASAHI_BIND_READ}(hj0ihhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj,iubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM]hj(iubj)}(hhh]h)}(hMap BO with GPU read permissionh]hMap BO with GPU read permission}(hjGihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCihM]hjDiubah}(h]h ]h"]h$]h&]uh1jhj(iubeh}(h]h ]h"]h$]h&]uh1jhjCihM]hjhubj)}(h:``DRM_ASAHI_BIND_WRITE`` Map BO with GPU write permission h](j)}(h``DRM_ASAHI_BIND_WRITE``h]jC)}(hjgih]hDRM_ASAHI_BIND_WRITE}(hjiihhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjeiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM`hjaiubj)}(hhh]h)}(h Map BO with GPU write permissionh]h Map BO with GPU write permission}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|ihM`hj}iubah}(h]h ]h"]h$]h&]uh1jhjaiubeh}(h]h ]h"]h$]h&]uh1jhj|ihM`hjhubj)}(h``DRM_ASAHI_BIND_SINGLE_PAGE`` Map a single page of the BO repeatedly across the VA range. This is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h](j)}(h``DRM_ASAHI_BIND_SINGLE_PAGE``h]jC)}(hjih]hDRM_ASAHI_BIND_SINGLE_PAGE}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMfhjiubj)}(hhh](h)}(h;Map a single page of the BO repeatedly across the VA range.h]h;Map a single page of the BO repeatedly across the VA range.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMchjiubh)}(hwThis is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h]hwThis is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMfhjiubeh}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jhjihMfhjhubeh}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_asahi_gem_bind_op (C struct)c.drm_asahi_gem_bind_ophNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_gem_bind_oph]jg)}(hstruct drm_asahi_gem_bind_oph](jm)}(hjph]hstruct}(hjjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMlubj)}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjjhhhjjhMlubj)}(hdrm_asahi_gem_bind_oph]j)}(hjjh]hdrm_asahi_gem_bind_op}(hj(jhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$jubah}(h]h ](jjeh"]h$]h&]jjuh1jhjjhhhjjhMlubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjjhhhjjhMlubah}(h]jiah ](jjeh"]h$]h&]jj)jhuh1j`hjjhMlhjihhubj)}(hhh]h)}(h+Description of a single GEM bind operation.h]h+Description of a single GEM bind operation.}(hjJjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMlhjGjhhubah}(h]h ]h"]h$]h&]uh1jhjihhhjjhMlubeh}(h]h ](jstructeh"]h$]h&]jjjjbjjjbjjjjuh1j[hhhjShNhNubj)}(hX**Definition**:: struct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; }; **Members** ``flags`` Combination of drm_asahi_bind_flags flags. ``handle`` GEM object to bind (except for UNBIND) ``offset`` Offset into the object (except for UNBIND). For a regular bind, this is the beginning of the region of the GEM object to bind. For a single-page bind, this is the offset to the single page that will be repeatedly bound. Must be page-size aligned. ``range`` Number of bytes to bind/unbind to **addr**. Must be page-size aligned. ``addr`` Address to bind to. Must be page-size aligned.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjnjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjjubh:}(hjjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMphjfjubj)}(hwstruct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; };h]hwstruct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; };}hjjsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMrhjfjubh)}(h **Members**h]j)}(hjjh]hMembers}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMzhjfjubj)}(hhh](j)}(h5``flags`` Combination of drm_asahi_bind_flags flags. h](j)}(h ``flags``h]jC)}(hjjh]hflags}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMphjjubj)}(hhh]h)}(h*Combination of drm_asahi_bind_flags flags.h]h*Combination of drm_asahi_bind_flags flags.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMphjjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjjhMphjjubj)}(h2``handle`` GEM object to bind (except for UNBIND) h](j)}(h ``handle``h]jC)}(hjjh]hhandle}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMshjjubj)}(hhh]h)}(h&GEM object to bind (except for UNBIND)h]h&GEM object to bind (except for UNBIND)}(hj khhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhMshjkubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjkhMshjjubj)}(hX``offset`` Offset into the object (except for UNBIND). For a regular bind, this is the beginning of the region of the GEM object to bind. For a single-page bind, this is the offset to the single page that will be repeatedly bound. Must be page-size aligned. h](j)}(h ``offset``h]jC)}(hj)kh]hoffset}(hj+khhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj'kubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj#kubj)}(hhh](h)}(h+Offset into the object (except for UNBIND).h]h+Offset into the object (except for UNBIND).}(hjBkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMwhj?kubh)}(hRFor a regular bind, this is the beginning of the region of the GEM object to bind.h]hRFor a regular bind, this is the beginning of the region of the GEM object to bind.}(hjQkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMyhj?kubh)}(h\For a single-page bind, this is the offset to the single page that will be repeatedly bound.h]h\For a single-page bind, this is the offset to the single page that will be repeatedly bound.}(hj`khhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM|hj?kubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hjokhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>khMhj?kubeh}(h]h ]h"]h$]h&]uh1jhj#kubeh}(h]h ]h"]h$]h&]uh1jhj>khMhjjubj)}(hR``range`` Number of bytes to bind/unbind to **addr**. Must be page-size aligned. h](j)}(h ``range``h]jC)}(hjkh]hrange}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjkubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjkubj)}(hhh](h)}(h+Number of bytes to bind/unbind to **addr**.h](h"Number of bytes to bind/unbind to }(hjkhhhNhNubj)}(h**addr**h]haddr}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubh.}(hjkhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjkubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhMhjkubeh}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jhjkhMhjjubj)}(h8``addr`` Address to bind to. Must be page-size aligned.h](j)}(h``addr``h]jC)}(hjkh]haddr}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjkubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjkubj)}(hhh](h)}(hAddress to bind to.h]hAddress to bind to.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjkubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjkubeh}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jhjkhMhjjubeh}(h]h ]h"]h$]h&]uh1jhjfjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_vm_bind (C struct)c.drm_asahi_vm_bindhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_vm_bindh]jg)}(hstruct drm_asahi_vm_bindh](jm)}(hjph]hstruct}(hjRlhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjNlhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj`lhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjNlhhhj_lhMubj)}(hdrm_asahi_vm_bindh]j)}(hjLlh]hdrm_asahi_vm_bind}(hjrlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnlubah}(h]h ](jjeh"]h$]h&]jjuh1jhjNlhhhj_lhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjJlhhhj_lhMubah}(h]jElah ](jjeh"]h$]h&]jj)jhuh1j`hj_lhMhjGlhhubj)}(hhh]h)}(h+Arguments passed to DRM_IOCTL_ASAHI_VM_BINDh]h+Arguments passed to DRM_IOCTL_ASAHI_VM_BIND}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjlhhubah}(h]h ]h"]h$]h&]uh1jhjGlhhhj_lhMubeh}(h]h ](jstructeh"]h$]h&]jjjjljjljjjuh1j[hhhjShNhNubj)}(hX**Definition**:: struct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; }; **Members** ``vm_id`` The ID of the VM to bind to ``num_binds`` number of binds in this IOCTL. ``stride`` Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op. ``pad`` MBZ ``userptr`` User pointer to an array of **num_binds** structures of type **drm_asahi_gem_bind_op** and size **stride** bytes.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubh:}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjlubj)}(hwstruct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; };h]hwstruct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; };}hjlsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjlubh)}(h **Members**h]j)}(hjlh]hMembers}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjlubj)}(hhh](j)}(h&``vm_id`` The ID of the VM to bind to h](j)}(h ``vm_id``h]jC)}(hjmh]hvm_id}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjlubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjlubj)}(hhh]h)}(hThe ID of the VM to bind toh]hThe ID of the VM to bind to}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhMhjmubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jhjmhMhjlubj)}(h-``num_binds`` number of binds in this IOCTL. h](j)}(h ``num_binds``h]jC)}(hj:mh]h num_binds}(hj``object_handle`` Object handle (out for BIND, in for UNBIND) h](j)}(h``object_handle``h]jC)}(hjlrh]h object_handle}(hjnrhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjjrubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjfrubj)}(hhh]h)}(h+Object handle (out for BIND, in for UNBIND)h]h+Object handle (out for BIND, in for UNBIND)}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1jhjfrubeh}(h]h ]h"]h$]h&]uh1jhjrhMhj qubj)}(h ``pad`` MBZh](j)}(h``pad``h]jC)}(hjrh]hpad}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjrubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjrubj)}(hhh]h)}(hMBZh]hMBZ}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjrubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jhjrhMhj qubeh}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_cmd_type (C enum)c.drm_asahi_cmd_typehNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_cmd_typeh]jg)}(henum drm_asahi_cmd_typeh](jm)}(hjh]henum}(hjrhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjrhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj shhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjrhhhj shMubj)}(hdrm_asahi_cmd_typeh]j)}(hjrh]hdrm_asahi_cmd_type}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ](jjeh"]h$]h&]jjuh1jhjrhhhj shMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjrhhhj shMubah}(h]jrah ](jjeh"]h$]h&]jj)jhuh1j`hj shMhjrhhubj)}(hhh]h)}(h Command typeh]h Command type}(hjAshhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj>shhubah}(h]h ]h"]h$]h&]uh1jhjrhhhj shMubeh}(h]h ](jenumeh"]h$]h&]jjjjYsjjYsjjjuh1j[hhhjShNhNubj)}(hX**Constants** ``DRM_ASAHI_CMD_RENDER`` Render command, executing on the render subqueue. Combined vertex and fragment operation. Followed by a **drm_asahi_cmd_render** payload. ``DRM_ASAHI_CMD_COMPUTE`` Compute command on the compute subqueue. Followed by a **drm_asahi_cmd_compute** payload. ``DRM_ASAHI_SET_VERTEX_ATTACHMENTS`` Software command to set attachments for subsequent vertex shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. ``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS`` Software command to set attachments for subsequent fragment shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. ``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS`` Software command to set attachments for subsequent compute shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads.h](h)}(h **Constants**h]j)}(hjcsh]h Constants}(hjeshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjasubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj]subj)}(hhh](j)}(h``DRM_ASAHI_CMD_RENDER`` Render command, executing on the render subqueue. Combined vertex and fragment operation. Followed by a **drm_asahi_cmd_render** payload. h](j)}(h``DRM_ASAHI_CMD_RENDER``h]jC)}(hjsh]hDRM_ASAHI_CMD_RENDER}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjsubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj|subj)}(hhh](h)}(hYRender command, executing on the render subqueue. Combined vertex and fragment operation.h]hYRender command, executing on the render subqueue. Combined vertex and fragment operation.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjsubh)}(h/Followed by a **drm_asahi_cmd_render** payload.h](hFollowed by a }(hjshhhNhNubj)}(h**drm_asahi_cmd_render**h]hdrm_asahi_cmd_render}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubh payload.}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjshMhjsubeh}(h]h ]h"]h$]h&]uh1jhj|subeh}(h]h ]h"]h$]h&]uh1jhjshMhjysubj)}(hu``DRM_ASAHI_CMD_COMPUTE`` Compute command on the compute subqueue. Followed by a **drm_asahi_cmd_compute** payload. h](j)}(h``DRM_ASAHI_CMD_COMPUTE``h]jC)}(hjsh]hDRM_ASAHI_CMD_COMPUTE}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjsubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjsubj)}(hhh](h)}(h(Compute command on the compute subqueue.h]h(Compute command on the compute subqueue.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjsubh)}(h0Followed by a **drm_asahi_cmd_compute** payload.h](hFollowed by a }(hjthhhNhNubj)}(h**drm_asahi_cmd_compute**h]hdrm_asahi_cmd_compute}(hj thhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubh payload.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjshMhjsubeh}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhjshMhjysubj)}(h``DRM_ASAHI_SET_VERTEX_ATTACHMENTS`` Software command to set attachments for subsequent vertex shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. h](j)}(h$``DRM_ASAHI_SET_VERTEX_ATTACHMENTS``h]jC)}(hj6th]h DRM_ASAHI_SET_VERTEX_ATTACHMENTS}(hj8thhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj4tubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj0tubj)}(hhh](h)}(hUSoftware command to set attachments for subsequent vertex shaders in the same submit.h]hUSoftware command to set attachments for subsequent vertex shaders in the same submit.}(hjOthhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjLtubh)}(hBFollowed by (possibly multiple) **drm_asahi_attachment** payloads.h](h Followed by (possibly multiple) }(hj^thhhNhNubj)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hjfthhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^tubh payloads.}(hj^thhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjKthMhjLtubeh}(h]h ]h"]h$]h&]uh1jhj0tubeh}(h]h ]h"]h$]h&]uh1jhjKthMhjysubj)}(h``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS`` Software command to set attachments for subsequent fragment shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. h](j)}(h&``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS``h]jC)}(hjth]h"DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjtubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjtubj)}(hhh](h)}(hWSoftware command to set attachments for subsequent fragment shaders in the same submit.h]hWSoftware command to set attachments for subsequent fragment shaders in the same submit.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjtubh)}(hBFollowed by (possibly multiple) **drm_asahi_attachment** payloads.h](h Followed by (possibly multiple) }(hjthhhNhNubj)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubh payloads.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjthMhjtubeh}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjthMhjysubj)}(h``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS`` Software command to set attachments for subsequent compute shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads.h](j)}(h%``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS``h]jC)}(hjth]h!DRM_ASAHI_SET_COMPUTE_ATTACHMENTS}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjtubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjtubj)}(hhh](h)}(hVSoftware command to set attachments for subsequent compute shaders in the same submit.h]hVSoftware command to set attachments for subsequent compute shaders in the same submit.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjuubh)}(hBFollowed by (possibly multiple) **drm_asahi_attachment** payloads.h](h Followed by (possibly multiple) }(hjuhhhNhNubj)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubh payloads.}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjuubeh}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjthMhjysubeh}(h]h ]h"]h$]h&]uh1jhj]subeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_priority (C enum)c.drm_asahi_priorityhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_priorityh]jg)}(henum drm_asahi_priorityh](jm)}(hjh]henum}(hjeuhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjauhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjsuhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjauhhhjruhMubj)}(hdrm_asahi_priorityh]j)}(hj_uh]hdrm_asahi_priority}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubah}(h]h ](jjeh"]h$]h&]jjuh1jhjauhhhjruhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj]uhhhjruhMubah}(h]jXuah ](jjeh"]h$]h&]jj)jhuh1j`hjruhMhjZuhhubj)}(hhh]h)}(hScheduling queue priority.h]hScheduling queue priority.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM hjuhhubah}(h]h ]h"]h$]h&]uh1jhjZuhhhjruhMubeh}(h]h ](jenumeh"]h$]h&]jjjjujjujjjuh1j[hhhjShNhNubj)}(hX,**Constants** ``DRM_ASAHI_PRIORITY_LOW`` Low priority queue. ``DRM_ASAHI_PRIORITY_MEDIUM`` Medium priority queue. ``DRM_ASAHI_PRIORITY_HIGH`` High priority queue. Reserved for future extension. ``DRM_ASAHI_PRIORITY_REALTIME`` Real-time priority queue. Reserved for future extension.h](h)}(h **Constants**h]j)}(hjuh]h Constants}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjuubj)}(hhh](j)}(h/``DRM_ASAHI_PRIORITY_LOW`` Low priority queue. h](j)}(h``DRM_ASAHI_PRIORITY_LOW``h]jC)}(hjuh]hDRM_ASAHI_PRIORITY_LOW}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjuubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjuubj)}(hhh]h)}(hLow priority queue.h]hLow priority queue.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjuhMhjuubj)}(h5``DRM_ASAHI_PRIORITY_MEDIUM`` Medium priority queue. h](j)}(h``DRM_ASAHI_PRIORITY_MEDIUM``h]jC)}(hj!vh]hDRM_ASAHI_PRIORITY_MEDIUM}(hj#vhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjvubj)}(hhh]h)}(hMedium priority queue.h]hMedium priority queue.}(hj:vhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6vhMhj7vubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhj6vhMhjuubj)}(hQ``DRM_ASAHI_PRIORITY_HIGH`` High priority queue. Reserved for future extension. h](j)}(h``DRM_ASAHI_PRIORITY_HIGH``h]jC)}(hjZvh]hDRM_ASAHI_PRIORITY_HIGH}(hj\vhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjXvubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjTvubj)}(hhh](h)}(hHigh priority queue.h]hHigh priority queue.}(hjsvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjpvubh)}(hReserved for future extension.h]hReserved for future extension.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjovhMhjpvubeh}(h]h ]h"]h$]h&]uh1jhjTvubeh}(h]h ]h"]h$]h&]uh1jhjovhMhjuubj)}(hY``DRM_ASAHI_PRIORITY_REALTIME`` Real-time priority queue. Reserved for future extension.h](j)}(h``DRM_ASAHI_PRIORITY_REALTIME``h]jC)}(hjvh]hDRM_ASAHI_PRIORITY_REALTIME}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM hjvubj)}(hhh](h)}(hReal-time priority queue.h]hReal-time priority queue.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjvubh)}(hReserved for future extension.h]hReserved for future extension.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM!hjvubeh}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhjvhM hjuubeh}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hjvh]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM#hjShhubh)}(hThese priorities are forwarded to the firmware to influence firmware scheduling. The exact policy is ultimately decided by firmware, but these enums allow userspace to communicate the intentions.h]hThese priorities are forwarded to the firmware to influence firmware scheduling. The exact policy is ultimately decided by firmware, but these enums allow userspace to communicate the intentions.}(hj whhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW!drm_asahi_queue_create (C struct)c.drm_asahi_queue_createhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_queue_createh]jg)}(hstruct drm_asahi_queue_createh](jm)}(hjph]hstruct}(hj2whhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj.whhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj@whhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj.whhhj?whMubj)}(hdrm_asahi_queue_createh]j)}(hj,wh]hdrm_asahi_queue_create}(hjRwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNwubah}(h]h ](jjeh"]h$]h&]jjuh1jhj.whhhj?whMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj*whhhj?whMubah}(h]j%wah ](jjeh"]h$]h&]jj)jhuh1j`hj?whMhj'whhubj)}(hhh]h)}(h0Arguments passed to DRM_IOCTL_ASAHI_QUEUE_CREATEh]h0Arguments passed to DRM_IOCTL_ASAHI_QUEUE_CREATE}(hjtwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM*hjqwhhubah}(h]h ]h"]h$]h&]uh1jhj'whhhj?whMubeh}(h]h ](jstructeh"]h$]h&]jjjjwjjwjjjuh1j[hhhjShNhNubj)}(hXR**Definition**:: struct drm_asahi_queue_create { __u32 flags; __u32 vm_id; __u32 priority; __u32 queue_id; __u64 usc_exec_base; }; **Members** ``flags`` MBZ ``vm_id`` The ID of the VM this queue is bound to ``priority`` One of drm_asahi_priority ``queue_id`` The returned queue ID ``usc_exec_base`` GPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base. This sets the following registers on all queue commands: USC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) While the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubh:}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM.hjwubj)}(hstruct drm_asahi_queue_create { __u32 flags; __u32 vm_id; __u32 priority; __u32 queue_id; __u64 usc_exec_base; };h]hstruct drm_asahi_queue_create { __u32 flags; __u32 vm_id; __u32 priority; __u32 queue_id; __u64 usc_exec_base; };}hjwsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM0hjwubh)}(h **Members**h]j)}(hjwh]hMembers}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM8hjwubj)}(hhh](j)}(h``flags`` MBZ h](j)}(h ``flags``h]jC)}(hjwh]hflags}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjwubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM/hjwubj)}(hhh]h)}(hMBZh]hMBZ}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhM/hjwubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjwhM/hjwubj)}(h2``vm_id`` The ID of the VM this queue is bound to h](j)}(h ``vm_id``h]jC)}(hjxh]hvm_id}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjxubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM2hjxubj)}(hhh]h)}(h'The ID of the VM this queue is bound toh]h'The ID of the VM this queue is bound to}(hj3xhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/xhM2hj0xubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhj/xhM2hjwubj)}(h'``priority`` One of drm_asahi_priority h](j)}(h ``priority``h]jC)}(hjSxh]hpriority}(hjUxhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjQxubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM5hjMxubj)}(hhh]h)}(hOne of drm_asahi_priorityh]hOne of drm_asahi_priority}(hjlxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhxhM5hjixubah}(h]h ]h"]h$]h&]uh1jhjMxubeh}(h]h ]h"]h$]h&]uh1jhjhxhM5hjwubj)}(h#``queue_id`` The returned queue ID h](j)}(h ``queue_id``h]jC)}(hjxh]hqueue_id}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjxubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM8hjxubj)}(hhh]h)}(hThe returned queue IDh]hThe returned queue ID}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhM8hjxubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjxhM8hjwubj)}(hX``usc_exec_base`` GPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base. This sets the following registers on all queue commands: USC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) While the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h](j)}(h``usc_exec_base``h]jC)}(hjxh]h usc_exec_base}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjxubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMFhjxubj)}(hhh](h)}(huGPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base.h]huGPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM<hjxubh)}(h8This sets the following registers on all queue commands:h]h8This sets the following registers on all queue commands:}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM?hjxubjK)}(hTUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) h]h)}(hSUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute)h]hSUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute)}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMAhjxubah}(h]h ]h"]h$]h&]uh1jJhjyhMAhjxubh)}(hWhile the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h]hWhile the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMEhjxubeh}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjxhMFhjwubeh}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW"drm_asahi_queue_destroy (C struct)c.drm_asahi_queue_destroyhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_queue_destroyh]jg)}(hstruct drm_asahi_queue_destroyh](jm)}(hjph]hstruct}(hjVyhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjRyhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMMubj)}(h h]h }(hjdyhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjRyhhhjcyhMMubj)}(hdrm_asahi_queue_destroyh]j)}(hjPyh]hdrm_asahi_queue_destroy}(hjvyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjryubah}(h]h ](jjeh"]h$]h&]jjuh1jhjRyhhhjcyhMMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjNyhhhjcyhMMubah}(h]jIyah ](jjeh"]h$]h&]jj)jhuh1j`hjcyhMMhjKyhhubj)}(hhh]h)}(h1Arguments passed to DRM_IOCTL_ASAHI_QUEUE_DESTROYh]h1Arguments passed to DRM_IOCTL_ASAHI_QUEUE_DESTROY}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMLhjyhhubah}(h]h ]h"]h$]h&]uh1jhjKyhhhjcyhMMubeh}(h]h ](jstructeh"]h$]h&]jjjjyjjyjjjuh1j[hhhjShNhNubj)}(h**Definition**:: struct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; }; **Members** ``queue_id`` The queue ID to be destroyed ``pad`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubh:}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMPhjyubj)}(hFstruct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; };h]hFstruct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; };}hjysbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMRhjyubh)}(h **Members**h]j)}(hjyh]hMembers}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMWhjyubj)}(hhh](j)}(h*``queue_id`` The queue ID to be destroyed h](j)}(h ``queue_id``h]jC)}(hjzh]hqueue_id}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjzubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMQhjyubj)}(hhh]h)}(hThe queue ID to be destroyedh]hThe queue ID to be destroyed}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMQhjzubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jhjzhMQhjyubj)}(h ``pad`` MBZh](j)}(h``pad``h]jC)}(hj>zh]hpad}(hj@zhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj|h]hMembers}(hj@|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<|ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMohj |ubj)}(hhh](j)}(h)``sync_type`` One of drm_asahi_sync_type h](j)}(h ``sync_type``h]jC)}(hj]|h]h sync_type}(hj_|hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj[|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMghjW|ubj)}(hhh]h)}(hOne of drm_asahi_sync_typeh]hOne of drm_asahi_sync_type}(hjv|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjr|hMghjs|ubah}(h]h ]h"]h$]h&]uh1jhjW|ubeh}(h]h ]h"]h$]h&]uh1jhjr|hMghjT|ubj)}(h"``handle`` The sync object handle h](j)}(h ``handle``h]jC)}(hj|h]hhandle}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMjhj|ubj)}(hhh]h)}(hThe sync object handleh]hThe sync object handle}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMjhj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hMjhjT|ubj)}(h;``timeline_value`` Timeline value for timeline sync objectsh](j)}(h``timeline_value``h]jC)}(hj|h]htimeline_value}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMlhj|ubj)}(hhh]h)}(h(Timeline value for timeline sync objectsh]h(Timeline value for timeline sync objects}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMmhj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hMlhjT|ubeh}(h]h ]h"]h$]h&]uh1jhj |ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW DRM_ASAHI_BARRIER_NONE (C macro)c.DRM_ASAHI_BARRIER_NONEhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hDRM_ASAHI_BARRIER_NONEh]jg)}(hDRM_ASAHI_BARRIER_NONEh]j)}(hDRM_ASAHI_BARRIER_NONEh]j)}(hj#}h]hDRM_ASAHI_BARRIER_NONE}(hj-}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)}ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj%}hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMqubah}(h]h ]h"]h$]h&]jjjuh1jfjjhj!}hhhj@}hMqubah}(h]j}ah ](jjeh"]h$]h&]jj)jhuh1j`hj@}hMqhj}hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj}hhhj@}hMqubeh}(h]h ](jmacroeh"]h$]h&]jjjjY}jjY}jjjuh1j[hhhjShNhNubh)}(h``DRM_ASAHI_BARRIER_NONE``h]jC)}(hj_}h]hDRM_ASAHI_BARRIER_NONE}(hja}hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj]}ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMshjShhubjK)}(h Command index for no barrier **Description** This special value may be passed in to drm_asahi_command::vdm_barrier or drm_asahi_command::cdm_barrier to indicate that the respective subqueue should not wait on any previous work. h](jK)}(hCommand index for no barrier h]h)}(hCommand index for no barrierh]hCommand index for no barrier}(hj}}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMqhjy}ubah}(h]h ]h"]h$]h&]uh1jJhj}hMqhju}ubh)}(h**Description**h]j)}(hj}h]h Description}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMshju}ubh)}(hThis special value may be passed in to drm_asahi_command::vdm_barrier or drm_asahi_command::cdm_barrier to indicate that the respective subqueue should not wait on any previous work.h]hThis special value may be passed in to drm_asahi_command::vdm_barrier or drm_asahi_command::cdm_barrier to indicate that the respective subqueue should not wait on any previous work.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMrhju}ubeh}(h]h ]h"]h$]h&]uh1jJhj}hMqhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_cmd_header (C struct)c.drm_asahi_cmd_headerhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_cmd_headerh]jg)}(hstruct drm_asahi_cmd_headerh](jm)}(hjph]hstruct}(hj}hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj}hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMyubj)}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj}hhhj}hMyubj)}(hdrm_asahi_cmd_headerh]j)}(hj}h]hdrm_asahi_cmd_header}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj}hhhj}hMyubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj}hhhj}hMyubah}(h]j}ah ](jjeh"]h$]h&]jj)jhuh1j`hj}hMyhj}hhubj)}(hhh]h)}(hTop level command structureh]hTop level command structure}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMzhj~hhubah}(h]h ]h"]h$]h&]uh1jhj}hhhj}hMyubeh}(h]h ](jstructeh"]h$]h&]jjjj2~jj2~jjjuh1j[hhhjShNhNubj)}(hX**Definition**:: struct drm_asahi_cmd_header { __u16 cmd_type; __u16 size; __u16 vdm_barrier; __u16 cdm_barrier; }; **Members** ``cmd_type`` One of drm_asahi_cmd_type ``size`` Size of this command, not including this header. For hardware commands, this enables extensibility of commands without requiring extra command types. Passing a command that is shorter than expected is explicitly allowed for backwards-compatibility. Truncated fields will be zeroed. For the synthetic attachment setting commands, this implicitly encodes the number of attachments. These commands take multiple fixed-size **drm_asahi_attachment** structures as their payload, so size equals number of attachments * sizeof(struct drm_asahi_attachment). ``vdm_barrier`` VDM (render) command index to wait on. Barriers are indices relative to the beginning of a given submit. A barrier of 0 waits on commands submitted to the respective subqueue in previous submit ioctls. A barrier of N waits on N previous commands on the subqueue within the current submit ioctl. As a special case, passing **DRM_ASAHI_BARRIER_NONE** avoids waiting on any commands in the subqueue. Examples: 0: This waits on all previous work. NONE: This does not wait for anything on this subqueue. 1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit. Barriers are valid only for hardware commands. Synthetic software commands to set attachments must pass NONE here. ``cdm_barrier`` CDM (compute) command index to wait on. See **vdm_barrier**, and replace VDM/render with CDM/compute.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj>~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:~ubh:}(hj:~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM~hj6~ubj)}(hrstruct drm_asahi_cmd_header { __u16 cmd_type; __u16 size; __u16 vdm_barrier; __u16 cdm_barrier; };h]hrstruct drm_asahi_cmd_header { __u16 cmd_type; __u16 size; __u16 vdm_barrier; __u16 cdm_barrier; };}hjW~sbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj6~ubh)}(h **Members**h]j)}(hjh~h]hMembers}(hjj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf~ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj6~ubj)}(hhh](j)}(h'``cmd_type`` One of drm_asahi_cmd_type h](j)}(h ``cmd_type``h]jC)}(hj~h]hcmd_type}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj~ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj~ubj)}(hhh]h)}(hOne of drm_asahi_cmd_typeh]hOne of drm_asahi_cmd_type}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hMhj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hMhj~~ubj)}(hX1``size`` Size of this command, not including this header. For hardware commands, this enables extensibility of commands without requiring extra command types. Passing a command that is shorter than expected is explicitly allowed for backwards-compatibility. Truncated fields will be zeroed. For the synthetic attachment setting commands, this implicitly encodes the number of attachments. These commands take multiple fixed-size **drm_asahi_attachment** structures as their payload, so size equals number of attachments * sizeof(struct drm_asahi_attachment). h](j)}(h``size``h]jC)}(hj~h]hsize}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj~ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj~ubj)}(hhh](h)}(h0Size of this command, not including this header.h]h0Size of this command, not including this header.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj~ubh)}(hFor hardware commands, this enables extensibility of commands without requiring extra command types. Passing a command that is shorter than expected is explicitly allowed for backwards-compatibility. Truncated fields will be zeroed.h]hFor hardware commands, this enables extensibility of commands without requiring extra command types. Passing a command that is shorter than expected is explicitly allowed for backwards-compatibility. Truncated fields will be zeroed.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj~ubh)}(hX For the synthetic attachment setting commands, this implicitly encodes the number of attachments. These commands take multiple fixed-size **drm_asahi_attachment** structures as their payload, so size equals number of attachments * sizeof(struct drm_asahi_attachment).h](hFor the synthetic attachment setting commands, this implicitly encodes the number of attachments. These commands take multiple fixed-size }(hj~hhhNhNubj)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubhi structures as their payload, so size equals number of attachments * sizeof(struct drm_asahi_attachment).}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj~ubeh}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hMhj~~ubj)}(hX ``vdm_barrier`` VDM (render) command index to wait on. Barriers are indices relative to the beginning of a given submit. A barrier of 0 waits on commands submitted to the respective subqueue in previous submit ioctls. A barrier of N waits on N previous commands on the subqueue within the current submit ioctl. As a special case, passing **DRM_ASAHI_BARRIER_NONE** avoids waiting on any commands in the subqueue. Examples: 0: This waits on all previous work. NONE: This does not wait for anything on this subqueue. 1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit. Barriers are valid only for hardware commands. Synthetic software commands to set attachments must pass NONE here. h](j)}(h``vdm_barrier``h]jC)}(hj*h]h vdm_barrier}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj(ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj$ubj)}(hhh](h)}(h&VDM (render) command index to wait on.h]h&VDM (render) command index to wait on.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj@ubh)}(hXeBarriers are indices relative to the beginning of a given submit. A barrier of 0 waits on commands submitted to the respective subqueue in previous submit ioctls. A barrier of N waits on N previous commands on the subqueue within the current submit ioctl. As a special case, passing **DRM_ASAHI_BARRIER_NONE** avoids waiting on any commands in the subqueue.h](hXBarriers are indices relative to the beginning of a given submit. A barrier of 0 waits on commands submitted to the respective subqueue in previous submit ioctls. A barrier of N waits on N previous commands on the subqueue within the current submit ioctl. As a special case, passing }(hjRhhhNhNubj)}(h**DRM_ASAHI_BARRIER_NONE**h]hDRM_ASAHI_BARRIER_NONE}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubh0 avoids waiting on any commands in the subqueue.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj@ubh)}(h Examples:h]h Examples:}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj@ubjK)}(h0: This waits on all previous work. NONE: This does not wait for anything on this subqueue. 1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit. h](h)}(h#0: This waits on all previous work.h]h#0: This waits on all previous work.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubh)}(h7NONE: This does not wait for anything on this subqueue.h]h7NONE: This does not wait for anything on this subqueue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubh)}(h1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit.h]h1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jJhjhMhj@ubh)}(hrBarriers are valid only for hardware commands. Synthetic software commands to set attachments must pass NONE here.h]hrBarriers are valid only for hardware commands. Synthetic software commands to set attachments must pass NONE here.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj@ubeh}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj~~ubj)}(hv``cdm_barrier`` CDM (compute) command index to wait on. See **vdm_barrier**, and replace VDM/render with CDM/compute.h](j)}(h``cdm_barrier``h]jC)}(hjh]h cdm_barrier}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh](h)}(h'CDM (compute) command index to wait on.h]h'CDM (compute) command index to wait on.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubh)}(h=See **vdm_barrier**, and replace VDM/render with CDM/compute.h](hSee }(hjhhhNhNubj)}(h**vdm_barrier**h]h vdm_barrier}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh*, and replace VDM/render with CDM/compute.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj~~ubeh}(h]h ]h"]h$]h&]uh1jhj6~ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hj>h]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hUThis struct is core to the command buffer definition and therefore is not extensible.h]hUThis struct is core to the command buffer definition and therefore is not extensible.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM{hjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_submit (C struct)c.drm_asahi_submithNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_submith]jg)}(hstruct drm_asahi_submith](jm)}(hjph]hstruct}(hj|hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjxhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjxhhhjhMubj)}(hdrm_asahi_submith]j)}(hjvh]hdrm_asahi_submit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjxhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjthhhjhMubah}(h]joah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjqhhubj)}(hhh]h)}(h*Arguments passed to DRM_IOCTL_ASAHI_SUBMITh]h*Arguments passed to DRM_IOCTL_ASAHI_SUBMIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjqhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjրjjրjjjuh1j[hhhjShNhNubj)}(hXv**Definition**:: struct drm_asahi_submit { __u64 syncs; __u64 cmdbuf; __u32 flags; __u32 queue_id; __u32 in_sync_count; __u32 out_sync_count; __u32 cmdbuf_size; __u32 pad; }; **Members** ``syncs`` An optional pointer to an array of drm_asahi_sync. The first **in_sync_count** elements are in-syncs, then the remaining **out_sync_count** elements are out-syncs. Using a single array with explicit partitioning simplifies handling. ``cmdbuf`` Pointer to the command buffer to submit. This is a flat command buffer. By design, it contains no CPU pointers, which makes it suitable for a virtgpu wire protocol without requiring any serializing/deserializing step. It consists of a series of commands. Each command begins with a fixed-size **drm_asahi_cmd_header** header and is followed by a variable-length payload according to the type and size in the header. The combined count of "real" hardware commands must be nonzero and at most drm_asahi_params_global::max_commands_per_submission. ``flags`` Flags for command submission (MBZ) ``queue_id`` The queue ID to be submitted to ``in_sync_count`` Number of sync objects to wait on before starting this job. ``out_sync_count`` Number of sync objects to signal upon completion of this job. ``cmdbuf_size`` Command buffer size in bytes ``pad`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjހubh:}(hjހhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjڀubj)}(hstruct drm_asahi_submit { __u64 syncs; __u64 cmdbuf; __u32 flags; __u32 queue_id; __u32 in_sync_count; __u32 out_sync_count; __u32 cmdbuf_size; __u32 pad; };h]hstruct drm_asahi_submit { __u64 syncs; __u64 cmdbuf; __u32 flags; __u32 queue_id; __u32 in_sync_count; __u32 out_sync_count; __u32 cmdbuf_size; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjڀubh)}(h **Members**h]j)}(hj h]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjڀubj)}(hhh](j)}(h``syncs`` An optional pointer to an array of drm_asahi_sync. The first **in_sync_count** elements are in-syncs, then the remaining **out_sync_count** elements are out-syncs. Using a single array with explicit partitioning simplifies handling. h](j)}(h ``syncs``h]jC)}(hj+h]hsyncs}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj)ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj%ubj)}(hhh]h)}(hAn optional pointer to an array of drm_asahi_sync. The first **in_sync_count** elements are in-syncs, then the remaining **out_sync_count** elements are out-syncs. Using a single array with explicit partitioning simplifies handling.h](h=An optional pointer to an array of drm_asahi_sync. The first }(hjDhhhNhNubj)}(h**in_sync_count**h]h in_sync_count}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubh+ elements are in-syncs, then the remaining }(hjDhhhNhNubj)}(h**out_sync_count**h]hout_sync_count}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubh] elements are out-syncs. Using a single array with explicit partitioning simplifies handling.}(hjDhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjAubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj"ubj)}(hX/``cmdbuf`` Pointer to the command buffer to submit. This is a flat command buffer. By design, it contains no CPU pointers, which makes it suitable for a virtgpu wire protocol without requiring any serializing/deserializing step. It consists of a series of commands. Each command begins with a fixed-size **drm_asahi_cmd_header** header and is followed by a variable-length payload according to the type and size in the header. The combined count of "real" hardware commands must be nonzero and at most drm_asahi_params_global::max_commands_per_submission. h](j)}(h ``cmdbuf``h]jC)}(hjh]hcmdbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh](h)}(h(Pointer to the command buffer to submit.h]h(Pointer to the command buffer to submit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubh)}(hThis is a flat command buffer. By design, it contains no CPU pointers, which makes it suitable for a virtgpu wire protocol without requiring any serializing/deserializing step.h]hThis is a flat command buffer. By design, it contains no CPU pointers, which makes it suitable for a virtgpu wire protocol without requiring any serializing/deserializing step.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubh)}(hIt consists of a series of commands. Each command begins with a fixed-size **drm_asahi_cmd_header** header and is followed by a variable-length payload according to the type and size in the header.h](hKIt consists of a series of commands. Each command begins with a fixed-size }(hjhhhNhNubj)}(h**drm_asahi_cmd_header**h]hdrm_asahi_cmd_header}(hjȁhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhb header and is followed by a variable-length payload according to the type and size in the header.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubh)}(hThe combined count of "real" hardware commands must be nonzero and at most drm_asahi_params_global::max_commands_per_submission.h]hThe combined count of “real” hardware commands must be nonzero and at most drm_asahi_params_global::max_commands_per_submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj"ubj)}(h-``flags`` Flags for command submission (MBZ) h](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h"Flags for command submission (MBZ)h]h"Flags for command submission (MBZ)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj"ubj)}(h-``queue_id`` The queue ID to be submitted to h](j)}(h ``queue_id``h]jC)}(hj;h]hqueue_id}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj9ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj5ubj)}(hhh]h)}(hThe queue ID to be submitted toh]hThe queue ID to be submitted to}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhMhj"ubj)}(hN``in_sync_count`` Number of sync objects to wait on before starting this job. h](j)}(h``in_sync_count``h]jC)}(hjth]h in_sync_count}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjrubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjnubj)}(hhh]h)}(h;Number of sync objects to wait on before starting this job.h]h;Number of sync objects to wait on before starting this job.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjhMhj"ubj)}(hQ``out_sync_count`` Number of sync objects to signal upon completion of this job. h](j)}(h``out_sync_count``h]jC)}(hjh]hout_sync_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h=Number of sync objects to signal upon completion of this job.h]h=Number of sync objects to signal upon completion of this job.}(hjǂhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjĂubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjÂhMhj"ubj)}(h-``cmdbuf_size`` Command buffer size in bytes h](j)}(h``cmdbuf_size``h]jC)}(hjh]h cmdbuf_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hCommand buffer size in bytesh]hCommand buffer size in bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj"ubj)}(h ``pad`` MBZh](j)}(h``pad``h]jC)}(hj!h]hpad}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj"ubeh}(h]h ]h"]h$]h&]uh1jhjڀubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_attachment (C struct)c.drm_asahi_attachmenthNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_attachmenth]jg)}(hstruct drm_asahi_attachmenth](jm)}(hjph]hstruct}(hj{hhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjwhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjwhhhjhMubj)}(hdrm_asahi_attachmenth]j)}(hjuh]hdrm_asahi_attachment}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjwhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjshhhjhMubah}(h]jnah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjphhubj)}(hhh]h)}(hDescribe an "attachment".h]hDescribe an “attachment”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjphhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjՃjjՃjjjuh1j[hhhjShNhNubj)}(hX**Definition**:: struct drm_asahi_attachment { __u64 pointer; __u64 size; __u32 pad; __u32 flags; }; **Members** ``pointer`` Base address of the attachment ``size`` Size of the attachment in bytes ``pad`` MBZ ``flags`` MBZh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj݃ubh:}(hj݃hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjكubj)}(hcstruct drm_asahi_attachment { __u64 pointer; __u64 size; __u32 pad; __u32 flags; };h]hcstruct drm_asahi_attachment { __u64 pointer; __u64 size; __u32 pad; __u32 flags; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjكubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjكubj)}(hhh](j)}(h+``pointer`` Base address of the attachment h](j)}(h ``pointer``h]jC)}(hj*h]hpointer}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj(ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj$ubj)}(hhh]h)}(hBase address of the attachmenth]hBase address of the attachment}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj!ubj)}(h)``size`` Size of the attachment in bytes h](j)}(h``size``h]jC)}(hjch]hsize}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj]ubj)}(hhh]h)}(hSize of the attachment in bytesh]hSize of the attachment in bytes}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhMhj!ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]jC)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj!ubj)}(h ``flags`` MBZh](j)}(h ``flags``h]jC)}(hjՄh]hflags}(hjׄhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjӄubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjτubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjτubeh}(h]h ]h"]h$]h&]uh1jhjhMhj!ubeh}(h]h ]h"]h$]h&]uh1jhjكubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hXAttachments are any memory written by shaders, notably including render target attachments written by the end-of-tile program. This is purely a hint about the accessed memory regions. It is optional to specify, which is fortunate as it cannot be specified precisely with bindless access anyway. But where possible, it's probably a good idea for userspace to include these hints, forwarded to the firmware.h]hXAttachments are any memory written by shaders, notably including render target attachments written by the end-of-tile program. This is purely a hint about the accessed memory regions. It is optional to specify, which is fortunate as it cannot be specified precisely with bindless access anyway. But where possible, it’s probably a good idea for userspace to include these hints, forwarded to the firmware.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(h@This struct is implicitly sized and therefore is not extensible.h]h@This struct is implicitly sized and therefore is not extensible.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_zls_buffer (C struct)c.drm_asahi_zls_bufferhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_zls_bufferh]jg)}(hstruct drm_asahi_zls_bufferh](jm)}(hjph]hstruct}(hjehhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjahhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjahhhjrhMubj)}(hdrm_asahi_zls_bufferh]j)}(hj_h]hdrm_asahi_zls_buffer}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjahhhjrhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj]hhhjrhMubah}(h]jXah ](jjeh"]h$]h&]jj)jhuh1j`hjrhMhjZhhubj)}(hhh]h)}(h#Describe a depth or stencil buffer.h]h#Describe a depth or stencil buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM(hjhhubah}(h]h ]h"]h$]h&]uh1jhjZhhhjrhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjShNhNubj)}(hX**Definition**:: struct drm_asahi_zls_buffer { __u64 base; __u64 comp_base; __u32 stride; __u32 comp_stride; }; **Members** ``base`` Base address of the buffer ``comp_base`` If the load buffer is compressed, address of the compression metadata section. ``stride`` If layered rendering is enabled, the number of bytes between each layer of the buffer. ``comp_stride`` If layered rendering is enabled, the number of bytes between each layer of the compression metadata.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj˅hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDžubh:}(hjDžhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM,hjÅubj)}(hnstruct drm_asahi_zls_buffer { __u64 base; __u64 comp_base; __u32 stride; __u32 comp_stride; };h]hnstruct drm_asahi_zls_buffer { __u64 base; __u64 comp_base; __u32 stride; __u32 comp_stride; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM.hjÅubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM5hjÅubj)}(hhh](j)}(h$``base`` Base address of the buffer h](j)}(h``base``h]jC)}(hjh]hbase}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM4hjubj)}(hhh]h)}(hBase address of the bufferh]hBase address of the buffer}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hM4hj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj)hM4hj ubj)}(h]``comp_base`` If the load buffer is compressed, address of the compression metadata section. h](j)}(h ``comp_base``h]jC)}(hjMh]h comp_base}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjKubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM9hjGubj)}(hhh]h)}(hNIf the load buffer is compressed, address of the compression metadata section.h]hNIf the load buffer is compressed, address of the compression metadata section.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM8hjcubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjbhM9hj ubj)}(hb``stride`` If layered rendering is enabled, the number of bytes between each layer of the buffer. h](j)}(h ``stride``h]jC)}(hjh]hstride}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM?hjubj)}(hhh]h)}(hVIf layered rendering is enabled, the number of bytes between each layer of the buffer.h]hVIf layered rendering is enabled, the number of bytes between each layer of the buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM>hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM?hj ubj)}(ht``comp_stride`` If layered rendering is enabled, the number of bytes between each layer of the compression metadata.h](j)}(h``comp_stride``h]jC)}(hjh]h comp_stride}(hjÆhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMDhjubj)}(hhh]h)}(hdIf layered rendering is enabled, the number of bytes between each layer of the compression metadata.h]hdIf layered rendering is enabled, the number of bytes between each layer of the compression metadata.}(hjچhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjֆhMDhj׆ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjֆhMDhj ubeh}(h]h ]h"]h$]h&]uh1jhjÅubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMHhjShhubh)}(hXdThese fields correspond to hardware registers in the ZLS (Z Load/Store) unit. There are three hardware registers for each field respectively for loads, stores, and partial renders. In practice, it makes sense to set all to the same values, except in exceptional cases not yet implemented in userspace, so we do not duplicate here for simplicity/efficiency.h]hXdThese fields correspond to hardware registers in the ZLS (Z Load/Store) unit. There are three hardware registers for each field respectively for loads, stores, and partial renders. In practice, it makes sense to set all to the same values, except in exceptional cases not yet implemented in userspace, so we do not duplicate here for simplicity/efficiency.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM)hjShhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM/hjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_timestamp (C struct)c.drm_asahi_timestamphNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_timestamph]jg)}(hstruct drm_asahi_timestamph](jm)}(hjph]hstruct}(hjPhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjLhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM4ubj)}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjLhhhj]hM4ubj)}(hdrm_asahi_timestamph]j)}(hjJh]hdrm_asahi_timestamp}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubah}(h]h ](jjeh"]h$]h&]jjuh1jhjLhhhj]hM4ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjHhhhj]hM4ubah}(h]jCah ](jjeh"]h$]h&]jj)jhuh1j`hj]hM4hjEhhubj)}(hhh]h)}(hDescribe a timestamp write.h]hDescribe a timestamp write.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMJhjhhubah}(h]h ]h"]h$]h&]uh1jhjEhhhj]hM4ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjShNhNubj)}(hXM**Definition**:: struct drm_asahi_timestamp { __u32 handle; __u32 offset; }; **Members** ``handle`` Handle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle. ``offset`` Offset to write into the timestamp bufferh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMNhjubj)}(hCstruct drm_asahi_timestamp { __u32 handle; __u32 offset; };h]hCstruct drm_asahi_timestamp { __u32 handle; __u32 offset; };}hjχsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMPhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjއubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMUhjubj)}(hhh](j)}(h``handle`` Handle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle. h](j)}(h ``handle``h]jC)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMXhjubj)}(hhh]h)}(hHandle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle.h]hHandle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMVhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMXhjubj)}(h4``offset`` Offset to write into the timestamp bufferh](j)}(h ``offset``h]jC)}(hj9h]hoffset}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj7ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM[hj3ubj)}(hhh]h)}(h)Offset to write into the timestamp bufferh]h)Offset to write into the timestamp buffer}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM\hjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhM[hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hj|h]h Description}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM_hjShhubh)}(hX The firmware can optionally write the GPU timestamp at render pass granularities, but it needs to be mapped specially via DRM_IOCTL_ASAHI_GEM_BIND_OBJECT. This structure therefore describes where to write as a handle-offset pair, rather than a GPU address like normal.h]hX The firmware can optionally write the GPU timestamp at render pass granularities, but it needs to be mapped specially via DRM_IOCTL_ASAHI_GEM_BIND_OBJECT. This structure therefore describes where to write as a handle-offset pair, rather than a GPU address like normal.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMKhjShhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMPhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_timestamps (C struct)c.drm_asahi_timestampshNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_timestampsh]jg)}(hstruct drm_asahi_timestampsh](jm)}(hjph]hstruct}(hjɈhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjňhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMUubj)}(h h]h }(hj׈hhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjňhhhjֈhMUubj)}(hdrm_asahi_timestampsh]j)}(hjÈh]hdrm_asahi_timestamps}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjňhhhjֈhMUubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjֈhMUubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjֈhMUhjhhubj)}(hhh]h)}(hDescribe timestamp writes.h]hDescribe timestamp writes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM`hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjֈhMUubeh}(h]h ](jstructeh"]h$]h&]jjjj#jj#jjjuh1j[hhhjShNhNubj)}(hX **Definition**:: struct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; }; **Members** ``start`` Timestamp recorded at the start of the operation ``end`` Timestamp recorded at the end of the operationh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubh:}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMdhj'ubj)}(hjstruct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; };h]hjstruct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; };}hjHsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMfhj'ubh)}(h **Members**h]j)}(hjYh]hMembers}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMkhj'ubj)}(hhh](j)}(h;``start`` Timestamp recorded at the start of the operation h](j)}(h ``start``h]jC)}(hjxh]hstart}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjvubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMjhjrubj)}(hhh]h)}(h0Timestamp recorded at the start of the operationh]h0Timestamp recorded at the start of the operation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMjhjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jhjhMjhjoubj)}(h6``end`` Timestamp recorded at the end of the operationh](j)}(h``end``h]jC)}(hjh]hend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMlhjubj)}(hhh]h)}(h.Timestamp recorded at the end of the operationh]h.Timestamp recorded at the end of the operation}(hjʉhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMmhjljubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjƉhMlhjoubeh}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMphjShhubh)}(hEach operation that can be timestamped, can be timestamped at the start and end. Therefore, drm_asahi_timestamp structs always come in pairs, bundled together into drm_asahi_timestamps.h]hEach operation that can be timestamped, can be timestamped at the start and end. Therefore, drm_asahi_timestamp structs always come in pairs, bundled together into drm_asahi_timestamps.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMahjShhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMehjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW#drm_asahi_helper_program (C struct)c.drm_asahi_helper_programhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_helper_programh]jg)}(hstruct drm_asahi_helper_programh](jm)}(hjph]hstruct}(hjAhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj=hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMjubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj=hhhjNhMjubj)}(hdrm_asahi_helper_programh]j)}(hj;h]hdrm_asahi_helper_program}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj=hhhjNhMjubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhj9hhhjNhMjubah}(h]j4ah ](jjeh"]h$]h&]jj)jhuh1j`hjNhMjhj6hhubj)}(hhh]h)}(h&Describe helper program configuration.h]h&Describe helper program configuration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMqhjhhubah}(h]h ]h"]h$]h&]uh1jhj6hhhjNhMjubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j[hhhjShNhNubj)}(hX**Definition**:: struct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; }; **Members** ``binary`` USC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits. ``cfg`` Additional configuration bits for the helper program. ``data`` Data passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program. In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMuhjubj)}(hUstruct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; };h]hUstruct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMwhjubh)}(h **Members**h]j)}(hjъh]hMembers}(hjӊhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϊubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM}hjubj)}(hhh](j)}(hu``binary`` USC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits. h](j)}(h ``binary``h]jC)}(hjh]hbinary}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hiUSC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits.h]hiUSC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h>``cfg`` Additional configuration bits for the helper program. h](j)}(h``cfg``h]jC)}(hj*h]hcfg}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj(ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj$ubj)}(hhh]h)}(h5Additional configuration bits for the helper program.h]h5Additional configuration bits for the helper program.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhjubj)}(hXu``data`` Data passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program. In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h](j)}(h``data``h]jC)}(hjch]hdata}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj]ubj)}(hhh](h)}(hData passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program.h]hData passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjyubh)}(h~In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h]hIn practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don’t fit in 64-bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMhjyubeh}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hXhThe helper program is a compute-like kernel required for various hardware functionality. Its most important role is dynamically allocating scratch/stack memory for individual subgroups, by partitioning a static allocation shared for the whole device. It is supplied by userspace via drm_asahi_helper_program and internally dispatched by the hardware as needed.h]hXhThe helper program is a compute-like kernel required for various hardware functionality. Its most important role is dynamically allocating scratch/stack memory for individual subgroups, by partitioning a static allocation shared for the whole device. It is supplied by userspace via drm_asahi_helper_program and internally dispatched by the hardware as needed.}(hjʋhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMrhjShhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjًhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMxhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_bg_eot (C struct)c.drm_asahi_bg_eothNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_bg_eoth]jg)}(hstruct drm_asahi_bg_eoth](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM}ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhM}ubj)}(hdrm_asahi_bg_eoth]j)}(hjh]hdrm_asahi_bg_eot}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM}ubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhM}ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhM}hjhhubj)}(hhh]h)}(h-Describe a background or end-of-tile program.h]h-Describe a background or end-of-tile program.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj@hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM}ubeh}(h]h ](jstructeh"]h$]h&]jjjj[jj[jjjuh1j[hhhjShNhNubj)}(hXm**Definition**:: struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; }; **Members** ``usc`` USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits. ``rsrc_spec`` Resource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubh:}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj_ubj)}(h@struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; };h]h@struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj_ubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj_ubj)}(hhh](j)}(hX>``usc`` USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits. h](j)}(h``usc``h]jC)}(hjh]husc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hX5USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits.h]hX5USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits.}(hjɌhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjƌubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjŌhMhjubj)}(h``rsrc_spec`` Resource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h](j)}(h ``rsrc_spec``h]jC)}(hjh]h rsrc_spec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hResource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h]hResource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hj-h]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hXThe background and end-of-tile programs are dispatched by the hardware at the beginning and end of rendering. As the hardware "tilebuffer" is simply local memory, these programs are necessary to implement API-level render targets. The fragment-like background program is responsible for loading either the clear colour or the existing render target contents, while the compute-like end-of-tile program stores the tilebuffer contents to memory.h]hXThe background and end-of-tile programs are dispatched by the hardware at the beginning and end of rendering. As the hardware “tilebuffer” is simply local memory, these programs are necessary to implement API-level render targets. The fragment-like background program is responsible for loading either the clear colour or the existing render target contents, while the compute-like end-of-tile program stores the tilebuffer contents to memory.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_cmd_render (C struct)c.drm_asahi_cmd_renderhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_cmd_renderh]jg)}(hstruct drm_asahi_cmd_renderh](jm)}(hjph]hstruct}(hjzhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjvhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjvhhhjhMubj)}(hdrm_asahi_cmd_renderh]j)}(hjth]hdrm_asahi_cmd_render}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjvhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjrhhhjhMubah}(h]jmah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjohhubj)}(hhh]h)}(hCommand to submit 3Dh]hCommand to submit 3D}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjohhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjԍjjԍjjjuh1j[hhhjShNhNubj)}(hXh**Definition**:: struct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; }; **Members** ``flags`` Combination of drm_asahi_render_flags flags. ``isp_zls_pixels`` ISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height. ``vdm_ctrl_stream_base`` VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream. ``vertex_helper`` Helper program used for the vertex shader ``fragment_helper`` Helper program used for the fragment shader ``isp_scissor_base`` ISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass. ``isp_dbias_base`` ISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass. ``isp_oclqry_base`` ISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass. ``depth`` Depth buffer ``stencil`` Stencil buffer ``zls_ctrl`` ZLS_CTRL register value ``ppp_multisamplectl`` PPP_MULTISAMPLECTL register value ``sampler_heap`` Base address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps. ``ppp_ctrl`` PPP_CTRL register value ``width_px`` Framebuffer width in pixels ``height_px`` Framebuffer height in pixels ``layers`` Number of layers in the framebuffer ``sampler_count`` Number of samplers in the sampler heap. ``utile_width_px`` Width of a logical tilebuffer tile in pixels ``utile_height_px`` Height of a logical tilebuffer tile in pixels ``samples`` # of samples in the framebuffer. Must be 1, 2, or 4. ``sample_size_B`` # of bytes in the tilebuffer required per sample. ``isp_merge_upper_x`` 32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width. Making these values UAPI avoids requiring floating-point calculations in the kernel in the hot path. ``isp_merge_upper_y`` 32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**. ``bg`` Background program run for each tile at the start ``eot`` End-of-tile program ran for each tile at the end ``partial_bg`` Background program ran at the start of each tile when resuming the render pass during a partial render. ``partial_eot`` End-of-tile program ran at the end of each tile when pausing the render pass during a partial render. ``isp_bgobjdepth`` ISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed). ``isp_bgobjvals`` ISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value. ``ts_vtx`` Timestamps for the vertex portion of the render ``ts_frag`` Timestamps for the fragment portion of the renderh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj܍ubh:}(hj܍hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj؍ubj)}(hXstruct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; };h]hXstruct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj؍ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj؍ubj)}(hhh](j)}(h7``flags`` Combination of drm_asahi_render_flags flags. h](j)}(h ``flags``h]jC)}(hj)h]hflags}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj'ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj#ubj)}(hhh]h)}(h,Combination of drm_asahi_render_flags flags.h]h,Combination of drm_asahi_render_flags flags.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhj ubj)}(h``isp_zls_pixels`` ISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height. h](j)}(h``isp_zls_pixels``h]jC)}(hjbh]hisp_zls_pixels}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj\ubj)}(hhh]h)}(hISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height.h]hISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jhjwhMhj ubj)}(hv``vdm_ctrl_stream_base`` VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream. h](j)}(h``vdm_ctrl_stream_base``h]jC)}(hjh]hvdm_ctrl_stream_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h\VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream.h]h\VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h<``vertex_helper`` Helper program used for the vertex shader h](j)}(h``vertex_helper``h]jC)}(hj֎h]h vertex_helper}(hj؎hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjԎubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjЎubj)}(hhh]h)}(h)Helper program used for the vertex shaderh]h)Helper program used for the vertex shader}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjЎubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h@``fragment_helper`` Helper program used for the fragment shader h](j)}(h``fragment_helper``h]jC)}(hjh]hfragment_helper}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj ubj)}(hhh]h)}(h+Helper program used for the fragment shaderh]h+Helper program used for the fragment shader}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMhj%ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhj ubj)}(h``isp_scissor_base`` ISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass. h](j)}(h``isp_scissor_base``h]jC)}(hjHh]hisp_scissor_base}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjFubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjBubj)}(hhh]h)}(hkISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass.h]hkISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj^ubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhj]hMhj ubj)}(h{``isp_dbias_base`` ISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass. h](j)}(h``isp_dbias_base``h]jC)}(hjh]hisp_dbias_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj|ubj)}(hhh]h)}(hgISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass.h]hgISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h``isp_oclqry_base`` ISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass. h](j)}(h``isp_oclqry_base``h]jC)}(hjh]hisp_oclqry_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hnISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass.h]hnISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass.}(hjՏhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjҏubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjяhMhj ubj)}(h``depth`` Depth buffer h](j)}(h ``depth``h]jC)}(hjh]hdepth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h Depth bufferh]h Depth buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubj)}(h``stencil`` Stencil buffer h](j)}(h ``stencil``h]jC)}(hj/h]hstencil}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj-ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj)ubj)}(hhh]h)}(hStencil bufferh]hStencil buffer}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjEubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhjDhMhj ubj)}(h%``zls_ctrl`` ZLS_CTRL register value h](j)}(h ``zls_ctrl``h]jC)}(hjhh]hzls_ctrl}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjbubj)}(hhh]h)}(hZLS_CTRL register valueh]hZLS_CTRL register value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj~ubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj ubj)}(h9``ppp_multisamplectl`` PPP_MULTISAMPLECTL register value h](j)}(h``ppp_multisamplectl``h]jC)}(hjh]hppp_multisamplectl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h!PPP_MULTISAMPLECTL register valueh]h!PPP_MULTISAMPLECTL register value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h``sampler_heap`` Base address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps. h](j)}(h``sampler_heap``h]jC)}(hjڐh]h sampler_heap}(hjܐhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjؐubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjԐubj)}(hhh]h)}(hBase address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps.h]hBase address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjԐubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h%``ppp_ctrl`` PPP_CTRL register value h](j)}(h ``ppp_ctrl``h]jC)}(hjh]hppp_ctrl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM hjubj)}(hhh]h)}(hPPP_CTRL register valueh]hPPP_CTRL register value}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hM hj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj)hM hj ubj)}(h)``width_px`` Framebuffer width in pixels h](j)}(h ``width_px``h]jC)}(hjMh]hwidth_px}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjKubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM hjGubj)}(hhh]h)}(hFramebuffer width in pixelsh]hFramebuffer width in pixels}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhM hjcubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjbhM hj ubj)}(h+``height_px`` Framebuffer height in pixels h](j)}(h ``height_px``h]jC)}(hjh]h height_px}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hFramebuffer height in pixelsh]hFramebuffer height in pixels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h/``layers`` Number of layers in the framebuffer h](j)}(h ``layers``h]jC)}(hjh]hlayers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h#Number of layers in the framebufferh]h#Number of layers in the framebuffer}(hjؑhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjԑhMhjՑubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjԑhMhj ubj)}(h:``sampler_count`` Number of samplers in the sampler heap. h](j)}(h``sampler_count``h]jC)}(hjh]h sampler_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h'Number of samplers in the sampler heap.h]h'Number of samplers in the sampler heap.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhj ubj)}(h@``utile_width_px`` Width of a logical tilebuffer tile in pixels h](j)}(h``utile_width_px``h]jC)}(hj1h]hutile_width_px}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj/ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj+ubj)}(hhh]h)}(h,Width of a logical tilebuffer tile in pixelsh]h,Width of a logical tilebuffer tile in pixels}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhMhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjFhMhj ubj)}(hB``utile_height_px`` Height of a logical tilebuffer tile in pixels h](j)}(h``utile_height_px``h]jC)}(hjjh]hutile_height_px}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjdubj)}(hhh]h)}(h-Height of a logical tilebuffer tile in pixelsh]h-Height of a logical tilebuffer tile in pixels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(hA``samples`` # of samples in the framebuffer. Must be 1, 2, or 4. h](j)}(h ``samples``h]jC)}(hjh]hsamples}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h4# of samples in the framebuffer. Must be 1, 2, or 4.h]h4# of samples in the framebuffer. Must be 1, 2, or 4.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(hD``sample_size_B`` # of bytes in the tilebuffer required per sample. h](j)}(h``sample_size_B``h]jC)}(hjܒh]h sample_size_B}(hjޒhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjڒubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM!hj֒ubj)}(hhh]h)}(h1# of bytes in the tilebuffer required per sample.h]h1# of bytes in the tilebuffer required per sample.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM!hjubah}(h]h ]h"]h$]h&]uh1jhj֒ubeh}(h]h ]h"]h$]h&]uh1jhjhM!hj ubj)}(h``isp_merge_upper_x`` 32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width. Making these values UAPI avoids requiring floating-point calculations in the kernel in the hot path. h](j)}(h``isp_merge_upper_x``h]jC)}(hjh]hisp_merge_upper_x}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM)hjubj)}(hhh](h)}(hV32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width.h]hV32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM%hj+ubh)}(hdMaking these values UAPI avoids requiring floating-point calculations in the kernel in the hot path.h]hdMaking these values UAPI avoids requiring floating-point calculations in the kernel in the hot path.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM(hj+ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hM)hj ubj)}(hc``isp_merge_upper_y`` 32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**. h](j)}(h``isp_merge_upper_y``h]jC)}(hj^h]hisp_merge_upper_y}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM/hjXubj)}(hhh]h)}(hL32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**.h](h632-bit float. Calculate as: tan(60 deg) * height. See }(hjwhhhNhNubj)}(h**isp_merge_upper_x**h]hisp_merge_upper_x}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubh.}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM.hjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jhjshM/hj ubj)}(h9``bg`` Background program run for each tile at the start h](j)}(h``bg``h]jC)}(hjh]hbg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM3hjubj)}(hhh]h)}(h1Background program run for each tile at the starth]h1Background program run for each tile at the start}(hjÓhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM3hj ubj)}(h9``eot`` End-of-tile program ran for each tile at the end h](j)}(h``eot``h]jC)}(hjh]heot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM6hjݓubj)}(hhh]h)}(h0End-of-tile program ran for each tile at the endh]h0End-of-tile program ran for each tile at the end}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM6hjubah}(h]h ]h"]h$]h&]uh1jhjݓubeh}(h]h ]h"]h$]h&]uh1jhjhM6hj ubj)}(hw``partial_bg`` Background program ran at the start of each tile when resuming the render pass during a partial render. h](j)}(h``partial_bg``h]jC)}(hjh]h partial_bg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM;hjubj)}(hhh]h)}(hgBackground program ran at the start of each tile when resuming the render pass during a partial render.h]hgBackground program ran at the start of each tile when resuming the render pass during a partial render.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM:hj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj1hM;hj ubj)}(hv``partial_eot`` End-of-tile program ran at the end of each tile when pausing the render pass during a partial render. h](j)}(h``partial_eot``h]jC)}(hjVh]h partial_eot}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjTubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMAhjPubj)}(hhh]h)}(heEnd-of-tile program ran at the end of each tile when pausing the render pass during a partial render.h]heEnd-of-tile program ran at the end of each tile when pausing the render pass during a partial render.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM@hjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhjkhMAhj ubj)}(h``isp_bgobjdepth`` ISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed). h](j)}(h``isp_bgobjdepth``h]jC)}(hjh]hisp_bgobjdepth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMHhjubj)}(hhh]h)}(hISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed).h]hISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer’s format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMFhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMHhj ubj)}(hj``isp_bgobjvals`` ISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value. h](j)}(h``isp_bgobjvals``h]jC)}(hjʔh]h isp_bgobjvals}(hj̔hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjȔubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMNhjĔubj)}(hhh]h)}(hWISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value.h]hWISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMMhjubah}(h]h ]h"]h$]h&]uh1jhjĔubeh}(h]h ]h"]h$]h&]uh1jhjߔhMNhj ubj)}(h;``ts_vtx`` Timestamps for the vertex portion of the render h](j)}(h ``ts_vtx``h]jC)}(hjh]hts_vtx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMRhjubj)}(hhh]h)}(h/Timestamps for the vertex portion of the renderh]h/Timestamps for the vertex portion of the render}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMRhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMRhj ubj)}(h=``ts_frag`` Timestamps for the fragment portion of the renderh](j)}(h ``ts_frag``h]jC)}(hj=h]hts_frag}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj;ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMThj7ubj)}(hhh]h)}(h1Timestamps for the fragment portion of the renderh]h1Timestamps for the fragment portion of the render}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMUhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhjRhMThj ubeh}(h]h ]h"]h$]h&]uh1jhj؍ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMXhjShhubh)}(hThis command submits a single render pass. The hardware control stream may include many draws and subpasses, but within the command, the framebuffer dimensions and attachments are fixed.h]hThis command submits a single render pass. The hardware control stream may include many draws and subpasses, but within the command, the framebuffer dimensions and attachments are fixed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hXBThe hardware requires the firmware to set a large number of Control Registers setting up state at render pass granularity before each command rendering 3D. The firmware bundles this state into data structures. Unfortunately, we cannot expose either any of that directly to userspace, because the kernel-firmware ABI is not stable. Although we can guarantee the firmware updates in tandem with the kernel, we cannot break old userspace when upgrading the firmware and kernel. Therefore, we need to abstract well the data structures to avoid tying our hands with future firmwares.h]hXBThe hardware requires the firmware to set a large number of Control Registers setting up state at render pass granularity before each command rendering 3D. The firmware bundles this state into data structures. Unfortunately, we cannot expose either any of that directly to userspace, because the kernel-firmware ABI is not stable. Although we can guarantee the firmware updates in tandem with the kernel, we cannot break old userspace when upgrading the firmware and kernel. Therefore, we need to abstract well the data structures to avoid tying our hands with future firmwares.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hThe bulk of drm_asahi_cmd_render therefore consists of values of hardware control registers, marshalled via the firmware interface.h]hThe bulk of drm_asahi_cmd_render therefore consists of values of hardware control registers, marshalled via the firmware interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hXThe framebuffer/tilebuffer dimensions are also specified here. In addition to being passed to the firmware/hardware, the kernel requires these dimensions to calculate various essential tiling-related data structures. It is unfortunate that our submits are heavier than on vendors with saner hardware-software interfaces. The upshot is all of this information is readily available to userspace with all current APIs.h]hXThe framebuffer/tilebuffer dimensions are also specified here. In addition to being passed to the firmware/hardware, the kernel requires these dimensions to calculate various essential tiling-related data structures. It is unfortunate that our submits are heavier than on vendors with saner hardware-software interfaces. The upshot is all of this information is readily available to userspace with all current APIs.}(hjÕhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubh)}(hiIt looks odd - but it's not overly burdensome and it ensures we can remain compatible with old userspace.h]hkIt looks odd - but it’s not overly burdensome and it ensures we can remain compatible with old userspace.}(hjҕhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jW drm_asahi_cmd_compute (C struct)c.drm_asahi_cmd_computehNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_cmd_computeh]jg)}(hstruct drm_asahi_cmd_computeh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hjhhhjhMubj)}(hdrm_asahi_cmd_computeh]j)}(hjh]hdrm_asahi_cmd_compute}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjhMhjhhubj)}(hhh]h)}(hCommand to submit computeh]hCommand to submit compute}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMYhj9hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjTjjTjjjuh1j[hhhjShNhNubj)}(hXV**Definition**:: struct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; }; **Members** ``flags`` MBZ ``sampler_count`` Number of samplers in the sampler heap. ``cdm_ctrl_stream_base`` CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream. ``cdm_ctrl_stream_end`` GPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere. ``sampler_heap`` Base address of the sampler heap. ``helper`` Helper program used for this compute command ``ts`` Timestamps for the compute commandh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh:}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM]hjXubj)}(hstruct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; };h]hstruct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; };}hjysbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM_hjXubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMihjXubj)}(hhh](j)}(h``flags`` MBZ h](j)}(h ``flags``h]jC)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMahjubj)}(hhh]h)}(hMBZh]hMBZ}(hj–hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMahjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMahjubj)}(h:``sampler_count`` Number of samplers in the sampler heap. h](j)}(h``sampler_count``h]jC)}(hjh]h sampler_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMdhjܖubj)}(hhh]h)}(h'Number of samplers in the sampler heap.h]h'Number of samplers in the sampler heap.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMdhjubah}(h]h ]h"]h$]h&]uh1jhjܖubeh}(h]h ]h"]h$]h&]uh1jhjhMdhjubj)}(hv``cdm_ctrl_stream_base`` CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream. h](j)}(h``cdm_ctrl_stream_base``h]jC)}(hjh]hcdm_ctrl_stream_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMihjubj)}(hhh]h)}(h\CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream.h]h\CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj0hMihjubj)}(h``cdm_ctrl_stream_end`` GPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere. h](j)}(h``cdm_ctrl_stream_end``h]jC)}(hjUh]hcdm_ctrl_stream_end}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjSubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMphjOubj)}(hhh]h)}(hGPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere.h]hGPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMnhjkubah}(.Qh]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhjjhMphjubj)}(h3``sampler_heap`` Base address of the sampler heap. h](j)}(h``sampler_heap``h]jC)}(hjh]h sampler_heap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMthjubj)}(hhh]h)}(h!Base address of the sampler heap.h]h!Base address of the sampler heap.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMthjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMthjubj)}(h8``helper`` Helper program used for this compute command h](j)}(h ``helper``h]jC)}(hjȗh]hhelper}(hjʗhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjƗubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMwhj—ubj)}(hhh]h)}(h,Helper program used for this compute commandh]h,Helper program used for this compute command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjݗhMwhjޗubah}(h]h ]h"]h$]h&]uh1jhj—ubeh}(h]h ]h"]h$]h&]uh1jhjݗhMwhjubj)}(h)``ts`` Timestamps for the compute commandh](j)}(h``ts``h]jC)}(hjh]hts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMyhjubj)}(hhh]h)}(h"Timestamps for the compute commandh]h"Timestamps for the compute command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMzhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMyhjubeh}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubh)}(h**Description**h]j)}(hjDh]h Description}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM}hjShhubh)}(hThis command submits a control stream consisting of compute dispatches. There is essentially no limit on how many compute dispatches may be included in a single compute command, although timestamps are at command granularity.h]hThis command submits a control stream consisting of compute dispatches. There is essentially no limit on how many compute dispatches may be included in a single compute command, although timestamps are at command granularity.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMZhjShhubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWdrm_asahi_get_time (C struct)c.drm_asahi_get_timehNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hdrm_asahi_get_timeh]jg)}(hstruct drm_asahi_get_timeh](jm)}(hjph]hstruct}(hjhhhNhNubah}(h]h ]jyah"]h$]h&]uh1jlhj~hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMaubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j~hj~hhhjhMaubj)}(hdrm_asahi_get_timeh]j)}(hj|h]hdrm_asahi_get_time}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj~hhhjhMaubeh}(h]h ]h"]h$]h&]jjjuh1jfjjhjzhhhjhMaubah}(h]juah ](jjeh"]h$]h&]jj)jhuh1j`hjhMahjwhhubj)}(hhh]h)}(h,Arguments passed to DRM_IOCTL_ASAHI_GET_TIMEh]h,Arguments passed to DRM_IOCTL_ASAHI_GET_TIME}(hjĘhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhM~hjhhubah}(h]h ]h"]h$]h&]uh1jhjwhhhjhMaubeh}(h]h ](jstructeh"]h$]h&]jjjjܘjjܘjjjuh1j[hhhjShNhNubj)}(h**Definition**:: struct drm_asahi_get_time { __u64 flags; __u64 gpu_timestamp; }; **Members** ``flags`` MBZ. ``gpu_timestamp`` On return, the GPU timestamp in nanoseconds.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hHstruct drm_asahi_get_time { __u64 flags; __u64 gpu_timestamp; };h]hHstruct drm_asahi_get_time { __u64 flags; __u64 gpu_timestamp; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh](j)}(h``flags`` MBZ. h](j)}(h ``flags``h]jC)}(hj1h]hflags}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jBhj/ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj+ubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhMhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjFhMhj(ubj)}(h>``gpu_timestamp`` On return, the GPU timestamp in nanoseconds.h](j)}(h``gpu_timestamp``h]jC)}(hjjh]h gpu_timestamp}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjdubj)}(hhh]h)}(h,On return, the GPU timestamp in nanoseconds.h]h,On return, the GPU timestamp in nanoseconds.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjhMhj(ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubjK)}(hhh]h}(h]h ]h"]h$]h&]entries](jWDRM_IOCTL_ASAHI (C macro)c.DRM_IOCTL_ASAHIhNtauh1jJhjShhhNhNubj\)}(hhh](ja)}(hDRM_IOCTL_ASAHIh]jg)}(hDRM_IOCTL_ASAHIh]j)}(hDRM_IOCTL_ASAHIh]j)}(hjh]hDRM_IOCTL_ASAHI}(hjșhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjęubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMubah}(h]h ]h"]h$]h&]jjjuh1jfjjhjhhhjۙhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j`hjۙhMhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhjۙhMubeh}(h]h ](jmacroeh"]h$]h&]jjjjjjjjjuh1j[hhhjShNhNubh)}(h,``DRM_IOCTL_ASAHI (__access, __id, __type)``h]jC)}(hjh]h(DRM_IOCTL_ASAHI (__access, __id, __type)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjShhubjK)}(hBuild an Asahi IOCTL number h]h)}(hBuild an Asahi IOCTL numberh]hBuild an Asahi IOCTL number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jJhj"hMhjShhubj)}(hXF**Parameters** ``__access`` Access type. Must be R, W or RW. ``__id`` One of the DRM_ASAHI_xxx id. ``__type`` Suffix of the type being passed to the IOCTL. **Description** Don't use this macro directly, use the DRM_IOCTL_ASAHI_xxx values instead. **Return** An IOCTL number to be passed to ioctl() from userspace.h](h)}(h**Parameters**h]j)}(hj/h]h Parameters}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj)ubj)}(hhh](j)}(h.``__access`` Access type. Must be R, W or RW. h](j)}(h ``__access``h]jC)}(hjNh]h__access}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjLubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjHubj)}(hhh]h)}(h Access type. Must be R, W or RW.h]h Access type. Must be R, W or RW.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhjchMhjEubj)}(h&``__id`` One of the DRM_ASAHI_xxx id. h](j)}(h``__id``h]jC)}(hjh]h__id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(hOne of the DRM_ASAHI_xxx id.h]hOne of the DRM_ASAHI_xxx id.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjEubj)}(h9``__type`` Suffix of the type being passed to the IOCTL. h](j)}(h ``__type``h]jC)}(hjh]h__type}(hjšhhhNhNubah}(h]h ]h"]h$]h&]uh1jBhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhjubj)}(hhh]h)}(h-Suffix of the type being passed to the IOCTL.h]h-Suffix of the type being passed to the IOCTL.}(hjٚhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj՚hMhj֚ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj՚hMhjEubeh}(h]h ]h"]h$]h&]uh1jhj)ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj)ubh)}(hJDon't use this macro directly, use the DRM_IOCTL_ASAHI_xxx values instead.h]hLDon’t use this macro directly, use the DRM_IOCTL_ASAHI_xxx values instead.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj)ubh)}(h **Return**h]j)}(hj"h]hReturn}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj)ubh)}(h7An IOCTL number to be passed to ioctl() from userspace.h]h7An IOCTL number to be passed to ioctl() from userspace.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:36: ./include/uapi/drm/asahi_drm.hhMhj)ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjShhhNhNubeh}(h]jAah ]h"]drm/asahi uapiah$]h&]uh1hhhhhhhhK"ubeh}(h]jah ]h"]drm driver uapiah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceȟ _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}engine discovery uapi]j!asrefids}(j]j|ajm ]jc aj ]j aj$]jv$aj!]j9aj3M]j)Majg]jgaj3i]j)iajj]jjajdj]jZjajH]j>aj]jaj]j ajmO]jcOajS]jSaunameids}(jYjjfjbjWjjjj jm j j j$j$j9j!jIMj3MjgjAjgj`j*jjgjgjIij3ij'jjjjzjjdjjSjj^jHjjj,jjOjmOjOjjOjjSjjRjAjTjSu nametypes}(jYjfjWjj j j$j9jIMjgjgj*jgjIij'jjzjjSj^jj,jOjOjOjSjRjTuh}(jhjbhjjijjjYjbjjjj jm jn j j j j j] jb jdjijjj3j8jXj]jrjwjj"jj j j j!j!j$j$jN%jS%j&j&j(j(j+j+j.j.j3j3j6j6j!j9j:j:j#=j(=j>j>jBjCjDjDjSEjXEjIjIjKjKj3Mj4MjyMj~MjPjPjSjSj^UjcUjAjWj`j,WjmXjrXjZj"Zj[j[j_j_jbjbjdjdjjgjgjgj3ij4ij[ij`ijijijjjjjdjjejjjjjj=ljBljmjmjBojGojpjpjrjrjsjsjyjyj$|j)|j~j~jӁj؁jjj{jjjj·jӇjjjjjQjVj-j2jjjjjJjOjojtjޖjjYj^jՙjڙj{jjjğjjjjj3j8jjjjjpjujjƬjKjPjjjjjjjjj˴jдjjjj-jHjIjjjjjjjBjGjjjjj{jjjjjjjjjj`jejjjBjGjjjjjjjQjVjxj}jpjujNjSjijnj jjj j\jaj jjj j j j3 j8 j@jEjjjjjjjjj?jDj'!j,!j"j"j%j%j(j (j)j*jH/jM/jx1j}1j3j 3j4j4j5j5j7j7j:j:jEjEjIjIjIMjNMjmOjnOjjOjjOjjOjPjPjQjQjAjSjSjSjSUjXUjXjXj]j]j^j^jf`jk`jbjbjcjcjdjejfjfjdhjihjijjjEljJljhnjmnj~ojojZpj_pjrjrjXuj]uj%wj*wjIyjNyjzjzj{j{j}j!}j}j}jojtjnjsjXj]jCjHjjj4j9jjjmjrjjjujzjjhhjjj;j2jZjQjjjjjjjjj jj;j2u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}jK sRparse_messages]transform_messages](hsystem_message)}(hhh]h)}(hhh]hRHyperlink target "uevents-generated-by-i915-on-its-device-node" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypeINFOlineKsourcehuh1jubj)}(hhh]h)}(hhh]hlHyperlink target "perf-events-exposed-by-i915-through-sys-bus-event-sources-drivers-i915" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypejlineKsourcehuh1jubj)}(hhh]h)}(hhh]h9Hyperlink target "virtual-engine-uapi" is not referenced.}hj.sbah}(h]h ]h"]h$]h&]uh1hhj+ubah}(h]h ]h"]h$]h&]levelKtypejlineMsourcehuh1jubj)}(hhh]h)}(hhh]h=Hyperlink target "context-engine-map-uapi" is not referenced.}hjHsbah}(h]h ]h"]h$]h&]uh1hhjEubah}(h]h ]h"]h$]h&]levelKtypejlineMsourcehuh1jubj)}(hhh]h)}(hhh]h