sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget#/translations/zh_CN/gpu/driver-uapimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/zh_TW/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/it_IT/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ja_JP/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ko_KR/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/sp_SP/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hDRM Driver uAPIh]hDRM Driver uAPI}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh=/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi.rsthKubh)}(hhh](h)}(h drm/i915 uAPIh]h drm/i915 uAPI}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubhtarget)}(h1.. _uevents generated by i915 on its device node:h]h}(h]h ]h"]h$]h&]refid,uevents-generated-by-i915-on-its-device-nodeuh1hhKhhhhhNubh paragraph)}(h0**uevents generated by i915 on its device node**h]hstrong)}(hhh]h,uevents generated by i915 on its device node}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]hah ]h"],uevents generated by i915 on its device nodeah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhexpect_referenced_by_name}hhsexpect_referenced_by_id}hhsubhdefinition_list)}(hhh](hdefinition_list_item)}(hXI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch event from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1. h](hterm)}(hLI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatchh]hLI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK.hhubh definition)}(hhh]h)}(hXQevent from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1.h]hXQevent from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK*hjubah}(h]h ]h"]h$]h&]uh1jhhubeh}(h]h ]h"]h$]h&]uh1hhjhK.hhubh)}(hXI915_ERROR_UEVENT - Generated upon error detection, currently only via hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen. h](j)}(hFI915_ERROR_UEVENT - Generated upon error detection, currently only viah]hFI915_ERROR_UEVENT - Generated upon error detection, currently only via}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK5hj3ubj)}(hhh]h)}(hX?hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen.h]hX?hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK1hjFubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1hhjEhK5hhubh)}(hI915_RESET_UEVENT - Event is generated just before an attempt to reset the GPU. The value supplied with the event is always 1. NOTE: Disable reset via module parameter will cause this event to not be seen. h](j)}(hJI915_RESET_UEVENT - Event is generated just before an attempt to reset theh]hJI915_RESET_UEVENT - Event is generated just before an attempt to reset the}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhK>ubh desc_name)}(hi915_user_extensionh]h desc_sig_name)}(hjh]hi915_user_extension}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhK>ubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jsphinx_line_type declaratorhjhhhjhK>ubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhK>hjhhubh desc_content)}(hhh]h)}(h-Base class for defining a chain of extensionsh]h-Base class for defining a chain of extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKBhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhK>ubeh}(h]h ](cstructeh"]h$]h&]domainj1objtypej2desctypej2noindex noindexentrynocontentsentryuh1jhhhhhNhNubh container)}(hX**Definition**:: struct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; }; **Members** ``next_extension`` Pointer to the next struct i915_user_extension, or zero if the end. ``name`` Name of the extension. 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Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension. ``flags`` MBZ All undefined bits must be zero. ``rsvd`` MBZ Reserved for future use; must be zero.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBubh:}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKFhj>ubh literal_block)}(hmstruct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; };h]hmstruct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; };}hjasbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKHhj>ubh)}(h **Members**h]h)}(hjrh]hMembers}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKOhj>ubh)}(hhh](h)}(hW``next_extension`` Pointer to the next struct i915_user_extension, or zero if the end. h](j)}(h``next_extension``h]hliteral)}(hjh]hnext_extension}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKihjubj)}(hhh]h)}(hCPointer to the next struct i915_user_extension, or zero if the end.h]hCPointer to the next struct i915_user_extension, or zero if the end.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKihjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKihjubh)}(hX``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension. h](j)}(h``name``h]j)}(hjh]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKuhjubj)}(hhh](h)}(hName of the extension.h]hName of the extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKohjubh)}(h-Note that the name here is just some integer.h]h-Note that the name here is just some integer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKqhjubh)}(hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension.h]hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKshjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKuhjubh)}(h0``flags`` MBZ All undefined bits must be zero. h](j)}(h ``flags``h]j)}(hj$h]hflags}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK{hjubj)}(hhh](h)}(hMBZh]hMBZ}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKyhj:ubh)}(h All undefined bits must be zero.h]h All undefined bits must be zero.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hK{hj:ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj9hK{hjubh)}(h4``rsvd`` MBZ Reserved for future use; must be zero.h](j)}(h``rsvd``h]j)}(hjlh]hrsvd}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjfubj)}(hhh](h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubh)}(h&Reserved for future use; must be zero.h]h&Reserved for future use; must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hX5Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan's approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.h]hX7Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan’s approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKChhhhubh)}(hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. 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The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKIhhhhubh)}(hExample chaining:h]hExample chaining:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKOhhhhubj`)}(hX)struct i915_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct i915_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct i915_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };h]hX)struct i915_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct i915_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct i915_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };}hjsbah}(h]h ]h"]h$]h&]jjforcelanguageChighlight_args}uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKQhhhhubh)}(hTypically the struct i915_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.h]hTypically the struct i915_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK`hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_engine_class (C enum)c.drm_i915_gem_engine_classhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_engine_classh]j)}(henum drm_i915_gem_engine_classh](j)}(henumh]henum}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKgubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9hhhjKhKgubj)}(hdrm_i915_gem_engine_classh]j)}(hj7h]hdrm_i915_gem_engine_class}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubah}(h]h ](jjeh"]h$]h&]jjuh1jhj9hhhjKhKgubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj5hhhjKhKgubah}(h]j0ah ](j j eh"]h$]h&]jj)jhuh1jhjKhKghj2hhubj)}(hhh]h)}(huapi engine type enumerationh]huapi engine type enumeration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj}hhubah}(h]h ]h"]h$]h&]uh1jhj2hhhjKhKgubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhhhNhNubj=)}(hXN**Constants** ``I915_ENGINE_CLASS_RENDER`` Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs). ``I915_ENGINE_CLASS_COPY`` Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data. ``I915_ENGINE_CLASS_VIDEO`` Video engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode. ``I915_ENGINE_CLASS_VIDEO_ENHANCE`` Video enhancement engines (also referred to as "vebox") support instructions related to image enhancement. ``I915_ENGINE_CLASS_COMPUTE`` Compute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline. ``I915_ENGINE_CLASS_INVALID`` Placeholder value to represent an invalid engine class assignment.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubh)}(hhh](h)}(hXK``I915_ENGINE_CLASS_RENDER`` Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs). h](j)}(h``I915_ENGINE_CLASS_RENDER``h]j)}(hjh]hI915_ENGINE_CLASS_RENDER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hX-Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs).h]hX7Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called “kernels” or “shaders”) on the GPU’s execution units (EUs).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(hXL``I915_ENGINE_CLASS_COPY`` Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data. h](j)}(h``I915_ENGINE_CLASS_COPY``h]j)}(hjh]hI915_ENGINE_CLASS_COPY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hX0Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data.h]hX4Copy engines (also referred to as “blitters”) support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``I915_ENGINE_CLASS_VIDEO`` Video engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode. h](j)}(h``I915_ENGINE_CLASS_VIDEO``h]j)}(hj5h]hI915_ENGINE_CLASS_VIDEO}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj/ubj)}(hhh]h)}(hVideo engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode.h]hVideo engines (also referred to as “bit stream decode” (BSD) or “vdbox”) support instructions that perform fixed-function media decode and encode.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjKubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1hhjJhKhjubh)}(h``I915_ENGINE_CLASS_VIDEO_ENHANCE`` Video enhancement engines (also referred to as "vebox") support instructions related to image enhancement. h](j)}(h#``I915_ENGINE_CLASS_VIDEO_ENHANCE``h]j)}(hjoh]hI915_ENGINE_CLASS_VIDEO_ENHANCE}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjiubj)}(hhh]h)}(hjVideo enhancement engines (also referred to as "vebox") support instructions related to image enhancement.h]hnVideo enhancement engines (also referred to as “vebox”) support instructions related to image enhancement.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``I915_ENGINE_CLASS_COMPUTE`` Compute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline. h](j)}(h``I915_ENGINE_CLASS_COMPUTE``h]j)}(hjh]hI915_ENGINE_CLASS_COMPUTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hCompute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline.h]hCompute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h```I915_ENGINE_CLASS_INVALID`` Placeholder value to represent an invalid engine class assignment.h](j)}(h``I915_ENGINE_CLASS_INVALID``h]j)}(hjh]hI915_ENGINE_CLASS_INVALID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hBPlaceholder value to represent an invalid engine class assignment.h]hBPlaceholder value to represent an invalid engine class assignment.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj&h]h Description}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hX-Different engines serve different roles, and there may be more than one engine serving each role. This enum provides a classification of the role of the engine, which may be used when requesting operations to be performed on a certain subset of engines, or for providing information about that group.h]hX-Different engines serve different roles, and there may be more than one engine serving each role. This enum provides a classification of the role of the engine, which may be used when requesting operations to be performed on a certain subset of engines, or for providing information about that group.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%i915_engine_class_instance (C struct)c.i915_engine_class_instancehNtauh1jhhhhhNhNubj)}(hhh](j)}(hi915_engine_class_instanceh]j)}(h!struct i915_engine_class_instanceh](j)}(hjh]hstruct}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKubj)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`hhhjqhKubj)}(hi915_engine_class_instanceh]j)}(hj^h]hi915_engine_class_instance}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj`hhhjqhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj\hhhjqhKubah}(h]jWah ](j j eh"]h$]h&]jj)jhuh1jhjqhKhjYhhubj)}(hhh]h)}(h Engine class/instance identifierh]h Engine class/instance identifier}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjYhhhjqhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhhhNhNubj=)}(hXJ**Definition**:: struct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; }; **Members** ``engine_class`` Engine class from enum drm_i915_gem_engine_class ``engine_instance`` Engine instance.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj`)}(hstruct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; };h]hstruct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubh)}(hhh](h)}(hB``engine_class`` Engine class from enum drm_i915_gem_engine_class h](j)}(h``engine_class``h]j)}(hjh]h engine_class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj ubj)}(hhh]h)}(h0Engine class from enum drm_i915_gem_engine_classh]h0Engine class from enum drm_i915_gem_engine_class}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hKhj)ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj(hKhj ubh)}(h$``engine_instance`` Engine instance.h](j)}(h``engine_instance``h]j)}(hjLh]hengine_instance}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjFubj)}(hhh]h)}(hEngine instance.h]hEngine instance.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjbubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1hhjahKhj ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hX@There may be more than one engine fulfilling any role within the system. Each engine of a class is given a unique instance number and therefore any engine can be specified by its class:instance tuplet. APIs that allow access to any engine in the system will use struct i915_engine_class_instance for this identification.h]hX@There may be more than one engine fulfilling any role within the system. Each engine of a class is given a unique instance number and therefore any engine can be specified by its class:instance tuplet. APIs that allow access to any engine in the system will use struct i915_engine_class_instance for this identification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hL.. _perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915:h]h}(h]h ]h"]h$]h&]hԌFperf-events-exposed-by-i915-through-sys-bus-event-sources-drivers-i915uh1hhKhhhhhNubh)}(hK**perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915**h]h)}(hjh]hGperf_events exposed by i915 through /sys/bus/event_sources/drivers/i915}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]jah ]h"]Gperf_events exposed by i915 through /sys/bus/event_sources/drivers/i915ah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhh}jjsh}jjsubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_getparam (C struct)c.drm_i915_getparamhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_getparamh]j)}(hstruct drm_i915_getparamh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_i915_getparamh]j)}(hjh]hdrm_i915_getparam}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h!Driver parameter query structure.h]h!Driver parameter query structure.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2hj2hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jMj8jMj9j:j;uh1jhhhhhNhNubj=)}(hXN**Definition**:: struct drm_i915_getparam { __s32 param; int __user *value; }; **Members** ``param`` Driver parameter to query. ``value`` Address of memory where queried value should be put. WARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUubh:}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM6hjQubj`)}(hEstruct drm_i915_getparam { __s32 param; int __user *value; };h]hEstruct drm_i915_getparam { __s32 param; int __user *value; };}hjrsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM8hjQubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM=hjQubh)}(hhh](h)}(h%``param`` Driver parameter to query. h](j)}(h ``param``h]j)}(hjh]hparam}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5hjubj)}(hhh]h)}(hDriver parameter to query.h]hDriver parameter to query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM5hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM5hjubh)}(h``value`` Address of memory where queried value should be put. WARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h](j)}(h ``value``h]j)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM<hjubj)}(hhh](h)}(h4Address of memory where queried value should be put.h]h4Address of memory where queried value should be put.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM:hjubh)}(hrWARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h]htWARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don’t repeat this mistake.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM<hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM<hjubeh}(h]h ]h"]h$]h&]uh1hhjQubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_getparam_t (C type)c.drm_i915_getparam_thNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_getparam_th]j)}(htype drm_i915_getparam_th](j)}(htypeh]htype}(hjC hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj? hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMCubj)}(h h]h }(hjR hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj? hhhjQ hMCubj)}(hdrm_i915_getparam_th]j)}(hj= h]hdrm_i915_getparam_t}(hjd hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj` ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj? hhhjQ hMCubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj; hhhjQ hMCubah}(h]j6 ah ](j j eh"]h$]h&]jj)jhuh1jhjQ hMChj8 hhubj)}(hhh]h)}(h?Driver parameter query structure. See struct drm_i915_getparam.h]h?Driver parameter query structure. See struct drm_i915_getparam.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMBhj hhubah}(h]h ]h"]h$]h&]uh1jhj8 hhhjQ hMCubeh}(h]h ](j1typeeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_i915_gem_mmap_offset (C struct)c.drm_i915_gem_mmap_offsethNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_mmap_offseth]j)}(hstruct drm_i915_gem_mmap_offseth](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMGubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMGubj)}(hdrm_i915_gem_mmap_offseth]j)}(hj h]hdrm_i915_gem_mmap_offset}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMGubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hMGubah}(h]j ah ](j j eh"]h$]h&]jj)jhuh1jhj hMGhj hhubj)}(hhh]h)}(h5Retrieve an offset so we can mmap this buffer object.h]h5Retrieve an offset so we can mmap this buffer object.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMGubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhhhNhNubj=)}(hXh**Definition**:: struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; }; **Members** ``handle`` Handle for the object being mapped. ``pad`` Must be zero ``offset`` The fake offset to use for subsequent mmap call This is a fixed-size type for 32/64 compatibility. ``flags`` Flags for extended behaviour. It is mandatory that one of the `MMAP_OFFSET` types should be included: - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid. As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise. ``extensions`` Zero-terminated chain of extensions. No current extensions defined; mbz.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubj`)}(hX-struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; };h]hX-struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; };}hj: sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubh)}(h **Members**h]h)}(hjK h]hMembers}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubh)}(hhh](h)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]j)}(hjj h]hhandle}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjh ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjd ubj)}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjd ubeh}(h]h ]h"]h$]h&]uh1hhj hMhja ubh)}(h``pad`` Must be zero h](j)}(h``pad``h]j)}(hj h]hpad}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj ubj)}(hhh]h)}(h Must be zeroh]h Must be zero}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hKhja ubh)}(ho``offset`` The fake offset to use for subsequent mmap call This is a fixed-size type for 32/64 compatibility. h](j)}(h ``offset``h]j)}(hj h]hoffset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubj)}(hhh](h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubh)}(h2This is a fixed-size type for 32/64 compatibility.h]h2This is a fixed-size type for 32/64 compatibility.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhja ubh)}(hX``flags`` Flags for extended behaviour. It is mandatory that one of the `MMAP_OFFSET` types should be included: - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid. As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise. h](j)}(h ``flags``h]j)}(hj$ h]hflags}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj" ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubj)}(hhh](h)}(hFlags for extended behaviour.h]hFlags for extended behaviour.}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj: ubh)}(hGIt is mandatory that one of the `MMAP_OFFSET` types should be included:h](h It is mandatory that one of the }(hjL hhhNhNubhtitle_reference)}(h `MMAP_OFFSET`h]h MMAP_OFFSET}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjL ubh types should be included:}(hjL hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj: ubh bullet_list)}(hhh](h list_item)}(hO`I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)h]h)}(hjx h](jU )}(h`I915_MMAP_OFFSET_GTT`h]hI915_MMAP_OFFSET_GTT}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjz ubh9: Use mmap with the object bound to GTT. (Write-Combined)}(hjz hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjv ubah}(h]h ]h"]h$]h&]uh1jt hjq ubju )}(h2`I915_MMAP_OFFSET_WC`: Use Write-Combined caching.h]h)}(hj h](jU )}(h`I915_MMAP_OFFSET_WC`h]hI915_MMAP_OFFSET_WC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj ubh: Use Write-Combined caching.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubah}(h]h ]h"]h$]h&]uh1jt hjq ubju )}(h.`I915_MMAP_OFFSET_WB`: Use Write-Back caching.h]h)}(hj h](jU )}(h`I915_MMAP_OFFSET_WB`h]hI915_MMAP_OFFSET_WB}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj ubh: Use Write-Back caching.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubah}(h]h ]h"]h$]h&]uh1jt hjq ubju )}(hE`I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. h]h)}(hD`I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.h](jU )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj ubh,: Use object placement to determine caching.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubah}(h]h ]h"]h$]h&]uh1jt hjq ubeh}(h]h ]h"]h$]h&]bullet-uh1jo hj hMhj: ubh)}(hOn devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid.h](hOn devices with local memory }(hj hhhNhNubjU )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj ubhW is the only valid type. On devices without local memory, this caching mode is invalid.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj: ubh)}(hAs caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise.h](h As caching mode when specifying }(hj8 hhhNhNubjU )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj8 ubh, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise.}(hj8 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj: ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj9 hMhja ubh)}(hX``extensions`` Zero-terminated chain of extensions. No current extensions defined; mbz.h](j)}(h``extensions``h]j)}(hjk h]h extensions}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhje ubj)}(hhh](h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubh)}(h#No current extensions defined; mbz.h]h#No current extensions defined; mbz.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubeh}(h]h ]h"]h$]h&]uh1jhje ubeh}(h]h ]h"]h$]h&]uh1hhj hMhja ubeh}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM"hhhhubh)}(hThis struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, and is used to retrieve the fake offset to mmap an object specified by :c:type:`handle`.h](h)This struct is passed as argument to the }(hj hhhNhNubjU )}(h `DRM_IOCTL_I915_GEM_MMAP_OFFSET`h]hDRM_IOCTL_I915_GEM_MMAP_OFFSET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj ubhO ioctl, and is used to retrieve the fake offset to mmap an object specified by }(hj hhhNhNubh)}(h:c:type:`handle`h]j)}(hj h]hhandle}(hj hhhNhNubah}(h]h ](xrefj1c-typeeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocgpu/driver-uapi refdomainj1reftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sb reftargethandleuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj hMhhhhubh)}(hThe legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave as setting the :c:type:`extensions` to 0, and :c:type:`flags` to `I915_MMAP_OFFSET_GTT`.h](hThe legacy way of using }(hj" hhhNhNubjU )}(h`DRM_IOCTL_I915_GEM_MMAP`h]hDRM_IOCTL_I915_GEM_MMAP}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj" ubh is removed on gen12+. }(hj" hhhNhNubjU )}(h`DRM_IOCTL_I915_GEM_MMAP_GTT`h]hDRM_IOCTL_I915_GEM_MMAP_GTT}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj" ubhL is an older supported alias to this struct, but will behave as setting the }(hj" hhhNhNubh)}(h:c:type:`extensions`h]j)}(hjP h]h extensions}(hjR hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjN ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j extensionsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj" ubh to 0, and }(hj" hhhNhNubh)}(h:c:type:`flags`h]j)}(hjt h]hflags}(hjv hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjr ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j flagsuh1hhjm hMhj" ubh to }(hj" hhhNhNubjU )}(h`I915_MMAP_OFFSET_GTT`h]hI915_MMAP_OFFSET_GTT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj" ubh.}(hj" hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjm hMhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_set_domain (C struct)c.drm_i915_gem_set_domainhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_set_domainh]j)}(hstruct drm_i915_gem_set_domainh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMubj)}(hdrm_i915_gem_set_domainh]j)}(hj h]hdrm_i915_gem_set_domain}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hMubah}(h]j ah ](j j eh"]h$]h&]jj)jhuh1jhj hMhj hhubj)}(hhh]h)}(hdAdjust the objects write or read domain, in preparation for accessing the pages via some CPU domain.h]hdAdjust the objects write or read domain, in preparation for accessing the pages via some CPU domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM$hjhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhhhNhNubj=)}(hXo**Definition**:: struct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; }; **Members** ``handle`` Handle for the object. ``read_domains`` New read domains. ``write_domain`` New write domain. Note that having something in the write domain implies it's in the read domain, and only that read domain.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh:}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM(hj$ubj`)}(hestruct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; };h]hestruct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; };}hjEsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM*hj$ubh)}(h **Members**h]h)}(hjVh]hMembers}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM0hj$ubh)}(hhh](h)}(h"``handle`` Handle for the object. h](j)}(h ``handle``h]j)}(hjuh]hhandle}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMJhjoubj)}(hhh]h)}(hHandle for the object.h]hHandle for the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMJhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1hhjhMJhjlubh)}(h#``read_domains`` New read domains. h](j)}(h``read_domains``h]j)}(hjh]h read_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hNew read domains.h]hNew read domains.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjlubh)}(h``write_domain`` New write domain. Note that having something in the write domain implies it's in the read domain, and only that read domain.h](j)}(h``write_domain``h]j)}(hjh]h write_domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMThjubj)}(hhh](h)}(hNew write domain.h]hNew write domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMRhjubh)}(hjNote that having something in the write domain implies it's in the read domain, and only that read domain.h]hlNote that having something in the write domain implies it’s in the read domain, and only that read domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMThjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMThjlubeh}(h]h ]h"]h$]h&]uh1hhj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj8h]h Description}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMXhhhhubh)}(hSpecifying a new write or read domain will flush the object out of the previous domain(if required), before then updating the objects domain tracking with the new domain.h]hSpecifying a new write or read domain will flush the object out of the previous domain(if required), before then updating the objects domain tracking with the new domain.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM%hhhhubh)}(hVNote this might involve waiting for the object first if it is still active on the GPU.h]hVNote this might involve waiting for the object first if it is still active on the GPU.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM)hhhhubh)}(h;Supported values for **read_domains** and **write_domain**:h](hSupported values for }(hjlhhhNhNubh)}(h**read_domains**h]h read_domains}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlubh and }(hjlhhhNhNubh)}(h**write_domain**h]h write_domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlubh:}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM,hhhhubh block_quote)}(h- I915_GEM_DOMAIN_WC: Uncached write-combined domain - I915_GEM_DOMAIN_CPU: CPU cache domain - I915_GEM_DOMAIN_GTT: Mappable aperture domain h]jp )}(hhh](ju )}(h2I915_GEM_DOMAIN_WC: Uncached write-combined domainh]h)}(hjh]h2I915_GEM_DOMAIN_WC: Uncached write-combined domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM.hjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h%I915_GEM_DOMAIN_CPU: CPU cache domainh]h)}(hjh]h%I915_GEM_DOMAIN_CPU: CPU cache domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM/hjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h.I915_GEM_DOMAIN_GTT: Mappable aperture domain h]h)}(h-I915_GEM_DOMAIN_GTT: Mappable aperture domainh]h-I915_GEM_DOMAIN_GTT: Mappable aperture domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM0hjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hjhM.hjubah}(h]h ]h"]h$]h&]uh1jhjhM.hhhhubh)}(hAll other domains are rejected.h]hAll other domains are rejected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2hhhhubh)}(hXINote that for discrete, starting from DG1, this is no longer supported, and is instead rejected. On such platforms the CPU domain is effectively static, where we also only support a single :c:type:`drm_i915_gem_mmap_offset` cache mode, which can't be set explicitly and instead depends on the object placements, as per the below.h](hNote that for discrete, starting from DG1, this is no longer supported, and is instead rejected. On such platforms the CPU domain is effectively static, where we also only support a single }(hj hhhNhNubh)}(h":c:type:`drm_i915_gem_mmap_offset`h]j)}(hjh]hdrm_i915_gem_mmap_offset}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_gem_mmap_offsetuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM4hj ubhl cache mode, which can’t be set explicitly and instead depends on the object placements, as per the below.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj3hM4hhhhubh)}(h*Implicit caching rules, starting from DG1:h]h*Implicit caching rules, starting from DG1:}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM:hhhhubj)}(hXH- If any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. - Everything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]jp )}(hhh](ju )}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. h]h)}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.h](h%If any of the object placements (see }(hjXhhhNhNubh)}(h0:c:type:`drm_i915_gem_create_ext_memory_regions`h]j)}(hjbh]h&drm_i915_gem_create_ext_memory_regions}(hjdhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j &drm_i915_gem_create_ext_memory_regionsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM<hjXubhg) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM<hjTubah}(h]h ]h"]h$]h&]uh1jt hjQubju )}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]h)}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.h]hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM@hjubah}(h]h ]h"]h$]h&]uh1jt hjQubeh}(h]h ]h"]h$]h&]j j uh1jo hjhM<hjMubah}(h]h ]h"]h$]h&]uh1jhjhM<hhhhubh)}(hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new :c:type:`drm_i915_gem_create_ext` extension is probable.h](hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new }(hjhhhNhNubh)}(h!:c:type:`drm_i915_gem_create_ext`h]j)}(hjh]hdrm_i915_gem_create_ext}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_gem_create_extuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMChjubh extension is probable.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMChhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_exec_fence (C struct)c.drm_i915_gem_exec_fencehNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_exec_fenceh]j)}(hstruct drm_i915_gem_exec_fenceh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMJubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj hMJubj)}(hdrm_i915_gem_exec_fenceh]j)}(hjh]hdrm_i915_gem_exec_fence}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj hMJubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj hMJubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj hMJhjhhubj)}(hhh]h)}(h/An input or output fence for the execbuf ioctl.h]h/An input or output fence for the execbuf ioctl.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM'hj?hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hMJubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jZj8jZj9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); }; **Members** ``handle`` User's handle for a drm_syncobj to wait on or signal. ``flags`` Supported flags are: I915_EXEC_FENCE_WAIT: Wait for the input fence before request submission. I915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbubh:}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM+hj^ubj`)}(hstruct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); };h]hstruct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM-hj^ubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5hj^ubh)}(hhh](h)}(hA``handle`` User's handle for a drm_syncobj to wait on or signal. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM0hjubj)}(hhh]h)}(h5User's handle for a drm_syncobj to wait on or signal.h]h7User’s handle for a drm_syncobj to wait on or signal.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM0hjubh)}(h``flags`` Supported flags are: I915_EXEC_FENCE_WAIT: Wait for the input fence before request submission. I915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM:hjubj)}(hhh](h)}(hSupported flags are:h]hSupported flags are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5hjubh)}(hII915_EXEC_FENCE_WAIT: Wait for the input fence before request submission.h]hII915_EXEC_FENCE_WAIT: Wait for the input fence before request submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7hjubh)}(hAI915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh]hAI915_EXEC_FENCE_SIGNAL: Return request completion fence as output}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM:hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM:hjubeh}(h]h ]h"]h$]h&]uh1hhj^ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjHh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM>hhhhubh)}(hBThe request will wait for input fence to signal before submission.h]hBThe request will wait for input fence to signal before submission.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM(hhhhubh)}(hOThe returned output fence will be signaled after the completion of the request.h]hOThe returned output fence will be signaled after the completion of the request.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM*hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j6drm_i915_gem_execbuffer_ext_timeline_fences (C struct)-c.drm_i915_gem_execbuffer_ext_timeline_fenceshNtauh1jhhhhhNhNubj)}(hhh](j)}(h+drm_i915_gem_execbuffer_ext_timeline_fencesh]j)}(h2struct drm_i915_gem_execbuffer_ext_timeline_fencesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM0ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM0ubj)}(h+drm_i915_gem_execbuffer_ext_timeline_fencesh]j)}(hjh]h+drm_i915_gem_execbuffer_ext_timeline_fences}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM0ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM0ubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhM0hjhhubj)}(hhh]h)}(h"Timeline fences for execbuf ioctl.h]h"Timeline fences for execbuf ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMChjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM0ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``fence_count`` Number of elements in the **handles_ptr** & **value_ptr** arrays. ``handles_ptr`` Pointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**. ``values_ptr`` Pointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMGhjubj`)}(hstruct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; };h]hstruct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMIhjubh)}(h **Members**h]h)}(hj%h]hMembers}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMQhjubh)}(hhh](h)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]j)}(hjDh]hbase}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMKhj>ubj)}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMKhjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1hhjYhMKhj;ubh)}(hR``fence_count`` Number of elements in the **handles_ptr** & **value_ptr** arrays. h](j)}(h``fence_count``h]j)}(hj}h]h fence_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMRhjwubj)}(hhh]h)}(hANumber of elements in the **handles_ptr** & **value_ptr** arrays.h](hNumber of elements in the }(hjhhhNhNubh)}(h**handles_ptr**h]h handles_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh & }(hjhhhNhNubh)}(h **value_ptr**h]h value_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh arrays.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMQhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1hhjhMRhj;ubh)}(ha``handles_ptr`` Pointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**. h](j)}(h``handles_ptr``h]j)}(hjh]h handles_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMXhjubj)}(hhh]h)}(hPPointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**.h](h@Pointer to an array of struct drm_i915_gem_exec_fence of length }(hjhhhNhNubh)}(h**fence_count**h]h fence_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMXhj;ubh)}(h``values_ptr`` Pointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](j)}(h``values_ptr``h]j)}(hj'h]h values_ptr}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM`hj!ubj)}(hhh]h)}(hPointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](h,Pointer to an array of u64 values of length }(hj@hhhNhNubh)}(h**fence_count**h]h fence_count}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubh. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM]hj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhj<hM`hj;ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj|h]h Description}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMdhhhhubh)}(hThis structure describes an array of drm_syncobj and associated points for timeline variants of drm_syncobj. It is invalid to append this structure to the execbuf if I915_EXEC_FENCE_ARRAY is set.h]hThis structure describes an array of drm_syncobj and associated points for timeline variants of drm_syncobj. It is invalid to append this structure to the execbuf if I915_EXEC_FENCE_ARRAY is set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMDhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_i915_gem_execbuffer2 (C struct)c.drm_i915_gem_execbuffer2hNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_execbuffer2h]j)}(hstruct drm_i915_gem_execbuffer2h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMKubj)}(hdrm_i915_gem_execbuffer2h]j)}(hjh]hdrm_i915_gem_execbuffer2}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMKhjhhubj)}(hhh]h)}(h-Structure for DRM_I915_GEM_EXECBUFFER2 ioctl.h]h-Structure for DRM_I915_GEM_EXECBUFFER2 ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMfhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhhhNhNubj=)}(hX **Definition**:: struct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; }; **Members** ``buffers_ptr`` Pointer to a list of gem_exec_object2 structs ``buffer_count`` Number of elements in **buffers_ptr** array ``batch_start_offset`` Offset in the batchbuffer to start execution from. ``batch_len`` Length in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size. ``DR1`` deprecated ``DR4`` deprecated ``num_cliprects`` See **cliprects_ptr** ``cliprects_ptr`` Kernel clipping was a DRI1 misfeature. It is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set. If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array. If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0. ``flags`` Execbuf flags ``rsvd1`` Context id ``rsvd2`` in and out sync_file file descriptors. When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input). When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMjhjubj`)}(hXstruct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; };h]hXstruct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; };}hj9sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMlhjubh)}(h **Members**h]h)}(hjJh]hMembers}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hhh](h)}(h>``buffers_ptr`` Pointer to a list of gem_exec_object2 structs h](j)}(h``buffers_ptr``h]j)}(hjih]h buffers_ptr}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMjhjcubj)}(hhh]h)}(h-Pointer to a list of gem_exec_object2 structsh]h-Pointer to a list of gem_exec_object2 structs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hMjhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1hhj~hMjhj`ubh)}(h=``buffer_count`` Number of elements in **buffers_ptr** array h](j)}(h``buffer_count``h]j)}(hjh]h buffer_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(h+Number of elements in **buffers_ptr** arrayh](hNumber of elements in }(hjhhhNhNubh)}(h**buffers_ptr**h]h buffers_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh array}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj`ubh)}(hJ``batch_start_offset`` Offset in the batchbuffer to start execution from. h](j)}(h``batch_start_offset``h]j)}(hjh]hbatch_start_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMshjubj)}(hhh]h)}(h2Offset in the batchbuffer to start execution from.h]h2Offset in the batchbuffer to start execution from.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMrhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMshj`ubh)}(h``batch_len`` Length in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size. h](j)}(h ``batch_len``h]j)}(hj'h]h batch_len}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMzhj!ubj)}(hhh]h)}(hLength in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size.h](h7Length in bytes of the batch buffer, starting from the }(hj@hhhNhNubh)}(h**batch_start_offset**h]hbatch_start_offset}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubh=. If 0, length is assumed to be the batch buffer object size.}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMxhj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhj<hMzhj`ubh)}(h``DR1`` deprecated h](j)}(h``DR1``h]j)}(hjsh]hDR1}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjmubj)}(hhh]h)}(h deprecatedh]h deprecated}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1hhjhKhj`ubh)}(h``DR4`` deprecated h](j)}(h``DR4``h]j)}(hjh]hDR4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(h deprecatedh]h deprecated}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj`ubh)}(h(``num_cliprects`` See **cliprects_ptr** h](j)}(h``num_cliprects``h]j)}(hjh]h num_cliprects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hSee **cliprects_ptr**h](hSee }(hjhhhNhNubh)}(h**cliprects_ptr**h]h cliprects_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj`ubh)}(hX``cliprects_ptr`` Kernel clipping was a DRI1 misfeature. It is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set. If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array. If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0. h](j)}(h``cliprects_ptr``h]j)}(hj,h]h cliprects_ptr}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj&ubj)}(hhh](h)}(h&Kernel clipping was a DRI1 misfeature.h]h&Kernel clipping was a DRI1 misfeature.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjBubh)}(hgIt is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set.h]hgIt is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjBubh)}(hIf I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array.h](hGIf I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of }(hjchhhNhNubh)}(h!:c:type:`drm_i915_gem_exec_fence`h]j)}(hjmh]hdrm_i915_gem_exec_fence}(hjohhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_gem_exec_fenceuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjcubh and }(hjchhhNhNubh)}(h**num_cliprects**h]h num_cliprects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjcubh is the length of the array.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjBubh)}(h|If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0.h](hGIf I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single }(hjhhhNhNubh)}(h:c:type:`i915_user_extension`h]j)}(hjh]hi915_user_extension}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j i915_user_extensionuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh and num_cliprects is 0.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjBubeh}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1hhjAhMhj`ubh)}(h``flags`` Execbuf flags h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(h Execbuf flagsh]h Execbuf flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj`ubh)}(h``rsvd1`` Context id h](j)}(h ``rsvd1``h]j)}(hj$h]hrsvd1}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(h Context idh]h Context id}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hKhj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj9hKhj`ubh)}(hX'``rsvd2`` in and out sync_file file descriptors. When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input). When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h](j)}(h ``rsvd2``h]j)}(hj]h]hrsvd2}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjWubj)}(hhh](h)}(h&in and out sync_file file descriptors.h]h&in and out sync_file file descriptors.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjsubh)}(hWhen I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input).h]hWhen I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjsubh)}(hnWhen I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h]hnWhen I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjsubeh}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1hhjrhMhj`ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_gem_caching (C struct)c.drm_i915_gem_cachinghNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_cachingh]j)}(hstruct drm_i915_gem_cachingh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM!ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM!ubj)}(hdrm_i915_gem_cachingh]j)}(hjh]hdrm_i915_gem_caching}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM!ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM!ubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhM!hjhhubj)}(hhh]h)}(h/Set or get the caching for given object handle.h]h/Set or get the caching for given object handle.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMlhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM!ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j.j8j.j9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; }; **Members** ``handle`` Handle of the buffer to set/get the caching level. ``caching`` The GTT caching level to apply or possible return value. The supported **caching** values: I915_CACHING_NONE: GPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent. I915_CACHING_CACHED: GPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT. I915_CACHING_DISPLAY: Special GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6ubh:}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMphj2ubj`)}(hstruct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; };h]hstruct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; };}hjSsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMrhj2ubh)}(h **Members**h]h)}(hjdh]hMembers}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMzhj2ubh)}(hhh](h)}(h>``handle`` Handle of the buffer to set/get the caching level. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj}ubj)}(hhh]h)}(h2Handle of the buffer to set/get the caching level.h]h2Handle of the buffer to set/get the caching level.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1hhjhMhjzubh)}(hXm``caching`` The GTT caching level to apply or possible return value. The supported **caching** values: I915_CACHING_NONE: GPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent. I915_CACHING_CACHED: GPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT. I915_CACHING_DISPLAY: Special GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h](j)}(h ``caching``h]j)}(hjh]hcaching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh](h)}(h8The GTT caching level to apply or possible return value.h]h8The GTT caching level to apply or possible return value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h!The supported **caching** values:h](hThe supported }(hjhhhNhNubh)}(h **caching**h]hcaching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh values:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CACHING_NONE:h]hI915_CACHING_NONE:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hGPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent.h]hGPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CACHING_CACHED:h]hI915_CACHING_CACHED:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hGPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT.h]hGPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CACHING_DISPLAY:h]hI915_CACHING_DISPLAY:}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hXSpecial GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h]hXSpecial GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjzubeh}(h]h ]h"]h$]h&]uh1hhj2ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjzh]h Description}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hX?Allow userspace to control the GTT caching bits for a given object when the object is later mapped through the ppGTT(or GGTT on older platforms lacking ppGTT support, or if the object is used for scanout). Note that this might require unbinding the object from the GTT first, if its current caching value doesn't match.h]hXAAllow userspace to control the GTT caching bits for a given object when the object is later mapped through the ppGTT(or GGTT on older platforms lacking ppGTT support, or if the object is used for scanout). Note that this might require unbinding the object from the GTT first, if its current caching value doesn’t match.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMmhhhhubh)}(hXNote that this all changes on discrete platforms, starting from DG1, the set/get caching is no longer supported, and is now rejected. Instead the CPU caching attributes(WB vs WC) will become an immutable creation time property for the object, along with the GTT caching level. For now we don't expose any new uAPI for this, instead on DG1 this is all implicit, although this largely shouldn't matter since DG1 is coherent by default(without any way of controlling it).h]hXNote that this all changes on discrete platforms, starting from DG1, the set/get caching is no longer supported, and is now rejected. Instead the CPU caching attributes(WB vs WC) will become an immutable creation time property for the object, along with the GTT caching level. For now we don’t expose any new uAPI for this, instead on DG1 this is all implicit, although this largely shouldn’t matter since DG1 is coherent by default(without any way of controlling it).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMshhhhubh)}(h*Implicit caching rules, starting from DG1:h]h*Implicit caching rules, starting from DG1:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM{hhhhubj)}(hXH- If any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. - Everything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]jp )}(hhh](ju )}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. h]h)}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.h](h%If any of the object placements (see }(hjhhhNhNubh)}(h0:c:type:`drm_i915_gem_create_ext_memory_regions`h]j)}(hjh]h&drm_i915_gem_create_ext_memory_regions}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j &drm_i915_gem_create_ext_memory_regionsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM}hjubhg) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM}hjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]h)}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.h]hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hjhM}hjubah}(h]h ]h"]h$]h&]uh1jhjhM}hhhhubh)}(hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new :c:type:`drm_i915_gem_create_ext` extension is probable.h](hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new }(hj%hhhNhNubh)}(h!:c:type:`drm_i915_gem_create_ext`h]j)}(hj/h]hdrm_i915_gem_create_ext}(hj1hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_gem_create_extuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj%ubh extension is probable.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjLhMhhhhubh)}(hXSide note: Part of the reason for this is that changing the at-allocation-time CPU caching attributes for the pages might be required(and is expensive) if we need to then CPU map the pages later with different caching attributes. This inconsistent caching behaviour, while supported on x86, is not universally supported on other architectures. So for simplicity we opt for setting everything at creation time, whilst also making it immutable, on discrete platforms.h]hXSide note: Part of the reason for this is that changing the at-allocation-time CPU caching attributes for the pages might be required(and is expensive) if we need to then CPU map the pages later with different caching attributes. This inconsistent caching behaviour, while supported on x86, is not universally supported on other architectures. So for simplicity we opt for setting everything at creation time, whilst also making it immutable, on discrete platforms.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*drm_i915_gem_context_create_ext (C struct)!c.drm_i915_gem_context_create_exthNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_context_create_exth]j)}(h&struct drm_i915_gem_context_create_exth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{hhhjhMubj)}(hdrm_i915_gem_context_create_exth]j)}(hjyh]hdrm_i915_gem_context_create_ext}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj{hhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjwhhhjhMubah}(h]jrah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjthhubj)}(hhh]h)}(h Structure for creating contexts.h]h Structure for creating contexts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjthhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; }; **Members** ``ctx_id`` Id of the created context (output) ``flags`` Supported flags are: I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS: Extensions may be appended to this structure and driver must check for those. See **extensions**. I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE Created context will have single timeline. ``extensions`` Zero-terminated chain of extensions. I915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam. I915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj`)}(hXstruct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; };h]hXstruct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hhh](h)}(h.``ctx_id`` Id of the created context (output) h](j)}(h ``ctx_id``h]j)}(hj.h]hctx_id}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj(ubj)}(hhh]h)}(h"Id of the created context (output)h]h"Id of the created context (output)}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1hhjChMhj%ubh)}(hX``flags`` Supported flags are: I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS: Extensions may be appended to this structure and driver must check for those. See **extensions**. I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE Created context will have single timeline. h](j)}(h ``flags``h]j)}(hjgh]hflags}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjaubj)}(hhh](h)}(hSupported flags are:h]hSupported flags are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(h)I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS:h]h)I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(haExtensions may be appended to this structure and driver must check for those. See **extensions**.h](hRExtensions may be appended to this structure and driver must check for those. See }(hjhhhNhNubh)}(h**extensions**h]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(h)I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINEh]h)I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj}ubh)}(h*Created context will have single timeline.h]h*Created context will have single timeline.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMhj}ubeh}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1hhj|hMhj%ubh)}(hXh``extensions`` Zero-terminated chain of extensions. I915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam. I915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh](h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam.h]hI915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h]hI915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj%ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_i915_gem_context_param (C struct)c.drm_i915_gem_context_paramhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_context_paramh]j)}(h!struct drm_i915_gem_context_paramh](j)}(hjh]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhjshMubj)}(hdrm_i915_gem_context_paramh]j)}(hj`h]hdrm_i915_gem_context_param}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjbhhhjshMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj^hhhjshMubah}(h]jYah ](j j eh"]h$]h&]jj)jhuh1jhjshMhj[hhubj)}(hhh]h)}(h"Context parameter to set or query.h]h"Context parameter to set or query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj[hhhjshMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; }; **Members** ``ctx_id`` Context id ``size`` Size of the parameter **value** ``param`` Parameter to set or query ``value`` Context parameter value to be set or queriedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj`)}(hXstruct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; };h]hXstruct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hhh](h)}(h``ctx_id`` Context id h](j)}(h ``ctx_id``h]j)}(hjh]hctx_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj)}(hhh]h)}(h Context idh]h Context id}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj*hMhj ubh)}(h)``size`` Size of the parameter **value** h](j)}(h``size``h]j)}(hjNh]hsize}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjHubj)}(hhh]h)}(hSize of the parameter **value**h](hSize of the parameter }(hjghhhNhNubh)}(h **value**h]hvalue}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgubeh}(h]h ]h"]h$]h&]uh1hhjchKhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1hhjchKhj ubh)}(h$``param`` Parameter to set or query h](j)}(h ``param``h]j)}(hjh]hparam}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(hParameter to set or queryh]hParameter to set or query}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj ubh)}(h6``value`` Context parameter value to be set or queriedh](j)}(h ``value``h]j)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj)}(hhh]h)}(h,Context parameter value to be set or queriedh]h,Context parameter value to be set or queried}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h.. _Virtual Engine uAPI:h]h}(h]h ]h"]h$]h&]hԌvirtual-engine-uapiuh1hhMhhhhhNubh)}(h**Virtual Engine uAPI**h]h)}(hjh]hVirtual Engine uAPI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]jah ]h"]virtual engine uapiah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhh}j/jsh}jjsubh)}(hVirtual engine is a concept where userspace is able to configure a set of physical engines, submit a batch buffer, and let the driver execute it on any engine from the set as it sees fit.h]hVirtual engine is a concept where userspace is able to configure a set of physical engines, submit a batch buffer, and let the driver execute it on any engine from the set as it sees fit.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hThis is primarily useful on parts which have multiple instances of a same class engine, like for example GT3+ Skylake parts with their two VCS engines.h]hThis is primarily useful on parts which have multiple instances of a same class engine, like for example GT3+ Skylake parts with their two VCS engines.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXFor instance userspace can enumerate all engines of a certain class using the previously described `Engine Discovery uAPI`_. After that userspace can create a GEM context with a placeholder slot for the virtual engine (using `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class and instance respectively) and finally using the `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in the same reserved slot.h](hcFor instance userspace can enumerate all engines of a certain class using the previously described }(hjShhhNhNubh reference)}(h`Engine Discovery uAPI`_h]hEngine Discovery uAPI}(hj]hhhNhNubah}(h]h ]h"]h$]h&]nameEngine Discovery uAPIhԌengine-discovery-uapiuh1j[hjSresolvedKubhf. After that userspace can create a GEM context with a placeholder slot for the virtual engine (using }(hjShhhNhNubjU )}(h`I915_ENGINE_CLASS_INVALID`h]hI915_ENGINE_CLASS_INVALID}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjSubh and }(hjShhhNhNubjU )}(h `I915_ENGINE_CLASS_INVALID_NONE`h]hI915_ENGINE_CLASS_INVALID_NONE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjSubh< for class and instance respectively) and finally using the }(hjShhhNhNubjU )}(h'`I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE`h]h%I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjSubh< extension place a virtual engine in the same reserved slot.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hIExample of creating a virtual engine and submitting a batch buffer to it:h]hIExample of creating a virtual engine and submitting a batch buffer to it:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubj`)}(hX(I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, .engine_index = 0, // Place this virtual engine into engine map slot 0 .num_siblings = 2, .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, { I915_ENGINE_CLASS_VIDEO, 1 }, }, }; I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { .engines = { { I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE } }, .extensions = to_user_pointer(&virtual), // Chains after load_balance extension }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // Now we have created a GEM context with its engine map containing a // single virtual engine. Submissions to this slot can go either to // vcs0 or vcs1, depending on the load balancing algorithm used inside // the driver. The load balancing is dynamic from one batch buffer to // another and transparent to userspace. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0 which is the virtual engine gem_execbuf(drm_fd, &execbuf);h]hX(I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, .engine_index = 0, // Place this virtual engine into engine map slot 0 .num_siblings = 2, .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, { I915_ENGINE_CLASS_VIDEO, 1 }, }, }; I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { .engines = { { I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE } }, .extensions = to_user_pointer(&virtual), // Chains after load_balance extension }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // Now we have created a GEM context with its engine map containing a // single virtual engine. Submissions to this slot can go either to // vcs0 or vcs1, depending on the load balancing algorithm used inside // the driver. The load balancing is dynamic from one batch buffer to // another and transparent to userspace. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0 which is the virtual engine gem_execbuf(drm_fd, &execbuf);}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/i915_context_engines_parallel_submit (C struct)&c.i915_context_engines_parallel_submithNtauh1jhhhhhNhNubj)}(hhh](j)}(h$i915_context_engines_parallel_submith]j)}(h+struct i915_context_engines_parallel_submith](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(h$i915_context_engines_parallel_submith]j)}(hjh]h$i915_context_engines_parallel_submit}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h)Configure engine for parallel submission.h]h)Configure engine for parallel submission.}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhML hj' hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jB j8jB j9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; }; **Members** ``base`` base user extension. ``engine_index`` slot for parallel engine ``width`` number of contexts per parallel engine or in other words the number of batches in each submission ``num_siblings`` number of siblings per context or in other words the number of possible placements for each submission ``mbz16`` reserved for future use; must be zero ``flags`` all undefined flags must be zero, currently not defined flags ``mbz64`` reserved for future use; must be zero ``engines`` 2-d array of engine instances to configure parallel engine length = width (i) * num_siblings (j) index = j + i * num_siblingsh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ ubh:}(hjJ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMP hjF ubj`)}(hstruct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; };h]hstruct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; };}hjg sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMR hjF ubh)}(h **Members**h]h)}(hjx h]hMembers}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM] hjF ubh)}(hhh](h)}(h``base`` base user extension. h](j)}(h``base``h]j)}(hj h]hbase}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubj)}(hhh]h)}(hbase user extension.h]hbase user extension.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hM hj ubh)}(h*``engine_index`` slot for parallel engine h](j)}(h``engine_index``h]j)}(hj h]h engine_index}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubj)}(hhh]h)}(hslot for parallel engineh]hslot for parallel engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hM hj ubh)}(hl``width`` number of contexts per parallel engine or in other words the number of batches in each submission h](j)}(h ``width``h]j)}(hj !h]hwidth}(hj !hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj!ubj)}(hhh]h)}(hanumber of contexts per parallel engine or in other words the number of batches in each submissionh]hanumber of contexts per parallel engine or in other words the number of batches in each submission}(hj"!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhj!hM hj ubh)}(hx``num_siblings`` number of siblings per context or in other words the number of possible placements for each submission h](j)}(h``num_siblings``h]j)}(hjC!h]h num_siblings}(hjE!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj=!ubj)}(hhh]h)}(hfnumber of siblings per context or in other words the number of possible placements for each submissionh]hfnumber of siblings per context or in other words the number of possible placements for each submission}(hj\!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjY!ubah}(h]h ]h"]h$]h&]uh1jhj=!ubeh}(h]h ]h"]h$]h&]uh1hhjX!hM hj ubh)}(h0``mbz16`` reserved for future use; must be zero h](j)}(h ``mbz16``h]j)}(hj}!h]hmbz16}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjw!ubj)}(hhh]h)}(h%reserved for future use; must be zeroh]h%reserved for future use; must be zero}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1jhjw!ubeh}(h]h ]h"]h$]h&]uh1hhj!hM hj ubh)}(hH``flags`` all undefined flags must be zero, currently not defined flags h](j)}(h ``flags``h]j)}(hj!h]hflags}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj!ubj)}(hhh]h)}(h=all undefined flags must be zero, currently not defined flagsh]h=all undefined flags must be zero, currently not defined flags}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhj!hM hj ubh)}(h0``mbz64`` reserved for future use; must be zero h](j)}(h ``mbz64``h]j)}(hj!h]hmbz64}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj!ubj)}(hhh]h)}(h%reserved for future use; must be zeroh]h%reserved for future use; must be zero}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhj"hM hj ubh)}(h``engines`` 2-d array of engine instances to configure parallel engine length = width (i) * num_siblings (j) index = j + i * num_siblingsh](j)}(h ``engines``h]j)}(hj("h]hengines}(hj*"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&"ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj""ubj)}(hhh](h)}(h:2-d array of engine instances to configure parallel engineh]h:2-d array of engine instances to configure parallel engine}(hjA"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj>"ubh)}(hBlength = width (i) * num_siblings (j) index = j + i * num_siblingsh]hBlength = width (i) * num_siblings (j) index = j + i * num_siblings}(hjP"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj="hM hj>"ubeh}(h]h ]h"]h$]h&]uh1jhj""ubeh}(h]h ]h"]h$]h&]uh1hhj="hM hj ubeh}(h]h ]h"]h$]h&]uh1hhjF ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjy"h]h Description}(hj{"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjw"ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hXOSetup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot's configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.h]hXSSetup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn’t tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot’s configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMM hhhhubh)}(hX9The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.h]hX9The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMV hhhhubh)}(hReturns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn't supported on the platform / submission interface. Returns -ENODEV if extension isn't supported on the platform / submission interface.h]hReturns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn’t supported on the platform / submission interface. Returns -ENODEV if extension isn’t supported on the platform / submission interface.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM_ hhhhubj`)}(hX3Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1]) Results in the following valid placement: CS[0], CS[1] Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3]) Results in the following valid placements: CS[0], CS[1] CS[2], CS[3] This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3] Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3]) Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVALh]hX3Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1]) Results in the following valid placement: CS[0], CS[1] Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3]) Results in the following valid placements: CS[0], CS[1] CS[2], CS[3] This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3] Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3]) Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVAL}hj"sbah}(h]h ]h"]h$]h&]jjjjnonej}uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMe hhhhubh)}(h.. _Context Engine Map uAPI:h]h}(h]h ]h"]h$]h&]hԌcontext-engine-map-uapiuh1hhMhhhhhNubh)}(h**Context Engine Map uAPI**h]h)}(hj"h]hContext Engine Map uAPI}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubah}(h]j"ah ]h"]context engine map uapiah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhh}j"j"sh}j"j"subh)}(hContext engine map is a new way of addressing engines when submitting batch- buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` inside the flags field of `struct drm_i915_gem_execbuffer2`.h](hContext engine map is a new way of addressing engines when submitting batch- buffers, replacing the existing way of using identifiers like }(hj"hhhNhNubjU )}(h`I915_EXEC_BLT`h]h I915_EXEC_BLT}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj"ubh inside the flags field of }(hj"hhhNhNubjU )}(h!`struct drm_i915_gem_execbuffer2`h]hstruct drm_i915_gem_execbuffer2}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj"ubh.}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hTo use it created GEM contexts need to be configured with a list of engines the user is intending to submit to. This is accomplished using the `I915_CONTEXT_PARAM_ENGINES` parameter and `struct i915_context_param_engines`.h](hTo use it created GEM contexts need to be configured with a list of engines the user is intending to submit to. This is accomplished using the }(hj&#hhhNhNubjU )}(h`I915_CONTEXT_PARAM_ENGINES`h]hI915_CONTEXT_PARAM_ENGINES}(hj.#hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj&#ubh parameter and }(hj&#hhhNhNubjU )}(h#`struct i915_context_param_engines`h]h!struct i915_context_param_engines}(hj@#hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj&#ubh.}(hj&#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h[For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the configured map.h](hFor such contexts the }(hjY#hhhNhNubjU )}(h`I915_EXEC_RING_MASK`h]hI915_EXEC_RING_MASK}(hja#hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjY#ubh0 field becomes an index into the configured map.}(hjY#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h;Example of creating such context and submitting against it:h]h;Example of creating such context and submitting against it:}(hjz#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj`)}(hX}I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, { I915_ENGINE_CLASS_COPY, 0 } } }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // We have now created a GEM context with two engines in the map: // Index 0 points to rcs0 while index 1 points to bcs0. Other engines // will not be accessible from this context. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context gem_execbuf(drm_fd, &execbuf); ... execbuf.rsvd1 = ctx_id; execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context gem_execbuf(drm_fd, &execbuf);h]hX}I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, { I915_ENGINE_CLASS_COPY, 0 } } }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // We have now created a GEM context with two engines in the map: // Index 0 points to rcs0 while index 1 points to bcs0. Other engines // will not be accessible from this context. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context gem_execbuf(drm_fd, &execbuf); ... execbuf.rsvd1 = ctx_id; execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context gem_execbuf(drm_fd, &execbuf);}hj#sbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j3drm_i915_gem_context_create_ext_setparam (C struct)*c.drm_i915_gem_context_create_ext_setparamhNtauh1jhhhhhNhNubj)}(hhh](j)}(h(drm_i915_gem_context_create_ext_setparamh]j)}(h/struct drm_i915_gem_context_create_ext_setparamh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhj#hM ubj)}(h(drm_i915_gem_context_create_ext_setparamh]j)}(hj#h]h(drm_i915_gem_context_create_ext_setparam}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj#hhhj#hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj#hhhj#hM ubah}(h]j#ah ](j j eh"]h$]h&]jj)jhuh1jhj#hM hj#hhubj)}(hhh]h)}(h:Context parameter to set or query during context creation.h]h:Context parameter to set or query during context creation.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM# hj#hhubah}(h]h ]h"]h$]h&]uh1jhj#hhhj#hM ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j $j8j $j9j:j;uh1jhhhhhNhNubj=)}(hXB**Definition**:: struct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``param`` Context parameter to set or query. See struct drm_i915_gem_context_param.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$ubh:}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM' hj$ubj`)}(hstruct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; };h]hstruct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; };}hj1$sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM) hj$ubh)}(h **Members**h]h)}(hjB$h]hMembers}(hjD$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@$ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM. hj$ubh)}(hhh](h)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]j)}(hja$h]hbase}(hjc$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_$ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM' hj[$ubj)}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hjz$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv$hM' hjw$ubah}(h]h ]h"]h$]h&]uh1jhj[$ubeh}(h]h ]h"]h$]h&]uh1hhjv$hM' hjX$ubh)}(hS``param`` Context parameter to set or query. See struct drm_i915_gem_context_param.h](j)}(h ``param``h]j)}(hj$h]hparam}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM, hj$ubj)}(hhh]h)}(hIContext parameter to set or query. See struct drm_i915_gem_context_param.h]hIContext parameter to set or query. See struct drm_i915_gem_context_param.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM, hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1hhj$hM, hjX$ubeh}(h]h ]h"]h$]h&]uh1hhj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_vm_control (C struct)c.drm_i915_gem_vm_controlhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_vm_controlh]j)}(hstruct drm_i915_gem_vm_controlh](j)}(hjh]hstruct}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM3 ubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$hhhj%hM3 ubj)}(hdrm_i915_gem_vm_controlh]j)}(hj$h]hdrm_i915_gem_vm_control}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj$hhhj%hM3 ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj$hhhj%hM3 ubah}(h]j$ah ](j j eh"]h$]h&]jj)jhuh1jhj%hM3 hj$hhubj)}(hhh]h)}(h"Structure to create or destroy VM.h]h"Structure to create or destroy VM.}(hj5%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7 hj2%hhubah}(h]h ]h"]h$]h&]uh1jhj$hhhj%hM3 ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jM%j8jM%j9j:j;uh1jhhhhhNhNubj=)}(hX&**Definition**:: struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; }; **Members** ``extensions`` Zero-terminated chain of extensions. ``flags`` reserved for future usage, currently MBZ ``vm_id`` Id of the VM created or to be destroyedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjY%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU%ubh:}(hjU%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM; hjQ%ubj`)}(h[struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; };h]h[struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; };}hjr%sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM= hjQ%ubh)}(h **Members**h]h)}(hj%h]hMembers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMC hjQ%ubh)}(hhh](h)}(h4``extensions`` Zero-terminated chain of extensions. h](j)}(h``extensions``h]j)}(hj%h]h extensions}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhML hj%ubj)}(hhh]h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hML hj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1hhj%hML hj%ubh)}(h3``flags`` reserved for future usage, currently MBZ h](j)}(h ``flags``h]j)}(hj%h]hflags}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj%ubj)}(hhh]h)}(h(reserved for future usage, currently MBZh]h(reserved for future usage, currently MBZ}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hKhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1hhj%hKhj%ubh)}(h1``vm_id`` Id of the VM created or to be destroyedh](j)}(h ``vm_id``h]j)}(hj&h]hvm_id}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj&ubj)}(hhh]h)}(h'Id of the VM created or to be destroyedh]h'Id of the VM created or to be destroyed}(hj-&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj*&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1hhj)&hKhj%ubeh}(h]h ]h"]h$]h&]uh1hhjQ%ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjW&h]h Description}(hjY&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU&ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hDRM_I915_GEM_VM_CREATE -h]hDRM_I915_GEM_VM_CREATE -}(hjm&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM8 hhhhubh)}(hCreate a new virtual memory address space (ppGTT) for use within a context on the same file. Extensions can be provided to configure exactly how the address space is setup upon creation.h]hCreate a new virtual memory address space (ppGTT) for use within a context on the same file. Extensions can be provided to configure exactly how the address space is setup upon creation.}(hj|&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM: hhhhubh)}(hiThe id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is returned in the outparam **id**.h](hbThe id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is returned in the outparam }(hj&hhhNhNubh)}(h**id**h]hid}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&ubh.}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM> hhhhubh)}(hAn extension chain maybe provided, starting with **extensions**, and terminated by the **next_extension** being 0. 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Currently, no extensions are defined.}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMA hhhhubh)}(hDRM_I915_GEM_VM_DESTROY -h]hDRM_I915_GEM_VM_DESTROY -}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMD hhhhubh)}(h*ubh:}(hj>*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj:*ubj`)}(hstruct drm_i915_perf_oa_config { char uuid[36]; __u32 n_mux_regs; __u32 n_boolean_regs; __u32 n_flex_regs; __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; };h]hstruct drm_i915_perf_oa_config { char uuid[36]; __u32 n_mux_regs; __u32 n_boolean_regs; __u32 n_flex_regs; __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; };}hj[*sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj:*ubh)}(h **Members**h]h)}(hjl*h]hMembers}(hjn*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj*ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj:*ubh)}(hhh](h)}(h@``uuid`` String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" h](j)}(h``uuid``h]j)}(hj*h]huuid}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj*ubj)}(hhh]h)}(h6String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"h]h:String formatted like “%08x-%04x-%04x-%04x-%012x”}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubh)}(h=``n_mux_regs`` Number of mux regs in :c:type:`mux_regs_ptr`. h](j)}(h``n_mux_regs``h]j)}(hj*h]h n_mux_regs}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj*ubj)}(hhh]h)}(h-Number of mux regs in :c:type:`mux_regs_ptr`.h](hNumber of mux regs in }(hj*hhhNhNubh)}(h:c:type:`mux_regs_ptr`h]j)}(hj*h]h mux_regs_ptr}(hj*hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j mux_regs_ptruh1hhj*hM hj*ubh.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubh)}(hI``n_boolean_regs`` Number of boolean regs in :c:type:`boolean_regs_ptr`. h](j)}(h``n_boolean_regs``h]j)}(hj +h]hn_boolean_regs}(hj"+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj+ubj)}(hhh]h)}(h5Number of boolean regs in :c:type:`boolean_regs_ptr`.h](hNumber of boolean regs in }(hj9+hhhNhNubh)}(h:c:type:`boolean_regs_ptr`h]j)}(hjC+h]hboolean_regs_ptr}(hjE+hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjA+ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j boolean_regs_ptruh1hhj5+hM hj9+ubh.}(hj9+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj5+hM hj6+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1hhj5+hM hj*ubh)}(h@``n_flex_regs`` Number of flex regs in :c:type:`flex_regs_ptr`. h](j)}(h``n_flex_regs``h]j)}(hj|+h]h n_flex_regs}(hj~+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz+ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjv+ubj)}(hhh]h)}(h/Number of flex regs in :c:type:`flex_regs_ptr`.h](hNumber of flex regs in }(hj+hhhNhNubh)}(h:c:type:`flex_regs_ptr`h]j)}(hj+h]h flex_regs_ptr}(hj+hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j flex_regs_ptruh1hhj+hM hj+ubh.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj+hM hj+ubah}(h]h ]h"]h$]h&]uh1jhjv+ubeh}(h]h ]h"]h$]h&]uh1hhj+hM hj*ubh)}(h``mux_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_mux_regs`). h](j)}(h``mux_regs_ptr``h]j)}(hj+h]h mux_regs_ptr}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj+ubj)}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_mux_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hj+hhhNhNubh)}(h:c:type:`n_mux_regs`h]j)}(hj+h]h n_mux_regs}(hj+hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j n_mux_regsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj+ubh).}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj,hM hj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1hhj+hM hj*ubh)}(h``boolean_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_boolean_regs`). h](j)}(h``boolean_regs_ptr``h]j)}(hj5,h]hboolean_regs_ptr}(hj7,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3,ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj/,ubj)}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_boolean_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hjN,hhhNhNubh)}(h:c:type:`n_boolean_regs`h]j)}(hjX,h]hn_boolean_regs}(hjZ,hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjV,ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j n_boolean_regsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjN,ubh).}(hjN,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhju,hM hjK,ubah}(h]h ]h"]h$]h&]uh1jhj/,ubeh}(h]h ]h"]h$]h&]uh1hhjJ,hM hj*ubh)}(h``flex_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_flex_regs`).h](j)}(h``flex_regs_ptr``h]j)}(hj,h]h flex_regs_ptr}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj,ubj)}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_flex_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hj,hhhNhNubh)}(h:c:type:`n_flex_regs`h]j)}(hj,h]h n_flex_regs}(hj,hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j n_flex_regsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj,ubh).}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj,hM hj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1hhj,hM hj*ubeh}(h]h ]h"]h$]h&]uh1hhj:*ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj,h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h?Structure to upload perf dynamic configuration into the kernel.h]h?Structure to upload perf dynamic configuration into the kernel.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_query_item (C struct)c.drm_i915_query_itemhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_itemh]j)}(hstruct drm_i915_query_itemh](j)}(hjh]hstruct}(hj6-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2-hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjD-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2-hhhjC-hM ubj)}(hdrm_i915_query_itemh]j)}(hj0-h]hdrm_i915_query_item}(hjV-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjR-ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj2-hhhjC-hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj.-hhhjC-hM ubah}(h]j)-ah ](j j eh"]h$]h&]jj)jhuh1jhjC-hM hj+-hhubj)}(hhh]h)}(h.An individual query for the kernel to process.h]h.An individual query for the kernel to process.}(hjx-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hju-hhubah}(h]h ]h"]h$]h&]uh1jhj+-hhhjC-hM ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j-j8j-j9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; }; **Members** ``query_id`` The id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) ``length`` When set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item. ``flags`` When :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0. When :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following: - ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` When :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine. ``data_ptr`` Data will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-ubh:}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-ubj`)}(hXkstruct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; };h]hXkstruct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; };}hj-sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-ubh)}(h **Members**h]h)}(hj-h]hMembers}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-ubh)}(hhh](h)}(hXi``query_id`` The id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h](j)}(h ``query_id``h]j)}(hj-h]hquery_id}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-ubj)}(hhh]h)}(hhh]h)}(hXUThe id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h](j)}(h9The id for this query. Currently accepted query IDs are:h]h9The id for this query. Currently accepted query IDs are:}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-hM hj.ubj)}(hhh]jp )}(hhh](ju )}(hJ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info)h]h)}(hj.h](j)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj .hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh* (see struct drm_i915_query_topology_info)}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj.ubah}(h]h ]h"]h$]h&]uh1jt hj.ubju )}(h@``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info)h]h)}(hjA.h](j)}(h``DRM_I915_QUERY_ENGINE_INFO``h]hDRM_I915_QUERY_ENGINE_INFO}(hjF.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC.ubh" (see struct drm_i915_engine_info)}(hjC.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj?.ubah}(h]h ]h"]h$]h&]uh1jt hj.ubju )}(hF``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config)h]h)}(hjg.h](j)}(h``DRM_I915_QUERY_PERF_CONFIG``h]hDRM_I915_QUERY_PERF_CONFIG}(hjl.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji.ubh( (see struct drm_i915_query_perf_config)}(hji.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hje.ubah}(h]h ]h"]h$]h&]uh1jt hj.ubju )}(hL``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions)h]h)}(hj.h](j)}(h!``DRM_I915_QUERY_MEMORY_REGIONS``h]hDRM_I915_QUERY_MEMORY_REGIONS}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh+ (see struct drm_i915_query_memory_regions)}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj.ubah}(h]h ]h"]h$]h&]uh1jt hj.ubju )}(h?``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`)h]h)}(hj.h](j)}(h ``DRM_I915_QUERY_HWCONFIG_BLOB``h]hDRM_I915_QUERY_HWCONFIG_BLOB}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh (see }(hj.hhhNhNubjU )}(h`GuC HWCONFIG blob uAPI`h]hGuC HWCONFIG blob uAPI}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj.ubh)}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj.ubah}(h]h ]h"]h$]h&]uh1jt hj.ubju )}(hO``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info)h]h)}(hj.h](j)}(h%``DRM_I915_QUERY_GEOMETRY_SUBSLICES``h]h!DRM_I915_QUERY_GEOMETRY_SUBSLICES}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh* (see struct drm_i915_query_topology_info)}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj.ubah}(h]h ]h"]h$]h&]uh1jt hj.ubju )}(h]``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h]h)}(h\``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version)h](j)}(h)``DRM_I915_QUERY_GUC_SUBMISSION_VERSION``h]h%DRM_I915_QUERY_GUC_SUBMISSION_VERSION}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubh3 (see struct drm_i915_query_guc_submission_version)}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj-hM hj/ubah}(h]h ]h"]h$]h&]uh1jt hj.ubeh}(h]h ]h"]h$]h&]j j uh1jo hj8.hM hj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1hhj-hM hj-ubah}(h]h ]h"]h$]h&]uh1hhj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1hhj-hM hj-ubh)}(h``length`` When set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item. h](j)}(h ``length``h]j)}(hj_/h]hlength}(hja/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]/ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjY/ubj)}(hhh]h)}(hWhen set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item.h](h]When set to zero by userspace, this is filled with the size of the data to be written at the }(hjx/hhhNhNubh)}(h **data_ptr**h]hdata_ptr}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx/ubhg pointer. The kernel sets this value to a negative value to signal an error on a particular query item.}(hjx/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hju/ubah}(h]h ]h"]h$]h&]uh1jhjY/ubeh}(h]h ]h"]h$]h&]uh1hhjt/hM hj-ubh)}(hX``flags`` When :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0. When :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following: - ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` When :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine. h](j)}(h ``flags``h]j)}(hj/h]hflags}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj/ubj)}(hhh](h)}(hGWhen :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0.h](hWhen }(hj/hhhNhNubh)}(h:c:type:`query_id`h]j)}(hj/h]hquery_id}(hj/hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j query_iduh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj/ubh == }(hj/hhhNhNubj)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubh , must be 0.}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/hM hj/ubh)}(hXWhen :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following:h](hWhen }(hj0hhhNhNubh)}(h:c:type:`query_id`h]j)}(hj0h]hquery_id}(hj0hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j query_iduh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj0ubh == }(hj0hhhNhNubj)}(h``DRM_I915_QUERY_PERF_CONFIG``h]hDRM_I915_QUERY_PERF_CONFIG}(hj40hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh, must be one of the following:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/0hM hj/ubj)}(h- ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` h]jp )}(hhh](ju )}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]h)}(hjU0h]j)}(hjU0h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hjZ0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjW0ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjS0ubah}(h]h ]h"]h$]h&]uh1jt hjP0ubju )}(h,``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``h]h)}(hjv0h]j)}(hjv0h]h(DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID}(hj{0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjx0ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjt0ubah}(h]h ]h"]h$]h&]uh1jt hjP0ubju )}(h(``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` h]h)}(h'``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID``h]j)}(hj0h]h#DRM_I915_QUERY_PERF_CONFIG_FOR_UUID}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj0ubah}(h]h ]h"]h$]h&]uh1jt hjP0ubeh}(h]h ]h"]h$]h&]j j uh1jo hjm0hM hjL0ubah}(h]h ]h"]h$]h&]uh1jhjm0hM hj/ubh)}(hWhen :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine.h](hWhen }(hj0hhhNhNubh)}(h:c:type:`query_id`h]j)}(hj0h]hquery_id}(hj0hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j query_iduh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj0ubh == }(hj0hhhNhNubj)}(h%``DRM_I915_QUERY_GEOMETRY_SUBSLICES``h]h!DRM_I915_QUERY_GEOMETRY_SUBSLICES}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubhR must contain a struct i915_engine_class_instance that references a render engine.}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj0hM hj/ubeh}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1hhj/hM hj-ubh)}(h``data_ptr`` Data will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](j)}(h ``data_ptr``h]j)}(hj1h]hdata_ptr}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM) hj1ubj)}(hhh]h)}(hData will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](h0Data will be written at the location pointed by }(hj21hhhNhNubh)}(h **data_ptr**h]hdata_ptr}(hj:1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj21ubh when the value of }(hj21hhhNhNubh)}(h **length**h]hlength}(hjL1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj21ubh< matches the length of the data to be written by the kernel.}(hj21hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM( hj/1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1hhj.1hM) hj-ubeh}(h]h ]h"]h$]h&]uh1hhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj1h]h Description}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~1ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM- hhhhubh)}(hThe behaviour is determined by the **query_id**. Note that exactly what **data_ptr** is also depends on the specific **query_id**.h](h#The behaviour is determined by the }(hj1hhhNhNubh)}(h **query_id**h]hquery_id}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh. Note that exactly what }(hj1hhhNhNubh)}(h **data_ptr**h]hdata_ptr}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh! is also depends on the specific }(hj1hhhNhNubh)}(h **query_id**h]hquery_id}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_query (C struct)c.drm_i915_queryhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_queryh]j)}(hstruct drm_i915_queryh](j)}(hjh]hstruct}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhj2hM ubj)}(hdrm_i915_queryh]j)}(hj1h]hdrm_i915_query}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj1hhhj2hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj1hhhj2hM ubah}(h]j1ah ](j j eh"]h$]h&]jj)jhuh1jhj2hM hj1hhubj)}(hhh]h)}(hISupply an array of struct drm_i915_query_item for the kernel to fill out.h]hISupply an array of struct drm_i915_query_item for the kernel to fill out.}(hj62hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM1 hj32hhubah}(h]h ]h"]h$]h&]uh1jhj1hhhj2hM ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jN2j8jN2j9j:j;uh1jhhhhhNhNubj=)}(hXl**Definition**:: struct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; }; **Members** ``num_items`` The number of elements in the **items_ptr** array ``flags`` Unused for now. Must be cleared to zero. ``items_ptr`` Pointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjZ2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV2ubh:}(hjV2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5 hjR2ubj`)}(hUstruct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; };h]hUstruct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; };}hjs2sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7 hjR2ubh)}(h **Members**h]h)}(hj2h]hMembers}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM= hjR2ubh)}(hhh](h)}(h@``num_items`` The number of elements in the **items_ptr** array h](j)}(h ``num_items``h]j)}(hj2h]h num_items}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMH hj2ubj)}(hhh]h)}(h1The number of elements in the **items_ptr** arrayh](hThe number of elements in the }(hj2hhhNhNubh)}(h **items_ptr**h]h items_ptr}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ubh array}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj2hMH hj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhj2hMH hj2ubh)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]j)}(hj2h]hflags}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMM hj2ubj)}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMM hj3ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhj3hMM hj2ubh)}(ho``items_ptr`` Pointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](j)}(h ``items_ptr``h]j)}(hj'3h]h items_ptr}(hj)3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%3ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMR hj!3ubj)}(hhh]h)}(haPointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](hSPointer to an array of struct drm_i915_query_item. The number of array elements is }(hj@3hhhNhNubh)}(h **num_items**h]h num_items}(hjH3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@3ubh.}(hj@3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj<3hMR hj=3ubah}(h]h ]h"]h$]h&]uh1jhj!3ubeh}(h]h ]h"]h$]h&]uh1hhj<3hMR hj2ubeh}(h]h ]h"]h$]h&]uh1hhjR2ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj{3h]h Description}(hj}3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjy3ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMV hhhhubh)}(h`Note that this is generally a two step process for each struct drm_i915_query_item in the array:h]h`Note that this is generally a two step process for each struct drm_i915_query_item in the array:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2 hhhhubhenumerated_list)}(hhh](ju )}(hX4Call the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with :c:type:`drm_i915_query_item.length ` set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties). h]h)}(hX3Call the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with :c:type:`drm_i915_query_item.length ` set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties).h](hWCall the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with }(hj3hhhNhNubh)}(h::c:type:`drm_i915_query_item.length `h]j)}(hj3h]hdrm_i915_query_item.length}(hj3hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5 hj3ubh set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties).}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj3hM5 hj3ubah}(h]h ]h"]h$]h&]uh1jt hj3ubju )}(hXPNext we call DRM_IOCTL_I915_QUERY again, this time with the :c:type:`drm_i915_query_item.data_ptr ` equal to our newly allocated blob. Note that the :c:type:`drm_i915_query_item.length ` should still be the same as what the kernel previously set. At this point the kernel can fill in the blob. h]h)}(hXONext we call DRM_IOCTL_I915_QUERY again, this time with the :c:type:`drm_i915_query_item.data_ptr ` equal to our newly allocated blob. Note that the :c:type:`drm_i915_query_item.length ` should still be the same as what the kernel previously set. At this point the kernel can fill in the blob.h](h`h]j)}(hj3h]hdrm_i915_query_item.data_ptr}(hj3hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM: hj3ubh2 equal to our newly allocated blob. Note that the }(hj3hhhNhNubh)}(h::c:type:`drm_i915_query_item.length `h]j)}(hj4h]hdrm_i915_query_item.length}(hj4hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhj 4hM: hj3ubhk should still be the same as what the kernel previously set. At this point the kernel can fill in the blob.}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj 4hM: hj3ubah}(h]h ]h"]h$]h&]uh1jt hj3ubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j3hhhhhNhNubh)}(hNote that for some query items it can make sense for userspace to just pass in a buffer/blob equal to or larger than the required size. In this case only a single ioctl call is needed. For some smaller query items this can work quite well.h]hNote that for some query items it can make sense for userspace to just pass in a buffer/blob equal to or larger than the required size. In this case only a single ioctl call is needed. For some smaller query items this can work quite well.}(hjK4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM? hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'drm_i915_query_topology_info (C struct)c.drm_i915_query_topology_infohNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_topology_infoh]j)}(h#struct drm_i915_query_topology_infoh](j)}(hjh]hstruct}(hjs4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjo4hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMG ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjo4hhhj4hMG ubj)}(hdrm_i915_query_topology_infoh]j)}(hjm4h]hdrm_i915_query_topology_info}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjo4hhhj4hMG ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjk4hhhj4hMG ubah}(h]jf4ah ](j j eh"]h$]h&]jj)jhuh1jhj4hMG hjh4hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjh4hhhj4hMG ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j4j8j4j9j:j;uh1jhhhhhNhNubj=)}(hX? **Definition**:: struct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; }; **Members** ``flags`` Unused for now. Must be cleared to zero. ``max_slices`` The number of bits used to express the slice mask. ``max_subslices`` The number of bits used to express the subslice mask. ``max_eus_per_subslice`` The number of bits in the EU mask that correspond to a single subslice's EUs. ``subslice_offset`` Offset in data[] at which the subslice masks are stored. ``subslice_stride`` Stride at which each of the subslice masks for each slice are stored. ``eu_offset`` Offset in data[] at which the EU masks are stored. ``eu_stride`` Stride at which each of the EU masks for each subslice are stored. ``data`` Contains 3 pieces of information : - The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. - The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 - The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubh:}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM^ hj4ubj`)}(hstruct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; };h]hstruct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; };}hj4sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM` hj4ubh)}(h **Members**h]h)}(hj4h]hMembers}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMl hj4ubh)}(hhh](h)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]j)}(hj5h]hflags}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMb hj 5ubj)}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hj,5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(5hMb hj)5ubah}(h]h ]h"]h$]h&]uh1jhj 5ubeh}(h]h ]h"]h$]h&]uh1hhj(5hMb hj 5ubh)}(hB``max_slices`` The number of bits used to express the slice mask. h](j)}(h``max_slices``h]j)}(hjL5h]h max_slices}(hjN5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJ5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMi hjF5ubj)}(hhh]h)}(h2The number of bits used to express the slice mask.h]h2The number of bits used to express the slice mask.}(hje5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhja5hMi hjb5ubah}(h]h ]h"]h$]h&]uh1jhjF5ubeh}(h]h ]h"]h$]h&]uh1hhja5hMi hj 5ubh)}(hH``max_subslices`` The number of bits used to express the subslice mask. h](j)}(h``max_subslices``h]j)}(hj5h]h max_subslices}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMp hj5ubj)}(hhh]h)}(h5The number of bits used to express the subslice mask.h]h5The number of bits used to express the subslice mask.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMp hj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1hhj5hMp hj 5ubh)}(hg``max_eus_per_subslice`` The number of bits in the EU mask that correspond to a single subslice's EUs. h](j)}(h``max_eus_per_subslice``h]j)}(hj5h]hmax_eus_per_subslice}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMx hj5ubj)}(hhh]h)}(hMThe number of bits in the EU mask that correspond to a single subslice's EUs.h]hOThe number of bits in the EU mask that correspond to a single subslice’s EUs.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMw hj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1hhj5hMx hj 5ubh)}(hM``subslice_offset`` Offset in data[] at which the subslice masks are stored. h](j)}(h``subslice_offset``h]j)}(hj5h]hsubslice_offset}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj5ubj)}(hhh]h)}(h8Offset in data[] at which the subslice masks are stored.h]h8Offset in data[] at which the subslice masks are stored.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 6hM hj6ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1hhj 6hM hj 5ubh)}(hZ``subslice_stride`` Stride at which each of the subslice masks for each slice are stored. h](j)}(h``subslice_stride``h]j)}(hj16h]hsubslice_stride}(hj36hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj+6ubj)}(hhh]h)}(hEStride at which each of the subslice masks for each slice are stored.h]hEStride at which each of the subslice masks for each slice are stored.}(hjJ6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjG6ubah}(h]h ]h"]h$]h&]uh1jhj+6ubeh}(h]h ]h"]h$]h&]uh1hhjF6hM hj 5ubh)}(hA``eu_offset`` Offset in data[] at which the EU masks are stored. h](j)}(h ``eu_offset``h]j)}(hjk6h]h eu_offset}(hjm6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hje6ubj)}(hhh]h)}(h2Offset in data[] at which the EU masks are stored.h]h2Offset in data[] at which the EU masks are stored.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hM hj6ubah}(h]h ]h"]h$]h&]uh1jhje6ubeh}(h]h ]h"]h$]h&]uh1hhj6hM hj 5ubh)}(hQ``eu_stride`` Stride at which each of the EU masks for each subslice are stored. h](j)}(h ``eu_stride``h]j)}(hj6h]h eu_stride}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj6ubj)}(hhh]h)}(hBStride at which each of the EU masks for each subslice are stored.h]hBStride at which each of the EU masks for each subslice are stored.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hM hj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1hhj6hM hj 5ubh)}(hX```data`` Contains 3 pieces of information : - The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. - The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 - The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](j)}(h``data``h]j)}(hj6h]hdata}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj6ubj)}(hhh](h)}(h"Contains 3 pieces of information :h]h"Contains 3 pieces of information :}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj6ubjp )}(hhh](ju )}(hX6The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. h](h)}(hThe slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula :h]hThe slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula :}(hj 7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubj`)}(h(data[X / 8] >> (X % 8)) & 1h]h(data[X / 8] >> (X % 8)) & 1}hj7sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjj1uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubh)}(hXrStarting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask.h]hX|Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform’s subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as “gslices” or “cslices” since userspace is capable of inferring those from the subslice mask.}(hj-7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubeh}(h]h ]h"]h$]h&]uh1jt hj7ubju )}(hXThe subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 h](h)}(hX7The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula :h]hX?The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term “subslice” to refer to what the hardware documentation describes as a “dual-subslices.” The availability of subslice Y in slice X can be queried with the following formula :}(hjF7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjB7ubj`)}(hD(data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1h]hD(data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1}hjU7sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjj1uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjB7ubeh}(h]h ]h"]h$]h&]uh1jt hj7ubju )}(hX9The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](h)}(hThe EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula :h]hThe EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula :}(hjq7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjm7ubj`)}(h\(data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h]h\(data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1}hj7sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjjj1uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjm7ubeh}(h]h ]h"]h$]h&]uh1jt hj7ubeh}(h]h ]h"]h$]h&]j j uh1jo hj7hM hj6ubeh}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1hhj6hM hj 5ubeh}(h]h ]h"]h$]h&]uh1hhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj7h]h Description}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hSDescribes slice/subslice/EU information queried by ``DRM_I915_QUERY_TOPOLOGY_INFO``h](h3Describes slice/subslice/EU information queried by }(hj7hhhNhNubj)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM[ hhhhubh)}(h.. _Engine Discovery uAPI:h]h}(h]h ]h"]h$]h&]hjmuh1hhMhhhhhN referencedKubh)}(h**Engine Discovery uAPI**h]h)}(hj7h]hEngine Discovery uAPI}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubah}(h]jmah ]h"]engine discovery uapiah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMa hhhhh}j 8j7sh}jmj7sj7Kubh)}(hEngine discovery uAPI is a way of enumerating physical engines present in a GPU associated with an open i915 DRM file descriptor. This supersedes the old way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like `I915_PARAM_HAS_BLT`.h](hEngine discovery uAPI is a way of enumerating physical engines present in a GPU associated with an open i915 DRM file descriptor. This supersedes the old way of using }(hj8hhhNhNubjU )}(h`DRM_IOCTL_I915_GETPARAM`h]hDRM_IOCTL_I915_GETPARAM}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj8ubh and engine identifiers like }(hj8hhhNhNubjU )}(h`I915_PARAM_HAS_BLT`h]hI915_PARAM_HAS_BLT}(hj,8hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj8ubh.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hThe need for this interface came starting with Icelake and newer GPUs, which started to establish a pattern of having multiple engines of a same class, where not all instances were always completely functionally equivalent.h]hThe need for this interface came starting with Icelake and newer GPUs, which started to establish a pattern of having multiple engines of a same class, where not all instances were always completely functionally equivalent.}(hjE8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hqEntry point for this uapi is `DRM_IOCTL_I915_QUERY` with the `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.h](hEntry point for this uapi is }(hjT8hhhNhNubjU )}(h`DRM_IOCTL_I915_QUERY`h]hDRM_IOCTL_I915_QUERY}(hj\8hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjT8ubh with the }(hjT8hhhNhNubjU )}(h`DRM_I915_QUERY_ENGINE_INFO`h]hDRM_I915_QUERY_ENGINE_INFO}(hjn8hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjT8ubh as the queried item id.}(hjT8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h(Example for getting the list of engines:h]h(Example for getting the list of engines:}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj`)}(hXstruct drm_i915_query_engine_info *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_ENGINE_INFO; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of engines. The kernel will fill out the // item.length for us, which is the number of bytes we need. // // Alternatively a large buffer can be allocated straightaway enabling // querying in one pass, in which case item.length should contain the // length of the provided buffer. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with info on all engines. item.data_ptr = (uintptr_t)&info; err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each engine in the array for (i = 0; i < info->num_engines; i++) { struct drm_i915_engine_info einfo = info->engines[i]; u16 class = einfo.engine.class; u16 instance = einfo.engine.instance; .... } free(info);h]hXstruct drm_i915_query_engine_info *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_ENGINE_INFO; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of engines. The kernel will fill out the // item.length for us, which is the number of bytes we need. // // Alternatively a large buffer can be allocated straightaway enabling // querying in one pass, in which case item.length should contain the // length of the provided buffer. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with info on all engines. item.data_ptr = (uintptr_t)&info; err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each engine in the array for (i = 0; i < info->num_engines; i++) { struct drm_i915_engine_info einfo = info->engines[i]; u16 class = einfo.engine.class; u16 instance = einfo.engine.instance; .... } free(info);}hj8sbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hEach of the enumerated engines, apart from being defined by its class and instance (see `struct i915_engine_class_instance`), also can have flags and capabilities defined as documented in i915_drm.h.h](hXEach of the enumerated engines, apart from being defined by its class and instance (see }(hj8hhhNhNubjU )}(h#`struct i915_engine_class_instance`h]h!struct i915_engine_class_instance}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj8ubhL), also can have flags and capabilities defined as documented in i915_drm.h.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h{For instance video engines which support HEVC encoding will have the `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.h](hEFor instance video engines which support HEVC encoding will have the }(hj8hhhNhNubjU )}(h"`I915_VIDEO_CLASS_CAPABILITY_HEVC`h]h I915_VIDEO_CLASS_CAPABILITY_HEVC}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jT hj8ubh capability bit set.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hEngine discovery only fully comes to its own when combined with the new way of addressing engines when submitting batch buffers using contexts with engine maps configured.h]hEngine discovery only fully comes to its own when combined with the new way of addressing engines when submitting batch buffers using contexts with engine maps configured.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_engine_info (C struct)c.drm_i915_engine_infohNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_engine_infoh]j)}(hstruct drm_i915_engine_infoh](j)}(hjh]hstruct}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 9hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 9hhhj9hM ubj)}(hdrm_i915_engine_infoh]j)}(hj 9h]hdrm_i915_engine_info}(hj09hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,9ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj 9hhhj9hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj9hhhj9hM ubah}(h]j9ah ](j j eh"]h$]h&]jj)jhuh1jhj9hM hj9hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj9hhhj9hM ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j[9j8j[9j9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; }; **Members** ``engine`` Engine class and instance. ``rsvd0`` Reserved field. ``flags`` Engine flags. ``capabilities`` Capabilities of this engine. ``logical_instance`` Logical instance of engine ``rsvd1`` Reserved fields. ``rsvd2`` Reserved fields.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjg9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjc9ubh:}(hjc9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj_9ubj`)}(hXstruct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; };h]hXstruct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; };}hj9sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj_9ubh)}(h **Members**h]h)}(hj9h]hMembers}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj_9ubh)}(hhh](h)}(h&``engine`` Engine class and instance. h](j)}(h ``engine``h]j)}(hj9h]hengine}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj9ubj)}(hhh]h)}(hEngine class and instance.h]hEngine class and instance.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hM hj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1hhj9hM hj9ubh)}(h``rsvd0`` Reserved field. h](j)}(h ``rsvd0``h]j)}(hj9h]hrsvd0}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj9ubj)}(hhh]h)}(hReserved field.h]hReserved field.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hKhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1hhj9hKhj9ubh)}(h``flags`` Engine flags. h](j)}(h ``flags``h]j)}(hj":h]hflags}(hj$:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj :ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj:ubj)}(hhh]h)}(h Engine flags.h]h Engine flags.}(hj;:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7:hKhj8:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1hhj7:hKhj9ubh)}(h.``capabilities`` Capabilities of this engine. h](j)}(h``capabilities``h]j)}(hj[:h]h capabilities}(hj]:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY:ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjU:ubj)}(hhh]h)}(hCapabilities of this engine.h]hCapabilities of this engine.}(hjt:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp:hKhjq:ubah}(h]h ]h"]h$]h&]uh1jhjU:ubeh}(h]h ]h"]h$]h&]uh1hhjp:hKhj9ubh)}(h0``logical_instance`` Logical instance of engine h](j)}(h``logical_instance``h]j)}(hj:h]hlogical_instance}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj:ubj)}(hhh]h)}(hLogical instance of engineh]hLogical instance of engine}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1hhj:hKhj9ubh)}(h``rsvd1`` Reserved fields. h](j)}(h ``rsvd1``h]j)}(hj:h]hrsvd1}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj:ubj)}(hhh]h)}(hReserved fields.h]hReserved fields.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1hhj:hKhj9ubh)}(h``rsvd2`` Reserved fields.h](j)}(h ``rsvd2``h]j)}(hj;h]hrsvd2}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj;ubj)}(hhh]h)}(hReserved fields.h]hReserved fields.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1hhj;hKhj9ubeh}(h]h ]h"]h$]h&]uh1hhj_9ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjI;h]h Description}(hjK;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjG;ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hADescribes one engine and its capabilities as known to the driver.h]hADescribes one engine and its capabilities as known to the driver.}(hj_;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_i915_query_engine_info (C struct)c.drm_i915_query_engine_infohNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_engine_infoh]j)}(h!struct drm_i915_query_engine_infoh](j)}(hjh]hstruct}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhj;hM ubj)}(hdrm_i915_query_engine_infoh]j)}(hj;h]hdrm_i915_query_engine_info}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj;hhhj;hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj;hhhj;hM ubah}(h]jz;ah ](j j eh"]h$]h&]jj)jhuh1jhj;hM hj|;hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj|;hhhj;hM ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j;j8j;j9j:j;uh1jhhhhhNhNubj=)}(hX;**Definition**:: struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; }; **Members** ``num_engines`` Number of struct drm_i915_engine_info structs following. ``rsvd`` MBZ ``engines`` Marker for drm_i915_engine_info structures.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;ubh:}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM/ hj;ubj`)}(h{struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; };h]h{struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; };}hj;sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM1 hj;ubh)}(h **Members**h]h)}(hj<h]hMembers}(hj <hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7 hj;ubh)}(hhh](h)}(hI``num_engines`` Number of struct drm_i915_engine_info structs following. h](j)}(h``num_engines``h]j)}(hj'<h]h num_engines}(hj)<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%<ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM1 hj!<ubj)}(hhh]h)}(h8Number of struct drm_i915_engine_info structs following.h]h8Number of struct drm_i915_engine_info structs following.}(hj@<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<<hM1 hj=<ubah}(h]h ]h"]h$]h&]uh1jhj!<ubeh}(h]h ]h"]h$]h&]uh1hhj<<hM1 hj<ubh)}(h ``rsvd`` MBZ h](j)}(h``rsvd``h]j)}(hj`<h]hrsvd}(hjb<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^<ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjZ<ubj)}(hhh]h)}(hMBZh]hMBZ}(hjy<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju<hKhjv<ubah}(h]h ]h"]h$]h&]uh1jhjZ<ubeh}(h]h ]h"]h$]h&]uh1hhju<hKhj<ubh)}(h7``engines`` Marker for drm_i915_engine_info structures.h](j)}(h ``engines``h]j)}(hj<h]hengines}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj<ubj)}(hhh]h)}(h+Marker for drm_i915_engine_info structures.h]h+Marker for drm_i915_engine_info structures.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1hhj<hKhj<ubeh}(h]h ]h"]h$]h&]uh1hhj;ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj<h]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(h~Engine info query enumerates all engines known to the driver by filling in an array of struct drm_i915_engine_info structures.h]h~Engine info query enumerates all engines known to the driver by filling in an array of struct drm_i915_engine_info structures.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM, hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_i915_query_perf_config (C struct)c.drm_i915_query_perf_confighNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_perf_configh]j)}(h!struct drm_i915_query_perf_configh](j)}(hjh]hstruct}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2 ubj)}(h h]h }(hj(=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhhj'=hM2 ubj)}(hdrm_i915_query_perf_configh]j)}(hj=h]hdrm_i915_query_perf_config}(hj:=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6=ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj=hhhj'=hM2 ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj=hhhj'=hM2 ubah}(h]j =ah ](j j eh"]h$]h&]jj)jhuh1jhj'=hM2 hj=hhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj=hhhj'=hM2 ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7je=j8je=j9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; }; **Members** ``{unnamed_union}`` anonymous ``n_configs`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available. ``config`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. ``uuid`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. String formatted like "``08x-````04x-````04x-````04x-````012x``" ``flags`` Unused for now. Must be cleared to zero. ``data`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers. When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created : - :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjq=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjm=ubh:}(hjm=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM@ hji=ubj`)}(hstruct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; };h]hstruct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; };}hj=sbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMB hji=ubh)}(h **Members**h]h)}(hj=h]hMembers}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhML hji=ubh)}(hhh](h)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hj=h]h{unnamed_union}}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj=ubj)}(hhh]h)}(h anonymoush]h anonymous}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1hhj=hKhj=ubh)}(h``n_configs`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available. h](j)}(h ``n_configs``h]j)}(hj=h]h n_configs}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMG hj=ubj)}(hhh]h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available.h](hWhen }(hj >hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj>h]hdrm_i915_query_item.flags}(hj>hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhME hj >ubh == }(hj >hhhNhNubj)}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hj8>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj >ubhB, i915 sets this fields to the number of configurations available.}(hj >hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj3>hME hj >ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1hhj>hMG hj=ubh)}(h``config`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. h](j)}(h ``config``h]j)}(hjb>h]hconfig}(hjd>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`>ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMQ hj\>ubj)}(hhh]h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.h](hWhen }(hj{>hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj>h]hdrm_i915_query_item.flags}(hj>hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMN hj{>ubh == }(hj{>hhhNhNubj)}(h*``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``h]h&DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{>ubhq, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.}(hj{>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj>hMN hjx>ubah}(h]h ]h"]h$]h&]uh1jhj\>ubeh}(h]h ]h"]h$]h&]uh1hhjw>hMQ hj=ubh)}(hX+``uuid`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. String formatted like "``08x-````04x-````04x-````04x-````012x``" h](j)}(h``uuid``h]j)}(hj>h]huuid}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM] hj>ubj)}(hhh](h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.h](hWhen }(hj>hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj>h]hdrm_i915_query_item.flags}(hj>hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMX hj>ubh == }(hj>hhhNhNubj)}(h,``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``h]h(DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubhq, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj?hMX hj>ubh)}(h@String formatted like "``08x-````04x-````04x-````04x-````012x``"h](hString formatted like “}(hj.?hhhNhNubj)}(h(``08x-````04x-````04x-````04x-````012x``h]h$08x-````04x-````04x-````04x-````012x}(hj6?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.?ubh”}(hj.?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj>hM] hj>ubeh}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1hhj>hM] hj=ubh)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]j)}(hj`?h]hflags}(hjb?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^?ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMe hjZ?ubj)}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hjy?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju?hMe hjv?ubah}(h]h ]h"]h$]h&]uh1jhjZ?ubeh}(h]h ]h"]h$]h&]uh1hhju?hMe hj=ubh)}(hX``data`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers. When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created : - :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h](j)}(h``data``h]j)}(hj?h]hdata}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMv hj?ubj)}(hhh](h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers.h](hWhen }(hj?hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj?h]hdrm_i915_query_item.flags}(hj?hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMl hj?ubh == }(hj?hhhNhNubj)}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubhA, i915 will write an array of __u64 of configuration identifiers.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj?hMl hj?ubh)}(hXNWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created :h](hWhen }(hj?hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj@h]hdrm_i915_query_item.flags}(hj@hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMo hj?ubh == }(hj?hhhNhNubj)}(h#``DRM_I915_QUERY_PERF_CONFIG_DATA``h]hDRM_I915_QUERY_PERF_CONFIG_DATA}(hj"@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created :}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj@hMo hj?ubj)}(h- :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h]jp )}(hhh](ju )}(hF:c:type:`drm_i915_perf_oa_config.n_mux_regs `h]h)}(hjC@h]h)}(hjC@h]j)}(hjC@h]h"drm_i915_perf_oa_config.n_mux_regs}(hjK@hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjH@ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_perf_oa_configuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMu hjE@ubah}(h]h ]h"]h$]h&]uh1hhjf@hMu hjA@ubah}(h]h ]h"]h$]h&]uh1jt hj>@ubju )}(hJ:c:type:`drm_i915_perf_oa_config.n_boolean_regs `h]h)}(hju@h]h)}(hju@h]j)}(hju@h]h&drm_i915_perf_oa_config.n_boolean_regs}(hj}@hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjz@ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_perf_oa_configuh1hhj?hMv hjw@ubah}(h]h ]h"]h$]h&]uh1hhj?hMv hjs@ubah}(h]h ]h"]h$]h&]uh1jt hj>@ubju )}(hG:c:type:`drm_i915_perf_oa_config.n_flex_regs `h]h)}(hj@h]h)}(hj@h]j)}(hj@h]h#drm_i915_perf_oa_config.n_flex_regs}(hj@hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_perf_oa_configuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMw hj@ubah}(h]h ]h"]h$]h&]uh1hhj@hMw hj@ubah}(h]h ]h"]h$]h&]uh1jt hj>@ubeh}(h]h ]h"]h$]h&]j j uh1jo hjf@hMu hj:@ubah}(h]h ]h"]h$]h&]uh1jhjf@hMu hj?ubeh}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1hhj?hMv hj=ubeh}(h]h ]h"]h$]h&]uh1hhji=ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hj@h]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMz hhhhubh)}(hoData written by the kernel with query ``DRM_I915_QUERY_PERF_CONFIG`` and ``DRM_I915_QUERY_GEOMETRY_SUBSLICES``.h](h&Data written by the kernel with query }(hjAhhhNhNubj)}(h``DRM_I915_QUERY_PERF_CONFIG``h]hDRM_I915_QUERY_PERF_CONFIG}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh and }(hjAhhhNhNubj)}(h%``DRM_I915_QUERY_GEOMETRY_SUBSLICES``h]h!DRM_I915_QUERY_GEOMETRY_SUBSLICES}(hj-AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh.}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM= hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_memory_class (C enum)c.drm_i915_gem_memory_classhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_memory_classh]j)}(henum drm_i915_gem_memory_classh](j)}(hj?h]henum}(hj_AhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[AhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMC ubj)}(h h]h }(hjmAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[AhhhjlAhMC ubj)}(hdrm_i915_gem_memory_classh]j)}(hjYAh]hdrm_i915_gem_memory_class}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{Aubah}(h]h ](jjeh"]h$]h&]jjuh1jhj[AhhhjlAhMC ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjWAhhhjlAhMC ubah}(h]jRAah ](j j eh"]h$]h&]jj)jhuh1jhjlAhMC hjTAhhubj)}(hhh]h)}(hSupported memory classesh]hSupported memory classes}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM~ hjAhhubah}(h]h ]h"]h$]h&]uh1jhjTAhhhjlAhMC ubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jAj8jAj9j:j;uh1jhhhhhNhNubj=)}(ho**Constants** ``I915_MEMORY_CLASS_SYSTEM`` System memory ``I915_MEMORY_CLASS_DEVICE`` Device local-memoryh](h)}(h **Constants**h]h)}(hjAh]h Constants}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjAubh)}(hhh](h)}(h+``I915_MEMORY_CLASS_SYSTEM`` System memory h](j)}(h``I915_MEMORY_CLASS_SYSTEM``h]j)}(hjAh]hI915_MEMORY_CLASS_SYSTEM}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjAubj)}(hhh]h)}(h System memoryh]h System memory}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhM hjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1hhjAhM hjAubh)}(h0``I915_MEMORY_CLASS_DEVICE`` Device local-memoryh](j)}(h``I915_MEMORY_CLASS_DEVICE``h]j)}(hjBh]hI915_MEMORY_CLASS_DEVICE}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBubj)}(hhh]h)}(hDevice local-memoryh]hDevice local-memory}(hj4BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj1Bubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1hhj0BhM hjAubeh}(h]h ]h"]h$]h&]uh1hhjAubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j-drm_i915_gem_memory_class_instance (C struct)$c.drm_i915_gem_memory_class_instancehNtauh1jhhhhhNhNubj)}(hhh](j)}(h"drm_i915_gem_memory_class_instanceh]j)}(h)struct drm_i915_gem_memory_class_instanceh](j)}(hjh]hstruct}(hjuBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqBhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqBhhhjBhM ubj)}(h"drm_i915_gem_memory_class_instanceh]j)}(hjoBh]h"drm_i915_gem_memory_class_instance}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ](jjeh"]h$]h&]jjuh1jhjqBhhhjBhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjmBhhhjBhM ubah}(h]jhBah ](j j eh"]h$]h&]jj)jhuh1jhjBhM hjjBhhubj)}(hhh]h)}(h!Identify particular memory regionh]h!Identify particular memory region}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBhhubah}(h]h ]h"]h$]h&]uh1jhjjBhhhjBhM ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jBj8jBj9j:j;uh1jhhhhhNhNubj=)}(h**Definition**:: struct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; }; **Members** ``memory_class`` See enum drm_i915_gem_memory_class ``memory_instance`` Which instanceh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBubh:}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBubj`)}(hastruct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; };h]hastruct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; };}hjBsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBubh)}(h **Members**h]h)}(hjCh]hMembers}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBubh)}(hhh](h)}(h4``memory_class`` See enum drm_i915_gem_memory_class h](j)}(h``memory_class``h]j)}(hj$Ch]h memory_class}(hj&ChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"Cubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjCubj)}(hhh]h)}(h"See enum drm_i915_gem_memory_classh]h"See enum drm_i915_gem_memory_class}(hj=ChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9ChM hj:Cubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1hhj9ChM hjCubh)}(h"``memory_instance`` Which instanceh](j)}(h``memory_instance``h]j)}(hj]Ch]hmemory_instance}(hj_ChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[Cubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjWCubj)}(hhh]h)}(hWhich instanceh]hWhich instance}(hjvChhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjsCubah}(h]h ]h"]h$]h&]uh1jhjWCubeh}(h]h ]h"]h$]h&]uh1hhjrChKhjCubeh}(h]h ]h"]h$]h&]uh1hhjBubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&drm_i915_memory_region_info (C struct)c.drm_i915_memory_region_infohNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_memory_region_infoh]j)}(h"struct drm_i915_memory_region_infoh](j)}(hjh]hstruct}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjChhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjChhhjChKubj)}(hdrm_i915_memory_region_infoh]j)}(hjCh]hdrm_i915_memory_region_info}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ](jjeh"]h$]h&]jjuh1jhjChhhjChKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjChhhjChKubah}(h]jCah ](j j eh"]h$]h&]jj)jhuh1jhjChKhjChhubj)}(hhh]h)}(h,Describes one region as known to the driver.h]h,Describes one region as known to the driver.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjChhubah}(h]h ]h"]h$]h&]uh1jhjChhhjChKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jDj8jDj9j:j;uh1jhhhhhNhNubj=)}(hX **Definition**:: struct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; }; **Members** ``region`` The class:instance pair encoding ``rsvd0`` MBZ ``probed_size`` Memory probed by the driver Note that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields. ``unallocated_size`` Estimate of memory remaining Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the **probed_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). ``{unnamed_union}`` anonymous ``rsvd1`` MBZ ``{unnamed_struct}`` anonymous ``probed_cpu_visible_size`` Memory probed by the driver that is CPU accessible. This will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible. On systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). Note that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**. ``unallocated_cpu_visible_size`` Estimate of CPU visible memory remaining. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**). Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**). If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDubh:}(hjDhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjDubj`)}(hXCstruct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; };h]hXCstruct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; };}hj6Dsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjDubh)}(h **Members**h]h)}(hjGDh]hMembers}(hjIDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEDubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjDubh)}(hhh](h)}(h,``region`` The class:instance pair encoding h](j)}(h ``region``h]j)}(hjfDh]hregion}(hjhDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdDubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj`Dubj)}(hhh]h)}(h The class:instance pair encodingh]h The class:instance pair encoding}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{DhM hj|Dubah}(h]h ]h"]h$]h&]uh1jhj`Dubeh}(h]h ]h"]h$]h&]uh1hhj{DhM hj]Dubh)}(h``rsvd0`` MBZ h](j)}(h ``rsvd0``h]j)}(hjDh]hrsvd0}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjDubj)}(hhh]h)}(hMBZh]hMBZ}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhKhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1hhjDhKhj]Dubh)}(hX ``probed_size`` Memory probed by the driver Note that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields. h](j)}(h``probed_size``h]j)}(hjDh]h probed_size}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjDubj)}(hhh](h)}(hMemory probed by the driverh]hMemory probed by the driver}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjDubh)}(hNote that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields.h]hNote that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjDubeh}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1hhjDhM hj]Dubh)}(hXi``unallocated_size`` Estimate of memory remaining Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the **probed_size**. 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Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hjIEhhhNhNubh)}(h**probed_size**h]h probed_size}(hjcEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIEubh).}(hjIEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7Eubeh}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1hhj6EhM hj]Dubh)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjEh]h{unnamed_union}}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjEubj)}(hhh]h)}(h anonymoush]h anonymous}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhKhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1hhjEhKhj]Dubh)}(h``rsvd1`` MBZ h](j)}(h ``rsvd1``h]j)}(hjEh]hrsvd1}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjEubj)}(hhh]h)}(hMBZh]hMBZ}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhKhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1hhjEhKhj]Dubh)}(h``{unnamed_struct}`` anonymous h](j)}(h``{unnamed_struct}``h]j)}(hjFh]h{unnamed_struct}}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjEubj)}(hhh]h)}(h anonymoush]h anonymous}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhKhjFubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1hhjFhKhj]Dubh)}(hXs``probed_cpu_visible_size`` Memory probed by the driver that is CPU accessible. This will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible. On systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). Note that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**. h](j)}(h``probed_cpu_visible_size``h]j)}(hj9Fh]hprobed_cpu_visible_size}(hj;FhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7Fubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj3Fubj)}(hhh](h)}(h3Memory probed by the driver that is CPU accessible.h]h3Memory probed by the driver that is CPU accessible.}(hjRFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjOFubh)}(hjThis will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible.h](hThis will be always be <= }(hjaFhhhNhNubh)}(h**probed_size**h]h probed_size}(hjiFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaFubhA, and the remainder (if there is any) will not be CPU accessible.}(hjaFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjOFubh)}(hOn systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible.h](h"On systems without small BAR, the }(hjFhhhNhNubh)}(h**probed_size**h]h probed_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh will always equal the }(hjFhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh), since all of it will be CPU accessible.}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjOFubh)}(hNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**).h](huNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hjFhhhNhNubh)}(h**probed_size**h]h probed_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh).}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjOFubh)}(hXNote that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**.h](hXpNote that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when }(hjFhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh == }(hjFhhhNhNubh)}(h**probed_size**h]h probed_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh.}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjOFubeh}(h]h ]h"]h$]h&]uh1jhj3Fubeh}(h]h ]h"]h$]h&]uh1hhjNFhM hj]Dubh)}(hXr``unallocated_cpu_visible_size`` Estimate of CPU visible memory remaining. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**). Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**). If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](j)}(h ``unallocated_cpu_visible_size``h]j)}(hjGh]hunallocated_cpu_visible_size}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjGubj)}(hhh](h)}(h)Estimate of CPU visible memory remaining.h]h)Estimate of CPU visible memory remaining.}(hj4GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj1Gubh)}(hNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**).h](huNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hjCGhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjKGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCGubh).}(hjCGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj1Gubh)}(hX3Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**).h](huRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the }(hjdGhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjlGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdGubh. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the }(hjdGhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hj~GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdGubh).}(hjdGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj1Gubh)}(h]If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](hAIf this is an older kernel the value here will be zero, see also }(hjGhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj0GhM hj1Gubeh}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1hhj0GhM hj]Dubeh}(h]h ]h"]h$]h&]uh1hhjDubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjGh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hNote this is using both struct drm_i915_query_item and struct drm_i915_query. For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS at :c:type:`drm_i915_query_item.query_id `.h](hNote this is using both struct drm_i915_query_item and struct drm_i915_query. For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS at }(hjGhhhNhNubh)}(h<:c:type:`drm_i915_query_item.query_id `h]j)}(hjGh]hdrm_i915_query_item.query_id}(hjGhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjGubh.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjHhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(drm_i915_query_memory_regions (C struct)c.drm_i915_query_memory_regionshNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_memory_regionsh]j)}(h$struct drm_i915_query_memory_regionsh](j)}(hjh]hstruct}(hj3HhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/HhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjAHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/Hhhhj@HhM ubj)}(hdrm_i915_query_memory_regionsh]j)}(hj-Hh]hdrm_i915_query_memory_regions}(hjSHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOHubah}(h]h ](jjeh"]h$]h&]jjuh1jhj/Hhhhj@HhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj+Hhhhj@HhM ubah}(h]j&Hah ](j j eh"]h$]h&]jj)jhuh1jihj@HhM hj(Hhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj(Hhhhj@HhM ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j~Hj8j~Hj9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_query_memory_regions { __u32 num_regions; __u32 rsvd[3]; struct drm_i915_memory_region_info regions[]; }; **Members** ``num_regions`` Number of supported regions ``rsvd`` MBZ ``regions`` Info about each supported regionh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHubh:}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjHubj`)}(hstruct drm_i915_query_memory_regions { __u32 num_regions; __u32 rsvd[3]; struct drm_i915_memory_region_info regions[]; };h]hstruct drm_i915_query_memory_regions { __u32 num_regions; __u32 rsvd[3]; struct drm_i915_memory_region_info regions[]; };}hjHsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjHubh)}(h **Members**h]h)}(hjHh]hMembers}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjHubh)}(hhh](h)}(h,``num_regions`` Number of supported regions h](j)}(h``num_regions``h]j)}(hjHh]h num_regions}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjHubj)}(hhh]h)}(hNumber of supported regionsh]hNumber of supported regions}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMhjHubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1hhjHhMhjHubh)}(h ``rsvd`` MBZ h](j)}(h``rsvd``h]j)}(hj Ih]hrsvd}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Iubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjIubj)}(hhh]h)}(hMBZh]hMBZ}(hj%IhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!IhKhj"Iubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1hhj!IhKhjHubh)}(h,``regions`` Info about each supported regionh](j)}(h ``regions``h]j)}(hjEIh]hregions}(hjGIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCIubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj?Iubj)}(hhh]h)}(h Info about each supported regionh]h Info about each supported region}(hj^IhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj[Iubah}(h]h ]h"]h$]h&]uh1jhj?Iubeh}(h]h ]h"]h$]h&]uh1hhjZIhKhjHubeh}(h]h ]h"]h$]h&]uh1hhjHubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjIh]h Description}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hThe region info query enumerates all regions known to the driver by filling in an array of struct drm_i915_memory_region_info structures.h]hThe region info query enumerates all regions known to the driver by filling in an array of struct drm_i915_memory_region_info structures.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h2Example for getting the list of supported regions:h]h2Example for getting the list of supported regions:}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj`)}(hXVstruct drm_i915_query_memory_regions *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_MEMORY_REGIONS; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of regions. The kernel will fill out the // item.length for us, which is the number of bytes we need. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with the all the region info. item.data_ptr = (uintptr_t)&info, err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each region in the array for (i = 0; i < info->num_regions; i++) { struct drm_i915_memory_region_info mr = info->regions[i]; u16 class = mr.region.class; u16 instance = mr.region.instance; .... } free(info);h]hXVstruct drm_i915_query_memory_regions *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_MEMORY_REGIONS; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of regions. The kernel will fill out the // item.length for us, which is the number of bytes we need. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with the all the region info. item.data_ptr = (uintptr_t)&info, err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each region in the array for (i = 0; i < info->num_regions; i++) { struct drm_i915_memory_region_info mr = info->regions[i]; u16 class = mr.region.class; u16 instance = mr.region.instance; .... } free(info);}hjIsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j0drm_i915_query_guc_submission_version (C struct)'c.drm_i915_query_guc_submission_versionhNtauh1jhhhhhNhNubj)}(hhh](j)}(h%drm_i915_query_guc_submission_versionh]j)}(h,struct drm_i915_query_guc_submission_versionh](j)}(hjh]hstruct}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhhjIhMubj)}(h%drm_i915_query_guc_submission_versionh]j)}(hjIh]h%drm_i915_query_guc_submission_version}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubah}(h]h ](jjeh"]h$]h&]jjuh1jhjIhhhjIhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjIhhhjIhMubah}(h]jIah ](j j eh"]h$]h&]jj)jhuh1jhjIhMhjIhhubj)}(hhh]h)}(h&query GuC submission interface versionh]h&query GuC submission interface version}(hj'JhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM(hj$Jhhubah}(h]h ]h"]h$]h&]uh1jhjIhhhjIhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j?Jj8j?Jj9j:j;uh1jhhhhhNhNubj=)}(hX7**Definition**:: struct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; }; **Members** ``branch`` Firmware branch version. ``major`` Firmware major version. ``minor`` Firmware minor version. ``patch`` Firmware patch version.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjKJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGJubh:}(hjGJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM,hjCJubj`)}(hvstruct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; };h]hvstruct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; };}hjdJsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM.hjCJubh)}(h **Members**h]h)}(hjuJh]hMembers}(hjwJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjsJubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5hjCJubh)}(hhh](h)}(h$``branch`` Firmware branch version. h](j)}(h ``branch``h]j)}(hjJh]hbranch}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM+hjJubj)}(hhh]h)}(hFirmware branch version.h]hFirmware branch version.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhM+hjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1hhjJhM+hjJubh)}(h"``major`` Firmware major version. h](j)}(h ``major``h]j)}(hjJh]hmajor}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjJubj)}(hhh]h)}(hFirmware major version.h]hFirmware major version.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhKhjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1hhjJhKhjJubh)}(h"``minor`` Firmware minor version. h](j)}(h ``minor``h]j)}(hjKh]hminor}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjKubj)}(hhh]h)}(hFirmware minor version.h]hFirmware minor version.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhKhjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1hhjKhKhjJubh)}(h!``patch`` Firmware patch version.h](j)}(h ``patch``h]j)}(hj?Kh]hpatch}(hjAKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=Kubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj9Kubj)}(hhh]h)}(hFirmware patch version.h]hFirmware patch version.}(hjXKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjUKubah}(h]h ]h"]h$]h&]uh1jhj9Kubeh}(h]h ]h"]h$]h&]uh1hhjTKhKhjJubeh}(h]h ]h"]h$]h&]uh1hhjCJubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h.. _GuC HWCONFIG blob uAPI:h]h}(h]h ]h"]h$]h&]hԌguc-hwconfig-blob-uapiuh1hhMmhhhhhNubh)}(h**GuC HWCONFIG blob uAPI**h]h)}(hjKh]hGuC HWCONFIG blob uAPI}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKubah}(h]jKah ]h"]guc hwconfig blob uapiah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhh}jKjKsh}jKjKsubh)}(hThe GuC produces a blob with information about the current device. i915 reads this blob from GuC and makes it available via this uAPI.h]hThe GuC produces a blob with information about the current device. i915 reads this blob from GuC and makes it available via this uAPI.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM6hhhhubh)}(h_The format and meaning of the blob content are documented in the Programmer's Reference Manual.h]haThe format and meaning of the blob content are documented in the Programmer’s Reference Manual.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM9hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_create_ext (C struct)c.drm_i915_gem_create_exthNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_create_exth]j)}(hstruct drm_i915_gem_create_exth](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM?ubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKhhhjKhM?ubj)}(hdrm_i915_gem_create_exth]j)}(hjKh]hdrm_i915_gem_create_ext}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubah}(h]h ](jjeh"]h$]h&]jjuh1jhjKhhhjKhM?ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjKhhhjKhM?ubah}(h]jKah ](j j eh"]h$]h&]jj)jhuh1jhjKhM?hjKhhubj)}(hhh]h)}(h]Existing gem_create behaviour, with added extension support using struct i915_user_extension.h]h]Existing gem_create behaviour, with added extension support using struct i915_user_extension.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM@hjLhhubah}(h]h ]h"]h$]h&]uh1jhjKhhhjKhM?ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j7Lj8j7Lj9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; }; **Members** ``size`` Requested size for the object. The (page-aligned) allocated size for the object will be returned. On platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects. NOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications: 1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. However on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K. ``handle`` Returned handle for the object. Object handles are nonzero. ``flags`` Optional flags. Supported values: I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU. Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size ` for how to determine if this system applies. Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE. Also note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS. Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided. On older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed. ``extensions`` The chain of extensions to apply to this object. This will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension. If we don't supply any extensions then we get the same old gem_create behaviour. For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions. For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content. For I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjCLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?Lubh:}(hj?LhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMDhj;Lubj`)}(hX.struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; };h]hX.struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; };}hj\Lsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMFhj;Lubh)}(h **Members**h]h)}(hjmLh]hMembers}(hjoLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkLubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMQhj;Lubh)}(hhh](h)}(hX``size`` Requested size for the object. The (page-aligned) allocated size for the object will be returned. On platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects. NOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications: 1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. However on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K. h](j)}(h``size``h]j)}(hjLh]hsize}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMbhjLubj)}(hhh](h)}(hRequested size for the object.h]hRequested size for the object.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMLhjLubh)}(hBThe (page-aligned) allocated size for the object will be returned.h]hBThe (page-aligned) allocated size for the object will be returned.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMNhjLubh)}(hOn platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects.h]hOn platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMPhjLubh)}(hNOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications:h]hNOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications:}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMThjLubj)}(h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. h](h)}(h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware.h]h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMXhjLubh)}(hI2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects.h]hI2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM\hjLubeh}(h]h ]h"]h$]h&]uh1jhjLhMXhjLubh)}(hHowever on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K.h]hHowever on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K.}(hj MhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM_hjLubeh}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1hhjLhMbhjLubh)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]j)}(hj*Mh]hhandle}(hj,MhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(Mubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMihj$Mubj)}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hjCMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMghj@Mubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hjRMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?MhMihj@Mubeh}(h]h ]h"]h$]h&]uh1jhj$Mubeh}(h]h ]h"]h$]h&]uh1hhj?MhMihjLubh)}(hX``flags`` Optional flags. Supported values: I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU. Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size ` for how to determine if this system applies. Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE. Also note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS. Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided. On older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed. h](j)}(h ``flags``h]j)}(hjrMh]hflags}(hjtMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpMubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjlMubj)}(hhh](h)}(hOptional flags.h]hOptional flags.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMnhjMubh)}(hSupported values:h]hSupported values:}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMphjMubh)}(hvI915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU.h]hvI915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMrhjMubh)}(hXOnly valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size ` for how to determine if this system applies.h](hXOnly valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it’s something we can expect to see in the wild. See }(hjMhhhNhNubh)}(h[:c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `h]j)}(hjMh]h3drm_i915_memory_region_info.probed_cpu_visible_size}(hjMhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_memory_region_infouh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMuhjMubh- for how to determine if this system applies.}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjMhMuhjMubh)}(hNote that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE.h]hNote that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can’t be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM~hjMubh)}(hAlso note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS.h](hKAlso note that since the kernel only supports flat-CCS on objects that can }(hjMhhhNhNubhemphasis)}(h*only*h]honly}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jNhjMubh be placed in I915_MEMORY_CLASS_DEVICE, we therefore don’t support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS.}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjMubh)}(hX5Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided.h]hX5Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjMubh)}(hXOn older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed.h](hJOn older kernels which lack the relevant small-bar uAPI support (see also }(hj+NhhhNhNubh)}(h[:c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `h]j)}(hj5Nh]h3drm_i915_memory_region_info.probed_cpu_visible_size}(hj7NhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj3Nubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_memory_region_infouh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj+NubhXR), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed.}(hj+NhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjRNhMhjMubeh}(h]h ]h"]h$]h&]uh1jhjlMubeh}(h]h ]h"]h$]h&]uh1hhjMhMhjLubh)}(hXb``extensions`` The chain of extensions to apply to this object. This will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension. If we don't supply any extensions then we get the same old gem_create behaviour. For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions. For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content. For I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h](j)}(h``extensions``h]j)}(hjoNh]h extensions}(hjqNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmNubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjiNubj)}(hhh](h)}(h0The chain of extensions to apply to this object.h]h0The chain of extensions to apply to this object.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(hThis will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension.h]hThis will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(hPIf we don't supply any extensions then we get the same old gem_create behaviour.h]hRIf we don’t supply any extensions then we get the same old gem_create behaviour.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(h_For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions.h]h_For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(heFor I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content.h]heFor I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(hQFor I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h]hQFor I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhMhjNubeh}(h]h ]h"]h$]h&]uh1jhjiNubeh}(h]h ]h"]h$]h&]uh1hhjNhMhjLubeh}(h]h ]h"]h$]h&]uh1hhj;Lubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjNh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXcNote that new buffer flags should be added here, at least for the stuff that is immutable. Previously we would have two ioctls, one to create the object with gem_create, and another to apply various parameters, however this creates some ambiguity for the params which are considered immutable. Also in general we're phasing out the various SET/GET ioctls.h]hXeNote that new buffer flags should be added here, at least for the stuff that is immutable. Previously we would have two ioctls, one to create the object with gem_create, and another to apply various parameters, however this creates some ambiguity for the params which are considered immutable. Also in general we’re phasing out the various SET/GET ioctls.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMAhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j1drm_i915_gem_create_ext_memory_regions (C struct)(c.drm_i915_gem_create_ext_memory_regionshNtauh1jhhhhhNhNubj)}(hhh](j)}(h&drm_i915_gem_create_ext_memory_regionsh]j)}(h-struct drm_i915_gem_create_ext_memory_regionsh](j)}(hjh]hstruct}(hj:OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6OhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMJubj)}(h h]h }(hjHOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6OhhhjGOhMJubj)}(h&drm_i915_gem_create_ext_memory_regionsh]j)}(hj4Oh]h&drm_i915_gem_create_ext_memory_regions}(hjZOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVOubah}(h]h ](jjeh"]h$]h&]jjuh1jhj6OhhhjGOhMJubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj2OhhhjGOhMJubah}(h]j-Oah ](j j eh"]h$]h&]jj)jhuh1jhjGOhMJhj/Ohhubj)}(hhh]h)}(h1The I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.h]h1The I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.}(hj|OhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjyOhhubah}(h]h ]h"]h$]h&]uh1jhj/OhhhjGOhMJubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jOj8jOj9j:j;uh1jhhhhhNhNubj=)}(hX**Definition**:: struct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``pad`` MBZ ``num_regions`` Number of elements in the **regions** array. ``regions`` The regions/placements array. An array of struct drm_i915_gem_memory_class_instance.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubh:}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOubj`)}(hstruct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; };h]hstruct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; };}hjOsbah}(h]h ]h"]h$]h&]jjuh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOubh)}(h **Members**h]h)}(hjOh]hMembers}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOubh)}(hhh](h)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]j)}(hjOh]hbase}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOubj)}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhMhjOubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1hhjOhMhjOubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj"Ph]hpad}(hj$PhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Pubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjPubj)}(hhh]h)}(hMBZh]hMBZ}(hj;PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7PhKhj8Pubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1hhj7PhKhjOubh)}(h=``num_regions`` Number of elements in the **regions** array. h](j)}(h``num_regions``h]j)}(hj[Ph]h num_regions}(hj]PhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYPubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjUPubj)}(hhh]h)}(h,Number of elements in the **regions** array.h](hNumber of elements in the }(hjtPhhhNhNubh)}(h **regions**h]hregions}(hj|PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjtPubh array.}(hjtPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjpPhKhjqPubah}(h]h ]h"]h$]h&]uh1jhjUPubeh}(h]h ]h"]h$]h&]uh1hhjpPhKhjOubh)}(ha``regions`` The regions/placements array. An array of struct drm_i915_gem_memory_class_instance.h](j)}(h ``regions``h]j)}(hjPh]hregions}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjPubj)}(hhh](h)}(hThe regions/placements array.h]hThe regions/placements array.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjPubh)}(h6An array of struct drm_i915_gem_memory_class_instance.h]h6An array of struct drm_i915_gem_memory_class_instance.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjPubeh}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1hhjPhMhjOubeh}(h]h ]h"]h$]h&]uh1hhjOubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hhhhhNhNubh)}(h**Description**h]h)}(hjPh]h Description}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hSet the object with the desired set of placements/regions in priority order. Each entry must be unique and supported by the device.h]hSet the object with the desired set of placements/regions in priority order. Each entry must be unique and supported by the device.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXThis is provided as an array of struct drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance pair encodings. See struct drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to query the supported regions for a device.h]hXThis is provided as an array of struct drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance pair encodings. See struct drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to query the supported regions for a device.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(htAs an example, on discrete devices, if we wish to set the placement as device local-memory we can do something like:h]htAs an example, on discrete devices, if we wish to set the placement as device local-memory we can do something like:}(hj,QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubj`)}(hXstruct drm_i915_gem_memory_class_instance region_lmem = { .memory_class = I915_MEMORY_CLASS_DEVICE, .memory_instance = 0, }; struct drm_i915_gem_create_ext_memory_regions regions = { .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, .regions = (uintptr_t)®ion_lmem, .num_regions = 1, }; struct drm_i915_gem_create_ext create_ext = { .size = 16 * PAGE_SIZE, .extensions = (uintptr_t)®ions, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...h]hXstruct drm_i915_gem_memory_class_instance region_lmem = { .memory_class = I915_MEMORY_CLASS_DEVICE, .memory_instance = 0, }; struct drm_i915_gem_create_ext_memory_regions regions = { .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, .regions = (uintptr_t)®ion_lmem, .num_regions = 1, }; struct drm_i915_gem_create_ext create_ext = { .size = 16 * PAGE_SIZE, .extensions = (uintptr_t)®ions, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...}hj;Qsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hX At which point we get the object handle in :c:type:`drm_i915_gem_create_ext.handle `, along with the final object size in :c:type:`drm_i915_gem_create_ext.size `, which should account for any rounding up, if required.h](h+At which point we get the object handle in }(hjKQhhhNhNubh)}(hB:c:type:`drm_i915_gem_create_ext.handle `h]j)}(hjUQh]hdrm_i915_gem_create_ext.handle}(hjWQhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjSQubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_gem_create_extuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjKQubh&, along with the final object size in }(hjKQhhhNhNubh)}(h@:c:type:`drm_i915_gem_create_ext.size `h]j)}(hjyQh]hdrm_i915_gem_create_ext.size}(hj{QhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjwQubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_i915_gem_create_extuh1hhjrQhMhjKQubh8, which should account for any rounding up, if required.}(hjKQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjrQhMhhhhubh)}(hX4Note that userspace has no means of knowing the current backing region for objects where **num_regions** is larger than one. The kernel will only ensure that the priority order of the **regions** array is honoured, either when initially placing the object, or when moving memory around due to memory pressureh](hYNote that userspace has no means of knowing the current backing region for objects where }(hjQhhhNhNubh)}(h**num_regions**h]h num_regions}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQubhP is larger than one. The kernel will only ensure that the priority order of the }(hjQhhhNhNubh)}(h **regions**h]hregions}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQubhq array is honoured, either when initially placing the object, or when moving memory around due to memory pressure}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXOn Flat-CCS capable HW, compression is supported for the objects residing in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other memory class in **regions** and migrated (by i915, due to memory constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to decompress the content. But i915 doesn't have the required information to decompress the userspace compressed objects.h](hOn Flat-CCS capable HW, compression is supported for the objects residing in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other memory class in }(hjQhhhNhNubh)}(h **regions**h]hregions}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQubh and migrated (by i915, due to memory constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to decompress the content. But i915 doesn’t have the required information to decompress the userspace compressed objects.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hdSo i915 supports Flat-CCS, on the objects which can reside only on I915_MEMORY_CLASS_DEVICE regions.h]hdSo i915 supports Flat-CCS, on the objects which can reside only on I915_MEMORY_CLASS_DEVICE regions.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j4drm_i915_gem_create_ext_protected_content (C struct)+c.drm_i915_gem_create_ext_protected_contenthNtauh1jhhhhhNhNubj)}(hhh](j)}(h)drm_i915_gem_create_ext_protected_contenth]j)}(h0struct drm_i915_gem_create_ext_protected_contenth](j)}(hjh]hstruct}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hj*RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRhhhj)RhMubj)}(h)drm_i915_gem_create_ext_protected_contenth]j)}(hjRh]h)drm_i915_gem_create_ext_protected_content}(hj]h]hop_ptr}(hj@]hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj<]ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j op_ptruh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhj4]ubh field.}(hj4]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj[]hMhjUhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_nouveau_vm_bind (C struct)c.drm_nouveau_vm_bindhNtauh1jhjUhhhNhNubj)}(hhh](j)}(hdrm_nouveau_vm_bindh]j)}(hstruct drm_nouveau_vm_bindh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{]hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{]hhhj]hMubj)}(hdrm_nouveau_vm_bindh]j)}(hjy]h]hdrm_nouveau_vm_bind}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj{]hhhj]hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjw]hhhj]hMubah}(h]jr]ah ](j j eh"]h$]h&]jj)jhuh1jhj]hMhjt]hhubj)}(hhh]h)}(h'structure for DRM_IOCTL_NOUVEAU_VM_BINDh]h'structure for DRM_IOCTL_NOUVEAU_VM_BIND}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMPhj]hhubah}(h]h ]h"]h$]h&]uh1jhjt]hhhj]hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j]j8j]j9j:j;uh1jhhhjUhNhNubj=)}(hX***Definition**:: struct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; }; **Members** ``op_count`` the number of :c:type:`drm_nouveau_vm_bind_op` ``flags`` the flags for a :c:type:`drm_nouveau_vm_bind` ioctl Supported values: ``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel. If this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects. ``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` ``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished ``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for ``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished ``op_ptr`` pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]ubh:}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMThj]ubj`)}(hstruct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; };h]hstruct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; };}hj]sbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMVhj]ubh)}(h **Members**h]h)}(hj^h]hMembers}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ^ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMahj]ubh)}(hhh](h)}(h<``op_count`` the number of :c:type:`drm_nouveau_vm_bind_op` h](j)}(h ``op_count``h]j)}(hj.^h]hop_count}(hj0^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMUhj(^ubj)}(hhh]h)}(h.the number of :c:type:`drm_nouveau_vm_bind_op`h](hthe number of }(hjG^hhhNhNubh)}(h :c:type:`drm_nouveau_vm_bind_op`h]j)}(hjQ^h]hdrm_nouveau_vm_bind_op}(hjS^hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjO^ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_vm_bind_opuh1hhjC^hMUhjG^ubeh}(h]h ]h"]h$]h&]uh1hhjC^hMUhjD^ubah}(h]h ]h"]h$]h&]uh1jhj(^ubeh}(h]h ]h"]h$]h&]uh1hhjC^hMUhj%^ubh)}(hXg``flags`` the flags for a :c:type:`drm_nouveau_vm_bind` ioctl Supported values: ``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel. If this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects. h](j)}(h ``flags``h]j)}(hj^h]hflags}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMbhj^ubj)}(hhh](h)}(h3the flags for a :c:type:`drm_nouveau_vm_bind` ioctlh](hthe flags for a }(hj^hhhNhNubh)}(h:c:type:`drm_nouveau_vm_bind`h]j)}(hj^h]hdrm_nouveau_vm_bind}(hj^hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_vm_binduh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMYhj^ubh ioctl}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj^hMYhj^ubh)}(hSupported values:h]hSupported values:}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM[hj^ubh)}(h``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel.h](j)}(h!``DRM_NOUVEAU_VM_BIND_RUN_ASYNC``h]hDRM_NOUVEAU_VM_BIND_RUN_ASYNC}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubh^ - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel.}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM]hj^ubh)}(hIf this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects.h](hrIf this flag is not supplied the kernel executes the associated operations synchronously and doesn’t accept any }(hj^hhhNhNubh)}(h:c:type:`drm_nouveau_sync`h]j)}(hj_h]hdrm_nouveau_sync}(hj _hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM`hj^ubh objects.}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj$_hM`hj^ubeh}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1hhj^hMbhj%^ubh)}(h>``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` h](j)}(h``wait_count``h]j)}(hjA_h]h wait_count}(hjC_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?_ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMghj;_ubj)}(hhh]h)}(h.the number of wait :c:type:`drm_nouveau_syncs`h](hthe number of wait }(hjZ_hhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjd_h]hdrm_nouveau_syncs}(hjf_hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjb_ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncsuh1hhjV_hMghjZ_ubeh}(h]h ]h"]h$]h&]uh1hhjV_hMghjW_ubah}(h]h ]h"]h$]h&]uh1jhj;_ubeh}(h]h ]h"]h$]h&]uh1hhjV_hMghj%^ubh)}(hP``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_count``h]j)}(hj_h]h sig_count}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMkhj_ubj)}(hhh]h)}(hAthe number of :c:type:`drm_nouveau_syncs` to signal when finishedh](hthe number of }(hj_hhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hj_h]hdrm_nouveau_syncs}(hj_hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncsuh1hhj_hMkhj_ubh to signal when finished}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj_hMkhj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1hhj_hMkhj%^ubh)}(h@``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for h](j)}(h ``wait_ptr``h]j)}(hj_h]hwait_ptr}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMohj_ubj)}(hhh]h)}(h2pointer to :c:type:`drm_nouveau_syncs` to wait forh](h pointer to }(hj`hhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hj`h]hdrm_nouveau_syncs}(hj`hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncsuh1hhj `hMohj`ubh to wait for}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj `hMohj `ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1hhj `hMohj%^ubh)}(hK``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_ptr``h]j)}(hjQ`h]hsig_ptr}(hjS`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjO`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMshjK`ubj)}(hhh]h)}(h>pointer to :c:type:`drm_nouveau_syncs` to signal when finishedh](h pointer to }(hjj`hhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjt`h]hdrm_nouveau_syncs}(hjv`hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjr`ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncsuh1hhjf`hMshjj`ubh to signal when finished}(hjj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjf`hMshjg`ubah}(h]h ]h"]h$]h&]uh1jhjK`ubeh}(h]h ]h"]h$]h&]uh1hhjf`hMshj%^ubh)}(hF``op_ptr`` pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](j)}(h ``op_ptr``h]j)}(hj`h]hop_ptr}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMvhj`ubj)}(hhh]h)}(h;pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](hpointer to the }(hj`hhhNhNubh)}(h!:c:type:`drm_nouveau_vm_bind_ops`h]j)}(hj`h]hdrm_nouveau_vm_bind_ops}(hj`hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_vm_bind_opsuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMwhj`ubh to execute}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj`hMwhj`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1hhj`hMvhj%^ubeh}(h]h ]h"]h$]h&]uh1hhj]ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjUhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_nouveau_exec_push (C struct)c.drm_nouveau_exec_pushhNtauh1jhjUhhhNhNubj)}(hhh](j)}(hdrm_nouveau_exec_pushh]j)}(hstruct drm_nouveau_exec_pushh](j)}(hjh]hstruct}(hj*ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ahhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM}ubj)}(h h]h }(hj8ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ahhhj7ahM}ubj)}(hdrm_nouveau_exec_pushh]j)}(hj$ah]hdrm_nouveau_exec_push}(hjJahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFaubah}(h]h ](jjeh"]h$]h&]jjuh1jhj&ahhhj7ahM}ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj"ahhhj7ahM}ubah}(h]jaah ](j j eh"]h$]h&]jj)jhuh1jhj7ahM}hjahhubj)}(hhh]h)}(hEXEC push operationh]hEXEC push operation}(hjlahhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM|hjiahhubah}(h]h ]h"]h$]h&]uh1jhjahhhj7ahM}ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jaj8jaj9j:j;uh1jhhhjUhNhNubj=)}(hXM**Definition**:: struct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; }; **Members** ``va`` the virtual address of the push buffer mapping ``va_len`` the length of the push buffer mapping ``flags`` the flags for this push buffer mappingh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaubh:}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjaubj`)}(hstruct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; };h]hstruct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; };}hjasbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjaubh)}(h **Members**h]h)}(hjah]hMembers}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjaubh)}(hhh](h)}(h6``va`` the virtual address of the push buffer mapping h](j)}(h``va``h]j)}(hjah]hva}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjaubj)}(hhh]h)}(h.the virtual address of the push buffer mappingh]h.the virtual address of the push buffer mapping}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahMhjaubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1hhjahMhjaubh)}(h1``va_len`` the length of the push buffer mapping h](j)}(h ``va_len``h]j)}(hjbh]hva_len}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhj bubj)}(hhh]h)}(h%the length of the push buffer mappingh]h%the length of the push buffer mapping}(hj+bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'bhMhj(bubah}(h]h ]h"]h$]h&]uh1jhj bubeh}(h]h ]h"]h$]h&]uh1hhj'bhMhjaubh)}(h0``flags`` the flags for this push buffer mappingh](j)}(h ``flags``h]j)}(hjKbh]hflags}(hjMbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIbubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjEbubj)}(hhh]h)}(h&the flags for this push buffer mappingh]h&the flags for this push buffer mapping}(hjdbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjabubah}(h]h ]h"]h$]h&]uh1jhjEbubeh}(h]h ]h"]h$]h&]uh1hhj`bhMhjaubeh}(h]h ]h"]h$]h&]uh1hhjaubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjUhhhNhNubh)}(h**Description**h]h)}(hjbh]h Description}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjUhhubh)}(hThis structure represents a single EXEC push operation. UMDs should pass an array of this structure via struct drm_nouveau_exec's :c:type:`push_ptr` field.h](hThis structure represents a single EXEC push operation. UMDs should pass an array of this structure via struct drm_nouveau_exec’s }(hjbhhhNhNubh)}(h:c:type:`push_ptr`h]j)}(hjbh]hpush_ptr}(hjbhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j push_ptruh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM}hjbubh field.}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjbhM}hjUhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_nouveau_exec (C struct)c.drm_nouveau_exechNtauh1jhjUhhhNhNubj)}(hhh](j)}(hdrm_nouveau_exech]j)}(hstruct drm_nouveau_exech](j)}(hjh]hstruct}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhjbhMubj)}(hdrm_nouveau_exech]j)}(hjbh]hdrm_nouveau_exec}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj cubah}(h]h ](jjeh"]h$]h&]jjuh1jhjbhhhjbhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjbhhhjbhMubah}(h]jbah ](j j eh"]h$]h&]jj)jhuh1jhjbhMhjbhhubj)}(hhh]h)}(h$structure for DRM_IOCTL_NOUVEAU_EXECh]h$structure for DRM_IOCTL_NOUVEAU_EXEC}(hj1chhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhj.chhubah}(h]h ]h"]h$]h&]uh1jhjbhhhjbhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jIcj8jIcj9j:j;uh1jhhhjUhNhNubj=)}(hX**Definition**:: struct drm_nouveau_exec { __u32 channel; __u32 push_count; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 push_ptr; }; **Members** ``channel`` the channel to execute the push buffer in ``push_count`` the number of :c:type:`drm_nouveau_exec_push` ops ``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` ``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished ``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for ``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished ``push_ptr`` pointer to :c:type:`drm_nouveau_exec_push` opsh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjUchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQcubh:}(hjQchhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjMcubj`)}(hstruct drm_nouveau_exec { __u32 channel; __u32 push_count; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 push_ptr; };h]hstruct drm_nouveau_exec { __u32 channel; __u32 push_count; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 push_ptr; };}hjncsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjMcubh)}(h **Members**h]h)}(hjch]hMembers}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}cubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjMcubh)}(hhh](h)}(h6``channel`` the channel to execute the push buffer in h](j)}(h ``channel``h]j)}(hjch]hchannel}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjcubj)}(hhh]h)}(h)the channel to execute the push buffer inh]h)the channel to execute the push buffer in}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjcubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1hhjchMhjcubh)}(hA``push_count`` the number of :c:type:`drm_nouveau_exec_push` ops h](j)}(h``push_count``h]j)}(hjch]h push_count}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjcubj)}(hhh]h)}(h1the number of :c:type:`drm_nouveau_exec_push` opsh](hthe number of }(hjchhhNhNubh)}(h:c:type:`drm_nouveau_exec_push`h]j)}(hjch]hdrm_nouveau_exec_push}(hjchhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_exec_pushuh1hhjchMhjcubh ops}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjchMhjcubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1hhjchMhjcubh)}(h>``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` h](j)}(h``wait_count``h]j)}(hj3dh]h wait_count}(hj5dhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1dubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhj-dubj)}(hhh]h)}(h.the number of wait :c:type:`drm_nouveau_syncs`h](hthe number of wait }(hjLdhhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjVdh]hdrm_nouveau_syncs}(hjXdhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjTdubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncsuh1hhjHdhMhjLdubeh}(h]h ]h"]h$]h&]uh1hhjHdhMhjIdubah}(h]h ]h"]h$]h&]uh1jhj-dubeh}(h]h ]h"]h$]h&]uh1hhjHdhMhjcubh)}(hP``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_count``h]j)}(hjdh]h sig_count}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjdubj)}(hhh]h)}(hAthe number of :c:type:`drm_nouveau_syncs` to signal when finishedh](hthe number of }(hjdhhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjdh]hdrm_nouveau_syncs}(hjdhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncsuh1hhjdhMhjdubh to signal when finished}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjdhMhjdubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1hhjdhMhjcubh)}(h@``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for h](j)}(h ``wait_ptr``h]j)}(hjdh]hwait_ptr}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjdubj)}(hhh]h)}(h2pointer to :c:type:`drm_nouveau_syncs` to wait forh](h pointer to }(hjehhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hj eh]hdrm_nouveau_syncs}(hj ehhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncsuh1hhjdhMhjeubh to wait for}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjdhMhjdubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1hhjdhMhjcubh)}(hK``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_ptr``h]j)}(hjCeh]hsig_ptr}(hjEehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAeubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhj=eubj)}(hhh]h)}(h>pointer to :c:type:`drm_nouveau_syncs` to signal when finishedh](h pointer to }(hj\ehhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjfeh]hdrm_nouveau_syncs}(hjhehhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjdeubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_syncsuh1hhjXehMhj\eubh to signal when finished}(hj\ehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjXehMhjYeubah}(h]h ]h"]h$]h&]uh1jhj=eubeh}(h]h ]h"]h$]h&]uh1hhjXehMhjcubh)}(h;``push_ptr`` pointer to :c:type:`drm_nouveau_exec_push` opsh](j)}(h ``push_ptr``h]j)}(hjeh]hpush_ptr}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjeubj)}(hhh]h)}(h.pointer to :c:type:`drm_nouveau_exec_push` opsh](h pointer to }(hjehhhNhNubh)}(h:c:type:`drm_nouveau_exec_push`h]j)}(hjeh]hdrm_nouveau_exec_push}(hjehhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j drm_nouveau_exec_pushuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjeubh ops}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjehMhjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1hhjehMhjcubeh}(h]h ]h"]h$]h&]uh1hhjMcubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjUhhhNhNubeh}(h]vm-bind-exec-uapiah ]h"]vm_bind / exec uapiah$]h&]uh1hhjsUhhhhhKubeh}(h]drm-nouveau-uapiah ]h"]drm/nouveau uapiah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hdrm/panthor uAPIh]hdrm/panthor uAPI}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhhhhhKubh)}(h.. _Introduction:h]h}(h]h ]h"]h$]h&]hԌ introductionuh1hhKhjfhhhNubh)}(h**Introduction**h]h)}(hj1fh]h Introduction}(hj3fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/fubah}(h]j.fah ]h"] introductionah$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfhhh}jDfj$fsh}j.fj$fsubh)}(h0This documentation describes the Panthor IOCTLs.h]h0This documentation describes the Panthor IOCTLs.}(hjJfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK hjfhhubh)}(hEJust a few generic rules about the data passed to the Panthor IOCTLs:h]hEJust a few generic rules about the data passed to the Panthor IOCTLs:}(hjYfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfhhubjp )}(hhh](ju )}(hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.h]h)}(hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.h]hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.}(hjofhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjkfubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]h)}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]h)}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]hNAll padding fields will be checked by the driver to make sure they are zeroed.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(h-Flags can be added, but not removed/replaced.h]h)}(hjfh]h-Flags can be added, but not removed/replaced.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]h)}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).h]h)}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).h]hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]h)}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK!hjgubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h)}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK#hjgubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to trial and error to know which flags are supported.h]h)}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to trial and error to know which flags are supported.h]hEach new flag/field addition must come with a driver version update so the userspace driver doesn’t have to trial and error to know which flags are supported.}(hj6ghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK%hj2gubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h)}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h`Structures should not contain unions, as this would defeat the extensibility of such structures.}(hjOghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK(hjKgubah}(h]h ]h"]h$]h&]uh1jt hjhfubju )}(hrIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum. h]h)}(hpIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum.h]hrIOCTLs can’t be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum.}(hjhghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK*hjdgubah}(h]h ]h"]h$]h&]uh1jt hjhfubeh}(h]h ]h"]h$]h&]j j uh1jo hj}fhKhjfhhubh)}(h'.. _MMIO regions exposed to userspace.:h]h}(h]h ]h"]h$]h&]hԌ!mmio-regions-exposed-to-userspaceuh1hhK&hjfhhhNubh)}(h&**MMIO regions exposed to userspace.**h]h)}(hjgh]h"MMIO regions exposed to userspace.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgubah}(h]jgah ]h"]"mmio regions exposed to userspace.ah$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK0hjfhhh}jgjgsh}jgjgsubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&DRM_PANTHOR_USER_MMIO_OFFSET (C macro)c.DRM_PANTHOR_USER_MMIO_OFFSEThNtauh1jhjfhhhNhNubj)}(hhh](j)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]j)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]j)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]j)}(hjgh]hDRM_PANTHOR_USER_MMIO_OFFSET}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubah}(h]h ](jjeh"]h$]h&]jjuh1jhjghhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK1ubah}(h]h ]h"]h$]h&]jjjuh1jjjhjghhhjghK1ubah}(h]jgah ](j j eh"]h$]h&]jj)jhuh1jhjghK1hjghhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjghhhjghK1ubeh}(h]h ](j1macroeh"]h$]h&]j6j1j7jgj8jgj9j:j;uh1jhhhjfhNhNubh)}(hXFile offset for all MMIO regions being exposed to userspace. Don't use this value directly, use DRM_PANTHOR_USER__OFFSET values instead. pgoffset passed to mmap2() is an unsigned long, which forces us to use a different offset on 32-bit and 64-bit systems.h]hXFile offset for all MMIO regions being exposed to userspace. Don’t use this value directly, use DRM_PANTHOR_USER__OFFSET values instead. pgoffset passed to mmap2() is an unsigned long, which forces us to use a different offset on 32-bit and 64-bit systems.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK3hjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET (C macro)'c.DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSEThNtauh1jhjfhhhNhNubj)}(hhh](j)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]j)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]j)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]j)}(hjhh]h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET}(hj"hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK8ubah}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhhj5hhK8ubah}(h]jhah ](j j eh"]h$]h&]jj)jhuh1jhj5hhK8hjhhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhhj5hhK8ubeh}(h]h ](j1macroeh"]h$]h&]j6j1j7jNhj8jNhj9j:j;uh1jhhhjfhNhNubh)}(hXFile offset for the LATEST_FLUSH_ID register. The Userspace driver controls GPU cache flushing through CS instructions, but the flush reduction mechanism requires a flush_id. This flush_id could be queried with an ioctl, but Arm provides a well-isolated register page containing only this read-only register, so let's expose this page through a static mmap offset and allow direct mapping of this MMIO region so we can avoid the user <-> kernel round-trip.h]hXFile offset for the LATEST_FLUSH_ID register. The Userspace driver controls GPU cache flushing through CS instructions, but the flush reduction mechanism requires a flush_id. This flush_id could be queried with an ioctl, but Arm provides a well-isolated register page containing only this read-only register, so let’s expose this page through a static mmap offset and allow direct mapping of this MMIO region so we can avoid the user <-> kernel round-trip.}(hjRhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK:hjfhhubh)}(h.. _IOCTL IDs:h]h}(h]h ]h"]h$]h&]hԌ ioctl-idsuh1hhK> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; }; **Members** ``gpu_id`` GPU ID. ``gpu_rev`` GPU revision. ``csf_id`` Command stream frontend ID. ``l2_features`` L2-cache features. ``tiler_features`` Tiler features. ``mem_features`` Memory features. ``mmu_features`` MMU features. ``thread_features`` Thread features. ``max_threads`` Maximum number of threads. ``thread_max_workgroup_size`` Maximum workgroup size. ``thread_max_barrier_size`` Maximum number of threads that can wait simultaneously on a barrier. ``coherency_features`` Coherency features. ``texture_features`` Texture features. ``as_present`` Bitmask encoding the number of address-space exposed by the MMU. ``shader_present`` Bitmask encoding the shader cores exposed by the GPU. ``l2_present`` Bitmask encoding the L2 caches exposed by the GPU. ``tiler_present`` Bitmask encoding the tiler units exposed by the GPU. ``core_features`` Used to discriminate core variants when they exist. ``pad`` MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj9qhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5qubh:}(hj5qhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj1qubj`)}(hXstruct drm_panthor_gpu_info { __u32 gpu_id; #define DRM_PANTHOR_ARCH_MAJOR(x) ((x) >> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; };h]hXstruct drm_panthor_gpu_info { __u32 gpu_id; #define DRM_PANTHOR_ARCH_MAJOR(x) ((x) >> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; };}hjRqsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj1qubh)}(h **Members**h]h)}(hjcqh]hMembers}(hjeqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaqubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj1qubh)}(hhh](h)}(h``gpu_id`` GPU ID. h](j)}(h ``gpu_id``h]j)}(hjqh]hgpu_id}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj|qubj)}(hhh]h)}(hGPU ID.h]hGPU ID.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhKhjqubah}(h]h ]h"]h$]h&]uh1jhj|qubeh}(h]h ]h"]h$]h&]uh1hhjqhKhjyqubh)}(h``gpu_rev`` GPU revision. h](j)}(h ``gpu_rev``h]j)}(hjqh]hgpu_rev}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjqubj)}(hhh]h)}(h GPU revision.h]h GPU revision.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhKhjqubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1hhjqhKhjyqubh)}(h'``csf_id`` Command stream frontend ID. h](j)}(h ``csf_id``h]j)}(hjqh]hcsf_id}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjqubj)}(hhh]h)}(hCommand stream frontend ID.h]hCommand stream frontend ID.}(hj rhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj rhKhj rubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1hhj rhKhjyqubh)}(h#``l2_features`` L2-cache features. h](j)}(h``l2_features``h]j)}(hj-rh]h l2_features}(hj/rhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+rubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj'rubj)}(hhh]h)}(hL2-cache features.h]hL2-cache features.}(hjFrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBrhKhjCrubah}(h]h ]h"]h$]h&]uh1jhj'rubeh}(h]h ]h"]h$]h&]uh1hhjBrhKhjyqubh)}(h#``tiler_features`` Tiler features. h](j)}(h``tiler_features``h]j)}(hjfrh]htiler_features}(hjhrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdrubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj`rubj)}(hhh]h)}(hTiler features.h]hTiler features.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{rhKhj|rubah}(h]h ]h"]h$]h&]uh1jhj`rubeh}(h]h ]h"]h$]h&]uh1hhj{rhKhjyqubh)}(h"``mem_features`` Memory features. h](j)}(h``mem_features``h]j)}(hjrh]h mem_features}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjrubj)}(hhh]h)}(hMemory features.h]hMemory features.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhKhjrubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1hhjrhKhjyqubh)}(h``mmu_features`` MMU features. h](j)}(h``mmu_features``h]j)}(hjrh]h mmu_features}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjrubj)}(hhh]h)}(h MMU features.h]h MMU features.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhKhjrubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1hhjrhKhjyqubh)}(h%``thread_features`` Thread features. h](j)}(h``thread_features``h]j)}(hjsh]hthread_features}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj subj)}(hhh]h)}(hThread features.h]hThread features.}(hj*shhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&shKhj'subah}(h]h ]h"]h$]h&]uh1jhj subeh}(h]h ]h"]h$]h&]uh1hhj&shKhjyqubh)}(h+``max_threads`` Maximum number of threads. h](j)}(h``max_threads``h]j)}(hjJsh]h max_threads}(hjLshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjDsubj)}(hhh]h)}(hMaximum number of threads.h]hMaximum number of threads.}(hjcshhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_shKhj`subah}(h]h ]h"]h$]h&]uh1jhjDsubeh}(h]h ]h"]h$]h&]uh1hhj_shKhjyqubh)}(h6``thread_max_workgroup_size`` Maximum workgroup size. h](j)}(h``thread_max_workgroup_size``h]j)}(hjsh]hthread_max_workgroup_size}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj}subj)}(hhh]h)}(hMaximum workgroup size.h]hMaximum workgroup size.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshKhjsubah}(h]h ]h"]h$]h&]uh1jhj}subeh}(h]h ]h"]h$]h&]uh1hhjshKhjyqubh)}(ha``thread_max_barrier_size`` Maximum number of threads that can wait simultaneously on a barrier. h](j)}(h``thread_max_barrier_size``h]j)}(hjsh]hthread_max_barrier_size}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjsubj)}(hhh]h)}(hDMaximum number of threads that can wait simultaneously on a barrier.h]hDMaximum number of threads that can wait simultaneously on a barrier.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1hhjshMhjyqubh)}(h+``coherency_features`` Coherency features. h](j)}(h``coherency_features``h]j)}(hjsh]hcoherency_features}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjsubj)}(hhh]h)}(hCoherency features.h]hCoherency features.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhj thKhj tubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1hhj thKhjyqubh)}(h'``texture_features`` Texture features. h](j)}(h``texture_features``h]j)}(hj/th]htexture_features}(hj1thhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-tubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj)tubj)}(hhh]h)}(hTexture features.h]hTexture features.}(hjHthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDthKhjEtubah}(h]h ]h"]h$]h&]uh1jhj)tubeh}(h]h ]h"]h$]h&]uh1hhjDthKhjyqubh)}(hP``as_present`` Bitmask encoding the number of address-space exposed by the MMU. h](j)}(h``as_present``h]j)}(hjhth]h as_present}(hjjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjftubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjbtubj)}(hhh]h)}(h@Bitmask encoding the number of address-space exposed by the MMU.h]h@Bitmask encoding the number of address-space exposed by the MMU.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}thKhj~tubah}(h]h ]h"]h$]h&]uh1jhjbtubeh}(h]h ]h"]h$]h&]uh1hhj}thKhjyqubh)}(hI``shader_present`` Bitmask encoding the shader cores exposed by the GPU. h](j)}(h``shader_present``h]j)}(hjth]hshader_present}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjtubj)}(hhh]h)}(h5Bitmask encoding the shader cores exposed by the GPU.h]h5Bitmask encoding the shader cores exposed by the GPU.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthKhjtubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1hhjthKhjyqubh)}(hB``l2_present`` Bitmask encoding the L2 caches exposed by the GPU. h](j)}(h``l2_present``h]j)}(hjth]h l2_present}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjtubj)}(hhh]h)}(h2Bitmask encoding the L2 caches exposed by the GPU.h]h2Bitmask encoding the L2 caches exposed by the GPU.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthKhjtubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1hhjthKhjyqubh)}(hG``tiler_present`` Bitmask encoding the tiler units exposed by the GPU. h](j)}(h``tiler_present``h]j)}(hjuh]h tiler_present}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj uubj)}(hhh]h)}(h4Bitmask encoding the tiler units exposed by the GPU.h]h4Bitmask encoding the tiler units exposed by the GPU.}(hj,uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(uhKhj)uubah}(h]h ]h"]h$]h&]uh1jhj uubeh}(h]h ]h"]h$]h&]uh1hhj(uhKhjyqubh)}(hF``core_features`` Used to discriminate core variants when they exist. h](j)}(h``core_features``h]j)}(hjLuh]h core_features}(hjNuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjFuubj)}(hhh]h)}(h3Used to discriminate core variants when they exist.h]h3Used to discriminate core variants when they exist.}(hjeuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjauhKhjbuubah}(h]h ]h"]h$]h&]uh1jhjFuubeh}(h]h ]h"]h$]h&]uh1hhjauhKhjyqubh)}(h ``pad`` MBZ.h](j)}(h``pad``h]j)}(hjuh]hpad}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjuubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1hhjuhKhjyqubeh}(h]h ]h"]h$]h&]uh1hhj1qubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubh)}(h**Description**h]h)}(hjuh]h Description}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfhhubh)}(hAStructure grouping all queryable information relating to the GPU.h]hAStructure grouping all queryable information relating to the GPU.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_panthor_csif_info (C struct)c.drm_panthor_csif_infohNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_csif_infoh]j)}(hstruct drm_panthor_csif_infoh](j)}(hjh]hstruct}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhhjvhKubj)}(hdrm_panthor_csif_infoh]j)}(hjvh]hdrm_panthor_csif_info}(hj&vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"vubah}(h]h ](jjeh"]h$]h&]jjuh1jhjvhhhjvhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjuhhhjvhKubah}(h]juah ](j j eh"]h$]h&]jj)jhuh1jhjvhKhjuhhubj)}(hhh]h)}(h$Command stream interface informationh]h$Command stream interface information}(hjHvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM<hjEvhhubah}(h]h ]h"]h$]h&]uh1jhjuhhhjvhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j`vj8j`vj9j:j;uh1jhhhjfhNhNubj=)}(hXu**Definition**:: struct drm_panthor_csif_info { __u32 csg_slot_count; __u32 cs_slot_count; __u32 cs_reg_count; __u32 scoreboard_slot_count; __u32 unpreserved_cs_reg_count; __u32 pad; }; **Members** ``csg_slot_count`` Number of command stream group slots exposed by the firmware. ``cs_slot_count`` Number of command stream slots per group. ``cs_reg_count`` Number of command stream registers. ``scoreboard_slot_count`` Number of scoreboard slots. ``unpreserved_cs_reg_count`` Number of command stream registers reserved by the kernel driver to call a userspace command stream. All registers can be used by a userspace command stream, but the [cs_slot_count - unpreserved_cs_reg_count .. cs_slot_count] registers are used by the kernel when DRM_PANTHOR_IOCTL_GROUP_SUBMIT is called. ``pad`` Padding field, set to zero.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjlvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhvubh:}(hjhvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM@hjdvubj`)}(hstruct drm_panthor_csif_info { __u32 csg_slot_count; __u32 cs_slot_count; __u32 cs_reg_count; __u32 scoreboard_slot_count; __u32 unpreserved_cs_reg_count; __u32 pad; };h]hstruct drm_panthor_csif_info { __u32 csg_slot_count; __u32 cs_slot_count; __u32 cs_reg_count; __u32 scoreboard_slot_count; __u32 unpreserved_cs_reg_count; __u32 pad; };}hjvsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMBhjdvubh)}(h **Members**h]h)}(hjvh]hMembers}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMKhjdvubh)}(hhh](h)}(hQ``csg_slot_count`` Number of command stream group slots exposed by the firmware. h](j)}(h``csg_slot_count``h]j)}(hjvh]hcsg_slot_count}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMAhjvubj)}(hhh]h)}(h=Number of command stream group slots exposed by the firmware.h]h=Number of command stream group slots exposed by the firmware.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMAhjvubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1hhjvhMAhjvubh)}(h<``cs_slot_count`` Number of command stream slots per group. h](j)}(h``cs_slot_count``h]j)}(hjvh]h cs_slot_count}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjvubj)}(hhh]h)}(h)Number of command stream slots per group.h]h)Number of command stream slots per group.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhKhjwubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1hhjwhKhjvubh)}(h5``cs_reg_count`` Number of command stream registers. h](j)}(h``cs_reg_count``h]j)}(hj'wh]h cs_reg_count}(hj)whhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%wubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj!wubj)}(hhh]h)}(h#Number of command stream registers.h]h#Number of command stream registers.}(hj@whhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfhhubh)}(hVStructure grouping all queryable information relating to the allowed group priorities.h]hVStructure grouping all queryable information relating to the allowed group priorities.}(hjV{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMrhjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_panthor_dev_query (C struct)c.drm_panthor_dev_queryhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_dev_queryh]j)}(hstruct drm_panthor_dev_queryh](j)}(hjh]hstruct}(hj~{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz{hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMwubj)}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz{hhhj{hMwubj)}(hdrm_panthor_dev_queryh]j)}(hjx{h]hdrm_panthor_dev_query}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjz{hhhj{hMwubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjv{hhhj{hMwubah}(h]jq{ah ](j j eh"]h$]h&]jj)jhuh1jhj{hMwhjs{hhubj)}(hhh]h)}(h/Arguments passed to DRM_PANTHOR_IOCTL_DEV_QUERYh]h/Arguments passed to DRM_PANTHOR_IOCTL_DEV_QUERY}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj{hhubah}(h]h ]h"]h$]h&]uh1jhjs{hhhj{hMwubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j{j8j{j9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; }; **Members** ``type`` the query type (see drm_panthor_dev_query_type). ``size`` size of the type being queried. If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace. ``pointer`` user pointer to a query type struct. Pointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubh:}(hj{hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj{ubj`)}(hTstruct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; };h]hTstruct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; };}hj{sbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj{ubh)}(h **Members**h]h)}(hj|h]hMembers}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj |ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj{ubh)}(hhh](h)}(h:``type`` the query type (see drm_panthor_dev_query_type). h](j)}(h``type``h]j)}(hj-|h]htype}(hj/|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'|ubj)}(hhh]h)}(h0the query type (see drm_panthor_dev_query_type).h]h0the query type (see drm_panthor_dev_query_type).}(hjF|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB|hMhjC|ubah}(h]h ]h"]h$]h&]uh1jhj'|ubeh}(h]h ]h"]h$]h&]uh1hhjB|hMhj$|ubh)}(hXM``size`` size of the type being queried. If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace. h](j)}(h``size``h]j)}(hjf|h]hsize}(hjh|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjd|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj`|ubj)}(hhh](h)}(hsize of the type being queried.h]hsize of the type being queried.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj||ubh)}(hX"If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace.h]hX"If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj||ubeh}(h]h ]h"]h$]h&]uh1jhj`|ubeh}(h]h ]h"]h$]h&]uh1hhj{|hMhj$|ubh)}(h``pointer`` user pointer to a query type struct. Pointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h](j)}(h ``pointer``h]j)}(hj|h]hpointer}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|ubj)}(hhh](h)}(h$user pointer to a query type struct.h]h$user pointer to a query type struct.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|ubh)}(hPointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h]hPointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that’s large enough to hold size bytes.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|ubeh}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1hhj|hMhj$|ubeh}(h]h ]h"]h$]h&]uh1hhj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_panthor_vm_create (C struct)c.drm_panthor_vm_createhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_createh]j)}(hstruct drm_panthor_vm_createh](j)}(hjh]hstruct}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj&}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhhj%}hMubj)}(hdrm_panthor_vm_createh]j)}(hj}h]hdrm_panthor_vm_create}(hj8}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4}ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj}hhhj%}hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj}hhhj%}hMubah}(h]j }ah ](j j eh"]h$]h&]jj)jhuh1jhj%}hMhj }hhubj)}(hhh]h)}(h/Arguments passed to DRM_PANTHOR_IOCTL_VM_CREATEh]h/Arguments passed to DRM_PANTHOR_IOCTL_VM_CREATE}(hjZ}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjW}hhubah}(h]h ]h"]h$]h&]uh1jhj }hhhj%}hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jr}j8jr}j9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; }; **Members** ``flags`` VM flags, MBZ. ``id`` Returned VM ID. ``user_va_range`` Size of the VA space reserved for user objects. The kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel. If user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**. User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj~}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjz}ubh:}(hjz}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjv}ubj`)}(hYstruct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; };h]hYstruct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; };}hj}sbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjv}ubh)}(h **Members**h]h)}(hj}h]hMembers}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjv}ubh)}(hhh](h)}(h``flags`` VM flags, MBZ. h](j)}(h ``flags``h]j)}(hj}h]hflags}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj}ubj)}(hhh]h)}(hVM flags, MBZ.h]hVM flags, MBZ.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1hhj}hMhj}ubh)}(h``id`` Returned VM ID. h](j)}(h``id``h]j)}(hj~h]hid}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj}ubj)}(hhh]h)}(hReturned VM ID.h]hReturned VM ID.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKhj~ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1hhj~hKhj}ubh)}(hX``user_va_range`` Size of the VA space reserved for user objects. The kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel. If user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**. User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h](j)}(h``user_va_range``h]j)}(hj9~h]h user_va_range}(hj;~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj3~ubj)}(hhh](h)}(h/Size of the VA space reserved for user objects.h]h/Size of the VA space reserved for user objects.}(hjR~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjO~ubh)}(hXThe kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel.h]hXThe kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel.}(hja~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjO~ubh)}(hXIf user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**.h](hXoIf user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in }(hjp~hhhNhNubh)}(h**user_va_range**h]h user_va_range}(hjx~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp~ubh.}(hjp~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjO~ubh)}(h]User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h]h]User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjN~hMhjO~ubeh}(h]h ]h"]h$]h&]uh1jhj3~ubeh}(h]h ]h"]h$]h&]uh1hhjN~hMhj}ubeh}(h]h ]h"]h$]h&]uh1hhjv}ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_panthor_vm_destroy (C struct)c.drm_panthor_vm_destroyhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_destroyh]j)}(hstruct drm_panthor_vm_destroyh](j)}(hjh]hstruct}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhhj~hMubj)}(hdrm_panthor_vm_destroyh]j)}(hj~h]hdrm_panthor_vm_destroy}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj~hhhj~hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj~hhhj~hMubah}(h]j~ah ](j j eh"]h$]h&]jj)jhuh1jhj~hMhj~hhubj)}(hhh]h)}(h0Arguments passed to DRM_PANTHOR_IOCTL_VM_DESTROYh]h0Arguments passed to DRM_PANTHOR_IOCTL_VM_DESTROY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj~hhhj~hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j+j8j+j9j:j;uh1jhhhjfhNhNubj=)}(h**Definition**:: struct drm_panthor_vm_destroy { __u32 id; __u32 pad; }; **Members** ``id`` ID of the VM to destroy. ``pad`` MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3ubh:}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj/ubj`)}(h?struct drm_panthor_vm_destroy { __u32 id; __u32 pad; };h]h?struct drm_panthor_vm_destroy { __u32 id; __u32 pad; };}hjPsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj/ubh)}(h **Members**h]h)}(hjah]hMembers}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj/ubh)}(hhh](h)}(h ``id`` ID of the VM to destroy. h](j)}(h``id``h]j)}(hjh]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjzubj)}(hhh]h)}(hID of the VM to destroy.h]hID of the VM to destroy.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1hhjhMhjwubh)}(h ``pad`` MBZ.h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjwubeh}(h]h ]h"]h$]h&]uh1hhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_panthor_vm_bind_op_flags (C enum)c.drm_panthor_vm_bind_op_flagshNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_bind_op_flagsh]j)}(h!enum drm_panthor_vm_bind_op_flagsh](j)}(hj?h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj hKubj)}(hdrm_panthor_vm_bind_op_flagsh]j)}(hj h]hdrm_panthor_vm_bind_op_flags}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj hKhjhhubj)}(hhh]h)}(hVM bind operation flagsh]hVM bind operation flags}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjRhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jmj8jmj9j:j;uh1jhhhjfhNhNubj=)}(hXO**Constants** ``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY`` Map the memory read-only. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC`` Map the memory not-executable. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED`` Map the memory uncached. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK`` Mask used to determine the type of operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP`` Map operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP`` Unmap operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY`` No VM operation. Just serves as a synchronization point on a VM queue. Only valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](h)}(h **Constants**h]h)}(hjwh]h Constants}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjqubh)}(hhh](h)}(ht``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY`` Map the memory read-only. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h'``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY``h]j)}(hjh]h#DRM_PANTHOR_VM_BIND_OP_MAP_READONLY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(hMap the memory read-only.h]hMap the memory read-only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hw``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC`` Map the memory not-executable. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h%``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC``h]j)}(hjހh]h!DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj܀ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj؀ubj)}(hhh](h)}(hMap the memory not-executable.h]hMap the memory not-executable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhj؀ubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hs``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED`` Map the memory uncached. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h'``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED``h]j)}(hj&h]h#DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj ubj)}(hhh](h)}(hMap the memory uncached.h]hMap the memory uncached.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj<ubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj<ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj;hMhjubh)}(hS``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK`` Mask used to determine the type of operation. h](j)}(h$``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK``h]j)}(hjnh]h DRM_PANTHOR_VM_BIND_OP_TYPE_MASK}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhubj)}(hhh]h)}(h-Mask used to determine the type of operation.h]h-Mask used to determine the type of operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h3``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP`` Map operation. h](j)}(h#``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP``h]j)}(hjh]hDRM_PANTHOR_VM_BIND_OP_TYPE_MAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hMap operation.h]hMap operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h7``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP`` Unmap operation. h](j)}(h%``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP``h]j)}(hjh]h!DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjށubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjځubj)}(hhh]h)}(hUnmap operation.h]hUnmap operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjځubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hX``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY`` No VM operation. Just serves as a synchronization point on a VM queue. Only valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](j)}(h)``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY``h]j)}(hjh]h%DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(hNo VM operation.h]hNo VM operation.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj/ubh)}(h5Just serves as a synchronization point on a VM queue.h]h5Just serves as a synchronization point on a VM queue.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj/ubh)}(hOnly valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](hOnly valid if }(hjPhhhNhNubj)}(h``DRM_PANTHOR_VM_BIND_ASYNC``h]hDRM_PANTHOR_VM_BIND_ASYNC}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubhg is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj.hMhj/ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj.hMhjubeh}(h]h ]h"]h$]h&]uh1hhjqubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_panthor_vm_bind_op (C struct)c.drm_panthor_vm_bind_ophNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_bind_oph]j)}(hstruct drm_panthor_vm_bind_oph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_panthor_vm_bind_oph]j)}(hjh]hdrm_panthor_vm_bind_op}(hj‚hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hVM bind operationh]hVM bind operation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhjfhNhNubj=)}(hX`**Definition**:: struct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; }; **Members** ``flags`` Combination of drm_panthor_vm_bind_op_flags flags. ``bo_handle`` Handle of the buffer object to map. MBZ for unmap or sync-only operations. ``bo_offset`` Buffer object offset. MBZ for unmap or sync-only operations. ``va`` Virtual address to map/unmap. MBZ for sync-only operations. ``size`` Size to map/unmap. MBZ for sync-only operations. ``syncs`` Array of struct drm_panthor_sync_op synchronization operations. This array must be empty if ``DRM_PANTHOR_VM_BIND_ASYNC`` is not set on the drm_panthor_vm_bind object containing this VM bind operation. This array shall not be empty for sync-only operations.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj`)}(hstruct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; };h]hstruct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; };}hj!sbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hj2h]hMembers}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hhh](h)}(h=``flags`` Combination of drm_panthor_vm_bind_op_flags flags. h](j)}(h ``flags``h]j)}(hjQh]hflags}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjKubj)}(hhh]h)}(h2Combination of drm_panthor_vm_bind_op_flags flags.h]h2Combination of drm_panthor_vm_bind_op_flags flags.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMhjgubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1hhjfhMhjHubh)}(hY``bo_handle`` Handle of the buffer object to map. MBZ for unmap or sync-only operations. h](j)}(h ``bo_handle``h]j)}(hjh]h bo_handle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hJHandle of the buffer object to map. MBZ for unmap or sync-only operations.h]hJHandle of the buffer object to map. MBZ for unmap or sync-only operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjHubh)}(hK``bo_offset`` Buffer object offset. MBZ for unmap or sync-only operations. h](j)}(h ``bo_offset``h]j)}(hjăh]h bo_offset}(hjƃhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjƒubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM%hj;hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hM%ubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jVj8jVj9j:j;uh1jhhhjfhNhNubj=)}(h**Constants** ``DRM_PANTHOR_VM_BIND_ASYNC`` VM bind operations are queued to the VM queue instead of being executed synchronously.h](h)}(h **Constants**h]h)}(hj`h]h Constants}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM)hjZubh)}(hhh]h)}(ht``DRM_PANTHOR_VM_BIND_ASYNC`` VM bind operations are queued to the VM queue instead of being executed synchronously.h](j)}(h``DRM_PANTHOR_VM_BIND_ASYNC``h]j)}(hjh]hDRM_PANTHOR_VM_BIND_ASYNC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM,hjyubj)}(hhh]h)}(hVVM bind operations are queued to the VM queue instead of being executed synchronously.h]hVVM bind operations are queued to the VM queue instead of being executed synchronously.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM,hjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1hhjhM,hjvubah}(h]h ]h"]h$]h&]uh1hhjZubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_panthor_vm_bind (C struct)c.drm_panthor_vm_bindhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_bindh]j)}(hstruct drm_panthor_vm_bindh](j)}(hjh]hstruct}(hj؅hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjԅhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM2ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjԅhhhjhM2ubj)}(hdrm_panthor_vm_bindh]j)}(hj҅h]hdrm_panthor_vm_bind}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjԅhhhjhM2ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjЅhhhjhM2ubah}(h]j˅ah ](j j eh"]h$]h&]jj)jhuh1jhjhM2hjͅhhubj)}(hhh]h)}(h-Arguments passed to DRM_IOCTL_PANTHOR_VM_BINDh]h-Arguments passed to DRM_IOCTL_PANTHOR_VM_BIND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM0hjhhubah}(h]h ]h"]h$]h&]uh1jhjͅhhhjhM2ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j2j8j2j9j:j;uh1jhhhjfhNhNubj=)}(hX>**Definition**:: struct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; }; **Members** ``vm_id`` VM targeted by the bind request. ``flags`` Combination of drm_panthor_vm_bind_flags flags. ``ops`` Array of struct drm_panthor_vm_bind_op bind operations.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh:}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM4hj6ubj`)}(hgstruct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; };h]hgstruct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; };}hjWsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM6hj6ubh)}(h **Members**h]h)}(hjhh]hMembers}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM<hj6ubh)}(hhh](h)}(h+``vm_id`` VM targeted by the bind request. h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM3hjubj)}(hhh]h)}(h VM targeted by the bind request.h]h VM targeted by the bind request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM3hj~ubh)}(h:``flags`` Combination of drm_panthor_vm_bind_flags flags. h](j)}(h ``flags``h]j)}(hjh]hflags}(hj†hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(h/Combination of drm_panthor_vm_bind_flags flags.h]h/Combination of drm_panthor_vm_bind_flags flags.}(hjنhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjՆhKhjֆubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjՆhKhj~ubh)}(h?``ops`` Array of struct drm_panthor_vm_bind_op bind operations.h](j)}(h``ops``h]j)}(hjh]hops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(h7Array of struct drm_panthor_vm_bind_op bind operations.h]h7Array of struct drm_panthor_vm_bind_op bind operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj~ubeh}(h]h ]h"]h$]h&]uh1hhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_panthor_vm_state (C enum)c.drm_panthor_vm_statehNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_stateh]j)}(henum drm_panthor_vm_stateh](j)}(hj?h]henum}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhhj`hKubj)}(hdrm_panthor_vm_stateh]j)}(hjMh]hdrm_panthor_vm_state}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ](jjeh"]h$]h&]jjuh1jhjOhhhj`hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjKhhhj`hKubah}(h]jFah ](j j eh"]h$]h&]jj)jhuh1jhj`hKhjHhhubj)}(hhh]h)}(h VM states.h]h VM states.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM>hjhhubah}(h]h ]h"]h$]h&]uh1jhjHhhhj`hKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhjfhNhNubj=)}(hX**Constants** ``DRM_PANTHOR_VM_STATE_USABLE`` VM is usable. New VM operations will be accepted on this VM. ``DRM_PANTHOR_VM_STATE_UNUSABLE`` VM is unusable. Something put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason). Once the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted. The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMBhjubh)}(hhh](h)}(h^``DRM_PANTHOR_VM_STATE_USABLE`` VM is usable. New VM operations will be accepted on this VM. h](j)}(h``DRM_PANTHOR_VM_STATE_USABLE``h]j)}(hjևh]hDRM_PANTHOR_VM_STATE_USABLE}(hj؇hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjԇubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMGhjЇubj)}(hhh](h)}(h VM is usable.h]h VM is usable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMEhjubh)}(h.New VM operations will be accepted on this VM.h]h.New VM operations will be accepted on this VM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMGhjubeh}(h]h ]h"]h$]h&]uh1jhjЇubeh}(h]h ]h"]h$]h&]uh1hhjhMGhj͇ubh)}(hX``DRM_PANTHOR_VM_STATE_UNUSABLE`` VM is unusable. Something put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason). Once the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted. The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h](j)}(h!``DRM_PANTHOR_VM_STATE_UNUSABLE``h]j)}(hjh]hDRM_PANTHOR_VM_STATE_UNUSABLE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMShjubj)}(hhh](h)}(hVM is unusable.h]hVM is unusable.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMJhj4ubh)}(hhSomething put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason).h]hhSomething put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason).}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMLhj4ubh)}(hOnce the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted.h]hOnce the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMOhj4ubh)}(h[The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h]h[The only way to recover from an unusable VM is to create a new VM, and destroy the old one.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMShj4ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj3hMShj͇ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_vm_get_state (C struct)c.drm_panthor_vm_get_statehNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_get_stateh]j)}(hstruct drm_panthor_vm_get_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMYubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMYubj)}(hdrm_panthor_vm_get_stateh]j)}(hjh]hdrm_panthor_vm_get_state}(hjĈhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMYubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMYubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMYhjhhubj)}(hhh]h)}(h Get VM state.h]h Get VM state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMYhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMYubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; }; **Members** ``vm_id`` VM targeted by the get_state request. ``state`` state returned by the driver. Must be one of the enum drm_panthor_vm_state values.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM]hjubj`)}(hFstruct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; };h]hFstruct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; };}hj#sbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM_hjubh)}(h **Members**h]h)}(hj4h]hMembers}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMdhjubh)}(hhh](h)}(h0``vm_id`` VM targeted by the get_state request. h](j)}(h ``vm_id``h]j)}(hjSh]hvm_id}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM\hjMubj)}(hhh]h)}(h%VM targeted by the get_state request.h]h%VM targeted by the get_state request.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhM\hjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1hhjhhM\hjJubh)}(h]``state`` state returned by the driver. Must be one of the enum drm_panthor_vm_state values.h](j)}(h ``state``h]j)}(hjh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMbhjubj)}(hhh](h)}(hstate returned by the driver.h]hstate returned by the driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMahjubh)}(h4Must be one of the enum drm_panthor_vm_state values.h]h4Must be one of the enum drm_panthor_vm_state values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMchjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMbhjJubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_panthor_bo_flags (C enum)c.drm_panthor_bo_flagshNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_flagsh]j)}(henum drm_panthor_bo_flagsh](j)}(hj?h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMiubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMiubj)}(hdrm_panthor_bo_flagsh]j)}(hjh]hdrm_panthor_bo_flags}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMiubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMiubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMihjhhubj)}(hhh]h)}(h-Buffer object flags, passed at creation time.h]h-Buffer object flags, passed at creation time.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhhj4hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMiubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jOj8jOj9j:j;uh1jhhhjfhNhNubj=)}(hd**Constants** ``DRM_PANTHOR_BO_NO_MMAP`` The buffer object will never be CPU-mapped in userspace.h](h)}(h **Constants**h]h)}(hjYh]h Constants}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMlhjSubh)}(hhh]h)}(hS``DRM_PANTHOR_BO_NO_MMAP`` The buffer object will never be CPU-mapped in userspace.h](j)}(h``DRM_PANTHOR_BO_NO_MMAP``h]j)}(hjxh]hDRM_PANTHOR_BO_NO_MMAP}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMnhjrubj)}(hhh]h)}(h8The buffer object will never be CPU-mapped in userspace.h]h8The buffer object will never be CPU-mapped in userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMohjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1hhjhMnhjoubah}(h]h ]h"]h$]h&]uh1hhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_panthor_bo_create (C struct)c.drm_panthor_bo_createhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_createh]j)}(hstruct drm_panthor_bo_createh](j)}(hjh]hstruct}(hjҊhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΊhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMtubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΊhhhjߊhMtubj)}(hdrm_panthor_bo_createh]j)}(hj̊h]hdrm_panthor_bo_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjΊhhhjߊhMtubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjʊhhhjߊhMtubah}(h]jŊah ](j j eh"]h$]h&]jj)jhuh1jhjߊhMthjNJhhubj)}(hhh]h)}(h0Arguments passed to DRM_IOCTL_PANTHOR_BO_CREATE.h]h0Arguments passed to DRM_IOCTL_PANTHOR_BO_CREATE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMphjhhubah}(h]h ]h"]h$]h&]uh1jhjNJhhhjߊhMtubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j,j8j,j9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; }; **Members** ``size`` Requested size for the object The (page-aligned) allocated size for the object will be returned. ``flags`` Flags. Must be a combination of drm_panthor_bo_flags flags. ``exclusive_vm_id`` Exclusive VM this buffer object will be mapped to. If not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd ``handle`` Returned handle for the object. Object handles are nonzero. ``pad`` MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubh:}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMthj0ubj`)}(h~struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; };h]h~struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; };}hjQsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMvhj0ubh)}(h **Members**h]h)}(hjbh]hMembers}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM~hj0ubh)}(hhh](h)}(hk``size`` Requested size for the object The (page-aligned) allocated size for the object will be returned. h](j)}(h``size``h]j)}(hjh]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMwhj{ubj)}(hhh](h)}(hRequested size for the objecth]hRequested size for the object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMuhjubh)}(hBThe (page-aligned) allocated size for the object will be returned.h]hBThe (page-aligned) allocated size for the object will be returned.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMwhjubeh}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1hhjhMwhjxubh)}(hF``flags`` Flags. Must be a combination of drm_panthor_bo_flags flags. h](j)}(h ``flags``h]j)}(hjɋh]hflags}(hjˋhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM|hjËubj)}(hhh]h)}(h;Flags. Must be a combination of drm_panthor_bo_flags flags.h]h;Flags. Must be a combination of drm_panthor_bo_flags flags.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjދhM|hjߋubah}(h]h ]h"]h$]h&]uh1jhjËubeh}(h]h ]h"]h$]h&]uh1hhjދhM|hjxubh)}(h``exclusive_vm_id`` Exclusive VM this buffer object will be mapped to. If not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd h](j)}(h``exclusive_vm_id``h]j)}(hjh]hexclusive_vm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h2Exclusive VM this buffer object will be mapped to.h]h2Exclusive VM this buffer object will be mapped to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hhh]h)}(hIf not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd h](j)}(hEIf not zero, the field must refer to a valid VM ID, and implies that:h]hEIf not zero, the field must refer to a valid VM ID, and implies that:}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhj-ubj)}(hhh]jp )}(hhh](ju )}(h4the buffer object will only ever be bound to that VMh]h)}(hjGh]h4the buffer object will only ever be bound to that VM}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjEubah}(h]h ]h"]h$]h&]uh1jt hjBubju )}(h!cannot be exported as a PRIME fd h]h)}(h cannot be exported as a PRIME fdh]h cannot be exported as a PRIME fd}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhj]ubah}(h]h ]h"]h$]h&]uh1jt hjBubeh}(h]h ]h"]h$]h&]j j uh1jo hjVhMhj?ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1hhjhMhj*ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjxubh)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hjnjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjxubh)}(h ``pad`` MBZ.h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjxubeh}(h]h ]h"]h$]h&]uh1hhj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_panthor_bo_mmap_offset (C struct)c.drm_panthor_bo_mmap_offsethNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_mmap_offseth]j)}(h!struct drm_panthor_bo_mmap_offseth](j)}(hjh]hstruct}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhhjNhKubj)}(hdrm_panthor_bo_mmap_offseth]j)}(hj;h]hdrm_panthor_bo_mmap_offset}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj=hhhjNhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj9hhhjNhKubah}(h]j4ah ](j j eh"]h$]h&]jj)jhuh1jhjNhKhj6hhubj)}(hhh]h)}(h5Arguments passed to DRM_IOCTL_PANTHOR_BO_MMAP_OFFSET.h]h5Arguments passed to DRM_IOCTL_PANTHOR_BO_MMAP_OFFSET.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj6hhhjNhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; }; **Members** ``handle`` Handle of the object we want an mmap offset for. ``pad`` MBZ. ``offset`` The fake offset to use for subsequent mmap calls.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj`)}(hYstruct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; };h]hYstruct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjэh]hMembers}(hjӍhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjύubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hhh](h)}(h<``handle`` Handle of the object we want an mmap offset for. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h0Handle of the object we want an mmap offset for.h]h0Handle of the object we want an mmap offset for.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h ``pad`` MBZ. h](j)}(h``pad``h]j)}(hj)h]hpad}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj#ubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hKhj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1hhj>hKhjubh)}(h<``offset`` The fake offset to use for subsequent mmap calls.h](j)}(h ``offset``h]j)}(hjbh]hoffset}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj\ubj)}(hhh]h)}(h1The fake offset to use for subsequent mmap calls.h]h1The fake offset to use for subsequent mmap calls.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1hhjwhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_queue_create (C struct)c.drm_panthor_queue_createhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_queue_createh]j)}(hstruct drm_panthor_queue_createh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hjʎhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjɎhKubj)}(hdrm_panthor_queue_createh]j)}(hjh]hdrm_panthor_queue_create}(hj܎hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj؎ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjɎhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjɎhKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjɎhKhjhhubj)}(hhh]h)}(hQueue creation arguments.h]hQueue creation arguments.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjɎhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhjfhNhNubj=)}(hXc**Definition**:: struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; }; **Members** ``priority`` Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority. ``pad`` Padding fields, MBZ. ``ringbuf_size`` Size of the ring buffer to allocate to this queue.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj`)}(h`struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; };h]h`struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; };}hj;sbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjLh]hMembers}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hhh](h)}(hn``priority`` Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority. h](j)}(h ``priority``h]j)}(hjkh]hpriority}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjeubj)}(hhh]h)}(h`Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority.h]h`Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1hhjhMhjbubh)}(h``pad`` Padding fields, MBZ. h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(hPadding fields, MBZ.h]hPadding fields, MBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjbubh)}(hC``ringbuf_size`` Size of the ring buffer to allocate to this queue.h](j)}(h``ringbuf_size``h]j)}(hjޏh]h ringbuf_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj܏ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj؏ubj)}(hhh]h)}(h2Size of the ring buffer to allocate to this queue.h]h2Size of the ring buffer to allocate to this queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhj؏ubeh}(h]h ]h"]h$]h&]uh1hhjhKhjbubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_group_priority (C enum)c.drm_panthor_group_priorityhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_priorityh]j)}(henum drm_panthor_group_priorityh](j)}(hj?h]henum}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhjEhKubj)}(hdrm_panthor_group_priorityh]j)}(hj2h]hdrm_panthor_group_priority}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ](jjeh"]h$]h&]jjuh1jhj4hhhjEhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj0hhhjEhKubah}(h]j+ah ](j j eh"]h$]h&]jj)jhuh1jhjEhKhj-hhubj)}(hhh]h)}(hScheduling group priorityh]hScheduling group priority}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjwhhubah}(h]h ]h"]h$]h&]uh1jhj-hhhjEhKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhjfhNhNubj=)}(hXG**Constants** ``PANTHOR_GROUP_PRIORITY_LOW`` Low priority group. ``PANTHOR_GROUP_PRIORITY_MEDIUM`` Medium priority group. ``PANTHOR_GROUP_PRIORITY_HIGH`` High priority group. Requires CAP_SYS_NICE or DRM_MASTER. ``PANTHOR_GROUP_PRIORITY_REALTIME`` Realtime priority group. Requires CAP_SYS_NICE or DRM_MASTER.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hhh](h)}(h3``PANTHOR_GROUP_PRIORITY_LOW`` Low priority group. h](j)}(h``PANTHOR_GROUP_PRIORITY_LOW``h]j)}(hjh]hPANTHOR_GROUP_PRIORITY_LOW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hLow priority group.h]hLow priority group.}(hjԐhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjАhMhjѐubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjАhMhjubh)}(h9``PANTHOR_GROUP_PRIORITY_MEDIUM`` Medium priority group. h](j)}(h!``PANTHOR_GROUP_PRIORITY_MEDIUM``h]j)}(hjh]hPANTHOR_GROUP_PRIORITY_MEDIUM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hMedium priority group.h]hMedium priority group.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hMhjubh)}(h[``PANTHOR_GROUP_PRIORITY_HIGH`` High priority group. Requires CAP_SYS_NICE or DRM_MASTER. h](j)}(h``PANTHOR_GROUP_PRIORITY_HIGH``h]j)}(hj-h]hPANTHOR_GROUP_PRIORITY_HIGH}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'ubj)}(hhh](h)}(hHigh priority group.h]hHigh priority group.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjCubh)}(h$Requires CAP_SYS_NICE or DRM_MASTER.h]h$Requires CAP_SYS_NICE or DRM_MASTER.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMhjCubeh}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1hhjBhMhjubh)}(hb``PANTHOR_GROUP_PRIORITY_REALTIME`` Realtime priority group. Requires CAP_SYS_NICE or DRM_MASTER.h](j)}(h#``PANTHOR_GROUP_PRIORITY_REALTIME``h]j)}(hjuh]hPANTHOR_GROUP_PRIORITY_REALTIME}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjoubj)}(hhh](h)}(hRealtime priority group.h]hRealtime priority group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h$Requires CAP_SYS_NICE or DRM_MASTER.h]h$Requires CAP_SYS_NICE or DRM_MASTER.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_group_create (C struct)c.drm_panthor_group_createhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_createh]j)}(hstruct drm_panthor_group_createh](j)}(hjh]hstruct}(hjޑhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjڑhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjڑhhhjhMubj)}(hdrm_panthor_group_createh]j)}(hjؑh]hdrm_panthor_group_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjڑhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj֑hhhjhMubah}(h]jёah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjӑhhubj)}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_CREATEh]h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_CREATE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjӑhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j8j8j8j9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; }; **Members** ``queues`` Array of drm_panthor_queue_create elements. ``max_compute_cores`` Maximum number of cores that can be used by compute jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **compute_core_mask**. ``max_fragment_cores`` Maximum number of cores that can be used by fragment jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **fragment_core_mask**. ``max_tiler_cores`` Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **tiler_core_mask**. ``priority`` Group priority (see enum drm_panthor_group_priority). ``pad`` Padding field, MBZ. ``compute_core_mask`` Mask encoding cores that can be used for compute jobs. This field must have at least **max_compute_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. ``fragment_core_mask`` Mask encoding cores that can be used for fragment jobs. This field must have at least **max_fragment_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. ``tiler_core_mask`` Mask encoding cores that can be used for tiler jobs. This field must have at least **max_tiler_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::tiler_present. ``vm_id`` VM ID to bind this group to. All submission to queues bound to this group will use this VM. ``group_handle`` Returned group handle. Passed back when submitting jobs or destroying a group.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubh:}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj<ubj`)}(hXAstruct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; };h]hXAstruct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; };}hj]sbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj<ubh)}(h **Members**h]h)}(hjnh]hMembers}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj<ubh)}(hhh](h)}(h7``queues`` Array of drm_panthor_queue_create elements. h](j)}(h ``queues``h]j)}(hjh]hqueues}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h+Array of drm_panthor_queue_create elements.h]h+Array of drm_panthor_queue_create elements.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h``max_compute_cores`` Maximum number of cores that can be used by compute jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **compute_core_mask**. h](j)}(h``max_compute_cores``h]j)}(hjƒh]hmax_compute_cores}(hjȒhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjĒubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h^Maximum number of cores that can be used by compute jobs across CS queues bound to this group.h]h^Maximum number of cores that can be used by compute jobs across CS queues bound to this group.}(hjߒhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjܒubh)}(hIMust be less or equal to the number of bits set in **compute_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjhhhNhNubh)}(h**compute_core_mask**h]hcompute_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjےhMhjܒubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjےhMhjubh)}(h``max_fragment_cores`` Maximum number of cores that can be used by fragment jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **fragment_core_mask**. h](j)}(h``max_fragment_cores``h]j)}(hj h]hmax_fragment_cores}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h_Maximum number of cores that can be used by fragment jobs across CS queues bound to this group.h]h_Maximum number of cores that can be used by fragment jobs across CS queues bound to this group.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj6ubh)}(hJMust be less or equal to the number of bits set in **fragment_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjHhhhNhNubh)}(h**fragment_core_mask**h]hfragment_core_mask}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHubh.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj5hMhj6ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj5hMhjubh)}(h``max_tiler_cores`` Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **tiler_core_mask**. h](j)}(h``max_tiler_cores``h]j)}(hjzh]hmax_tiler_cores}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjtubj)}(hhh](h)}(h]Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group.h]h]Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hGMust be less or equal to the number of bits set in **tiler_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjhhhNhNubh)}(h**tiler_core_mask**h]htiler_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hC``priority`` Group priority (see enum drm_panthor_group_priority). h](j)}(h ``priority``h]j)}(hjԓh]hpriority}(hj֓hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjғubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjΓubj)}(hhh]h)}(h5Group priority (see enum drm_panthor_group_priority).h]h5Group priority (see enum drm_panthor_group_priority).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjΓubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``pad`` Padding field, MBZ. h](j)}(h``pad``h]j)}(hj h]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hKhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj"hKhjubh)}(h``compute_core_mask`` Mask encoding cores that can be used for compute jobs. This field must have at least **max_compute_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. h](j)}(h``compute_core_mask``h]j)}(hjFh]hcompute_core_mask}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj@ubj)}(hhh](h)}(h6Mask encoding cores that can be used for compute jobs.h]h6Mask encoding cores that can be used for compute jobs.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj\ubh)}(h=This field must have at least **max_compute_cores** bits set.h](hThis field must have at least }(hjnhhhNhNubh)}(h**max_compute_cores**h]hmax_compute_cores}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnubh bits set.}(hjnhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj\ubh)}(hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.h]hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hMhj\ubeh}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1hhj[hMhjubh)}(h``fragment_core_mask`` Mask encoding cores that can be used for fragment jobs. This field must have at least **max_fragment_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. h](j)}(h``fragment_core_mask``h]j)}(hjh]hfragment_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h7Mask encoding cores that can be used for fragment jobs.h]h7Mask encoding cores that can be used for fragment jobs.}(hjȔhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjŔubh)}(h>This field must have at least **max_fragment_cores** bits set.h](hThis field must have at least }(hjהhhhNhNubh)}(h**max_fragment_cores**h]hmax_fragment_cores}(hjߔhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjהubh bits set.}(hjהhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjŔubh)}(hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.h]hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjĔhMhjŔubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjĔhMhjubh)}(h``tiler_core_mask`` Mask encoding cores that can be used for tiler jobs. This field must have at least **max_tiler_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::tiler_present. h](j)}(h``tiler_core_mask``h]j)}(hjh]htiler_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h4Mask encoding cores that can be used for tiler jobs.h]h4Mask encoding cores that can be used for tiler jobs.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj.ubh)}(h;This field must have at least **max_tiler_cores** bits set.h](hThis field must have at least }(hj@hhhNhNubh)}(h**max_tiler_cores**h]hmax_tiler_cores}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubh bits set.}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj.ubh)}(hLThe bits set here should also be set in drm_panthor_gpu_info::tiler_present.h]hLThe bits set here should also be set in drm_panthor_gpu_info::tiler_present.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMhj.ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj-hMhjubh)}(hg``vm_id`` VM ID to bind this group to. All submission to queues bound to this group will use this VM. h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj{ubj)}(hhh](h)}(hVM ID to bind this group to.h]hVM ID to bind this group to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM hjubh)}(h>All submission to queues bound to this group will use this VM.h]h>All submission to queues bound to this group will use this VM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h_``group_handle`` Returned group handle. Passed back when submitting jobs or destroying a group.h](j)}(h``group_handle``h]j)}(hjɕh]h group_handle}(hj˕hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjǕubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjÕubj)}(hhh]h)}(hNReturned group handle. Passed back when submitting jobs or destroying a group.h]hNReturned group handle. Passed back when submitting jobs or destroying a group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjޕhMhjߕubah}(h]h ]h"]h$]h&]uh1jhjÕubeh}(h]h ]h"]h$]h&]uh1hhjޕhMhjubeh}(h]h ]h"]h$]h&]uh1hhj<ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_panthor_group_destroy (C struct)c.drm_panthor_group_destroyhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_destroyh]j)}(h struct drm_panthor_group_destroyh](j)}(hjh]hstruct}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj/hMubj)}(hdrm_panthor_group_destroyh]j)}(hjh]hdrm_panthor_group_destroy}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj/hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj/hMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj/hMhjhhubj)}(hhh]h)}(h3Arguments passed to DRM_IOCTL_PANTHOR_GROUP_DESTROYh]h3Arguments passed to DRM_IOCTL_PANTHOR_GROUP_DESTROY}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjahhubah}(h]h ]h"]h$]h&]uh1jhjhhhj/hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j|j8j|j9j:j;uh1jhhhjfhNhNubj=)}(h**Definition**:: struct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; }; **Members** ``group_handle`` Group to destroy ``pad`` Padding field, MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj`)}(hLstruct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; };h]hLstruct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM hjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM%hjubh)}(hhh](h)}(h"``group_handle`` Group to destroy h](j)}(h``group_handle``h]j)}(hjіh]h group_handle}(hjӖhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϖubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj˖ubj)}(hhh]h)}(hGroup to destroyh]hGroup to destroy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj˖ubeh}(h]h ]h"]h$]h&]uh1hhjhMhjȖubh)}(h``pad`` Padding field, MBZ.h](j)}(h``pad``h]j)}(hj h]hpad}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjȖubeh}(h]h ]h"]4h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_queue_submit (C struct)c.drm_panthor_queue_submithNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_queue_submith]j)}(hstruct drm_panthor_queue_submith](j)}(hjh]hstruct}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`hhhjqhKubj)}(hdrm_panthor_queue_submith]j)}(hj^h]hdrm_panthor_queue_submit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj`hhhjqhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj\hhhjqhKubah}(h]jWah ](j j eh"]h$]h&]jj)jhuh1jhjqhKhjYhhubj)}(hhh]h)}(hJob submission arguments.h]hJob submission arguments.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM%hjhhubah}(h]h ]h"]h$]h&]uh1jhjYhhhjqhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; }; **Members** ``queue_index`` Index of the queue inside a group. ``stream_size`` Size of the command stream to execute. Must be 64-bit/8-byte aligned (the size of a CS instruction) Can be zero if stream_addr is zero too. When the stream size is zero, the queue submit serves as a synchronization point. ``stream_addr`` GPU address of the command stream to execute. Must be aligned on 64-byte. Can be zero is stream_size is zero too. ``latest_flush`` FLUSH_ID read at the time the stream was built. This allows cache flush elimination for the automatic flush+invalidate(all) done at submission time, which is needed to ensure the GPU doesn't get garbage when reading the indirect command stream buffers. If you want the cache flush to happen unconditionally, pass a zero here. Ignored when stream_size is zero. ``pad`` MBZ. ``syncs`` Array of struct drm_panthor_sync_op sync operations.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjʗhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjƗubh:}(hjƗhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM)hj—ubj`)}(hstruct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; };h]hstruct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM+hj—ubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM4hj—ubh)}(hhh](h)}(h3``queue_index`` Index of the queue inside a group. h](j)}(h``queue_index``h]j)}(hjh]h queue_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM,hj ubj)}(hhh]h)}(h"Index of the queue inside a group.h]h"Index of the queue inside a group.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hM,hj)ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj(hM,hj ubh)}(h``stream_size`` Size of the command stream to execute. Must be 64-bit/8-byte aligned (the size of a CS instruction) Can be zero if stream_addr is zero too. When the stream size is zero, the queue submit serves as a synchronization point. h](j)}(h``stream_size``h]j)}(hjLh]h stream_size}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM8hjFubj)}(hhh](h)}(h&Size of the command stream to execute.h]h&Size of the command stream to execute.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM1hjbubh)}(h``syncs`` Array of struct drm_panthor_sync_op sync operations.h](j)}(h ``syncs``h]j)}(hjh]hsyncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(h4Array of struct drm_panthor_sync_op sync operations.h]h4Array of struct drm_panthor_sync_op sync operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj ubeh}(h]h ]h"]h$]h&]uh1hhj—ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubh)}(h**Description**h]h)}(hjݙh]h Description}(hjߙhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjۙubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfhhubh)}(hThis is describing the userspace command stream to call from the kernel command stream ring-buffer. Queue submission is always part of a group submission, taking one or more jobs to submit to the underlying queues.h]hThis is describing the userspace command stream to call from the kernel command stream ring-buffer. Queue submission is always part of a group submission, taking one or more jobs to submit to the underlying queues.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM&hjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_group_submit (C struct)c.drm_panthor_group_submithNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_submith]j)}(hstruct drm_panthor_group_submith](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM-ubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj(hM-ubj)}(hdrm_panthor_group_submith]j)}(hjh]hdrm_panthor_group_submit}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj(hM-ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj(hM-ubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj(hM-hjhhubj)}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_SUBMITh]h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_SUBMIT}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMYhjZhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj(hM-ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7juj8juj9j:j;uh1jhhhjfhNhNubj=)}(hX.**Definition**:: struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; }; **Members** ``group_handle`` Handle of the group to queue jobs to. ``pad`` MBZ. ``queue_submits`` Array of drm_panthor_queue_submit objects.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}ubh:}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM]hjyubj`)}(h{struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; };h]h{struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM_hjyubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMehjyubh)}(hhh](h)}(h7``group_handle`` Handle of the group to queue jobs to. h](j)}(h``group_handle``h]j)}(hjʚh]h group_handle}(hj̚hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȚubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM\hjĚubj)}(hhh]h)}(h%Handle of the group to queue jobs to.h]h%Handle of the group to queue jobs to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjߚhM\hjubah}(h]h ]h"]h$]h&]uh1jhjĚubeh}(h]h ]h"]h$]h&]uh1hhjߚhM\hjubh)}(h ``pad`` MBZ. h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h<``queue_submits`` Array of drm_panthor_queue_submit objects.h](j)}(h``queue_submits``h]j)}(hj<h]h queue_submits}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj6ubj)}(hhh]h)}(h*Array of drm_panthor_queue_submit objects.h]h*Array of drm_panthor_queue_submit objects.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjRubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1hhjQhKhjubeh}(h]h ]h"]h$]h&]uh1hhjyubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&drm_panthor_group_state_flags (C enum)c.drm_panthor_group_state_flagshNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_state_flagsh]j)}(h"enum drm_panthor_group_state_flagsh](j)}(hj?h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hdrm_panthor_group_state_flagsh]j)}(hjh]hdrm_panthor_group_state_flags}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hGroup state flagsh]hGroup state flags}(hj؛hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMghj՛hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhjfhNhNubj=)}(hX**Constants** ``DRM_PANTHOR_GROUP_STATE_TIMEDOUT`` Group had unfinished jobs. When a group ends up with this flag set, no jobs can be submitted to its queues. ``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT`` Group had fatal faults. When a group ends up with this flag set, no jobs can be submitted to its queues. ``DRM_PANTHOR_GROUP_STATE_INNOCENT`` Group was killed during a reset caused by other groups. This flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMkhjubh)}(hhh](h)}(h``DRM_PANTHOR_GROUP_STATE_TIMEDOUT`` Group had unfinished jobs. When a group ends up with this flag set, no jobs can be submitted to its queues. h](j)}(h$``DRM_PANTHOR_GROUP_STATE_TIMEDOUT``h]j)}(hjh]h DRM_PANTHOR_GROUP_STATE_TIMEDOUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMphjubj)}(hhh](h)}(hGroup had unfinished jobs.h]hGroup had unfinished jobs.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMnhj/ubh)}(hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.h]hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMphj/ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj.hMphjubh)}(h``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT`` Group had fatal faults. When a group ends up with this flag set, no jobs can be submitted to its queues. h](j)}(h'``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT``h]j)}(hjah]h#DRM_PANTHOR_GROUP_STATE_FATAL_FAULT}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMuhj[ubj)}(hhh](h)}(hGroup had fatal faults.h]hGroup had fatal faults.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMshjwubh)}(hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.h]hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMuhjwubeh}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1hhjvhMuhjubh)}(h``DRM_PANTHOR_GROUP_STATE_INNOCENT`` Group was killed during a reset caused by other groups. This flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h](j)}(h$``DRM_PANTHOR_GROUP_STATE_INNOCENT``h]j)}(hjh]h DRM_PANTHOR_GROUP_STATE_INNOCENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM{hjubj)}(hhh](h)}(h7Group was killed during a reset caused by other groups.h]h7Group was killed during a reset caused by other groups.}(hjœhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMxhjubh)}(htThis flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h]htThis flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.}(hjќhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM{hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM{hjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&drm_panthor_group_get_state (C struct)c.drm_panthor_group_get_statehNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_get_stateh]j)}(h"struct drm_panthor_group_get_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhjhMubj)}(hdrm_panthor_group_get_stateh]j)}(hj h]hdrm_panthor_group_get_state}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h5Arguments passed to DRM_IOCTL_PANTHOR_GROUP_GET_STATEh]h5Arguments passed to DRM_IOCTL_PANTHOR_GROUP_GET_STATE}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjPhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jkj8jkj9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; }; **Members** ``group_handle`` Handle of the group to query state on ``state`` Combination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state. ``fatal_queues`` Bitmask of queues that faced fatal faults. ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjsubh:}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjoubj`)}(hwstruct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; };h]hwstruct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjoubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjoubh)}(hhh](h)}(h7``group_handle`` Handle of the group to query state on h](j)}(h``group_handle``h]j)}(hjh]h group_handle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h%Handle of the group to query state onh]h%Handle of the group to query state on}(hjٝhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj՝hMhj֝ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj՝hMhjubh)}(hS``state`` Combination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state. h](j)}(h ``state``h]j)}(hjh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(hHCombination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state.h]hHCombination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h<``fatal_queues`` Bitmask of queues that faced fatal faults. h](j)}(h``fatal_queues``h]j)}(hj3h]h fatal_queues}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj-ubj)}(hhh]h)}(h*Bitmask of queues that faced fatal faults.h]h*Bitmask of queues that faced fatal faults.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhKhjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1hhjHhKhjubh)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hjlh]hpad}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjoubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfhhubh)}(hbUsed to query the state of a group and decide whether a new group should be created to replace it.h]hbUsed to query the state of a group and decide whether a new group should be created to replace it.}(hjŞhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(drm_panthor_tiler_heap_create (C struct)c.drm_panthor_tiler_heap_createhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_tiler_heap_createh]j)}(h$struct drm_panthor_tiler_heap_createh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_panthor_tiler_heap_createh]j)}(hjh]hdrm_panthor_tiler_heap_create}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h7Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_CREATEh]h7Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj,hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jGj8jGj9j:j;uh1jhhhjfhNhNubj=)}(hXp**Definition**:: struct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; }; **Members** ``vm_id`` VM ID the tiler heap should be mapped to ``initial_chunk_count`` Initial number of chunks to allocate. Must be at least one. ``chunk_size`` Chunk size. Must be page-aligned and lie in the [128k:8M] range. ``max_chunks`` Maximum number of chunks that can be allocated. Must be at least **initial_chunk_count**. ``target_in_flight`` Maximum number of in-flight render passes. If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs. ``handle`` Returned heap handle. Passed back to DESTROY_TILER_HEAP. ``tiler_heap_ctx_gpu_va`` Returned heap GPU virtual address returned ``first_heap_chunk_gpu_va`` First heap chunk. The tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubh:}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjKubj`)}(hstruct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; };h]hstruct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; };}hjlsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjKubh)}(h **Members**h]h)}(hj}h]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjKubh)}(hhh](h)}(h3``vm_id`` VM ID the tiler heap should be mapped to h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h(VM ID the tiler heap should be mapped toh]h(VM ID the tiler heap should be mapped to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hT``initial_chunk_count`` Initial number of chunks to allocate. Must be at least one. h](j)}(h``initial_chunk_count``h]j)}(hj՟h]hinitial_chunk_count}(hjןhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjӟubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjϟubj)}(hhh]h)}(h;Initial number of chunks to allocate. Must be at least one.h]h;Initial number of chunks to allocate. Must be at least one.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjϟubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(hQ``chunk_size`` Chunk size. Must be page-aligned and lie in the [128k:8M] range. h](j)}(h``chunk_size``h]j)}(hjh]h chunk_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h Chunk size.h]h Chunk size.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj$ubh)}(h4Must be page-aligned and lie in the [128k:8M] range.h]h4Must be page-aligned and lie in the [128k:8M] range.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMhj$ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj#hMhjubh)}(hj``max_chunks`` Maximum number of chunks that can be allocated. Must be at least **initial_chunk_count**. h](j)}(h``max_chunks``h]j)}(hjVh]h max_chunks}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjPubj)}(hhh](h)}(h/Maximum number of chunks that can be allocated.h]h/Maximum number of chunks that can be allocated.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjlubh)}(h)Must be at least **initial_chunk_count**.h](hMust be at least }(hj~hhhNhNubh)}(h**initial_chunk_count**h]hinitial_chunk_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~ubh.}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjkhMhjlubeh}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1hhjkhMhjubh)}(h``target_in_flight`` Maximum number of in-flight render passes. If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs. h](j)}(h``target_in_flight``h]j)}(hjh]htarget_in_flight}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh](h)}(h*Maximum number of in-flight render passes.h]h*Maximum number of in-flight render passes.}(hjɠhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjƠubh)}(h{If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs.h]h{If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs.}(hjؠhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjƠubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjŠhMhjubh)}(hD``handle`` Returned heap handle. Passed back to DESTROY_TILER_HEAP. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(h8Returned heap handle. Passed back to DESTROY_TILER_HEAP.h]h8Returned heap handle. Passed back to DESTROY_TILER_HEAP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(hE``tiler_heap_ctx_gpu_va`` Returned heap GPU virtual address returned h](j)}(h``tiler_heap_ctx_gpu_va``h]j)}(hj2h]htiler_heap_ctx_gpu_va}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj,ubj)}(hhh]h)}(h*Returned heap GPU virtual address returnedh]h*Returned heap GPU virtual address returned}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhKhjHubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1hhjGhKhjubh)}(h``first_heap_chunk_gpu_va`` First heap chunk. The tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h](j)}(h``first_heap_chunk_gpu_va``h]j)}(hjkh]hfirst_heap_chunk_gpu_va}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjeubj)}(hhh](h)}(hFirst heap chunk.h]hFirst heap chunk.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hjThe tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h]hjThe tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1hhjKubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)drm_panthor_tiler_heap_destroy (C struct) c.drm_panthor_tiler_heap_destroyhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_tiler_heap_destroyh]j)}(h%struct drm_panthor_tiler_heap_destroyh](j)}(hjh]hstruct}(hjӡhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjϡhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjϡhhhjhMubj)}(hdrm_panthor_tiler_heap_destroyh]j)}(hj͡h]hdrm_panthor_tiler_heap_destroy}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjϡhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjˡhhhjhMubah}(h]jơah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjȡhhubj)}(hhh]h)}(h8Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROYh]h8Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjȡhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j-j8j-j9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; }; **Members** ``handle`` Handle of the tiler heap to destroy. Must be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE. ``pad`` Padding field, MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5ubh:}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj1ubj`)}(hKstruct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; };h]hKstruct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; };}hjRsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj1ubh)}(h **Members**h]h)}(hjch]hMembers}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj1ubh)}(hhh](h)}(h~``handle`` Handle of the tiler heap to destroy. Must be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|ubj)}(hhh](h)}(h$Handle of the tiler heap to destroy.h]h$Handle of the tiler heap to destroy.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hLMust be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE.h]hLMust be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1hhjhMhjyubh)}(h``pad`` Padding field, MBZ.h](j)}(h``pad``h]j)}(hjʢh]hpad}(hj̢hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȢubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjĢubj)}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjĢubeh}(h]h ]h"]h$]h&]uh1hhjߢhKhjyubeh}(h]h ]h"]h$]h&]uh1hhj1ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_bo_set_label (C struct)c.drm_panthor_bo_set_labelhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_set_labelh]j)}(hstruct drm_panthor_bo_set_labelh](j)}(hjh]hstruct}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj1hKubj)}(hdrm_panthor_bo_set_labelh]j)}(hjh]hdrm_panthor_bo_set_label}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj1hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj1hKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj1hKhjhhubj)}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_BO_SET_LABELh]h2Arguments passed to DRM_IOCTL_PANTHOR_BO_SET_LABEL}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjchhubah}(h]h ]h"]h$]h&]uh1jhjhhhj1hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j~j8j~j9j:j;uh1jhhhjfhNhNubj=)}(hX**Definition**:: struct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; }; **Members** ``handle`` Handle of the buffer object to label. ``pad`` MBZ. ``label`` User pointer to a NUL-terminated string Length cannot be greater than 4096h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj`)}(hVstruct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; };h]hVstruct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_h^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hhh](h)}(h1``handle`` Handle of the buffer object to label. h](j)}(h ``handle``h]j)}(hjӣh]hhandle}(hjգhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjѣubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjͣubj)}(hhh]h)}(h%Handle of the buffer object to label.h]h%Handle of the buffer object to label.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjͣubeh}(h]h ]h"]h$]h&]uh1hhjhMhjʣubh)}(h ``pad`` MBZ. h](j)}(h``pad``h]j)}(hj h]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjubj)}(hhh]h)}(hMBZ.h]hMBZ.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hKhj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj!hKhjʣubh)}(hU``label`` User pointer to a NUL-terminated string Length cannot be greater than 4096h](j)}(h ``label``h]j)}(hjEh]hlabel}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj?ubj)}(hhh](h)}(h'User pointer to a NUL-terminated stringh]h'User pointer to a NUL-terminated string}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj[ubh)}(h"Length cannot be greater than 4096h]h"Length cannot be greater than 4096}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj[ubeh}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1hhjZhMhjʣubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jDRM_IOCTL_PANTHOR (C macro)c.DRM_IOCTL_PANTHORhNtauh1jhjfhhhNhNubj)}(hhh](j)}(hDRM_IOCTL_PANTHORh]j)}(hDRM_IOCTL_PANTHORh]j)}(hDRM_IOCTL_PANTHORh]j)}(hjh]hDRM_IOCTL_PANTHOR}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubah}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjŤhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjŤhMhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhjŤhMubeh}(h]h ](j1macroeh"]h$]h&]j6j1j7jޤj8jޤj9j:j;uh1jhhhjfhNhNubh)}(h.``DRM_IOCTL_PANTHOR (__access, __id, __type)``h]j)}(hjh]h*DRM_IOCTL_PANTHOR (__access, __id, __type)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjfhhubj)}(hBuild a Panthor IOCTL number h]h)}(hBuild a Panthor IOCTL numberh]hBuild a Panthor IOCTL number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhj hMhjfhhubj=)}(hXJ**Parameters** ``__access`` Access type. Must be R, W or RW. ``__id`` One of the DRM_PANTHOR_xxx id. ``__type`` Suffix of the type being passed to the IOCTL. **Description** Don't use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead. **Return** An IOCTL number to be passed to ioctl() from userspace.h](h)}(h**Parameters**h]h)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hhh](h)}(h.``__access`` Access type. Must be R, W or RW. h](j)}(h ``__access``h]j)}(hj8h]h__access}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj2ubj)}(hhh]h)}(h Access type. Must be R, W or RW.h]h Access type. Must be R, W or RW.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhMhjNubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhjMhMhj/ubh)}(h(``__id`` One of the DRM_PANTHOR_xxx id. h](j)}(h``__id``h]j)}(hjqh]h__id}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjkubj)}(hhh]h)}(hOne of the DRM_PANTHOR_xxx id.h]hOne of the DRM_PANTHOR_xxx id.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1hhjhMhj/ubh)}(h9``__type`` Suffix of the type being passed to the IOCTL. h](j)}(h ``__type``h]j)}(hjh]h__type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj)}(hhh]h)}(h-Suffix of the type being passed to the IOCTL.h]h-Suffix of the type being passed to the IOCTL.}(hjåhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj/ubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hLDon't use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead.h]hNDon’t use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Return**h]h)}(hj h]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h7An IOCTL number to be passed to ioctl() from userspace.h]h7An IOCTL number to be passed to ioctl() from userspace.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjfhhhNhNubeh}(h]drm-panthor-uapiah ]h"]drm/panthor uapiah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h drm/xe uAPIh]h drm/xe uAPI}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhKubh)}(h.. _Xe Device Block Diagram:h]h}(h]h ]h"]h$]h&]hԌxe-device-block-diagramuh1hhKhj@hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hubh)}(h**Xe Device Block Diagram**h]h)}(hj_h]hXe Device Block Diagram}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]ubah}(h]j[ah ]h"]xe device block diagramah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhh}jrjQsh}j[jQsubh)}(hXThe diagram below represents a high-level simplification of a discrete GPU supported by the Xe driver. It shows some device components which are necessary to understand this API, as well as how their relations to each other. This diagram does not represent real hardware::h]hXThe diagram below represents a high-level simplification of a discrete GPU supported by the Xe driver. It shows some device components which are necessary to understand this API, as well as how their relations to each other. This diagram does not represent real hardware:}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubj`)}(hX┌──────────────────────────────────────────────────────────────────┐ │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ └─────────────────────────────Device0───────┬──────────────────────┘ │ ───────────────────────┴────────── PCI bush]hX┌──────────────────────────────────────────────────────────────────┐ │ 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│EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ └─────────────────────────────Device0───────┬──────────────────────┘ │ ───────────────────────┴────────── PCI bus'}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(h.. _Xe uAPI Overview:h]h}(h]h ]h"]h$]h&]hԌxe-uapi-overviewuh1hhK)hj@hhhj\ubh)}(h**Xe uAPI Overview**h]h)}(hjh]hXe uAPI Overview}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]jah ]h"]xe uapi overviewah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhK@hj@hhh}jjsh}jjsubh)}(hThis section aims to describe the Xe's IOCTL entries, its structs, and other Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related entries and usage.h]hThis section aims to describe the Xe’s IOCTL entries, its structs, and other Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related entries and usage.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKAhj@hhubh)}(hhh]h)}(hXList of supported IOCTLs: - :c:type:`DRM_IOCTL_XE_DEVICE_QUERY` - :c:type:`DRM_IOCTL_XE_GEM_CREATE` - :c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET` - :c:type:`DRM_IOCTL_XE_VM_CREATE` - :c:type:`DRM_IOCTL_XE_VM_DESTROY` - :c:type:`DRM_IOCTL_XE_VM_BIND` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY` - :c:type:`DRM_IOCTL_XE_EXEC` - :c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE` - :c:type:`DRM_IOCTL_XE_OBSERVATION` h](j)}(hList of supported IOCTLs:h]hList of supported IOCTLs:}(hjҦhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKRhjΦubj)}(hhh]jp )}(hhh](ju )}(h#:c:type:`DRM_IOCTL_XE_DEVICE_QUERY`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_DEVICE_QUERY}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j DRM_IOCTL_XE_DEVICE_QUERYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKFhjubah}(h]h ]h"]h$]h&]uh1hhj hKFhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_GEM_CREATE}(hj#hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j 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hjubju )}(h!:c:type:`DRM_IOCTL_XE_VM_DESTROY`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_VM_DESTROY}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j DRM_IOCTL_XE_VM_DESTROYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKJhjubah}(h]h ]h"]h$]h&]uh1hhjԧhKJhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_VM_BIND}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j DRM_IOCTL_XE_VM_BINDuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKKhjubah}(h]h ]h"]h$]h&]uh1hhjhKKhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h(:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_EXEC_QUEUE_CREATE}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype 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h]h)}(h":c:type:`DRM_IOCTL_XE_OBSERVATION`h]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_OBSERVATION}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j DRM_IOCTL_XE_OBSERVATIONuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKQhjubah}(h]h ]h"]h$]h&]uh1hhj3hKQhj ubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hj hKFhjubah}(h]h ]h"]h$]h&]uh1jhjΦubeh}(h]h ]h"]h$]h&]uh1hhjhKRhj˦ubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubh)}(h.. _Xe IOCTL Extensions:h]h}(h]h ]h"]h$]h&]hԌxe-ioctl-extensionsuh1hhK@hj@hhhj\ubh)}(h**Xe IOCTL Extensions**h]h)}(hjeh]hXe IOCTL Extensions}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjcubah}(h]jbah ]h"]xe ioctl extensionsah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKVhj@hhh}jxjXsh}jbjXsubh)}(hoBefore detailing the IOCTLs and its structs, it is important to highlight that every IOCTL in Xe is extensible.h]hoBefore detailing the IOCTLs and its structs, it is important to highlight that every IOCTL in Xe is extensible.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKzhj@hhubh)}(hX5Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan's approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.h]hX7Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan’s approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhK}hj@hhubh)}(hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. 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The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hExample chaining:h]hExample chaining:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubj`)}(hX/struct drm_xe_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct drm_xe_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct drm_xe_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };h]hX/struct drm_xe_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct drm_xe_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct drm_xe_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hTypically the struct drm_xe_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.h]hTypically the struct drm_xe_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.}(hjʩhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_user_extension (C struct)c.drm_xe_user_extensionhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_user_extensionh]j)}(hstruct drm_xe_user_extensionh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hdrm_xe_user_extensionh]j)}(hjh]hdrm_xe_user_extension}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h-Base class for defining a chain of extensionsh]h-Base class for defining a chain of extensions}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj1hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jLj8jLj9j:j;uh1jhhhj@hj\hNubj=)}(hX3**Definition**:: struct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; }; **Members** ``next_extension`` Pointer to the next struct drm_xe_user_extension, or zero if the end. ``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension. ``pad`` MBZ All undefined bits must be zero.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubh:}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjPubj`)}(hZstruct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; };h]hZstruct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; };}hjqsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjPubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjPubh)}(hhh](h)}(hY``next_extension`` Pointer to the next struct drm_xe_user_extension, or zero if the end. h](j)}(h``next_extension``h]j)}(hjh]hnext_extension}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hEPointer to the next struct drm_xe_user_extension, or zero if the end.h]hEPointer to the next struct drm_xe_user_extension, or zero if the end.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(hX``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension. h](j)}(h``name``h]j)}(hjڪh]hname}(hjܪhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjتubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjԪubj)}(hhh](h)}(hName of the extension.h]hName of the extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubh)}(h-Note that the name here is just some integer.h]h-Note that the name here is just some integer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubh)}(hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension.h]hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjԪubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h-``pad`` MBZ All undefined bits must be zero.h](j)}(h``pad``h]j)}(hj2h]hpad}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj,ubj)}(hhh](h)}(hMBZh]hMBZ}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjHubh)}(h All undefined bits must be zero.h]h All undefined bits must be zero.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjHubeh}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1hhjGhKhjubeh}(h]h ]h"]h$]h&]uh1hhjPubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_xe_ext_set_property (C struct)c.drm_xe_ext_set_propertyhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_ext_set_propertyh]j)}(hstruct drm_xe_ext_set_propertyh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hdrm_xe_ext_set_propertyh]j)}(hjh]hdrm_xe_ext_set_property}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hGeneric set property extensionh]hGeneric set property extension}(hjݫhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjګhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hXF**Definition**:: struct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; __u64 value; __u64 reserved[2]; }; **Members** ``base`` base user extension ``property`` property to set ``pad`` MBZ ``value`` property value ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj`)}(hstruct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; __u64 value; __u64 reserved[2]; };h]hstruct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; __u64 value; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubh)}(h **Members**h]h)}(hj+h]hMembers}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubh)}(hhh](h)}(h``base`` base user extension h](j)}(h``base``h]j)}(hjJh]hbase}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjDubj)}(hhh]h)}(hbase user extensionh]hbase user extension}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1hhj_hKhjAubh)}(h``property`` property to set h](j)}(h ``property``h]j)}(hjh]hproperty}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj}ubj)}(hhh]h)}(hproperty to seth]hproperty to set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1hhjhKhjAubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjլhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjѬhKhjҬubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjѬhKhjAubh)}(h``value`` property value h](j)}(h ``value``h]j)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hproperty valueh]hproperty value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hKhjAubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hj.h]hreserved}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj(ubj)}(hhh]h)}(hReservedh]hReserved}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1hhjChKhjAubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjqh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjoubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(h`A generic struct that allows any of the Xe's IOCTL to be extended with a set_property operation.h]hbA generic struct that allows any of the Xe’s IOCTL to be extended with a set_property operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'drm_xe_engine_class_instance (C struct)c.drm_xe_engine_class_instancehNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_engine_class_instanceh]j)}(h#struct drm_xe_engine_class_instanceh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hdrm_xe_engine_class_instanceh]j)}(hjh]hdrm_xe_engine_class_instance}(hjϭhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj˭ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hinstance of an engine classh]hinstance of an engine class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhj@hj\hNubj=)}(hXy**Definition**:: struct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0; #define DRM_XE_ENGINE_CLASS_COPY 1; #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2; #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; }; **Members** ``engine_class`` engine class id ``engine_instance`` engine instance id ``gt_id`` Unique ID of this GT within the PCI Device ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubj`)}(hXstruct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0; #define DRM_XE_ENGINE_CLASS_COPY 1; #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2; #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; };h]hXstruct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0; #define DRM_XE_ENGINE_CLASS_COPY 1; #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2; #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; };}hj.sbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubh)}(h **Members**h]h)}(hj?h]hMembers}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubh)}(hhh](h)}(h!``engine_class`` engine class id h](j)}(h``engine_class``h]j)}(hj^h]h engine_class}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjXubj)}(hhh]h)}(hengine class idh]hengine class id}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshKhjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1hhjshKhjUubh)}(h'``engine_instance`` engine instance id h](j)}(h``engine_instance``h]j)}(hjh]hengine_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hengine instance idh]hengine instance id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjUubh)}(h5``gt_id`` Unique ID of this GT within the PCI Device h](j)}(h ``gt_id``h]j)}(hjЮh]hgt_id}(hjҮhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjήubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjʮubj)}(hhh]h)}(h*Unique ID of this GT within the PCI Deviceh]h*Unique ID of this GT within the PCI Device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjʮubeh}(h]h ]h"]h$]h&]uh1hhjhKhjUubh)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hj h]hpad}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjUubeh}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjLh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hIt is returned as part of the **drm_xe_engine**, but it also is used as the input of engine selection for both **drm_xe_exec_queue_create** and **drm_xe_query_engine_cycles**h](hIt is returned as part of the }(hjbhhhNhNubh)}(h**drm_xe_engine**h]h drm_xe_engine}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbubh@, but it also is used as the input of engine selection for both }(hjbhhhNhNubh)}(h**drm_xe_exec_queue_create**h]hdrm_xe_exec_queue_create}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbubh and }(hjbhhhNhNubh)}(h**drm_xe_query_engine_cycles**h]hdrm_xe_query_engine_cycles}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hhh]h)}(hXiThe **engine_class** can be: - ``DRM_XE_ENGINE_CLASS_RENDER`` - ``DRM_XE_ENGINE_CLASS_COPY`` - ``DRM_XE_ENGINE_CLASS_VIDEO_DECODE`` - ``DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE`` - ``DRM_XE_ENGINE_CLASS_COMPUTE`` - ``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations. h](j)}(hThe **engine_class** can be:h](hThe }(hjhhhNhNubh)}(h**engine_class**h]h engine_class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]jp )}(hhh](ju )}(h``DRM_XE_ENGINE_CLASS_RENDER``h]h)}(hjӯh]j)}(hjӯh]hDRM_XE_ENGINE_CLASS_RENDER}(hjدhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjկubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjѯubah}(h]h ]h"]h$]h&]uh1jt hjίubju )}(h``DRM_XE_ENGINE_CLASS_COPY``h]h)}(hjh]j)}(hjh]hDRM_XE_ENGINE_CLASS_COPY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jt hjίubju )}(h$``DRM_XE_ENGINE_CLASS_VIDEO_DECODE``h]h)}(hjh]j)}(hjh]h DRM_XE_ENGINE_CLASS_VIDEO_DECODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jt hjίubju )}(h%``DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE``h]h)}(hj6h]j)}(hj6h]h!DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj4ubah}(h]h ]h"]h$]h&]uh1jt hjίubju )}(h``DRM_XE_ENGINE_CLASS_COMPUTE``h]h)}(hjWh]j)}(hjWh]hDRM_XE_ENGINE_CLASS_COMPUTE}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjUubah}(h]h ]h"]h$]h&]uh1jt hjίubju )}(h``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations. h]h)}(h``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations.h](j)}(h``DRM_XE_ENGINE_CLASS_VM_BIND``h]hDRM_XE_ENGINE_CLASS_VM_BIND}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubhr - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations.}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjvubah}(h]h ]h"]h$]h&]uh1jt hjίubeh}(h]h ]h"]h$]h&]j j uh1jo hjhKhj˯ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjʯhKhjubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_engine (C struct)c.drm_xe_enginehNtauh1jhj@hhhj\hNubj)}(hhh](j)}(h drm_xe_engineh]j)}(hstruct drm_xe_engineh](j)}(hjh]hstruct}(hjΰhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʰhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjܰhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʰhhhj۰hKubj)}(h drm_xe_engineh]j)}(hjȰh]h drm_xe_engine}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjʰhhhj۰hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjưhhhj۰hKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj۰hKhjðhhubj)}(hhh]h)}(hdescribe hardware engineh]hdescribe hardware engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jhjðhhhj۰hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j(j8j(j9j:j;uh1jhhhj@hj\hNubj=)}(h**Definition**:: struct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; }; **Members** ``instance`` The **drm_xe_engine_class_instance** ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubh:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj,ubj`)}(hbstruct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; };h]hbstruct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; };}hjMsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj,ubh)}(h **Members**h]h)}(hj^h]hMembers}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj,ubh)}(hhh](h)}(h2``instance`` The **drm_xe_engine_class_instance** h](j)}(h ``instance``h]j)}(hj}h]hinstance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjwubj)}(hhh]h)}(h$The **drm_xe_engine_class_instance**h](hThe }(hjhhhNhNubh)}(h **drm_xe_engine_class_instance**h]hdrm_xe_engine_class_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1hhjhKhjtubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjıh]hreserved}(hjƱhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj±ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjݱhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjڱubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjٱhKhjtubeh}(h]h ]h"]h$]h&]uh1hhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_query_engines (C struct)c.drm_xe_query_engineshNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_enginesh]j)}(hstruct drm_xe_query_enginesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj+hKubj)}(hdrm_xe_query_enginesh]j)}(hjh]hdrm_xe_query_engines}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj+hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj+hKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj+hKhjhhubj)}(hhh]h)}(hdescribe enginesh]hdescribe engines}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj]hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj+hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jxj8jxj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; }; **Members** ``num_engines`` number of engines returned in **engines** ``pad`` MBZ ``engines`` The returned engines for this deviceh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj|ubj`)}(hjstruct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; };h]hjstruct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj|ubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj|ubh)}(hhh](h)}(h:``num_engines`` number of engines returned in **engines** h](j)}(h``num_engines``h]j)}(hjͲh]h num_engines}(hjϲhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj˲ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjDzubj)}(hhh]h)}(h)number of engines returned in **engines**h](hnumber of engines returned in }(hjhhhNhNubh)}(h **engines**h]hengines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjDzubeh}(h]h ]h"]h$]h&]uh1hhjhM hjIJubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj)hKhjIJubh)}(h0``engines`` The returned engines for this deviceh](j)}(h ``engines``h]j)}(hjMh]hengines}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjGubj)}(hhh]h)}(h$The returned engines for this deviceh]h$The returned engines for this device}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjcubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1hhjbhKhjIJubeh}(h]h ]h"]h$]h&]uh1hhj|ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hIf a query is made with a struct **drm_xe_device_query** where .query is equal to ``DRM_XE_DEVICE_QUERY_ENGINES``, then the reply uses an array of struct **drm_xe_query_engines** in .data.h](h!If a query is made with a struct }(hjhhhNhNubh)}(h**drm_xe_device_query**h]hdrm_xe_device_query}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh where .query is equal to }(hjhhhNhNubj)}(h``DRM_XE_DEVICE_QUERY_ENGINES``h]hDRM_XE_DEVICE_QUERY_ENGINES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh), then the reply uses an array of struct }(hjhhhNhNubh)}(h**drm_xe_query_engines**h]hdrm_xe_query_engines}(hjҳhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh in .data.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_memory_class (C enum)c.drm_xe_memory_classhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_memory_classh]j)}(henum drm_xe_memory_classh](j)}(hj?h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM ubj)}(hdrm_xe_memory_classh]j)}(hjh]hdrm_xe_memory_class}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM ubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhM hjhhubj)}(hhh]h)}(hSupported memory classes.h]hSupported memory classes.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjChhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7j^j8j^j9j:j;uh1jhhhj@hj\hNubj=)}(h**Constants** ``DRM_XE_MEM_REGION_CLASS_SYSMEM`` Represents system memory. ``DRM_XE_MEM_REGION_CLASS_VRAM`` On discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h](h)}(h **Constants**h]h)}(hjhh]h Constants}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjbubh)}(hhh](h)}(h=``DRM_XE_MEM_REGION_CLASS_SYSMEM`` Represents system memory. h](j)}(h"``DRM_XE_MEM_REGION_CLASS_SYSMEM``h]j)}(hjh]hDRM_XE_MEM_REGION_CLASS_SYSMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hRepresents system memory.h]hRepresents system memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj~ubh)}(h``DRM_XE_MEM_REGION_CLASS_VRAM`` On discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h](j)}(h ``DRM_XE_MEM_REGION_CLASS_VRAM``h]j)}(hjh]hDRM_XE_MEM_REGION_CLASS_VRAM}(hj´hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hOn discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h]hOn discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.}(hjٴhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjִubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjմhMhj~ubeh}(h]h ]h"]h$]h&]uh1hhjbubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_mem_region (C struct)c.drm_xe_mem_regionhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_mem_regionh]j)}(hstruct drm_xe_mem_regionh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM%ubj)}(h h]h }(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj'hM%ubj)}(hdrm_xe_mem_regionh]j)}(hjh]hdrm_xe_mem_region}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj'hM%ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj'hM%ubah}(h]j ah ](j j eh"]h$]h&]jj)jhuh1jhj'hM%hjhhubj)}(hhh]h)}(h-Describes some region as known to the driver.h]h-Describes some region as known to the driver.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM"hjYhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj'hM%ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jtj8jtj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; }; **Members** ``mem_class`` The memory class describing this region. See enum drm_xe_memory_class for supported values. ``instance`` The unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE` ``min_page_size`` Min page-size in bytes for this region. When the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met. ``total_size`` The usable size in bytes for this region. ``used`` Estimate of the memory used in bytes for this region. Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal zero. ``cpu_visible_size`` How much of this region can be CPU accessed, in bytes. This will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system. On systems without small BAR (full BAR), the probed_size will always equal the **total_size**, since all of it will be CPU accessible. Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero). ``cpu_visible_used`` Estimate of CPU visible memory used, in bytes. Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal zero. Note this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero). ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|ubh:}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM&hjxubj`)}(hstruct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; };h]hstruct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM(hjxubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM3hjxubh)}(hhh](h)}(hk``mem_class`` The memory class describing this region. See enum drm_xe_memory_class for supported values. h](j)}(h ``mem_class``h]j)}(hjɵh]h mem_class}(hj˵hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjǵubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM*hjõubj)}(hhh](h)}(h(The memory class describing this region.h]h(The memory class describing this region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM(hjߵubh)}(h2See enum drm_xe_memory_class for supported values.h]h2See enum drm_xe_memory_class for supported values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj޵hM*hjߵubeh}(h]h ]h"]h$]h&]uh1jhjõubeh}(h]h ]h"]h$]h&]uh1hhj޵hM*hjubh)}(h``instance`` The unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE` h](j)}(h ``instance``h]j)}(hjh]hinstance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM0hj ubj)}(hhh]h)}(hThe unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE`h](hgThe unique ID for this region, which serves as the index in the placement bitmask used as argument for }(hj*hhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]j)}(hj4h]hDRM_IOCTL_XE_GEM_CREATE}(hj6hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j DRM_IOCTL_XE_GEM_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM.hj*ubeh}(h]h ]h"]h$]h&]uh1hhjQhM.hj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj&hM0hjubh)}(hX``min_page_size`` Min page-size in bytes for this region. When the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met. h](j)}(h``min_page_size``h]j)}(hjjh]h min_page_size}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM>hjdubj)}(hhh](h)}(h'Min page-size in bytes for this region.h]h'Min page-size in bytes for this region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM4hjubh)}(hXWhen the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met.h](hXWhen the kernel allocates memory for this region, the underlying pages will be at least }(hjhhhNhNubh)}(h**min_page_size**h]h min_page_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhX9 in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return }(hjhhhNhNubj)}(h ``-EINVAL``h]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh' if alignment restrictions are not met.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM6hjubeh}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1hhjhM>hjubh)}(h9``total_size`` The usable size in bytes for this region. h](j)}(h``total_size``h]j)}(hj׶h]h total_size}(hjٶhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjնubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMBhjѶubj)}(hhh]h)}(h)The usable size in bytes for this region.h]h)The usable size in bytes for this region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMBhjubah}(h]h ]h"]h$]h&]uh1jhjѶubeh}(h]h ]h"]h$]h&]uh1hhjhMBhjubh)}(h``used`` Estimate of the memory used in bytes for this region. Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal zero. h](j)}(h``used``h]j)}(hjh]hused}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMJhj ubj)}(hhh](h)}(h5Estimate of the memory used in bytes for this region.h]h5Estimate of the memory used in bytes for this region.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMFhj&ubh)}(hvRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal zero.h]hvRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal zero.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMHhj&ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj%hMJhjubh)}(hX``cpu_visible_size`` How much of this region can be CPU accessed, in bytes. This will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system. On systems without small BAR (full BAR), the probed_size will always equal the **total_size**, since all of it will be CPU accessible. Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero). h](j)}(h``cpu_visible_size``h]j)}(hjYh]hcpu_visible_size}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM\hjSubj)}(hhh](h)}(h6How much of this region can be CPU accessed, in bytes.h]h6How much of this region can be CPU accessed, in bytes.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMNhjoubh)}(hThis will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system.h](hThis will always be <= }(hjhhhNhNubh)}(h**total_size**h]h total_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhd, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than }(hjhhhNhNubh)}(h**total_size**h]h total_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh0 then this is referred to as a small BAR system.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMQhjoubh)}(hOn systems without small BAR (full BAR), the probed_size will always equal the **total_size**, since all of it will be CPU accessible.h](hOOn systems without small BAR (full BAR), the probed_size will always equal the }(hjhhhNhNubh)}(h**total_size**h]h total_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh), since all of it will be CPU accessible.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMVhjoubh)}(h{Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero).h]h{Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero).}(hjշhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMZhjoubeh}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1hhjnhM\hjubh)}(hX?``cpu_visible_used`` Estimate of CPU visible memory used, in bytes. Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal zero. Note this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero). h](j)}(h``cpu_visible_used``h]j)}(hjh]hcpu_visible_used}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMghjubj)}(hhh](h)}(h.Estimate of CPU visible memory used, in bytes.h]h.Estimate of CPU visible memory used, in bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM`hj ubh)}(hRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal zero. Note this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero).h]hRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal zero. Note this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMchj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hMghjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hj?h]hreserved}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj9ubj)}(hhh]h)}(hReservedh]hReserved}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjUubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1hhjThKhjubeh}(h]h ]h"]h$]h&]uh1hhjxubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_xe_query_mem_regions (C struct)c.drm_xe_query_mem_regionshNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_mem_regionsh]j)}(hstruct drm_xe_query_mem_regionsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hdrm_xe_query_mem_regionsh]j)}(hjh]hdrm_xe_query_mem_regions}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hdescribe memory regionsh]hdescribe memory regions}(hj۸hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMnhjظhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX=**Definition**:: struct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; }; **Members** ``num_mem_regions`` number of memory regions returned in **mem_regions** ``pad`` MBZ ``mem_regions`` The returned memory regions for this deviceh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMrhjubj`)}(hzstruct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; };h]hzstruct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMthjubh)}(h **Members**h]h)}(hj)h]hMembers}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMzhjubh)}(hhh](h)}(hI``num_mem_regions`` number of memory regions returned in **mem_regions** h](j)}(h``num_mem_regions``h]j)}(hjHh]hnum_mem_regions}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMuhjBubj)}(hhh]h)}(h4number of memory regions returned in **mem_regions**h](h%number of memory regions returned in }(hjahhhNhNubh)}(h**mem_regions**h]h mem_regions}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaubeh}(h]h ]h"]h$]h&]uh1hhj]hMuhj^ubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1hhj]hMuhj?ubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj?ubh)}(h;``mem_regions`` The returned memory regions for this deviceh](j)}(h``mem_regions``h]j)}(hjȹh]h mem_regions}(hjʹhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjƹubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj¹ubj)}(hhh]h)}(h+The returned memory regions for this deviceh]h+The returned memory regions for this device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj޹ubah}(h]h ]h"]h$]h&]uh1jhj¹ubeh}(h]h ]h"]h$]h&]uh1hhjݹhKhj?ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses struct drm_xe_query_mem_regions in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses struct drm_xe_query_mem_regions in .data.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMohj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_query_config (C struct)c.drm_xe_query_confighNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_configh]j)}(hstruct drm_xe_query_configh](j)}(hjh]hstruct}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMvubj)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEhhhjVhMvubj)}(hdrm_xe_query_configh]j)}(hjCh]hdrm_xe_query_config}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubah}(h]h ](jjeh"]h$]h&]jjuh1jhjEhhhjVhMvubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjAhhhjVhMvubah}(h]j<ah ](j j eh"]h$]h&]jj)jhuh1jhjVhMvhj>hhubj)}(hhh]h)}(h!describe the device configurationh]h!describe the device configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hjhhubah}(h]h ]h"]h$]h&]uh1jhj>hhhjVhMvubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; }; **Members** ``num_params`` number of parameters returned in info ``pad`` MBZ ``info`` array of elements containing the config infoh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hX3struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; };h]hX3struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; };}hjȺsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjٺh]hMembers}(hjۺhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj׺ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h5``num_params`` number of parameters returned in info h](j)}(h``num_params``h]j)}(hjh]h num_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h%number of parameters returned in infoh]h%number of parameters returned in info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hMhjubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj1h]hpad}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj+ubj)}(hhh]h)}(hMBZh]hMBZ}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhKhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1hhjFhKhjubh)}(h5``info`` array of elements containing the config infoh](j)}(h``info``h]j)}(hjjh]hinfo}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjdubj)}(hhh]h)}(h,array of elements containing the config infoh]h,array of elements containing the config info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses struct drm_xe_query_config in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses struct drm_xe_query_config in .data.}(hjûhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hhh]h)}(hXVThe index in **info** can be: - ``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits) - ``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list below - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAM - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring support - ``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64K - ``DRM_XE_QUERY_CONFIG_VA_BITS`` - Maximum bits of a virtual address - ``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priority h](j)}(hThe index in **info** can be:h](h The index in }(hjٻhhhNhNubh)}(h**info**h]hinfo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjٻubh can be:}(hjٻhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjջubj)}(hhh]jp )}(hhh](ju )}(hk``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits)h]h)}(hk``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits)h](j)}(h)``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID``h]h%DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhB - Device ID (lower 16 bits) and the device revision (next 8 bits)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hX``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list below - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAM - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring supporth](h)}(hY``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list belowh](j)}(h``DRM_XE_QUERY_CONFIG_FLAGS``h]hDRM_XE_QUERY_CONFIG_FLAGS}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubh< - Flags describing the device configuration, see list below}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj'ubjp )}(hhh](ju )}(hQ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAMh]h)}(hQ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAMh](j)}(h%``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM``h]h!DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubh, - Flag is set if the device has usable VRAM}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjKubah}(h]h ]h"]h$]h&]uh1jt hjHubju )}(he``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint supporth]h)}(he``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint supporth](j)}(h,``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY``h]h(DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubh9 - Flag is set if the device has low latency hint support}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjrubah}(h]h ]h"]h$]h&]uh1jt hjHubju )}(hn``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring supporth]h)}(hn``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring supporth](j)}(h0``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR``h]h,DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh> - Flag is set if the device has CPU address mirroring support}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjHubeh}(h]h ]h"]h$]h&]j j uh1jo hjkhMhj'ubeh}(h]h ]h"]h$]h&]uh1jt hjubju )}(hs``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64Kh]h)}(hs``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64Kh](j)}(h%``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT``h]h!DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT}(hjԼhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjмubhN - Minimal memory alignment required by this device, typically SZ_4K or SZ_64K}(hjмhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj̼ubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hC``DRM_XE_QUERY_CONFIG_VA_BITS`` - Maximum bits of a virtual addressh]h)}(hjh](j)}(h``DRM_XE_QUERY_CONFIG_VA_BITS``h]hDRM_XE_QUERY_CONFIG_VA_BITS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh$ - Maximum bits of a virtual address}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hh``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priority h]h)}(hd``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priorityh](j)}(h/``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY``h]h+DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh5 - Value of the highest available exec queue priority}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hj hMhjubah}(h]h ]h"]h$]h&]uh1jhjջubeh}(h]h ]h"]h$]h&]uh1hhjhMhjһubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_gt (C struct) c.drm_xe_gthNtauh1jhj@hhhj\hNubj)}(hhh](j)}(h drm_xe_gth]j)}(hstruct drm_xe_gth](j)}(hjh]hstruct}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhhj~hMubj)}(h drm_xe_gth]j)}(hjkh]h drm_xe_gt}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjmhhhj~hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjihhhj~hMubah}(h]jdah ](j j eh"]h$]h&]jj)jhuh1jhj~hMhjfhhubj)}(hhh]h)}(hdescribe an individual GT.h]hdescribe an individual GT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjfhhhj~hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j˽j8j˽j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; }; **Members** ``type`` GT type: Main or Media ``tile_id`` Tile ID where this GT lives (Information only) ``gt_id`` Unique ID of this GT within the PCI Device ``pad`` MBZ ``reference_clock`` A clock frequency for timestamp ``near_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``far_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``ip_ver_major`` Graphics/media IP major version on GMD_ID platforms ``ip_ver_minor`` Graphics/media IP minor version on GMD_ID platforms ``ip_ver_rev`` Graphics/media IP revision version on GMD_ID platforms ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj׽hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjӽubh:}(hjӽhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjϽubj`)}(hXstruct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; };h]hXstruct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjϽubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjϽubh)}(hhh](h)}(h ``type`` GT type: Main or Media h](j)}(h``type``h]j)}(hj h]htype}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hGT type: Main or Mediah]hGT type: Main or Media}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj5hMhjubh)}(h;``tile_id`` Tile ID where this GT lives (Information only) h](j)}(h ``tile_id``h]j)}(hjYh]htile_id}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjSubj)}(hhh]h)}(h.Tile ID where this GT lives (Information only)h]h.Tile ID where this GT lives (Information only)}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhKhjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1hhjnhKhjubh)}(h5``gt_id`` Unique ID of this GT within the PCI Device h](j)}(h ``gt_id``h]j)}(hjh]hgt_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h*Unique ID of this GT within the PCI Deviceh]h*Unique ID of this GT within the PCI Device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj˾h]hpad}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjɾubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjžubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjžubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h4``reference_clock`` A clock frequency for timestamp h](j)}(h``reference_clock``h]j)}(hjh]hreference_clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hA clock frequency for timestamph]hA clock frequency for timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(hXV``near_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h``near_mem_regions``h]j)}(hj=h]hnear_mem_regions}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj7ubj)}(hhh]h)}(hX@Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h]hXDBit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1hhjRhMhjubh)}(hX``far_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h``far_mem_regions``h]j)}(hjwh]hfar_mem_regions}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjqubj)}(hhh]h)}(hXBit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h](hBit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the }(hjhhhNhNubh)}(h**near_mem_regions**h]hnear_mem_regions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhX9. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hE``ip_ver_major`` Graphics/media IP major version on GMD_ID platforms h](j)}(h``ip_ver_major``h]j)}(hjÿh]h ip_ver_major}(hjſhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h3Graphics/media IP major version on GMD_ID platformsh]h3Graphics/media IP major version on GMD_ID platforms}(hjܿhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjؿhKhjٿubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjؿhKhjubh)}(hE``ip_ver_minor`` Graphics/media IP minor version on GMD_ID platforms h](j)}(h``ip_ver_minor``h]j)}(hjh]h ip_ver_minor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h3Graphics/media IP minor version on GMD_ID platformsh]h3Graphics/media IP minor version on GMD_ID platforms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(hF``ip_ver_rev`` Graphics/media IP revision version on GMD_ID platforms h](j)}(h``ip_ver_rev``h]j)}(hj5h]h ip_ver_rev}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj/ubj)}(hhh]h)}(h6Graphics/media IP revision version on GMD_ID platformsh]h6Graphics/media IP revision version on GMD_ID platforms}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhKhjKubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1hhjJhKhjubh)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjnh]hpad2}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjhubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjϽubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hTo be used with drm_xe_query_gt_list, which will return a list with all the existing GT individual descriptions. Graphics Technology (GT) is a subset of a GPU/tile that is responsible for implementing graphics and/or media operations.h]hTo be used with drm_xe_query_gt_list, which will return a list with all the existing GT individual descriptions. Graphics Technology (GT) is a subset of a GPU/tile that is responsible for implementing graphics and/or media operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hhh]h)}(hbThe index in **type** can be: - ``DRM_XE_QUERY_GT_TYPE_MAIN`` - ``DRM_XE_QUERY_GT_TYPE_MEDIA`` h](j)}(hThe index in **type** can be:h](h The index in }(hjhhhNhNubh)}(h**type**h]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]jp )}(hhh](ju )}(h``DRM_XE_QUERY_GT_TYPE_MAIN``h]h)}(hj?h]j)}(hj?h]hDRM_XE_QUERY_GT_TYPE_MAIN}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj=ubah}(h]h ]h"]h$]h&]uh1jt hj:ubju )}(h"``DRM_XE_QUERY_GT_TYPE_MEDIA`` h]h)}(h``DRM_XE_QUERY_GT_TYPE_MEDIA``h]j)}(hjdh]hDRM_XE_QUERY_GT_TYPE_MEDIA}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj^ubah}(h]h ]h"]h$]h&]uh1jt hj:ubeh}(h]h ]h"]h$]h&]j j uh1jo hjWhMhj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj6hMhjubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_query_gt_list (C struct)c.drm_xe_query_gt_listhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_gt_listh]j)}(hstruct drm_xe_query_gt_listh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_query_gt_listh]j)}(hjh]hdrm_xe_query_gt_list}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h!A list with GT description items.h]h!A list with GT description items.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; }; **Members** ``num_gt`` number of GT items returned in gt_list ``pad`` MBZ ``gt_list`` The GT list returned for this deviceh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hastruct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; };h]hastruct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; };}hj0sbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjAh]hMembers}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h2``num_gt`` number of GT items returned in gt_list h](j)}(h ``num_gt``h]j)}(hj`h]hnum_gt}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjZubj)}(hhh]h)}(h&number of GT items returned in gt_listh]h&number of GT items returned in gt_list}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1hhjuhMhjWubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjWubh)}(h0``gt_list`` The GT list returned for this deviceh](j)}(h ``gt_list``h]j)}(hjh]hgt_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h$The GT list returned for this deviceh]h$The GT list returned for this device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjWubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct drm_xe_query_gt_list in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct drm_xe_query_gt_list in .data.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_xe_query_topology_mask (C struct)c.drm_xe_query_topology_maskhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_topology_maskh]j)}(h!struct drm_xe_query_topology_maskh](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhhj`hMubj)}(hdrm_xe_query_topology_maskh]j)}(hjMh]hdrm_xe_query_topology_mask}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ](jjeh"]h$]h&]jjuh1jhjOhhhj`hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjKhhhj`hMubah}(h]jFah ](j j eh"]h$]h&]jj)jhuh1jhj`hMhjHhhubj)}(hhh]h)}(h"describe the topology mask of a GTh]h"describe the topology mask of a GT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjHhhhj`hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX$**Definition**:: struct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; }; **Members** ``gt_id`` GT ID the mask is associated with ``type`` type of mask ``num_bytes`` number of bytes in requested mask ``mask`` little-endian mask of **num_bytes**h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hXDstruct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; };h]hXDstruct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h,``gt_id`` GT ID the mask is associated with h](j)}(h ``gt_id``h]j)}(hjh]hgt_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h!GT ID the mask is associated withh]h!GT ID the mask is associated with}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h``type`` type of mask h](j)}(h``type``h]j)}(hj;h]htype}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj5ubj)}(hhh]h)}(h type of maskh]h type of mask}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhKhjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1hhjPhKhjubh)}(h0``num_bytes`` number of bytes in requested mask h](j)}(h ``num_bytes``h]j)}(hjth]h num_bytes}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjnubj)}(hhh]h)}(h!number of bytes in requested maskh]h!number of bytes in requested mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h,``mask`` little-endian mask of **num_bytes**h](j)}(h``mask``h]j)}(hjh]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h#little-endian mask of **num_bytes**h](hlittle-endian mask of }(hjhhhNhNubh)}(h **num_bytes**h]h num_bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hXThis is the hardware topology which reflects the internal physical structure of the GPU.h]hXThis is the hardware topology which reflects the internal physical structure of the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses struct drm_xe_query_topology_mask in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses struct drm_xe_query_topology_mask in .data.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hhh]h)}(hXYThe **type** can be: - ``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry. - ``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute. - ``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware. - ``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs. - ``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs. h](j)}(hThe **type** can be:h](hThe }(hj9hhhNhNubh)}(h**type**h]htype}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9ubh can be:}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj5ubj)}(hhh]jp )}(hhh](ju )}(hX``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry.h]h)}(hX``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry.h](j)}(h``DRM_XE_TOPO_DSS_GEOMETRY``h]hDRM_XE_TOPO_DSS_GEOMETRY}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubh - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: }(hjdhhhNhNubj)}(h+``DSS_GEOMETRY ff ff ff ff 00 00 00 00``h]h'DSS_GEOMETRY ff ff ff ff 00 00 00 00}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubh) means 32 DSS are available for geometry.}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj`ubah}(h]h ]h"]h$]h&]uh1jt hj]ubju )}(h``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute.h]h)}(h``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute.h](j)}(h``DRM_XE_TOPO_DSS_COMPUTE``h]hDRM_XE_TOPO_DSS_COMPUTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: }(hjhhhNhNubj)}(h*``DSS_COMPUTE ff ff ff ff 00 00 00 00``h]h&DSS_COMPUTE ff ff ff ff 00 00 00 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh( means 32 DSS are available for compute.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hj]ubju )}(h``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.h]h)}(h``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.h](j)}(h``DRM_XE_TOPO_L3_BANK``h]hDRM_XE_TOPO_L3_BANK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hj]ubju )}(hX0``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs.h]h)}(hX0``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs.h](j)}(h``DRM_XE_TOPO_EU_PER_DSS``h]hDRM_XE_TOPO_EU_PER_DSS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: }(hjhhhNhNubj)}(h)``EU_PER_DSS ff ff 00 00 00 00 00 00``h]h%EU_PER_DSS ff ff 00 00 00 00 00 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh^ means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn’t have SIMD8 EUs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubah}(h]h ]h"]h$]h&]uh1jt hj]ubju )}(hXK``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs. h]h)}(hXG``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs.h](j)}(h!``DRM_XE_TOPO_SIMD16_EU_PER_DSS``h]hDRM_XE_TOPO_SIMD16_EU_PER_DSS}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubh - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: }(hj6hhhNhNubj)}(h0``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00``h]h,SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubh` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn’t have SIMD16 EUs.}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj2ubah}(h]h ]h"]h$]h&]uh1jt hj]ubeh}(h]h ]h"]h$]h&]j j uh1jo hjhMhjZubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1hhjYhMhj2ubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_xe_query_engine_cycles (C struct)c.drm_xe_query_engine_cycleshNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_engine_cyclesh]j)}(h!struct drm_xe_query_engine_cyclesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_query_engine_cyclesh]j)}(hjh]hdrm_xe_query_engine_cycles}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h correlate CPU and GPU timestampsh]h correlate CPU and GPU timestamps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM-hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; }; **Members** ``eci`` This is input by the user and is the engine for which command streamer cycles is queried. ``clockid`` This is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. ``width`` Width of the engine cycle counter in bits. ``engine_cycles`` Engine cycles as read from its register at 0x358 offset. ``cpu_timestamp`` CPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user. ``cpu_delta`` Time delta in ns captured around reading the lower dword of the engine_cycles register.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM1hjubj`)}(hstruct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; };h]hstruct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM3hjubh)}(h **Members**h]h)}(hj,h]hMembers}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM<hjubh)}(hhh](h)}(hb``eci`` This is input by the user and is the engine for which command streamer cycles is queried. h](j)}(h``eci``h]j)}(hjKh]heci}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=hjEubj)}(hhh]h)}(hYThis is input by the user and is the engine for which command streamer cycles is queried.h]hYThis is input by the user and is the engine for which command streamer cycles is queried.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM<hjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1hhj`hM=hjBubh)}(h``clockid`` This is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. h](j)}(h ``clockid``h]j)}(hjh]hclockid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMEhjubj)}(hhh]h)}(hThis is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.h]hThis is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMBhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMEhjBubh)}(h5``width`` Width of the engine cycle counter in bits. h](j)}(h ``width``h]j)}(hjh]hwidth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h*Width of the engine cycle counter in bits.h]h*Width of the engine cycle counter in bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjBubh)}(hK``engine_cycles`` Engine cycles as read from its register at 0x358 offset. h](j)}(h``engine_cycles``h]j)}(hjh]h engine_cycles}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMNhjubj)}(hhh]h)}(h8Engine cycles as read from its register at 0x358 offset.h]h8Engine cycles as read from its register at 0x358 offset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hMNhjBubh)}(h``cpu_timestamp`` CPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user. h](j)}(h``cpu_timestamp``h]j)}(hj2h]h cpu_timestamp}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMUhj,ubj)}(hhh]h)}(hCPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user.h]hCPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMShjHubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1hhjGhMUhjBubh)}(he``cpu_delta`` Time delta in ns captured around reading the lower dword of the engine_cycles register.h](j)}(h ``cpu_delta``h]j)}(hjlh]h cpu_delta}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMZhjfubj)}(hhh]h)}(hWTime delta in ns captured around reading the lower dword of the engine_cycles register.h]hWTime delta in ns captured around reading the lower dword of the engine_cycles register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMZhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1hhjhMZhjBubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM^hj@hhubh)}(hXIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles in .data. struct drm_xe_query_engine_cycles is allocated by the user and .data points to this allocated structure.h]hXIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles in .data. struct drm_xe_query_engine_cycles is allocated by the user and .data points to this allocated structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM.hj@hhubh)}(hThe query returns the engine cycles, which along with GT's **reference_clock**, can be used to calculate the engine timestamp. In addition the query returns a set of cpu timestamps that indicate when the command streamer cycle count was captured.h](h=The query returns the engine cycles, which along with GT’s }(hjhhhNhNubh)}(h**reference_clock**h]hreference_clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh, can be used to calculate the engine timestamp. In addition the query returns a set of cpu timestamps that indicate when the command streamer cycle count was captured.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM3hj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_xe_query_uc_fw_version (C struct)c.drm_xe_query_uc_fw_versionhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_uc_fw_versionh]j)}(h!struct drm_xe_query_uc_fw_versionh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM;ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhjhM;ubj)}(hdrm_xe_query_uc_fw_versionh]j)}(hjh]hdrm_xe_query_uc_fw_version}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhjhM;ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM;ubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhM;hjhhubj)}(hhh]h)}(h)query a micro-controller firmware versionh]h)query a micro-controller firmware version}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM`hjLhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM;ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jgj8jgj9j:j;uh1jhhhj@hj\hNubj=)}(hXT**Definition**:: struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; }; **Members** ``uc_type`` The micro-controller type to query firmware version ``pad`` MBZ ``branch_ver`` branch uc fw version ``major_ver`` major uc fw version ``minor_ver`` minor uc fw version ``patch_ver`` patch uc fw version ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjoubh:}(hjohhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMdhjkubj`)}(hX struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; };h]hX struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMfhjkubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMshjkubh)}(hhh](h)}(h@``uc_type`` The micro-controller type to query firmware version h](j)}(h ``uc_type``h]j)}(hjh]huc_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMfhjubj)}(hhh]h)}(h3The micro-controller type to query firmware versionh]h3The micro-controller type to query firmware version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMfhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMfhjubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hKhjubh)}(h$``branch_ver`` branch uc fw version h](j)}(h``branch_ver``h]j)}(hj.h]h branch_ver}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj(ubj)}(hhh]h)}(hbranch uc fw versionh]hbranch uc fw version}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChKhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1hhjChKhjubh)}(h"``major_ver`` major uc fw version h](j)}(h ``major_ver``h]j)}(hjgh]h major_ver}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjaubj)}(hhh]h)}(hmajor uc fw versionh]hmajor uc fw version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hKhj}ubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1hhj|hKhjubh)}(h"``minor_ver`` minor uc fw version h](j)}(h ``minor_ver``h]j)}(hjh]h minor_ver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hminor uc fw versionh]hminor uc fw version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h"``patch_ver`` patch uc fw version h](j)}(h ``patch_ver``h]j)}(hjh]h patch_ver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hpatch uc fw versionh]hpatch uc fw version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubj)}(hhh]h)}(hMBZh]hMBZ}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hKhj(ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj'hKhjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjKh]hreserved}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjEubj)}(hhh]h)}(hReservedh]hReserved}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1hhj`hKhjubeh}(h]h ]h"]h$]h&]uh1hhjkubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hmGiven a uc_type this will return the branch, major, minor and patch version of the micro-controller firmware.h]hmGiven a uc_type this will return the branch, major, minor and patch version of the micro-controller firmware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMahj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_xe_query_pxp_status (C struct)c.drm_xe_query_pxp_statushNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_pxp_statush]j)}(hstruct drm_xe_query_pxp_statush](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMgubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMgubj)}(hdrm_xe_query_pxp_statush]j)}(hjh]hdrm_xe_query_pxp_status}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMgubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMgubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMghjhhubj)}(hhh]h)}(hquery if PXP is readyh]hquery if PXP is ready}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMgubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j&j8j&j9j:j;uh1jhhhj@hj\hNubj=)}(h**Definition**:: struct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; }; **Members** ``status`` current PXP status ``supported_session_types`` bitmask of supported PXP session typesh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.ubh:}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj*ubj`)}(hXstruct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; };h]hXstruct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; };}hjKsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj*ubh)}(h **Members**h]h)}(hj\h]hMembers}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj*ubh)}(hhh](h)}(h``status`` current PXP status h](j)}(h ``status``h]j)}(hj{h]hstatus}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjuubj)}(hhh]h)}(hcurrent PXP statush]hcurrent PXP status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1hhjhMhjrubh)}(hB``supported_session_types`` bitmask of supported PXP session typesh](j)}(h``supported_session_types``h]j)}(hjh]hsupported_session_types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h&bitmask of supported PXP session typesh]h&bitmask of supported PXP session types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjrubeh}(h]h ]h"]h$]h&]uh1hhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hIf PXP is enabled and no fatal error has occurred, the status will be set to one of the following values: 0: PXP init still in progress 1: PXP init completeh]hIf PXP is enabled and no fatal error has occurred, the status will be set to one of the following values: 0: PXP init still in progress 1: PXP init complete}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hXXIf PXP is not enabled or something has gone wrong, the query will be failed with one of the following error codes: -ENODEV: PXP not supported or disabled; -EIO: fatal error occurred during init, so PXP will never be enabled; -EINVAL: incorrect value provided as part of the query; -EFAULT: error copying the memory between kernel and userspace.h]hXXIf PXP is not enabled or something has gone wrong, the query will be failed with one of the following error codes: -ENODEV: PXP not supported or disabled; -EIO: fatal error occurred during init, so PXP will never be enabled; -EINVAL: incorrect value provided as part of the query; -EFAULT: error copying the memory between kernel and userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hX.The status can only be 0 in the first few seconds after driver load. If everything works as expected, the status will transition to init complete in less than 1 second, while in case of errors the driver might take longer to start returning an error code, but it should still take less than 10 seconds.h]hX.The status can only be 0 in the first few seconds after driver load. If everything works as expected, the status will transition to init complete in less than 1 second, while in case of errors the driver might take longer to start returning an error code, but it should still take less than 10 seconds.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hThe supported session type bitmask is based on the values in enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore is not reported in the bitmask.h]hThe supported session type bitmask is based on the values in enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore is not reported in the bitmask.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_device_query (C struct)c.drm_xe_device_queryhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_device_queryh]j)}(hstruct drm_xe_device_queryh](j)}(hjh]hstruct}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhjohMubj)}(hdrm_xe_device_queryh]j)}(hj\h]hdrm_xe_device_query}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj^hhhjohMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjZhhhjohMubah}(h]jUah ](j j eh"]h$]h&]jj)jhuh1jhjohMhjWhhubj)}(hhh]h)}(hYInput of :c:type:`DRM_IOCTL_XE_DEVICE_QUERY` - main structure to query device informationh](h Input of }(hjhhhNhNubh)}(h#:c:type:`DRM_IOCTL_XE_DEVICE_QUERY`h]j)}(hjh]hDRM_IOCTL_XE_DEVICE_QUERY}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j ASTIdentifier)} identifierj\sbc.drm_xe_device_queryasbj DRM_IOCTL_XE_DEVICE_QUERYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubh- - main structure to query device information}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjWhhhjohMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``query`` The type of data to query ``size`` Size of the queried data ``data`` Queried data is placed here ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hXstruct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; };h]hXstruct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hj h]hMembers}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj?h]h extensions}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj9ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThMhjUubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1hhjThMhj6ubh)}(h$``query`` The type of data to query h](j)}(h ``query``h]j)}(hjxh]hquery}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjrubj)}(hhh]h)}(hThe type of data to queryh]hThe type of data to query}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1hhjhKhj6ubh)}(h"``size`` Size of the queried data h](j)}(h``size``h]j)}(hjh]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hSize of the queried datah]hSize of the queried data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj6ubh)}(h%``data`` Queried data is placed here h](j)}(h``data``h]j)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hQueried data is placed hereh]hQueried data is placed here}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj6ubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hj#h]hreserved}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj8hKhj6ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjfh]h Description}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hThe user selects the type of data to query among DRM_XE_DEVICE_QUERY_* and sets the value in the query member. This determines the type of the structure provided by the driver in data, among struct drm_xe_query_*.h]hThe user selects the type of data to query among DRM_XE_DEVICE_QUERY_* and sets the value in the query member. This determines the type of the structure provided by the driver in data, among struct drm_xe_query_*.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hhh]h)}(hXThe **query** can be: - ``DRM_XE_DEVICE_QUERY_ENGINES`` - ``DRM_XE_DEVICE_QUERY_MEM_REGIONS`` - ``DRM_XE_DEVICE_QUERY_CONFIG`` - ``DRM_XE_DEVICE_QUERY_GT_LIST`` - ``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes. - ``DRM_XE_DEVICE_QUERY_GT_TOPOLOGY`` - ``DRM_XE_DEVICE_QUERY_ENGINE_CYCLES`` - ``DRM_XE_DEVICE_QUERY_PXP_STATUS`` h](j)}(hThe **query** can be:h](hThe }(hjhhhNhNubh)}(h **query**h]hquery}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]jp )}(hhh](ju )}(h``DRM_XE_DEVICE_QUERY_ENGINES``h]h)}(hjh]j)}(hjh]hDRM_XE_DEVICE_QUERY_ENGINES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h#``DRM_XE_DEVICE_QUERY_MEM_REGIONS``h]h)}(hjh]j)}(hjh]hDRM_XE_DEVICE_QUERY_MEM_REGIONS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_DEVICE_QUERY_CONFIG``h]h)}(hjh]j)}(hjh]hDRM_XE_DEVICE_QUERY_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_DEVICE_QUERY_GT_LIST``h]h)}(hjh]j)}(hjh]hDRM_XE_DEVICE_QUERY_GT_LIST}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.h]h)}(h``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.h](j)}(h ``DRM_XE_DEVICE_QUERY_HWCONFIG``h]hDRM_XE_DEVICE_QUERY_HWCONFIG}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj=ubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h#``DRM_XE_DEVICE_QUERY_GT_TOPOLOGY``h]h)}(hjfh]j)}(hjfh]hDRM_XE_DEVICE_QUERY_GT_TOPOLOGY}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjdubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h%``DRM_XE_DEVICE_QUERY_ENGINE_CYCLES``h]h)}(hjh]j)}(hjh]h!DRM_XE_DEVICE_QUERY_ENGINE_CYCLES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h#``DRM_XE_DEVICE_QUERY_PXP_STATUS`` h]h)}(h"``DRM_XE_DEVICE_QUERY_PXP_STATUS``h]j)}(hjh]hDRM_XE_DEVICE_QUERY_PXP_STATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubh)}(hX-If size is set to 0, the driver fills it with the required size for the requested type of data to query. If size is equal to the required size, the queried information is copied into data. If size is set to a value different from 0 and different from the required size, the IOCTL call returns -EINVAL.h]hX-If size is set to 0, the driver fills it with the required size for the requested type of data to query. If size is equal to the required size, the queried information is copied into data. If size is set to a value different from 0 and different from the required size, the IOCTL call returns -EINVAL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hFor example the following code snippet allows retrieving and printing information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:h]hFor example the following code snippet allows retrieving and printing information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj`)}(hXstruct drm_xe_query_engines *engines; struct drm_xe_device_query query = { .extensions = 0, .query = DRM_XE_DEVICE_QUERY_ENGINES, .size = 0, .data = 0, }; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); engines = malloc(query.size); query.data = (uintptr_t)engines; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); for (int i = 0; i < engines->num_engines; i++) { printf("Engine %d: %s\n", i, engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": "UNKNOWN"); } free(engines);h]hXstruct drm_xe_query_engines *engines; struct drm_xe_device_query query = { .extensions = 0, .query = DRM_XE_DEVICE_QUERY_ENGINES, .size = 0, .data = 0, }; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); engines = malloc(query.size); query.data = (uintptr_t)engines; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); for (int i = 0; i < engines->num_engines; i++) { printf("Engine %d: %s\n", i, engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": "UNKNOWN"); } free(engines);}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_gem_create (C struct)c.drm_xe_gem_createhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_gem_createh]j)}(hstruct drm_xe_gem_createh](j)}(hjh]hstruct}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"hhhj3hMubj)}(hdrm_xe_gem_createh]j)}(hj h]hdrm_xe_gem_create}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ](jjeh"]h$]h&]jjuh1jhj"hhhj3hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj3hMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj3hMhjhhubj)}(hhh]h)}(hIInput of :c:type:`DRM_IOCTL_XE_GEM_CREATE` - A structure for gem creationh](h Input of }(hjhhhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]j)}(hjrh]hDRM_IOCTL_XE_GEM_CREATE}(hjthhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jj sbc.drm_xe_gem_createasbj DRM_IOCTL_XE_GEM_CREATEuh1hhjhKhjhubh - A structure for gem creation}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjehhubah}(h]h ]h"]h$]h&]uh1jhjhhhj3hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``size`` Size of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`). ``placement`` A mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``flags`` Flags, currently a mask of memory instances of where BO can be placed ``vm_id`` Attached VM, if any If a VM is specified, this BO must: 1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. ``handle`` Returned handle for the object. Object handles are nonzero. ``cpu_caching`` The CPU caching mode to select for this object. If mmaping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients. ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hXzstruct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; };h]hXzstruct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM#hjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM#hjubh)}(h{``size`` Size of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`). h](j)}(h``size``h]j)}(hj8h]hsize}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM+hj2ubj)}(hhh]h)}(hqSize of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`).h](hXSize of the object to be created, must match region (system or vram) minimum alignment (}(hjQhhhNhNubh)}(h:c:type:`min_page_size`h]j)}(hj[h]h min_page_size}(hj]hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j min_page_sizeuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM*hjQubh).}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjxhM*hjNubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhjMhM+hjubh)}(hX``placement`` A mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h ``placement``h]j)}(hjh]h placement}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM4hjubj)}(hhh]h)}(hXA mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h]hXA mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM4hjubh)}(hP``flags`` Flags, currently a mask of memory instances of where BO can be placed h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=hjubj)}(hhh]h)}(hEFlags, currently a mask of memory instances of where BO can be placedh]hEFlags, currently a mask of memory instances of where BO can be placed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM<hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM=hjubh)}(h``vm_id`` Attached VM, if any If a VM is specified, this BO must: 1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. h](j)}(h ``vm_id``h]j)}(hj h]hvm_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMGhjubj)}(hhh](h)}(hAttached VM, if anyh]hAttached VM, if any}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMBhjubh)}(h#If a VM is specified, this BO must:h]h#If a VM is specified, this BO must:}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMDhjubj)}(hG1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. h]j3)}(hhh](ju )}(hOnly ever be bound to that VM.h]h)}(hjIh]hOnly ever be bound to that VM.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMFhjGubah}(h]h ]h"]h$]h&]uh1jt hjDubju )}(h"Cannot be exported as a PRIME fd. h]h)}(h!Cannot be exported as a PRIME fd.h]h!Cannot be exported as a PRIME fd.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMGhj_ubah}(h]h ]h"]h$]h&]uh1jt hjDubeh}(h]h ]h"]h$]h&]jF4jG4jH4hjI4jJ4uh1j3hj@ubah}(h]h ]h"]h$]h&]uh1jhjXhMFhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMGhjubh)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMNhjubj)}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMLhjubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMNhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMNhjubh)}(hX``cpu_caching`` The CPU caching mode to select for this object. If mmaping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients. h](j)}(h``cpu_caching``h]j)}(hjh]h cpu_caching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM\hjubj)}(hhh]h)}(hXThe CPU caching mode to select for this object. If mmaping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients.h]hXThe CPU caching mode to select for this object. If mmaping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMUhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM\hjubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hKhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj,hKhjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjPh]hreserved}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjJubj)}(hhh]h)}(hReservedh]hReserved}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1hhjehKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hhh](h)}(hXThe **flags** can be: - ``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING`` - ``DRM_XE_GEM_CREATE_FLAG_SCANOUT`` - ``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems. h](j)}(hThe **flags** can be:h](hThe }(hjhhhNhNubh)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubj)}(hhh]jp )}(hhh](ju )}(h(``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING``h]h)}(hjh]j)}(hjh]h$DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h"``DRM_XE_GEM_CREATE_FLAG_SCANOUT``h]h)}(hjh]j)}(hjh]hDRM_XE_GEM_CREATE_FLAG_SCANOUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hXO``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems. h]h)}(hXN``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems.h](j)}(h-``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM``h]h)DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX# - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can’t be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM hjubh)}(hX**cpu_caching** supports the following values: - ``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM. - ``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this. h](j)}(h.**cpu_caching** supports the following values:h](h)}(h**cpu_caching**h]h cpu_caching}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVubh supports the following values:}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjRubj)}(hhh]jp )}(hhh](ju )}(h``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM.h]h)}(h``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM.h](j)}(h``DRM_XE_GEM_CPU_CACHING_WB``h]hDRM_XE_GEM_CPU_CACHING_WB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubh - Allocate the pages with write-back caching. On iGPU this can’t be used for scanout surfaces. Currently not allowed for objects placed in VRAM.}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjyubah}(h]h ]h"]h$]h&]uh1jt hjvubju )}(h``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this. h]h)}(h``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this.h](j)}(h``DRM_XE_GEM_CPU_CACHING_WC``h]hDRM_XE_GEM_CPU_CACHING_WC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjvubeh}(h]h ]h"]h$]h&]j j uh1jo hjhM hjsubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1hhjrhMhjubeh}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubh)}(hThis ioctl supports setting the following properties via the ``DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY`` extension, which uses the generic **drm_xe_ext_set_property** struct:h](h=This ioctl supports setting the following properties via the }(hjhhhNhNubj)}(h,``DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY``h]h(DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh# extension, which uses the generic }(hjhhhNhNubh)}(h**drm_xe_ext_set_property**h]hdrm_xe_ext_set_property}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh struct:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hX=- ``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected. h]jp )}(hhh]ju )}(hX-``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected. h]h)}(hX)``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected.h](j)}(h+``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE``h]h'DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhw - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. }(hjhhhNhNubj)}(h``DRM_XE_PXP_TYPE_NONE``h]hDRM_XE_PXP_TYPE_NONE}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhh is the default behavior, so there is no need to explicitly set that. Objects used with session of type }(hjhhhNhNubj)}(h``DRM_XE_PXP_TYPE_HWDRM``h]hDRM_XE_PXP_TYPE_HWDRM}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubah}(h]h ]h"]h$]h&]j j uh1jo hj]hMhjubah}(h]h ]h"]h$]h&]uh1jhj]hMhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_xe_gem_mmap_offset (C struct)c.drm_xe_gem_mmap_offsethNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_gem_mmap_offseth]j)}(hstruct drm_xe_gem_mmap_offseth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM#ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM#ubj)}(hdrm_xe_gem_mmap_offseth]j)}(hjh]hdrm_xe_gem_mmap_offset}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM#ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM#ubah}(h]j|ah ](j j eh"]h$]h&]jj)jhuh1jhjhM#hj~hhubj)}(hhh]h)}(h/Input of :c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET`h](h Input of }(hjhhhNhNubh)}(h&:c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET`h]j)}(hjh]hDRM_IOCTL_XE_GEM_MMAP_OFFSET}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjsbc.drm_xe_gem_mmap_offsetasbj DRM_IOCTL_XE_GEM_MMAP_OFFSETuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMfhjhhubah}(h]h ]h"]h$]h&]uh1jhj~hhhjhM#ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``handle`` Handle for the object being mapped. ``flags`` Flags ``offset`` The fake offset to use for subsequent mmap call ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMjhj ubj`)}(hstruct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; };h]hstruct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; };}hj.sbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhj ubh)}(h **Members**h]h)}(hj?h]hMembers}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMuhj ubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj^h]h extensions}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjXubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMhjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1hhjshMhjUubh)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjUubh)}(h``flags`` Flags h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hFlagsh]hFlags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjUubh)}(h;``offset`` The fake offset to use for subsequent mmap call h](j)}(h ``offset``h]j)}(hj h]hoffset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjUubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjBh]hreserved}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj<ubj)}(hhh]h)}(hReservedh]hReserved}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1hhjWhKhjUubeh}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hhh]h)}(hXUThe **flags** can be: - ``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction. h](j)}(hThe **flags** can be:h](hThe }(hjhhhNhNubh)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhjubj)}(hhh]jp )}(hhh]ju )}(hX5``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction. h]h)}(hX4``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction.h](j)}(h'``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER``h]h#DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX  - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhhjubah}(h]h ]h"]h$]h&]uh1jt hjubah}(h]h ]h"]h$]h&]j j uh1jo hjhMhhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMlhjubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubh)}(h&Roughly the usage would be as follows:h]h&Roughly the usage would be as follows:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMnhj@hhubj`)}(hXstruct drm_xe_gem_mmap_offset mmo = { .handle = 0, // must be set to 0 .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, }; err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); map[i] = 0xdeadbeaf; // issue barrierh]hXstruct drm_xe_gem_mmap_offset mmo = { .handle = 0, // must be set to 0 .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, }; err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); map[i] = 0xdeadbeaf; // issue barrier}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMphj@hhubh)}(h**Note**h]h)}(hj)h]hNote}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM{hj@hhubh)}(hX5The mmap size can be at most 4K, due to HW limitations. As a result this interface is only supported on CPU architectures that support 4K page size. The mmap_offset ioctl will detect this and gracefully return an error, where userspace is expected to have a different fallback method for triggering a barrier.h]hX5The mmap size can be at most 4K, due to HW limitations. As a result this interface is only supported on CPU architectures that support 4K page size. The mmap_offset ioctl will detect this and gracefully return an error, where userspace is expected to have a different fallback method for triggering a barrier.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMohj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_vm_create (C struct)c.drm_xe_vm_createhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_vm_createh]j)}(hstruct drm_xe_vm_createh](j)}(hjh]hstruct}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjchhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMxubj)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjchhhjthMxubj)}(hdrm_xe_vm_createh]j)}(hjah]hdrm_xe_vm_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjchhhjthMxubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj_hhhjthMxubah}(h]jZah ](j j eh"]h$]h&]jj)jhuh1jhjthMxhj\hhubj)}(hhh]h)}(h)Input of :c:type:`DRM_IOCTL_XE_VM_CREATE`h](h Input of }(hjhhhNhNubh)}(h :c:type:`DRM_IOCTL_XE_VM_CREATE`h]j)}(hjh]hDRM_IOCTL_XE_VM_CREATE}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjasbc.drm_xe_vm_createasbj DRM_IOCTL_XE_VM_CREATEuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj\hhhjthMxubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); __u32 flags; __u32 vm_id; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``flags`` Flags ``vm_id`` Returned VM ID ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hXstruct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); __u32 flags; __u32 vm_id; __u64 reserved[2]; };h]hXstruct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); __u32 flags; __u32 vm_id; __u64 reserved[2]; };}hj sbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj<h]h extensions}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj6ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhMhjRubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1hhjQhMhj3ubh)}(h``flags`` Flags h](j)}(h ``flags``h]j)}(hjuh]hflags}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjoubj)}(hhh]h)}(hFlagsh]hFlags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1hhjhKhj3ubh)}(h``vm_id`` Returned VM ID h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReturned VM IDh]hReturned VM ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj3ubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj3ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hj*h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hhh]h)}(hXPThe **flags** can be: - ``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception of on x2 and xe3 platform. - ``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device. - ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this. h](j)}(hThe **flags** can be:h](hThe }(hjGhhhNhNubh)}(h **flags**h]hflags}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh can be:}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjCubj)}(hhh]jp )}(hhh](ju )}(hX``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception of on x2 and xe3 platform.h]h)}(hX``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception of on x2 and xe3 platform.h](j)}(h&``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE``h]h"DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubh - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the }(hjrhhhNhNubj)}(h$``DRM_XE_VM_CREATE_FLAG_FAULT_MODE``h]h DRM_XE_VM_CREATE_FLAG_FAULT_MODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubh3 flag, with an exception of on x2 and xe3 platform.}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjnubah}(h]h ]h"]h$]h&]uh1jt hjkubju )}(hX``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.h]h)}(hX``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.h](j)}(h!``DRM_XE_VM_CREATE_FLAG_LR_MODE``h]hDRM_XE_VM_CREATE_FLAG_LR_MODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX - An LR, or Long Running VM accepts exec submissions to its exec_queues that don’t have an upper time limit on the job execution time. But exec submissions to these don’t allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjkubju )}(hX``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this. h]h)}(hX``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this.h](j)}(h$``DRM_XE_VM_CREATE_FLAG_FAULT_MODE``h]h DRM_XE_VM_CREATE_FLAG_FAULT_MODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjkubeh}(h]h ]h"]h$]h&]j j uh1jo hjhMhjhubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1hhjghMhj@ubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_vm_destroy (C struct)c.drm_xe_vm_destroyhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_vm_destroyh]j)}(hstruct drm_xe_vm_destroyh](j)}(hjh]hstruct}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"hhhj3hMubj)}(hdrm_xe_vm_destroyh]j)}(hj h]hdrm_xe_vm_destroy}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ](jjeh"]h$]h&]jjuh1jhj"hhhj3hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj3hMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj3hMhjhhubj)}(hhh]h)}(h*Input of :c:type:`DRM_IOCTL_XE_VM_DESTROY`h](h Input of }(hjhhhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_VM_DESTROY`h]j)}(hjrh]hDRM_IOCTL_XE_VM_DESTROY}(hjthhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jj sbc.drm_xe_vm_destroyasbj DRM_IOCTL_XE_VM_DESTROYuh1hhjhKhjhubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjehhubah}(h]h ]h"]h$]h&]uh1jhjhhhj3hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(h**Definition**:: struct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; }; **Members** ``vm_id`` VM ID ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hTstruct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; };h]hTstruct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h``vm_id`` VM ID h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hVM IDh]hVM ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj4h]hpad}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj.ubj)}(hhh]h)}(hMBZh]hMBZ}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhKhjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1hhjIhKhjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjmh]hreserved}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjgubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_vm_bind_op (C struct)c.drm_xe_vm_bind_ophNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_vm_bind_oph]j)}(hstruct drm_xe_vm_bind_oph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hdrm_xe_vm_bind_oph]j)}(hjh]hdrm_xe_vm_bind_op}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hrun bind operationsh]hrun bind operations}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j!j8j!j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); __u32 flags; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``obj`` GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP ``pat_index`` The platform defined **pat_index** to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE. For coherency the **pat_index** needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the **pat_index** and reject if there is a mismatch (see note below for pre-MTL platforms). Note: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It's only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms: ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY In practice UC/WC/WT should only ever used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible. Note: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**. For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped. ``pad`` MBZ ``{unnamed_union}`` anonymous ``obj_offset`` Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind ``userptr`` user pointer to bind on ``cpu_addr_mirror_offset`` Offset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported). ``range`` Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL ``addr`` Address to operate on, MBZ for UNMAP_ALL ``op`` Bind operation to perform ``flags`` Bind flags ``prefetch_mem_region_instance`` Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation. ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)ubh:}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj%ubj`)}(hXtstruct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); __u32 flags; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; };h]hXtstruct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); __u32 flags; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; };}hjFsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj%ubh)}(h **Members**h]h)}(hjWh]hMembers}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj%ubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjvh]h extensions}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjpubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1hhjhMhjmubh)}(hE``obj`` GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP h](j)}(h``obj``h]j)}(hjh]hobj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY In practice UC/WC/WT should only ever used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible. Note: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**. For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped. h](j)}(h ``pat_index``h]j)}(hjh]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM%hjubj)}(hhh](h)}(hXaThe platform defined **pat_index** to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE.h](hThe platform defined }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhX? to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hX For coherency the **pat_index** needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the **pat_index** and reject if there is a mismatch (see note below for pre-MTL platforms).h](hFor coherency the }(hj"hhhNhNubh)}(h **pat_index**h]h pat_index}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubh needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the }(hj"hhhNhNubh)}(h **pat_index**h]h pat_index}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubhJ and reject if there is a mismatch (see note below for pre-MTL platforms).}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hXNote: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It's only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms:h]hXNote: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It’s only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms:}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(h]ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY h]h)}(h\ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAYh]h\ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjdubah}(h]h ]h"]h$]h&]uh1jhjvhMhjubh)}(hXIn practice UC/WC/WT should only ever used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible.h](hXuIn practice UC/WC/WT should only ever used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the }(hj}hhhNhNubh)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}ubh), where incoherent GT access is possible.}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hoNote: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**.h](haNote: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hXFor DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped.h](hKFor DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhXS. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM%hjmubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjmubh)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hj+h]h{unnamed_union}}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj%ubj)}(hhh]h)}(h anonymoush]h anonymous}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hKhjAubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1hhj@hKhjmubh)}(hO``obj_offset`` Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind h](j)}(h``obj_offset``h]j)}(hjdh]h obj_offset}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM/hj^ubj)}(hhh]h)}(h?Offset into the object, MBZ for CLEAR_RANGE, ignored for unbindh]h?Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM.hjzubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1hhjyhM/hjmubh)}(h$``userptr`` user pointer to bind on h](j)}(h ``userptr``h]j)}(hjh]huserptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(huser pointer to bind onh]huser pointer to bind on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjmubh)}(h``cpu_addr_mirror_offset`` Offset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported). h](j)}(h``cpu_addr_mirror_offset``h]j)}(hjh]hcpu_addr_mirror_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM:hjubj)}(hhh]h)}(hOffset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported).h](hOffset from GPU }(hjhhhNhNubh)}(h**addr**h]haddr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM:hjmubh)}(hM``range`` Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL h](j)}(h ``range``h]j)}(hj#h]hrange}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM@hjubj)}(hhh]h)}(hBNumber of bytes from the object to bind to addr, MBZ for UNMAP_ALLh]hBNumber of bytes from the object to bind to addr, MBZ for UNMAP_ALL}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hM@hj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj8hM@hjmubh)}(h2``addr`` Address to operate on, MBZ for UNMAP_ALL h](j)}(h``addr``h]j)}(hj\h]haddr}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjVubj)}(hhh]h)}(h(Address to operate on, MBZ for UNMAP_ALLh]h(Address to operate on, MBZ for UNMAP_ALL}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhKhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1hhjqhKhjmubh)}(h!``op`` Bind operation to perform h](j)}(h``op``h]j)}(hjh]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hBind operation to performh]hBind operation to perform}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjmubh)}(h``flags`` Bind flags h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h Bind flagsh]h Bind flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjmubh)}(h``prefetch_mem_region_instance`` Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation. h](j)}(h ``prefetch_mem_region_instance``h]j)}(hjh]hprefetch_mem_region_instance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM[hjubj)}(hhh]h)}(hMemory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation.h](h\Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with }(hj hhhNhNubj)}(h``DRM_XE_VM_BIND_OP_PREFETCH``h]hDRM_XE_VM_BIND_OP_PREFETCH}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh operation.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM[hjmubh)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjSh]hpad2}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjMubj)}(hhh]h)}(hMBZh]hMBZ}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhKhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1hhjhhKhjmubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjmubeh}(h]h ]h"]h$]h&]uh1hhj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hhh](h)}(hThe **op** can be: - ``DRM_XE_VM_BIND_OP_MAP`` - ``DRM_XE_VM_BIND_OP_UNMAP`` - ``DRM_XE_VM_BIND_OP_MAP_USERPTR`` - ``DRM_XE_VM_BIND_OP_UNMAP_ALL`` - ``DRM_XE_VM_BIND_OP_PREFETCH`` h](j)}(hThe **op** can be:h](hThe }(hjhhhNhNubh)}(h**op**h]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]jp )}(hhh](ju )}(h``DRM_XE_VM_BIND_OP_MAP``h]h)}(hjh]j)}(hjh]hDRM_XE_VM_BIND_OP_MAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_VM_BIND_OP_UNMAP``h]h)}(hj6h]j)}(hj6h]hDRM_XE_VM_BIND_OP_UNMAP}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj4ubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h!``DRM_XE_VM_BIND_OP_MAP_USERPTR``h]h)}(hjWh]j)}(hjWh]hDRM_XE_VM_BIND_OP_MAP_USERPTR}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjUubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_VM_BIND_OP_UNMAP_ALL``h]h)}(hjxh]j)}(hjxh]hDRM_XE_VM_BIND_OP_UNMAP_ALL}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjvubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_VM_BIND_OP_PREFETCH`` h]h)}(h``DRM_XE_VM_BIND_OP_PREFETCH``h]j)}(hjh]hDRM_XE_VM_BIND_OP_PREFETCH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhj hMhjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hj-hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hMhjubh)}(hX>and the **flags** can be: - ``DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protection - ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to. - ``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings. - ``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP. - ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. h](j)}(hand the **flags** can be:h](hand the }(hjhhhNhNubh)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]jp )}(hhh](ju )}(h```DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protectionh]h)}(h```DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protectionh](j)}(h ``DRM_XE_VM_BIND_FLAG_READONLY``h]hDRM_XE_VM_BIND_FLAG_READONLY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh@ - Setup the page tables as read-only to ensure write protection}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.h]h)}(h``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.h](j)}(h!``DRM_XE_VM_BIND_FLAG_IMMEDIATE``h]hDRM_XE_VM_BIND_FLAG_IMMEDIATE}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hX\``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.h]h)}(hX\``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.h](j)}(h``DRM_XE_VM_BIND_FLAG_NULL``h]hDRM_XE_VM_BIND_FLAG_NULL}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubhX@ - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjCubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.h]h)}(h``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.h](j)}(h!``DRM_XE_VM_BIND_FLAG_CHECK_PXP``h]hDRM_XE_VM_BIND_FLAG_CHECK_PXP}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubh - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.}(hjnhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hX``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. h]h)}(hX``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ.h](j)}(h'``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR``h]h#DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhXl - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_vm_bind (C struct)c.drm_xe_vm_bindhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_vm_bindh]j)}(hstruct drm_xe_vm_bindh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_vm_bindh]j)}(hjh]hdrm_xe_vm_bind}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h'Input of :c:type:`DRM_IOCTL_XE_VM_BIND`h](h Input of }(hj+hhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]j)}(hj5h]hDRM_IOCTL_XE_VM_BIND}(hj7hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjsbc.drm_xe_vm_bindasbj DRM_IOCTL_XE_VM_BINDuh1hhjhKhj+ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMfhj(hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jij8jij9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``vm_id`` The ID of the VM to bind to ``exec_queue_id`` exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used. ``pad`` MBZ ``num_binds`` number of binds in this IOCTL ``{unnamed_union}`` anonymous ``bind`` used if num_binds == 1 ``vector_of_binds`` userptr to array of struct drm_xe_vm_bind_op if num_binds > 1 ``pad2`` MBZ ``num_syncs`` amount of syncs to wait on ``syncs`` pointer to struct drm_xe_sync array ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqubh:}(hjqhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMjhjmubj`)}(hX$struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; };h]hX$struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhjmubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM|hjmubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h&``vm_id`` The ID of the VM to bind to h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hThe ID of the VM to bind toh]hThe ID of the VM to bind to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hKhjubh)}(h``exec_queue_id`` exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used. h](j)}(h``exec_queue_id``h]j)}(hj0h]h exec_queue_id}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj*ubj)}(hhh]h)}(hexec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used.h]hexec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1hhjEhMhjubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjjh]hpad}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjdubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h,``num_binds`` number of binds in this IOCTL h](j)}(h ``num_binds``h]j)}(hjh]h num_binds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hnumber of binds in this IOCTLh]hnumber of binds in this IOCTL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h ``bind`` used if num_binds == 1 h](j)}(h``bind``h]j)}(hjh]hbind}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hused if num_binds == 1h]hused if num_binds == 1}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hKhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj*hKhjubh)}(hR``vector_of_binds`` userptr to array of struct drm_xe_vm_bind_op if num_binds > 1 h](j)}(h``vector_of_binds``h]j)}(hjNh]hvector_of_binds}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjHubj)}(hhh]h)}(h=userptr to array of struct drm_xe_vm_bind_op if num_binds > 1h]h=userptr to array of struct drm_xe_vm_bind_op if num_binds > 1}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1hhjchMhjubh)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h)``num_syncs`` amount of syncs to wait on h](j)}(h ``num_syncs``h]j)}(hjh]h num_syncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hamount of syncs to wait onh]hamount of syncs to wait on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h.``syncs`` pointer to struct drm_xe_sync array h](j)}(h ``syncs``h]j)}(hjh]hsyncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h#pointer to struct drm_xe_sync arrayh]h#pointer to struct drm_xe_sync array}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hj3h]hreserved}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj-ubj)}(hhh]h)}(hReservedh]hReserved}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1hhjHhKhjubeh}(h]h ]h"]h$]h&]uh1hhjmubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjvh]h Description}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjtubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hBelow is an example of a minimal use of **drm_xe_vm_bind** to asynchronously bind the buffer `data` at address `BIND_ADDRESS` to illustrate `userptr`. It can be synchronized by using the example provided for **drm_xe_sync**.h](h(Below is an example of a minimal use of }(hjhhhNhNubh)}(h**drm_xe_vm_bind**h]hdrm_xe_vm_bind}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh# to asynchronously bind the buffer }(hjhhhNhNubjU )}(h`data`h]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjubh at address }(hjhhhNhNubjU )}(h`BIND_ADDRESS`h]h BIND_ADDRESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjubh to illustrate }(hjhhhNhNubjU )}(h `userptr`h]huserptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jT hjubh;. It can be synchronized by using the example provided for }(hjhhhNhNubh)}(h**drm_xe_sync**h]h drm_xe_sync}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMghj@hhubj`)}(hXdata = aligned_alloc(ALIGNMENT, BO_SIZE); struct drm_xe_vm_bind bind = { .vm_id = vm, .num_binds = 1, .bind.obj = 0, .bind.obj_offset = to_user_pointer(data), .bind.range = BO_SIZE, .bind.addr = BIND_ADDRESS, .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, .bind.flags = 0, .num_syncs = 1, .syncs = &sync, .exec_queue_id = 0, }; ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);h]hXdata = aligned_alloc(ALIGNMENT, BO_SIZE); struct drm_xe_vm_bind bind = { .vm_id = vm, .num_binds = 1, .bind.obj = 0, .bind.obj_offset = to_user_pointer(data), .bind.range = BO_SIZE, .bind.addr = BIND_ADDRESS, .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, .bind.flags = 0, .num_syncs = 1, .syncs = &sync, .exec_queue_id = 0, }; ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_xe_exec_queue_create (C struct)c.drm_xe_exec_queue_createhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_exec_queue_createh]j)}(hstruct drm_xe_exec_queue_createh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj+hMubj)}(hdrm_xe_exec_queue_createh]j)}(hjh]hdrm_xe_exec_queue_create}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj+hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj+hMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj+hMhjhhubj)}(hhh]h)}(h1Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h](h Input of }(hj`hhhNhNubh)}(h(:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h]j)}(hjjh]hDRM_IOCTL_XE_EXEC_QUEUE_CREATE}(hjlhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjsbc.drm_xe_exec_queue_createasbj DRM_IOCTL_XE_EXEC_QUEUE_CREATEuh1hhjhKhj`ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj]hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj+hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hXL**Definition**:: struct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``width`` submission width (number BB per exec) for this exec queue ``num_placements`` number of valid placements for this exec queue ``vm_id`` VM to use for this exec queue ``flags`` flags to use for this exec queue ``exec_queue_id`` Returned exec queue ID ``instances`` user pointer to a 2-d array of struct drm_xe_engine_class_instance length = width (i) * num_placements (j) index = j + i * width ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hX struct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; };h]hX struct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(hD``width`` submission width (number BB per exec) for this exec queue h](j)}(h ``width``h]j)}(hj,h]hwidth}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj&ubj)}(hhh]h)}(h9submission width (number BB per exec) for this exec queueh]h9submission width (number BB per exec) for this exec queue}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhKhjBubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1hhjAhKhjubh)}(hB``num_placements`` number of valid placements for this exec queue h](j)}(h``num_placements``h]j)}(hjeh]hnum_placements}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj_ubj)}(hhh]h)}(h.number of valid placements for this exec queueh]h.number of valid placements for this exec queue}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhKhj{ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1hhjzhKhjubh)}(h(``vm_id`` VM to use for this exec queue h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hVM to use for this exec queueh]hVM to use for this exec queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h+``flags`` flags to use for this exec queue h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h flags to use for this exec queueh]h flags to use for this exec queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h)``exec_queue_id`` Returned exec queue ID h](j)}(h``exec_queue_id``h]j)}(hjh]h exec_queue_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubj)}(hhh]h)}(hReturned exec queue IDh]hReturned exec queue ID}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hKhj&ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj%hKhjubh)}(h``instances`` user pointer to a 2-d array of struct drm_xe_engine_class_instance length = width (i) * num_placements (j) index = j + i * width h](j)}(h ``instances``h]j)}(hjIh]h instances}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjCubj)}(hhh](h)}(hBuser pointer to a 2-d array of struct drm_xe_engine_class_instanceh]hBuser pointer to a 2-d array of struct drm_xe_engine_class_instance}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj_ubh)}(h=length = width (i) * num_placements (j) index = j + i * widthh]h=length = width (i) * num_placements (j) index = j + i * width}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj_ubeh}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1hhj^hMhjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hThis ioctl supports setting the following properties via the ``DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY`` extension, which uses the generic **drm_xe_ext_set_property** struct:h](h=This ioctl supports setting the following properties via the }(hjhhhNhNubj)}(h,``DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY``h]h(DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh# extension, which uses the generic }(hjhhhNhNubh)}(h**drm_xe_ext_set_property**h]hdrm_xe_ext_set_property}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh struct:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hX- ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs. h]jp )}(hhh](ju )}(h{``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal.h]h)}(h{``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal.h](j)}(h+``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY``h]h'DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubhP - set the queue priority. CAP_SYS_NICE is required to set a value above normal.}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj%ubah}(h]h ]h"]h$]h&]uh1jt hj"ubju )}(h```DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds.h]h)}(h```DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds.h](j)}(h,``DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE``h]h(DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubh4 - set the queue timeslice duration in microseconds.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjLubah}(h]h ]h"]h$]h&]uh1jt hj"ubju )}(hX``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs. h]h)}(hX``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs.h](j)}(h+``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE``h]h'DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubhv - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. }(hjwhhhNhNubj)}(h``DRM_XE_PXP_TYPE_NONE``h]hDRM_XE_PXP_TYPE_NONE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubh[ is the default behavior, so there is no need to explicitly set that. When a queue of type }(hjwhhhNhNubj)}(h``DRM_XE_PXP_TYPE_HWDRM``h]hDRM_XE_PXP_TYPE_HWDRM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubh, is created, the PXP default HWDRM session (}(hjwhhhNhNubj)}(h ``XE_PXP_HWDRM_DEFAULT_SESSION``h]hXE_PXP_HWDRM_DEFAULT_SESSION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubhu) will be started, if isn’t already running. The user is expected to query the PXP status via the query ioctl (see }(hjwhhhNhNubj)}(h"``DRM_XE_DEVICE_QUERY_PXP_STATUS``h]hDRM_XE_DEVICE_QUERY_PXP_STATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubhX) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs.}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjsubah}(h]h ]h"]h$]h&]uh1jt hj"ubeh}(h]h ]h"]h$]h&]j j uh1jo hjEhMhjubah}(h]h ]h"]h$]h&]uh1jhjEhMhj@hhubh)}(hThe example below shows how to use **drm_xe_exec_queue_create** to create a simple exec_queue (no parallel submission) of class :c:type:`DRM_XE_ENGINE_CLASS_RENDER`.h](h#The example below shows how to use }(hjhhhNhNubh)}(h**drm_xe_exec_queue_create**h]hdrm_xe_exec_queue_create}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhA to create a simple exec_queue (no parallel submission) of class }(hjhhhNhNubh)}(h$:c:type:`DRM_XE_ENGINE_CLASS_RENDER`h]j)}(hj h]hDRM_XE_ENGINE_CLASS_RENDER}(hj hhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j j DRM_XE_ENGINE_CLASS_RENDERuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj'hMhj@hhubj`)}(hXstruct drm_xe_engine_class_instance instance = { .engine_class = DRM_XE_ENGINE_CLASS_RENDER, }; struct drm_xe_exec_queue_create exec_queue_create = { .extensions = 0, .vm_id = vm, .num_bb_per_exec = 1, .num_eng_per_bb = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); Allow users to provide a hint to kernel for cases demanding low latency profile. Please note it will have impact on power consumption. User can indicate low latency hint with flag while creating exec queue as mentioned below, struct drm_xe_exec_queue_create exec_queue_create = { .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, .extensions = 0, .vm_id = vm, .num_bb_per_exec = 1, .num_eng_per_bb = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);h]hXstruct drm_xe_engine_class_instance instance = { .engine_class = DRM_XE_ENGINE_CLASS_RENDER, }; struct drm_xe_exec_queue_create exec_queue_create = { .extensions = 0, .vm_id = vm, .num_bb_per_exec = 1, .num_eng_per_bb = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); Allow users to provide a hint to kernel for cases demanding low latency profile. Please note it will have impact on power consumption. User can indicate low latency hint with flag while creating exec queue as mentioned below, struct drm_xe_exec_queue_create exec_queue_create = { .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, .extensions = 0, .vm_id = vm, .num_bb_per_exec = 1, .num_eng_per_bb = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);}hj2sbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_xe_exec_queue_destroy (C struct)c.drm_xe_exec_queue_destroyhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_exec_queue_destroyh]j)}(h struct drm_xe_exec_queue_destroyh](j)}(hjh]hstruct}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWhhhjhhMubj)}(hdrm_xe_exec_queue_destroyh]j)}(hjUh]hdrm_xe_exec_queue_destroy}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubah}(h]h ](jjeh"]h$]h&]jjuh1jhjWhhhjhhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjShhhjhhMubah}(h]jNah ](j j eh"]h$]h&]jj)jhuh1jhjhhMhjPhhubj)}(hhh]h)}(h2Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY`h](h Input of }(hjhhhNhNubh)}(h):c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY`h]j)}(hjh]hDRM_IOCTL_XE_EXEC_QUEUE_DESTROY}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjUsbc.drm_xe_exec_queue_destroyasbj DRM_IOCTL_XE_EXEC_QUEUE_DESTROYuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjPhhhjhhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(h**Definition**:: struct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; }; **Members** ``exec_queue_id`` Exec queue ID ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hdstruct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; };h]hdstruct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h ``exec_queue_id`` Exec queue ID h](j)}(h``exec_queue_id``h]j)}(hj0h]h exec_queue_id}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj*ubj)}(hhh]h)}(h Exec queue IDh]h Exec queue ID}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1hhjEhMhj'ubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjih]hpad}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjcubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1hhj~hKhj'ubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj'ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)drm_xe_exec_queue_get_property (C struct) c.drm_xe_exec_queue_get_propertyhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_exec_queue_get_propertyh]j)}(h%struct drm_xe_exec_queue_get_propertyh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj hKubj)}(hdrm_xe_exec_queue_get_propertyh]j)}(hjh]hdrm_xe_exec_queue_get_property}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj hKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj hKhjhhubj)}(hhh]h)}(h7Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY`h](h Input of }(hj>hhhNhNubh)}(h.:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY`h]j)}(hjHh]h$DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY}(hjJhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjsb c.drm_xe_exec_queue_get_propertyasbj $DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTYuh1hhjhKhj>ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj;hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j|j8j|j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``exec_queue_id`` Exec queue ID ``property`` property to get ``value`` property value ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubj`)}(hstruct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; };h]hstruct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM"hjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM+hjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM"hjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM"hjubh)}(h ``exec_queue_id`` Exec queue ID h](j)}(h``exec_queue_id``h]j)}(hj h]h exec_queue_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h Exec queue IDh]h Exec queue ID}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``property`` property to get h](j)}(h ``property``h]j)}(hjCh]hproperty}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj=ubj)}(hhh]h)}(hproperty to geth]hproperty to get}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhKhjYubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1hhjXhKhjubh)}(h``value`` property value h](j)}(h ``value``h]j)}(hj|h]hvalue}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjvubj)}(hhh]h)}(hproperty valueh]hproperty value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hhh]h)}(hEThe **property** can be: - ``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN`` h](j)}(hThe **property** can be:h](hThe }(hjhhhNhNubh)}(h **property**h]hproperty}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM!hjubj)}(hhh]jp )}(hhh]ju )}(h*``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN`` h]h)}(h&``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN``h]j)}(hjBh]h"DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj<ubah}(h]h ]h"]h$]h&]uh1jt hj9ubah}(h]h ]h"]h$]h&]j j uh1jo hjWhMhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj5hM!hjubah}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_sync (C struct) c.drm_xe_synchNtauh1jhj@hhhj\hNubj)}(hhh](j)}(h drm_xe_synch]j)}(hstruct drm_xe_synch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM#ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM#ubj)}(h drm_xe_synch]j)}(hjh]h drm_xe_sync}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM#ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM#ubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhM#hjhhubj)}(hhh]h)}(h sync objecth]h sync object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM4hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM#ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hXr**Definition**:: struct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``type`` Type of the this sync object ``flags`` Sync Flags ``{unnamed_union}`` anonymous ``handle`` Handle for the object ``addr`` Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync passed in via VM bind IOCTL this is a user pointer. In either case, it is the users responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned. ``timeline_value`` Input for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ``. ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM8hjubj`)}(hXstruct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; };h]hXstruct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM:hjubh)}(h **Members**h]h)}(hjh]hMembers}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMJhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj>h]h extensions}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMWhj8ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMWhjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1hhjShMWhj5ubh)}(h&``type`` Type of the this sync object h](j)}(h``type``h]j)}(hjwh]htype}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjqubj)}(hhh]h)}(hType of the this sync objecth]hType of the this sync object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1hhjhKhj5ubh)}(h``flags`` Sync Flags h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h Sync Flagsh]h Sync Flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj5ubh)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj5ubh)}(h!``handle`` Handle for the object h](j)}(h ``handle``h]j)}(hj"h]hhandle}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hHandle for the objecth]hHandle for the object}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hKhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj7hKhj5ubh)}(hX5``addr`` Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync passed in via VM bind IOCTL this is a user pointer. In either case, it is the users responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned. h](j)}(h``addr``h]j)}(hj[h]haddr}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMohjUubj)}(hhh]h)}(hX+Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync passed in via VM bind IOCTL this is a user pointer. In either case, it is the users responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned.h]hX+Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync passed in via VM bind IOCTL this is a user pointer. In either case, it is the users responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMjhjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1hhjphMohj5ubh)}(h``timeline_value`` Input for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ``. h](j)}(h``timeline_value``h]j)}(hjh]htimeline_value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMvhjubj)}(hhh]h)}(hvInput for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ``.h](hPInput for the timeline sync object. Needs to be different than 0 when used with }(hjhhhNhNubj)}(h%``DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ``h]h!DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMuhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMvhj5ubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhj5ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hj$h]h Description}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hhh](h)}(h~The **type** can be: - ``DRM_XE_SYNC_TYPE_SYNCOBJ`` - ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ`` - ``DRM_XE_SYNC_TYPE_USER_FENCE`` h](j)}(hThe **type** can be:h](hThe }(hjAhhhNhNubh)}(h**type**h]htype}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAubh can be:}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM8hj=ubj)}(hhh]jp )}(hhh](ju )}(h``DRM_XE_SYNC_TYPE_SYNCOBJ``h]h)}(hjjh]j)}(hjjh]hDRM_XE_SYNC_TYPE_SYNCOBJ}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM6hjhubah}(h]h ]h"]h$]h&]uh1jt hjeubju )}(h%``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``h]h)}(hjh]j)}(hjh]h!DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM7hjubah}(h]h ]h"]h$]h&]uh1jt hjeubju )}(h ``DRM_XE_SYNC_TYPE_USER_FENCE`` h]h)}(h``DRM_XE_SYNC_TYPE_USER_FENCE``h]j)}(hjh]hDRM_XE_SYNC_TYPE_USER_FENCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhjahM8hjubah}(h]h ]h"]h$]h&]uh1jt hjeubeh}(h]h ]h"]h$]h&]j j uh1jo hjhM6hjbubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1hhjahM8hj:ubh)}(h8and the **flags** can be: - ``DRM_XE_SYNC_FLAG_SIGNAL`` h](j)}(hand the **flags** can be:h](hand the }(hjhhhNhNubh)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM;hjubj)}(hhh]jp )}(hhh]ju )}(h``DRM_XE_SYNC_FLAG_SIGNAL`` h]h)}(h``DRM_XE_SYNC_FLAG_SIGNAL``h]j)}(hjh]hDRM_XE_SYNC_FLAG_SIGNAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhjhM;hjubah}(h]h ]h"]h$]h&]uh1jt hjubah}(h]h ]h"]h$]h&]j j uh1jo hjhM;hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM;hj:ubeh}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubh)}(h1A minimal use of **drm_xe_sync** looks like this:h](hA minimal use of }(hjAhhhNhNubh)}(h**drm_xe_sync**h]h drm_xe_sync}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAubh looks like this:}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=hj@hhubj`)}(hXstruct drm_xe_sync sync = { .flags = DRM_XE_SYNC_FLAG_SIGNAL, .type = DRM_XE_SYNC_TYPE_SYNCOBJ, }; struct drm_syncobj_create syncobj_create = { 0 }; ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); sync.handle = syncobj_create.handle; ... use of &sync in drm_xe_exec or drm_xe_vm_bind ... struct drm_syncobj_wait wait = { .handles = &sync.handle, .timeout_nsec = INT64_MAX, .count_handles = 1, .flags = 0, .first_signaled = 0, .pad = 0, }; ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);h]hXstruct drm_xe_sync sync = { .flags = DRM_XE_SYNC_FLAG_SIGNAL, .type = DRM_XE_SYNC_TYPE_SYNCOBJ, }; struct drm_syncobj_create syncobj_create = { 0 }; ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); sync.handle = syncobj_create.handle; ... use of &sync in drm_xe_exec or drm_xe_vm_bind ... struct drm_syncobj_wait wait = { .handles = &sync.handle, .timeout_nsec = INT64_MAX, .count_handles = 1, .flags = 0, .first_signaled = 0, .pad = 0, }; ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);}hjbsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM?hj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_exec (C struct) c.drm_xe_exechNtauh1jhj@hhhj\hNubj)}(hhh](j)}(h drm_xe_exech]j)}(hstruct drm_xe_exech](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMXubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMXubj)}(h drm_xe_exech]j)}(hjh]h drm_xe_exec}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMXubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMXubah}(h]j~ah ](j j eh"]h$]h&]jj)jhuh1jhjhMXhjhhubj)}(hhh]h)}(h$Input of :c:type:`DRM_IOCTL_XE_EXEC`h](h Input of }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_EXEC`h]j)}(hjh]hDRM_IOCTL_XE_EXEC}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjsb c.drm_xe_execasbj DRM_IOCTL_XE_EXECuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMXubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``exec_queue_id`` Exec queue ID for the batch buffer ``num_syncs`` Amount of struct drm_xe_sync in array. ``syncs`` Pointer to struct drm_xe_sync array. ``address`` address of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses ``num_batch_buffer`` number of batch buffer in this exec, must match the width of the engine ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hstruct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; };h]hstruct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; };}hj0sbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjAh]hMembers}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj`h]h extensions}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjZubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1hhjuhMhjWubh)}(h5``exec_queue_id`` Exec queue ID for the batch buffer h](j)}(h``exec_queue_id``h]j)}(hjh]h exec_queue_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h"Exec queue ID for the batch bufferh]h"Exec queue ID for the batch buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjWubh)}(h5``num_syncs`` Amount of struct drm_xe_sync in array. h](j)}(h ``num_syncs``h]j)}(hjh]h num_syncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h&Amount of struct drm_xe_sync in array.h]h&Amount of struct drm_xe_sync in array.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjWubh)}(h/``syncs`` Pointer to struct drm_xe_sync array. h](j)}(h ``syncs``h]j)}(hj h]hsyncs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h$Pointer to struct drm_xe_sync array.h]h$Pointer to struct drm_xe_sync array.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hKhjWubh)}(hc``address`` address of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses h](j)}(h ``address``h]j)}(hjDh]haddress}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj>ubj)}(hhh]h)}(hVaddress of batch buffer if num_batch_buffer == 1 or an array of batch buffer addressesh]hVaddress of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1hhjYhMhjWubh)}(h]``num_batch_buffer`` number of batch buffer in this exec, must match the width of the engine h](j)}(h``num_batch_buffer``h]j)}(hj~h]hnum_batch_buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjxubj)}(hhh]h)}(hGnumber of batch buffer in this exec, must match the width of the engineh]hGnumber of batch buffer in this exec, must match the width of the engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1hhjhMhjWubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjWubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjWubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hj4h]h Description}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(hXThis is an example to use **drm_xe_exec** for execution of the object at BIND_ADDRESS (see example in **drm_xe_vm_bind**) by an exec_queue (see example in **drm_xe_exec_queue_create**). It can be synchronized by using the example provided for **drm_xe_sync**.h](hThis is an example to use }(hjJhhhNhNubh)}(h**drm_xe_exec**h]h drm_xe_exec}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubh= for execution of the object at BIND_ADDRESS (see example in }(hjJhhhNhNubh)}(h**drm_xe_vm_bind**h]hdrm_xe_vm_bind}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubh#) by an exec_queue (see example in }(hjJhhhNhNubh)}(h**drm_xe_exec_queue_create**h]hdrm_xe_exec_queue_create}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubh<). It can be synchronized by using the example provided for }(hjJhhhNhNubh)}(h**drm_xe_sync**h]h drm_xe_sync}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubh.}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj`)}(hstruct drm_xe_exec exec = { .exec_queue_id = exec_queue, .syncs = &sync, .num_syncs = 1, .address = BIND_ADDRESS, .num_batch_buffer = 1, }; ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);h]hstruct drm_xe_exec exec = { .exec_queue_id = exec_queue, .syncs = &sync, .num_syncs = 1, .address = BIND_ADDRESS, .num_batch_buffer = 1, }; ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);}hjsbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_xe_wait_user_fence (C struct)c.drm_xe_wait_user_fencehNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_wait_user_fenceh]j)}(hstruct drm_xe_wait_user_fenceh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_wait_user_fenceh]j)}(hjh]hdrm_xe_wait_user_fence}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h/Input of :c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE`h](h Input of }(hj hhhNhNubh)}(h&:c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE`h]j)}(hjh]hDRM_IOCTL_XE_WAIT_USER_FENCE}(hjhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjsbc.drm_xe_wait_user_fenceasbj DRM_IOCTL_XE_WAIT_USER_FENCEuh1hhjhKhj ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jJj8jJj9j:j;uh1jhhhj@hj\hNubj=)}(hXu**Definition**:: struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``addr`` user pointer address to wait on, must qword aligned ``op`` wait operation (type of comparison) ``flags`` wait flags ``pad`` MBZ ``value`` compare value ``mask`` comparison mask ``timeout`` how long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait will end at timeout (uses system MONOTONIC_CLOCK). Passing negative timeout leads to neverending wait. On relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time). ``exec_queue_id`` exec_queue_id returned from xe_exec_queue_create_ioctl ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRubh:}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjNubj`)}(hX*struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; };h]hX*struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; };}hjosbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjNubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjNubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h=``addr`` user pointer address to wait on, must qword aligned h](j)}(h``addr``h]j)}(hjh]haddr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h3user pointer address to wait on, must qword alignedh]h3user pointer address to wait on, must qword aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h+``op`` wait operation (type of comparison) h](j)}(h``op``h]j)}(hjh]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubj)}(hhh]h)}(h#wait operation (type of comparison)h]h#wait operation (type of comparison)}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj&hKhjubh)}(h``flags`` wait flags h](j)}(h ``flags``h]j)}(hjJh]hflags}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjDubj)}(hhh]h)}(h wait flagsh]h wait flags}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1hhj_hKhjubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj}ubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``value`` compare value h](j)}(h ``value``h]j)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h compare valueh]h compare value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``mask`` comparison mask h](j)}(h``mask``h]j)}(hjh]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hcomparison maskh]hcomparison mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hKhjubh)}(hXl``timeout`` how long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait will end at timeout (uses system MONOTONIC_CLOCK). Passing negative timeout leads to neverending wait. On relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time). h](j)}(h ``timeout``h]j)}(hj.h]htimeout}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubj)}(hhh](h)}(hXhow long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait will end at timeout (uses system MONOTONIC_CLOCK). Passing negative timeout leads to neverending wait.h]hXhow long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait will end at timeout (uses system MONOTONIC_CLOCK). Passing negative timeout leads to neverending wait.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjDubh)}(hOn relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time).h]hOn relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time).}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjDubeh}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1hhjChMhjubh)}(hI``exec_queue_id`` exec_queue_id returned from xe_exec_queue_create_ioctl h](j)}(h``exec_queue_id``h]j)}(hjwh]h exec_queue_id}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjqubj)}(hhh]h)}(h6exec_queue_id returned from xe_exec_queue_create_ioctlh]h6exec_queue_id returned from xe_exec_queue_create_ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjNubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hj,h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj@hhubh)}(h|Wait on user fence, XE will wake-up on every HW engine interrupt in the instances list and check if user fence is complete::h]h{Wait on user fence, XE will wake-up on every HW engine interrupt in the instances list and check if user fence is complete:}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj`)}(h (*addr & MASK) OP (VALUE & MASK)h]h (*addr & MASK) OP (VALUE & MASK)}hjQsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(h4Returns to user on user fence completion or timeout.h]h4Returns to user on user fence completion or timeout.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hhh](h)}(hThe **op** can be: - ``DRM_XE_UFENCE_WAIT_OP_EQ`` - ``DRM_XE_UFENCE_WAIT_OP_NEQ`` - ``DRM_XE_UFENCE_WAIT_OP_GT`` - ``DRM_XE_UFENCE_WAIT_OP_GTE`` - ``DRM_XE_UFENCE_WAIT_OP_LT`` - ``DRM_XE_UFENCE_WAIT_OP_LTE`` h](j)}(hThe **op** can be:h](hThe }(hjvhhhNhNubh)}(h**op**h]hop}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvubh can be:}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjrubj)}(hhh]jp )}(hhh](ju )}(h``DRM_XE_UFENCE_WAIT_OP_EQ``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_EQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_UFENCE_WAIT_OP_NEQ``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_NEQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_UFENCE_WAIT_OP_GT``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_GT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_UFENCE_WAIT_OP_GTE``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_GTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_UFENCE_WAIT_OP_LT``h]h)}(hj#h]j)}(hj#h]hDRM_XE_UFENCE_WAIT_OP_LT}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj!ubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h``DRM_XE_UFENCE_WAIT_OP_LTE`` h]h)}(h``DRM_XE_UFENCE_WAIT_OP_LTE``h]j)}(hjHh]hDRM_XE_UFENCE_WAIT_OP_LTE}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1hhjhMhjBubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1hhjhMhjoubh)}(hfand the **flags** can be: - ``DRM_XE_UFENCE_WAIT_FLAG_ABSTIME`` - ``DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP`` h](j)}(hand the **flags** can be:h](hand the }(hjyhhhNhNubh)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyubh can be:}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjuubj)}(hhh]jp )}(hhh](ju )}(h#``DRM_XE_UFENCE_WAIT_FLAG_ABSTIME``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_FLAG_ABSTIME}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h$``DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP`` h]h)}(h#``DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP``h]j)}(hjh]hDRM_XE_UFENCE_WAIT_FLAG_SOFT_OP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1hhjhMhjoubh)}(hThe **mask** values can be for example: - 0xffu for u8 - 0xffffu for u16 - 0xffffffffu for u32 - 0xffffffffffffffffu for u64 h](j)}(h'The **mask** values can be for example:h](hThe }(hjhhhNhNubh)}(h**mask**h]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh values can be for example:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]jp )}(hhh](ju )}(h 0xffu for u8h]h)}(hj!h]h 0xffu for u8}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h0xffffu for u16h]h)}(hj9h]h0xffffu for u16}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj7ubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h0xffffffffu for u32h]h)}(hjQh]h0xffffffffu for u32}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjOubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h0xffffffffffffffffu for u64 h]h)}(h0xffffffffffffffffu for u64h]h0xffffffffffffffffu for u64}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjgubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hj0hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjoubeh}(h]h ]h"]h$]h&]uh1hhj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_observation_type (C enum)c.drm_xe_observation_typehNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_observation_typeh]j)}(henum drm_xe_observation_typeh](j)}(hj?h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_observation_typeh]j)}(hjh]hdrm_xe_observation_type}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hObservation stream typesh]hObservation stream types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhj@hj\hNubj=)}(h**Constants** ``DRM_XE_OBSERVATION_TYPE_OA`` OA observation stream type ``DRM_XE_OBSERVATION_TYPE_EU_STALL`` EU stall sampling observation stream typeh](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubh)}(hhh](h)}(h:``DRM_XE_OBSERVATION_TYPE_OA`` OA observation stream type h](j)}(h``DRM_XE_OBSERVATION_TYPE_OA``h]j)}(hj4h]hDRM_XE_OBSERVATION_TYPE_OA}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj.ubj)}(hhh]h)}(hOA observation stream typeh]hOA observation stream type}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMhjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1hhjIhMhj+ubh)}(hN``DRM_XE_OBSERVATION_TYPE_EU_STALL`` EU stall sampling observation stream typeh](j)}(h$``DRM_XE_OBSERVATION_TYPE_EU_STALL``h]j)}(hjmh]h DRM_XE_OBSERVATION_TYPE_EU_STALL}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjgubj)}(hhh]h)}(h)EU stall sampling observation stream typeh]h)EU stall sampling observation stream type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1hhjhMhj+ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_observation_op (C enum)c.drm_xe_observation_ophNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_observation_oph]j)}(henum drm_xe_observation_oph](j)}(hj?h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_observation_oph]j)}(hjh]hdrm_xe_observation_op}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hObservation stream opsh]hObservation stream ops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7j!j8j!j9j:j;uh1jhhhj@hj\hNubj=)}(h**Constants** ``DRM_XE_OBSERVATION_OP_STREAM_OPEN`` Open an observation stream ``DRM_XE_OBSERVATION_OP_ADD_CONFIG`` Add observation stream config ``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG`` Remove observation stream configh](h)}(h **Constants**h]h)}(hj+h]h Constants}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj%ubh)}(hhh](h)}(hA``DRM_XE_OBSERVATION_OP_STREAM_OPEN`` Open an observation stream h](j)}(h%``DRM_XE_OBSERVATION_OP_STREAM_OPEN``h]j)}(hjJh]h!DRM_XE_OBSERVATION_OP_STREAM_OPEN}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjDubj)}(hhh]h)}(hOpen an observation streamh]hOpen an observation stream}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hMhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1hhj_hMhjAubh)}(hC``DRM_XE_OBSERVATION_OP_ADD_CONFIG`` Add observation stream config h](j)}(h$``DRM_XE_OBSERVATION_OP_ADD_CONFIG``h]j)}(hjh]h DRM_XE_OBSERVATION_OP_ADD_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj}ubj)}(hhh]h)}(hAdd observation stream configh]hAdd observation stream config}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1hhjhMhjAubh)}(hH``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG`` Remove observation stream configh](j)}(h'``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG``h]j)}(hjh]h#DRM_XE_OBSERVATION_OP_REMOVE_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h Remove observation stream configh]h Remove observation stream config}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjAubeh}(h]h ]h"]h$]h&]uh1hhj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_xe_observation_param (C struct)c.drm_xe_observation_paramhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_observation_paramh]j)}(hstruct drm_xe_observation_paramh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM#ubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj#hM#ubj)}(hdrm_xe_observation_paramh]j)}(hjh]hdrm_xe_observation_param}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj#hM#ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj#hM#ubah}(h]j ah ](j j eh"]h$]h&]jj)jhuh1jhj#hM#hj hhubj)}(hhh]h)}(h%Input of :c:type:`DRM_XE_OBSERVATION`h](h Input of }(hjXhhhNhNubh)}(h:c:type:`DRM_XE_OBSERVATION`h]j)}(hjbh]hDRM_XE_OBSERVATION}(hjdhhhNhNubah}(h]h ](j j1c-typeeh"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]refdocj refdomainj1reftypetype refexplicitrefwarnj j )}j ]j)}jjsbc.drm_xe_observation_paramasbj DRM_XE_OBSERVATIONuh1hhjhKhjXubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjUhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj#hM#ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``observation_type`` observation stream type, of enum **drm_xe_observation_type** ``observation_op`` observation stream op, of enum **drm_xe_observation_op** ``param`` Pointer to actual stream paramsh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM#hjubj`)}(hstruct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; };h]hstruct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM%hjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM,hjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM'hjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM'hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM'hjubh)}(hR``observation_type`` observation stream type, of enum **drm_xe_observation_type** h](j)}(h``observation_type``h]j)}(hj$h]hobservation_type}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hh]hdrm_xe_oa_unit}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj@hhhjQhMYubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj<hhhjQhMYubah}(h]j7ah ](j j eh"]h$]h&]jj)jhuh1jhjQhMYhj9hhubj)}(hhh]h)}(hdescribe OA unith]hdescribe OA unit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMWhjhhubah}(h]h ]h"]h$]h&]uh1jhj9hhhjQhMYubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hXZ**Definition**:: struct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); __u64 oa_timestamp_freq; __u64 reserved[4]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``oa_unit_id`` OA unit ID ``oa_unit_type`` OA unit type of **drm_xe_oa_unit_type** ``capabilities`` OA capabilities bit-mask ``oa_timestamp_freq`` OA timestamp freq ``reserved`` MBZ ``num_engines`` number of engines in **eci** array ``eci`` engines attached to this OA unith](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM[hjubj`)}(hXstruct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); __u64 oa_timestamp_freq; __u64 reserved[4]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; };h]hXstruct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); __u64 oa_timestamp_freq; __u64 reserved[4]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM]hjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMZhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMZhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMZhjubh)}(h``oa_unit_id`` OA unit ID h](j)}(h``oa_unit_id``h]j)}(hj,h]h oa_unit_id}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj&ubj)}(hhh]h)}(h OA unit IDh]h OA unit ID}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhKhjBubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1hhjAhKhjubh)}(h9``oa_unit_type`` OA unit type of **drm_xe_oa_unit_type** h](j)}(h``oa_unit_type``h]j)}(hjeh]h oa_unit_type}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj_ubj)}(hhh]h)}(h'OA unit type of **drm_xe_oa_unit_type**h](hOA unit type of }(hj~hhhNhNubh)}(h**drm_xe_oa_unit_type**h]hdrm_xe_oa_unit_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~ubeh}(h]h ]h"]h$]h&]uh1hhjzhKhj{ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1hhjzhKhjubh)}(h*``capabilities`` OA capabilities bit-mask h](j)}(h``capabilities``h]j)}(hjh]h capabilities}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hOA capabilities bit-maskh]hOA capabilities bit-mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h(``oa_timestamp_freq`` OA timestamp freq h](j)}(h``oa_timestamp_freq``h]j)}(hjh]hoa_timestamp_freq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hOA timestamp freqh]hOA timestamp freq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h``reserved`` MBZ h](j)}(h ``reserved``h]j)}(hjh]hreserved}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hMBZh]hMBZ}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hKhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj3hKhjubh)}(h3``num_engines`` number of engines in **eci** array h](j)}(h``num_engines``h]j)}(hjWh]h num_engines}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjQubj)}(hhh]h)}(h"number of engines in **eci** arrayh](hnumber of engines in }(hjphhhNhNubh)}(h**eci**h]heci}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpubh array}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjlhKhjmubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1hhjlhKhjubh)}(h(``eci`` engines attached to this OA unith](j)}(h``eci``h]j)}(hjh]heci}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h engines attached to this OA unith]h engines attached to this OA unit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_query_oa_units (C struct)c.drm_xe_query_oa_unitshNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_oa_unitsh]j)}(hstruct drm_xe_query_oa_unitsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj hKubj)}(hdrm_xe_query_oa_unitsh]j)}(hjh]hdrm_xe_query_oa_units}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj hKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhj hKhjhhubj)}(hhh]h)}(hdescribe OA unitsh]hdescribe OA units}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMxhj; hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jV j8jV j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``num_oa_units`` number of OA units returned in oau[] ``pad`` MBZ ``oa_units`` struct **drm_xe_oa_unit** array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjb hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^ ubh:}(hj^ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM|hjZ ubj`)}(htstruct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; };h]htstruct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; };}hj{ sbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hjZ ubh)}(h **Members**h]h)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjZ ubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj h]h extensions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj ubh)}(h6``num_oa_units`` number of OA units returned in oau[] h](j)}(h``num_oa_units``h]j)}(hj h]h num_oa_units}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubj)}(hhh]h)}(h$number of OA units returned in oau[]h]h$number of OA units returned in oau[]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hKhj ubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj h]hpad}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubj)}(hhh]h)}(hMBZh]hMBZ}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2 hKhj3 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj2 hKhj ubh)}(h``oa_units`` struct **drm_xe_oa_unit** array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](j)}(h ``oa_units``h]j)}(hjV h]hoa_units}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjP ubj)}(hhh]h)}(hstruct **drm_xe_oa_unit** array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](hstruct }(hjo hhhNhNubh)}(h**drm_xe_oa_unit**h]hdrm_xe_oa_unit}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjo ubh array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilers}(hjo hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjl ubah}(h]h ]h"]h$]h&]uh1jhjP ubeh}(h]h ]h"]h$]h&]uh1hhjk hMhj ubeh}(h]h ]h"]h$]h&]uh1hhjZ ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct drm_xe_query_oa_units in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct drm_xe_query_oa_units in .data.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMyhj@hhubh)}(h]OA unit properties for all OA units can be accessed using a code block such as the one below:h]h]OA unit properties for all OA units can be accessed using a code block such as the one below:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM}hj@hhubj`)}(hXstruct drm_xe_query_oa_units *qoa; struct drm_xe_oa_unit *oau; u8 *poau; // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: poau = (u8 *)&qoa->oa_units[0]; for (int i = 0; i < qoa->num_oa_units; i++) { oau = (struct drm_xe_oa_unit *)poau; // Access 'struct drm_xe_oa_unit' fields here poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); }h]hXstruct drm_xe_query_oa_units *qoa; struct drm_xe_oa_unit *oau; u8 *poau; // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: poau = (u8 *)&qoa->oa_units[0]; for (int i = 0; i < qoa->num_oa_units; i++) { oau = (struct drm_xe_oa_unit *)poau; // Access 'struct drm_xe_oa_unit' fields here poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); }}hj sbah}(h]h ]h"]h$]h&]jjjjjj}uh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_oa_format_type (C enum)c.drm_xe_oa_format_typehNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_oa_format_typeh]j)}(henum drm_xe_oa_format_typeh](j)}(hj?h]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMubj)}(hdrm_xe_oa_format_typeh]j)}(hj h]hdrm_xe_oa_format_type}(hj( hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hMubah}(h]j ah ](j j eh"]h$]h&]jj)jhuh1jhj hMhj hhubj)}(hhh]h)}(h5OA format types as specified in PRM/Bspec 52198/60942h]h5OA format types as specified in PRM/Bspec 52198/60942}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjG hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jb j8jb j9j:j;uh1jhhhj@hj\hNubj=)}(hXF**Constants** ``DRM_XE_OA_FMT_TYPE_OAG`` OAG report format ``DRM_XE_OA_FMT_TYPE_OAR`` OAR report format ``DRM_XE_OA_FMT_TYPE_OAM`` OAM report format ``DRM_XE_OA_FMT_TYPE_OAC`` OAC report format ``DRM_XE_OA_FMT_TYPE_OAM_MPEC`` OAM SAMEDIA or OAM MPEC report format ``DRM_XE_OA_FMT_TYPE_PEC`` PEC report formath](h)}(h **Constants**h]h)}(hjl h]h Constants}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjf ubh)}(hhh](h)}(h-``DRM_XE_OA_FMT_TYPE_OAG`` OAG report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAG``h]j)}(hj h]hDRM_XE_OA_FMT_TYPE_OAG}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hOAG report formath]hOAG report format}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj ubh)}(h-``DRM_XE_OA_FMT_TYPE_OAR`` OAR report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAR``h]j)}(hj h]hDRM_XE_OA_FMT_TYPE_OAR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hOAR report formath]hOAR report format}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj ubh)}(h-``DRM_XE_OA_FMT_TYPE_OAM`` OAM report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAM``h]j)}(hj h]hDRM_XE_OA_FMT_TYPE_OAM}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hOAM report formath]hOAM report format}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj ubh)}(h-``DRM_XE_OA_FMT_TYPE_OAC`` OAC report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAC``h]j)}(hj6 h]hDRM_XE_OA_FMT_TYPE_OAC}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4 ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj0 ubj)}(hhh]h)}(hOAC report formath]hOAC report format}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjK hMhjL ubah}(h]h ]h"]h$]h&]uh1jhj0 ubeh}(h]h ]h"]h$]h&]uh1hhjK hMhj ubh)}(hF``DRM_XE_OA_FMT_TYPE_OAM_MPEC`` OAM SAMEDIA or OAM MPEC report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAM_MPEC``h]j)}(hjo h]hDRM_XE_OA_FMT_TYPE_OAM_MPEC}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhji ubj)}(hhh]h)}(h%OAM SAMEDIA or OAM MPEC report formath]h%OAM SAMEDIA or OAM MPEC report format}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhji ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj ubh)}(h,``DRM_XE_OA_FMT_TYPE_PEC`` PEC report formath](j)}(h``DRM_XE_OA_FMT_TYPE_PEC``h]j)}(hj h]hDRM_XE_OA_FMT_TYPE_PEC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hPEC report formath]hPEC report format}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1hhjf ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_oa_property_id (C enum)c.drm_xe_oa_property_idhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_oa_property_idh]j)}(henum drm_xe_oa_property_idh](j)}(hj?h]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMubj)}(hdrm_xe_oa_property_idh]j)}(hj h]hdrm_xe_oa_property_id}(hj" hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hMubah}(h]j ah ](j j eh"]h$]h&]jj)jhuh1jhj hMhj hhubj)}(hhh]h)}(hOA stream property id'sh]hOA stream property id’s}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjA hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7j\ j8j\ j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Constants** ``DRM_XE_OA_PROPERTY_OA_UNIT_ID`` ID of the OA unit on which to open the OA stream, see **oa_unit_id** in 'struct drm_xe_query_oa_units'. Defaults to 0 if not provided. ``DRM_XE_OA_PROPERTY_SAMPLE_OA`` A value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit. ``DRM_XE_OA_PROPERTY_OA_METRIC_SET`` OA metrics defining contents of OA reports, previously added via **DRM_XE_OBSERVATION_OP_ADD_CONFIG**. ``DRM_XE_OA_PROPERTY_OA_FORMAT`` OA counter report format ``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT`` Requests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1) ``DRM_XE_OA_PROPERTY_OA_DISABLED`` A value of 1 will open the OA stream in a DISABLED state (see **DRM_XE_OBSERVATION_IOCTL_ENABLE**). ``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` Open the stream for a specific **exec_queue_id**. OA queries can be executed on this exec queue. ``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE`` Optional engine instance to pass along with **DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID** or will default to 0. ``DRM_XE_OA_PROPERTY_NO_PREEMPT`` Allow preemption and timeslicing to be disabled for the stream exec queue. ``DRM_XE_OA_PROPERTY_NUM_SYNCS`` Number of syncs in the sync array specified in **DRM_XE_OA_PROPERTY_SYNCS** ``DRM_XE_OA_PROPERTY_SYNCS`` Pointer to struct **drm_xe_sync** array with array size specified via **DRM_XE_OA_PROPERTY_NUM_SYNCS**. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For **DRM_XE_SYNC_TYPE_USER_FENCE**, **addr** is a user pointer, similar to the VM bind case. ``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE`` Size of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default. ``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS`` Number of reports to wait for before unblocking poll or readh](h)}(h **Constants**h]h)}(hjf h]h Constants}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjd ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj` ubh)}(hhh](h)}(h``DRM_XE_OA_PROPERTY_OA_UNIT_ID`` ID of the OA unit on which to open the OA stream, see **oa_unit_id** in 'struct drm_xe_query_oa_units'. Defaults to 0 if not provided. h](j)}(h!``DRM_XE_OA_PROPERTY_OA_UNIT_ID``h]j)}(hj h]hDRM_XE_OA_PROPERTY_OA_UNIT_ID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hID of the OA unit on which to open the OA stream, see **oa_unit_id** in 'struct drm_xe_query_oa_units'. Defaults to 0 if not provided.h](h6ID of the OA unit on which to open the OA stream, see }(hj hhhNhNubh)}(h**oa_unit_id**h]h oa_unit_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubhF in ‘struct drm_xe_query_oa_units’. Defaults to 0 if not provided.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj| ubh)}(h``DRM_XE_OA_PROPERTY_SAMPLE_OA`` A value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit. h](j)}(h ``DRM_XE_OA_PROPERTY_SAMPLE_OA``h]j)}(hj h]hDRM_XE_OA_PROPERTY_SAMPLE_OA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj)}(hhh]h)}(hsA value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit.h]hsA value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj hMhj| ubh)}(h``DRM_XE_OA_PROPERTY_OA_METRIC_SET`` OA metrics defining contents of OA reports, previously added via **DRM_XE_OBSERVATION_OP_ADD_CONFIG**. h](j)}(h$``DRM_XE_OA_PROPERTY_OA_METRIC_SET``h]j)}(hj h]h DRM_XE_OA_PROPERTY_OA_METRIC_SET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hfOA metrics defining contents of OA reports, previously added via **DRM_XE_OBSERVATION_OP_ADD_CONFIG**.h](hAOA metrics defining contents of OA reports, previously added via }(hj$hhhNhNubh)}(h$**DRM_XE_OBSERVATION_OP_ADD_CONFIG**h]h DRM_XE_OBSERVATION_OP_ADD_CONFIG}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$ubh.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj hMhj| ubh)}(h:``DRM_XE_OA_PROPERTY_OA_FORMAT`` OA counter report format h](j)}(h ``DRM_XE_OA_PROPERTY_OA_FORMAT``h]j)}(hjWh]hDRM_XE_OA_PROPERTY_OA_FORMAT}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjQubj)}(hhh]h)}(hOA counter report formath]hOA counter report format}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMhjmubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1hhjlhMhj| ubh)}(h``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT`` Requests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1) h](j)}(h)``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT``h]j)}(hjh]h%DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hbRequests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1)h]hbRequests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj| ubh)}(h``DRM_XE_OA_PROPERTY_OA_DISABLED`` A value of 1 will open the OA stream in a DISABLED state (see **DRM_XE_OBSERVATION_IOCTL_ENABLE**). h](j)}(h"``DRM_XE_OA_PROPERTY_OA_DISABLED``h]j)}(hjh]hDRM_XE_OA_PROPERTY_OA_DISABLED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hcA value of 1 will open the OA stream in a DISABLED state (see **DRM_XE_OBSERVATION_IOCTL_ENABLE**).h](h>A value of 1 will open the OA stream in a DISABLED state (see }(hjhhhNhNubh)}(h#**DRM_XE_OBSERVATION_IOCTL_ENABLE**h]hDRM_XE_OBSERVATION_IOCTL_ENABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj| ubh)}(h``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` Open the stream for a specific **exec_queue_id**. OA queries can be executed on this exec queue. h](j)}(h$``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID``h]j)}(hjh]h DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(h`Open the stream for a specific **exec_queue_id**. OA queries can be executed on this exec queue.h](hOpen the stream for a specific }(hj/hhhNhNubh)}(h**exec_queue_id**h]h exec_queue_id}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/ubh0. OA queries can be executed on this exec queue.}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj+hMhj| ubh)}(h``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE`` Optional engine instance to pass along with **DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID** or will default to 0. h](j)}(h)``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE``h]j)}(hjbh]h%DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj\ubj)}(hhh]h)}(hfOptional engine instance to pass along with **DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID** or will default to 0.h](h,Optional engine instance to pass along with }(hj{hhhNhNubh)}(h$**DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID**h]h DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubh or will default to 0.}(hj{hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1hhjwhMhj| ubh)}(hm``DRM_XE_OA_PROPERTY_NO_PREEMPT`` Allow preemption and timeslicing to be disabled for the stream exec queue. h](j)}(h!``DRM_XE_OA_PROPERTY_NO_PREEMPT``h]j)}(hjh]hDRM_XE_OA_PROPERTY_NO_PREEMPT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hJAllow preemption and timeslicing to be disabled for the stream exec queue.h]hJAllow preemption and timeslicing to be disabled for the stream exec queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj| ubh)}(hm``DRM_XE_OA_PROPERTY_NUM_SYNCS`` Number of syncs in the sync array specified in **DRM_XE_OA_PROPERTY_SYNCS** h](j)}(h ``DRM_XE_OA_PROPERTY_NUM_SYNCS``h]j)}(hjh]hDRM_XE_OA_PROPERTY_NUM_SYNCS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hKNumber of syncs in the sync array specified in **DRM_XE_OA_PROPERTY_SYNCS**h](h/Number of syncs in the sync array specified in }(hjhhhNhNubh)}(h**DRM_XE_OA_PROPERTY_SYNCS**h]hDRM_XE_OA_PROPERTY_SYNCS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj| ubh)}(hX_``DRM_XE_OA_PROPERTY_SYNCS`` Pointer to struct **drm_xe_sync** array with array size specified via **DRM_XE_OA_PROPERTY_NUM_SYNCS**. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For **DRM_XE_SYNC_TYPE_USER_FENCE**, **addr** is a user pointer, similar to the VM bind case. h](j)}(h``DRM_XE_OA_PROPERTY_SYNCS``h]j)}(hj0h]hDRM_XE_OA_PROPERTY_SYNCS}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj*ubj)}(hhh]h)}(hXAPointer to struct **drm_xe_sync** array with array size specified via **DRM_XE_OA_PROPERTY_NUM_SYNCS**. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For **DRM_XE_SYNC_TYPE_USER_FENCE**, **addr** is a user pointer, similar to the VM bind case.h](hPointer to struct }(hjIhhhNhNubh)}(h**drm_xe_sync**h]h drm_xe_sync}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubh% array with array size specified via }(hjIhhhNhNubh)}(h **DRM_XE_OA_PROPERTY_NUM_SYNCS**h]hDRM_XE_OA_PROPERTY_NUM_SYNCS}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubh. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For }(hjIhhhNhNubh)}(h**DRM_XE_SYNC_TYPE_USER_FENCE**h]hDRM_XE_SYNC_TYPE_USER_FENCE}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubh, }(hjIhhhNhNubh)}(h**addr**h]haddr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubh0 is a user pointer, similar to the VM bind case.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1hhjEhMhj| ubh)}(h``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE`` Size of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default. h](j)}(h%``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE``h]j)}(hjh]h!DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hSize of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default.h]hSize of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj| ubh)}(hd``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS`` Number of reports to wait for before unblocking poll or readh](j)}(h'``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS``h]j)}(hjh]h#DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hh]hn_regs}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj8ubj)}(hhh]h)}(hNumber of regs in **regs_ptr**h](hNumber of regs in }(hjWhhhNhNubh)}(h **regs_ptr**h]hregs_ptr}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWubeh}(h]h ]h"]h$]h&]uh1hhjShKhjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1hhjShKhjubh)}(h``regs_ptr`` Pointer to (register address, value) pairs for OA config registers. Expected length of buffer is: (2 * sizeof(u32) * **n_regs**).h](j)}(h ``regs_ptr``h]j)}(hjh]hregs_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM1hjubj)}(hhh]h)}(hPointer to (register address, value) pairs for OA config registers. Expected length of buffer is: (2 * sizeof(u32) * **n_regs**).h](huPointer to (register address, value) pairs for OA config registers. Expected length of buffer is: (2 * sizeof(u32) * }(hjhhhNhNubh)}(h **n_regs**h]hn_regs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM1hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM1hjubeh}(h]h ]h"]h$]h&]uh1hhj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM5hj@hhubh)}(hMultiple OA configs can be added using **DRM_XE_OBSERVATION_OP_ADD_CONFIG**. A particular config can be specified when opening an OA stream using **DRM_XE_OA_PROPERTY_OA_METRIC_SET** property.h](h'Multiple OA configs can be added using }(hjhhhNhNubh)}(h$**DRM_XE_OBSERVATION_OP_ADD_CONFIG**h]h DRM_XE_OBSERVATION_OP_ADD_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhG. A particular config can be specified when opening an OA stream using }(hjhhhNhNubh)}(h$**DRM_XE_OA_PROPERTY_OA_METRIC_SET**h]h DRM_XE_OA_PROPERTY_OA_METRIC_SET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh property.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_xe_oa_stream_status (C struct)c.drm_xe_oa_stream_statushNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_oa_stream_statush]j)}(hstruct drm_xe_oa_stream_statush](j)}(hjh]hstruct}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM'ubj)}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7hhhjHhM'ubj)}(hdrm_xe_oa_stream_statush]j)}(hj5h]hdrm_xe_oa_stream_status}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubah}(h]h ](jjeh"]h$]h&]jjuh1jhj7hhhjHhM'ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj3hhhjHhM'ubah}(h]j.ah ](j j eh"]h$]h&]jj)jhuh1jhjHhM'hj0hhubj)}(hhh]h)}(hOA stream status returned from **DRM_XE_OBSERVATION_IOCTL_STATUS** observation stream fd ioctl. Userspace can call the ioctl to query stream status in response to EIO errno from observation fd read().h](hOA stream status returned from }(hj}hhhNhNubh)}(h#**DRM_XE_OBSERVATION_IOCTL_STATUS**h]hDRM_XE_OBSERVATION_IOCTL_STATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}ubh observation stream fd ioctl. Userspace can call the ioctl to query stream status in response to EIO errno from observation fd read().}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM7hjzhhubah}(h]h ]h"]h$]h&]uh1jhj0hhhjHhM'ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX **Definition**:: struct drm_xe_oa_stream_status { __u64 extensions; __u64 oa_status; #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3); #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2); #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1); #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0); __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``oa_status`` OA stream status (see Bspec 46717/61226) ``reserved`` reserved for future useh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM;hjubj`)}(hXMstruct drm_xe_oa_stream_status { __u64 extensions; __u64 oa_status; #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3); #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2); #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1); #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0); __u64 reserved[3]; };h]hXMstruct drm_xe_oa_stream_status { __u64 extensions; __u64 oa_status; #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3); #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2); #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1); #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0); __u64 reserved[3]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=hjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMGhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=hjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhM=hjubh)}(h7``oa_status`` OA stream status (see Bspec 46717/61226) h](j)}(h ``oa_status``h]j)}(hj5h]h oa_status}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj/ubj)}(hhh]h)}(h(OA stream status (see Bspec 46717/61226)h]h(OA stream status (see Bspec 46717/61226)}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhKhjKubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1hhjJhKhjubh)}(h$``reserved`` reserved for future useh](j)}(h ``reserved``h]j)}(hjnh]hreserved}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjhubj)}(hhh]h)}(hreserved for future useh]hreserved for future use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_oa_stream_info (C struct)c.drm_xe_oa_stream_infohNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_oa_stream_infoh]j)}(hstruct drm_xe_oa_stream_infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hdrm_xe_oa_stream_infoh]j)}(hjh]hdrm_xe_oa_stream_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hZOA stream info returned from **DRM_XE_OBSERVATION_IOCTL_INFO** observation stream fd ioctlh](hOA stream info returned from }(hj hhhNhNubh)}(h!**DRM_XE_OBSERVATION_IOCTL_INFO**h]hDRM_XE_OBSERVATION_IOCTL_INFO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh observation stream fd ioctl}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMLhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j4j8j4j9j:j;uh1jhhhj@hj\hNubj=)}(hX**Definition**:: struct drm_xe_oa_stream_info { __u64 extensions; __u64 oa_buf_size; __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``oa_buf_size`` OA buffer size ``reserved`` reserved for future useh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubh:}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMPhj8ubj`)}(hestruct drm_xe_oa_stream_info { __u64 extensions; __u64 oa_buf_size; __u64 reserved[3]; };h]hestruct drm_xe_oa_stream_info { __u64 extensions; __u64 oa_buf_size; __u64 reserved[3]; };}hjYsbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMRhj8ubh)}(h **Members**h]h)}(hjjh]hMembers}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMXhj8ubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMPhjubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMPhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMPhjubh)}(h``oa_buf_size`` OA buffer size h](j)}(h``oa_buf_size``h]j)}(hjh]h oa_buf_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hOA buffer sizeh]hOA buffer size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubh)}(h$``reserved`` reserved for future useh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hreserved for future useh]hreserved for future use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_pxp_session_type (C enum)c.drm_xe_pxp_session_typehNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_pxp_session_typeh]j)}(henum drm_xe_pxp_session_typeh](j)}(hj?h]henum}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQhhhjbhKubj)}(hdrm_xe_pxp_session_typeh]j)}(hjOh]hdrm_xe_pxp_session_type}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubah}(h]h ](jjeh"]h$]h&]jjuh1jhjQhhhjbhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjMhhhjbhKubah}(h]jHah ](j j eh"]h$]h&]jj)jhuh1jhjbhKhjJhhubj)}(hhh]h)}(hSupported PXP session types.h]hSupported PXP session types.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM[hjhhubah}(h]h ]h"]h$]h&]uh1jhjJhhhjbhKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(h**Constants** ``DRM_XE_PXP_TYPE_NONE`` PXP not used ``DRM_XE_PXP_TYPE_HWDRM`` HWDRM sessions are used for content that ends up on the display.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM_hjubh)}(hhh](h)}(h&``DRM_XE_PXP_TYPE_NONE`` PXP not used h](j)}(h``DRM_XE_PXP_TYPE_NONE``h]j)}(hjh]hDRM_XE_PXP_TYPE_NONE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMbhjubj)}(hhh]h)}(h PXP not usedh]h PXP not used}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMbhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMbhjubh)}(hZ``DRM_XE_PXP_TYPE_HWDRM`` HWDRM sessions are used for content that ends up on the display.h](j)}(h``DRM_XE_PXP_TYPE_HWDRM``h]j)}(hjh]hDRM_XE_PXP_TYPE_HWDRM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMehj ubj)}(hhh]h)}(h@HWDRM sessions are used for content that ends up on the display.h]h@HWDRM sessions are used for content that ends up on the display.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hMehj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hhj&hMehjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjSh]h Description}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhhj@hhubh)}(hWe currently only support HWDRM sessions, which are used for protected content that ends up being displayed, but the HW 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](j j eh"]h$]h&]jj)jhuh1jhjhMchjhhubj)}(hhh]h)}(h%EU stall sampling input property ids.h]h%EU stall sampling input property ids.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMohjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMcubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jj8jj9j:j;uh1jhhhj@hj\hNubj=)}(hX**Constants** ``DRM_XE_EU_STALL_PROP_GT_ID`` **gt_id** of the GT on which EU stall data will be captured. ``DRM_XE_EU_STALL_PROP_SAMPLE_RATE`` Sampling rate in GPU cycles from **sampling_rates** in struct **drm_xe_query_eu_stall** ``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS`` Minimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMshjubh)}(hhh](h)}(h\``DRM_XE_EU_STALL_PROP_GT_ID`` **gt_id** of the GT on which EU stall data will be captured. h](j)}(h``DRM_XE_EU_STALL_PROP_GT_ID``h]j)}(hjh]hDRM_XE_EU_STALL_PROP_GT_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMwhjubj)}(hhh]h)}(h<**gt_id** of the GT on which EU stall data will be captured.h](h)}(h **gt_id**h]hgt_id}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-ubh3 of the GT on which EU stall data will be captured.}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMvhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj)hMwhj ubh)}(h}``DRM_XE_EU_STALL_PROP_SAMPLE_RATE`` Sampling rate in GPU cycles from **sampling_rates** in struct **drm_xe_query_eu_stall** h](j)}(h$``DRM_XE_EU_STALL_PROP_SAMPLE_RATE``h]j)}(hj\h]h DRM_XE_EU_STALL_PROP_SAMPLE_RATE}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM{hjVubj)}(hhh]h)}(hWSampling rate in GPU cycles from **sampling_rates** in struct **drm_xe_query_eu_stall**h](h!Sampling rate in GPU cycles from }(hjuhhhNhNubh)}(h**sampling_rates**h]hsampling_rates}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuubh in struct }(hjuhhhNhNubh)}(h**drm_xe_query_eu_stall**h]hdrm_xe_query_eu_stall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMzhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1hhjqhM{hj ubh)}(h``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS`` Minimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h](j)}(h)``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS``h]j)}(hjh]h%DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(htMinimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h]htMinimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhj ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hj@hhhj\hNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj@hhubh)}(hX;These properties are passed to the driver at open as a chain of **drm_xe_ext_set_property** structures with **property** set to these properties' enums and **value** set to the corresponding values of these properties. **drm_xe_user_extension** base.name should be set to **DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY**.h](h@These properties are passed to the driver at open as a chain of }(hjhhhNhNubh)}(h**drm_xe_ext_set_property**h]hdrm_xe_ext_set_property}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh structures with }(hjhhhNhNubh)}(h **property**h]hproperty}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh& set to these properties’ enums and }(hjhhhNhNubh)}(h **value**h]hvalue}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh6 set to the corresponding values of these properties. }(hjhhhNhNubh)}(h**drm_xe_user_extension**h]hdrm_xe_user_extension}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh base.name should be set to }(hjhhhNhNubh)}(h***DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY**h]h&DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMphj@hhubh)}(hWith the file descriptor obtained from open, user space must enable the EU stall stream fd with **DRM_XE_OBSERVATION_IOCTL_ENABLE** before calling read(). EIO errno from read() indicates HW dropped data due to full buffer.h](h`With the file descriptor obtained from open, user space must enable the EU stall stream fd with }(hjxhhhNhNubh)}(h#**DRM_XE_OBSERVATION_IOCTL_ENABLE**h]hDRM_XE_OBSERVATION_IOCTL_ENABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxubh[ before calling read(). EIO errno from read() indicates HW dropped data due to full buffer.}(hjxhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMvhj@hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_query_eu_stall (C struct)c.drm_xe_query_eu_stallhNtauh1jhj@hhhj\hNubj)}(hhh](j)}(hdrm_xe_query_eu_stallh]j)}(hstruct drm_xe_query_eu_stallh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM~ubj)}(hdrm_xe_query_eu_stallh]j)}(hjh]hdrm_xe_query_eu_stall}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM~ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM~ubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhM~hjhhubj)}(hhh]h)}(h$Information about EU stall sampling.h]h$Information about EU stall sampling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM~ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j j8j j9j:j;uh1jhhhj@hj\hNubj=)}(hX#**Definition**:: struct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``capabilities`` EU stall capabilities bit-mask ``record_size`` size of each EU stall data record ``per_xecore_buf_size`` internal per XeCore buffer size ``reserved`` Reserved ``num_sampling_rates`` Number of sampling rates in **sampling_rates** array ``sampling_rates`` Flexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj`)}(hXstruct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; };h]hXstruct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; };}hj1sbah}(h]h ]h"]h$]h&]jjuh1j_hY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjBh]hMembers}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(hhh](h)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjah]h extensions}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj[ubj)}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1hhjvhMhjXubh)}(h0``capabilities`` EU stall capabilities bit-mask h](j)}(h``capabilities``h]j)}(hjh]h capabilities}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hEU stall capabilities bit-maskh]hEU stall capabilities bit-mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjXubh)}(h2``record_size`` size of each EU stall data record h](j)}(h``record_size``h]j)}(hjh]h record_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(h!size of each EU stall data recordh]h!size of each EU stall data record}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhjhKhjXubh)}(h8``per_xecore_buf_size`` internal per XeCore buffer size h](j)}(h``per_xecore_buf_size``h]j)}(hj h]hper_xecore_buf_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj)}(hhh]h)}(hinternal per XeCore buffer sizeh]hinternal per XeCore buffer size}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hKhj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhj!hKhjXubh)}(h``reserved`` Reserved h](j)}(h ``reserved``h]j)}(hjEh]hreserved}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj?ubj)}(hhh]h)}(hReservedh]hReserved}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhKhj[ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1hhjZhKhjXubh)}(hL``num_sampling_rates`` Number of sampling rates in **sampling_rates** array h](j)}(h``num_sampling_rates``h]j)}(hj~h]hnum_sampling_rates}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjxubj)}(hhh]h)}(h4Number of sampling rates in **sampling_rates** arrayh](hNumber of sampling rates in }(hjhhhNhNubh)}(h**sampling_rates**h]hsampling_rates}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh array}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1hhjhKhjXubh)}(h``sampling_rates`` Flexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h](j)}(h``sampling_rates``h]j)}(hjh]hsampling_rates}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj)}(hhh]h)}(hzFlexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h]hzFlexible array of sampling rates sorted in the fastest to slowest order. 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If the object is not naturally aligned, a padding field must be added.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]h)}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]h)}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]hNAll padding fields will be checked by the driver to make sure they are zeroed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h-Flags can be added, but not removed/replaced.h]h)}(hjh]h-Flags can be added, but not removed/replaced.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]h)}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj*ubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_asahi_cmd_header::size).h]h)}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_asahi_cmd_header::size).h]hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_asahi_cmd_header::size).}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK"hjCubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]h)}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK&hj\ubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h)}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK(hjuubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to guess which flags are supported.h]h)}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to guess which flags are supported.h]hEach new flag/field addition must come with a driver version update so the userspace driver doesn’t have to guess which flags are supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK*hjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h)}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h`Structures should not contain unions, as this would defeat the extensibility of such structures.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK,hjubah}(h]h ]h"]h$]h&]uh1jt hjubju )}(hrIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_asahi_ioctl_id enum. h]h)}(hnIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_asahi_ioctl_id enum.h]hpIOCTLs can’t be removed or replaced. New IOCTL IDs should be placed at the end of the drm_asahi_ioctl_id enum.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK.hjubah}(h]h ]h"]h$]h&]uh1jt hjubeh}(h]h ]h"]h$]h&]j j uh1jo hjhKhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_ioctl_id (C enum)c.drm_asahi_ioctl_idhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_ioctl_idh]j)}(henum drm_asahi_ioctl_idh](j)}(hj?h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK4ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhK4ubj)}(hdrm_asahi_ioctl_idh]j)}(hjh]hdrm_asahi_ioctl_id}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhK4ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhK4ubah}(h]jah ](j j eh"]h$]h&]jj)jhuh1jhjhK4hjhhubj)}(hhh]h)}(h IOCTL IDsh]h IOCTL IDs}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK5hj7hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhK4ubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jRj8jRj9j:j;uh1jhhhjohNhNubj=)}(hX**Constants** ``DRM_ASAHI_GET_PARAMS`` Query device properties. ``DRM_ASAHI_GET_TIME`` Query device time. ``DRM_ASAHI_VM_CREATE`` Create a GPU VM address space. ``DRM_ASAHI_VM_DESTROY`` Destroy a VM. ``DRM_ASAHI_VM_BIND`` Bind/unbind memory to a VM. ``DRM_ASAHI_GEM_CREATE`` Create a buffer object. ``DRM_ASAHI_GEM_MMAP_OFFSET`` Get offset to pass to mmap() to map a given GEM handle. ``DRM_ASAHI_GEM_BIND_OBJECT`` Bind memory as a special object ``DRM_ASAHI_QUEUE_CREATE`` Create a scheduling queue. ``DRM_ASAHI_QUEUE_DESTROY`` Destroy a scheduling queue. ``DRM_ASAHI_SUBMIT`` Submit commands to a queue.h](h)}(h **Constants**h]h)}(hj\h]h Constants}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK9hjVubh)}(hhh](h)}(h2``DRM_ASAHI_GET_PARAMS`` Query device properties. h](j)}(h``DRM_ASAHI_GET_PARAMS``h]j)}(hj{h]hDRM_ASAHI_GET_PARAMS}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK``DRM_ASAHI_GEM_BIND_OBJECT`` Bind memory as a special object h](j)}(h``DRM_ASAHI_GEM_BIND_OBJECT``h]j)}(hj !h]hDRM_ASAHI_GEM_BIND_OBJECT}(hj !hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj !ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKRhj!ubj)}(hhh]h)}(hBind memory as a special objecth]hBind memory as a special object}(hj$!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj !hKRhj!!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhj !hKRhjrubh)}(h6``DRM_ASAHI_QUEUE_CREATE`` Create a scheduling queue. h](j)}(h``DRM_ASAHI_QUEUE_CREATE``h]j)}(hjD!h]hDRM_ASAHI_QUEUE_CREATE}(hjF!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKUhj>!ubj)}(hhh]h)}(hCreate a scheduling queue.h]hCreate a scheduling queue.}(hj]!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjY!hKUhjZ!ubah}(h]h ]h"]h$]h&]uh1jhj>!ubeh}(h]h ]h"]h$]h&]uh1hhjY!hKUhjrubh)}(h8``DRM_ASAHI_QUEUE_DESTROY`` Destroy a scheduling queue. h](j)}(h``DRM_ASAHI_QUEUE_DESTROY``h]j)}(hj}!h]hDRM_ASAHI_QUEUE_DESTROY}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKXhjw!ubj)}(hhh]h)}(hDestroy a scheduling queue.h]hDestroy a scheduling queue.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hKXhj!ubah}(h]h ]h"]h$]h&]uh1jhjw!ubeh}(h]h ]h"]h$]h&]uh1hhj!hKXhjrubh)}(h0``DRM_ASAHI_SUBMIT`` Submit commands to a queue.h](j)}(h``DRM_ASAHI_SUBMIT``h]j)}(hj!h]hDRM_ASAHI_SUBMIT}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKZhj!ubj)}(hhh]h)}(hSubmit commands to a queue.h]hSubmit commands to a queue.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK[hj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1hhj!hKZhjrubeh}(h]h ]h"]h$]h&]uh1hhjVubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hj!h]h Description}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK]hjohhubh)}(hMPlace new ioctls at the end, don't re-order, don't replace or remove entries.h]hQPlace new ioctls at the end, don’t re-order, don’t replace or remove entries.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK6hjohhubh)}(h]These IDs are not meant to be used directly. Use the DRM_IOCTL_ASAHI_xxx definitions instead.h]h]These IDs are not meant to be used directly. Use the DRM_IOCTL_ASAHI_xxx definitions instead.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK8hjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_asahi_params_global (C struct)c.drm_asahi_params_globalhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_params_globalh]j)}(hstruct drm_asahi_params_globalh](j)}(hjh]hstruct}(hjF"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjB"hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK>ubj)}(h h]h }(hjT"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjB"hhhjS"hK>ubj)}(hdrm_asahi_params_globalh]j)}(hj@"h]hdrm_asahi_params_global}(hjf"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjb"ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjB"hhhjS"hK>ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj>"hhhjS"hK>ubah}(h]j9"ah ](j j eh"]h$]h&]jj)jhuh1jhjS"hK>hj;"hhubj)}(hhh]h)}(hGlobal parameters.h]hGlobal parameters.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKehj"hhubah}(h]h ]h"]h$]h&]uh1jhj;"hhhjS"hK>ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j"j8j"j9j:j;uh1jhhhjohNhNubj=)}(hX **Definition**:: struct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; }; **Members** ``features`` Feature bits from drm_asahi_feature ``gpu_generation`` GPU generation, e.g. 13 for G13G ``gpu_variant`` GPU variant as a character, e.g. 'C' for G13C ``gpu_revision`` GPU revision in BCD, e.g. 0x00 for 'A0' or 0x21 for 'C1' ``chip_id`` Chip ID in BCD, e.g. 0x8103 for T8103 ``num_dies`` Number of dies in the SoC ``num_clusters_total`` Number of GPU clusters (across all dies) ``num_cores_per_cluster`` Number of logical cores per cluster (including inactive/nonexistent) ``max_frequency_khz`` Maximum GPU core clock frequency ``core_masks`` Bitmask of present/enabled cores per cluster ``vm_start`` VM range start VMA. Together with **vm_end**, this defines the window of valid GPU VAs. Userspace is expected to subdivide VAs out of this window. This window contains all virtual addresses that userspace needs to know about. There may be kernel-internal GPU VAs outside this range, but that detail is not relevant here. ``vm_end`` VM range end VMA ``vm_kernel_min_size`` Minimum kernel VMA window size. When creating a VM, userspace is required to carve out a section of virtual addresses (within the range given by **vm_start** and **vm_end**). The kernel will allocate various internal structures within the specified VA range. Allowing userspace to choose the VA range for the kernel, rather than the kernel reserving VAs and requiring userspace to cope, can assist in implementing SVM. ``max_commands_per_submission`` Maximum number of supported commands per submission. This mirrors firmware limits. Userspace must split up larger command buffers, which may require inserting additional synchronization. ``max_attachments`` Maximum number of drm_asahi_attachment's per command ``command_timestamp_frequency_hz`` Timebase frequency for timestamps written during command execution, specified via drm_asahi_timestamp structures. As this rate is controlled by the firmware, it is a queryable parameter. Userspace must divide by this frequency to convert timestamps to seconds, rather than hardcoding a particular firmware's rate.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubh:}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKihj"ubj`)}(hXstruct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; };h]hXstruct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; };}hj"sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKkhj"ubh)}(h **Members**h]h)}(hj"h]hMembers}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK~hj"ubh)}(hhh](h)}(h1``features`` Feature bits from drm_asahi_feature h](j)}(h ``features``h]j)}(hj"h]hfeatures}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKjhj"ubj)}(hhh]h)}(h#Feature bits from drm_asahi_featureh]h#Feature bits from drm_asahi_feature}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj #hKjhj #ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1hhj #hKjhj"ubh)}(h4``gpu_generation`` GPU generation, e.g. 13 for G13G h](j)}(h``gpu_generation``h]j)}(hj.#h]hgpu_generation}(hj0#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,#ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj(#ubj)}(hhh]h)}(h GPU generation, e.g. 13 for G13Gh]h GPU generation, e.g. 13 for G13G}(hjG#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC#hKhjD#ubah}(h]h ]h"]h$]h&]uh1jhj(#ubeh}(h]h ]h"]h$]h&]uh1hhjC#hKhj"ubh)}(h>``gpu_variant`` GPU variant as a character, e.g. 'C' for G13C h](j)}(h``gpu_variant``h]j)}(hjg#h]h gpu_variant}(hji#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje#ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhja#ubj)}(hhh]h)}(h-GPU variant as a character, e.g. 'C' for G13Ch]h1GPU variant as a character, e.g. ‘C’ for G13C}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|#hKhj}#ubah}(h]h ]h"]h$]h&]uh1jhja#ubeh}(h]h ]h"]h$]h&]uh1hhj|#hKhj"ubh)}(hJ``gpu_revision`` GPU revision in BCD, e.g. 0x00 for 'A0' or 0x21 for 'C1' h](j)}(h``gpu_revision``h]j)}(hj#h]h gpu_revision}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKvhj#ubj)}(hhh]h)}(h8GPU revision in BCD, e.g. 0x00 for 'A0' or 0x21 for 'C1'h]h@GPU revision in BCD, e.g. 0x00 for ‘A0’ or 0x21 for ‘C1’}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKuhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1hhj#hKvhj"ubh)}(h2``chip_id`` Chip ID in BCD, e.g. 0x8103 for T8103 h](j)}(h ``chip_id``h]j)}(hj#h]hchip_id}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj#ubj)}(hhh]h)}(h%Chip ID in BCD, e.g. 0x8103 for T8103h]h%Chip ID in BCD, e.g. 0x8103 for T8103}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hKhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1hhj#hKhj"ubh)}(h'``num_dies`` Number of dies in the SoC h](j)}(h ``num_dies``h]j)}(hj$h]hnum_dies}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj $ubj)}(hhh]h)}(hNumber of dies in the SoCh]hNumber of dies in the SoC}(hj,$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj($hKhj)$ubah}(h]h ]h"]h$]h&]uh1jhj $ubeh}(h]h ]h"]h$]h&]uh1hhj($hKhj"ubh)}(h@``num_clusters_total`` Number of GPU clusters (across all dies) h](j)}(h``num_clusters_total``h]j)}(hjL$h]hnum_clusters_total}(hjN$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJ$ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjF$ubj)}(hhh]h)}(h(Number of GPU clusters (across all dies)h]h(Number of GPU clusters (across all dies)}(hje$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhja$hKhjb$ubah}(h]h ]h"]h$]h&]uh1jhjF$ubeh}(h]h ]h"]h$]h&]uh1hhja$hKhj"ubh)}(h_``num_cores_per_cluster`` Number of logical cores per cluster (including inactive/nonexistent) h](j)}(h``num_cores_per_cluster``h]j)}(hj$h]hnum_cores_per_cluster}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj$ubj)}(hhh]h)}(hDNumber of logical cores per cluster (including inactive/nonexistent)h]hDNumber of logical cores per cluster (including inactive/nonexistent)}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1hhj$hKhj"ubh)}(h7``max_frequency_khz`` Maximum GPU core clock frequency h](j)}(h``max_frequency_khz``h]j)}(hj$h]hmax_frequency_khz}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj$ubj)}(hhh]h)}(h Maximum GPU core clock frequencyh]h Maximum GPU core clock frequency}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hKhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1hhj$hKhj"ubh)}(h<``core_masks`` Bitmask of present/enabled cores per cluster h](j)}(h``core_masks``h]j)}(hj$h]h core_masks}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj$ubj)}(hhh]h)}(h,Bitmask of present/enabled cores per clusterh]h,Bitmask of present/enabled cores per cluster}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj %hKhj%ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1hhj %hKhj"ubh)}(hXO``vm_start`` VM range start VMA. Together with **vm_end**, this defines the window of valid GPU VAs. Userspace is expected to subdivide VAs out of this window. This window contains all virtual addresses that userspace needs to know about. There may be kernel-internal GPU VAs outside this range, but that detail is not relevant here. h](j)}(h ``vm_start``h]j)}(hj1%h]hvm_start}(hj3%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/%ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj+%ubj)}(hhh](h)}(hVM range start VMA. Together with **vm_end**, this defines the window of valid GPU VAs. Userspace is expected to subdivide VAs out of this window.h](h"VM range start VMA. Together with }(hjJ%hhhNhNubh)}(h **vm_end**h]hvm_end}(hjR%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ%ubhf, this defines the window of valid GPU VAs. Userspace is expected to subdivide VAs out of this window.}(hjJ%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjG%ubh)}(hThis window contains all virtual addresses that userspace needs to know about. There may be kernel-internal GPU VAs outside this range, but that detail is not relevant here.h]hThis window contains all virtual addresses that userspace needs to know about. There may be kernel-internal GPU VAs outside this range, but that detail is not relevant here.}(hjk%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjG%ubeh}(h]h ]h"]h$]h&]uh1jhj+%ubeh}(h]h ]h"]h$]h&]uh1hhjF%hKhj"ubh)}(h``vm_end`` VM range end VMA h](j)}(h ``vm_end``h]j)}(hj%h]hvm_end}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj%ubj)}(hhh]h)}(hVM range end VMAh]hVM range end VMA}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hKhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1hhj%hKhj"ubh)}(hX``vm_kernel_min_size`` Minimum kernel VMA window size. When creating a VM, userspace is required to carve out a section of virtual addresses (within the range given by **vm_start** and **vm_end**). The kernel will allocate various internal structures within the specified VA range. Allowing userspace to choose the VA range for the kernel, rather than the kernel reserving VAs and requiring userspace to cope, can assist in implementing SVM. h](j)}(h``vm_kernel_min_size``h]j)}(hj%h]hvm_kernel_min_size}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj%ubj)}(hhh](h)}(hMinimum kernel VMA window size.h]hMinimum kernel VMA window size.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj%ubh)}(hWhen creating a VM, userspace is required to carve out a section of virtual addresses (within the range given by **vm_start** and **vm_end**). The kernel will allocate various internal structures within the specified VA range.h](hqWhen creating a VM, userspace is required to carve out a section of virtual addresses (within the range given by }(hj%hhhNhNubh)}(h **vm_start**h]hvm_start}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubh and }(hj%hhhNhNubh)}(h **vm_end**h]hvm_end}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubhV). The kernel will allocate various internal structures within the specified VA range.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj%ubh)}(hAllowing userspace to choose the VA range for the kernel, rather than the kernel reserving VAs and requiring userspace to cope, can assist in implementing SVM.h]hAllowing userspace to choose the VA range for the kernel, rather than the kernel reserving VAs and requiring userspace to cope, can assist in implementing SVM.}(hj &hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj%ubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1hhj%hKhj"ubh)}(h``max_commands_per_submission`` Maximum number of supported commands per submission. This mirrors firmware limits. Userspace must split up larger command buffers, which may require inserting additional synchronization. h](j)}(h``max_commands_per_submission``h]j)}(hjA&h]hmax_commands_per_submission}(hjC&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj;&ubj)}(hhh]h)}(hMaximum number of supported commands per submission. This mirrors firmware limits. Userspace must split up larger command buffers, which may require inserting additional synchronization.h]hMaximum number of supported commands per submission. This mirrors firmware limits. Userspace must split up larger command buffers, which may require inserting additional synchronization.}(hjZ&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjW&ubah}(h]h ]h"]h$]h&]uh1jhj;&ubeh}(h]h ]h"]h$]h&]uh1hhjV&hKhj"ubh)}(hI``max_attachments`` Maximum number of drm_asahi_attachment's per command h](j)}(h``max_attachments``h]j)}(hj{&h]hmax_attachments}(hj}&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhju&ubj)}(hhh]h)}(h4Maximum number of drm_asahi_attachment's per commandh]h6Maximum number of drm_asahi_attachment’s per command}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj&ubah}(h]h ]h"]h$]h&]uh1jhju&ubeh}(h]h ]h"]h$]h&]uh1hhj&hKhj"ubh)}(hX]``command_timestamp_frequency_hz`` Timebase frequency for timestamps written during command execution, specified via drm_asahi_timestamp structures. As this rate is controlled by the firmware, it is a queryable parameter. Userspace must divide by this frequency to convert timestamps to seconds, rather than hardcoding a particular firmware's rate.h](j)}(h"``command_timestamp_frequency_hz``h]j)}(hj&h]hcommand_timestamp_frequency_hz}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj&ubj)}(hhh](h)}(hTimebase frequency for timestamps written during command execution, specified via drm_asahi_timestamp structures. As this rate is controlled by the firmware, it is a queryable parameter.h]hTimebase frequency for timestamps written during command execution, specified via drm_asahi_timestamp structures. As this rate is controlled by the firmware, it is a queryable parameter.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj&ubh)}(h~Userspace must divide by this frequency to convert timestamps to seconds, rather than hardcoding a particular firmware's rate.h]hUserspace must divide by this frequency to convert timestamps to seconds, rather than hardcoding a particular firmware’s rate.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKhj&ubeh}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1hhj&hKhj"ubeh}(h]h ]h"]h$]h&]uh1hhj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hj'h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjohhubh)}(h3This struct may be queried by drm_asahi_get_params.h]h3This struct may be queried by drm_asahi_get_params.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKfhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_feature (C enum)c.drm_asahi_featurehNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_featureh]j)}(henum drm_asahi_featureh](j)}(hj?h]henum}(hjD'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@'hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKkubj)}(h h]h }(hjR'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@'hhhjQ'hKkubj)}(hdrm_asahi_featureh]j)}(hj>'h]hdrm_asahi_feature}(hjd'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`'ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj@'hhhjQ'hKkubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj<'hhhjQ'hKkubah}(h]j7'ah ](j j eh"]h$]h&]jj)jhuh1jhjQ'hKkhj9'hhubj)}(hhh]h)}(h Feature bitsh]h Feature bits}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj'hhubah}(h]h ]h"]h$]h&]uh1jhj9'hhhjQ'hKkubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7j'j8j'j9j:j;uh1jhhhjohNhNubj=)}(hXB**Constants** ``DRM_ASAHI_FEATURE_SOFT_FAULTS`` GPU has "soft fault" enabled. Shader loads of unmapped memory will return zero. Shader stores to unmapped memory will be silently discarded. Note that only shader load/store is affected. Other hardware units are not affected, notably including texture sampling. Soft fault is set when initializing the GPU and cannot be runtime toggled. Therefore, it is exposed as a feature bit and not a userspace-settable flag on the VM. When soft fault is enabled, userspace can speculate memory accesses more aggressively.h](h)}(h **Constants**h]h)}(hj'h]h Constants}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj'ubh)}(hhh]h)}(hX!``DRM_ASAHI_FEATURE_SOFT_FAULTS`` GPU has "soft fault" enabled. Shader loads of unmapped memory will return zero. Shader stores to unmapped memory will be silently discarded. Note that only shader load/store is affected. Other hardware units are not affected, notably including texture sampling. Soft fault is set when initializing the GPU and cannot be runtime toggled. Therefore, it is exposed as a feature bit and not a userspace-settable flag on the VM. When soft fault is enabled, userspace can speculate memory accesses more aggressively.h](j)}(h!``DRM_ASAHI_FEATURE_SOFT_FAULTS``h]j)}(hj'h]hDRM_ASAHI_FEATURE_SOFT_FAULTS}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj'ubj)}(hhh](h)}(hXGPU has "soft fault" enabled. Shader loads of unmapped memory will return zero. Shader stores to unmapped memory will be silently discarded. Note that only shader load/store is affected. Other hardware units are not affected, notably including texture sampling.h]hX GPU has “soft fault” enabled. Shader loads of unmapped memory will return zero. Shader stores to unmapped memory will be silently discarded. Note that only shader load/store is affected. Other hardware units are not affected, notably including texture sampling.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj'ubh)}(hSoft fault is set when initializing the GPU and cannot be runtime toggled. Therefore, it is exposed as a feature bit and not a userspace-settable flag on the VM. When soft fault is enabled, userspace can speculate memory accesses more aggressively.h]hSoft fault is set when initializing the GPU and cannot be runtime toggled. Therefore, it is exposed as a feature bit and not a userspace-settable flag on the VM. When soft fault is enabled, userspace can speculate memory accesses more aggressively.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj'ubeh}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1hhj'hKhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hj(h]h Description}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjohhubh)}(hyThis covers only features that userspace cannot infer from the architecture version. Most features don't need to be here.h]h{This covers only features that userspace cannot infer from the architecture version. Most features don’t need to be here.}(hj/(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_get_params (C struct)c.drm_asahi_get_paramshNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_get_paramsh]j)}(hstruct drm_asahi_get_paramsh](j)}(hjh]hstruct}(hjW(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjS(hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hje(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjS(hhhjd(hKubj)}(hdrm_asahi_get_paramsh]j)}(hjQ(h]hdrm_asahi_get_params}(hjw(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs(ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjS(hhhjd(hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjO(hhhjd(hKubah}(h]jJ(ah ](j j eh"]h$]h&]jj)jhuh1jhjd(hKhjL(hhubj)}(hhh]h)}(h.Arguments passed to DRM_IOCTL_ASAHI_GET_PARAMSh]h.Arguments passed to DRM_IOCTL_ASAHI_GET_PARAMS}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj(hhubah}(h]h ]h"]h$]h&]uh1jhjL(hhhjd(hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j(j8j(j9j:j;uh1jhhhjohNhNubj=)}(hX**Definition**:: struct drm_asahi_get_params { __u32 param_group; __u32 pad; __u64 pointer; __u64 size; }; **Members** ``param_group`` Parameter group to fetch (MBZ) ``pad`` MBZ ``pointer`` User pointer to write parameter struct ``size`` Size of the user buffer. In case of older userspace, this may be less than sizeof(struct drm_asahi_params_global). The kernel will not write past the length specified here, allowing extensibility.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh:}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj(ubj`)}(histruct drm_asahi_get_params { __u32 param_group; __u32 pad; __u64 pointer; __u64 size; };h]histruct drm_asahi_get_params { __u32 param_group; __u32 pad; __u64 pointer; __u64 size; };}hj(sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj(ubh)}(h **Members**h]h)}(hj(h]hMembers}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj(ubh)}(hhh](h)}(h/``param_group`` Parameter group to fetch (MBZ) h](j)}(h``param_group``h]j)}(hj)h]h param_group}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj)ubj)}(hhh]h)}(hParameter group to fetch (MBZ)h]hParameter group to fetch (MBZ)}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1hhj)hKhj(ubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj?)h]hpad}(hjA)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=)ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj9)ubj)}(hhh]h)}(hMBZh]hMBZ}(hjX)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT)hKhjU)ubah}(h]h ]h"]h$]h&]uh1jhj9)ubeh}(h]h ]h"]h$]h&]uh1hhjT)hKhj(ubh)}(h3``pointer`` User pointer to write parameter struct h](j)}(h ``pointer``h]j)}(hjx)h]hpointer}(hjz)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjv)ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjr)ubj)}(hhh]h)}(h&User pointer to write parameter structh]h&User pointer to write parameter struct}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKhj)ubah}(h]h ]h"]h$]h&]uh1jhjr)ubeh}(h]h ]h"]h$]h&]uh1hhj)hKhj(ubh)}(h``size`` Size of the user buffer. In case of older userspace, this may be less than sizeof(struct drm_asahi_params_global). The kernel will not write past the length specified here, allowing extensibility.h](j)}(h``size``h]j)}(hj)h]hsize}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj)ubj)}(hhh]h)}(hSize of the user buffer. In case of older userspace, this may be less than sizeof(struct drm_asahi_params_global). The kernel will not write past the length specified here, allowing extensibility.h]hSize of the user buffer. In case of older userspace, this may be less than sizeof(struct drm_asahi_params_global). The kernel will not write past the length specified here, allowing extensibility.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1hhj)hKhj(ubeh}(h]h ]h"]h$]h&]uh1hhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_vm_create (C struct)c.drm_asahi_vm_createhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_vm_createh]j)}(hstruct drm_asahi_vm_createh](j)}(hjh]hstruct}(hj *hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*hhhj*hKubj)}(hdrm_asahi_vm_createh]j)}(hj*h]hdrm_asahi_vm_create}(hj+*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'*ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj*hhhj*hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj*hhhj*hKubah}(h]j)ah ](j j eh"]h$]h&]jj)jhuh1jhj*hKhj*hhubj)}(hhh]h)}(h-Arguments passed to DRM_IOCTL_ASAHI_VM_CREATEh]h-Arguments passed to DRM_IOCTL_ASAHI_VM_CREATE}(hjM*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjJ*hhubah}(h]h ]h"]h$]h&]uh1jhj*hhhj*hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7je*j8je*j9j:j;uh1jhhhjohNhNubj=)}(hX**Definition**:: struct drm_asahi_vm_create { __u64 kernel_start; __u64 kernel_end; __u32 vm_id; __u32 pad; }; **Members** ``kernel_start`` Start of the kernel-reserved address range. See drm_asahi_params_global::vm_kernel_min_size. Both **kernel_start** and **kernel_end** must be within the range of valid VAs given by drm_asahi_params_global::vm_start and drm_asahi_params_global::vm_end. The size of the kernel range (**kernel_end** - **kernel_start**) must be at least drm_asahi_params_global::vm_kernel_min_size. Userspace must not bind any memory on this VM into this reserved range, it is for kernel use only. ``kernel_end`` End of the kernel-reserved address range. See **kernel_start**. ``vm_id`` Returned VM ID ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjq*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjm*ubh:}(hjm*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhji*ubj`)}(hmstruct drm_asahi_vm_create { __u64 kernel_start; __u64 kernel_end; __u32 vm_id; __u32 pad; };h]hmstruct drm_asahi_vm_create { __u64 kernel_start; __u64 kernel_end; __u32 vm_id; __u32 pad; };}hj*sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhji*ubh)}(h **Members**h]h)}(hj*h]hMembers}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhji*ubh)}(hhh](h)}(hX``kernel_start`` Start of the kernel-reserved address range. See drm_asahi_params_global::vm_kernel_min_size. Both **kernel_start** and **kernel_end** must be within the range of valid VAs given by drm_asahi_params_global::vm_start and drm_asahi_params_global::vm_end. The size of the kernel range (**kernel_end** - **kernel_start**) must be at least drm_asahi_params_global::vm_kernel_min_size. Userspace must not bind any memory on this VM into this reserved range, it is for kernel use only. h](j)}(h``kernel_start``h]j)}(hj*h]h kernel_start}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj*ubj)}(hhh](h)}(h\Start of the kernel-reserved address range. See drm_asahi_params_global::vm_kernel_min_size.h]h\Start of the kernel-reserved address range. See drm_asahi_params_global::vm_kernel_min_size.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj*ubh)}(hXBoth **kernel_start** and **kernel_end** must be within the range of valid VAs given by drm_asahi_params_global::vm_start and drm_asahi_params_global::vm_end. The size of the kernel range (**kernel_end** - **kernel_start**) must be at least drm_asahi_params_global::vm_kernel_min_size.h](hBoth }(hj*hhhNhNubh)}(h**kernel_start**h]h kernel_start}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*ubh and }(hj*hhhNhNubh)}(h**kernel_end**h]h kernel_end}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*ubh must be within the range of valid VAs given by drm_asahi_params_global::vm_start and drm_asahi_params_global::vm_end. The size of the kernel range (}(hj*hhhNhNubh)}(h**kernel_end**h]h kernel_end}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*ubh - }(hj*hhhNhNubh)}(h**kernel_start**h]h kernel_start}(hj +hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*ubh?) must be at least drm_asahi_params_global::vm_kernel_min_size.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj*ubh)}(hbUserspace must not bind any memory on this VM into this reserved range, it is for kernel use only.h]hbUserspace must not bind any memory on this VM into this reserved range, it is for kernel use only.}(hj9+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj*ubeh}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1hhj*hKhj*ubh)}(hO``kernel_end`` End of the kernel-reserved address range. See **kernel_start**. h](j)}(h``kernel_end``h]j)}(hjZ+h]h kernel_end}(hj\+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX+ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjT+ubj)}(hhh]h)}(h?End of the kernel-reserved address range. See **kernel_start**.h](h.End of the kernel-reserved address range. See }(hjs+hhhNhNubh)}(h**kernel_start**h]h kernel_start}(hj{+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs+ubh.}(hjs+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjp+ubah}(h]h ]h"]h$]h&]uh1jhjT+ubeh}(h]h ]h"]h$]h&]uh1hhjo+hMhj*ubh)}(h``vm_id`` Returned VM ID h](j)}(h ``vm_id``h]j)}(hj+h]hvm_id}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj+ubj)}(hhh]h)}(hReturned VM IDh]hReturned VM ID}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hKhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1hhj+hKhj*ubh)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hj+h]hpad}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj+ubj)}(hhh]h)}(hMBZh]hMBZ}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1hhj+hKhj*ubeh}(h]h ]h"]h$]h&]uh1hhji*ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_vm_destroy (C struct)c.drm_asahi_vm_destroyhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_vm_destroyh]j)}(hstruct drm_asahi_vm_destroyh](j)}(hjh]hstruct}(hj9,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5,hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hjG,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5,hhhjF,hKubj)}(hdrm_asahi_vm_destroyh]j)}(hj3,h]hdrm_asahi_vm_destroy}(hjY,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU,ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj5,hhhjF,hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj1,hhhjF,hKubah}(h]j,,ah ](j j eh"]h$]h&]jj)jhuh1jhjF,hKhj.,hhubj)}(hhh]h)}(h.Arguments passed to DRM_IOCTL_ASAHI_VM_DESTROYh]h.Arguments passed to DRM_IOCTL_ASAHI_VM_DESTROY}(hj{,hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjx,hhubah}(h]h ]h"]h$]h&]uh1jhj.,hhhjF,hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j,j8j,j9j:j;uh1jhhhjohNhNubj=)}(h**Definition**:: struct drm_asahi_vm_destroy { __u32 vm_id; __u32 pad; }; **Members** ``vm_id`` VM ID to be destroyed ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,ubh:}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj,ubj`)}(h@struct drm_asahi_vm_destroy { __u32 vm_id; __u32 pad; };h]h@struct drm_asahi_vm_destroy { __u32 vm_id; __u32 pad; };}hj,sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj,ubh)}(h **Members**h]h)}(hj,h]hMembers}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj,ubh)}(hhh](h)}(h ``vm_id`` VM ID to be destroyed h](j)}(h ``vm_id``h]j)}(hj,h]hvm_id}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj,ubj)}(hhh]h)}(hVM ID to be destroyedh]hVM ID to be destroyed}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMhj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1hhj,hMhj,ubh)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hj!-h]hpad}(hj#-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj-ubj)}(hhh]h)}(hMBZh]hMBZ}(hj:-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj7-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1hhj6-hKhj,ubeh}(h]h ]h"]h$]h&]uh1hhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_gem_flags (C enum)c.drm_asahi_gem_flagshNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_gem_flagsh]j)}(henum drm_asahi_gem_flagsh](j)}(hj?h]henum}(hj{-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw-hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw-hhhj-hKubj)}(hdrm_asahi_gem_flagsh]j)}(hju-h]hdrm_asahi_gem_flags}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjw-hhhj-hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjs-hhhj-hKubah}(h]jn-ah ](j j eh"]h$]h&]jj)jhuh1jhj-hKhjp-hhubj)}(hhh]h)}(hFlags for GEM creationh]hFlags for GEM creation}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj-hhubah}(h]h ]h"]h$]h&]uh1jhjp-hhhj-hKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7j-j8j-j9j:j;uh1jhhhjohNhNubj=)}(h**Constants** ``DRM_ASAHI_GEM_WRITEBACK`` BO should be CPU-mapped as writeback. Map as writeback instead of write-combine. This optimizes for CPU reads. ``DRM_ASAHI_GEM_VM_PRIVATE`` BO is private to this GPU VM (no exports).h](h)}(h **Constants**h]h)}(hj-h]h Constants}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj-ubh)}(hhh](h)}(h``DRM_ASAHI_GEM_WRITEBACK`` BO should be CPU-mapped as writeback. Map as writeback instead of write-combine. This optimizes for CPU reads. h](j)}(h``DRM_ASAHI_GEM_WRITEBACK``h]j)}(hj-h]hDRM_ASAHI_GEM_WRITEBACK}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM%hj-ubj)}(hhh](h)}(h%BO should be CPU-mapped as writeback.h]h%BO should be CPU-mapped as writeback.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM"hj.ubh)}(hHMap as writeback instead of write-combine. This optimizes for CPU reads.h]hHMap as writeback instead of write-combine. This optimizes for CPU reads.}(hj&.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM$hj.ubeh}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1hhj.hM%hj-ubh)}(hG``DRM_ASAHI_GEM_VM_PRIVATE`` BO is private to this GPU VM (no exports).h](j)}(h``DRM_ASAHI_GEM_VM_PRIVATE``h]j)}(hjG.h]hDRM_ASAHI_GEM_VM_PRIVATE}(hjI.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE.ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM'hjA.ubj)}(hhh]h)}(h*BO is private to this GPU VM (no exports).h]h*BO is private to this GPU VM (no exports).}(hj`.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM(hj].ubah}(h]h ]h"]h$]h&]uh1jhjA.ubeh}(h]h ]h"]h$]h&]uh1hhj\.hM'hj-ubeh}(h]h ]h"]h$]h&]uh1hhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_gem_create (C struct)c.drm_asahi_gem_createhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_gem_createh]j)}(hstruct drm_asahi_gem_createh](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM-ubj)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hhhj.hM-ubj)}(hdrm_asahi_gem_createh]j)}(hj.h]hdrm_asahi_gem_create}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj.hhhj.hM-ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj.hhhj.hM-ubah}(h]j.ah ](j j eh"]h$]h&]jj)jhuh1jhj.hM-hj.hhubj)}(hhh]h)}(h.Arguments passed to DRM_IOCTL_ASAHI_GEM_CREATEh]h.Arguments passed to DRM_IOCTL_ASAHI_GEM_CREATE}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM-hj.hhubah}(h]h ]h"]h$]h&]uh1jhj.hhhj.hM-ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j.j8j.j9j:j;uh1jhhhjohNhNubj=)}(hXy**Definition**:: struct drm_asahi_gem_create { __u64 size; __u32 flags; __u32 vm_id; __u32 handle; __u32 pad; }; **Members** ``size`` Size of the BO ``flags`` Combination of drm_asahi_gem_flags flags. ``vm_id`` VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is set ``handle`` Returned GEM handle for the BO ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/ubh:}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM1hj.ubj`)}(hsstruct drm_asahi_gem_create { __u64 size; __u32 flags; __u32 vm_id; __u32 handle; __u32 pad; };h]hsstruct drm_asahi_gem_create { __u64 size; __u32 flags; __u32 vm_id; __u32 handle; __u32 pad; };}hj /sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM3hj.ubh)}(h **Members**h]h)}(hj1/h]hMembers}(hj3/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj//ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM;hj.ubh)}(hhh](h)}(h``size`` Size of the BO h](j)}(h``size``h]j)}(hjP/h]hsize}(hjR/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN/ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM0hjJ/ubj)}(hhh]h)}(hSize of the BOh]hSize of the BO}(hji/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhje/hM0hjf/ubah}(h]h ]h"]h$]h&]uh1jhjJ/ubeh}(h]h ]h"]h$]h&]uh1hhje/hM0hjG/ubh)}(h4``flags`` Combination of drm_asahi_gem_flags flags. h](j)}(h ``flags``h]j)}(hj/h]hflags}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj/ubj)}(hhh]h)}(h)Combination of drm_asahi_gem_flags flags.h]h)Combination of drm_asahi_gem_flags flags.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hKhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1hhj/hKhjG/ubh)}(hH``vm_id`` VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is set h](j)}(h ``vm_id``h]j)}(hj/h]hvm_id}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM8hj/ubj)}(hhh]h)}(h=VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is seth]h=VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is set}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hM8hj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1hhj/hM8hjG/ubh)}(h*``handle`` Returned GEM handle for the BO h](j)}(h ``handle``h]j)}(hj/h]hhandle}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj/ubj)}(hhh]h)}(hReturned GEM handle for the BOh]hReturned GEM handle for the BO}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hKhj0ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1hhj0hKhjG/ubh)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hj40h]hpad}(hj60hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj20ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj.0ubj)}(hhh]h)}(hMBZh]hMBZ}(hjM0hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjJ0ubah}(h]h ]h"]h$]h&]uh1jhj.0ubeh}(h]h ]h"]h$]h&]uh1hhjI0hKhjG/ubeh}(h]h ]h"]h$]h&]uh1hhj.ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_asahi_gem_mmap_offset (C struct)c.drm_asahi_gem_mmap_offsethNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_gem_mmap_offseth]j)}(h struct drm_asahi_gem_mmap_offseth](j)}(hjh]hstruct}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0hhhj0hKubj)}(hdrm_asahi_gem_mmap_offseth]j)}(hj0h]hdrm_asahi_gem_mmap_offset}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj0hhhj0hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj0hhhj0hKubah}(h]j0ah ](j j eh"]h$]h&]jj)jhuh1jhj0hKhj0hhubj)}(hhh]h)}(h3Arguments passed to DRM_IOCTL_ASAHI_GEM_MMAP_OFFSETh]h3Arguments passed to DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMChj0hhubah}(h]h ]h"]h$]h&]uh1jhj0hhhj0hKubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j0j8j0j9j:j;uh1jhhhjohNhNubj=)}(hX **Definition**:: struct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; }; **Members** ``handle`` Handle for the object being mapped. ``flags`` Must be zero ``offset`` The fake offset to use for subsequent mmap callh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubh:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMGhj0ubj`)}(hZstruct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; };h]hZstruct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; };}hj 1sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMIhj0ubh)}(h **Members**h]h)}(hj1h]hMembers}(hj 1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMOhj0ubh)}(hhh](h)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]j)}(hj=1h]hhandle}(hj?1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;1ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMGhj71ubj)}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hjV1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR1hMGhjS1ubah}(h]h ]h"]h$]h&]uh1jhj71ubeh}(h]h ]h"]h$]h&]uh1hhjR1hMGhj41ubh)}(h``flags`` Must be zero h](j)}(h ``flags``h]j)}(hjv1h]hflags}(hjx1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt1ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjp1ubj)}(hhh]h)}(h Must be zeroh]h Must be zero}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hKhj1ubah}(h]h ]h"]h$]h&]uh1jhjp1ubeh}(h]h ]h"]h$]h&]uh1hhj1hKhj41ubh)}(h:``offset`` The fake offset to use for subsequent mmap callh](j)}(h ``offset``h]j)}(hj1h]hoffset}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj1ubj)}(hhh]h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1hhj1hKhj41ubeh}(h]h ]h"]h$]h&]uh1hhj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_bind_flags (C enum)c.drm_asahi_bind_flagshNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_bind_flagsh]j)}(henum drm_asahi_bind_flagsh](j)}(hj?h]henum}(hj 2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhj2hKubj)}(hdrm_asahi_bind_flagsh]j)}(hj2h]hdrm_asahi_bind_flags}(hj)2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%2ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj2hhhj2hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj2hhhj2hKubah}(h]j1ah ](j j eh"]h$]h&]jj)jhuh1jhj2hKhj1hhubj)}(hhh]h)}(hFlags for GEM bindingh]hFlags for GEM binding}(hjK2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMRhjH2hhubah}(h]h ]h"]h$]h&]uh1jhj1hhhj2hKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jc2j8jc2j9j:j;uh1jhhhjohNhNubj=)}(hX**Constants** ``DRM_ASAHI_BIND_UNBIND`` Instead of binding a GEM object to the range, simply unbind the GPU VMA range. ``DRM_ASAHI_BIND_READ`` Map BO with GPU read permission ``DRM_ASAHI_BIND_WRITE`` Map BO with GPU write permission ``DRM_ASAHI_BIND_SINGLE_PAGE`` Map a single page of the BO repeatedly across the VA range. This is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h](h)}(h **Constants**h]h)}(hjm2h]h Constants}(hjo2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk2ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMVhjg2ubh)}(hhh](h)}(hi``DRM_ASAHI_BIND_UNBIND`` Instead of binding a GEM object to the range, simply unbind the GPU VMA range. h](j)}(h``DRM_ASAHI_BIND_UNBIND``h]j)}(hj2h]hDRM_ASAHI_BIND_UNBIND}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMZhj2ubj)}(hhh]h)}(hNInstead of binding a GEM object to the range, simply unbind the GPU VMA range.h]hNInstead of binding a GEM object to the range, simply unbind the GPU VMA range.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMYhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhj2hMZhj2ubh)}(h8``DRM_ASAHI_BIND_READ`` Map BO with GPU read permission h](j)}(h``DRM_ASAHI_BIND_READ``h]j)}(hj2h]hDRM_ASAHI_BIND_READ}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM]hj2ubj)}(hhh]h)}(hMap BO with GPU read permissionh]hMap BO with GPU read permission}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hM]hj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhj2hM]hj2ubh)}(h:``DRM_ASAHI_BIND_WRITE`` Map BO with GPU write permission h](j)}(h``DRM_ASAHI_BIND_WRITE``h]j)}(hj2h]hDRM_ASAHI_BIND_WRITE}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM`hj2ubj)}(hhh]h)}(h Map BO with GPU write permissionh]h Map BO with GPU write permission}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hM`hj3ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1hhj3hM`hj2ubh)}(h``DRM_ASAHI_BIND_SINGLE_PAGE`` Map a single page of the BO repeatedly across the VA range. This is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h](j)}(h``DRM_ASAHI_BIND_SINGLE_PAGE``h]j)}(hj83h]hDRM_ASAHI_BIND_SINGLE_PAGE}(hj:3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj63ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMfhj23ubj)}(hhh](h)}(h;Map a single page of the BO repeatedly across the VA range.h]h;Map a single page of the BO repeatedly across the VA range.}(hjQ3hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMchjN3ubh)}(hwThis is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h]hwThis is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.}(hj`3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM3hMfhjN3ubeh}(h]h ]h"]h$]h&]uh1jhj23ubeh}(h]h ]h"]h$]h&]uh1hhjM3hMfhj2ubeh}(h]h ]h"]h$]h&]uh1hhjg2ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_asahi_gem_bind_op (C struct)c.drm_asahi_gem_bind_ophNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_gem_bind_oph]j)}(hstruct drm_asahi_gem_bind_oph](j)}(hjh]hstruct}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMlubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3hhhj3hMlubj)}(hdrm_asahi_gem_bind_oph]j)}(hj3h]hdrm_asahi_gem_bind_op}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj3hhhj3hMlubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj3hhhj3hMlubah}(h]j3ah ](j j eh"]h$]h&]jj)jhuh1jhj3hMlhj3hhubj)}(hhh]h)}(h+Description of a single GEM bind operation.h]h+Description of a single GEM bind operation.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMlhj3hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj3hMlubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j3j8j3j9j:j;uh1jhhhjohNhNubj=)}(hX**Definition**:: struct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; }; **Members** ``flags`` Combination of drm_asahi_bind_flags flags. ``handle`` GEM object to bind (except for UNBIND) ``offset`` Offset into the object (except for UNBIND). For a regular bind, this is the beginning of the region of the GEM object to bind. For a single-page bind, this is the offset to the single page that will be repeatedly bound. Must be page-size aligned. ``range`` Number of bytes to bind/unbind to **addr**. Must be page-size aligned. ``addr`` Address to bind to. Must be page-size aligned.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubh:}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMphj3ubj`)}(hwstruct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; };h]hwstruct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; };}hj4sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMrhj3ubh)}(h **Members**h]h)}(hj04h]hMembers}(hj24hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.4ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMzhj3ubh)}(hhh](h)}(h5``flags`` Combination of drm_asahi_bind_flags flags. h](j)}(h ``flags``h]j)}(hjO4h]hflags}(hjQ4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM4ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMohjI4ubj)}(hhh]h)}(h*Combination of drm_asahi_bind_flags flags.h]h*Combination of drm_asahi_bind_flags flags.}(hjh4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjd4hMohje4ubah}(h]h ]h"]h$]h&]uh1jhjI4ubeh}(h]h ]h"]h$]h&]uh1hhjd4hMohjF4ubh)}(h2``handle`` GEM object to bind (except for UNBIND) h](j)}(h ``handle``h]j)}(hj4h]hhandle}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj4ubj)}(hhh]h)}(h&GEM object to bind (except for UNBIND)h]h&GEM object to bind (except for UNBIND)}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hKhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1hhj4hKhjF4ubh)}(hX``offset`` Offset into the object (except for UNBIND). For a regular bind, this is the beginning of the region of the GEM object to bind. For a single-page bind, this is the offset to the single page that will be repeatedly bound. Must be page-size aligned. h](j)}(h ``offset``h]j)}(hj4h]hoffset}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj4ubj)}(hhh](h)}(h+Offset into the object (except for UNBIND).h]h+Offset into the object (except for UNBIND).}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMwhj4ubh)}(hRFor a regular bind, this is the beginning of the region of the GEM object to bind.h]hRFor a regular bind, this is the beginning of the region of the GEM object to bind.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMyhj4ubh)}(h\For a single-page bind, this is the offset to the single page that will be repeatedly bound.h]h\For a single-page bind, this is the offset to the single page that will be repeatedly bound.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM|hj4ubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMhj4ubeh}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1hhj4hMhjF4ubh)}(hR``range`` Number of bytes to bind/unbind to **addr**. Must be page-size aligned. h](j)}(h ``range``h]j)}(hj'5h]hrange}(hj)5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%5ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj!5ubj)}(hhh](h)}(h+Number of bytes to bind/unbind to **addr**.h](h"Number of bytes to bind/unbind to }(hj@5hhhNhNubh)}(h**addr**h]haddr}(hjH5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@5ubh.}(hj@5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj=5ubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hja5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<5hMhj=5ubeh}(h]h ]h"]h$]h&]uh1jhj!5ubeh}(h]h ]h"]h$]h&]uh1hhj<5hMhjF4ubh)}(h8``addr`` Address to bind to. Must be page-size aligned.h](j)}(h``addr``h]j)}(hj5h]haddr}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj{5ubj)}(hhh](h)}(hAddress to bind to.h]hAddress to bind to.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj5ubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj5ubeh}(h]h ]h"]h$]h&]uh1jhj{5ubeh}(h]h ]h"]h$]h&]uh1hhj5hMhjF4ubeh}(h]h ]h"]h$]h&]uh1hhj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_vm_bind (C struct)c.drm_asahi_vm_bindhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_vm_bindh]j)}(hstruct drm_asahi_vm_bindh](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5hhhj5hMubj)}(hdrm_asahi_vm_bindh]j)}(hj5h]hdrm_asahi_vm_bind}(hj 6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj5hhhj5hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj5hhhj5hMubah}(h]j5ah ](j j eh"]h$]h&]jj)jhuh1jhj5hMhj5hhubj)}(hhh]h)}(h+Arguments passed to DRM_IOCTL_ASAHI_VM_BINDh]h+Arguments passed to DRM_IOCTL_ASAHI_VM_BIND}(hj,6hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj)6hhubah}(h]h ]h"]h$]h&]uh1jhj5hhhj5hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jD6j8jD6j9j:j;uh1jhhhjohNhNubj=)}(hX**Definition**:: struct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; }; **Members** ``vm_id`` The ID of the VM to bind to ``num_binds`` number of binds in this IOCTL. ``stride`` Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op. ``pad`` MBZ ``userptr`` User pointer to an array of **num_binds** structures of type **drm_asahi_gem_bind_op** and size **stride** bytes.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjP6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjL6ubh:}(hjL6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjH6ubj`)}(hwstruct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; };h]hwstruct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; };}hji6sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjH6ubh)}(h **Members**h]h)}(hjz6h]hMembers}(hj|6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx6ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjH6ubh)}(hhh](h)}(h&``vm_id`` The ID of the VM to bind to h](j)}(h ``vm_id``h]j)}(hj6h]hvm_id}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj6ubj)}(hhh]h)}(hThe ID of the VM to bind toh]hThe ID of the VM to bind to}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubh)}(h-``num_binds`` number of binds in this IOCTL. h](j)}(h ``num_binds``h]j)}(hj6h]h num_binds}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj6ubj)}(hhh]h)}(hnumber of binds in this IOCTL.h]hnumber of binds in this IOCTL.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hKhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1hhj6hKhj6ubh)}(hj``stride`` Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op. h](j)}(h ``stride``h]j)}(hj 7h]hstride}(hj 7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 7ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj7ubj)}(hhh]h)}(h^Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op.h]h^Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op.}(hj$7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj!7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1hhj 7hMhj6ubh)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjE7h]hpad}(hjG7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC7ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj?7ubj)}(hhh]h)}(hMBZh]hMBZ}(hj^7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ7hKhj[7ubah}(h]h ]h"]h$]h&]uh1jhj?7ubeh}(h]h ]h"]h$]h&]uh1hhjZ7hKhj6ubh)}(h}``userptr`` User pointer to an array of **num_binds** structures of type **drm_asahi_gem_bind_op** and size **stride** bytes.h](j)}(h ``userptr``h]j)}(hj~7h]huserptr}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|7ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjx7ubj)}(hhh]h)}(hqUser pointer to an array of **num_binds** structures of type **drm_asahi_gem_bind_op** and size **stride** bytes.h](hUser pointer to an array of }(hj7hhhNhNubh)}(h **num_binds**h]h num_binds}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubh structures of type }(hj7hhhNhNubh)}(h**drm_asahi_gem_bind_op**h]hdrm_asahi_gem_bind_op}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubh and size }(hj7hhhNhNubh)}(h **stride**h]hstride}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubh bytes.}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj7hMhj7ubah}(h]h ]h"]h$]h&]uh1jhjx7ubeh}(h]h ]h"]h$]h&]uh1hhj7hMhj6ubeh}(h]h ]h"]h$]h&]uh1hhjH6ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_asahi_bind_object_op (C enum)c.drm_asahi_bind_object_ophNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_bind_object_oph]j)}(henum drm_asahi_bind_object_oph](j)}(hj?h]henum}(hj 8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 8hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 8hhhj8hMubj)}(hdrm_asahi_bind_object_oph]j)}(hj8h]hdrm_asahi_bind_object_op}(hj-8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)8ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj 8hhhj8hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj8hhhj8hMubah}(h]j8ah ](j j eh"]h$]h&]jj)jhuh1jhj8hMhj8hhubj)}(hhh]h)}(hSpecial object bind operationh]hSpecial object bind operation}(hjO8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjL8hhubah}(h]h ]h"]h$]h&]uh1jhj8hhhj8hMubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jg8j8jg8j9j:j;uh1jhhhjohNhNubj=)}(h**Constants** ``DRM_ASAHI_BIND_OBJECT_OP_BIND`` Bind a BO as a special GPU object ``DRM_ASAHI_BIND_OBJECT_OP_UNBIND`` Unbind a special GPU objecth](h)}(h **Constants**h]h)}(hjq8h]h Constants}(hjs8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjo8ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjk8ubh)}(hhh](h)}(hD``DRM_ASAHI_BIND_OBJECT_OP_BIND`` Bind a BO as a special GPU object h](j)}(h!``DRM_ASAHI_BIND_OBJECT_OP_BIND``h]j)}(hj8h]hDRM_ASAHI_BIND_OBJECT_OP_BIND}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj8ubj)}(hhh]h)}(h!Bind a BO as a special GPU objecth]h!Bind a BO as a special GPU object}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubh)}(h?``DRM_ASAHI_BIND_OBJECT_OP_UNBIND`` Unbind a special GPU objecth](j)}(h#``DRM_ASAHI_BIND_OBJECT_OP_UNBIND``h]j)}(hj8h]hDRM_ASAHI_BIND_OBJECT_OP_UNBIND}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj8ubj)}(hhh]h)}(hUnbind a special GPU objecth]hUnbind a special GPU object}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubeh}(h]h ]h"]h$]h&]uh1hhjk8ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_asahi_bind_object_flags (C enum)c.drm_asahi_bind_object_flagshNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_bind_object_flagsh]j)}(h enum drm_asahi_bind_object_flagsh](j)}(hj?h]henum}(hj#9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj19hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9hhhj09hMubj)}(hdrm_asahi_bind_object_flagsh]j)}(hj9h]hdrm_asahi_bind_object_flags}(hjC9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?9ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj9hhhj09hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj9hhhj09hMubah}(h]j9ah ](j j eh"]h$]h&]jj)jhuh1jhj09hMhj9hhubj)}(hhh]h)}(hSpecial object bind flagsh]hSpecial object bind flags}(hje9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjb9hhubah}(h]h ]h"]h$]h&]uh1jhj9hhhj09hMubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7j}9j8j}9j9j:j;uh1jhhhjohNhNubj=)}(h]**Constants** ``DRM_ASAHI_BIND_OBJECT_USAGE_TIMESTAMPS`` Map a BO as a timestamp buffer.h](h)}(h **Constants**h]h)}(hj9h]h Constants}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj9ubh)}(hhh]h)}(hJ``DRM_ASAHI_BIND_OBJECT_USAGE_TIMESTAMPS`` Map a BO as a timestamp buffer.h](j)}(h*``DRM_ASAHI_BIND_OBJECT_USAGE_TIMESTAMPS``h]j)}(hj9h]h&DRM_ASAHI_BIND_OBJECT_USAGE_TIMESTAMPS}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj9ubj)}(hhh]h)}(hMap a BO as a timestamp buffer.h]hMap a BO as a timestamp buffer.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1hhj9ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_asahi_gem_bind_object (C struct)c.drm_asahi_gem_bind_objecthNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_gem_bind_objecth]j)}(h struct drm_asahi_gem_bind_objecth](j)}(hjh]hstruct}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj :hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9hhhj :hMubj)}(hdrm_asahi_gem_bind_objecth]j)}(hj9h]hdrm_asahi_gem_bind_object}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj9hhhj :hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj9hhhj :hMubah}(h]j9ah ](j j eh"]h$]h&]jj)jhuh1jhj :hMhj9hhubj)}(hhh]h)}(h3Arguments passed to DRM_IOCTL_ASAHI_GEM_BIND_OBJECTh]h3Arguments passed to DRM_IOCTL_ASAHI_GEM_BIND_OBJECT}(hjA:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj>:hhubah}(h]h ]h"]h$]h&]uh1jhj9hhhj :hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jY:j8jY:j9j:j;uh1jhhhjohNhNubj=)}(hX**Definition**:: struct drm_asahi_gem_bind_object { __u32 op; __u32 flags; __u32 handle; __u32 vm_id; __u64 offset; __u64 range; __u32 object_handle; __u32 pad; }; **Members** ``op`` Bind operation (enum drm_asahi_bind_object_op) ``flags`` Combination of drm_asahi_bind_object_flags flags. ``handle`` GEM object to bind/unbind (BIND) ``vm_id`` The ID of the VM to operate on (MBZ currently) ``offset`` Offset into the object (BIND only) ``range`` Number of bytes to bind/unbind (BIND only) ``object_handle`` Object handle (out for BIND, in for UNBIND) ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hje:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhja:ubh:}(hja:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj]:ubj`)}(hstruct drm_asahi_gem_bind_object { __u32 op; __u32 flags; __u32 handle; __u32 vm_id; __u64 offset; __u64 range; __u32 object_handle; __u32 pad; };h]hstruct drm_asahi_gem_bind_object { __u32 op; __u32 flags; __u32 handle; __u32 vm_id; __u64 offset; __u64 range; __u32 object_handle; __u32 pad; };}hj~:sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj]:ubh)}(h **Members**h]h)}(hj:h]hMembers}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj]:ubh)}(hhh](h)}(h6``op`` Bind operation (enum drm_asahi_bind_object_op) h](j)}(h``op``h]j)}(hj:h]hop}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj:ubj)}(hhh]h)}(h.Bind operation (enum drm_asahi_bind_object_op)h]h.Bind operation (enum drm_asahi_bind_object_op)}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1hhj:hMhj:ubh)}(h<``flags`` Combination of drm_asahi_bind_object_flags flags. h](j)}(h ``flags``h]j)}(hj:h]hflags}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj:ubj)}(hhh]h)}(h1Combination of drm_asahi_bind_object_flags flags.h]h1Combination of drm_asahi_bind_object_flags flags.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1hhj:hKhj:ubh)}(h,``handle`` GEM object to bind/unbind (BIND) h](j)}(h ``handle``h]j)}(hj ;h]hhandle}(hj";hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj;ubj)}(hhh]h)}(h GEM object to bind/unbind (BIND)h]h GEM object to bind/unbind (BIND)}(hj9;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5;hKhj6;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1hhj5;hKhj:ubh)}(h9``vm_id`` The ID of the VM to operate on (MBZ currently) h](j)}(h ``vm_id``h]j)}(hjY;h]hvm_id}(hj[;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjW;ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjS;ubj)}(hhh]h)}(h.The ID of the VM to operate on (MBZ currently)h]h.The ID of the VM to operate on (MBZ currently)}(hjr;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn;hKhjo;ubah}(h]h ]h"]h$]h&]uh1jhjS;ubeh}(h]h ]h"]h$]h&]uh1hhjn;hKhj:ubh)}(h.``offset`` Offset into the object (BIND only) h](j)}(h ``offset``h]j)}(hj;h]hoffset}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj;ubj)}(hhh]h)}(h"Offset into the object (BIND only)h]h"Offset into the object (BIND only)}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hKhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1hhj;hKhj:ubh)}(h5``range`` Number of bytes to bind/unbind (BIND only) h](j)}(h ``range``h]j)}(hj;h]hrange}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj;ubj)}(hhh]h)}(h*Number of bytes to bind/unbind (BIND only)h]h*Number of bytes to bind/unbind (BIND only)}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hKhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1hhj;hKhj:ubh)}(h>``object_handle`` Object handle (out for BIND, in for UNBIND) h](j)}(h``object_handle``h]j)}(hj<h]h object_handle}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj;ubj)}(hhh]h)}(h+Object handle (out for BIND, in for UNBIND)h]h+Object handle (out for BIND, in for UNBIND)}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hKhj<ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1hhj<hKhj:ubh)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hj=<h]hpad}(hj?<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;<ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj7<ubj)}(hhh]h)}(hMBZh]hMBZ}(hjV<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjS<ubah}(h]h ]h"]h$]h&]uh1jhj7<ubeh}(h]h ]h"]h$]h&]uh1hhjR<hKhj:ubeh}(h]h ]h"]h$]h&]uh1hhj]:ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_cmd_type (C enum)c.drm_asahi_cmd_typehNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_cmd_typeh]j)}(henum drm_asahi_cmd_typeh](j)}(hj?h]henum}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj<hKubj)}(hdrm_asahi_cmd_typeh]j)}(hj<h]hdrm_asahi_cmd_type}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj<hhhj<hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj<hhhj<hKubah}(h]j<ah ](j j eh"]h$]h&]jj)jhuh1jhj<hKhj<hhubj)}(hhh]h)}(h Command typeh]h Command type}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj<hhubah}(h]h ]h"]h$]h&]uh1jhj<hhhj<hKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7j<j8j<j9j:j;uh1jhhhjohNhNubj=)}(hX**Constants** ``DRM_ASAHI_CMD_RENDER`` Render command, executing on the render subqueue. Combined vertex and fragment operation. Followed by a **drm_asahi_cmd_render** payload. ``DRM_ASAHI_CMD_COMPUTE`` Compute command on the compute subqueue. Followed by a **drm_asahi_cmd_compute** payload. ``DRM_ASAHI_SET_VERTEX_ATTACHMENTS`` Software command to set attachments for subsequent vertex shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. ``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS`` Software command to set attachments for subsequent fragment shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. ``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS`` Software command to set attachments for subsequent compute shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads.h](h)}(h **Constants**h]h)}(hj<h]h Constants}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj<ubh)}(hhh](h)}(h``DRM_ASAHI_CMD_RENDER`` Render command, executing on the render subqueue. Combined vertex and fragment operation. Followed by a **drm_asahi_cmd_render** payload. h](j)}(h``DRM_ASAHI_CMD_RENDER``h]j)}(hj=h]hDRM_ASAHI_CMD_RENDER}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj=ubj)}(hhh](h)}(hYRender command, executing on the render subqueue. Combined vertex and fragment operation.h]hYRender command, executing on the render subqueue. Combined vertex and fragment operation.}(hj3=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj0=ubh)}(h/Followed by a **drm_asahi_cmd_render** payload.h](hFollowed by a }(hjB=hhhNhNubh)}(h**drm_asahi_cmd_render**h]hdrm_asahi_cmd_render}(hjJ=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB=ubh payload.}(hjB=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/=hMhj0=ubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1hhj/=hMhj=ubh)}(hu``DRM_ASAHI_CMD_COMPUTE`` Compute command on the compute subqueue. Followed by a **drm_asahi_cmd_compute** payload. h](j)}(h``DRM_ASAHI_CMD_COMPUTE``h]j)}(hjt=h]hDRM_ASAHI_CMD_COMPUTE}(hjv=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjr=ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjn=ubj)}(hhh](h)}(h(Compute command on the compute subqueue.h]h(Compute command on the compute subqueue.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj=ubh)}(h0Followed by a **drm_asahi_cmd_compute** payload.h](hFollowed by a }(hj=hhhNhNubh)}(h**drm_asahi_cmd_compute**h]hdrm_asahi_cmd_compute}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubh payload.}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj=hMhj=ubeh}(h]h ]h"]h$]h&]uh1jhjn=ubeh}(h]h ]h"]h$]h&]uh1hhj=hMhj=ubh)}(h``DRM_ASAHI_SET_VERTEX_ATTACHMENTS`` Software command to set attachments for subsequent vertex shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. h](j)}(h$``DRM_ASAHI_SET_VERTEX_ATTACHMENTS``h]j)}(hj=h]h DRM_ASAHI_SET_VERTEX_ATTACHMENTS}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj=ubj)}(hhh](h)}(hUSoftware command to set attachments for subsequent vertex shaders in the same submit.h]hUSoftware command to set attachments for subsequent vertex shaders in the same submit.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj=ubh)}(hBFollowed by (possibly multiple) **drm_asahi_attachment** payloads.h](h Followed by (possibly multiple) }(hj=hhhNhNubh)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubh payloads.}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj=hMhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1hhj=hMhj=ubh)}(h``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS`` Software command to set attachments for subsequent fragment shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. h](j)}(h&``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS``h]j)}(hj(>h]h"DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS}(hj*>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&>ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj">ubj)}(hhh](h)}(hWSoftware command to set attachments for subsequent fragment shaders in the same submit.h]hWSoftware command to set attachments for subsequent fragment shaders in the same submit.}(hjA>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj>>ubh)}(hBFollowed by (possibly multiple) **drm_asahi_attachment** payloads.h](h Followed by (possibly multiple) }(hjP>hhhNhNubh)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hjX>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP>ubh payloads.}(hjP>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj=>hMhj>>ubeh}(h]h ]h"]h$]h&]uh1jhj">ubeh}(h]h ]h"]h$]h&]uh1hhj=>hMhj=ubh)}(h``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS`` Software command to set attachments for subsequent compute shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads.h](j)}(h%``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS``h]j)}(hj>h]h!DRM_ASAHI_SET_COMPUTE_ATTACHMENTS}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj|>ubj)}(hhh](h)}(hVSoftware command to set attachments for subsequent compute shaders in the same submit.h]hVSoftware command to set attachments for subsequent compute shaders in the same submit.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj>ubh)}(hBFollowed by (possibly multiple) **drm_asahi_attachment** payloads.h](h Followed by (possibly multiple) }(hj>hhhNhNubh)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>ubh payloads.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj>ubeh}(h]h ]h"]h$]h&]uh1jhj|>ubeh}(h]h ]h"]h$]h&]uh1hhj>hMhj=ubeh}(h]h ]h"]h$]h&]uh1hhj<ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_priority (C enum)c.drm_asahi_priorityhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_priorityh]j)}(henum drm_asahi_priorityh](j)}(hj?h]henum}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj ?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>hhhj ?hMubj)}(hdrm_asahi_priorityh]j)}(hj>h]hdrm_asahi_priority}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj>hhhj ?hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj>hhhj ?hMubah}(h]j>ah ](j j eh"]h$]h&]jj)jhuh1jhj ?hMhj>hhubj)}(hhh]h)}(hScheduling queue priority.h]hScheduling queue priority.}(hj??hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM hjhhhj ?hMubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jW?j8jW?j9j:j;uh1jhhhjohNhNubj=)}(hX,**Constants** ``DRM_ASAHI_PRIORITY_LOW`` Low priority queue. ``DRM_ASAHI_PRIORITY_MEDIUM`` Medium priority queue. ``DRM_ASAHI_PRIORITY_HIGH`` High priority queue. Reserved for future extension. ``DRM_ASAHI_PRIORITY_REALTIME`` Real-time priority queue. Reserved for future extension.h](h)}(h **Constants**h]h)}(hja?h]h Constants}(hjc?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_?ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj[?ubh)}(hhh](h)}(h/``DRM_ASAHI_PRIORITY_LOW`` Low priority queue. h](j)}(h``DRM_ASAHI_PRIORITY_LOW``h]j)}(hj?h]hDRM_ASAHI_PRIORITY_LOW}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~?ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjz?ubj)}(hhh]h)}(hLow priority queue.h]hLow priority queue.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhjz?ubeh}(h]h ]h"]h$]h&]uh1hhj?hMhjw?ubh)}(h5``DRM_ASAHI_PRIORITY_MEDIUM`` Medium priority queue. h](j)}(h``DRM_ASAHI_PRIORITY_MEDIUM``h]j)}(hj?h]hDRM_ASAHI_PRIORITY_MEDIUM}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj?ubj)}(hhh]h)}(hMedium priority queue.h]hMedium priority queue.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1hhj?hMhjw?ubh)}(hQ``DRM_ASAHI_PRIORITY_HIGH`` High priority queue. Reserved for future extension. h](j)}(h``DRM_ASAHI_PRIORITY_HIGH``h]j)}(hj?h]hDRM_ASAHI_PRIORITY_HIGH}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj?ubj)}(hhh](h)}(hHigh priority queue.h]hHigh priority queue.}(hj @hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj@ubh)}(hReserved for future extension.h]hReserved for future extension.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubeh}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1hhj@hMhjw?ubh)}(hY``DRM_ASAHI_PRIORITY_REALTIME`` Real-time priority queue. Reserved for future extension.h](j)}(h``DRM_ASAHI_PRIORITY_REALTIME``h]j)}(hj:@h]hDRM_ASAHI_PRIORITY_REALTIME}(hj<@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8@ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM hj4@ubj)}(hhh](h)}(hReal-time priority queue.h]hReal-time priority queue.}(hjS@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjP@ubh)}(hReserved for future extension.h]hReserved for future extension.}(hjb@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM!hjP@ubeh}(h]h ]h"]h$]h&]uh1jhj4@ubeh}(h]h ]h"]h$]h&]uh1hhjO@hM hjw?ubeh}(h]h ]h"]h$]h&]uh1hhj[?ubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hj@h]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM#hjohhubh)}(hThese priorities are forwarded to the firmware to influence firmware scheduling. The exact policy is ultimately decided by firmware, but these enums allow userspace to communicate the intentions.h]hThese priorities are forwarded to the firmware to influence firmware scheduling. The exact policy is ultimately decided by firmware, but these enums allow userspace to communicate the intentions.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_asahi_queue_create (C struct)c.drm_asahi_queue_createhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_queue_createh]j)}(hstruct drm_asahi_queue_createh](j)}(hjh]hstruct}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@hhhj@hMubj)}(hdrm_asahi_queue_createh]j)}(hj@h]hdrm_asahi_queue_create}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj@hhhj@hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj@hhhj@hMubah}(h]j@ah ](j j eh"]h$]h&]jj)jhuh1jhj@hMhj@hhubj)}(hhh]h)}(h0Arguments passed to DRM_IOCTL_ASAHI_QUEUE_CREATEh]h0Arguments passed to DRM_IOCTL_ASAHI_QUEUE_CREATE}(hj AhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM*hj Ahhubah}(h]h ]h"]h$]h&]uh1jhj@hhhj@hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j$Aj8j$Aj9j:j;uh1jhhhjohNhNubj=)}(hXR**Definition**:: struct drm_asahi_queue_create { __u32 flags; __u32 vm_id; __u32 priority; __u32 queue_id; __u64 usc_exec_base; }; **Members** ``flags`` MBZ ``vm_id`` The ID of the VM this queue is bound to ``priority`` One of drm_asahi_priority ``queue_id`` The returned queue ID ``usc_exec_base`` GPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base. This sets the following registers on all queue commands: USC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) While the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj0AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,Aubh:}(hj,AhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM.hj(Aubj`)}(hstruct drm_asahi_queue_create { __u32 flags; __u32 vm_id; __u32 priority; __u32 queue_id; __u64 usc_exec_base; };h]hstruct drm_asahi_queue_create { __u32 flags; __u32 vm_id; __u32 priority; __u32 queue_id; __u64 usc_exec_base; };}hjIAsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM0hj(Aubh)}(h **Members**h]h)}(hjZAh]hMembers}(hj\AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXAubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM8hj(Aubh)}(hhh](h)}(h``flags`` MBZ h](j)}(h ``flags``h]j)}(hjyAh]hflags}(hj{AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwAubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM.hjsAubj)}(hhh]h)}(hMBZh]hMBZ}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhM.hjAubah}(h]h ]h"]h$]h&]uh1jhjsAubeh}(h]h ]h"]h$]h&]uh1hhjAhM.hjpAubh)}(h2``vm_id`` The ID of the VM this queue is bound to h](j)}(h ``vm_id``h]j)}(hjAh]hvm_id}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjAubj)}(hhh]h)}(h'The ID of the VM this queue is bound toh]h'The ID of the VM this queue is bound to}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhKhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1hhjAhKhjpAubh)}(h'``priority`` One of drm_asahi_priority h](j)}(h ``priority``h]j)}(hjAh]hpriority}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjAubj)}(hhh]h)}(hOne of drm_asahi_priorityh]hOne of drm_asahi_priority}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhKhjBubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1hhjBhKhjpAubh)}(h#``queue_id`` The returned queue ID h](j)}(h ``queue_id``h]j)}(hj$Bh]hqueue_id}(hj&BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"Bubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjBubj)}(hhh]h)}(hThe returned queue IDh]hThe returned queue ID}(hj=BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9BhKhj:Bubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1hhj9BhKhjpAubh)}(hX``usc_exec_base`` GPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base. This sets the following registers on all queue commands: USC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) While the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h](j)}(h``usc_exec_base``h]j)}(hj]Bh]h usc_exec_base}(hj_BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[Bubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMFhjWBubj)}(hhh](h)}(huGPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base.h]huGPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base.}(hjvBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM<hjsBubh)}(h8This sets the following registers on all queue commands:h]h8This sets the following registers on all queue commands:}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM?hjsBubj)}(hTUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) h]h)}(hSUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute)h]hSUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute)}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMAhjBubah}(h]h ]h"]h$]h&]uh1jhjBhMAhjsBubh)}(hWhile the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h]hWhile the hardware lets us configure these independently per command, we do not have a use case for this. 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eh"]h$]h&]jj)jhuh1jhjBhMMhjBhhubj)}(hhh]h)}(h1Arguments passed to DRM_IOCTL_ASAHI_QUEUE_DESTROYh]h1Arguments passed to DRM_IOCTL_ASAHI_QUEUE_DESTROY}(hj0ChhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMLhj-Chhubah}(h]h ]h"]h$]h&]uh1jhjBhhhjBhMMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jHCj8jHCj9j:j;uh1jhhhjohNhNubj=)}(h**Definition**:: struct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; }; **Members** ``queue_id`` The queue ID to be destroyed ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjTChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPCubh:}(hjPChhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMPhjLCubj`)}(hFstruct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; };h]hFstruct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; };}hjmCsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMRhjLCubh)}(h **Members**h]h)}(hj~Ch]hMembers}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|Cubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMWhjLCubh)}(hhh](h)}(h*``queue_id`` The queue ID to be destroyed h](j)}(h ``queue_id``h]j)}(hjCh]hqueue_id}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMPhjCubj)}(hhh]h)}(hThe queue ID to be destroyedh]hThe queue ID to be destroyed}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMPhjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1hhjChMPhjCubh)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hjCh]hpad}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjCubj)}(hhh]h)}(hMBZh]hMBZ}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1hhjChKhjCubeh}(h]h ]h"]h$]h&]uh1hhjLCubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_sync_type (C enum)c.drm_asahi_sync_typehNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_sync_typeh]j)}(henum drm_asahi_sync_typeh](j)}(hj?h]henum}(hj0DhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,Dhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKubj)}(h h]h }(hj>DhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,Dhhhj=DhKubj)}(hdrm_asahi_sync_typeh]j)}(hj*Dh]hdrm_asahi_sync_type}(hjPDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLDubah}(h]h ](jjeh"]h$]h&]jjuh1jhj,Dhhhj=DhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj(Dhhhj=DhKubah}(h]j#Dah ](j j eh"]h$]h&]jj)jhuh1jhj=DhKhj%Dhhubj)}(hhh]h)}(hSync item typeh]hSync item type}(hjrDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMXhjoDhhubah}(h]h ]h"]h$]h&]uh1jhj%Dhhhj=DhKubeh}(h]h ](j1enumeh"]h$]h&]j6j1j7jDj8jDj9j:j;uh1jhhhjohNhNubj=)}(hz**Constants** ``DRM_ASAHI_SYNC_SYNCOBJ`` Binary sync object ``DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ`` Timeline sync objecth](h)}(h **Constants**h]h)}(hjDh]h Constants}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM\hjDubh)}(hhh](h)}(h.``DRM_ASAHI_SYNC_SYNCOBJ`` Binary sync object h](j)}(h``DRM_ASAHI_SYNC_SYNCOBJ``h]j)}(hjDh]hDRM_ASAHI_SYNC_SYNCOBJ}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM_hjDubj)}(hhh]h)}(hBinary sync objecth]hBinary sync object}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhM_hjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1hhjDhM_hjDubh)}(h8``DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ`` Timeline sync objecth](j)}(h#``DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ``h]j)}(hjDh]hDRM_ASAHI_SYNC_TIMELINE_SYNCOBJ}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMahjDubj)}(hhh]h)}(hTimeline sync objecth]hTimeline sync object}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMbhjEubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1hhjEhMahjDubeh}(h]h ]h"]h$]h&]uh1hhjDubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_sync (C struct)c.drm_asahi_synchNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_synch]j)}(hstruct drm_asahi_synch](j)}(hjh]hstruct}(hjFEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBEhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMgubj)}(h h]h }(hjTEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBEhhhjSEhMgubj)}(hdrm_asahi_synch]j)}(hj@Eh]hdrm_asahi_sync}(hjfEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbEubah}(h]h ](jjeh"]h$]h&]jjuh1jhjBEhhhjSEhMgubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj>EhhhjSEhMgubah}(h]j9Eah ](j j eh"]h$]h&]jj)jhuh1jhjSEhMghj;Ehhubj)}(hhh]h)}(h Sync itemh]h Sync item}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMchjEhhubah}(h]h ]h"]h$]h&]uh1jhj;EhhhjSEhMgubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jEj8jEj9j:j;uh1jhhhjohNhNubj=)}(hX**Definition**:: struct drm_asahi_sync { __u32 sync_type; __u32 handle; __u64 timeline_value; }; **Members** ``sync_type`` One of drm_asahi_sync_type ``handle`` The sync object handle ``timeline_value`` Timeline value for timeline sync objectsh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEubh:}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMghjEubj`)}(h[struct drm_asahi_sync { __u32 sync_type; __u32 handle; __u64 timeline_value; };h]h[struct drm_asahi_sync { __u32 sync_type; __u32 handle; __u64 timeline_value; };}hjEsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMihjEubh)}(h **Members**h]h)}(hjEh]hMembers}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMohjEubh)}(hhh](h)}(h)``sync_type`` One of drm_asahi_sync_type h](j)}(h ``sync_type``h]j)}(hjEh]h sync_type}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMfhjEubj)}(hhh]h)}(hOne of drm_asahi_sync_typeh]hOne of drm_asahi_sync_type}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj FhMfhj Fubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1hhj FhMfhjEubh)}(h"``handle`` The sync object handle h](j)}(h ``handle``h]j)}(hj.Fh]hhandle}(hj0FhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,Fubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj(Fubj)}(hhh]h)}(hThe sync object handleh]hThe sync object handle}(hjGFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCFhKhjDFubah}(h]h ]h"]h$]h&]uh1jhj(Fubeh}(h]h ]h"]h$]h&]uh1hhjCFhKhjEubh)}(h;``timeline_value`` Timeline value for timeline sync objectsh](j)}(h``timeline_value``h]j)}(hjgFh]htimeline_value}(hjiFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeFubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjaFubj)}(hhh]h)}(h(Timeline value for timeline sync objectsh]h(Timeline value for timeline sync objects}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj}Fubah}(h]h ]h"]h$]h&]uh1jhjaFubeh}(h]h ]h"]h$]h&]uh1hhj|FhKhjEubeh}(h]h ]h"]h$]h&]uh1hhjEubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j DRM_ASAHI_BARRIER_NONE (C macro)c.DRM_ASAHI_BARRIER_NONEhNtauh1jhjohhhNhNubj)}(hhh](j)}(hDRM_ASAHI_BARRIER_NONEh]j)}(hDRM_ASAHI_BARRIER_NONEh]j)}(hDRM_ASAHI_BARRIER_NONEh]j)}(hjFh]hDRM_ASAHI_BARRIER_NONE}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ](jjeh"]h$]h&]jjuh1jhjFhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMqubah}(h]h ]h"]h$]h&]jjjuh1jjjhjFhhhjFhMqubah}(h]jFah ](j j eh"]h$]h&]jj)jhuh1jhjFhMqhjFhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjFhhhjFhMqubeh}(h]h ](j1macroeh"]h$]h&]j6j1j7jFj8jFj9j:j;uh1jhhhjohNhNubh)}(h``DRM_ASAHI_BARRIER_NONE``h]j)}(hjFh]hDRM_ASAHI_BARRIER_NONE}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMshjohhubj)}(h Command index for no barrier **Description** This special value may be passed in to drm_asahi_command::vdm_barrier or drm_asahi_command::cdm_barrier to indicate that the respective subqueue should not wait on any previous work. h](j)}(hCommand index for no barrier h]h)}(hCommand index for no barrierh]hCommand index for no barrier}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMqhjGubah}(h]h ]h"]h$]h&]uh1jhj#GhMqhj Gubh)}(h**Description**h]h)}(hj,Gh]h Description}(hj.GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*Gubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMshj Gubh)}(hThis special value may be passed in to drm_asahi_command::vdm_barrier or drm_asahi_command::cdm_barrier to indicate that the respective subqueue should not wait on any previous work.h]hThis special value may be passed in to drm_asahi_command::vdm_barrier or drm_asahi_command::cdm_barrier to indicate that the respective subqueue should not wait on any previous work.}(hjBGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMrhj Gubeh}(h]h ]h"]h$]h&]uh1jhj#GhMqhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_cmd_header (C struct)c.drm_asahi_cmd_headerhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_cmd_headerh]j)}(hstruct drm_asahi_cmd_headerh](j)}(hjh]hstruct}(hjpGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlGhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMyubj)}(h h]h }(hj~GhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlGhhhj}GhMyubj)}(hdrm_asahi_cmd_headerh]j)}(hjjGh]hdrm_asahi_cmd_header}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubah}(h]h ](jjeh"]h$]h&]jjuh1jhjlGhhhj}GhMyubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhGhhhj}GhMyubah}(h]jcGah ](j j eh"]h$]h&]jj)jhuh1jhj}GhMyhjeGhhubj)}(hhh]h)}(hTop level command structureh]hTop level command structure}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMzhjGhhubah}(h]h ]h"]h$]h&]uh1jhjeGhhhj}GhMyubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jGj8jGj9j:j;uh1jhhhjohNhNubj=)}(hX**Definition**:: struct drm_asahi_cmd_header { __u16 cmd_type; __u16 size; __u16 vdm_barrier; __u16 cdm_barrier; }; **Members** ``cmd_type`` One of drm_asahi_cmd_type ``size`` Size of this command, not including this header. For hardware commands, this enables extensibility of commands without requiring extra command types. Passing a command that is shorter than expected is explicitly allowed for backwards-compatibility. Truncated fields will be zeroed. For the synthetic attachment setting commands, this implicitly encodes the number of attachments. These commands take multiple fixed-size **drm_asahi_attachment** structures as their payload, so size equals number of attachments * sizeof(struct drm_asahi_attachment). ``vdm_barrier`` VDM (render) command index to wait on. Barriers are indices relative to the beginning of a given submit. A barrier of 0 waits on commands submitted to the respective subqueue in previous submit ioctls. A barrier of N waits on N previous commands on the subqueue within the current submit ioctl. As a special case, passing **DRM_ASAHI_BARRIER_NONE** avoids waiting on any commands in the subqueue. Examples: 0: This waits on all previous work. NONE: This does not wait for anything on this subqueue. 1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit. Barriers are valid only for hardware commands. Synthetic software commands to set attachments must pass NONE here. ``cdm_barrier`` CDM (compute) command index to wait on. See **vdm_barrier**, and replace VDM/render with CDM/compute.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh:}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM~hjGubj`)}(hrstruct drm_asahi_cmd_header { __u16 cmd_type; __u16 size; __u16 vdm_barrier; __u16 cdm_barrier; };h]hrstruct drm_asahi_cmd_header { __u16 cmd_type; __u16 size; __u16 vdm_barrier; __u16 cdm_barrier; };}hjGsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjGubh)}(h **Members**h]h)}(hjHh]hMembers}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjGubh)}(hhh](h)}(h'``cmd_type`` One of drm_asahi_cmd_type h](j)}(h ``cmd_type``h]j)}(hjHh]hcmd_type}(hj!HhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjHubj)}(hhh]h)}(hOne of drm_asahi_cmd_typeh]hOne of drm_asahi_cmd_type}(hj8HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4HhMhj5Hubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1hhj4HhMhjHubh)}(hX1``size`` Size of this command, not including this header. For hardware commands, this enables extensibility of commands without requiring extra command types. Passing a command that is shorter than expected is explicitly allowed for backwards-compatibility. Truncated fields will be zeroed. For the synthetic attachment setting commands, this implicitly encodes the number of attachments. These commands take multiple fixed-size **drm_asahi_attachment** structures as their payload, so size equals number of attachments * sizeof(struct drm_asahi_attachment). h](j)}(h``size``h]j)}(hjXHh]hsize}(hjZHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVHubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjRHubj)}(hhh](h)}(h0Size of this command, not including this header.h]h0Size of this command, not including this header.}(hjqHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjnHubh)}(hFor hardware commands, this enables extensibility of commands without requiring extra command types. Passing a command that is shorter than expected is explicitly allowed for backwards-compatibility. Truncated fields will be zeroed.h]hFor hardware commands, this enables extensibility of commands without requiring extra command types. Passing a command that is shorter than expected is explicitly allowed for backwards-compatibility. Truncated fields will be zeroed.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjnHubh)}(hX For the synthetic attachment setting commands, this implicitly encodes the number of attachments. These commands take multiple fixed-size **drm_asahi_attachment** structures as their payload, so size equals number of attachments * sizeof(struct drm_asahi_attachment).h](hFor the synthetic attachment setting commands, this implicitly encodes the number of attachments. These commands take multiple fixed-size }(hjHhhhNhNubh)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHubhi structures as their payload, so size equals number of attachments * sizeof(struct drm_asahi_attachment).}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjnHubeh}(h]h ]h"]h$]h&]uh1jhjRHubeh}(h]h ]h"]h$]h&]uh1hhjmHhMhjHubh)}(hX ``vdm_barrier`` VDM (render) command index to wait on. Barriers are indices relative to the beginning of a given submit. A barrier of 0 waits on commands submitted to the respective subqueue in previous submit ioctls. A barrier of N waits on N previous commands on the subqueue within the current submit ioctl. As a special case, passing **DRM_ASAHI_BARRIER_NONE** avoids waiting on any commands in the subqueue. Examples: 0: This waits on all previous work. NONE: This does not wait for anything on this subqueue. 1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit. Barriers are valid only for hardware commands. Synthetic software commands to set attachments must pass NONE here. h](j)}(h``vdm_barrier``h]j)}(hjHh]h vdm_barrier}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjHubj)}(hhh](h)}(h&VDM (render) command index to wait on.h]h&VDM (render) command index to wait on.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjHubh)}(hXeBarriers are indices relative to the beginning of a given submit. A barrier of 0 waits on commands submitted to the respective subqueue in previous submit ioctls. A barrier of N waits on N previous commands on the subqueue within the current submit ioctl. As a special case, passing **DRM_ASAHI_BARRIER_NONE** avoids waiting on any commands in the subqueue.h](hXBarriers are indices relative to the beginning of a given submit. A barrier of 0 waits on commands submitted to the respective subqueue in previous submit ioctls. A barrier of N waits on N previous commands on the subqueue within the current submit ioctl. As a special case, passing }(hjHhhhNhNubh)}(h**DRM_ASAHI_BARRIER_NONE**h]hDRM_ASAHI_BARRIER_NONE}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHubh0 avoids waiting on any commands in the subqueue.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjHubh)}(h Examples:h]h Examples:}(hj IhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjHubj)}(h0: This waits on all previous work. NONE: This does not wait for anything on this subqueue. 1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit. h](h)}(h#0: This waits on all previous work.h]h#0: This waits on all previous work.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjIubh)}(h7NONE: This does not wait for anything on this subqueue.h]h7NONE: This does not wait for anything on this subqueue.}(hj-IhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjIubh)}(h1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit.h]h1: This waits on the first render command in the submit. This is valid only if there are multiple render commands in the same submit.}(hjhj5Pubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1hhj4PhM?hjOubh)}(ht``comp_stride`` If layered rendering is enabled, the number of bytes between each layer of the compression metadata.h](j)}(h``comp_stride``h]j)}(hjYPh]h comp_stride}(hj[PhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWPubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMDhjSPubj)}(hhh]h)}(hdIf layered rendering is enabled, the number of bytes between each layer of the compression metadata.h]hdIf layered rendering is enabled, the number of bytes between each layer of the compression metadata.}(hjrPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnPhMDhjoPubah}(h]h ]h"]h$]h&]uh1jhjSPubeh}(h]h ]h"]h$]h&]uh1hhjnPhMDhjOubeh}(h]h ]h"]h$]h&]uh1hhj[Oubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hjPh]h Description}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMHhjohhubh)}(hXdThese fields correspond to hardware registers in the ZLS (Z Load/Store) unit. There are three hardware registers for each field respectively for loads, stores, and partial renders. In practice, it makes sense to set all to the same values, except in exceptional cases not yet implemented in userspace, so we do not duplicate here for simplicity/efficiency.h]hXdThese fields correspond to hardware registers in the ZLS (Z Load/Store) unit. There are three hardware registers for each field respectively for loads, stores, and partial renders. In practice, it makes sense to set all to the same values, except in exceptional cases not yet implemented in userspace, so we do not duplicate here for simplicity/efficiency.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM)hjohhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM/hjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_timestamp (C struct)c.drm_asahi_timestamphNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_timestamph]j)}(hstruct drm_asahi_timestamph](j)}(hjh]hstruct}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM4ubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhjPhM4ubj)}(hdrm_asahi_timestamph]j)}(hjPh]hdrm_asahi_timestamp}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ](jjeh"]h$]h&]jjuh1jhjPhhhjPhM4ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjPhhhjPhM4ubah}(h]jPah ](j j eh"]h$]h&]jj)jhuh1jhjPhM4hjPhhubj)}(hhh]h)}(hDescribe a timestamp write.h]hDescribe a timestamp write.}(hj*QhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMJhj'Qhhubah}(h]h ]h"]h$]h&]uh1jhjPhhhjPhM4ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jBQj8jBQj9j:j;uh1jhhhjohNhNubj=)}(hXM**Definition**:: struct drm_asahi_timestamp { __u32 handle; __u32 offset; }; **Members** ``handle`` Handle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle. ``offset`` Offset to write into the timestamp bufferh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjNQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJQubh:}(hjJQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMNhjFQubj`)}(hCstruct drm_asahi_timestamp { __u32 handle; __u32 offset; };h]hCstruct drm_asahi_timestamp { __u32 handle; __u32 offset; };}hjgQsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMPhjFQubh)}(h **Members**h]h)}(hjxQh]hMembers}(hjzQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvQubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMUhjFQubh)}(hhh](h)}(h``handle`` Handle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle. h](j)}(h ``handle``h]j)}(hjQh]hhandle}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMXhjQubj)}(hhh]h)}(hHandle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle.h]hHandle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMVhjQubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1hhjQhMXhjQubh)}(h4``offset`` Offset to write into the timestamp bufferh](j)}(h ``offset``h]j)}(hjQh]hoffset}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjQubj)}(hhh]h)}(h)Offset to write into the timestamp bufferh]h)Offset to write into the timestamp buffer}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjQubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1hhjQhKhjQubeh}(h]h ]h"]h$]h&]uh1hhjFQubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hjRh]h Description}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjohhubh)}(hX The firmware can optionally write the GPU timestamp at render pass granularities, but it needs to be mapped specially via DRM_IOCTL_ASAHI_GEM_BIND_OBJECT. This structure therefore describes where to write as a handle-offset pair, rather than a GPU address like normal.h]hX The firmware can optionally write the GPU timestamp at render pass granularities, but it needs to be mapped specially via DRM_IOCTL_ASAHI_GEM_BIND_OBJECT. This structure therefore describes where to write as a handle-offset pair, rather than a GPU address like normal.}(hj*RhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMKhjohhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hj9RhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMPhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_timestamps (C struct)c.drm_asahi_timestampshNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_timestampsh]j)}(hstruct drm_asahi_timestampsh](j)}(hjh]hstruct}(hjaRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]Rhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMUubj)}(h h]h }(hjoRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]RhhhjnRhMUubj)}(hdrm_asahi_timestampsh]j)}(hj[Rh]hdrm_asahi_timestamps}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}Rubah}(h]h ](jjeh"]h$]h&]jjuh1jhj]RhhhjnRhMUubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjYRhhhjnRhMUubah}(h]jTRah ](j j eh"]h$]h&]jj)jhuh1jhjnRhMUhjVRhhubj)}(hhh]h)}(hDescribe timestamp writes.h]hDescribe timestamp writes.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM`hjRhhubah}(h]h ]h"]h$]h&]uh1jhjVRhhhjnRhMUubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jRj8jRj9j:j;uh1jhhhjohNhNubj=)}(hX **Definition**:: struct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; }; **Members** ``start`` Timestamp recorded at the start of the operation ``end`` Timestamp recorded at the end of the operationh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRubh:}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMdhjRubj`)}(hjstruct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; };h]hjstruct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; };}hjRsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMfhjRubh)}(h **Members**h]h)}(hjRh]hMembers}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMkhjRubh)}(hhh](h)}(h;``start`` Timestamp recorded at the start of the operation h](j)}(h ``start``h]j)}(hjSh]hstart}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMihj Subj)}(hhh]h)}(h0Timestamp recorded at the start of the operationh]h0Timestamp recorded at the start of the operation}(hj)ShhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ShMihj&Subah}(h]h ]h"]h$]h&]uh1jhj Subeh}(h]h ]h"]h$]h&]uh1hhj%ShMihjSubh)}(h6``end`` Timestamp recorded at the end of the operationh](j)}(h``end``h]j)}(hjISh]hend}(hjKShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGSubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjCSubj)}(hhh]h)}(h.Timestamp recorded at the end of the operationh]h.Timestamp recorded at the end of the operation}(hjbShhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj_Subah}(h]h ]h"]h$]h&]uh1jhjCSubeh}(h]h ]h"]h$]h&]uh1hhj^ShKhjSubeh}(h]h ]h"]h$]h&]uh1hhjRubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hjSh]h Description}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjSubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjohhubh)}(hEach operation that can be timestamped, can be timestamped at the start and end. Therefore, drm_asahi_timestamp structs always come in pairs, bundled together into drm_asahi_timestamps.h]hEach operation that can be timestamped, can be timestamped at the start and end. Therefore, drm_asahi_timestamp structs always come in pairs, bundled together into drm_asahi_timestamps.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMahjohhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMehjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_asahi_helper_program (C struct)c.drm_asahi_helper_programhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_helper_programh]j)}(hstruct drm_asahi_helper_programh](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjShhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMjubj)}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjShhhjShMjubj)}(hdrm_asahi_helper_programh]j)}(hjSh]hdrm_asahi_helper_program}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ](jjeh"]h$]h&]jjuh1jhjShhhjShMjubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjShhhjShMjubah}(h]jSah ](j j eh"]h$]h&]jj)jhuh1jhjShMjhjShhubj)}(hhh]h)}(h&Describe helper program configuration.h]h&Describe helper program configuration.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMqhjThhubah}(h]h ]h"]h$]h&]uh1jhjShhhjShMjubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j3Tj8j3Tj9j:j;uh1jhhhjohNhNubj=)}(hX**Definition**:: struct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; }; **Members** ``binary`` USC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits. ``cfg`` Additional configuration bits for the helper program. ``data`` Data passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program. In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj?ThhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;Tubh:}(hj;ThhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMuhj7Tubj`)}(hUstruct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; };h]hUstruct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; };}hjXTsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMwhj7Tubh)}(h **Members**h]h)}(hjiTh]hMembers}(hjkThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgTubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM}hj7Tubh)}(hhh](h)}(hu``binary`` USC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits. h](j)}(h ``binary``h]j)}(hjTh]hbinary}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjTubj)}(hhh]h)}(hiUSC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits.h]hiUSC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM~hjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1hhjThMhjTubh)}(h>``cfg`` Additional configuration bits for the helper program. h](j)}(h``cfg``h]j)}(hjTh]hcfg}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjTubj)}(hhh]h)}(h5Additional configuration bits for the helper program.h]h5Additional configuration bits for the helper program.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThKhjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1hhjThKhjTubh)}(hXu``data`` Data passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program. In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h](j)}(h``data``h]j)}(hjTh]hdata}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjTubj)}(hhh](h)}(hData passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program.h]hData passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjUubh)}(h~In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h]hIn practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don’t fit in 64-bits.}(hj#UhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjUubeh}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1hhjUhMhjTubeh}(h]h ]h"]h$]h&]uh1hhj7Tubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hjLUh]h Description}(hjNUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJUubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubh)}(hXhThe helper program is a compute-like kernel required for various hardware functionality. Its most important role is dynamically allocating scratch/stack memory for individual subgroups, by partitioning a static allocation shared for the whole device. It is supplied by userspace via drm_asahi_helper_program and internally dispatched by the hardware as needed.h]hXhThe helper program is a compute-like kernel required for various hardware functionality. Its most important role is dynamically allocating scratch/stack memory for individual subgroups, by partitioning a static allocation shared for the whole device. It is supplied by userspace via drm_asahi_helper_program and internally dispatched by the hardware as needed.}(hjbUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMrhjohhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjqUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMxhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_bg_eot (C struct)c.drm_asahi_bg_eothNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_bg_eoth]j)}(hstruct drm_asahi_bg_eoth](j)}(hjh]hstruct}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM}ubj)}(h h]h }(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUhhhjUhM}ubj)}(hdrm_asahi_bg_eoth]j)}(hjUh]hdrm_asahi_bg_eot}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubah}(h]h ](jjeh"]h$]h&]jjuh1jhjUhhhjUhM}ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjUhhhjUhM}ubah}(h]jUah ](j j eh"]h$]h&]jj)jhuh1jhjUhM}hjUhhubj)}(hhh]h)}(h-Describe a background or end-of-tile program.h]h-Describe a background or end-of-tile program.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjUhhubah}(h]h ]h"]h$]h&]uh1jhjUhhhjUhM}ubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jUj8jUj9j:j;uh1jhhhjohNhNubj=)}(hXm**Definition**:: struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; }; **Members** ``usc`` USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits. ``rsrc_spec`` Resource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUubh:}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjUubj`)}(h@struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; };h]h@struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; };}hjVsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjUubh)}(h **Members**h]h)}(hj)Vh]hMembers}(hj+VhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'Vubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjUubh)}(hhh](h)}(hX>``usc`` USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits. h](j)}(h``usc``h]j)}(hjHVh]husc}(hjJVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFVubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjBVubj)}(hhh]h)}(hX5USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits.h]hX5USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits.}(hjaVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj^Vubah}(h]h ]h"]h$]h&]uh1jhjBVubeh}(h]h ]h"]h$]h&]uh1hhj]VhMhj?Vubh)}(h``rsrc_spec`` Resource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h](j)}(h ``rsrc_spec``h]j)}(hjVh]h rsrc_spec}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj|Vubj)}(hhh]h)}(hResource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h]hResource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjVubah}(h]h ]h"]h$]h&]uh1jhj|Vubeh}(h]h ]h"]h$]h&]uh1hhjVhMhj?Vubeh}(h]h ]h"]h$]h&]uh1hhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hjVh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubh)}(hXThe background and end-of-tile programs are dispatched by the hardware at the beginning and end of rendering. As the hardware "tilebuffer" is simply local memory, these programs are necessary to implement API-level render targets. The fragment-like background program is responsible for loading either the clear colour or the existing render target contents, while the compute-like end-of-tile program stores the tilebuffer contents to memory.h]hXThe background and end-of-tile programs are dispatched by the hardware at the beginning and end of rendering. As the hardware “tilebuffer” is simply local memory, these programs are necessary to implement API-level render targets. The fragment-like background program is responsible for loading either the clear colour or the existing render target contents, while the compute-like end-of-tile program stores the tilebuffer contents to memory.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_cmd_render (C struct)c.drm_asahi_cmd_renderhNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_cmd_renderh]j)}(hstruct drm_asahi_cmd_renderh](j)}(hjh]hstruct}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj WhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWhhhjWhMubj)}(hdrm_asahi_cmd_renderh]j)}(hj Wh]hdrm_asahi_cmd_render}(hj2WhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.Wubah}(h]h ](jjeh"]h$]h&]jjuh1jhjWhhhjWhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj WhhhjWhMubah}(h]jWah ](j j eh"]h$]h&]jj)jhuh1jhjWhMhjWhhubj)}(hhh]h)}(hCommand to submit 3Dh]hCommand to submit 3D}(hjTWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjQWhhubah}(h]h ]h"]h$]h&]uh1jhjWhhhjWhMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7jlWj8jlWj9j:j;uh1jhhhjohNhNubj=)}(hXh**Definition**:: struct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; }; **Members** ``flags`` Combination of drm_asahi_render_flags flags. ``isp_zls_pixels`` ISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height. ``vdm_ctrl_stream_base`` VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream. ``vertex_helper`` Helper program used for the vertex shader ``fragment_helper`` Helper program used for the fragment shader ``isp_scissor_base`` ISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass. ``isp_dbias_base`` ISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass. ``isp_oclqry_base`` ISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass. ``depth`` Depth buffer ``stencil`` Stencil buffer ``zls_ctrl`` ZLS_CTRL register value ``ppp_multisamplectl`` PPP_MULTISAMPLECTL register value ``sampler_heap`` Base address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps. ``ppp_ctrl`` PPP_CTRL register value ``width_px`` Framebuffer width in pixels ``height_px`` Framebuffer height in pixels ``layers`` Number of layers in the framebuffer ``sampler_count`` Number of samplers in the sampler heap. ``utile_width_px`` Width of a logical tilebuffer tile in pixels ``utile_height_px`` Height of a logical tilebuffer tile in pixels ``samples`` # of samples in the framebuffer. Must be 1, 2, or 4. ``sample_size_B`` # of bytes in the tilebuffer required per sample. ``isp_merge_upper_x`` 32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width. Making these values UAPI avoids requiring floating-point calculations in the kernel in the hot path. ``isp_merge_upper_y`` 32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**. ``bg`` Background program run for each tile at the start ``eot`` End-of-tile program ran for each tile at the end ``partial_bg`` Background program ran at the start of each tile when resuming the render pass during a partial render. ``partial_eot`` End-of-tile program ran at the end of each tile when pausing the render pass during a partial render. ``isp_bgobjdepth`` ISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed). ``isp_bgobjvals`` ISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value. ``ts_vtx`` Timestamps for the vertex portion of the render ``ts_frag`` Timestamps for the fragment portion of the renderh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjxWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjtWubh:}(hjtWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjpWubj`)}(hXstruct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; };h]hXstruct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; };}hjWsbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjpWubh)}(h **Members**h]h)}(hjWh]hMembers}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjpWubh)}(hhh](h)}(h7``flags`` Combination of drm_asahi_render_flags flags. h](j)}(h ``flags``h]j)}(hjWh]hflags}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjWubj)}(hhh]h)}(h,Combination of drm_asahi_render_flags flags.h]h,Combination of drm_asahi_render_flags flags.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhMhjWubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1hhjWhMhjWubh)}(h``isp_zls_pixels`` ISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height. h](j)}(h``isp_zls_pixels``h]j)}(hjWh]hisp_zls_pixels}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjWubj)}(hhh]h)}(hISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height.h]hISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjXubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1hhjXhMhjWubh)}(hv``vdm_ctrl_stream_base`` VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream. h](j)}(h``vdm_ctrl_stream_base``h]j)}(hj4Xh]hvdm_ctrl_stream_base}(hj6XhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2Xubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj.Xubj)}(hhh]h)}(h\VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream.h]h\VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream.}(hjMXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjJXubah}(h]h ]h"]h$]h&]uh1jhj.Xubeh}(h]h ]h"]h$]h&]uh1hhjIXhMhjWubh)}(h<``vertex_helper`` Helper program used for the vertex shader h](j)}(h``vertex_helper``h]j)}(hjnXh]h vertex_helper}(hjpXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlXubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjhXubj)}(hhh]h)}(h)Helper program used for the vertex shaderh]h)Helper program used for the vertex shader}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhKhjXubah}(h]h ]h"]h$]h&]uh1jhjhXubeh}(h]h ]h"]h$]h&]uh1hhjXhKhjWubh)}(h@``fragment_helper`` Helper program used for the fragment shader h](j)}(h``fragment_helper``h]j)}(hjXh]hfragment_helper}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjXubj)}(hhh]h)}(h+Helper program used for the fragment shaderh]h+Helper program used for the fragment shader}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhKhjXubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1hhjXhKhjWubh)}(h``isp_scissor_base`` ISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass. h](j)}(h``isp_scissor_base``h]j)}(hjXh]hisp_scissor_base}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjXubj)}(hhh]h)}(hkISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass.h]hkISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjXubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1hhjXhMhjWubh)}(h{``isp_dbias_base`` ISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass. h](j)}(h``isp_dbias_base``h]j)}(hjYh]hisp_dbias_base}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjYubj)}(hhh]h)}(hgISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass.h]hgISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass.}(hj3YhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj0Yubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1hhj/YhMhjWubh)}(h``isp_oclqry_base`` ISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass. h](j)}(h``isp_oclqry_base``h]j)}(hjTYh]hisp_oclqry_base}(hjVYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRYubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjNYubj)}(hhh]h)}(hnISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass.h]hnISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass.}(hjmYhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjjYubah}(h]h ]h"]h$]h&]uh1jhjNYubeh}(h]h ]h"]h$]h&]uh1hhjiYhMhjWubh)}(h``depth`` Depth buffer h](j)}(h ``depth``h]j)}(hjYh]hdepth}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjYubj)}(hhh]h)}(h Depth bufferh]h Depth buffer}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhKhjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1hhjYhKhjWubh)}(h``stencil`` Stencil buffer h](j)}(h ``stencil``h]j)}(hjYh]hstencil}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjYubj)}(hhh]h)}(hStencil bufferh]hStencil buffer}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhKhjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1hhjYhKhjWubh)}(h%``zls_ctrl`` ZLS_CTRL register value h](j)}(h ``zls_ctrl``h]j)}(hjZh]hzls_ctrl}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjYubj)}(hhh]h)}(hZLS_CTRL register valueh]hZLS_CTRL register value}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhKhjZubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1hhjZhKhjWubh)}(h9``ppp_multisamplectl`` PPP_MULTISAMPLECTL register value h](j)}(h``ppp_multisamplectl``h]j)}(hj9Zh]hppp_multisamplectl}(hj;ZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7Zubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj3Zubj)}(hhh]h)}(h!PPP_MULTISAMPLECTL register valueh]h!PPP_MULTISAMPLECTL register value}(hjRZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNZhKhjOZubah}(h]h ]h"]h$]h&]uh1jhj3Zubeh}(h]h ]h"]h$]h&]uh1hhjNZhKhjWubh)}(h``sampler_heap`` Base address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps. h](j)}(h``sampler_heap``h]j)}(hjrZh]h sampler_heap}(hjtZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpZubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjlZubj)}(hhh]h)}(hBase address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps.h]hBase address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjZubah}(h]h ]h"]h$]h&]uh1jhjlZubeh}(h]h ]h"]h$]h&]uh1hhjZhMhjWubh)}(h%``ppp_ctrl`` PPP_CTRL register value h](j)}(h ``ppp_ctrl``h]j)}(hjZh]hppp_ctrl}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjZubj)}(hhh]h)}(hPPP_CTRL register valueh]hPPP_CTRL register value}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhKhjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1hhjZhKhjWubh)}(h)``width_px`` Framebuffer width in pixels h](j)}(h ``width_px``h]j)}(hjZh]hwidth_px}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjZubj)}(hhh]h)}(hFramebuffer width in pixelsh]hFramebuffer width in pixels}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhKhjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1hhjZhKhjWubh)}(h+``height_px`` Framebuffer height in pixels kh](j)}(h ``height_px``h]j)}(hj[h]h height_px}(hj [hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj[ubj)}(hhh]h)}(hFramebuffer height in pixelsh]hFramebuffer height in pixels}(hj7[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3[hKhj4[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1hhj3[hKhjWubh)}(h/``layers`` Number of layers in the framebuffer h](j)}(h ``layers``h]j)}(hjW[h]hlayers}(hjY[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU[ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjQ[ubj)}(hhh]h)}(h#Number of layers in the framebufferh]h#Number of layers in the framebuffer}(hjp[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl[hKhjm[ubah}(h]h ]h"]h$]h&]uh1jhjQ[ubeh}(h]h ]h"]h$]h&]uh1hhjl[hKhjWubh)}(h:``sampler_count`` Number of samplers in the sampler heap. h](j)}(h``sampler_count``h]j)}(hj[h]h sampler_count}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj[ubj)}(hhh]h)}(h'Number of samplers in the sampler heap.h]h'Number of samplers in the sampler heap.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hKhj[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1hhj[hKhjWubh)}(h@``utile_width_px`` Width of a logical tilebuffer tile in pixels h](j)}(h``utile_width_px``h]j)}(hj[h]hutile_width_px}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj[ubj)}(hhh]h)}(h,Width of a logical tilebuffer tile in pixelsh]h,Width of a logical tilebuffer tile in pixels}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hKhj[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1hhj[hKhjWubh)}(hB``utile_height_px`` Height of a logical tilebuffer tile in pixels h](j)}(h``utile_height_px``h]j)}(hj\h]hutile_height_px}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj[ubj)}(hhh]h)}(h-Height of a logical tilebuffer tile in pixelsh]h-Height of a logical tilebuffer tile in pixels}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hKhj\ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1hhj\hKhjWubh)}(hA``samples`` # of samples in the framebuffer. Must be 1, 2, or 4. h](j)}(h ``samples``h]j)}(hj;\h]hsamples}(hj=\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj5\ubj)}(hhh]h)}(h4# of samples in the framebuffer. Must be 1, 2, or 4.h]h4# of samples in the framebuffer. Must be 1, 2, or 4.}(hjT\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP\hKhjQ\ubah}(h]h ]h"]h$]h&]uh1jhj5\ubeh}(h]h ]h"]h$]h&]uh1hhjP\hKhjWubh)}(hD``sample_size_B`` # of bytes in the tilebuffer required per sample. h](j)}(h``sample_size_B``h]j)}(hjt\h]h sample_size_B}(hjv\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjr\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjn\ubj)}(hhh]h)}(h1# of bytes in the tilebuffer required per sample.h]h1# of bytes in the tilebuffer required per sample.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hKhj\ubah}(h]h ]h"]h$]h&]uh1jhjn\ubeh}(h]h ]h"]h$]h&]uh1hhj\hKhjWubh)}(h``isp_merge_upper_x`` 32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width. Making these values UAPI avoids requiring floating-point calculations in the kernel in the hot path. h](j)}(h``isp_merge_upper_x``h]j)}(hj\h]hisp_merge_upper_x}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM)hj\ubj)}(hhh](h)}(hV32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width.h]hV32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM%hj\ubh)}(hdMaking these values UAPI avoids requiring floating-point calculations in the kernel in the hot path.h]hdMaking these values UAPI avoids requiring floating-point calculations in the kernel in the hot path.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM(hj\ubeh}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1hhj\hM)hjWubh)}(hc``isp_merge_upper_y`` 32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**. h](j)}(h``isp_merge_upper_y``h]j)}(hj\h]hisp_merge_upper_y}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM/hj\ubj)}(hhh]h)}(hL32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**.h](h632-bit float. Calculate as: tan(60 deg) * height. See }(hj]hhhNhNubh)}(h**isp_merge_upper_x**h]hisp_merge_upper_x}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]ubh.}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM.hj ]ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1hhj ]hM/hjWubh)}(h9``bg`` Background program run for each tile at the start h](j)}(h``bg``h]j)}(hjB]h]hbg}(hjD]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@]ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj<]ubj)}(hhh]h)}(h1Background program run for each tile at the starth]h1Background program run for each tile at the start}(hj[]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjW]hKhjX]ubah}(h]h ]h"]h$]h&]uh1jhj<]ubeh}(h]h ]h"]h$]h&]uh1hhjW]hKhjWubh)}(h9``eot`` End-of-tile program ran for each tile at the end h](j)}(h``eot``h]j)}(hj{]h]heot}(hj}]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy]ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhju]ubj)}(hhh]h)}(h0End-of-tile program ran for each tile at the endh]h0End-of-tile program ran for each tile at the end}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hKhj]ubah}(h]h ]h"]h$]h&]uh1jhju]ubeh}(h]h ]h"]h$]h&]uh1hhj]hKhjWubh)}(hw``partial_bg`` Background program ran at the start of each tile when resuming the render pass during a partial render. h](j)}(h``partial_bg``h]j)}(hj]h]h partial_bg}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM;hj]ubj)}(hhh]h)}(hgBackground program ran at the start of each tile when resuming the render pass during a partial render.h]hgBackground program ran at the start of each tile when resuming the render pass during a partial render.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM:hj]ubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1hhj]hM;hjWubh)}(hv``partial_eot`` End-of-tile program ran at the end of each tile when pausing the render pass during a partial render. h](j)}(h``partial_eot``h]j)}(hj]h]h partial_eot}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMAhj]ubj)}(hhh]h)}(heEnd-of-tile program ran at the end of each tile when pausing the render pass during a partial render.h]heEnd-of-tile program ran at the end of each tile when pausing the render pass during a partial render.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM@hj^ubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1hhj^hMAhjWubh)}(h``isp_bgobjdepth`` ISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed). h](j)}(h``isp_bgobjdepth``h]j)}(hj(^h]hisp_bgobjdepth}(hj*^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMHhj"^ubj)}(hhh]h)}(hISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed).h]hISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer’s format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed).}(hjA^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMFhj>^ubah}(h]h ]h"]h$]h&]uh1jhj"^ubeh}(h]h ]h"]h$]h&]uh1hhj=^hMHhjWubh)}(hj``isp_bgobjvals`` ISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value. h](j)}(h``isp_bgobjvals``h]j)}(hjb^h]h isp_bgobjvals}(hjd^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMNhj\^ubj)}(hhh]h)}(hWISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value.h]hWISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value.}(hj{^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMMhjx^ubah}(h]h ]h"]h$]h&]uh1jhj\^ubeh}(h]h ]h"]h$]h&]uh1hhjw^hMNhjWubh)}(h;``ts_vtx`` Timestamps for the vertex portion of the render h](j)}(h ``ts_vtx``h]j)}(hj^h]hts_vtx}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj^ubj)}(hhh]h)}(h/Timestamps for the vertex portion of the renderh]h/Timestamps for the vertex portion of the render}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hKhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1hhj^hKhjWubh)}(h=``ts_frag`` Timestamps for the fragment portion of the renderh](j)}(h ``ts_frag``h]j)}(hj^h]hts_frag}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj^ubj)}(hhh]h)}(h1Timestamps for the fragment portion of the renderh]h1Timestamps for the fragment portion of the render}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1hhj^hKhjWubeh}(h]h ]h"]h$]h&]uh1hhjpWubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubh)}(h**Description**h]h)}(hj_h]h Description}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjohhubh)}(hThis command submits a single render pass. The hardware control stream may include many draws and subpasses, but within the command, the framebuffer dimensions and attachments are fixed.h]hThis command submits a single render pass. The hardware control stream may include many draws and subpasses, but within the command, the framebuffer dimensions and attachments are fixed.}(hj._hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubh)}(hXBThe hardware requires the firmware to set a large number of Control Registers setting up state at render pass granularity before each command rendering 3D. The firmware bundles this state into data structures. Unfortunately, we cannot expose either any of that directly to userspace, because the kernel-firmware ABI is not stable. Although we can guarantee the firmware updates in tandem with the kernel, we cannot break old userspace when upgrading the firmware and kernel. Therefore, we need to abstract well the data structures to avoid tying our hands with future firmwares.h]hXBThe hardware requires the firmware to set a large number of Control Registers setting up state at render pass granularity before each command rendering 3D. The firmware bundles this state into data structures. Unfortunately, we cannot expose either any of that directly to userspace, because the kernel-firmware ABI is not stable. Although we can guarantee the firmware updates in tandem with the kernel, we cannot break old userspace when upgrading the firmware and kernel. Therefore, we need to abstract well the data structures to avoid tying our hands with future firmwares.}(hj=_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubh)}(hThe bulk of drm_asahi_cmd_render therefore consists of values of hardware control registers, marshalled via the firmware interface.h]hThe bulk of drm_asahi_cmd_render therefore consists of values of hardware control registers, marshalled via the firmware interface.}(hjL_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubh)}(hXThe framebuffer/tilebuffer dimensions are also specified here. In addition to being passed to the firmware/hardware, the kernel requires these dimensions to calculate various essential tiling-related data structures. It is unfortunate that our submits are heavier than on vendors with saner hardware-software interfaces. The upshot is all of this information is readily available to userspace with all current APIs.h]hXThe framebuffer/tilebuffer dimensions are also specified here. In addition to being passed to the firmware/hardware, the kernel requires these dimensions to calculate various essential tiling-related data structures. It is unfortunate that our submits are heavier than on vendors with saner hardware-software interfaces. The upshot is all of this information is readily available to userspace with all current APIs.}(hj[_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubh)}(hiIt looks odd - but it's not overly burdensome and it ensures we can remain compatible with old userspace.h]hkIt looks odd - but it’s not overly burdensome and it ensures we can remain compatible with old userspace.}(hjj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_asahi_cmd_compute (C struct)c.drm_asahi_cmd_computehNtauh1jhjohhhNhNubj)}(hhh](j)}(hdrm_asahi_cmd_computeh]j)}(hstruct drm_asahi_cmd_computeh](j)}(hjh]hstruct}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhhj_hMubj)}(hdrm_asahi_cmd_computeh]j)}(hj_h]hdrm_asahi_cmd_compute}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj_hhhj_hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj_hhhj_hMubah}(h]j_ah ](j j eh"]h$]h&]jj)jhuh1jhj_hMhj_hhubj)}(hhh]h)}(hCommand to submit computeh]hCommand to submit compute}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMYhj_hhubah}(h]h ]h"]h$]h&]uh1jhj_hhhj_hMubeh}(h]h ](j1structeh"]h$]h&]j6j1j7j_j8j_j9j:j;uh1jhhhjohNhNubj=)}(hXV**Definition**:: struct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; }; **Members** ``flags`` MBZ ``sampler_count`` Number of samplers in the sampler heap. ``cdm_ctrl_stream_base`` CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream. ``cdm_ctrl_stream_end`` GPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere. ``sampler_heap`` Base address of the sampler heap. ``helper`` Helper program used for this compute command ``ts`` Timestamps for the compute commandh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_ubh:}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM]hj_ubj`)}(hstruct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; };h]hstruct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; };}hj`sbah}(h]h ]h"]h$]h&]jjuh1j_h\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM_hj_ubh)}(h **Members**h]h)}(hj"`h]hMembers}(hj$`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj `ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMihj_ubh)}(hhh](h)}(h``flags`` MBZ h](j)}(h ``flags``h]j)}(hjA`h]hflags}(hjC`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM`hj;`ubj)}(hhh]h)}(hMBZh]hMBZ}(hjZ`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV`hM`hjW`ubah}(h]h ]h"]h$]h&]uh1jhj;`ubeh}(h]h ]h"]h$]h&]uh1hhjV`hM`hj8`ubh)}(h:``sampler_count`` Number of samplers in the sampler heap. h](j)}(h``sampler_count``h]j)}(hjz`h]h sampler_count}(hj|`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjx`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjt`ubj)}(hhh]h)}(h'Number of samplers in the sampler heap.h]h'Number of samplers in the sampler heap.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hKhj`ubah}(h]h ]h"]h$]h&]uh1jhjt`ubeh}(h]h ]h"]h$]h&]uh1hhj`hKhj8`ubh)}(hv``cdm_ctrl_stream_base`` CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream. h](j)}(h``cdm_ctrl_stream_base``h]j)}(hj`h]hcdm_ctrl_stream_base}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMihj`ubj)}(hhh]h)}(h\CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream.h]h\CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhhj`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1hhj`hMihj8`ubh)}(h``cdm_ctrl_stream_end`` GPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere. h](j)}(h``cdm_ctrl_stream_end``h]j)}(hj`h]hcdm_ctrl_stream_end}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMphj`ubj)}(hhh]h)}(hGPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere.h]hGPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMnhjaubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1hhjahMphj8`ubh)}(h3``sampler_heap`` Base address of the sampler heap. h](j)}(h``sampler_heap``h]j)}(hj'ah]h sampler_heap}(hj)ahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%aubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhj!aubj)}(hhh]h)}(h!Base address of the sampler heap.h]h!Base address of the sampler heap.}(hj@ahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj``gpu_timestamp`` On return, the GPU timestamp in nanoseconds.h](j)}(h``gpu_timestamp``h]j)}(hjch]h gpu_timestamp}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjbubj)}(hhh]h)}(h,On return, the GPU timestamp in nanoseconds.h]h,On return, the GPU timestamp in nanoseconds.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKhjcubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1hhjchKhjbubeh}(h]h ]h"]h$]h&]uh1hhjxbubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jDRM_IOCTL_ASAHI (C macro)c.DRM_IOCTL_ASAHIhNtauh1jhjohhhNhNubj)}(hhh](j)}(hDRM_IOCTL_ASAHIh]j)}(hDRM_IOCTL_ASAHIh]j)}(hDRM_IOCTL_ASAHIh]j)}(hjVch]hDRM_IOCTL_ASAHI}(hj`chhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\cubah}(h]h ](jjeh"]h$]h&]jjuh1jhjXchhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubah}(h]h ]h"]h$]h&]jjjuh1jjjhjTchhhjschMubah}(h]jOcah ](j j eh"]h$]h&]jj)jhuh1jhjschMhjQchhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjQchhhjschMubeh}(h]h ](j1macroeh"]h$]h&]j6j1j7jcj8jcj9j:j;uh1jhhhjohNhNubh)}(h,``DRM_IOCTL_ASAHI (__access, __id, __type)``h]j)}(hjch]h(DRM_IOCTL_ASAHI (__access, __id, __type)}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjohhubj)}(hBuild an Asahi IOCTL number h]h)}(hBuild an Asahi IOCTL numberh]hBuild an Asahi IOCTL number}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubah}(h]h ]h"]h$]h&]uh1jhjchMhjohhubj=)}(hXF**Parameters** ``__access`` Access type. Must be R, W or RW. ``__id`` One of the DRM_ASAHI_xxx id. ``__type`` Suffix of the type being passed to the IOCTL. **Description** Don't use this macro directly, use the DRM_IOCTL_ASAHI_xxx values instead. **Return** An IOCTL number to be passed to ioctl() from userspace.h](h)}(h**Parameters**h]h)}(hjch]h Parameters}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjcubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubh)}(hhh](h)}(h.``__access`` Access type. Must be R, W or RW. h](j)}(h ``__access``h]j)}(hjch]h__access}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubj)}(hhh]h)}(h Access type. Must be R, W or RW.h]h Access type. Must be R, W or RW.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjcubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1hhjchMhjcubh)}(h&``__id`` One of the DRM_ASAHI_xxx id. h](j)}(h``__id``h]j)}(hjdh]h__id}(hj!dhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjdubj)}(hhh]h)}(hOne of the DRM_ASAHI_xxx id.h]hOne of the DRM_ASAHI_xxx id.}(hj8dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4dhMhj5dubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1hhj4dhMhjcubh)}(h9``__type`` Suffix of the type being passed to the IOCTL. h](j)}(h ``__type``h]j)}(hjXdh]h__type}(hjZdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVdubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjRdubj)}(hhh]h)}(h-Suffix of the type being passed to the IOCTL.h]h-Suffix of the type being passed to the IOCTL.}(hjqdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmdhMhjndubah}(h]h ]h"]h$]h&]uh1jhjRdubeh}(h]h ]h"]h$]h&]uh1hhjmdhMhjcubeh}(h]h ]h"]h$]h&]uh1hhjcubh)}(h**Description**h]h)}(hjdh]h Description}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubh)}(hJDon't use this macro directly, use the DRM_IOCTL_ASAHI_xxx values instead.h]hLDon’t use this macro directly, use the DRM_IOCTL_ASAHI_xxx values instead.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubh)}(h **Return**h]h)}(hjdh]hReturn}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubh)}(h7An IOCTL number to be passed to ioctl() from userspace.h]h7An IOCTL number to be passed to ioctl() from userspace.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubeh}(h]h ] kernelindentah"]h$]h&]uh1j<hjohhhNhNubeh}(h]drm-asahi-uapiah ]h"]drm/asahi uapiah$]h&]uh1hhhhhhhhK ubeh}(h]drm-driver-uapiah ]h"]drm driver uapiah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjeerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}engine discovery uapi]j]asrefids}(h]haj]jaj]jaj"]j"ajm]j7ajK]jKaj.f]j$fajg]jgajkh]jahajh]jhaj[]jQaj]jajb]jXaj]jaunameids}(jdjdjpUjmUhhjjj/jj"j"j 8jmjKjKjfj fjfjfj=j:jDfj.fjgjgjhjkhjhjhjljijrj[jjjxjbjdjdjju nametypes}(jdjpUhjj/j"j 8jKjfjfj=jDfjgjhjhjljrjjxjdjuh}(jdhjmUhhhjjj0j5jWj\jjjjj6 j; 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