9sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget#/translations/zh_CN/gpu/driver-uapimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/zh_TW/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/it_IT/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ja_JP/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ko_KR/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/pt_BR/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/sp_SP/gpu/driver-uapimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hDRM Driver uAPIh]hDRM Driver uAPI}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh=/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi.rsthKubh)}(hhh](h)}(h drm/i915 uAPIh]h drm/i915 uAPI}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubhtarget)}(h1.. _uevents generated by i915 on its device node:h]h}(h]h ]h"]h$]h&]refid,uevents-generated-by-i915-on-its-device-nodeuh1hhKhhhhhNubh paragraph)}(h0**uevents generated by i915 on its device node**h]hstrong)}(hhh]h,uevents generated by i915 on its device node}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]hah ]h"],uevents generated by i915 on its device nodeah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhexpect_referenced_by_name}jhsexpect_referenced_by_id}hhsubhdefinition_list)}(hhh](hdefinition_list_item)}(hXI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch event from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1. h](hterm)}(hLI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatchh]hLI915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK.hjubh definition)}(hhh]h)}(hXQevent from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1.h]hXQevent from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK*hj)ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj&hK.hj ubj)}(hXI915_ERROR_UEVENT - Generated upon error detection, currently only via hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen. h](j)}(hFI915_ERROR_UEVENT - Generated upon error detection, currently only viah]hFI915_ERROR_UEVENT - Generated upon error detection, currently only via}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK5hjGubj()}(hhh]h)}(hX?hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen.h]hX?hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK1hjZubah}(h]h ]h"]h$]h&]uh1j'hjGubeh}(h]h ]h"]h$]h&]uh1jhjYhK5hj ubj)}(hI915_RESET_UEVENT - Event is generated just before an attempt to reset the GPU. The value supplied with the event is always 1. NOTE: Disable reset via module parameter will cause this event to not be seen. h](j)}(hJI915_RESET_UEVENT - Event is generated just before an attempt to reset theh]hJI915_RESET_UEVENT - Event is generated just before an attempt to reset the}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhK>ubh desc_name)}(hi915_user_extensionh]h desc_sig_name)}(hjh]hi915_user_extension}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhK>ubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jsphinx_line_type declaratorhjhhhjhK>ubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhK>hjhhubh desc_content)}(hhh]h)}(h-Base class for defining a chain of extensionsh]h-Base class for defining a chain of extensions}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKBhj*hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhK>ubeh}(h]h ](cstructeh"]h$]h&]domainjEobjtypejFdesctypejFnoindex noindexentrynocontentsentryuh1jhhhhhNhNubh container)}(hX**Definition**:: struct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; }; **Members** ``next_extension`` Pointer to the next struct i915_user_extension, or zero if the end. ``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension. ``flags`` MBZ All undefined bits must be zero. ``rsvd`` MBZ Reserved for future use; must be zero.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVubh:}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKFhjRubh literal_block)}(hmstruct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; };h]hmstruct i915_user_extension { __u64 next_extension; __u32 name; __u32 flags; __u32 rsvd[4]; };}hjusbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKHhjRubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKOhjRubj )}(hhh](j)}(hW``next_extension`` Pointer to the next struct i915_user_extension, or zero if the end. h](j)}(h``next_extension``h]hliteral)}(hjh]hnext_extension}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKihjubj()}(hhh]h)}(hCPointer to the next struct i915_user_extension, or zero if the end.h]hCPointer to the next struct i915_user_extension, or zero if the end.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKihjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKihjubj)}(hX``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension. h](j)}(h``name``h]j)}(hjh]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKuhjubj()}(hhh](h)}(hName of the extension.h]hName of the extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKohjubh)}(h-Note that the name here is just some integer.h]h-Note that the name here is just some integer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKqhjubh)}(hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension.h]hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct i915_user_extension.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKshjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKuhjubj)}(h0``flags`` MBZ All undefined bits must be zero. h](j)}(h ``flags``h]j)}(hj8h]hflags}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK{hj2ubj()}(hhh](h)}(hMBZh]hMBZ}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKyhjNubh)}(h All undefined bits must be zero.h]h All undefined bits must be zero.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhK{hjNubeh}(h]h ]h"]h$]h&]uh1j'hj2ubeh}(h]h ]h"]h$]h&]uh1jhjMhK{hjubj)}(h4``rsvd`` MBZ Reserved for future use; must be zero.h](j)}(h``rsvd``h]j)}(hjh]hrsvd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjzubj()}(hhh](h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubh)}(h&Reserved for future use; must be zero.h]h&Reserved for future use; must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubeh}(h]h ]h"]h$]h&]uh1j'hjzubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1j hjRubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hX5Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan's approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.h]hX7Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan’s approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKChhhhubh)}(hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. 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The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKIhhhhubh)}(hExample chaining:h]hExample chaining:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKOhhhhubjt)}(hX)struct i915_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct i915_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct i915_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };h]hX)struct i915_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct i915_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct i915_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };}hjsbah}(h]h ]h"]h$]h&]jjforcelanguageChighlight_args}uh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKQhhhhubh)}(hTypically the struct i915_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.h]hTypically the struct i915_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhK`hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_engine_class (C enum)c.drm_i915_gem_engine_classhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_engine_classh]j)}(henum drm_i915_gem_engine_classh](j)}(henumh]henum}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKgubj)}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMhhhj_hKgubj)}(hdrm_i915_gem_engine_classh]j)}(hjKh]hdrm_i915_gem_engine_class}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubah}(h]h ](j jeh"]h$]h&]jjuh1jhjMhhhj_hKgubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjIhhhj_hKgubah}(h]jDah ](j j!eh"]h$]h&]j%j&)j'huh1jhj_hKghjFhhubj))}(hhh]h)}(huapi engine type enumerationh]huapi engine type enumeration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1j(hjFhhhj_hKgubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhhhNhNubjQ)}(hXN**Constants** ``I915_ENGINE_CLASS_RENDER`` Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs). ``I915_ENGINE_CLASS_COPY`` Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data. ``I915_ENGINE_CLASS_VIDEO`` Video engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode. ``I915_ENGINE_CLASS_VIDEO_ENHANCE`` Video enhancement engines (also referred to as "vebox") support instructions related to image enhancement. ``I915_ENGINE_CLASS_COMPUTE`` Compute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline. ``I915_ENGINE_CLASS_INVALID`` Placeholder value to represent an invalid engine class assignment.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj )}(hhh](j)}(hXK``I915_ENGINE_CLASS_RENDER`` Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs). h](j)}(h``I915_ENGINE_CLASS_RENDER``h]j)}(hjh]hI915_ENGINE_CLASS_RENDER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj()}(hhh]h)}(hX-Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs).h]hX7Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called “kernels” or “shaders”) on the GPU’s execution units (EUs).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hXL``I915_ENGINE_CLASS_COPY`` Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data. h](j)}(h``I915_ENGINE_CLASS_COPY``h]j)}(hjh]hI915_ENGINE_CLASS_COPY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj ubj()}(hhh]h)}(hX0Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data.h]hX4Copy engines (also referred to as “blitters”) support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj%ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj$hKhjubj)}(h``I915_ENGINE_CLASS_VIDEO`` Video engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode. h](j)}(h``I915_ENGINE_CLASS_VIDEO``h]j)}(hjIh]hI915_ENGINE_CLASS_VIDEO}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjCubj()}(hhh]h)}(hVideo engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode.h]hVideo engines (also referred to as “bit stream decode” (BSD) or “vdbox”) support instructions that perform fixed-function media decode and encode.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj_ubah}(h]h ]h"]h$]h&]uh1j'hjCubeh}(h]h ]h"]h$]h&]uh1jhj^hKhjubj)}(h``I915_ENGINE_CLASS_VIDEO_ENHANCE`` Video enhancement engines (also referred to as "vebox") support instructions related to image enhancement. h](j)}(h#``I915_ENGINE_CLASS_VIDEO_ENHANCE``h]j)}(hjh]hI915_ENGINE_CLASS_VIDEO_ENHANCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj}ubj()}(hhh]h)}(hjVideo enhancement engines (also referred to as "vebox") support instructions related to image enhancement.h]hnVideo enhancement engines (also referred to as “vebox”) support instructions related to image enhancement.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1j'hj}ubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h``I915_ENGINE_CLASS_COMPUTE`` Compute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline. h](j)}(h``I915_ENGINE_CLASS_COMPUTE``h]j)}(hjh]hI915_ENGINE_CLASS_COMPUTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj()}(hhh]h)}(hCompute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline.h]hCompute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h```I915_ENGINE_CLASS_INVALID`` Placeholder value to represent an invalid engine class assignment.h](j)}(h``I915_ENGINE_CLASS_INVALID``h]j)}(hjh]hI915_ENGINE_CLASS_INVALID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj()}(hhh]h)}(hBPlaceholder value to represent an invalid engine class assignment.h]hBPlaceholder value to represent an invalid engine class assignment.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj:h]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hX-Different engines serve different roles, and there may be more than one engine serving each role. This enum provides a classification of the role of the engine, which may be used when requesting operations to be performed on a certain subset of engines, or for providing information about that group.h]hX-Different engines serve different roles, and there may be more than one engine serving each role. This enum provides a classification of the role of the engine, which may be used when requesting operations to be performed on a certain subset of engines, or for providing information about that group.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%i915_engine_class_instance (C struct)c.i915_engine_class_instancehNtauh1jhhhhhNhNubj)}(hhh](j)}(hi915_engine_class_instanceh]j)}(h!struct i915_engine_class_instanceh](j)}(hjh]hstruct}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjthhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjthhhjhKubj)}(hi915_engine_class_instanceh]j)}(hjrh]hi915_engine_class_instance}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjthhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjphhhjhKubah}(h]jkah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhKhjmhhubj))}(hhh]h)}(h Engine class/instance identifierh]h Engine class/instance identifier}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1j(hjmhhhjhKubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhhhNhNubjQ)}(hXJ**Definition**:: struct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; }; **Members** ``engine_class`` Engine class from enum drm_i915_gem_engine_class ``engine_instance`` Engine instance.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubjt)}(hstruct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; };h]hstruct i915_engine_class_instance { __u16 engine_class; #define I915_ENGINE_CLASS_INVALID_NONE -1; #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2; __u16 engine_instance; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubh)}(h **Members**h]h)}(hjh]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjubj )}(hhh](j)}(hB``engine_class`` Engine class from enum drm_i915_gem_engine_class h](j)}(h``engine_class``h]j)}(hj'h]h engine_class}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj!ubj()}(hhh]h)}(h0Engine class from enum drm_i915_gem_engine_classh]h0Engine class from enum drm_i915_gem_engine_class}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hKhj=ubah}(h]h ]h"]h$]h&]uh1j'hj!ubeh}(h]h ]h"]h$]h&]uh1jhj<hKhjubj)}(h$``engine_instance`` Engine instance.h](j)}(h``engine_instance``h]j)}(hj`h]hengine_instance}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjZubj()}(hhh]h)}(hEngine instance.h]hEngine instance.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjvubah}(h]h ]h"]h$]h&]uh1j'hjZubeh}(h]h ]h"]h$]h&]uh1jhjuhKhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hX@There may be more than one engine fulfilling any role within the system. Each engine of a class is given a unique instance number and therefore any engine can be specified by its class:instance tuplet. APIs that allow access to any engine in the system will use struct i915_engine_class_instance for this identification.h]hX@There may be more than one engine fulfilling any role within the system. Each engine of a class is given a unique instance number and therefore any engine can be specified by its class:instance tuplet. APIs that allow access to any engine in the system will use struct i915_engine_class_instance for this identification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhubh)}(hL.. _perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915:h]h}(h]h ]h"]h$]h&]hFperf-events-exposed-by-i915-through-sys-bus-event-sources-drivers-i915uh1hhKhhhhhNubh)}(hK**perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915**h]h)}(hjh]hGperf_events exposed by i915 through /sys/bus/event_sources/drivers/i915}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]jah ]h"]Gperf_events exposed by i915 through /sys/bus/event_sources/drivers/i915ah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhhhhj}jjsj }jjsubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_getparam (C struct)c.drm_i915_getparamhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_getparamh]j)}(hstruct drm_i915_getparamh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_i915_getparamh]j)}(hjh]hdrm_i915_getparam}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h!Driver parameter query structure.h]h!Driver parameter query structure.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2hjFhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjajLjajMjNjOuh1jhhhhhNhNubjQ)}(hXN**Definition**:: struct drm_i915_getparam { __s32 param; int __user *value; }; **Members** ``param`` Driver parameter to query. ``value`` Address of memory where queried value should be put. WARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjiubh:}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM6hjeubjt)}(hEstruct drm_i915_getparam { __s32 param; int __user *value; };h]hEstruct drm_i915_getparam { __s32 param; int __user *value; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM8hjeubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM=hjeubj )}(hhh](j)}(h%``param`` Driver parameter to query. h](j)}(h ``param``h]j)}(hjh]hparam}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM6hjubj()}(hhh]h)}(hDriver parameter to query.h]hDriver parameter to query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM6hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM6hjubj)}(h``value`` Address of memory where queried value should be put. WARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h](j)}(h ``value``h]j)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM<hjubj()}(hhh](h)}(h4Address of memory where queried value should be put.h]h4Address of memory where queried value should be put.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM:hj ubh)}(hrWARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don't repeat this mistake.h]htWARNING: Using pointers instead of fixed-size u64 means we need to write compat32 code. Don’t repeat this mistake.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM<hj ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hM<hjubeh}(h]h ]h"]h$]h&]uh1j hjeubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_getparam_t (C type)c.drm_i915_getparam_thNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_getparam_th]j)}(htype drm_i915_getparam_th](j)}(htypeh]htype}(hjW hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjS hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMCubj)}(h h]h }(hjf hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjS hhhje hMCubj)}(hdrm_i915_getparam_th]j)}(hjQ h]hdrm_i915_getparam_t}(hjx hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjt ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjS hhhje hMCubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjO hhhje hMCubah}(h]jJ ah ](j j!eh"]h$]h&]j%j&)j'huh1jhje hMChjL hhubj))}(hhh]h)}(h?Driver parameter query structure. See struct drm_i915_getparam.h]h?Driver parameter query structure. See struct drm_i915_getparam.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMBhj hhubah}(h]h ]h"]h$]h&]uh1j(hjL hhhje hMCubeh}(h]h ](jEtypeeh"]h$]h&]jJjEjKj jLj jMjNjOuh1jhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_i915_gem_mmap_offset (C struct)c.drm_i915_gem_mmap_offsethNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_mmap_offseth]j)}(hstruct drm_i915_gem_mmap_offseth](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMGubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMGubj)}(hdrm_i915_gem_mmap_offseth]j)}(hj h]hdrm_i915_gem_mmap_offset}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj hhhj hMGubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hMGubah}(h]j ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj hMGhj hhubj))}(hhh]h)}(h5Retrieve an offset so we can mmap this buffer object.h]h5Retrieve an offset so we can mmap this buffer object.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1j(hj hhhj hMGubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj) jLj) jMjNjOuh1jhhhhhNhNubjQ)}(hXh**Definition**:: struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; }; **Members** ``handle`` Handle for the object being mapped. ``pad`` Must be zero ``offset`` The fake offset to use for subsequent mmap call This is a fixed-size type for 32/64 compatibility. ``flags`` Flags for extended behaviour. It is mandatory that one of the `MMAP_OFFSET` types should be included: - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid. As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise. ``extensions`` Zero-terminated chain of extensions. No current extensions defined; mbz.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1 ubh:}(hj1 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj- ubjt)}(hX-struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; };h]hX-struct drm_i915_gem_mmap_offset { __u32 handle; __u32 pad; __u64 offset; __u64 flags; #define I915_MMAP_OFFSET_GTT 0; #define I915_MMAP_OFFSET_WC 1; #define I915_MMAP_OFFSET_WB 2; #define I915_MMAP_OFFSET_UC 3; #define I915_MMAP_OFFSET_FIXED 4; __u64 extensions; };}hjN sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj- ubh)}(h **Members**h]h)}(hj_ h]hMembers}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj] ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj- ubj )}(hhh](j)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]j)}(hj~ h]hhandle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj| ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjx ubj()}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j'hjx ubeh}(h]h ]h"]h$]h&]uh1jhj hMhju ubj)}(h``pad`` Must be zero h](j)}(h``pad``h]j)}(hj h]hpad}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubj()}(hhh]h)}(h Must be zeroh]h Must be zero}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhju ubj)}(ho``offset`` The fake offset to use for subsequent mmap call This is a fixed-size type for 32/64 compatibility. h](j)}(h ``offset``h]j)}(hj h]hoffset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubj()}(hhh](h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubh)}(h2This is a fixed-size type for 32/64 compatibility.h]h2This is a fixed-size type for 32/64 compatibility.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhju ubj)}(hX``flags`` Flags for extended behaviour. It is mandatory that one of the `MMAP_OFFSET` types should be included: - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid. As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise. h](j)}(h ``flags``h]j)}(hj8 h]hflags}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6 ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj2 ubj()}(hhh](h)}(hFlags for extended behaviour.h]hFlags for extended behaviour.}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjN ubh)}(hGIt is mandatory that one of the `MMAP_OFFSET` types should be included:h](h It is mandatory that one of the }(hj` hhhNhNubhtitle_reference)}(h `MMAP_OFFSET`h]h MMAP_OFFSET}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj` ubh types should be included:}(hj` hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjN ubh bullet_list)}(hhh](h list_item)}(hO`I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)h]h)}(hj h](ji )}(h`I915_MMAP_OFFSET_GTT`h]hI915_MMAP_OFFSET_GTT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj ubh9: Use mmap with the object bound to GTT. (Write-Combined)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(h2`I915_MMAP_OFFSET_WC`: Use Write-Combined caching.h]h)}(hj h](ji )}(h`I915_MMAP_OFFSET_WC`h]hI915_MMAP_OFFSET_WC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj ubh: Use Write-Combined caching.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(h.`I915_MMAP_OFFSET_WB`: Use Write-Back caching.h]h)}(hj h](ji )}(h`I915_MMAP_OFFSET_WB`h]hI915_MMAP_OFFSET_WB}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj ubh: Use Write-Back caching.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hE`I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. h]h)}(hD`I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.h](ji )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj ubh,: Use object placement to determine caching.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]bullet-uh1j hj hMhjN ubh)}(hOn devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid type. On devices without local memory, this caching mode is invalid.h](hOn devices with local memory }(hj+ hhhNhNubji )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj+ ubhW is the only valid type. On devices without local memory, this caching mode is invalid.}(hj+ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjN ubh)}(hAs caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise.h](h As caching mode when specifying }(hjL hhhNhNubji )}(h`I915_MMAP_OFFSET_FIXED`h]hI915_MMAP_OFFSET_FIXED}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjL ubh, WC or WB will be used, depending on the object placement on creation. WB will be used when the object can only exist in system memory, WC otherwise.}(hjL hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjN ubeh}(h]h ]h"]h$]h&]uh1j'hj2 ubeh}(h]h ]h"]h$]h&]uh1jhjM hMhju ubj)}(hX``extensions`` Zero-terminated chain of extensions. No current extensions defined; mbz.h](j)}(h``extensions``h]j)}(hj h]h extensions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj} ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjy ubj()}(hhh](h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubh)}(h#No current extensions defined; mbz.h]h#No current extensions defined; mbz.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubeh}(h]h ]h"]h$]h&]uh1j'hjy ubeh}(h]h ]h"]h$]h&]uh1jhj hMhju ubeh}(h]h ]h"]h$]h&]uh1j hj- ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM"hhhhubh)}(hThis struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, and is used to retrieve the fake offset to mmap an object specified by :c:type:`handle`.h](h)This struct is passed as argument to the }(hj hhhNhNubji )}(h `DRM_IOCTL_I915_GEM_MMAP_OFFSET`h]hDRM_IOCTL_I915_GEM_MMAP_OFFSET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj ubhO ioctl, and is used to retrieve the fake offset to mmap an object specified by }(hj hhhNhNubh)}(h:c:type:`handle`h]j)}(hj h]hhandle}(hj hhhNhNubah}(h]h ](xrefjEc-typeeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocgpu/driver-uapi refdomainjEreftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sb reftargethandleuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj+ hMhhhhubh)}(hThe legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave as setting the :c:type:`extensions` to 0, and :c:type:`flags` to `I915_MMAP_OFFSET_GTT`.h](hThe legacy way of using }(hj6 hhhNhNubji )}(h`DRM_IOCTL_I915_GEM_MMAP`h]hDRM_IOCTL_I915_GEM_MMAP}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj6 ubh is removed on gen12+. }(hj6 hhhNhNubji )}(h`DRM_IOCTL_I915_GEM_MMAP_GTT`h]hDRM_IOCTL_I915_GEM_MMAP_GTT}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj6 ubhL is an older supported alias to this struct, but will behave as setting the }(hj6 hhhNhNubh)}(h:c:type:`extensions`h]j)}(hjd h]h extensions}(hjf hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjb ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) extensionsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj6 ubh to 0, and }(hj6 hhhNhNubh)}(h:c:type:`flags`h]j)}(hj h]hflags}(hj hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) flagsuh1hhj hMhj6 ubh to }(hj6 hhhNhNubji )}(h`I915_MMAP_OFFSET_GTT`h]hI915_MMAP_OFFSET_GTT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj6 ubh.}(hj6 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj hMhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_set_domain (C struct)c.drm_i915_gem_set_domainhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_set_domainh]j)}(hstruct drm_i915_gem_set_domainh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMubj)}(hdrm_i915_gem_set_domainh]j)}(hj h]hdrm_i915_gem_set_domain}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hMubah}(h]j ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj hMhj hhubj))}(hhh]h)}(hdAdjust the objects write or read domain, in preparation for accessing the pages via some CPU domain.h]hdAdjust the objects write or read domain, in preparation for accessing the pages via some CPU domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM$hjhhubah}(h]h ]h"]h$]h&]uh1j(hj hhhj hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj4jLj4jMjNjOuh1jhhhhhNhNubjQ)}(hXo**Definition**:: struct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; }; **Members** ``handle`` Handle for the object. ``read_domains`` New read domains. ``write_domain`` New write domain. Note that having something in the write domain implies it's in the read domain, and only that read domain.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubh:}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM(hj8ubjt)}(hestruct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; };h]hestruct drm_i915_gem_set_domain { __u32 handle; __u32 read_domains; __u32 write_domain; };}hjYsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM*hj8ubh)}(h **Members**h]h)}(hjjh]hMembers}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM0hj8ubj )}(hhh](j)}(h"``handle`` Handle for the object. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMKhjubj()}(hhh]h)}(hHandle for the object.h]hHandle for the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMKhjubj)}(h#``read_domains`` New read domains. h](j)}(h``read_domains``h]j)}(hjh]h read_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMNhjubj()}(hhh]h)}(hNew read domains.h]hNew read domains.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMNhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMNhjubj)}(h``write_domain`` New write domain. Note that having something in the write domain implies it's in the read domain, and only that read domain.h](j)}(h``write_domain``h]j)}(hjh]h write_domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMThjubj()}(hhh](h)}(hNew write domain.h]hNew write domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMRhjubh)}(hjNote that having something in the write domain implies it's in the read domain, and only that read domain.h]hlNote that having something in the write domain implies it’s in the read domain, and only that read domain.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMThjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMThjubeh}(h]h ]h"]h$]h&]uh1j hj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjLh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMXhhhhubh)}(hSpecifying a new write or read domain will flush the object out of the previous domain(if required), before then updating the objects domain tracking with the new domain.h]hSpecifying a new write or read domain will flush the object out of the previous domain(if required), before then updating the objects domain tracking with the new domain.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM%hhhhubh)}(hVNote this might involve waiting for the object first if it is still active on the GPU.h]hVNote this might involve waiting for the object first if it is still active on the GPU.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM)hhhhubh)}(h;Supported values for **read_domains** and **write_domain**:h](hSupported values for }(hjhhhNhNubh)}(h**read_domains**h]h read_domains}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh and }(hjhhhNhNubh)}(h**write_domain**h]h write_domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM,hhhhubh block_quote)}(h- I915_GEM_DOMAIN_WC: Uncached write-combined domain - I915_GEM_DOMAIN_CPU: CPU cache domain - I915_GEM_DOMAIN_GTT: Mappable aperture domain h]j )}(hhh](j )}(h2I915_GEM_DOMAIN_WC: Uncached write-combined domainh]h)}(hjh]h2I915_GEM_DOMAIN_WC: Uncached write-combined domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM.hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h%I915_GEM_DOMAIN_CPU: CPU cache domainh]h)}(hjh]h%I915_GEM_DOMAIN_CPU: CPU cache domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM/hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h.I915_GEM_DOMAIN_GTT: Mappable aperture domain h]h)}(h-I915_GEM_DOMAIN_GTT: Mappable aperture domainh]h-I915_GEM_DOMAIN_GTT: Mappable aperture domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM0hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhM.hjubah}(h]h ]h"]h$]h&]uh1jhjhM.hhhhubh)}(hAll other domains are rejected.h]hAll other domains are rejected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2hhhhubh)}(hXINote that for discrete, starting from DG1, this is no longer supported, and is instead rejected. On such platforms the CPU domain is effectively static, where we also only support a single :c:type:`drm_i915_gem_mmap_offset` cache mode, which can't be set explicitly and instead depends on the object placements, as per the below.h](hNote that for discrete, starting from DG1, this is no longer supported, and is instead rejected. On such platforms the CPU domain is effectively static, where we also only support a single }(hj hhhNhNubh)}(h":c:type:`drm_i915_gem_mmap_offset`h]j)}(hj*h]hdrm_i915_gem_mmap_offset}(hj,hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_gem_mmap_offsetuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM4hj ubhl cache mode, which can’t be set explicitly and instead depends on the object placements, as per the below.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjGhM4hhhhubh)}(h*Implicit caching rules, starting from DG1:h]h*Implicit caching rules, starting from DG1:}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM:hhhhubj)}(hXH- If any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. - Everything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]j )}(hhh](j )}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. h]h)}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.h](h%If any of the object placements (see }(hjlhhhNhNubh)}(h0:c:type:`drm_i915_gem_create_ext_memory_regions`h]j)}(hjvh]h&drm_i915_gem_create_ext_memory_regions}(hjxhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) &drm_i915_gem_create_ext_memory_regionsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM<hjlubhg) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM<hjhubah}(h]h ]h"]h$]h&]uh1j hjeubj )}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]h)}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.h]hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM@hjubah}(h]h ]h"]h$]h&]uh1j hjeubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhM<hjaubah}(h]h ]h"]h$]h&]uh1jhjhM<hhhhubh)}(hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new :c:type:`drm_i915_gem_create_ext` extension is probable.h](hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new }(hjhhhNhNubh)}(h!:c:type:`drm_i915_gem_create_ext`h]j)}(hjh]hdrm_i915_gem_create_ext}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_gem_create_extuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMChjubh extension is probable.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMChhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_exec_fence (C struct)c.drm_i915_gem_exec_fencehNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_exec_fenceh]j)}(hstruct drm_i915_gem_exec_fenceh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMJubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj!hMJubj)}(hdrm_i915_gem_exec_fenceh]j)}(hjh]hdrm_i915_gem_exec_fence}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhj!hMJubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj!hMJubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj!hMJhj hhubj))}(hhh]h)}(h/An input or output fence for the execbuf ioctl.h]h/An input or output fence for the execbuf ioctl.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM'hjShhubah}(h]h ]h"]h$]h&]uh1j(hj hhhj!hMJubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjnjLjnjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); }; **Members** ``handle`` User's handle for a drm_syncobj to wait on or signal. ``flags`` Supported flags are: I915_EXEC_FENCE_WAIT: Wait for the input fence before request submission. I915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvubh:}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM+hjrubjt)}(hstruct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); };h]hstruct drm_i915_gem_exec_fence { __u32 handle; __u32 flags; #define I915_EXEC_FENCE_WAIT (1<<0); #define I915_EXEC_FENCE_SIGNAL (1<<1); #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)); };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM-hjrubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5hjrubj )}(hhh](j)}(hA``handle`` User's handle for a drm_syncobj to wait on or signal. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM1hjubj()}(hhh]h)}(h5User's handle for a drm_syncobj to wait on or signal.h]h7User’s handle for a drm_syncobj to wait on or signal.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM1hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM1hjubj)}(h``flags`` Supported flags are: I915_EXEC_FENCE_WAIT: Wait for the input fence before request submission. I915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM:hjubj()}(hhh](h)}(hSupported flags are:h]hSupported flags are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5hjubh)}(hII915_EXEC_FENCE_WAIT: Wait for the input fence before request submission.h]hII915_EXEC_FENCE_WAIT: Wait for the input fence before request submission.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7hjubh)}(hAI915_EXEC_FENCE_SIGNAL: Return request completion fence as outputh]hAI915_EXEC_FENCE_SIGNAL: Return request completion fence as output}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM:hjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM:hjubeh}(h]h ]h"]h$]h&]uh1j hjrubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj\h]h Description}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM>hhhhubh)}(hBThe request will wait for input fence to signal before submission.h]hBThe request will wait for input fence to signal before submission.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM(hhhhubh)}(hOThe returned output fence will be signaled after the completion of the request.h]hOThe returned output fence will be signaled after the completion of the request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM*hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j6drm_i915_gem_execbuffer_ext_timeline_fences (C struct)-c.drm_i915_gem_execbuffer_ext_timeline_fenceshNtauh1jhhhhhNhNubj)}(hhh](j)}(h+drm_i915_gem_execbuffer_ext_timeline_fencesh]j)}(h2struct drm_i915_gem_execbuffer_ext_timeline_fencesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM0ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM0ubj)}(h+drm_i915_gem_execbuffer_ext_timeline_fencesh]j)}(hjh]h+drm_i915_gem_execbuffer_ext_timeline_fences}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhM0ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM0ubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM0hjhhubj))}(hhh]h)}(h"Timeline fences for execbuf ioctl.h]h"Timeline fences for execbuf ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMChjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhM0ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``fence_count`` Number of elements in the **handles_ptr** & **value_ptr** arrays. ``handles_ptr`` Pointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**. ``values_ptr`` Pointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMGhjubjt)}(hstruct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; };h]hstruct drm_i915_gem_execbuffer_ext_timeline_fences { #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0; struct i915_user_extension base; __u64 fence_count; __u64 handles_ptr; __u64 values_ptr; };}hj(sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMIhjubh)}(h **Members**h]h)}(hj9h]hMembers}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMQhjubj )}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]j)}(hjXh]hbase}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMMhjRubj()}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhMMhjnubah}(h]h ]h"]h$]h&]uh1j'hjRubeh}(h]h ]h"]h$]h&]uh1jhjmhMMhjOubj)}(hR``fence_count`` Number of elements in the **handles_ptr** & **value_ptr** arrays. h](j)}(h``fence_count``h]j)}(hjh]h fence_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMRhjubj()}(hhh]h)}(hANumber of elements in the **handles_ptr** & **value_ptr** arrays.h](hNumber of elements in the }(hjhhhNhNubh)}(h**handles_ptr**h]h handles_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh & }(hjhhhNhNubh)}(h **value_ptr**h]h value_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh arrays.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMQhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMRhjOubj)}(ha``handles_ptr`` Pointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**. h](j)}(h``handles_ptr``h]j)}(hjh]h handles_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMXhjubj()}(hhh]h)}(hPPointer to an array of struct drm_i915_gem_exec_fence of length **fence_count**.h](h@Pointer to an array of struct drm_i915_gem_exec_fence of length }(hjhhhNhNubh)}(h**fence_count**h]h fence_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMWhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMXhjOubj)}(h``values_ptr`` Pointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](j)}(h``values_ptr``h]j)}(hj;h]h values_ptr}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM`hj5ubj()}(hhh]h)}(hPointer to an array of u64 values of length **fence_count**. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.h](h,Pointer to an array of u64 values of length }(hjThhhNhNubh)}(h**fence_count**h]h fence_count}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubh. Values must be 0 for a binary drm_syncobj. A Value of 0 for a timeline drm_syncobj is invalid as it turns a drm_syncobj into a binary one.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM]hjQubah}(h]h ]h"]h$]h&]uh1j'hj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhM`hjOubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMdhhhhubh)}(hThis structure describes an array of drm_syncobj and associated points for timeline variants of drm_syncobj. It is invalid to append this structure to the execbuf if I915_EXEC_FENCE_ARRAY is set.h]hThis structure describes an array of drm_syncobj and associated points for timeline variants of drm_syncobj. It is invalid to append this structure to the execbuf if I915_EXEC_FENCE_ARRAY is set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMDhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_i915_gem_execbuffer2 (C struct)c.drm_i915_gem_execbuffer2hNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_execbuffer2h]j)}(hstruct drm_i915_gem_execbuffer2h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMKubj)}(hdrm_i915_gem_execbuffer2h]j)}(hjh]hdrm_i915_gem_execbuffer2}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMKubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMKhjhhubj))}(hhh]h)}(h-Structure for DRM_I915_GEM_EXECBUFFER2 ioctl.h]h-Structure for DRM_I915_GEM_EXECBUFFER2 ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMfhj hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMKubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj(jLj(jMjNjOuh1jhhhhhNhNubjQ)}(hX **Definition**:: struct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; }; **Members** ``buffers_ptr`` Pointer to a list of gem_exec_object2 structs ``buffer_count`` Number of elements in **buffers_ptr** array ``batch_start_offset`` Offset in the batchbuffer to start execution from. ``batch_len`` Length in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size. ``DR1`` deprecated ``DR4`` deprecated ``num_cliprects`` See **cliprects_ptr** ``cliprects_ptr`` Kernel clipping was a DRI1 misfeature. It is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set. If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array. If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0. ``flags`` Execbuf flags ``rsvd1`` Context id ``rsvd2`` in and out sync_file file descriptors. When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input). When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubh:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMjhj,ubjt)}(hXstruct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; };h]hXstruct drm_i915_gem_execbuffer2 { __u64 buffers_ptr; __u32 buffer_count; __u32 batch_start_offset; __u32 batch_len; __u32 DR1; __u32 DR4; __u32 num_cliprects; __u64 cliprects_ptr; __u64 flags; #define I915_EXEC_RING_MASK (0x3f); #define I915_EXEC_DEFAULT (0<<0); #define I915_EXEC_RENDER (1<<0); #define I915_EXEC_BSD (2<<0); #define I915_EXEC_BLT (3<<0); #define I915_EXEC_VEBOX (4<<0); #define I915_EXEC_CONSTANTS_MASK (3<<6); #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) ; #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6); #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) ; #define I915_EXEC_GEN7_SOL_RESET (1<<8); #define I915_EXEC_SECURE (1<<9); #define I915_EXEC_IS_PINNED (1<<10); #define I915_EXEC_NO_RELOC (1<<11); #define I915_EXEC_HANDLE_LUT (1<<12); #define I915_EXEC_BSD_SHIFT (13); #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT); #define I915_EXEC_RESOURCE_STREAMER (1<<15); #define I915_EXEC_FENCE_IN (1<<16); #define I915_EXEC_FENCE_OUT (1<<17); #define I915_EXEC_BATCH_FIRST (1<<18); #define I915_EXEC_FENCE_ARRAY (1<<19); #define I915_EXEC_FENCE_SUBMIT (1 << 20); #define I915_EXEC_USE_EXTENSIONS (1 << 21); #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)); __u64 rsvd1; __u64 rsvd2; };}hjMsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMlhj,ubh)}(h **Members**h]h)}(hj^h]hMembers}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj,ubj )}(hhh](j)}(h>``buffers_ptr`` Pointer to a list of gem_exec_object2 structs h](j)}(h``buffers_ptr``h]j)}(hj}h]h buffers_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMkhjwubj()}(hhh]h)}(h-Pointer to a list of gem_exec_object2 structsh]h-Pointer to a list of gem_exec_object2 structs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMkhjubah}(h]h ]h"]h$]h&]uh1j'hjwubeh}(h]h ]h"]h$]h&]uh1jhjhMkhjtubj)}(h=``buffer_count`` Number of elements in **buffers_ptr** array h](j)}(h``buffer_count``h]j)}(hjh]h buffer_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMnhjubj()}(hhh]h)}(h+Number of elements in **buffers_ptr** arrayh](hNumber of elements in }(hjhhhNhNubh)}(h**buffers_ptr**h]h buffers_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh array}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMnhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMnhjtubj)}(hJ``batch_start_offset`` Offset in the batchbuffer to start execution from. h](j)}(h``batch_start_offset``h]j)}(hjh]hbatch_start_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMshjubj()}(hhh]h)}(h2Offset in the batchbuffer to start execution from.h]h2Offset in the batchbuffer to start execution from.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMrhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMshjtubj)}(h``batch_len`` Length in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size. h](j)}(h ``batch_len``h]j)}(hj;h]h batch_len}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMzhj5ubj()}(hhh]h)}(hLength in bytes of the batch buffer, starting from the **batch_start_offset**. If 0, length is assumed to be the batch buffer object size.h](h7Length in bytes of the batch buffer, starting from the }(hjThhhNhNubh)}(h**batch_start_offset**h]hbatch_start_offset}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTubh=. If 0, length is assumed to be the batch buffer object size.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMxhjQubah}(h]h ]h"]h$]h&]uh1j'hj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhMzhjtubj)}(h``DR1`` deprecated h](j)}(h``DR1``h]j)}(hjh]hDR1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM~hjubj()}(hhh]h)}(h deprecatedh]h deprecated}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM~hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM~hjtubj)}(h``DR4`` deprecated h](j)}(h``DR4``h]j)}(hjh]hDR4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj()}(hhh]h)}(h deprecatedh]h deprecated}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(h(``num_cliprects`` See **cliprects_ptr** h](j)}(h``num_cliprects``h]j)}(hjh]h num_cliprects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj()}(hhh]h)}(hSee **cliprects_ptr**h](hSee }(hjhhhNhNubh)}(h**cliprects_ptr**h]h cliprects_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(hX``cliprects_ptr`` Kernel clipping was a DRI1 misfeature. It is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set. If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array. If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0. h](j)}(h``cliprects_ptr``h]j)}(hj@h]h cliprects_ptr}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj:ubj()}(hhh](h)}(h&Kernel clipping was a DRI1 misfeature.h]h&Kernel clipping was a DRI1 misfeature.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjVubh)}(hgIt is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set.h]hgIt is invalid to use this field if I915_EXEC_FENCE_ARRAY or I915_EXEC_USE_EXTENSIONS flags are not set.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjVubh)}(hIf I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of :c:type:`drm_i915_gem_exec_fence` and **num_cliprects** is the length of the array.h](hGIf I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array of }(hjwhhhNhNubh)}(h!:c:type:`drm_i915_gem_exec_fence`h]j)}(hjh]hdrm_i915_gem_exec_fence}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_gem_exec_fenceuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjwubh and }(hjwhhhNhNubh)}(h**num_cliprects**h]h num_cliprects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwubh is the length of the array.}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjVubh)}(h|If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single :c:type:`i915_user_extension` and num_cliprects is 0.h](hGIf I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a single }(hjhhhNhNubh)}(h:c:type:`i915_user_extension`h]j)}(hjh]hi915_user_extension}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) i915_user_extensionuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh and num_cliprects is 0.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjVubeh}(h]h ]h"]h$]h&]uh1j'hj:ubeh}(h]h ]h"]h$]h&]uh1jhjUhMhjtubj)}(h``flags`` Execbuf flags h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj()}(hhh]h)}(h Execbuf flagsh]h Execbuf flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(h``rsvd1`` Context id h](j)}(h ``rsvd1``h]j)}(hj8h]hrsvd1}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj2ubj()}(hhh]h)}(h Context idh]h Context id}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhMhjNubah}(h]h ]h"]h$]h&]uh1j'hj2ubeh}(h]h ]h"]h$]h&]uh1jhjMhMhjtubj)}(hX'``rsvd2`` in and out sync_file file descriptors. When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input). When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h](j)}(h ``rsvd2``h]j)}(hjqh]hrsvd2}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjkubj()}(hhh](h)}(h&in and out sync_file file descriptors.h]h&in and out sync_file file descriptors.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hWhen I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input).h]hWhen I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the lower 32 bits of this field will have the in sync_file fd (input).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hnWhen I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).h]hnWhen I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this field will have the out sync_file fd (output).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjkubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubeh}(h]h ]h"]h$]h&]uh1j hj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_gem_caching (C struct)c.drm_i915_gem_cachinghNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_cachingh]j)}(hstruct drm_i915_gem_cachingh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM!ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM!ubj)}(hdrm_i915_gem_cachingh]j)}(hjh]hdrm_i915_gem_caching}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhM!ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM!ubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM!hjhhubj))}(hhh]h)}(h/Set or get the caching for given object handle.h]h/Set or get the caching for given object handle.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMlhj'hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhM!ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjBjLjBjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; }; **Members** ``handle`` Handle of the buffer to set/get the caching level. ``caching`` The GTT caching level to apply or possible return value. The supported **caching** values: I915_CACHING_NONE: GPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent. I915_CACHING_CACHED: GPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT. I915_CACHING_DISPLAY: Special GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubh:}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMphjFubjt)}(hstruct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; };h]hstruct drm_i915_gem_caching { __u32 handle; #define I915_CACHING_NONE 0; #define I915_CACHING_CACHED 1; #define I915_CACHING_DISPLAY 2; __u32 caching; };}hjgsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMrhjFubh)}(h **Members**h]h)}(hjxh]hMembers}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMzhjFubj )}(hhh](j)}(h>``handle`` Handle of the buffer to set/get the caching level. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj()}(hhh]h)}(h2Handle of the buffer to set/get the caching level.h]h2Handle of the buffer to set/get the caching level.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hXm``caching`` The GTT caching level to apply or possible return value. The supported **caching** values: I915_CACHING_NONE: GPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent. I915_CACHING_CACHED: GPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT. I915_CACHING_DISPLAY: Special GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h](j)}(h ``caching``h]j)}(hjh]hcaching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj()}(hhh](h)}(h8The GTT caching level to apply or possible return value.h]h8The GTT caching level to apply or possible return value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h!The supported **caching** values:h](hThe supported }(hjhhhNhNubh)}(h **caching**h]hcaching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh values:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CACHING_NONE:h]hI915_CACHING_NONE:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hGPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent.h]hGPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CACHING_CACHED:h]hI915_CACHING_CACHED:}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hGPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT.h]hGPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CACHING_DISPLAY:h]hI915_CACHING_DISPLAY:}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hXSpecial GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.h]hXSpecial GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjFubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hX?Allow userspace to control the GTT caching bits for a given object when the object is later mapped through the ppGTT(or GGTT on older platforms lacking ppGTT support, or if the object is used for scanout). Note that this might require unbinding the object from the GTT first, if its current caching value doesn't match.h]hXAAllow userspace to control the GTT caching bits for a given object when the object is later mapped through the ppGTT(or GGTT on older platforms lacking ppGTT support, or if the object is used for scanout). Note that this might require unbinding the object from the GTT first, if its current caching value doesn’t match.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMmhhhhubh)}(hXNote that this all changes on discrete platforms, starting from DG1, the set/get caching is no longer supported, and is now rejected. Instead the CPU caching attributes(WB vs WC) will become an immutable creation time property for the object, along with the GTT caching level. For now we don't expose any new uAPI for this, instead on DG1 this is all implicit, although this largely shouldn't matter since DG1 is coherent by default(without any way of controlling it).h]hXNote that this all changes on discrete platforms, starting from DG1, the set/get caching is no longer supported, and is now rejected. Instead the CPU caching attributes(WB vs WC) will become an immutable creation time property for the object, along with the GTT caching level. For now we don’t expose any new uAPI for this, instead on DG1 this is all implicit, although this largely shouldn’t matter since DG1 is coherent by default(without any way of controlling it).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMshhhhubh)}(h*Implicit caching rules, starting from DG1:h]h*Implicit caching rules, starting from DG1:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM{hhhhubj)}(hXH- If any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. - Everything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]j )}(hhh](j )}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only. h]h)}(hIf any of the object placements (see :c:type:`drm_i915_gem_create_ext_memory_regions`) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.h](h%If any of the object placements (see }(hjhhhNhNubh)}(h0:c:type:`drm_i915_gem_create_ext_memory_regions`h]j)}(hjh]h&drm_i915_gem_create_ext_memory_regions}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) &drm_i915_gem_create_ext_memory_regionsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM}hjubhg) contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and mapped as write-combined only.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM}hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU. h]h)}(hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.h]hEverything else is always allocated and mapped as write-back, with the guarantee that everything is also coherent with the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhM}hjubah}(h]h ]h"]h$]h&]uh1jhjhM}hhhhubh)}(hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new :c:type:`drm_i915_gem_create_ext` extension is probable.h](hNote that this is likely to change in the future again, where we might need more flexibility on future devices, so making this all explicit as part of a new }(hj9hhhNhNubh)}(h!:c:type:`drm_i915_gem_create_ext`h]j)}(hjCh]hdrm_i915_gem_create_ext}(hjEhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_gem_create_extuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj9ubh extension is probable.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj`hMhhhhubh)}(hXSide note: Part of the reason for this is that changing the at-allocation-time CPU caching attributes for the pages might be required(and is expensive) if we need to then CPU map the pages later with different caching attributes. This inconsistent caching behaviour, while supported on x86, is not universally supported on other architectures. So for simplicity we opt for setting everything at creation time, whilst also making it immutable, on discrete platforms.h]hXSide note: Part of the reason for this is that changing the at-allocation-time CPU caching attributes for the pages might be required(and is expensive) if we need to then CPU map the pages later with different caching attributes. This inconsistent caching behaviour, while supported on x86, is not universally supported on other architectures. So for simplicity we opt for setting everything at creation time, whilst also making it immutable, on discrete platforms.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*drm_i915_gem_context_create_ext (C struct)!c.drm_i915_gem_context_create_exthNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_context_create_exth]j)}(h&struct drm_i915_gem_context_create_exth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_i915_gem_context_create_exth]j)}(hjh]hdrm_i915_gem_context_create_ext}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h Structure for creating contexts.h]h Structure for creating contexts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; }; **Members** ``ctx_id`` Id of the created context (output) ``flags`` Supported flags are: I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS: Extensions may be appended to this structure and driver must check for those. See **extensions**. I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE Created context will have single timeline. ``extensions`` Zero-terminated chain of extensions. I915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam. I915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubjt)}(hXstruct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; };h]hXstruct drm_i915_gem_context_create_ext { __u32 ctx_id; __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0); #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1); #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)); __u64 extensions; #define I915_CONTEXT_CREATE_EXT_SETPARAM 0; #define I915_CONTEXT_CREATE_EXT_CLONE 1; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h **Members**h]h)}(hj#h]hMembers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj )}(hhh](j)}(h.``ctx_id`` Id of the created context (output) h](j)}(h ``ctx_id``h]j)}(hjBh]hctx_id}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj<ubj()}(hhh]h)}(h"Id of the created context (output)h]h"Id of the created context (output)}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhMhjXubah}(h]h ]h"]h$]h&]uh1j'hj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhMhj9ubj)}(hX``flags`` Supported flags are: I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS: Extensions may be appended to this structure and driver must check for those. See **extensions**. I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE Created context will have single timeline. h](j)}(h ``flags``h]j)}(hj{h]hflags}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjuubj()}(hhh](h)}(hSupported flags are:h]hSupported flags are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h)I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS:h]h)I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(haExtensions may be appended to this structure and driver must check for those. See **extensions**.h](hRExtensions may be appended to this structure and driver must check for those. See }(hjhhhNhNubh)}(h**extensions**h]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h)I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINEh]h)I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h*Created context will have single timeline.h]h*Created context will have single timeline.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjuubeh}(h]h ]h"]h$]h&]uh1jhjhMhj9ubj)}(hXh``extensions`` Zero-terminated chain of extensions. I915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam. I915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj()}(hhh](h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam.h]hI915_CONTEXT_CREATE_EXT_SETPARAM: Context parameter to set or query during context creation. See struct drm_i915_gem_context_create_ext_setparam.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(hI915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.h]hI915_CONTEXT_CREATE_EXT_CLONE: This extension has been removed. On the off chance someone somewhere has attempted to use it, never re-use this extension number.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj9ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_i915_gem_context_param (C struct)c.drm_i915_gem_context_paramhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_context_paramh]j)}(h!struct drm_i915_gem_context_paramh](j)}(hjh]hstruct}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhhjhMubj)}(hdrm_i915_gem_context_paramh]j)}(hjth]hdrm_i915_gem_context_param}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjvhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjrhhhjhMubah}(h]jmah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjohhubj))}(hhh]h)}(h"Context parameter to set or query.h]h"Context parameter to set or query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjohhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; }; **Members** ``ctx_id`` Context id ``size`` Size of the parameter **value** ``param`` Parameter to set or query ``value`` Context parameter value to be set or queriedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubjt)}(hXstruct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; };h]hXstruct drm_i915_gem_context_param { __u32 ctx_id; __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1; #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2; #define I915_CONTEXT_PARAM_GTT_SIZE 0x3; #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4; #define I915_CONTEXT_PARAM_BANNABLE 0x5; #define I915_CONTEXT_PARAM_PRIORITY 0x6; #define I915_CONTEXT_MAX_USER_PRIORITY 1023 ; #define I915_CONTEXT_DEFAULT_PRIORITY 0; #define I915_CONTEXT_MIN_USER_PRIORITY -1023 ; #define I915_CONTEXT_PARAM_SSEU 0x7; #define I915_CONTEXT_PARAM_RECOVERABLE 0x8; #define I915_CONTEXT_PARAM_VM 0x9; #define I915_CONTEXT_PARAM_ENGINES 0xa; #define I915_CONTEXT_PARAM_PERSISTENCE 0xb; #define I915_CONTEXT_PARAM_RINGSIZE 0xc; #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd; #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe; #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf; __u64 value; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubh)}(h **Members**h]h)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj )}(hhh](j)}(h``ctx_id`` Context id h](j)}(h ``ctx_id``h]j)}(hj)h]hctx_id}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj#ubj()}(hhh]h)}(h Context idh]h Context id}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj?ubah}(h]h ]h"]h$]h&]uh1j'hj#ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhj ubj)}(h)``size`` Size of the parameter **value** h](j)}(h``size``h]j)}(hjbh]hsize}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj\ubj()}(hhh]h)}(hSize of the parameter **value**h](hSize of the parameter }(hj{hhhNhNubh)}(h **value**h]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ubeh}(h]h ]h"]h$]h&]uh1hhjwhMhjxubah}(h]h ]h"]h$]h&]uh1j'hj\ubeh}(h]h ]h"]h$]h&]uh1jhjwhMhj ubj)}(h$``param`` Parameter to set or query h](j)}(h ``param``h]j)}(hjh]hparam}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj()}(hhh]h)}(hParameter to set or queryh]hParameter to set or query}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubj)}(h6``value`` Context parameter value to be set or queriedh](j)}(h ``value``h]j)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubj()}(hhh]h)}(h,Context parameter value to be set or queriedh]h,Context parameter value to be set or queried}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h.. _Virtual Engine uAPI:h]h}(h]h ]h"]h$]h&]hvirtual-engine-uapiuh1hhMhhhhhNubh)}(h**Virtual Engine uAPI**h]h)}(hj0h]hVirtual Engine uAPI}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.ubah}(h]j-ah ]h"]virtual engine uapiah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhj}jCj#sj }j-j#subh)}(hVirtual engine is a concept where userspace is able to configure a set of physical engines, submit a batch buffer, and let the driver execute it on any engine from the set as it sees fit.h]hVirtual engine is a concept where userspace is able to configure a set of physical engines, submit a batch buffer, and let the driver execute it on any engine from the set as it sees fit.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hThis is primarily useful on parts which have multiple instances of a same class engine, like for example GT3+ Skylake parts with their two VCS engines.h]hThis is primarily useful on parts which have multiple instances of a same class engine, like for example GT3+ Skylake parts with their two VCS engines.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXFor instance userspace can enumerate all engines of a certain class using the previously described `Engine Discovery uAPI`_. After that userspace can create a GEM context with a placeholder slot for the virtual engine (using `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class and instance respectively) and finally using the `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in the same reserved slot.h](hcFor instance userspace can enumerate all engines of a certain class using the previously described }(hjghhhNhNubh reference)}(h`Engine Discovery uAPI`_h]hEngine Discovery uAPI}(hjqhhhNhNubah}(h]h ]h"]h$]h&]nameEngine Discovery uAPIhengine-discovery-uapiuh1johjgresolvedKubhf. After that userspace can create a GEM context with a placeholder slot for the virtual engine (using }(hjghhhNhNubji )}(h`I915_ENGINE_CLASS_INVALID`h]hI915_ENGINE_CLASS_INVALID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjgubh and }(hjghhhNhNubji )}(h `I915_ENGINE_CLASS_INVALID_NONE`h]hI915_ENGINE_CLASS_INVALID_NONE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjgubh< for class and instance respectively) and finally using the }(hjghhhNhNubji )}(h'`I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE`h]h%I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjgubh< extension place a virtual engine in the same reserved slot.}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hIExample of creating a virtual engine and submitting a batch buffer to it:h]hIExample of creating a virtual engine and submitting a batch buffer to it:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubjt)}(hX(I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, .engine_index = 0, // Place this virtual engine into engine map slot 0 .num_siblings = 2, .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, { I915_ENGINE_CLASS_VIDEO, 1 }, }, }; I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { .engines = { { I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE } }, .extensions = to_user_pointer(&virtual), // Chains after load_balance extension }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // Now we have created a GEM context with its engine map containing a // single virtual engine. Submissions to this slot can go either to // vcs0 or vcs1, depending on the load balancing algorithm used inside // the driver. The load balancing is dynamic from one batch buffer to // another and transparent to userspace. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0 which is the virtual engine gem_execbuf(drm_fd, &execbuf);h]hX(I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, .engine_index = 0, // Place this virtual engine into engine map slot 0 .num_siblings = 2, .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, { I915_ENGINE_CLASS_VIDEO, 1 }, }, }; I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { .engines = { { I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE } }, .extensions = to_user_pointer(&virtual), // Chains after load_balance extension }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // Now we have created a GEM context with its engine map containing a // single virtual engine. Submissions to this slot can go either to // vcs0 or vcs1, depending on the load balancing algorithm used inside // the driver. The load balancing is dynamic from one batch buffer to // another and transparent to userspace. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0 which is the virtual engine gem_execbuf(drm_fd, &execbuf);}hjsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/i915_context_engines_parallel_submit (C struct)&c.i915_context_engines_parallel_submithNtauh1jhhhhhNhNubj)}(hhh](j)}(h$i915_context_engines_parallel_submith]j)}(h+struct i915_context_engines_parallel_submith](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj hMubj)}(h$i915_context_engines_parallel_submith]j)}(hjh]h$i915_context_engines_parallel_submit}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj hMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj hMhjhhubj))}(hhh]h)}(h)Configure engine for parallel submission.h]h)Configure engine for parallel submission.}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhML hj; hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjV jLjV jMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; }; **Members** ``base`` base user extension. ``engine_index`` slot for parallel engine ``width`` number of contexts per parallel engine or in other words the number of batches in each submission ``num_siblings`` number of siblings per context or in other words the number of possible placements for each submission ``mbz16`` reserved for future use; must be zero ``flags`` all undefined flags must be zero, currently not defined flags ``mbz64`` reserved for future use; must be zero ``engines`` 2-d array of engine instances to configure parallel engine length = width (i) * num_siblings (j) index = j + i * num_siblingsh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjb hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^ ubh:}(hj^ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMP hjZ ubjt)}(hstruct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; };h]hstruct i915_context_engines_parallel_submit { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[]; };}hj{ sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMR hjZ ubh)}(h **Members**h]h)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM] hjZ ubj )}(hhh](j)}(h``base`` base user extension. h](j)}(h``base``h]j)}(hj h]hbase}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubj()}(hhh]h)}(hbase user extension.h]hbase user extension.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM hj ubj)}(h*``engine_index`` slot for parallel engine h](j)}(h``engine_index``h]j)}(hj h]h engine_index}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj ubj()}(hhh]h)}(hslot for parallel engineh]hslot for parallel engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM hj ubj)}(hl``width`` number of contexts per parallel engine or in other words the number of batches in each submission h](j)}(h ``width``h]j)}(hj!h]hwidth}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj!ubj()}(hhh]h)}(hanumber of contexts per parallel engine or in other words the number of batches in each submissionh]hanumber of contexts per parallel engine or in other words the number of batches in each submission}(hj6!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj3!ubah}(h]h ]h"]h$]h&]uh1j'hj!ubeh}(h]h ]h"]h$]h&]uh1jhj2!hM hj ubj)}(hx``num_siblings`` number of siblings per context or in other words the number of possible placements for each submission h](j)}(h``num_siblings``h]j)}(hjW!h]h num_siblings}(hjY!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjQ!ubj()}(hhh]h)}(hfnumber of siblings per context or in other words the number of possible placements for each submissionh]hfnumber of siblings per context or in other words the number of possible placements for each submission}(hjp!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjm!ubah}(h]h ]h"]h$]h&]uh1j'hjQ!ubeh}(h]h ]h"]h$]h&]uh1jhjl!hM hj ubj)}(h0``mbz16`` reserved for future use; must be zero h](j)}(h ``mbz16``h]j)}(hj!h]hmbz16}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj!ubj()}(hhh]h)}(h%reserved for future use; must be zeroh]h%reserved for future use; must be zero}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1j'hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hM hj ubj)}(hH``flags`` all undefined flags must be zero, currently not defined flags h](j)}(h ``flags``h]j)}(hj!h]hflags}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj!ubj()}(hhh]h)}(h=all undefined flags must be zero, currently not defined flagsh]h=all undefined flags must be zero, currently not defined flags}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM hj!ubah}(h]h ]h"]h$]h&]uh1j'hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hM hj ubj)}(h0``mbz64`` reserved for future use; must be zero h](j)}(h ``mbz64``h]j)}(hj"h]hmbz64}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj!ubj()}(hhh]h)}(h%reserved for future use; must be zeroh]h%reserved for future use; must be zero}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1j'hj!ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hj ubj)}(h``engines`` 2-d array of engine instances to configure parallel engine length = width (i) * num_siblings (j) index = j + i * num_siblingsh](j)}(h ``engines``h]j)}(hj<"h]hengines}(hj>"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:"ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj6"ubj()}(hhh](h)}(h:2-d array of engine instances to configure parallel engineh]h:2-d array of engine instances to configure parallel engine}(hjU"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjR"ubh)}(hBlength = width (i) * num_siblings (j) index = j + i * num_siblingsh]hBlength = width (i) * num_siblings (j) index = j + i * num_siblings}(hjd"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQ"hM hjR"ubeh}(h]h ]h"]h$]h&]uh1j'hj6"ubeh}(h]h ]h"]h$]h&]uh1jhjQ"hM hj ubeh}(h]h ]h"]h$]h&]uh1j hjZ ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj"h]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hXOSetup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot's configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.h]hXSSetup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn’t tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot’s configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMM hhhhubh)}(hX9The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.h]hX9The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMV hhhhubh)}(hReturns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn't supported on the platform / submission interface. Returns -ENODEV if extension isn't supported on the platform / submission interface.h]hReturns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn’t supported on the platform / submission interface. Returns -ENODEV if extension isn’t supported on the platform / submission interface.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM_ hhhhubjt)}(hX3Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1]) Results in the following valid placement: CS[0], CS[1] Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3]) Results in the following valid placements: CS[0], CS[1] CS[2], CS[3] This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3] Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3]) Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVALh]hX3Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1]) Results in the following valid placement: CS[0], CS[1] Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3]) Results in the following valid placements: CS[0], CS[1] CS[2], CS[3] This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3] Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3]) Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVAL}hj"sbah}(h]h ]h"]h$]h&]jjj#j$nonej&}uh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMe hhhhubh)}(h.. _Context Engine Map uAPI:h]h}(h]h ]h"]h$]h&]hcontext-engine-map-uapiuh1hhMhhhhhNubh)}(h**Context Engine Map uAPI**h]h)}(hj"h]hContext Engine Map uAPI}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubah}(h]j"ah ]h"]context engine map uapiah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhj}j#j"sj }j"j"subh)}(hContext engine map is a new way of addressing engines when submitting batch- buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` inside the flags field of `struct drm_i915_gem_execbuffer2`.h](hContext engine map is a new way of addressing engines when submitting batch- buffers, replacing the existing way of using identifiers like }(hj#hhhNhNubji )}(h`I915_EXEC_BLT`h]h I915_EXEC_BLT}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj#ubh inside the flags field of }(hj#hhhNhNubji )}(h!`struct drm_i915_gem_execbuffer2`h]hstruct drm_i915_gem_execbuffer2}(hj!#hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj#ubh.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hTo use it created GEM contexts need to be configured with a list of engines the user is intending to submit to. This is accomplished using the `I915_CONTEXT_PARAM_ENGINES` parameter and `struct i915_context_param_engines`.h](hTo use it created GEM contexts need to be configured with a list of engines the user is intending to submit to. This is accomplished using the }(hj:#hhhNhNubji )}(h`I915_CONTEXT_PARAM_ENGINES`h]hI915_CONTEXT_PARAM_ENGINES}(hjB#hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj:#ubh parameter and }(hj:#hhhNhNubji )}(h#`struct i915_context_param_engines`h]h!struct i915_context_param_engines}(hjT#hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj:#ubh.}(hj:#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h[For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the configured map.h](hFor such contexts the }(hjm#hhhNhNubji )}(h`I915_EXEC_RING_MASK`h]hI915_EXEC_RING_MASK}(hju#hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjm#ubh0 field becomes an index into the configured map.}(hjm#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h;Example of creating such context and submitting against it:h]h;Example of creating such context and submitting against it:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubjt)}(hX}I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, { I915_ENGINE_CLASS_COPY, 0 } } }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // We have now created a GEM context with two engines in the map: // Index 0 points to rcs0 while index 1 points to bcs0. Other engines // will not be accessible from this context. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context gem_execbuf(drm_fd, &execbuf); ... execbuf.rsvd1 = ctx_id; execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context gem_execbuf(drm_fd, &execbuf);h]hX}I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, { I915_ENGINE_CLASS_COPY, 0 } } }; struct drm_i915_gem_context_create_ext_setparam p_engines = { .base = { .name = I915_CONTEXT_CREATE_EXT_SETPARAM, }, .param = { .param = I915_CONTEXT_PARAM_ENGINES, .value = to_user_pointer(&engines), .size = sizeof(engines), }, }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, .extensions = to_user_pointer(&p_engines); }; ctx_id = gem_context_create_ext(drm_fd, &create); // We have now created a GEM context with two engines in the map: // Index 0 points to rcs0 while index 1 points to bcs0. Other engines // will not be accessible from this context. ... execbuf.rsvd1 = ctx_id; execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context gem_execbuf(drm_fd, &execbuf); ... execbuf.rsvd1 = ctx_id; execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context gem_execbuf(drm_fd, &execbuf);}hj#sbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j3drm_i915_gem_context_create_ext_setparam (C struct)*c.drm_i915_gem_context_create_ext_setparamhNtauh1jhhhhhNhNubj)}(hhh](j)}(h(drm_i915_gem_context_create_ext_setparamh]j)}(h/struct drm_i915_gem_context_create_ext_setparamh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhj#hM ubj)}(h(drm_i915_gem_context_create_ext_setparamh]j)}(hj#h]h(drm_i915_gem_context_create_ext_setparam}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj#hhhj#hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj#hhhj#hM ubah}(h]j#ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj#hM hj#hhubj))}(hhh]h)}(h:Context parameter to set or query during context creation.h]h:Context parameter to set or query during context creation.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM# hj$hhubah}(h]h ]h"]h$]h&]uh1j(hj#hhhj#hM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj $jLj $jMjNjOuh1jhhhhhNhNubjQ)}(hXB**Definition**:: struct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``param`` Context parameter to set or query. See struct drm_i915_gem_context_param.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj,$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj($ubh:}(hj($hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM' hj$$ubjt)}(hstruct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; };h]hstruct drm_i915_gem_context_create_ext_setparam { struct i915_user_extension base; struct drm_i915_gem_context_param param; };}hjE$sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM) hj$$ubh)}(h **Members**h]h)}(hjV$h]hMembers}(hjX$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT$ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM. hj$$ubj )}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]j)}(hju$h]hbase}(hjw$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs$ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM( hjo$ubj()}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM( hj$ubah}(h]h ]h"]h$]h&]uh1j'hjo$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM( hjl$ubj)}(hS``param`` Context parameter to set or query. See struct drm_i915_gem_context_param.h](j)}(h ``param``h]j)}(hj$h]hparam}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM, hj$ubj()}(hhh]h)}(hIContext parameter to set or query. See struct drm_i915_gem_context_param.h]hIContext parameter to set or query. See struct drm_i915_gem_context_param.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM, hj$ubah}(h]h ]h"]h$]h&]uh1j'hj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM, hjl$ubeh}(h]h ]h"]h$]h&]uh1j hj$$ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_vm_control (C struct)c.drm_i915_gem_vm_controlhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_vm_controlh]j)}(hstruct drm_i915_gem_vm_controlh](j)}(hjh]hstruct}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM3 ubj)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhhj%hM3 ubj)}(hdrm_i915_gem_vm_controlh]j)}(hj%h]hdrm_i915_gem_vm_control}(hj'%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#%ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj%hhhj%hM3 ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj$hhhj%hM3 ubah}(h]j$ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj%hM3 hj$hhubj))}(hhh]h)}(h"Structure to create or destroy VM.h]h"Structure to create or destroy VM.}(hjI%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7 hjF%hhubah}(h]h ]h"]h$]h&]uh1j(hj$hhhj%hM3 ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKja%jLja%jMjNjOuh1jhhhhhNhNubjQ)}(hX&**Definition**:: struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; }; **Members** ``extensions`` Zero-terminated chain of extensions. ``flags`` reserved for future usage, currently MBZ ``vm_id`` Id of the VM created or to be destroyedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjm%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji%ubh:}(hji%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM; hje%ubjt)}(h[struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; };h]h[struct drm_i915_gem_vm_control { __u64 extensions; __u32 flags; __u32 vm_id; };}hj%sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM= hje%ubh)}(h **Members**h]h)}(hj%h]hMembers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMC hje%ubj )}(hhh](j)}(h4``extensions`` Zero-terminated chain of extensions. h](j)}(h``extensions``h]j)}(hj%h]h extensions}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMM hj%ubj()}(hhh]h)}(h$Zero-terminated chain of extensions.h]h$Zero-terminated chain of extensions.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMM hj%ubah}(h]h ]h"]h$]h&]uh1j'hj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hMM hj%ubj)}(h3``flags`` reserved for future usage, currently MBZ h](j)}(h ``flags``h]j)}(hj%h]hflags}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMP hj%ubj()}(hhh]h)}(h(reserved for future usage, currently MBZh]h(reserved for future usage, currently MBZ}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hMP hj&ubah}(h]h ]h"]h$]h&]uh1j'hj%ubeh}(h]h ]h"]h$]h&]uh1jhj&hMP hj%ubj)}(h1``vm_id`` Id of the VM created or to be destroyedh](j)}(h ``vm_id``h]j)}(hj(&h]hvm_id}(hj*&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&&ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMR hj"&ubj()}(hhh]h)}(h'Id of the VM created or to be destroyedh]h'Id of the VM created or to be destroyed}(hjA&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMS hj>&ubah}(h]h ]h"]h$]h&]uh1j'hj"&ubeh}(h]h ]h"]h$]h&]uh1jhj=&hMR hj%ubeh}(h]h ]h"]h$]h&]uh1j hje%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjk&h]h Description}(hjm&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji&ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMV hhhhubh)}(hDRM_I915_GEM_VM_CREATE -h]hDRM_I915_GEM_VM_CREATE -}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM8 hhhhubh)}(hCreate a new virtual memory address space (ppGTT) for use within a context on the same file. Extensions can be provided to configure exactly how the address space is setup upon creation.h]hCreate a new virtual memory address space (ppGTT) for use within a context on the same file. Extensions can be provided to configure exactly how the address space is setup upon creation.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM: hhhhubh)}(hiThe id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is returned in the outparam **id**.h](hbThe id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is returned in the outparam }(hj&hhhNhNubh)}(h**id**h]hid}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&ubh.}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM> hhhhubh)}(hAn extension chain maybe provided, starting with **extensions**, and terminated by the **next_extension** being 0. Currently, no extensions are defined.h](h1An extension chain maybe provided, starting with }(hj&hhhNhNubh)}(h**extensions**h]h extensions}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&ubh, and terminated by the }(hj&hhhNhNubh)}(h**next_extension**h]hnext_extension}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&ubh/ being 0. Currently, no extensions are defined.}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMA hhhhubh)}(hDRM_I915_GEM_VM_DESTROY -h]hDRM_I915_GEM_VM_DESTROY -}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMD hhhhubh)}(h'ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjX'hMM hj@'hhubj))}(hhh]h)}(h-Create GEM object from user allocated memory.h]h-Create GEM object from user allocated memory.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj'hhubah}(h]h ]h"]h$]h&]uh1j(hj@'hhhjX'hMM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj'jLj'jMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_userptr { __u64 user_ptr; __u64 user_size; __u32 flags; #define I915_USERPTR_READ_ONLY 0x1; #define I915_USERPTR_PROBE 0x2; #define I915_USERPTR_UNSYNCHRONIZED 0x80000000; __u32 handle; }; **Members** ``user_ptr`` The pointer to the allocated memory. Needs to be aligned to PAGE_SIZE. ``user_size`` The size in bytes for the allocated memory. This will also become the object size. Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, or larger. ``flags`` Supported flags: I915_USERPTR_READ_ONLY: Mark the object as readonly, this also means GPU access can only be readonly. This is only supported on HW which supports readonly access through the GTT. If the HW can't support readonly access, an error is returned. I915_USERPTR_PROBE: Probe the provided **user_ptr** range and validate that the **user_ptr** is indeed pointing to normal memory and that the range is also valid. For example if some garbage address is given to the kernel, then this should complain. Returns -EFAULT if the probe failed. Note that this doesn't populate the backing pages, and also doesn't guarantee that the object will remain valid when the object is eventually used. The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE returns a non-zero value. I915_USERPTR_UNSYNCHRONIZED: NOT USED. Setting this flag will result in an error. ``handle`` Returned handle for the object. Object handles are nonzero.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubh:}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj'ubjt)}(hstruct drm_i915_gem_userptr { __u64 user_ptr; __u64 user_size; __u32 flags; #define I915_USERPTR_READ_ONLY 0x1; #define I915_USERPTR_PROBE 0x2; #define I915_USERPTR_UNSYNCHRONIZED 0x80000000; __u32 handle; };h]hstruct drm_i915_gem_userptr { __u64 user_ptr; __u64 user_size; __u32 flags; #define I915_USERPTR_READ_ONLY 0x1; #define I915_USERPTR_PROBE 0x2; #define I915_USERPTR_UNSYNCHRONIZED 0x80000000; __u32 handle; };}hj'sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj'ubh)}(h **Members**h]h)}(hj'h]hMembers}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj'ubj )}(hhh](j)}(hU``user_ptr`` The pointer to the allocated memory. Needs to be aligned to PAGE_SIZE. h](j)}(h ``user_ptr``h]j)}(hj'h]huser_ptr}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj'ubj()}(hhh](h)}(h$The pointer to the allocated memory.h]h$The pointer to the allocated memory.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(h!Needs to be aligned to PAGE_SIZE.h]h!Needs to be aligned to PAGE_SIZE.}(hj"(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hM hj(ubeh}(h]h ]h"]h$]h&]uh1j'hj'ubeh}(h]h ]h"]h$]h&]uh1jhj(hM hj'ubj)}(h``user_size`` The size in bytes for the allocated memory. This will also become the object size. Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, or larger. h](j)}(h ``user_size``h]j)}(hjB(h]h user_size}(hjD(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@(ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj<(ubj()}(hhh](h)}(hRThe size in bytes for the allocated memory. This will also become the object size.h]hRThe size in bytes for the allocated memory. This will also become the object size.}(hj[(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjX(ubh)}(hNNeeds to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, or larger.h]hNNeeds to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, or larger.}(hjj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjX(ubeh}(h]h ]h"]h$]h&]uh1j'hj<(ubeh}(h]h ]h"]h$]h&]uh1jhjW(hM hj'ubj)}(hXv``flags`` Supported flags: I915_USERPTR_READ_ONLY: Mark the object as readonly, this also means GPU access can only be readonly. This is only supported on HW which supports readonly access through the GTT. If the HW can't support readonly access, an error is returned. I915_USERPTR_PROBE: Probe the provided **user_ptr** range and validate that the **user_ptr** is indeed pointing to normal memory and that the range is also valid. For example if some garbage address is given to the kernel, then this should complain. Returns -EFAULT if the probe failed. Note that this doesn't populate the backing pages, and also doesn't guarantee that the object will remain valid when the object is eventually used. The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE returns a non-zero value. I915_USERPTR_UNSYNCHRONIZED: NOT USED. Setting this flag will result in an error. h](j)}(h ``flags``h]j)}(hj(h]hflags}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubj()}(hhh](h)}(hSupported flags:h]hSupported flags:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(hI915_USERPTR_READ_ONLY:h]hI915_USERPTR_READ_ONLY:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(hMark the object as readonly, this also means GPU access can only be readonly. This is only supported on HW which supports readonly access through the GTT. If the HW can't support readonly access, an error is returned.h]hMark the object as readonly, this also means GPU access can only be readonly. This is only supported on HW which supports readonly access through the GTT. If the HW can’t support readonly access, an error is returned.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(hI915_USERPTR_PROBE:h]hI915_USERPTR_PROBE:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(hProbe the provided **user_ptr** range and validate that the **user_ptr** is indeed pointing to normal memory and that the range is also valid. For example if some garbage address is given to the kernel, then this should complain.h](hProbe the provided }(hj(hhhNhNubh)}(h **user_ptr**h]huser_ptr}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh range and validate that the }(hj(hhhNhNubh)}(h **user_ptr**h]huser_ptr}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh is indeed pointing to normal memory and that the range is also valid. For example if some garbage address is given to the kernel, then this should complain.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(h$Returns -EFAULT if the probe failed.h]h$Returns -EFAULT if the probe failed.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(hNote that this doesn't populate the backing pages, and also doesn't guarantee that the object will remain valid when the object is eventually used.h]hNote that this doesn’t populate the backing pages, and also doesn’t guarantee that the object will remain valid when the object is eventually used.}(hj")hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(hZThe kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE returns a non-zero value.h]hZThe kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE returns a non-zero value.}(hj1)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(hI915_USERPTR_UNSYNCHRONIZED:h]hI915_USERPTR_UNSYNCHRONIZED:}(hj@)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj(ubh)}(h4NOT USED. Setting this flag will result in an error.h]h4NOT USED. Setting this flag will result in an error.}(hjO)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hM hj(ubeh}(h]h ]h"]h$]h&]uh1j'hj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hM hj'ubj)}(hG``handle`` Returned handle for the object. Object handles are nonzero.h](j)}(h ``handle``h]j)}(hjo)h]hhandle}(hjq)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm)ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hji)ubj()}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj)ubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj)ubeh}(h]h ]h"]h$]h&]uh1j'hji)ubeh}(h]h ]h"]h$]h&]uh1jhj)hM hj'ubeh}(h]h ]h"]h$]h&]uh1j hj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj)h]h Description}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h\Userptr objects have several restrictions on what ioctls can be used with the object handle.h]h\Userptr objects have several restrictions on what ioctls can be used with the object handle.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_perf_oa_config (C struct)c.drm_i915_perf_oa_confighNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_perf_oa_configh]j)}(hstruct drm_i915_perf_oa_configh](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj *hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)hhhj *hM ubj)}(hdrm_i915_perf_oa_configh]j)}(hj)h]hdrm_i915_perf_oa_config}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj)hhhj *hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj)hhhj *hM ubah}(h]j)ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj *hM hj)hhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hj)hhhj *hM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjJ*jLjJ*jMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_perf_oa_config { char uuid[36]; __u32 n_mux_regs; __u32 n_boolean_regs; __u32 n_flex_regs; __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; }; **Members** ``uuid`` String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" ``n_mux_regs`` Number of mux regs in :c:type:`mux_regs_ptr`. ``n_boolean_regs`` Number of boolean regs in :c:type:`boolean_regs_ptr`. ``n_flex_regs`` Number of flex regs in :c:type:`flex_regs_ptr`. ``mux_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_mux_regs`). ``boolean_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_boolean_regs`). ``flex_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_flex_regs`).h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjV*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR*ubh:}(hjR*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjN*ubjt)}(hstruct drm_i915_perf_oa_config { char uuid[36]; __u32 n_mux_regs; __u32 n_boolean_regs; __u32 n_flex_regs; __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; };h]hstruct drm_i915_perf_oa_config { char uuid[36]; __u32 n_mux_regs; __u32 n_boolean_regs; __u32 n_flex_regs; __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; };}hjo*sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjN*ubh)}(h **Members**h]h)}(hj*h]hMembers}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~*ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjN*ubj )}(hhh](j)}(h@``uuid`` String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" h](j)}(h``uuid``h]j)}(hj*h]huuid}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj*ubj()}(hhh]h)}(h6String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"h]h:String formatted like “%08x-%04x-%04x-%04x-%012x”}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1j'hj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hM hj*ubj)}(h=``n_mux_regs`` Number of mux regs in :c:type:`mux_regs_ptr`. h](j)}(h``n_mux_regs``h]j)}(hj*h]h n_mux_regs}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj*ubj()}(hhh]h)}(h-Number of mux regs in :c:type:`mux_regs_ptr`.h](hNumber of mux regs in }(hj*hhhNhNubh)}(h:c:type:`mux_regs_ptr`h]j)}(hj*h]h mux_regs_ptr}(hj*hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) mux_regs_ptruh1hhj*hM hj*ubh.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1j'hj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hM hj*ubj)}(hI``n_boolean_regs`` Number of boolean regs in :c:type:`boolean_regs_ptr`. h](j)}(h``n_boolean_regs``h]j)}(hj4+h]hn_boolean_regs}(hj6+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2+ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj.+ubj()}(hhh]h)}(h5Number of boolean regs in :c:type:`boolean_regs_ptr`.h](hNumber of boolean regs in }(hjM+hhhNhNubh)}(h:c:type:`boolean_regs_ptr`h]j)}(hjW+h]hboolean_regs_ptr}(hjY+hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjU+ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) boolean_regs_ptruh1hhjI+hM hjM+ubh.}(hjM+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjI+hM hjJ+ubah}(h]h ]h"]h$]h&]uh1j'hj.+ubeh}(h]h ]h"]h$]h&]uh1jhjI+hM hj*ubj)}(h@``n_flex_regs`` Number of flex regs in :c:type:`flex_regs_ptr`. h](j)}(h``n_flex_regs``h]j)}(hj+h]h n_flex_regs}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj+ubj()}(hhh]h)}(h/Number of flex regs in :c:type:`flex_regs_ptr`.h](hNumber of flex regs in }(hj+hhhNhNubh)}(h:c:type:`flex_regs_ptr`h]j)}(hj+h]h flex_regs_ptr}(hj+hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) flex_regs_ptruh1hhj+hM hj+ubh.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj+hM hj+ubah}(h]h ]h"]h$]h&]uh1j'hj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hM hj*ubj)}(h``mux_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_mux_regs`). h](j)}(h``mux_regs_ptr``h]j)}(hj+h]h mux_regs_ptr}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj+ubj()}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_mux_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hj,hhhNhNubh)}(h:c:type:`n_mux_regs`h]j)}(hj,h]h n_mux_regs}(hj,hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj ,ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) n_mux_regsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj,ubh).}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj,,hM hj,ubah}(h]h ]h"]h$]h&]uh1j'hj+ubeh}(h]h ]h"]h$]h&]uh1jhj,hM hj*ubj)}(h``boolean_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_boolean_regs`). h](j)}(h``boolean_regs_ptr``h]j)}(hjI,h]hboolean_regs_ptr}(hjK,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG,ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjC,ubj()}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_boolean_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hjb,hhhNhNubh)}(h:c:type:`n_boolean_regs`h]j)}(hjl,h]hn_boolean_regs}(hjn,hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjj,ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) n_boolean_regsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjb,ubh).}(hjb,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj,hM hj_,ubah}(h]h ]h"]h$]h&]uh1j'hjC,ubeh}(h]h ]h"]h$]h&]uh1jhj^,hM hj*ubj)}(h``flex_regs_ptr`` Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_flex_regs`).h](j)}(h``flex_regs_ptr``h]j)}(hj,h]h flex_regs_ptr}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj,ubj()}(hhh]h)}(hPointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * :c:type:`n_flex_regs`).h](h~Pointer to tuples of u32 values (register address, value) for mux registers. Expected length of buffer is (2 * sizeof(u32) * }(hj,hhhNhNubh)}(h:c:type:`n_flex_regs`h]j)}(hj,h]h n_flex_regs}(hj,hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) n_flex_regsuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj,ubh).}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj,hM hj,ubah}(h]h ]h"]h$]h&]uh1j'hj,ubeh}(h]h ]h"]h$]h&]uh1jhj,hM hj*ubeh}(h]h ]h"]h$]h&]uh1j hjN*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj -h]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj -ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h?Structure to upload perf dynamic configuration into the kernel.h]h?Structure to upload perf dynamic configuration into the kernel.}(hj"-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_query_item (C struct)c.drm_i915_query_itemhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_itemh]j)}(hstruct drm_i915_query_itemh](j)}(hjh]hstruct}(hjJ-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjF-hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjX-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjF-hhhjW-hM ubj)}(hdrm_i915_query_itemh]j)}(hjD-h]hdrm_i915_query_item}(hjj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjf-ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjF-hhhjW-hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjB-hhhjW-hM ubah}(h]j=-ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjW-hM hj?-hhubj))}(hhh]h)}(h.An individual query for the kernel to process.h]h.An individual query for the kernel to process.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-hhubah}(h]h ]h"]h$]h&]uh1j(hj?-hhhjW-hM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj-jLj-jMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; }; **Members** ``query_id`` The id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) ``length`` When set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item. ``flags`` When :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0. When :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following: - ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` When :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine. ``data_ptr`` Data will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-ubh:}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-ubjt)}(hXkstruct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; };h]hXkstruct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1; #define DRM_I915_QUERY_ENGINE_INFO 2; #define DRM_I915_QUERY_PERF_CONFIG 3; #define DRM_I915_QUERY_MEMORY_REGIONS 4; #define DRM_I915_QUERY_HWCONFIG_BLOB 5; #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6; #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7; __s32 length; __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2; #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3; __u64 data_ptr; };}hj-sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-ubh)}(h **Members**h]h)}(hj-h]hMembers}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-ubj )}(hhh](j)}(hXi``query_id`` The id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h](j)}(h ``query_id``h]j)}(hj-h]hquery_id}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-ubj()}(hhh]j )}(hhh]j)}(hXUThe id for this query. Currently accepted query IDs are: - ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info) - ``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config) - ``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions) - ``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`) - ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info) - ``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h](j)}(h9The id for this query. Currently accepted query IDs are:h]h9The id for this query. Currently accepted query IDs are:}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.hM hj.ubj()}(hhh]j )}(hhh](j )}(hJ``DRM_I915_QUERY_TOPOLOGY_INFO`` (see struct drm_i915_query_topology_info)h]h)}(hj/.h](j)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj4.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1.ubh* (see struct drm_i915_query_topology_info)}(hj1.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj-.ubah}(h]h ]h"]h$]h&]uh1j hj*.ubj )}(h@``DRM_I915_QUERY_ENGINE_INFO`` (see struct drm_i915_engine_info)h]h)}(hjU.h](j)}(h``DRM_I915_QUERY_ENGINE_INFO``h]hDRM_I915_QUERY_ENGINE_INFO}(hjZ.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjW.ubh" (see struct drm_i915_engine_info)}(hjW.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjS.ubah}(h]h ]h"]h$]h&]uh1j hj*.ubj )}(hF``DRM_I915_QUERY_PERF_CONFIG`` (see struct drm_i915_query_perf_config)h]h)}(hj{.h](j)}(h``DRM_I915_QUERY_PERF_CONFIG``h]hDRM_I915_QUERY_PERF_CONFIG}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}.ubh( (see struct drm_i915_query_perf_config)}(hj}.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjy.ubah}(h]h ]h"]h$]h&]uh1j hj*.ubj )}(hL``DRM_I915_QUERY_MEMORY_REGIONS`` (see struct drm_i915_query_memory_regions)h]h)}(hj.h](j)}(h!``DRM_I915_QUERY_MEMORY_REGIONS``h]hDRM_I915_QUERY_MEMORY_REGIONS}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh+ (see struct drm_i915_query_memory_regions)}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj.ubah}(h]h ]h"]h$]h&]uh1j hj*.ubj )}(h?``DRM_I915_QUERY_HWCONFIG_BLOB`` (see `GuC HWCONFIG blob uAPI`)h]h)}(hj.h](j)}(h ``DRM_I915_QUERY_HWCONFIG_BLOB``h]hDRM_I915_QUERY_HWCONFIG_BLOB}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh (see }(hj.hhhNhNubji )}(h`GuC HWCONFIG blob uAPI`h]hGuC HWCONFIG blob uAPI}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj.ubh)}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj.ubah}(h]h ]h"]h$]h&]uh1j hj*.ubj )}(hO``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` (see struct drm_i915_query_topology_info)h]h)}(hj.h](j)}(h%``DRM_I915_QUERY_GEOMETRY_SUBSLICES``h]h!DRM_I915_QUERY_GEOMETRY_SUBSLICES}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubh* (see struct drm_i915_query_topology_info)}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj.ubah}(h]h ]h"]h$]h&]uh1j hj*.ubj )}(h]``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version) h]h)}(h\``DRM_I915_QUERY_GUC_SUBMISSION_VERSION`` (see struct drm_i915_query_guc_submission_version)h](j)}(h)``DRM_I915_QUERY_GUC_SUBMISSION_VERSION``h]h%DRM_I915_QUERY_GUC_SUBMISSION_VERSION}(hj+/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'/ubh3 (see struct drm_i915_query_guc_submission_version)}(hj'/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj.hM hj#/ubah}(h]h ]h"]h$]h&]uh1j hj*.ubeh}(h]h ]h"]h$]h&]j) j* uh1j hjL.hM hj'.ubah}(h]h ]h"]h$]h&]uh1j'hj.ubeh}(h]h ]h"]h$]h&]uh1jhj.hM hj.ubah}(h]h ]h"]h$]h&]uh1j hj.ubah}(h]h ]h"]h$]h&]uh1j'hj-ubeh}(h]h ]h"]h$]h&]uh1jhj.hM hj-ubj)}(h``length`` When set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item. h](j)}(h ``length``h]j)}(hjs/h]hlength}(hju/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq/ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjm/ubj()}(hhh]h)}(hWhen set to zero by userspace, this is filled with the size of the data to be written at the **data_ptr** pointer. The kernel sets this value to a negative value to signal an error on a particular query item.h](h]When set to zero by userspace, this is filled with the size of the data to be written at the }(hj/hhhNhNubh)}(h **data_ptr**h]hdata_ptr}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/ubhg pointer. The kernel sets this value to a negative value to signal an error on a particular query item.}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj/ubah}(h]h ]h"]h$]h&]uh1j'hjm/ubeh}(h]h ]h"]h$]h&]uh1jhj/hM hj-ubj)}(hX``flags`` When :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0. When :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following: - ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` When :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine. h](j)}(h ``flags``h]j)}(hj/h]hflags}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj/ubj()}(hhh](h)}(hGWhen :c:type:`query_id` == ``DRM_I915_QUERY_TOPOLOGY_INFO``, must be 0.h](hWhen }(hj/hhhNhNubh)}(h:c:type:`query_id`h]j)}(hj/h]hquery_id}(hj/hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) query_iduh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj/ubh == }(hj/hhhNhNubj)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubh , must be 0.}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/hM hj/ubh)}(hXWhen :c:type:`query_id` == ``DRM_I915_QUERY_PERF_CONFIG``, must be one of the following:h](hWhen }(hj0hhhNhNubh)}(h:c:type:`query_id`h]j)}(hj&0h]hquery_id}(hj(0hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj$0ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) query_iduh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj0ubh == }(hj0hhhNhNubj)}(h``DRM_I915_QUERY_PERF_CONFIG``h]hDRM_I915_QUERY_PERF_CONFIG}(hjH0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh, must be one of the following:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjC0hM hj/ubj)}(h- ``DRM_I915_QUERY_PERF_CONFIG_LIST`` - ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID`` - ``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` h]j )}(hhh](j )}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]h)}(hji0h]j)}(hji0h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hjn0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk0ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjg0ubah}(h]h ]h"]h$]h&]uh1j hjd0ubj )}(h,``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``h]h)}(hj0h]j)}(hj0h]h(DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj0ubah}(h]h ]h"]h$]h&]uh1j hjd0ubj )}(h(``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID`` h]h)}(h'``DRM_I915_QUERY_PERF_CONFIG_FOR_UUID``h]j)}(hj0h]h#DRM_I915_QUERY_PERF_CONFIG_FOR_UUID}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj0ubah}(h]h ]h"]h$]h&]uh1j hjd0ubeh}(h]h ]h"]h$]h&]j) j* uh1j hj0hM hj`0ubah}(h]h ]h"]h$]h&]uh1jhj0hM hj/ubh)}(hWhen :c:type:`query_id` == ``DRM_I915_QUERY_GEOMETRY_SUBSLICES`` must contain a struct i915_engine_class_instance that references a render engine.h](hWhen }(hj0hhhNhNubh)}(h:c:type:`query_id`h]j)}(hj0h]hquery_id}(hj0hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) query_iduh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj0ubh == }(hj0hhhNhNubj)}(h%``DRM_I915_QUERY_GEOMETRY_SUBSLICES``h]h!DRM_I915_QUERY_GEOMETRY_SUBSLICES}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubhR must contain a struct i915_engine_class_instance that references a render engine.}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj0hM hj/ubeh}(h]h ]h"]h$]h&]uh1j'hj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hM hj-ubj)}(h``data_ptr`` Data will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](j)}(h ``data_ptr``h]j)}(hj-1h]hdata_ptr}(hj/1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+1ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM) hj'1ubj()}(hhh]h)}(hData will be written at the location pointed by **data_ptr** when the value of **length** matches the length of the data to be written by the kernel.h](h0Data will be written at the location pointed by }(hjF1hhhNhNubh)}(h **data_ptr**h]hdata_ptr}(hjN1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF1ubh when the value of }(hjF1hhhNhNubh)}(h **length**h]hlength}(hj`1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF1ubh< matches the length of the data to be written by the kernel.}(hjF1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM( hjC1ubah}(h]h ]h"]h$]h&]uh1j'hj'1ubeh}(h]h ]h"]h$]h&]uh1jhjB1hM) hj-ubeh}(h]h ]h"]h$]h&]uh1j hj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj1h]h Description}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM- hhhhubh)}(hThe behaviour is determined by the **query_id**. Note that exactly what **data_ptr** is also depends on the specific **query_id**.h](h#The behaviour is determined by the }(hj1hhhNhNubh)}(h **query_id**h]hquery_id}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh. Note that exactly what }(hj1hhhNhNubh)}(h **data_ptr**h]hdata_ptr}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh! is also depends on the specific }(hj1hhhNhNubh)}(h **query_id**h]hquery_id}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_query (C struct)c.drm_i915_queryhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_queryh]j)}(hstruct drm_i915_queryh](j)}(hjh]hstruct}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhj2hM ubj)}(hdrm_i915_queryh]j)}(hj2h]hdrm_i915_query}(hj(2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$2ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj2hhhj2hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj2hhhj2hM ubah}(h]j1ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj2hM hj1hhubj))}(hhh]h)}(hISupply an array of struct drm_i915_query_item for the kernel to fill out.h]hISupply an array of struct drm_i915_query_item for the kernel to fill out.}(hjJ2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM1 hjG2hhubah}(h]h ]h"]h$]h&]uh1j(hj1hhhj2hM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjb2jLjb2jMjNjOuh1jhhhhhNhNubjQ)}(hXl**Definition**:: struct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; }; **Members** ``num_items`` The number of elements in the **items_ptr** array ``flags`` Unused for now. Must be cleared to zero. ``items_ptr`` Pointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjn2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj2ubh:}(hjj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5 hjf2ubjt)}(hUstruct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; };h]hUstruct drm_i915_query { __u32 num_items; __u32 flags; __u64 items_ptr; };}hj2sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7 hjf2ubh)}(h **Members**h]h)}(hj2h]hMembers}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM= hjf2ubj )}(hhh](j)}(h@``num_items`` The number of elements in the **items_ptr** array h](j)}(h ``num_items``h]j)}(hj2h]h num_items}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMI hj2ubj()}(hhh]h)}(h1The number of elements in the **items_ptr** arrayh](hThe number of elements in the }(hj2hhhNhNubh)}(h **items_ptr**h]h items_ptr}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ubh array}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj2hMI hj2ubah}(h]h ]h"]h$]h&]uh1j'hj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hMI hj2ubj)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]j)}(hj3h]hflags}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMM hj2ubj()}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMM hj3ubah}(h]h ]h"]h$]h&]uh1j'hj2ubeh}(h]h ]h"]h$]h&]uh1jhj3hMM hj2ubj)}(ho``items_ptr`` Pointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](j)}(h ``items_ptr``h]j)}(hj;3h]h items_ptr}(hj=3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj93ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMR hj53ubj()}(hhh]h)}(haPointer to an array of struct drm_i915_query_item. The number of array elements is **num_items**.h](hSPointer to an array of struct drm_i915_query_item. The number of array elements is }(hjT3hhhNhNubh)}(h **num_items**h]h num_items}(hj\3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT3ubh.}(hjT3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjP3hMR hjQ3ubah}(h]h ]h"]h$]h&]uh1j'hj53ubeh}(h]h ]h"]h$]h&]uh1jhjP3hMR hj2ubeh}(h]h ]h"]h$]h&]uh1j hjf2ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj3h]h Description}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMV hhhhubh)}(h`Note that this is generally a two step process for each struct drm_i915_query_item in the array:h]h`Note that this is generally a two step process for each struct drm_i915_query_item in the array:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2 hhhhubhenumerated_list)}(hhh](j )}(hX4Call the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with :c:type:`drm_i915_query_item.length ` set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties). h]h)}(hX3Call the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with :c:type:`drm_i915_query_item.length ` set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties).h](hWCall the DRM_IOCTL_I915_QUERY, giving it our array of struct drm_i915_query_item, with }(hj3hhhNhNubh)}(h::c:type:`drm_i915_query_item.length `h]j)}(hj3h]hdrm_i915_query_item.length}(hj3hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5 hj3ubh set to zero. The kernel will then fill in the size, in bytes, which tells userspace how memory it needs to allocate for the blob(say for an array of properties).}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj3hM5 hj3ubah}(h]h ]h"]h$]h&]uh1j hj3ubj )}(hXPNext we call DRM_IOCTL_I915_QUERY again, this time with the :c:type:`drm_i915_query_item.data_ptr ` equal to our newly allocated blob. Note that the :c:type:`drm_i915_query_item.length ` should still be the same as what the kernel previously set. At this point the kernel can fill in the blob. h]h)}(hXONext we call DRM_IOCTL_I915_QUERY again, this time with the :c:type:`drm_i915_query_item.data_ptr ` equal to our newly allocated blob. Note that the :c:type:`drm_i915_query_item.length ` should still be the same as what the kernel previously set. At this point the kernel can fill in the blob.h](h`h]j)}(hj4h]hdrm_i915_query_item.data_ptr}(hj4hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM: hj3ubh2 equal to our newly allocated blob. Note that the }(hj3hhhNhNubh)}(h::c:type:`drm_i915_query_item.length `h]j)}(hj'4h]hdrm_i915_query_item.length}(hj)4hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj%4ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhj 4hM: hj3ubhk should still be the same as what the kernel previously set. At this point the kernel can fill in the blob.}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj 4hM: hj3ubah}(h]h ]h"]h$]h&]uh1j hj3ubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j3hhhhhNhNubh)}(hNote that for some query items it can make sense for userspace to just pass in a buffer/blob equal to or larger than the required size. In this case only a single ioctl call is needed. For some smaller query items this can work quite well.h]hNote that for some query items it can make sense for userspace to just pass in a buffer/blob equal to or larger than the required size. In this case only a single ioctl call is needed. For some smaller query items this can work quite well.}(hj_4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM? hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'drm_i915_query_topology_info (C struct)c.drm_i915_query_topology_infohNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_topology_infoh]j)}(h#struct drm_i915_query_topology_infoh](j)}(hjh]hstruct}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMG ubj)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhj4hMG ubj)}(hdrm_i915_query_topology_infoh]j)}(hj4h]hdrm_i915_query_topology_info}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj4hhhj4hMG ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj4hhhj4hMG ubah}(h]jz4ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj4hMG hj|4hhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hj|4hhhj4hMG ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj4jLj4jMjNjOuh1jhhhhhNhNubjQ)}(hX? **Definition**:: struct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; }; **Members** ``flags`` Unused for now. Must be cleared to zero. ``max_slices`` The number of bits used to express the slice mask. ``max_subslices`` The number of bits used to express the subslice mask. ``max_eus_per_subslice`` The number of bits in the EU mask that correspond to a single subslice's EUs. ``subslice_offset`` Offset in data[] at which the subslice masks are stored. ``subslice_stride`` Stride at which each of the subslice masks for each slice are stored. ``eu_offset`` Offset in data[] at which the EU masks are stored. ``eu_stride`` Stride at which each of the EU masks for each subslice are stored. ``data`` Contains 3 pieces of information : - The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. - The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 - The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubh:}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM^ hj4ubjt)}(hstruct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; };h]hstruct drm_i915_query_topology_info { __u16 flags; __u16 max_slices; __u16 max_subslices; __u16 max_eus_per_subslice; __u16 subslice_offset; __u16 subslice_stride; __u16 eu_offset; __u16 eu_stride; __u8 data[]; };}hj4sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM` hj4ubh)}(h **Members**h]h)}(hj5h]hMembers}(hj 5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMl hj4ubj )}(hhh](j)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]j)}(hj'5h]hflags}(hj)5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMb hj!5ubj()}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hj@5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<5hMb hj=5ubah}(h]h ]h"]h$]h&]uh1j'hj!5ubeh}(h]h ]h"]h$]h&]uh1jhj<5hMb hj5ubj)}(hB``max_slices`` The number of bits used to express the slice mask. h](j)}(h``max_slices``h]j)}(hj`5h]h max_slices}(hjb5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMi hjZ5ubj()}(hhh]h)}(h2The number of bits used to express the slice mask.h]h2The number of bits used to express the slice mask.}(hjy5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju5hMi hjv5ubah}(h]h ]h"]h$]h&]uh1j'hjZ5ubeh}(h]h ]h"]h$]h&]uh1jhju5hMi hj5ubj)}(hH``max_subslices`` The number of bits used to express the subslice mask. h](j)}(h``max_subslices``h]j)}(hj5h]h max_subslices}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMp hj5ubj()}(hhh]h)}(h5The number of bits used to express the subslice mask.h]h5The number of bits used to express the subslice mask.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMp hj5ubah}(h]h ]h"]h$]h&]uh1j'hj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hMp hj5ubj)}(hg``max_eus_per_subslice`` The number of bits in the EU mask that correspond to a single subslice's EUs. h](j)}(h``max_eus_per_subslice``h]j)}(hj5h]hmax_eus_per_subslice}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMx hj5ubj()}(hhh]h)}(hMThe number of bits in the EU mask that correspond to a single subslice's EUs.h]hOThe number of bits in the EU mask that correspond to a single subslice’s EUs.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMw hj5ubah}(h]h ]h"]h$]h&]uh1j'hj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hMx hj5ubj)}(hM``subslice_offset`` Offset in data[] at which the subslice masks are stored. h](j)}(h``subslice_offset``h]j)}(hj 6h]hsubslice_offset}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj6ubj()}(hhh]h)}(h8Offset in data[] at which the subslice masks are stored.h]h8Offset in data[] at which the subslice masks are stored.}(hj%6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!6hM hj"6ubah}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jhj!6hM hj5ubj)}(hZ``subslice_stride`` Stride at which each of the subslice masks for each slice are stored. h](j)}(h``subslice_stride``h]j)}(hjE6h]hsubslice_stride}(hjG6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj?6ubj()}(hhh]h)}(hEStride at which each of the subslice masks for each slice are stored.h]hEStride at which each of the subslice masks for each slice are stored.}(hj^6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj[6ubah}(h]h ]h"]h$]h&]uh1j'hj?6ubeh}(h]h ]h"]h$]h&]uh1jhjZ6hM hj5ubj)}(hA``eu_offset`` Offset in data[] at which the EU masks are stored. h](j)}(h ``eu_offset``h]j)}(hj6h]h eu_offset}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjy6ubj()}(hhh]h)}(h2Offset in data[] at which the EU masks are stored.h]h2Offset in data[] at which the EU masks are stored.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hM hj6ubah}(h]h ]h"]h$]h&]uh1j'hjy6ubeh}(h]h ]h"]h$]h&]uh1jhj6hM hj5ubj)}(hQ``eu_stride`` Stride at which each of the EU masks for each subslice are stored. h](j)}(h ``eu_stride``h]j)}(hj6h]h eu_stride}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj6ubj()}(hhh]h)}(hBStride at which each of the EU masks for each subslice are stored.h]hBStride at which each of the EU masks for each subslice are stored.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hM hj6ubah}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hM hj5ubj)}(hX```data`` Contains 3 pieces of information : - The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. - The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 - The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](j)}(h``data``h]j)}(hj6h]hdata}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj6ubj()}(hhh](h)}(h"Contains 3 pieces of information :h]h"Contains 3 pieces of information :}(hj 7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubj )}(hhh](j )}(hX6The slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula : .. code:: c (data[X / 8] >> (X % 8)) & 1 Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask. h](h)}(hThe slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula :h]hThe slice mask with one bit per slice telling whether a slice is available. The availability of slice X can be queried with the following formula :}(hj 7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubjt)}(h(data[X / 8] >> (X % 8)) & 1h]h(data[X / 8] >> (X % 8)) & 1}hj/7sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjj$jEuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubh)}(hXrStarting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform's subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as "gslices" or "cslices" since userspace is capable of inferring those from the subslice mask.h]hX|Starting with Xe_HP platforms, Intel hardware no longer has traditional slices so i915 will always report a single slice (hardcoded slicemask = 0x1) which contains all of the platform’s subslices. I.e., the mask here does not reflect any of the newer hardware concepts such as “gslices” or “cslices” since userspace is capable of inferring those from the subslice mask.}(hjA7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubeh}(h]h ]h"]h$]h&]uh1j hj7ubj )}(hXThe subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula : .. code:: c (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 h](h)}(hX7The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term "subslice" to refer to what the hardware documentation describes as a "dual-subslices." The availability of subslice Y in slice X can be queried with the following formula :h]hX?The subslice mask for each slice with one bit per subslice telling whether a subslice is available. Starting with Gen12 we use the term “subslice” to refer to what the hardware documentation describes as a “dual-subslices.” The availability of subslice Y in slice X can be queried with the following formula :}(hjZ7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjV7ubjt)}(hD(data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1h]hD(data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1}hji7sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjj$jEuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjV7ubeh}(h]h ]h"]h$]h&]uh1j hj7ubj )}(hX9The EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula : .. code:: c (data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h](h)}(hThe EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula :h]hThe EU mask for each subslice in each slice, with one bit per EU telling whether an EU is available. The availability of EU Z in subslice Y in slice X can be queried with the following formula :}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubjt)}(h\(data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1h]h\(data[eu_offset + (X * max_subslices + Y) * eu_stride + Z / 8 ] >> (Z % 8)) & 1}hj7sbah}(h]h ]h"]h$]h&]forcehighlight_args}jjj$jEuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj7ubeh}(h]h ]h"]h$]h&]uh1j hj7ubeh}(h]h ]h"]h$]h&]j) j* uh1j hj.7hM hj7ubeh}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jhj7hM hj5ubeh}(h]h ]h"]h$]h&]uh1j hj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj7h]h Description}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hSDescribes slice/subslice/EU information queried by ``DRM_I915_QUERY_TOPOLOGY_INFO``h](h3Describes slice/subslice/EU information queried by }(hj7hhhNhNubj)}(h ``DRM_I915_QUERY_TOPOLOGY_INFO``h]hDRM_I915_QUERY_TOPOLOGY_INFO}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM[ hhhhubh)}(h.. _Engine Discovery uAPI:h]h}(h]h ]h"]h$]h&]hjuh1hhMhhhhhN referencedKubh)}(h**Engine Discovery uAPI**h]h)}(hj 8h]hEngine Discovery uAPI}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 8ubah}(h]jah ]h"]engine discovery uapiah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMa hhhhj}j 8j8sj }jj8sj 8Kubh)}(hEngine discovery uAPI is a way of enumerating physical engines present in a GPU associated with an open i915 DRM file descriptor. This supersedes the old way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like `I915_PARAM_HAS_BLT`.h](hEngine discovery uAPI is a way of enumerating physical engines present in a GPU associated with an open i915 DRM file descriptor. This supersedes the old way of using }(hj&8hhhNhNubji )}(h`DRM_IOCTL_I915_GETPARAM`h]hDRM_IOCTL_I915_GETPARAM}(hj.8hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj&8ubh and engine identifiers like }(hj&8hhhNhNubji )}(h`I915_PARAM_HAS_BLT`h]hI915_PARAM_HAS_BLT}(hj@8hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj&8ubh.}(hj&8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hThe need for this interface came starting with Icelake and newer GPUs, which started to establish a pattern of having multiple engines of a same class, where not all instances were always completely functionally equivalent.h]hThe need for this interface came starting with Icelake and newer GPUs, which started to establish a pattern of having multiple engines of a same class, where not all instances were always completely functionally equivalent.}(hjY8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hqEntry point for this uapi is `DRM_IOCTL_I915_QUERY` with the `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.h](hEntry point for this uapi is }(hjh8hhhNhNubji )}(h`DRM_IOCTL_I915_QUERY`h]hDRM_IOCTL_I915_QUERY}(hjp8hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjh8ubh with the }(hjh8hhhNhNubji )}(h`DRM_I915_QUERY_ENGINE_INFO`h]hDRM_I915_QUERY_ENGINE_INFO#}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjh8ubh as the queried item id.}(hjh8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h(Example for getting the list of engines:h]h(Example for getting the list of engines:}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubjt)}(hXstruct drm_i915_query_engine_info *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_ENGINE_INFO; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of engines. The kernel will fill out the // item.length for us, which is the number of bytes we need. // // Alternatively a large buffer can be allocated straightaway enabling // querying in one pass, in which case item.length should contain the // length of the provided buffer. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with info on all engines. item.data_ptr = (uintptr_t)&info; err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each engine in the array for (i = 0; i < info->num_engines; i++) { struct drm_i915_engine_info einfo = info->engines[i]; u16 class = einfo.engine.class; u16 instance = einfo.engine.instance; .... } free(info);h]hXstruct drm_i915_query_engine_info *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_ENGINE_INFO; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of engines. The kernel will fill out the // item.length for us, which is the number of bytes we need. // // Alternatively a large buffer can be allocated straightaway enabling // querying in one pass, in which case item.length should contain the // length of the provided buffer. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with info on all engines. item.data_ptr = (uintptr_t)&info; err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each engine in the array for (i = 0; i < info->num_engines; i++) { struct drm_i915_engine_info einfo = info->engines[i]; u16 class = einfo.engine.class; u16 instance = einfo.engine.instance; .... } free(info);}hj8sbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hEach of the enumerated engines, apart from being defined by its class and instance (see `struct i915_engine_class_instance`), also can have flags and capabilities defined as documented in i915_drm.h.h](hXEach of the enumerated engines, apart from being defined by its class and instance (see }(hj8hhhNhNubji )}(h#`struct i915_engine_class_instance`h]h!struct i915_engine_class_instance}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj8ubhL), also can have flags and capabilities defined as documented in i915_drm.h.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(h{For instance video engines which support HEVC encoding will have the `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.h](hEFor instance video engines which support HEVC encoding will have the }(hj8hhhNhNubji )}(h"`I915_VIDEO_CLASS_CAPABILITY_HEVC`h]h I915_VIDEO_CLASS_CAPABILITY_HEVC}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jh hj8ubh capability bit set.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hEngine discovery only fully comes to its own when combined with the new way of addressing engines when submitting batch buffers using contexts with engine maps configured.h]hEngine discovery only fully comes to its own when combined with the new way of addressing engines when submitting batch buffers using contexts with engine maps configured.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_i915_engine_info (C struct)c.drm_i915_engine_infohNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_engine_infoh]j)}(hstruct drm_i915_engine_infoh](j)}(hjh]hstruct}(hj$9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 9hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj29hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 9hhhj19hM ubj)}(hdrm_i915_engine_infoh]j)}(hj9h]hdrm_i915_engine_info}(hjD9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@9ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj 9hhhj19hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj9hhhj19hM ubah}(h]j9ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj19hM hj9hhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hj9hhhj19hM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjo9jLjo9jMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; }; **Members** ``engine`` Engine class and instance. ``rsvd0`` Reserved field. ``flags`` Engine flags. ``capabilities`` Capabilities of this engine. ``logical_instance`` Logical instance of engine ``rsvd1`` Reserved fields. ``rsvd2`` Reserved fields.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj{9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjw9ubh:}(hjw9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjs9ubjt)}(hXstruct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; };h]hXstruct drm_i915_engine_info { struct i915_engine_class_instance engine; __u32 rsvd0; __u64 flags; #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0); __u64 capabilities; #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0); #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1); __u16 logical_instance; __u16 rsvd1[3]; __u64 rsvd2[3]; };}hj9sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjs9ubh)}(h **Members**h]h)}(hj9h]hMembers}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjs9ubj )}(hhh](j)}(h&``engine`` Engine class and instance. h](j)}(h ``engine``h]j)}(hj9h]hengine}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj9ubj()}(hhh]h)}(hEngine class and instance.h]hEngine class and instance.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hM hj9ubah}(h]h ]h"]h$]h&]uh1j'hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hM hj9ubj)}(h``rsvd0`` Reserved field. h](j)}(h ``rsvd0``h]j)}(hj9h]hrsvd0}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj9ubj()}(hhh]h)}(hReserved field.h]hReserved field.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hM hj:ubah}(h]h ]h"]h$]h&]uh1j'hj9ubeh}(h]h ]h"]h$]h&]uh1jhj:hM hj9ubj)}(h``flags`` Engine flags. h](j)}(h ``flags``h]j)}(hj6:h]hflags}(hj8:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4:ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj0:ubj()}(hhh]h)}(h Engine flags.h]h Engine flags.}(hjO:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjK:hM hjL:ubah}(h]h ]h"]h$]h&]uh1j'hj0:ubeh}(h]h ]h"]h$]h&]uh1jhjK:hM hj9ubj)}(h.``capabilities`` Capabilities of this engine. h](j)}(h``capabilities``h]j)}(hjo:h]h capabilities}(hjq:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm:ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hji:ubj()}(hhh]h)}(hCapabilities of this engine.h]hCapabilities of this engine.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hM hj:ubah}(h]h ]h"]h$]h&]uh1j'hji:ubeh}(h]h ]h"]h$]h&]uh1jhj:hM hj9ubj)}(h0``logical_instance`` Logical instance of engine h](j)}(h``logical_instance``h]j)}(hj:h]hlogical_instance}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM" hj:ubj()}(hhh]h)}(hLogical instance of engineh]hLogical instance of engine}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hM" hj:ubah}(h]h ]h"]h$]h&]uh1j'hj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hM" hj9ubj)}(h``rsvd1`` Reserved fields. h](j)}(h ``rsvd1``h]j)}(hj:h]hrsvd1}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM% hj:ubj()}(hhh]h)}(hReserved fields.h]hReserved fields.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hM% hj:ubah}(h]h ]h"]h$]h&]uh1j'hj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hM% hj9ubj)}(h``rsvd2`` Reserved fields.h](j)}(h ``rsvd2``h]j)}(hj;h]hrsvd2}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM& hj;ubj()}(hhh]h)}(hReserved fields.h]hReserved fields.}(hj3;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM' hj0;ubah}(h]h ]h"]h$]h&]uh1j'hj;ubeh}(h]h ]h"]h$]h&]uh1jhj/;hM& hj9ubeh}(h]h ]h"]h$]h&]uh1j hjs9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj];h]h Description}(hj_;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[;ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM* hhhhubh)}(hADescribes one engine and its capabilities as known to the driver.h]hADescribes one engine and its capabilities as known to the driver.}(hjs;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_i915_query_engine_info (C struct)c.drm_i915_query_engine_infohNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_engine_infoh]j)}(h!struct drm_i915_query_engine_infoh](j)}(hjh]hstruct}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhj;hM ubj)}(hdrm_i915_query_engine_infoh]j)}(hj;h]hdrm_i915_query_engine_info}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj;hhhj;hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj;hhhj;hM ubah}(h]j;ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj;hM hj;hhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hj;hhhj;hM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj;jLj;jMjNjOuh1jhhhhhNhNubjQ)}(hX;**Definition**:: struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; }; **Members** ``num_engines`` Number of struct drm_i915_engine_info structs following. ``rsvd`` MBZ ``engines`` Marker for drm_i915_engine_info structures.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;ubh:}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM/ hj;ubjt)}(h{struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; };h]h{struct drm_i915_query_engine_info { __u32 num_engines; __u32 rsvd[3]; struct drm_i915_engine_info engines[]; };}hj <sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM1 hj;ubh)}(h **Members**h]h)}(hj<h]hMembers}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7 hj;ubj )}(hhh](j)}(hI``num_engines`` Number of struct drm_i915_engine_info structs following. h](j)}(h``num_engines``h]j)}(hj;<h]h num_engines}(hj=<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9<ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2 hj5<ubj()}(hhh]h)}(h8Number of struct drm_i915_engine_info structs following.h]h8Number of struct drm_i915_engine_info structs following.}(hjT<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP<hM2 hjQ<ubah}(h]h ]h"]h$]h&]uh1j'hj5<ubeh}(h]h ]h"]h$]h&]uh1jhjP<hM2 hj2<ubj)}(h ``rsvd`` MBZ h](j)}(h``rsvd``h]j)}(hjt<h]hrsvd}(hjv<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjr<ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5 hjn<ubj()}(hhh]h)}(hMBZh]hMBZ}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM5 hj<ubah}(h]h ]h"]h$]h&]uh1j'hjn<ubeh}(h]h ]h"]h$]h&]uh1jhj<hM5 hj2<ubj)}(h7``engines`` Marker for drm_i915_engine_info structures.h](j)}(h ``engines``h]j)}(hj<h]hengines}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM7 hj<ubj()}(hhh]h)}(h+Marker for drm_i915_engine_info structures.h]h+Marker for drm_i915_engine_info structures.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM8 hj<ubah}(h]h ]h"]h$]h&]uh1j'hj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hM7 hj2<ubeh}(h]h ]h"]h$]h&]uh1j hj;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj<h]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM; hhhhubh)}(h~Engine info query enumerates all engines known to the driver by filling in an array of struct drm_i915_engine_info structures.h]h~Engine info query enumerates all engines known to the driver by filling in an array of struct drm_i915_engine_info structures.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM, hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_i915_query_perf_config (C struct)c.drm_i915_query_perf_confighNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_perf_configh]j)}(h!struct drm_i915_query_perf_configh](j)}(hjh]hstruct}(hj.=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*=hhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2 ubj)}(h h]h }(hj<=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*=hhhj;=hM2 ubj)}(hdrm_i915_query_perf_configh]j)}(hj(=h]hdrm_i915_query_perf_config}(hjN=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJ=ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj*=hhhj;=hM2 ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj&=hhhj;=hM2 ubah}(h]j!=ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj;=hM2 hj#=hhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hj#=hhhj;=hM2 ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjy=jLjy=jMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; }; **Members** ``{unnamed_union}`` anonymous ``n_configs`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available. ``config`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. ``uuid`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. String formatted like "``08x-````04x-````04x-````04x-````012x``" ``flags`` Unused for now. Must be cleared to zero. ``data`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers. When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created : - :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubh:}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM@ hj}=ubjt)}(hstruct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; };h]hstruct drm_i915_query_perf_config { union { __u64 n_configs; __u64 config; char uuid[36]; }; __u32 flags; __u8 data[]; };}hj=sbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMB hj}=ubh)}(h **Members**h]h)}(hj=h]hMembers}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhML hj}=ubj )}(hhh](j)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hj=h]h{unnamed_union}}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhj=ubj()}(hhh]h)}(h anonymoush]h anonymous}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hKhj=ubah}(h]h ]h"]h$]h&]uh1j'hj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hKhj=ubj)}(h``n_configs`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available. h](j)}(h ``n_configs``h]j)}(hj>h]h n_configs}(hj >hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMG hj>ubj()}(hhh]h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 sets this fields to the number of configurations available.h](hWhen }(hj >hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj*>h]hdrm_i915_query_item.flags}(hj,>hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj(>ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhME hj >ubh == }(hj >hhhNhNubj)}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hjL>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj >ubhB, i915 sets this fields to the number of configurations available.}(hj >hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjG>hME hj>ubah}(h]h ]h"]h$]h&]uh1j'hj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMG hj=ubj)}(h``config`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. h](j)}(h ``config``h]j)}(hjv>h]hconfig}(hjx>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt>ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMQ hjp>ubj()}(hhh]h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.h](hWhen }(hj>hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj>h]hdrm_i915_query_item.flags}(hj>hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMN hj>ubh == }(hj>hhhNhNubj)}(h*``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID``h]h&DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubhq, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj>hMN hj>ubah}(h]h ]h"]h$]h&]uh1j'hjp>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMQ hj=ubj)}(hX+``uuid`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr. String formatted like "``08x-````04x-````04x-````04x-````012x``" h](j)}(h``uuid``h]j)}(hj>h]huuid}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM] hj>ubj()}(hhh](h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.h](hWhen }(hj>hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj?h]hdrm_i915_query_item.flags}(hj ?hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMX hj>ubh == }(hj>hhhNhNubj)}(h,``DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID``h]h(DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID}(hj*?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubhq, i915 will use the value in this field as configuration identifier to decide what data to write into config_ptr.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj%?hMX hj>ubh)}(h@String formatted like "``08x-````04x-````04x-````04x-````012x``"h](hString formatted like “}(hjB?hhhNhNubj)}(h(``08x-````04x-````04x-````04x-````012x``h]h$08x-````04x-````04x-````04x-````012x}(hjJ?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB?ubh”}(hjB?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj>hM] hj>ubeh}(h]h ]h"]h$]h&]uh1j'hj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hM] hj=ubj)}(h3``flags`` Unused for now. Must be cleared to zero. h](j)}(h ``flags``h]j)}(hjt?h]hflags}(hjv?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjr?ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMe hjn?ubj()}(hhh]h)}(h(Unused for now. Must be cleared to zero.h]h(Unused for now. Must be cleared to zero.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMe hj?ubah}(h]h ]h"]h$]h&]uh1j'hjn?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMe hj=ubj)}(hX``data`` When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers. When :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created : - :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h](j)}(h``data``h]j)}(hj?h]hdata}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMv hj?ubj()}(hhh](h)}(hWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_LIST``, i915 will write an array of __u64 of configuration identifiers.h](hWhen }(hj?hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj?h]hdrm_i915_query_item.flags}(hj?hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMl hj?ubh == }(hj?hhhNhNubj)}(h#``DRM_I915_QUERY_PERF_CONFIG_LIST``h]hDRM_I915_QUERY_PERF_CONFIG_LIST}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubhA, i915 will write an array of __u64 of configuration identifiers.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj?hMl hj?ubh)}(hXNWhen :c:type:`drm_i915_query_item.flags ` == ``DRM_I915_QUERY_PERF_CONFIG_DATA``, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created :h](hWhen }(hj @hhhNhNubh)}(h9:c:type:`drm_i915_query_item.flags `h]j)}(hj@h]hdrm_i915_query_item.flags}(hj@hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMo hj @ubh == }(hj @hhhNhNubj)}(h#``DRM_I915_QUERY_PERF_CONFIG_DATA``h]hDRM_I915_QUERY_PERF_CONFIG_DATA}(hj6@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj @ubh, i915 will write a struct drm_i915_perf_oa_config. If the following fields of struct drm_i915_perf_oa_config are not set to 0, i915 will write into the associated pointers the values of submitted when the configuration was created :}(hj @hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj1@hMo hj?ubj)}(h- :c:type:`drm_i915_perf_oa_config.n_mux_regs ` - :c:type:`drm_i915_perf_oa_config.n_boolean_regs ` - :c:type:`drm_i915_perf_oa_config.n_flex_regs `h]j )}(hhh](j )}(hF:c:type:`drm_i915_perf_oa_config.n_mux_regs `h]h)}(hjW@h]h)}(hjW@h]j)}(hjW@h]h"drm_i915_perf_oa_config.n_mux_regs}(hj_@hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj\@ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_perf_oa_configuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMu hjY@ubah}(h]h ]h"]h$]h&]uh1hhjz@hMu hjU@ubah}(h]h ]h"]h$]h&]uh1j hjR@ubj )}(hJ:c:type:`drm_i915_perf_oa_config.n_boolean_regs `h]h)}(hj@h]h)}(hj@h]j)}(hj@h]h&drm_i915_perf_oa_config.n_boolean_regs}(hj@hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_perf_oa_configuh1hhj?hMv hj@ubah}(h]h ]h"]h$]h&]uh1hhj?hMv hj@ubah}(h]h ]h"]h$]h&]uh1j hjR@ubj )}(hG:c:type:`drm_i915_perf_oa_config.n_flex_regs `h]h)}(hj@h]h)}(hj@h]j)}(hj@h]h#drm_i915_perf_oa_config.n_flex_regs}(hj@hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_perf_oa_configuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMw hj@ubah}(h]h ]h"]h$]h&]uh1hhj@hMw hj@ubah}(h]h ]h"]h$]h&]uh1j hjR@ubeh}(h]h ]h"]h$]h&]j) j* uh1j hjz@hMu hjN@ubah}(h]h ]h"]h$]h&]uh1jhjz@hMu hj?ubeh}(h]h ]h"]h$]h&]uh1j'hj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMv hj=ubeh}(h]h ]h"]h$]h&]uh1j hj}=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjAh]h Description}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMz hhhhubh)}(hoData written by the kernel with query ``DRM_I915_QUERY_PERF_CONFIG`` and ``DRM_I915_QUERY_GEOMETRY_SUBSLICES``.h](h&Data written by the kernel with query }(hj'AhhhNhNubj)}(h``DRM_I915_QUERY_PERF_CONFIG``h]hDRM_I915_QUERY_PERF_CONFIG}(hj/AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'Aubh and }(hj'AhhhNhNubj)}(h%``DRM_I915_QUERY_GEOMETRY_SUBSLICES``h]h!DRM_I915_QUERY_GEOMETRY_SUBSLICES}(hjAAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'Aubh.}(hj'AhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM= hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_memory_class (C enum)c.drm_i915_gem_memory_classhNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_memory_classh]j)}(henum drm_i915_gem_memory_classh](j)}(hjSh]henum}(hjsAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoAhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMC ubj)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoAhhhjAhMC ubj)}(hdrm_i915_gem_memory_classh]j)}(hjmAh]hdrm_i915_gem_memory_class}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ](j jeh"]h$]h&]jjuh1jhjoAhhhjAhMC ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjkAhhhjAhMC ubah}(h]jfAah ](j j!eh"]h$]h&]j%j&)j'huh1jhjAhMC hjhAhhubj))}(hhh]h)}(hSupported memory classesh]hSupported memory classes}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM~ hjAhhubah}(h]h ]h"]h$]h&]uh1j(hjhAhhhjAhMC ubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjAjLjAjMjNjOuh1jhhhhhNhNubjQ)}(ho**Constants** ``I915_MEMORY_CLASS_SYSTEM`` System memory ``I915_MEMORY_CLASS_DEVICE`` Device local-memoryh](h)}(h **Constants**h]h)}(hjAh]h Constants}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjAubj )}(hhh](j)}(h+``I915_MEMORY_CLASS_SYSTEM`` System memory h](j)}(h``I915_MEMORY_CLASS_SYSTEM``h]j)}(hjAh]hI915_MEMORY_CLASS_SYSTEM}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjAubj()}(hhh]h)}(h System memoryh]h System memory}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj BhM hj Bubah}(h]h ]h"]h$]h&]uh1j'hjAubeh}(h]h ]h"]h$]h&]uh1jhj BhM hjAubj)}(h0``I915_MEMORY_CLASS_DEVICE`` Device local-memoryh](j)}(h``I915_MEMORY_CLASS_DEVICE``h]j)}(hj/Bh]hI915_MEMORY_CLASS_DEVICE}(hj1BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-Bubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj)Bubj()}(hhh]h)}(hDevice local-memoryh]hDevice local-memory}(hjHBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjEBubah}(h]h ]h"]h$]h&]uh1j'hj)Bubeh}(h]h ]h"]h$]h&]uh1jhjDBhM hjAubeh}(h]h ]h"]h$]h&]uh1j hjAubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j-drm_i915_gem_memory_class_instance (C struct)$c.drm_i915_gem_memory_class_instancehNtauh1jhhhhhNhNubj)}(hhh](j)}(h"drm_i915_gem_memory_class_instanceh]j)}(h)struct drm_i915_gem_memory_class_instanceh](j)}(hjh]hstruct}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBhhhjBhM ubj)}(h"drm_i915_gem_memory_class_instanceh]j)}(hjBh]h"drm_i915_gem_memory_class_instance}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ](j jeh"]h$]h&]jjuh1jhjBhhhjBhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjBhhhjBhM ubah}(h]j|Bah ](j j!eh"]h$]h&]j%j&)j'huh1jhjBhM hj~Bhhubj))}(hhh]h)}(h!Identify particular memory regionh]h!Identify particular memory region}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBhhubah}(h]h ]h"]h$]h&]uh1j(hj~BhhhjBhM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjBjLjBjMjNjOuh1jhhhhhNhNubjQ)}(h**Definition**:: struct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; }; **Members** ``memory_class`` See enum drm_i915_gem_memory_class ``memory_instance`` Which instanceh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBubh:}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBubjt)}(hastruct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; };h]hastruct drm_i915_gem_memory_class_instance { __u16 memory_class; __u16 memory_instance; };}hjCsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBubh)}(h **Members**h]h)}(hjCh]hMembers}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjBubj )}(hhh](j)}(h4``memory_class`` See enum drm_i915_gem_memory_class h](j)}(h``memory_class``h]j)}(hj8Ch]h memory_class}(hj:ChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6Cubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj2Cubj()}(hhh]h)}(h"See enum drm_i915_gem_memory_classh]h"See enum drm_i915_gem_memory_class}(hjQChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMChM hjNCubah}(h]h ]h"]h$]h&]uh1j'hj2Cubeh}(h]h ]h"]h$]h&]uh1jhjMChM hj/Cubj)}(h"``memory_instance`` Which instanceh](j)}(h``memory_instance``h]j)}(hjqCh]hmemory_instance}(hjsChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoCubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjkCubj()}(hhh]h)}(hWhich instanceh]hWhich instance}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjCubah}(h]h ]h"]h$]h&]uh1j'hjkCubeh}(h]h ]h"]h$]h&]uh1jhjChM hj/Cubeh}(h]h ]h"]h$]h&]uh1j hjBubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&drm_i915_memory_region_info (C struct)c.drm_i915_memory_region_infohNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_memory_region_infoh]j)}(h"struct drm_i915_memory_region_infoh](j)}(hjh]hstruct}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjChhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjChhhjChM ubj)}(hdrm_i915_memory_region_infoh]j)}(hjCh]hdrm_i915_memory_region_info}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ](j jeh"]h$]h&]jjuh1jhjChhhjChM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjChhhjChM ubah}(h]jCah ](j j!eh"]h$]h&]j%j&)j'huh1jhjChM hjChhubj))}(hhh]h)}(h,Describes one region as known to the driver.h]h,Describes one region as known to the driver.}(hj DhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj Dhhubah}(h]h ]h"]h$]h&]uh1j(hjChhhjChM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj%DjLj%DjMjNjOuh1jhhhhhNhNubjQ)}(hX **Definition**:: struct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; }; **Members** ``region`` The class:instance pair encoding ``rsvd0`` MBZ ``probed_size`` Memory probed by the driver Note that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields. ``unallocated_size`` Estimate of memory remaining Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the **probed_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). ``{unnamed_union}`` anonymous ``rsvd1`` MBZ ``{unnamed_struct}`` anonymous ``probed_cpu_visible_size`` Memory probed by the driver that is CPU accessible. This will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible. On systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). Note that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**. ``unallocated_cpu_visible_size`` Estimate of CPU visible memory remaining. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**). Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**). If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj1DhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-Dubh:}(hj-DhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj)Dubjt)}(hXCstruct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; };h]hXCstruct drm_i915_memory_region_info { struct drm_i915_gem_memory_class_instance region; __u32 rsvd0; __u64 probed_size; __u64 unallocated_size; union { __u64 rsvd1[8]; struct { __u64 probed_cpu_visible_size; __u64 unallocated_cpu_visible_size; }; }; };}hjJDsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj)Dubh)}(h **Members**h]h)}(hj[Dh]hMembers}(hj]DhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYDubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj)Dubj )}(hhh](j)}(h,``region`` The class:instance pair encoding h](j)}(h ``region``h]j)}(hjzDh]hregion}(hj|DhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxDubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjtDubj()}(hhh]h)}(h The class:instance pair encodingh]h The class:instance pair encoding}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhM hjDubah}(h]h ]h"]h$]h&]uh1j'hjtDubeh}(h]h ]h"]h$]h&]uh1jhjDhM hjqDubj)}(h``rsvd0`` MBZ h](j)}(h ``rsvd0``h]j)}(hjDh]hrsvd0}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjDubj()}(hhh]h)}(hMBZh]hMBZ}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhM hjDubah}(h]h ]h"]h$]h&]uh1j'hjDubeh}(h]h ]h"]h$]h&]uh1jhjDhM hjqDubj)}(hX ``probed_size`` Memory probed by the driver Note that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields. h](j)}(h``probed_size``h]j)}(hjDh]h probed_size}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjDubj()}(hhh](h)}(hMemory probed by the driverh]hMemory probed by the driver}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjEubh)}(hNote that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields.h]hNote that it should not be possible to ever encounter a zero value here, also note that no current region type will ever return -1 here. Although for future region types, this might be a possibility. The same applies to the other size fields.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjEubeh}(h]h ]h"]h$]h&]uh1j'hjDubeh}(h]h ]h"]h$]h&]uh1jhjEhM hjqDubj)}(hXi``unallocated_size`` Estimate of memory remaining Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the **probed_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). h](j)}(h``unallocated_size``h]j)}(hj5Eh]hunallocated_size}(hj7EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3Eubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj/Eubj()}(hhh](h)}(hEstimate of memory remainingh]hEstimate of memory remaining}(hjNEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjKEubh)}(hX5Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this (or if this is an older kernel) the value here will always equal the **probed_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**).h](hRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. 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Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hj]EhhhNhNubh)}(h**probed_size**h]h probed_size}(hjwEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]Eubh).}(hj]EhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjKEubeh}(h]h ]h"]h$]h&]uh1j'hj/Eubeh}(h]h ]h"]h$]h&]uh1jhjJEhM hjqDubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjEh]h{unnamed_union}}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjEubj()}(hhh]h)}(h anonymoush]h anonymous}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhKhjEubah}(h]h ]h"]h$]h&]uh1j'hjEubeh}(h]h ]h"]h$]h&]uh1jhjEhKhjqDubj)}(h``rsvd1`` MBZ h](j)}(h ``rsvd1``h]j)}(hjEh]hrsvd1}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjEubj()}(hhh]h)}(hMBZh]hMBZ}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhM hjEubah}(h]h ]h"]h$]h&]uh1j'hjEubeh}(h]h ]h"]h$]h&]uh1jhjEhM hjqDubj)}(h``{unnamed_struct}`` anonymous h](j)}(h``{unnamed_struct}``h]j)}(hjFh]h{unnamed_struct}}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhKhjFubj()}(hhh]h)}(h anonymoush]h anonymous}(hj-FhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)FhKhj*Fubah}(h]h ]h"]h$]h&]uh1j'hjFubeh}(h]h ]h"]h$]h&]uh1jhj)FhKhjqDubj)}(hXs``probed_cpu_visible_size`` Memory probed by the driver that is CPU accessible. This will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible. On systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**). Note that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**. h](j)}(h``probed_cpu_visible_size``h]j)}(hjMFh]hprobed_cpu_visible_size}(hjOFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKFubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjGFubj()}(hhh](h)}(h3Memory probed by the driver that is CPU accessible.h]h3Memory probed by the driver that is CPU accessible.}(hjfFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjcFubh)}(hjThis will be always be <= **probed_size**, and the remainder (if there is any) will not be CPU accessible.h](hThis will be always be <= }(hjuFhhhNhNubh)}(h**probed_size**h]h probed_size}(hj}FhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuFubhA, and the remainder (if there is any) will not be CPU accessible.}(hjuFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjcFubh)}(hOn systems without small BAR, the **probed_size** will always equal the **probed_cpu_visible_size**, since all of it will be CPU accessible.h](h"On systems without small BAR, the }(hjFhhhNhNubh)}(h**probed_size**h]h probed_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh will always equal the }(hjFhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh), since all of it will be CPU accessible.}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjcFubh)}(hNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_size**).h](huNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hjFhhhNhNubh)}(h**probed_size**h]h probed_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh).}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjcFubh)}(hXNote that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when **probed_cpu_visible_size** == **probed_size**.h](hXpNote that if the value returned here is zero, then this must be an old kernel which lacks the relevant small-bar uAPI support (including I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on such systems we should never actually end up with a small BAR configuration, assuming we are able to load the kernel module. Hence it should be safe to treat this the same as when }(hjFhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh == }(hjFhhhNhNubh)}(h**probed_size**h]h probed_size}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubh.}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjcFubeh}(h]h ]h"]h$]h&]uh1j'hjGFubeh}(h]h ]h"]h$]h&]uh1jhjbFhM hjqDubj)}(hXr``unallocated_cpu_visible_size`` Estimate of CPU visible memory remaining. Note this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**). Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**). If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](j)}(h ``unallocated_cpu_visible_size``h]j)}(hj/Gh]hunallocated_cpu_visible_size}(hj1GhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-Gubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hj)Gubj()}(hhh](h)}(h)Estimate of CPU visible memory remaining.h]h)Estimate of CPU visible memory remaining.}(hjHGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjEGubh)}(hNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the **probed_cpu_visible_size**).h](huNote this is only tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will always equal the }(hjWGhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hj_GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWGubh).}(hjWGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjEGubh)}(hX3Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the **probed_cpu_visible_size**. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the **probed_cpu_visible_size**).h](huRequires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. Without this the value here will always equal the }(hjxGhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxGubh. Note this is only currently tracked for I915_MEMORY_CLASS_DEVICE regions (for other types the value here will also always equal the }(hjxGhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxGubh).}(hjxGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjEGubh)}(h]If this is an older kernel the value here will be zero, see also **probed_cpu_visible_size**.h](hAIf this is an older kernel the value here will be zero, see also }(hjGhhhNhNubh)}(h**probed_cpu_visible_size**h]hprobed_cpu_visible_size}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjDGhM hjEGubeh}(h]h ]h"]h$]h&]uh1j'hj)Gubeh}(h]h ]h"]h$]h&]uh1jhjDGhM hjqDubeh}(h]h ]h"]h$]h&]uh1j hj)Dubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjGh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hNote this is using both struct drm_i915_query_item and struct drm_i915_query. For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS at :c:type:`drm_i915_query_item.query_id `.h](hNote this is using both struct drm_i915_query_item and struct drm_i915_query. For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS at }(hjGhhhNhNubh)}(h<:c:type:`drm_i915_query_item.query_id `h]j)}(hjHh]hdrm_i915_query_item.query_id}(hjHhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_query_itemuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hjGubh.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj#HhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(drm_i915_query_memory_regions (C struct)c.drm_i915_query_memory_regionshNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_query_memory_regionsh]j)}(h$struct drm_i915_query_memory_regionsh](j)}(hjh]hstruct}(hjGHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCHhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM ubj)}(h h]h }(hjUHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCHhhhjTHhM ubj)}(hdrm_i915_query_memory_regionsh]j)}(hjAHh]hdrm_i915_query_memory_regions}(hjgHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcHubah}(h]h ](j jeh"]h$]h&]jjuh1jhjCHhhhjTHhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj?HhhhjTHhM ubah}(h]j:Hah ](j j!eh"]h$]h&]j%j&)j'huh1jhjTHhM hjnum_regions; i++) { struct drm_i915_memory_region_info mr = info->regions[i]; u16 class = mr.region.class; u16 instance = mr.region.instance; .... } free(info);h]hXVstruct drm_i915_query_memory_regions *info; struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_MEMORY_REGIONS; }; struct drm_i915_query query = { .num_items = 1, .items_ptr = (uintptr_t)&item, }; int err, i; // First query the size of the blob we need, this needs to be large // enough to hold our array of regions. The kernel will fill out the // item.length for us, which is the number of bytes we need. err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... info = calloc(1, item.length); // Now that we allocated the required number of bytes, we call the ioctl // again, this time with the data_ptr pointing to our newly allocated // blob, which the kernel can then populate with the all the region info. item.data_ptr = (uintptr_t)&info, err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); if (err) ... // We can now access each region in the array for (i = 0; i < info->num_regions; i++) { struct drm_i915_memory_region_info mr = info->regions[i]; u16 class = mr.region.class; u16 instance = mr.region.instance; .... } free(info);}hjIsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j0drm_i915_query_guc_submission_version (C struct)'c.drm_i915_query_guc_submission_versionhNtauh1jhhhhhNhNubj)}(hhh](j)}(h%drm_i915_query_guc_submission_versionh]j)}(h,struct drm_i915_query_guc_submission_versionh](j)}(hjh]hstruct}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhhjJhMubj)}(h%drm_i915_query_guc_submission_versionh]j)}(hjIh]h%drm_i915_query_guc_submission_version}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubah}(h]h ](j jeh"]h$]h&]jjuh1jhjIhhhjJhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjIhhhjJhMubah}(h]jIah ](j j!eh"]h$]h&]j%j&)j'huh1jhjJhMhjIhhubj))}(hhh]h)}(h&query GuC submission interface versionh]h&query GuC submission interface version}(hj;JhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM(hj8Jhhubah}(h]h ]h"]h$]h&]uh1j(hjIhhhjJhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjSJjLjSJjMjNjOuh1jhhhhhNhNubjQ)}(hX7**Definition**:: struct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; }; **Members** ``branch`` Firmware branch version. ``major`` Firmware major version. ``minor`` Firmware minor version. ``patch`` Firmware patch version.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj_JhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[Jubh:}(hj[JhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM,hjWJubjt)}(hvstruct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; };h]hvstruct drm_i915_query_guc_submission_version { __u32 branch; __u32 major; __u32 minor; __u32 patch; };}hjxJsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM.hjWJubh)}(h **Members**h]h)}(hjJh]hMembers}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM5hjWJubj )}(hhh](j)}(h$``branch`` Firmware branch version. h](j)}(h ``branch``h]j)}(hjJh]hbranch}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM,hjJubj()}(hhh]h)}(hFirmware branch version.h]hFirmware branch version.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhM,hjJubah}(h]h ]h"]h$]h&]uh1j'hjJubeh}(h]h ]h"]h$]h&]uh1jhjJhM,hjJubj)}(h"``major`` Firmware major version. h](j)}(h ``major``h]j)}(hjJh]hmajor}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM.hjJubj()}(hhh]h)}(hFirmware major version.h]hFirmware major version.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhM.hjJubah}(h]h ]h"]h$]h&]uh1j'hjJubeh}(h]h ]h"]h$]h&]uh1jhjJhM.hjJubj)}(h"``minor`` Firmware minor version. h](j)}(h ``minor``h]j)}(hjKh]hminor}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM0hjKubj()}(hhh]h)}(hFirmware minor version.h]hFirmware minor version.}(hj3KhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/KhM0hj0Kubah}(h]h ]h"]h$]h&]uh1j'hjKubeh}(h]h ]h"]h$]h&]uh1jhj/KhM0hjJubj)}(h!``patch`` Firmware patch version.h](j)}(h ``patch``h]j)}(hjSKh]hpatch}(hjUKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQKubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM1hjMKubj()}(hhh]h)}(hFirmware patch version.h]hFirmware patch version.}(hjlKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM2hjiKubah}(h]h ]h"]h$]h&]uh1j'hjMKubeh}(h]h ]h"]h$]h&]uh1jhjhKhM1hjJubeh}(h]h ]h"]h$]h&]uh1j hjWJubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h.. _GuC HWCONFIG blob uAPI:h]h}(h]h ]h"]h$]h&]hguc-hwconfig-blob-uapiuh1hhMmhhhhhNubh)}(h**GuC HWCONFIG blob uAPI**h]h)}(hjKh]hGuC HWCONFIG blob uAPI}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKubah}(h]jKah ]h"]guc hwconfig blob uapiah$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM8hhhhj}jKjKsj }jKjKsubh)}(hThe GuC produces a blob with information about the current device. i915 reads this blob from GuC and makes it available via this uAPI.h]hThe GuC produces a blob with information about the current device. i915 reads this blob from GuC and makes it available via this uAPI.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM6hhhhubh)}(h_The format and meaning of the blob content are documented in the Programmer's Reference Manual.h]haThe format and meaning of the blob content are documented in the Programmer’s Reference Manual.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM9hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_i915_gem_create_ext (C struct)c.drm_i915_gem_create_exthNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_create_exth]j)}(hstruct drm_i915_gem_create_exth](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM?ubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKhhhjKhM?ubj)}(hdrm_i915_gem_create_exth]j)}(hjKh]hdrm_i915_gem_create_ext}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Lubah}(h]h ](j jeh"]h$]h&]jjuh1jhjKhhhjKhM?ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjKhhhjKhM?ubah}(h]jKah ](j j!eh"]h$]h&]j%j&)j'huh1jhjKhM?hjKhhubj))}(hhh]h)}(h]Existing gem_create behaviour, with added extension support using struct i915_user_extension.h]h]Existing gem_create behaviour, with added extension support using struct i915_user_extension.}(hj3LhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM@hj0Lhhubah}(h]h ]h"]h$]h&]uh1j(hjKhhhjKhM?ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjKLjLjKLjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; }; **Members** ``size`` Requested size for the object. The (page-aligned) allocated size for the object will be returned. On platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects. NOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications: 1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. However on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K. ``handle`` Returned handle for the object. Object handles are nonzero. ``flags`` Optional flags. Supported values: I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU. Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size ` for how to determine if this system applies. Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE. Also note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS. Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided. On older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed. ``extensions`` The chain of extensions to apply to this object. This will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension. If we don't supply any extensions then we get the same old gem_create behaviour. For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions. For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content. For I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjWLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjSLubh:}(hjSLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMDhjOLubjt)}(hX.struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; };h]hX.struct drm_i915_gem_create_ext { __u64 size; __u32 handle; #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0); __u32 flags; #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0; #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1; #define I915_GEM_CREATE_EXT_SET_PAT 2; __u64 extensions; };}hjpLsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMFhjOLubh)}(h **Members**h]h)}(hjLh]hMembers}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMQhjOLubj )}(hhh](j)}(hX``size`` Requested size for the object. The (page-aligned) allocated size for the object will be returned. On platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects. NOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications: 1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. However on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K. h](j)}(h``size``h]j)}(hjLh]hsize}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMbhjLubj()}(hhh](h)}(hRequested size for the object.h]hRequested size for the object.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMLhjLubh)}(hBThe (page-aligned) allocated size for the object will be returned.h]hBThe (page-aligned) allocated size for the object will be returned.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMNhjLubh)}(hOn platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects.h]hOn platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMPhjLubh)}(hNOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications:h]hNOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications:}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMThjLubj)}(h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. h](h)}(h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware.h]h1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMXhjLubh)}(hI2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects.h]hI2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM\hjLubeh}(h]h ]h"]h$]h&]uh1jhjMhMXhjLubh)}(hHowever on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K.h]hHowever on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM_hjLubeh}(h]h ]h"]h$]h&]uh1j'hjLubeh}(h]h ]h"]h$]h&]uh1jhjLhMbhjLubj)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]j)}(hj>Mh]hhandle}(hj@MhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj` for how to determine if this system applies. Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE. Also note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS. Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided. On older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed. h](j)}(h ``flags``h]j)}(hjMh]hflags}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjMubj()}(hhh](h)}(hOptional flags.h]hOptional flags.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMnhjMubh)}(hSupported values:h]hSupported values:}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMphjMubh)}(hvI915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU.h]hvI915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMrhjMubh)}(hXOnly valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size ` for how to determine if this system applies.h](hXOnly valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it’s something we can expect to see in the wild. See }(hjMhhhNhNubh)}(h[:c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `h]j)}(hjMh]h3drm_i915_memory_region_info.probed_cpu_visible_size}(hjMhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_memory_region_infouh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMuhjMubh- for how to determine if this system applies.}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjMhMuhjMubh)}(hNote that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE.h]hNote that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can’t be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM~hjMubh)}(hAlso note that since the kernel only supports flat-CCS on objects that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS.h](hKAlso note that since the kernel only supports flat-CCS on objects that can }(hj NhhhNhNubhemphasis)}(h*only*h]honly}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jNhj Nubh be placed in I915_MEMORY_CLASS_DEVICE, we therefore don’t support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS.}(hj NhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjMubh)}(hX5Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided.h]hX5Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided.}(hj0NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjMubh)}(hXOn older kernels which lack the relevant small-bar uAPI support (see also :c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed.h](hJOn older kernels which lack the relevant small-bar uAPI support (see also }(hj?NhhhNhNubh)}(h[:c:type:`drm_i915_memory_region_info.probed_cpu_visible_size `h]j)}(hjINh]h3drm_i915_memory_region_info.probed_cpu_visible_size}(hjKNhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjGNubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_memory_region_infouh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj?NubhXR), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed.}(hj?NhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjfNhMhjMubeh}(h]h ]h"]h$]h&]uh1j'hjMubeh}(h]h ]h"]h$]h&]uh1jhjMhMhjLubj)}(hXb``extensions`` The chain of extensions to apply to this object. This will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension. If we don't supply any extensions then we get the same old gem_create behaviour. For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions. For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content. For I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h](j)}(h``extensions``h]j)}(hjNh]h extensions}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj}Nubj()}(hhh](h)}(h0The chain of extensions to apply to this object.h]h0The chain of extensions to apply to this object.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(hThis will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension.h]hThis will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(hPIf we don't supply any extensions then we get the same old gem_create behaviour.h]hRIf we don’t supply any extensions then we get the same old gem_create behaviour.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(h_For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions.h]h_For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(heFor I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content.h]heFor I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjNubh)}(hQFor I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.h]hQFor I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhMhjNubeh}(h]h ]h"]h$]h&]uh1j'hj}Nubeh}(h]h ]h"]h$]h&]uh1jhjNhMhjLubeh}(h]h ]h"]h$]h&]uh1j hjOLubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hjOh]h Description}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXcNote that new buffer flags should be added here, at least for the stuff that is immutable. Previously we would have two ioctls, one to create the object with gem_create, and another to apply various parameters, however this creates some ambiguity for the params which are considered immutable. Also in general we're phasing out the various SET/GET ioctls.h]hXeNote that new buffer flags should be added here, at least for the stuff that is immutable. Previously we would have two ioctls, one to create the object with gem_create, and another to apply various parameters, however this creates some ambiguity for the params which are considered immutable. Also in general we’re phasing out the various SET/GET ioctls.}(hj&OhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMAhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j1drm_i915_gem_create_ext_memory_regions (C struct)(c.drm_i915_gem_create_ext_memory_regionshNtauh1jhhhhhNhNubj)}(hhh](j)}(h&drm_i915_gem_create_ext_memory_regionsh]j)}(h-struct drm_i915_gem_create_ext_memory_regionsh](j)}(hjh]hstruct}(hjNOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJOhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMJubj)}(h h]h }(hj\OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJOhhhj[OhMJubj)}(h&drm_i915_gem_create_ext_memory_regionsh]j)}(hjHOh]h&drm_i915_gem_create_ext_memory_regions}(hjnOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjOubah}(h]h ](j jeh"]h$]h&]jjuh1jhjJOhhhj[OhMJubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjFOhhhj[OhMJubah}(h]jAOah ](j j!eh"]h$]h&]j%j&)j'huh1jhj[OhMJhjCOhhubj))}(hhh]h)}(h1The I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.h]h1The I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOhhubah}(h]h ]h"]h$]h&]uh1j(hjCOhhhj[OhMJubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjOjLjOjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``pad`` MBZ ``num_regions`` Number of elements in the **regions** array. ``regions`` The regions/placements array. An array of struct drm_i915_gem_memory_class_instance.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubh:}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOubjt)}(hstruct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; };h]hstruct drm_i915_gem_create_ext_memory_regions { struct i915_user_extension base; __u32 pad; __u32 num_regions; __u64 regions; };}hjOsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOubh)}(h **Members**h]h)}(hjOh]hMembers}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOubj )}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]j)}(hjOh]hbase}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjOubj()}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjPubah}(h]h ]h"]h$]h&]uh1j'hjOubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjOubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj6Ph]hpad}(hj8PhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4Pubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj0Pubj()}(hhh]h)}(hMBZh]hMBZ}(hjOPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKPhMhjLPubah}(h]h ]h"]h$]h&]uh1j'hj0Pubeh}(h]h ]h"]h$]h&]uh1jhjKPhMhjOubj)}(h=``num_regions`` Number of elements in the **regions** array. h](j)}(h``num_regions``h]j)}(hjoPh]h num_regions}(hjqPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmPubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjiPubj()}(hhh]h)}(h,Number of elements in the **regions** array.h](hNumber of elements in the }(hjPhhhNhNubh)}(h **regions**h]hregions}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPubh array.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjPhMhjPubah}(h]h ]h"]h$]h&]uh1j'hjiPubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjOubj)}(ha``regions`` The regions/placements array. An array of struct drm_i915_gem_memory_class_instance.h](j)}(h ``regions``h]j)}(hjPh]hregions}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjPubj()}(hhh](h)}(hThe regions/placements array.h]hThe regions/placements array.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjPubh)}(h6An array of struct drm_i915_gem_memory_class_instance.h]h6An array of struct drm_i915_gem_memory_class_instance.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjPubeh}(h]h ]h"]h$]h&]uh1j'hjPubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjOubeh}(h]h ]h"]h$]h&]uh1j hjOubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj Qh]h Description}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj Qubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hSet the object with the desired set of placements/regions in priority order. Each entry must be unique and supported by the device.h]hSet the object with the desired set of placements/regions in priority order. Each entry must be unique and supported by the device.}(hj"QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXThis is provided as an array of struct drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance pair encodings. See struct drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to query the supported regions for a device.h]hXThis is provided as an array of struct drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance pair encodings. See struct drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to query the supported regions for a device.}(hj1QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(htAs an example, on discrete devices, if we wish to set the placement as device local-memory we can do something like:h]htAs an example, on discrete devices, if we wish to set the placement as device local-memory we can do something like:}(hj@QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubjt)}(hXstruct drm_i915_gem_memory_class_instance region_lmem = { .memory_class = I915_MEMORY_CLASS_DEVICE, .memory_instance = 0, }; struct drm_i915_gem_create_ext_memory_regions regions = { .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, .regions = (uintptr_t)®ion_lmem, .num_regions = 1, }; struct drm_i915_gem_create_ext create_ext = { .size = 16 * PAGE_SIZE, .extensions = (uintptr_t)®ions, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...h]hXstruct drm_i915_gem_memory_class_instance region_lmem = { .memory_class = I915_MEMORY_CLASS_DEVICE, .memory_instance = 0, }; struct drm_i915_gem_create_ext_memory_regions regions = { .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, .regions = (uintptr_t)®ion_lmem, .num_regions = 1, }; struct drm_i915_gem_create_ext create_ext = { .size = 16 * PAGE_SIZE, .extensions = (uintptr_t)®ions, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...}hjOQsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hX At which point we get the object handle in :c:type:`drm_i915_gem_create_ext.handle `, along with the final object size in :c:type:`drm_i915_gem_create_ext.size `, which should account for any rounding up, if required.h](h+At which point we get the object handle in }(hj_QhhhNhNubh)}(hB:c:type:`drm_i915_gem_create_ext.handle `h]j)}(hjiQh]hdrm_i915_gem_create_ext.handle}(hjkQhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjgQubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_gem_create_extuh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj_Qubh&, along with the final object size in }(hj_QhhhNhNubh)}(h@:c:type:`drm_i915_gem_create_ext.size `h]j)}(hjQh]hdrm_i915_gem_create_ext.size}(hjQhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_i915_gem_create_extuh1hhjQhMhj_Qubh8, which should account for any rounding up, if required.}(hj_QhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjQhMhhhhubh)}(hX4Note that userspace has no means of knowing the current backing region for objects where **num_regions** is larger than one. The kernel will only ensure that the priority order of the **regions** array is honoured, either when initially placing the object, or when moving memory around due to memory pressureh](hYNote that userspace has no means of knowing the current backing region for objects where }(hjQhhhNhNubh)}(h**num_regions**h]h num_regions}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQubhP is larger than one. The kernel will only ensure that the priority order of the }(hjQhhhNhNubh)}(h **regions**h]hregions}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQubhq array is honoured, either when initially placing the object, or when moving memory around due to memory pressure}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXOn Flat-CCS capable HW, compression is supported for the objects residing in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other memory class in **regions** and migrated (by i915, due to memory constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to decompress the content. But i915 doesn't have the required information to decompress the userspace compressed objects.h](hOn Flat-CCS capable HW, compression is supported for the objects residing in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other memory class in }(hjQhhhNhNubh)}(h **regions**h]hregions}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQubh and migrated (by i915, due to memory constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to decompress the content. But i915 doesn’t have the required information to decompress the userspace compressed objects.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hdSo i915 supports Flat-CCS, on the objects which can reside only on I915_MEMORY_CLASS_DEVICE regions.h]hdSo i915 supports Flat-CCS, on the objects which can reside only on I915_MEMORY_CLASS_DEVICE regions.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j4drm_i915_gem_create_ext_protected_content (C struct)+c.drm_i915_gem_create_ext_protected_contenthNtauh1jhhhhhNhNubj)}(hhh](j)}(h)drm_i915_gem_create_ext_protected_contenth]j)}(h0struct drm_i915_gem_create_ext_protected_contenth](j)}(hjh]hstruct}(hj0RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,RhhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hj>RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,Rhhhj=RhMubj)}(h)drm_i915_gem_create_ext_protected_contenth]j)}(hj*Rh]h)drm_i915_gem_create_ext_protected_content}(hjPRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLRubah}(h]h ](j jeh"]h$]h&]jjuh1jhj,Rhhhj=RhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj(Rhhhj=RhMubah}(h]j#Rah ](j j!eh"]h$]h&]j%j&)j'huh1jhj=RhMhj%Rhhubj))}(hhh]h)}(h2The I915_OBJECT_PARAM_PROTECTED_CONTENT extension.h]h2The I915_OBJECT_PARAM_PROTECTED_CONTENT extension.}(hjrRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjoRhhubah}(h]h ]h"]h$]h&]uh1j(hj%Rhhhj=RhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjRjLjRjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_create_ext_protected_content { struct i915_user_extension base; __u32 flags; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``flags`` reserved for future usage, currently MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRubh:}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjRubjt)}(hkstruct drm_i915_gem_create_ext_protected_content { struct i915_user_extension base; __u32 flags; };h]hkstruct drm_i915_gem_create_ext_protected_content { struct i915_user_extension base; __u32 flags; };}hjRsbah}(h]h ]h"]h$]h&]jjuh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjRubh)}(h **Members**h]h)}(hjRh]hMembers}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjRubj )}(hhh](j)}(h9``base`` Extension link. See struct i915_user_extension. h](j)}(h``base``h]j)}(hjRh]hbase}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjRubj()}(hhh]h)}(h/Extension link. See struct i915_user_extension.h]h/Extension link. See struct i915_user_extension.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhMhjRubah}(h]h ]h"]h$]h&]uh1j'hjRubeh}(h]h ]h"]h$]h&]uh1jhjRhMhjRubj)}(h2``flags`` reserved for future usage, currently MBZh](j)}(h ``flags``h]j)}(hjSh]hflags}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhjSubj()}(hhh]h)}(h(reserved for future usage, currently MBZh]h(reserved for future usage, currently MBZ}(hj1ShhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhj.Subah}(h]h ]h"]h$]h&]uh1j'hjSubeh}(h]h ]h"]h$]h&]uh1jhj-ShMhjRubeh}(h]h ]h"]h$]h&]uh1j hjRubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhhhhhNhNubh)}(h**Description**h]h)}(hj[Sh]h Description}(hj]ShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYSubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubh)}(hXIf this extension is provided, buffer contents are expected to be protected by PXP encryption and require decryption for scan out and processing. This is only possible on platforms that have PXP enabled, on all other scenarios using this extension will cause the ioctl to fail and return -ENODEV. The flags parameter is reserved for future expansion and must currently be set to zero.h]hXIf this extension is provided, buffer contents are expected to be protected by PXP encryption and require decryption for scan out and processing. This is only possible on platforms that have PXP enabled, on all other scenarios using this extension will cause the ioctl to fail and return -ENODEV. The flags parameter is reserved for future expansion and must currently be set to zero.}(hjqShhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hHThe buffer contents are considered invalid after a PXP session teardown.h]hHThe buffer contents are considered invalid after a PXP session teardown.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(hXThe encryption is guaranteed to be processed correctly only if the object is submitted with a context created using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks at submission time on the validity of the objects involved.h]hXThe encryption is guaranteed to be processed correctly only if the object is submitted with a context created using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks at submission time on the validity of the objects involved.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubh)}(h8Below is an example on how to create a protected object:h]h8Below is an example on how to create a protected object:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMhhhhubjt)}(hXhstruct drm_i915_gem_create_ext_protected_content protected_ext = { .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT }, .flags = 0, }; struct drm_i915_gem_create_ext create_ext = { .size = PAGE_SIZE, .extensions = (uintptr_t)&protected_ext, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...h]hXhstruct drm_i915_gem_create_ext_protected_content protected_ext = { .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT }, .flags = 0, }; struct drm_i915_gem_create_ext create_ext = { .size = PAGE_SIZE, .extensions = (uintptr_t)&protected_ext, }; int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); if (err) ...}hjSsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM hhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*drm_i915_gem_create_ext_set_pat (C struct)!c.drm_i915_gem_create_ext_set_pathNtauh1jhhhhhNhNubj)}(hhh](j)}(hdrm_i915_gem_create_ext_set_path]j)}(h&struct drm_i915_gem_create_ext_set_path](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjShhhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhMubj)}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjShhhjShMubj)}(hdrm_i915_gem_create_ext_set_path]j)}(hjSh]hdrm_i915_gem_create_ext_set_pat}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ](j jeh"]h$]h&]jjuh1jhjShhhjShMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjShhhjShMubah}(h]jSah ](j j!eh"]h$]h&]j%j&)j'huh1jhjShMhjShhubj))}(hhh]h)}(h*The I915_GEM_CREATE_EXT_SET_PAT extension.h]h*The I915_GEM_CREATE_EXT_SET_PAT extension.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:8: ./include/uapi/drm/i915_drm.hhM!hjThhubah}(h]h ]h"]h$]h&]uh1j(hjShhhjShMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj0TjLj0TjMjNjOuh1jhhhhhNhNubjQ)}(hX**Definition**:: struct drm_i915_gem_create_ext_set_pat { struct i915_user_extension base; __u32 pat_index; __u32 rsvd; }; **Members** ``base`` Extension link. See struct i915_user_extension. ``pat_index`` PAT index to be set PAT index is a bit field in Page Table Entry to control caching behaviors for GPU accesses. The definition of PAT index is platform dependent and can be found in hardware specifications, ``rsvd`` reserved for future useh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj\ubj()}(hhh]h)}(h32 bit padding, should be 0h]h32 bit padding, should be 0}(hj]\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjY\hM=hjZ\ubah}(h]h ]h"]h$]h&]uh1j'hj>\ubeh}(h]h ]h"]h$]h&]uh1jhjY\hM=hjZubj)}(hX``addr`` the address the VA space region or (memory backed) mapping should be mapped to h](j)}(h``addr``h]j)}(hj}\h]haddr}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{\ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMAhjw\ubj()}(hhh]h)}(hNthe address the VA space region or (memory backed) mapping should be mapped toh]hNthe address the VA space region or (memory backed) mapping should be mapped to}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMAhj\ubah}(h]h ]h"]h$]h&]uh1j'hjw\ubeh}(h]h ]h"]h$]h&]uh1jhj\hMAhjZubj)}(h;``bo_offset`` the offset within the BO backing the mapping h](j)}(h ``bo_offset``h]j)}(hj\h]h bo_offset}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMGhj\ubj()}(hhh]h)}(h,the offset within the BO backing the mappingh]h,the offset within the BO backing the mapping}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMGhj\ubah}(h]h ]h"]h$]h&]uh1j'hj\ubeh}(h]h ]h"]h$]h&]uh1jhj\hMGhjZubj)}(h4``range`` the size of the requested mapping in bytesh](j)}(h ``range``h]j)}(hj\h]hrange}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMJhj\ubj()}(hhh]h)}(h*the size of the requested mapping in bytesh]h*the size of the requested mapping in bytes}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMKhj]ubah}(h]h ]h"]h$]h&]uh1j'hj\ubeh}(h]h ]h"]h$]h&]uh1jhj]hMJhjZubeh}(h]h ]h"]h$]h&]uh1j hjlZubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhjUhhhNhNubh)}(h**Description**h]h)}(hj2]h]h Description}(hj4]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0]ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMNhjUhhubh)}(hThis structure represents a single VM_BIND operation. UMDs should pass an array of this structure via struct drm_nouveau_vm_bind's :c:type:`op_ptr` field.h](hThis structure represents a single VM_BIND operation. UMDs should pass an array of this structure via struct drm_nouveau_vm_bind’s }(hjH]hhhNhNubh)}(h:c:type:`op_ptr`h]j)}(hjR]h]hop_ptr}(hjT]hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjP]ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) op_ptruh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjH]ubh field.}(hjH]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjo]hMhjUhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_nouveau_vm_bind (C struct)c.drm_nouveau_vm_bindhNtauh1jhjUhhhNhNubj)}(hhh](j)}(hdrm_nouveau_vm_bindh]j)}(hstruct drm_nouveau_vm_bindh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhj]hMubj)}(hdrm_nouveau_vm_bindh]j)}(hj]h]hdrm_nouveau_vm_bind}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj]hhhj]hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj]hhhj]hMubah}(h]j]ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj]hMhj]hhubj))}(hhh]h)}(h'structure for DRM_IOCTL_NOUVEAU_VM_BINDh]h'structure for DRM_IOCTL_NOUVEAU_VM_BIND}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMPhj]hhubah}(h]h ]h"]h$]h&]uh1j(hj]hhhj]hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj]jLj]jMjNjOuh1jhhhjUhNhNubjQ)}(hX***Definition**:: struct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; }; **Members** ``op_count`` the number of :c:type:`drm_nouveau_vm_bind_op` ``flags`` the flags for a :c:type:`drm_nouveau_vm_bind` ioctl Supported values: ``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel. If this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects. ``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` ``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished ``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for ``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished ``op_ptr`` pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]ubh:}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMThj]ubjt)}(hstruct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; };h]hstruct drm_nouveau_vm_bind { __u32 op_count; __u32 flags; #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1; __u32 wait_count; __u32 sig_count; __u64 wait_ptr; __u64 sig_ptr; __u64 op_ptr; };}hj^sbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMVhj]ubh)}(h **Members**h]h)}(hj#^h]hMembers}(hj%^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!^ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMahj]ubj )}(hhh](j)}(h<``op_count`` the number of :c:type:`drm_nouveau_vm_bind_op` h](j)}(h ``op_count``h]j)}(hjB^h]hop_count}(hjD^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMUhj<^ubj()}(hhh]h)}(h.the number of :c:type:`drm_nouveau_vm_bind_op`h](hthe number of }(hj[^hhhNhNubh)}(h :c:type:`drm_nouveau_vm_bind_op`h]j)}(hje^h]hdrm_nouveau_vm_bind_op}(hjg^hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjc^ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_vm_bind_opuh1hhjW^hMUhj[^ubeh}(h]h ]h"]h$]h&]uh1hhjW^hMUhjX^ubah}(h]h ]h"]h$]h&]uh1j'hj<^ubeh}(h]h ]h"]h$]h&]uh1jhjW^hMUhj9^ubj)}(hXg``flags`` the flags for a :c:type:`drm_nouveau_vm_bind` ioctl Supported values: ``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel. If this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects. h](j)}(h ``flags``h]j)}(hj^h]hflags}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMbhj^ubj()}(hhh](h)}(h3the flags for a :c:type:`drm_nouveau_vm_bind` ioctlh](hthe flags for a }(hj^hhhNhNubh)}(h:c:type:`drm_nouveau_vm_bind`h]j)}(hj^h]hdrm_nouveau_vm_bind}(hj^hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_vm_binduh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMYhj^ubh ioctl}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj^hMYhj^ubh)}(hSupported values:h]hSupported values:}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM[hj^ubh)}(h``DRM_NOUVEAU_VM_BIND_RUN_ASYNC`` - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel.h](j)}(h!``DRM_NOUVEAU_VM_BIND_RUN_ASYNC``h]hDRM_NOUVEAU_VM_BIND_RUN_ASYNC}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubh^ - Indicates that the given VM_BIND operation should be executed asynchronously by the kernel.}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM]hj^ubh)}(hIf this flag is not supplied the kernel executes the associated operations synchronously and doesn't accept any :c:type:`drm_nouveau_sync` objects.h](hrIf this flag is not supplied the kernel executes the associated operations synchronously and doesn’t accept any }(hj_hhhNhNubh)}(h:c:type:`drm_nouveau_sync`h]j)}(hj_h]hdrm_nouveau_sync}(hj_hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM`hj_ubh objects.}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj8_hM`hj^ubeh}(h]h ]h"]h$]h&]uh1j'hj^ubeh}(h]h ]h"]h$]h&]uh1jhj^hMbhj9^ubj)}(h>``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` h](j)}(h``wait_count``h]j)}(hjU_h]h wait_count}(hjW_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjS_ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMghjO_ubj()}(hhh]h)}(h.the number of wait :c:type:`drm_nouveau_syncs`h](hthe number of wait }(hjn_hhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjx_h]hdrm_nouveau_syncs}(hjz_hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjv_ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncsuh1hhjj_hMghjn_ubeh}(h]h ]h"]h$]h&]uh1hhjj_hMghjk_ubah}(h]h ]h"]h$]h&]uh1j'hjO_ubeh}(h]h ]h"]h$]h&]uh1jhjj_hMghj9^ubj)}(hP``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_count``h]j)}(hj_h]h sig_count}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMkhj_ubj()}(hhh]h)}(hAthe number of :c:type:`drm_nouveau_syncs` to signal when finishedh](hthe number of }(hj_hhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hj_h]hdrm_nouveau_syncs}(hj_hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncsuh1hhj_hMkhj_ubh to signal when finished}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj_hMkhj_ubah}(h]h ]h"]h$]h&]uh1j'hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hMkhj9^ubj)}(h@``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for h](j)}(h ``wait_ptr``h]j)}(hj `h]hwait_ptr}(hj `hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMohj`ubj()}(hhh]h)}(h2pointer to :c:type:`drm_nouveau_syncs` to wait forh](h pointer to }(hj"`hhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hj,`h]hdrm_nouveau_syncs}(hj.`hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj*`ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncsuh1hhj`hMohj"`ubh to wait for}(hj"`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj`hMohj`ubah}(h]h ]h"]h$]h&]uh1j'hj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hMohj9^ubj)}(hK``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_ptr``h]j)}(hje`h]hsig_ptr}(hjg`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMshj_`ubj()}(hhh]h)}(h>pointer to :c:type:`drm_nouveau_syncs` to signal when finishedh](h pointer to }(hj~`hhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hj`h]hdrm_nouveau_syncs}(hj`hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncsuh1hhjz`hMshj~`ubh to signal when finished}(hj~`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjz`hMshj{`ubah}(h]h ]h"]h$]h&]uh1j'hj_`ubeh}(h]h ]h"]h$]h&]uh1jhjz`hMshj9^ubj)}(hF``op_ptr`` pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](j)}(h ``op_ptr``h]j)}(hj`h]hop_ptr}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMvhj`ubj()}(hhh]h)}(h;pointer to the :c:type:`drm_nouveau_vm_bind_ops` to executeh](hpointer to the }(hj`hhhNhNubh)}(h!:c:type:`drm_nouveau_vm_bind_ops`h]j)}(hj`h]hdrm_nouveau_vm_bind_ops}(hj`hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_vm_bind_opsuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMwhj`ubh to execute}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjahMwhj`ubah}(h]h ]h"]h$]h&]uh1j'hj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hMvhj9^ubeh}(h]h ]h"]h$]h&]uh1j hj]ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhjUhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_nouveau_exec_push (C struct)c.drm_nouveau_exec_pushhNtauh1jhjUhhhNhNubj)}(hhh](j)}(hdrm_nouveau_exec_pushh]j)}(hstruct drm_nouveau_exec_pushh](j)}(hjh]hstruct}(hj>ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ahhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM}ubj)}(h h]h }(hjLahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ahhhjKahM}ubj)}(hdrm_nouveau_exec_pushh]j)}(hj8ah]hdrm_nouveau_exec_push}(hj^ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZaubah}(h]h ](j jeh"]h$]h&]jjuh1jhj:ahhhjKahM}ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj6ahhhjKahM}ubah}(h]j1aah ](j j!eh"]h$]h&]j%j&)j'huh1jhjKahM}hj3ahhubj))}(hhh]h)}(hEXEC push operationh]hEXEC push operation}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhM|hj}ahhubah}(h]h ]h"]h$]h&]uh1j(hj3ahhhjKahM}ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjajLjajMjNjOuh1jhhhjUhNhNubjQ)}(hXM**Definition**:: struct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; }; **Members** ``va`` the virtual address of the push buffer mapping ``va_len`` the length of the push buffer mapping ``flags`` the flags for this push buffer mappingh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaubh:}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjaubjt)}(hstruct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; };h]hstruct drm_nouveau_exec_push { __u64 va; __u32 va_len; __u32 flags; #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1; };}hjasbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjaubh)}(h **Members**h]h)}(hjah]hMembers}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjaubj )}(hhh](j)}(h6``va`` the virtual address of the push buffer mapping h](j)}(h``va``h]j)}(hjah]hva}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjaubj()}(hhh]h)}(h.the virtual address of the push buffer mappingh]h.the virtual address of the push buffer mapping}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMhjbubah}(h]h ]h"]h$]h&]uh1j'hjaubeh}(h]h ]h"]h$]h&]uh1jhjbhMhjaubj)}(h1``va_len`` the length of the push buffer mapping h](j)}(h ``va_len``h]j)}(hj&bh]hva_len}(hj(bhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$bubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhj bubj()}(hhh]h)}(h%the length of the push buffer mappingh]h%the length of the push buffer mapping}(hj?bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;bhMhj``wait_count`` the number of wait :c:type:`drm_nouveau_syncs` h](j)}(h``wait_count``h]j)}(hjGdh]h wait_count}(hjIdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEdubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjAdubj()}(hhh]h)}(h.the number of wait :c:type:`drm_nouveau_syncs`h](hthe number of wait }(hj`dhhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjjdh]hdrm_nouveau_syncs}(hjldhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjhdubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncsuh1hhj\dhMhj`dubeh}(h]h ]h"]h$]h&]uh1hhj\dhMhj]dubah}(h]h ]h"]h$]h&]uh1j'hjAdubeh}(h]h ]h"]h$]h&]uh1jhj\dhMhjcubj)}(hP``sig_count`` the number of :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_count``h]j)}(hjdh]h sig_count}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjdubj()}(hhh]h)}(hAthe number of :c:type:`drm_nouveau_syncs` to signal when finishedh](hthe number of }(hjdhhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjdh]hdrm_nouveau_syncs}(hjdhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncsuh1hhjdhMhjdubh to signal when finished}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjdhMhjdubah}(h]h ]h"]h$]h&]uh1j'hjdubeh}(h]h ]h"]h$]h&]uh1jhjdhMhjcubj)}(h@``wait_ptr`` pointer to :c:type:`drm_nouveau_syncs` to wait for h](j)}(h ``wait_ptr``h]j)}(hjdh]hwait_ptr}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjdubj()}(hhh]h)}(h2pointer to :c:type:`drm_nouveau_syncs` to wait forh](h pointer to }(hjehhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjeh]hdrm_nouveau_syncs}(hj ehhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncsuh1hhjehMhjeubh to wait for}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjehMhjeubah}(h]h ]h"]h$]h&]uh1j'hjdubeh}(h]h ]h"]h$]h&]uh1jhjehMhjcubj)}(hK``sig_ptr`` pointer to :c:type:`drm_nouveau_syncs` to signal when finished h](j)}(h ``sig_ptr``h]j)}(hjWeh]hsig_ptr}(hjYehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUeubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjQeubj()}(hhh]h)}(h>pointer to :c:type:`drm_nouveau_syncs` to signal when finishedh](h pointer to }(hjpehhhNhNubh)}(h:c:type:`drm_nouveau_syncs`h]j)}(hjzeh]hdrm_nouveau_syncs}(hj|ehhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjxeubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_syncsuh1hhjlehMhjpeubh to signal when finished}(hjpehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjlehMhjmeubah}(h]h ]h"]h$]h&]uh1j'hjQeubeh}(h]h ]h"]h$]h&]uh1jhjlehMhjcubj)}(h;``push_ptr`` pointer to :c:type:`drm_nouveau_exec_push` opsh](j)}(h ``push_ptr``h]j)}(hjeh]hpush_ptr}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjeubj()}(hhh]h)}(h.pointer to :c:type:`drm_nouveau_exec_push` opsh](h pointer to }(hjehhhNhNubh)}(h:c:type:`drm_nouveau_exec_push`h]j)}(hjeh]hdrm_nouveau_exec_push}(hjehhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) drm_nouveau_exec_pushuh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:19: ./include/uapi/drm/nouveau_drm.hhMhjeubh ops}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjehMhjeubah}(h]h ]h"]h$]h&]uh1j'hjeubeh}(h]h ]h"]h$]h&]uh1jhjehMhjcubeh}(h]h ]h"]h$]h&]uh1j hjacubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhjUhhhNhNubeh}(h]vm-bind-exec-uapiah ]h"]vm_bind / exec uapiah$]h&]uh1hhjUhhhhhKubeh}(h]drm-nouveau-uapiah ]h"]drm/nouveau uapiah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hdrm/panthor uAPIh]hdrm/panthor uAPI}(hj*fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'fhhhhhKubh)}(h.. _Introduction:h]h}(h]h ]h"]h$]h&]h introductionuh1hhKhj'fhhhNubh)}(h**Introduction**h]h)}(hjEfh]h Introduction}(hjGfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCfubah}(h]jBfah ]h"] introductionah$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj'fhhj}jXfj8fsj }jBfj8fsubh)}(h0This documentation describes the Panthor IOCTLs.h]h0This documentation describes the Panthor IOCTLs.}(hj^fhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK hj'fhhubh)}(hEJust a few generic rules about the data passed to the Panthor IOCTLs:h]hEJust a few generic rules about the data passed to the Panthor IOCTLs:}(hjmfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj'fhhubj )}(hhh](j )}(hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.h]h)}(hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.h]hsStructures must be aligned on 64-bit/8-byte. If the object is not naturally aligned, a padding field must be added.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]h)}(hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.h]hXFields must be explicitly aligned to their natural type alignment with pad[0..N] fields.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]h)}(hNAll padding fields will be checked by the driver to make sure they are zeroed.h]hNAll padding fields will be checked by the driver to make sure they are zeroed.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(h-Flags can be added, but not removed/replaced.h]h)}(hjfh]h-Flags can be added, but not removed/replaced.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]h)}(hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.h]hX9New fields can be added to the main structures (the structures directly passed to the ioctl). Those fields can be added at the end of the structure, or replace existing padding fields. Any new field being added must preserve the behavior that existed before those fields were added when a value of zero is passed.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).h]h)}(hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).h]hNew fields can be added to indirect objects (objects pointed by the main structure), iff those objects are passed a size to reflect the size known by the userspace driver (see drm_panthor_obj_array::stride or drm_panthor_dev_query::size).}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjfubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]h)}(hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).h]hIf the kernel driver is too old to know some fields, those will be ignored if zero, and otherwise rejected (and so will be zero on output).}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK!hjgubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h)}(h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.h]h~If userspace is too old to know some fields, those will be zeroed (input) before the structure is parsed by the kernel driver.}(hj1ghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK#hj-gubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to trial and error to know which flags are supported.h]h)}(hEach new flag/field addition must come with a driver version update so the userspace driver doesn't have to trial and error to know which flags are supported.h]hEach new flag/field addition must come with a driver version update so the userspace driver doesn’t have to trial and error to know which flags are supported.}(hjJghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK%hjFgubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h)}(h`Structures should not contain unions, as this would defeat the extensibility of such structures.h]h`Structures should not contain unions, as this would defeat the extensibility of such structures.}(hjcghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK(hj_gubah}(h]h ]h"]h$]h&]uh1j hj|fubj )}(hrIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum. h]h)}(hpIOCTLs can't be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum.h]hrIOCTLs can’t be removed or replaced. New IOCTL IDs should be placed at the end of the drm_panthor_ioctl_id enum.}(hj|ghhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK*hjxgubah}(h]h ]h"]h$]h&]uh1j hj|fubeh}(h]h ]h"]h$]h&]j) j* uh1j hjfhKhj'fhhubh)}(h'.. _MMIO regions exposed to userspace.:h]h}(h]h ]h"]h$]h&]h!mmio-regions-exposed-to-userspaceuh1hhK&hj'fhhhNubh)}(h&**MMIO regions exposed to userspace.**h]h)}(hjgh]h"MMIO regions exposed to userspace.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgubah}(h]jgah ]h"]"mmio regions exposed to userspace.ah$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK0hj'fhhj}jgjgsj }jgjgsubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&DRM_PANTHOR_USER_MMIO_OFFSET (C macro)c.DRM_PANTHOR_USER_MMIO_OFFSEThNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]j)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]j)}(hDRM_PANTHOR_USER_MMIO_OFFSETh]j)}(hjgh]hDRM_PANTHOR_USER_MMIO_OFFSET}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubah}(h]h ](j jeh"]h$]h&]jjuh1jhjghhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK1ubah}(h]h ]h"]h$]h&]jjjuh1jjjhjghhhjghK1ubah}(h]jgah ](j j!eh"]h$]h&]j%j&)j'huh1jhjghK1hjghhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hjghhhjghK1ubeh}(h]h ](jEmacroeh"]h$]h&]jJjEjKjhjLjhjMjNjOuh1jhhhj'fhNhNubh)}(hXFile offset for all MMIO regions being exposed to userspace. Don't use this value directly, use DRM_PANTHOR_USER__OFFSET values instead. pgoffset passed to mmap2() is an unsigned long, which forces us to use a different offset on 32-bit and 64-bit systems.h]hXFile offset for all MMIO regions being exposed to userspace. Don’t use this value directly, use DRM_PANTHOR_USER__OFFSET values instead. pgoffset passed to mmap2() is an unsigned long, which forces us to use a different offset on 32-bit and 64-bit systems.}(hj hhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK3hj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET (C macro)'c.DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSEThNtauh1jhj'fhhhNhNubj)}(hhh](j)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]j)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]j)}(h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSETh]j)}(hj,hh]h%DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET}(hj6hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hubah}(h]h ](j jeh"]h$]h&]jjuh1jhj.hhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK8ubah}(h]h ]h"]h$]h&]jjjuh1jjjhj*hhhhjIhhK8ubah}(h]j%hah ](j j!eh"]h$]h&]j%j&)j'huh1jhjIhhK8hj'hhhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hj'hhhhjIhhK8ubeh}(h]h ](jEmacroeh"]h$]h&]jJjEjKjbhjLjbhjMjNjOuh1jhhhj'fhNhNubh)}(hXFile offset for the LATEST_FLUSH_ID register. The Userspace driver controls GPU cache flushing through CS instructions, but the flush reduction mechanism requires a flush_id. This flush_id could be queried with an ioctl, but Arm provides a well-isolated register page containing only this read-only register, so let's expose this page through a static mmap offset and allow direct mapping of this MMIO region so we can avoid the user <-> kernel round-trip.h]hXFile offset for the LATEST_FLUSH_ID register. The Userspace driver controls GPU cache flushing through CS instructions, but the flush reduction mechanism requires a flush_id. This flush_id could be queried with an ioctl, but Arm provides a well-isolated register page containing only this read-only register, so let’s expose this page through a static mmap offset and allow direct mapping of this MMIO region so we can avoid the user <-> kernel round-trip.}(hjfhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhK:hj'fhhubh)}(h.. _IOCTL IDs:h]h}(h]h ]h"]h$]h&]h ioctl-idsuh1hhKjubah}(h]h ]h"]h$]h&]uh1j'hj"jubeh}(h]h ]h"]h$]h&]uh1jhj=jhKhjiubeh}(h]h ]h"]h$]h&]uh1j hjeiubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubh)}(h**Description**h]h)}(hjkjh]h Description}(hjmjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjijubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj'fhhubh)}(hThis object is used to pass an array of objects whose size is subject to changes in future versions of the driver. In order to support this mutability, we pass a stride describing the size of the object as known by userspace.h]hThis object is used to pass an array of objects whose size is subject to changes in future versions of the driver. In order to support this mutability, we pass a stride describing the size of the object as known by userspace.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj'fhhubh)}(hYou shouldn't fill drm_panthor_obj_array fields directly. You should instead use the DRM_PANTHOR_OBJ_ARRAY() macro that takes care of initializing the stride to the object size.h]hYou shouldn’t fill drm_panthor_obj_array fields directly. You should instead use the DRM_PANTHOR_OBJ_ARRAY() macro that takes care of initializing the stride to the object size.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jDRM_PANTHOR_OBJ_ARRAY (C macro)c.DRM_PANTHOR_OBJ_ARRAYhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hDRM_PANTHOR_OBJ_ARRAYh]j)}(hDRM_PANTHOR_OBJ_ARRAYh]j)}(hDRM_PANTHOR_OBJ_ARRAYh]j)}(hjjh]hDRM_PANTHOR_OBJ_ARRAY}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKubah}(h]h ]h"]h$]h&]jjjuh1jjjhjjhhhjjhKubah}(h]jjah ](j j!eh"]h$]h&]j%j&)j'huh1jhjjhKhjjhhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hjjhhhjjhKubeh}(h]h ](jEmacroeh"]h$]h&]jJjEjKjjjLjjjMjNjOuh1jhhhj'fhNhNubh)}(h$``DRM_PANTHOR_OBJ_ARRAY (cnt, ptr)``h]j)}(hjjh]h DRM_PANTHOR_OBJ_ARRAY (cnt, ptr)}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj'fhhubj)}(h*Initialize a drm_panthor_obj_array field. h]h)}(h)Initialize a drm_panthor_obj_array field.h]h)Initialize a drm_panthor_obj_array field.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjkubah}(h]h ]h"]h$]h&]uh1jhjkhKhj'fhhubjQ)}(h**Parameters** ``cnt`` Number of elements in the array. ``ptr`` Pointer to the array to pass to the kernel. **Description** Macro initializing a drm_panthor_obj_array based on the object size as known by userspace.h](h)}(h**Parameters**h]h)}(hj#kh]h Parameters}(hj%khhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!kubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhjkubj )}(hhh](j)}(h)``cnt`` Number of elements in the array. h](j)}(h``cnt``h]j)}(hjBkh]hcnt}(hjDkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@kubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhKhj> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u32 selected_coherency; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; __u64 gpu_features; }; **Members** ``gpu_id`` GPU ID. ``gpu_rev`` GPU revision. ``csf_id`` Command stream frontend ID. ``l2_features`` L2-cache features. ``tiler_features`` Tiler features. ``mem_features`` Memory features. ``mmu_features`` MMU features. ``thread_features`` Thread features. ``max_threads`` Maximum number of threads. ``thread_max_workgroup_size`` Maximum workgroup size. ``thread_max_barrier_size`` Maximum number of threads that can wait simultaneously on a barrier. ``coherency_features`` Coherency features. Combination of drm_panthor_gpu_coherency flags. Note that this is just what the coherency protocols supported by the GPU, but the actual coherency in place depends on the SoC integration and is reflected by drm_panthor_gpu_info::selected_coherency. ``texture_features`` Texture features. ``as_present`` Bitmask encoding the number of address-space exposed by the MMU. ``selected_coherency`` Coherency selected for this device. One of drm_panthor_gpu_coherency. ``shader_present`` Bitmask encoding the shader cores exposed by the GPU. ``l2_present`` Bitmask encoding the L2 caches exposed by the GPU. ``tiler_present`` Bitmask encoding the tiler units exposed by the GPU. ``core_features`` Used to discriminate core variants when they exist. ``pad`` MBZ. ``gpu_features`` Bitmask describing supported GPU-wide featuresh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrubh:}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjrubjt)}(hXstruct drm_panthor_gpu_info { __u32 gpu_id; #define DRM_PANTHOR_ARCH_MAJOR(x) ((x) >> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u32 selected_coherency; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; __u64 gpu_features; };h]hXstruct drm_panthor_gpu_info { __u32 gpu_id; #define DRM_PANTHOR_ARCH_MAJOR(x) ((x) >> 28); #define DRM_PANTHOR_ARCH_MINOR(x) (((x) >> 24) & 0xf); #define DRM_PANTHOR_ARCH_REV(x) (((x) >> 20) & 0xf); #define DRM_PANTHOR_PRODUCT_MAJOR(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_VERSION_MAJOR(x) (((x) >> 12) & 0xf); #define DRM_PANTHOR_VERSION_MINOR(x) (((x) >> 4) & 0xff); #define DRM_PANTHOR_VERSION_STATUS(x) ((x) & 0xf); __u32 gpu_rev; __u32 csf_id; #define DRM_PANTHOR_CSHW_MAJOR(x) (((x) >> 26) & 0x3f); #define DRM_PANTHOR_CSHW_MINOR(x) (((x) >> 20) & 0x3f); #define DRM_PANTHOR_CSHW_REV(x) (((x) >> 16) & 0xf); #define DRM_PANTHOR_MCU_MAJOR(x) (((x) >> 10) & 0x3f); #define DRM_PANTHOR_MCU_MINOR(x) (((x) >> 4) & 0x3f); #define DRM_PANTHOR_MCU_REV(x) ((x) & 0xf); __u32 l2_features; __u32 tiler_features; __u32 mem_features; __u32 mmu_features; #define DRM_PANTHOR_MMU_VA_BITS(x) ((x) & 0xff); __u32 thread_features; __u32 max_threads; __u32 thread_max_workgroup_size; __u32 thread_max_barrier_size; __u32 coherency_features; __u32 texture_features[4]; __u32 as_present; __u32 selected_coherency; __u64 shader_present; __u64 l2_present; __u64 tiler_present; __u32 core_features; __u32 pad; __u64 gpu_features; };}hjrsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjrubh)}(h **Members**h]h)}(hjrh]hMembers}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMChjrubj )}(hhh](j)}(h``gpu_id`` GPU ID. h](j)}(h ``gpu_id``h]j)}(hjrh]hgpu_id}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjrubj()}(hhh]h)}(hGPU ID.h]hGPU ID.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1j'hjrubeh}(h]h ]h"]h$]h&]uh1jhjrhMhjrubj)}(h``gpu_rev`` GPU revision. h](j)}(h ``gpu_rev``h]j)}(hjsh]hgpu_rev}(hj shhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM'hjsubj()}(hhh]h)}(h GPU revision.h]h GPU revision.}(hj7shhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3shM'hj4subah}(h]h ]h"]h$]h&]uh1j'hjsubeh}(h]h ]h"]h$]h&]uh1jhj3shM'hjrubj)}(h'``csf_id`` Command stream frontend ID. h](j)}(h ``csf_id``h]j)}(hjWsh]hcsf_id}(hjYshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM*hjQsubj()}(hhh]h)}(hCommand stream frontend ID.h]hCommand stream frontend ID.}(hjpshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlshM*hjmsubah}(h]h ]h"]h$]h&]uh1j'hjQsubeh}(h]h ]h"]h$]h&]uh1jhjlshM*hjrubj)}(h#``l2_features`` L2-cache features. h](j)}(h``l2_features``h]j)}(hjsh]h l2_features}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM3hjsubj()}(hhh]h)}(hL2-cache features.h]hL2-cache features.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshM3hjsubah}(h]h ]h"]h$]h&]uh1j'hjsubeh}(h]h ]h"]h$]h&]uh1jhjshM3hjrubj)}(h#``tiler_features`` Tiler features. h](j)}(h``tiler_features``h]j)}(hjsh]htiler_features}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM6hjsubj()}(hhh]h)}(hTiler features.h]hTiler features.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshM6hjsubah}(h]h ]h"]h$]h&]uh1j'hjsubeh}(h]h ]h"]h$]h&]uh1jhjshM6hjrubj)}(h"``mem_features`` Memory features. h](j)}(h``mem_features``h]j)}(hjth]h mem_features}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM9hjsubj()}(hhh]h)}(hMemory features.h]hMemory features.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthM9hjtubah}(h]h ]h"]h$]h&]uh1j'hjsubeh}(h]h ]h"]h$]h&]uh1jhjthM9hjrubj)}(h``mmu_features`` MMU features. h](j)}(h``mmu_features``h]j)}(hj;th]h mmu_features}(hj=thhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9tubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM<hj5tubj()}(hhh]h)}(h MMU features.h]h MMU features.}(hjTthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPthM<hjQtubah}(h]h ]h"]h$]h&]uh1j'hj5tubeh}(h]h ]h"]h$]h&]uh1jhjPthM<hjrubj)}(h%``thread_features`` Thread features. h](j)}(h``thread_features``h]j)}(hjtth]hthread_features}(hjvthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM@hjntubj()}(hhh]h)}(hThread features.h]hThread features.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthM@hjtubah}(h]h ]h"]h$]h&]uh1j'hjntubeh}(h]h ]h"]h$]h&]uh1jhjthM@hjrubj)}(h+``max_threads`` Maximum number of threads. h](j)}(h``max_threads``h]j)}(hjth]h max_threads}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMChjtubj()}(hhh]h)}(hMaximum number of threads.h]hMaximum number of threads.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMChjtubah}(h]h ]h"]h$]h&]uh1j'hjtubeh}(h]h ]h"]h$]h&]uh1jhjthMChjrubj)}(h6``thread_max_workgroup_size`` Maximum workgroup size. h](j)}(h``thread_max_workgroup_size``h]j)}(hjth]hthread_max_workgroup_size}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMFhjtubj()}(hhh]h)}(hMaximum workgroup size.h]hMaximum workgroup size.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMFhjtubah}(h]h ]h"]h$]h&]uh1j'hjtubeh}(h]h ]h"]h$]h&]uh1jhjthMFhjrubj)}(ha``thread_max_barrier_size`` Maximum number of threads that can wait simultaneously on a barrier. h](j)}(h``thread_max_barrier_size``h]j)}(hjuh]hthread_max_barrier_size}(hj!uhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMKhjuubj()}(hhh]h)}(hDMaximum number of threads that can wait simultaneously on a barrier.h]hDMaximum number of threads that can wait simultaneously on a barrier.}(hj8uhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMJhj5uubah}(h]h ]h"]h$]h&]uh1j'hjuubeh}(h]h ]h"]h$]h&]uh1jhj4uhMKhjrubj)}(hX&``coherency_features`` Coherency features. Combination of drm_panthor_gpu_coherency flags. Note that this is just what the coherency protocols supported by the GPU, but the actual coherency in place depends on the SoC integration and is reflected by drm_panthor_gpu_info::selected_coherency. h](j)}(h``coherency_features``h]j)}(hjYuh]hcoherency_features}(hj[uhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMWhjSuubj()}(hhh](h)}(hCoherency features.h]hCoherency features.}(hjruhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMPhjouubh)}(h/Combination of drm_panthor_gpu_coherency flags.h]h/Combination of drm_panthor_gpu_coherency flags.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMRhjouubh)}(hNote that this is just what the coherency protocols supported by the GPU, but the actual coherency in place depends on the SoC integration and is reflected by drm_panthor_gpu_info::selected_coherency.h]hNote that this is just what the coherency protocols supported by the GPU, but the actual coherency in place depends on the SoC integration and is reflected by drm_panthor_gpu_info::selected_coherency.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMThjouubeh}(h]h ]h"]h$]h&]uh1j'hjSuubeh}(h]h ]h"]h$]h&]uh1jhjnuhMWhjrubj)}(h'``texture_features`` Texture features. h](j)}(h``texture_features``h]j)}(hjuh]htexture_features}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM[hjuubj()}(hhh]h)}(hTexture features.h]hTexture features.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhM[hjuubah}(h]h ]h"]h$]h&]uh1j'hjuubeh}(h]h ]h"]h$]h&]uh1jhjuhM[hjrubj)}(hP``as_present`` Bitmask encoding the number of address-space exposed by the MMU. h](j)}(h``as_present``h]j)}(hjuh]h as_present}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM^hjuubj()}(hhh]h)}(h@Bitmask encoding the number of address-space exposed by the MMU.h]h@Bitmask encoding the number of address-space exposed by the MMU.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhM^hjvubah}(h]h ]h"]h$]h&]uh1j'hjuubeh}(h]h ]h"]h$]h&]uh1jhjuhM^hjrubj)}(h^``selected_coherency`` Coherency selected for this device. One of drm_panthor_gpu_coherency. h](j)}(h``selected_coherency``h]j)}(hj#vh]hselected_coherency}(hj%vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!vubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMdhjvubj()}(hhh](h)}(h#Coherency selected for this device.h]h#Coherency selected for this device.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM|hj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)drm_panthor_timestamp_info_flags (C enum)"c.drm_panthor_timestamp_info_flagshNtauh1jhj'fhhhNhNubj)}(hhh](j)}(h drm_panthor_timestamp_info_flagsh]j)}(h%enum drm_panthor_timestamp_info_flagsh](j)}(hjSh]henum}(hjfzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbzhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjtzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbzhhhjszhMubj)}(h drm_panthor_timestamp_info_flagsh]j)}(hj`zh]h drm_panthor_timestamp_info_flags}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ](j jeh"]h$]h&]jjuh1jhjbzhhhjszhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj^zhhhjszhMubah}(h]jYzah ](j j!eh"]h$]h&]j%j&)j'huh1jhjszhMhj[zhhubj))}(hhh]h)}(h drm_panthor_timestamp_info.flagsh]h drm_panthor_timestamp_info.flags}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjzhhubah}(h]h ]h"]h$]h&]uh1j(hj[zhhhjszhMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjzjLjzjMjNjOuh1jhhhj'fhNhNubjQ)}(hXr**Constants** ``DRM_PANTHOR_TIMESTAMP_GPU`` Query GPU time. ``DRM_PANTHOR_TIMESTAMP_CPU_NONE`` Don't query CPU time. ``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC`` Query CPU time using CLOCK_MONOTONIC. ``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW`` Query CPU time using CLOCK_MONOTONIC_RAW. ``DRM_PANTHOR_TIMESTAMP_CPU_TYPE_MASK`` Space reserved for CPU clock type. ``DRM_PANTHOR_TIMESTAMP_GPU_OFFSET`` Query GPU offset. ``DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT`` Query GPU cycle count. ``DRM_PANTHOR_TIMESTAMP_FREQ`` Query timestamp frequency. ``DRM_PANTHOR_TIMESTAMP_DURATION`` Return duration of time query.h](h)}(h **Constants**h]h)}(hjzh]h Constants}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjzubj )}(hhh](j)}(h.``DRM_PANTHOR_TIMESTAMP_GPU`` Query GPU time. h](j)}(h``DRM_PANTHOR_TIMESTAMP_GPU``h]j)}(hjzh]hDRM_PANTHOR_TIMESTAMP_GPU}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjzubj()}(hhh]h)}(hQuery GPU time.h]hQuery GPU time.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMhjzubah}(h]h ]h"]h$]h&]uh1j'hjzubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjzubj)}(h9``DRM_PANTHOR_TIMESTAMP_CPU_NONE`` Don't query CPU time. h](j)}(h"``DRM_PANTHOR_TIMESTAMP_CPU_NONE``h]j)}(hj"{h]hDRM_PANTHOR_TIMESTAMP_CPU_NONE}(hj${hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj {ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj{ubj()}(hhh]h)}(hDon't query CPU time.h]hDon’t query CPU time.}(hj;{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7{hMhj8{ubah}(h]h ]h"]h$]h&]uh1j'hj{ubeh}(h]h ]h"]h$]h&]uh1jhj7{hMhjzubj)}(hN``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC`` Query CPU time using CLOCK_MONOTONIC. h](j)}(h'``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC``h]j)}(hj[{h]h#DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC}(hj]{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY{ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjU{ubj()}(hhh]h)}(h%Query CPU time using CLOCK_MONOTONIC.h]h%Query CPU time using CLOCK_MONOTONIC.}(hjt{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp{hMhjq{ubah}(h]h ]h"]h$]h&]uh1j'hjU{ubeh}(h]h ]h"]h$]h&]uh1jhjp{hMhjzubj)}(hV``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW`` Query CPU time using CLOCK_MONOTONIC_RAW. h](j)}(h+``DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW``h]j)}(hj{h]h'DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj{ubj()}(hhh]h)}(h)Query CPU time using CLOCK_MONOTONIC_RAW.h]h)Query CPU time using CLOCK_MONOTONIC_RAW.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hMhj{ubah}(h]h ]h"]h$]h&]uh1j'hj{ubeh}(h]h ]h"]h$]h&]uh1jhj{hMhjzubj)}(hK``DRM_PANTHOR_TIMESTAMP_CPU_TYPE_MASK`` Space reserved for CPU clock type. h](j)}(h'``DRM_PANTHOR_TIMESTAMP_CPU_TYPE_MASK``h]j)}(hj{h]h#DRM_PANTHOR_TIMESTAMP_CPU_TYPE_MASK}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj{ubj()}(hhh]h)}(h"Space reserved for CPU clock type.h]h"Space reserved for CPU clock type.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hMhj{ubah}(h]h ]h"]h$]h&]uh1j'hj{ubeh}(h]h ]h"]h$]h&]uh1jhj{hMhjzubj)}(h7``DRM_PANTHOR_TIMESTAMP_GPU_OFFSET`` Query GPU offset. h](j)}(h$``DRM_PANTHOR_TIMESTAMP_GPU_OFFSET``h]j)}(hj|h]h DRM_PANTHOR_TIMESTAMP_GPU_OFFSET}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|ubj()}(hhh]h)}(hQuery GPU offset.h]hQuery GPU offset.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMhj|ubah}(h]h ]h"]h$]h&]uh1j'hj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hMhjzubj)}(hA``DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT`` Query GPU cycle count. h](j)}(h)``DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT``h]j)}(hj?|h]h%DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT}(hjA|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj9|ubj()}(hhh]h)}(hQuery GPU cycle count.h]hQuery GPU cycle count.}(hjX|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT|hMhjU|ubah}(h]h ]h"]h$]h&]uh1j'hj9|ubeh}(h]h ]h"]h$]h&]uh1jhjT|hMhjzubj)}(h:``DRM_PANTHOR_TIMESTAMP_FREQ`` Query timestamp frequency. h](j)}(h``DRM_PANTHOR_TIMESTAMP_FREQ``h]j)}(hjx|h]hDRM_PANTHOR_TIMESTAMP_FREQ}(hjz|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjv|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjr|ubj()}(hhh]h)}(hQuery timestamp frequency.h]hQuery timestamp frequency.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMhj|ubah}(h]h ]h"]h$]h&]uh1j'hjr|ubeh}(h]h ]h"]h$]h&]uh1jhj|hMhjzubj)}(hA``DRM_PANTHOR_TIMESTAMP_DURATION`` Return duration of time query.h](j)}(h"``DRM_PANTHOR_TIMESTAMP_DURATION``h]j)}(hj|h]hDRM_PANTHOR_TIMESTAMP_DURATION}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|ubj()}(hhh]h)}(hReturn duration of time query.h]hReturn duration of time query.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|ubah}(h]h ]h"]h$]h&]uh1j'hj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hMhjzubeh}(h]h ]h"]h$]h&]uh1j hjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_panthor_timestamp_info (C struct)c.drm_panthor_timestamp_infohNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_timestamp_infoh]j)}(h!struct drm_panthor_timestamp_infoh](j)}(hjh]hstruct}(hj }hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhhj}hMubj)}(hdrm_panthor_timestamp_infoh]j)}(hj}h]hdrm_panthor_timestamp_info}(hj+}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'}ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj}hhhj}hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj}hhhj}hMubah}(h]j|ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj}hMhj}hhubj))}(hhh]h)}(hTimestamp informationh]hTimestamp information}(hjM}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjJ}hhubah}(h]h ]h"]h$]h&]uh1j(hj}hhhj}hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKje}jLje}jMjNjOuh1jhhhj'fhNhNubjQ)}(hXI**Definition**:: struct drm_panthor_timestamp_info { __u64 timestamp_frequency; __u64 current_timestamp; __u64 timestamp_offset; __u32 flags; __u32 duration_nsec; __u64 cycle_count; __u64 cpu_timestamp_sec; __u64 cpu_timestamp_nsec; }; **Members** ``timestamp_frequency`` The frequency of the timestamp timer or 0 if unknown. ``current_timestamp`` The current GPU timestamp. ``timestamp_offset`` The offset of the GPU timestamp timer. ``flags`` Bitmask of drm_panthor_timestamp_info_flags. If set to 0, then it is interpreted as: DRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQ Note: these flags are exclusive to each other (only one can be used): - DRM_PANTHOR_TIMESTAMP_CPU_NONE - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW ``duration_nsec`` Duration of time query. ``cycle_count`` Value of GPU_CYCLE_COUNT. ``cpu_timestamp_sec`` Seconds part of CPU timestamp. ``cpu_timestamp_nsec`` Nanseconds part of CPU timestamp.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjq}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjm}ubh:}(hjm}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhji}ubjt)}(hstruct drm_panthor_timestamp_info { __u64 timestamp_frequency; __u64 current_timestamp; __u64 timestamp_offset; __u32 flags; __u32 duration_nsec; __u64 cycle_count; __u64 cpu_timestamp_sec; __u64 cpu_timestamp_nsec; };h]hstruct drm_panthor_timestamp_info { __u64 timestamp_frequency; __u64 current_timestamp; __u64 timestamp_offset; __u32 flags; __u32 duration_nsec; __u64 cycle_count; __u64 cpu_timestamp_sec; __u64 cpu_timestamp_nsec; };}hj}sbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhji}ubh)}(h **Members**h]h)}(hj}h]hMembers}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhji}ubj )}(hhh](j)}(hN``timestamp_frequency`` The frequency of the timestamp timer or 0 if unknown. h](j)}(h``timestamp_frequency``h]j)}(hj}h]htimestamp_frequency}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj}ubj()}(hhh]h)}(h5The frequency of the timestamp timer or 0 if unknown.h]h5The frequency of the timestamp timer or 0 if unknown.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj}ubah}(h]h ]h"]h$]h&]uh1j'hj}ubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj}ubj)}(h1``current_timestamp`` The current GPU timestamp. h](j)}(h``current_timestamp``h]j)}(hj}h]hcurrent_timestamp}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj}ubj()}(hhh]h)}(hThe current GPU timestamp.h]hThe current GPU timestamp.}(hj ~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ~hMhj ~ubah}(h]h ]h"]h$]h&]uh1j'hj}ubeh}(h]h ]h"]h$]h&]uh1jhj ~hMhj}ubj)}(h<``timestamp_offset`` The offset of the GPU timestamp timer. h](j)}(h``timestamp_offset``h]j)}(hj-~h]htimestamp_offset}(hj/~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'~ubj()}(hhh]h)}(h&The offset of the GPU timestamp timer.h]h&The offset of the GPU timestamp timer.}(hjF~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB~hMhjC~ubah}(h]h ]h"]h$]h&]uh1j'hj'~ubeh}(h]h ]h"]h$]h&]uh1jhjB~hMhj}ubj)}(hXu``flags`` Bitmask of drm_panthor_timestamp_info_flags. If set to 0, then it is interpreted as: DRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQ Note: these flags are exclusive to each other (only one can be used): - DRM_PANTHOR_TIMESTAMP_CPU_NONE - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW h](j)}(h ``flags``h]j)}(hjf~h]hflags}(hjh~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjd~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj`~ubj()}(hhh](h)}(h,Bitmask of drm_panthor_timestamp_info_flags.h]h,Bitmask of drm_panthor_timestamp_info_flags.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|~ubj )}(hhh]j)}(hIf set to 0, then it is interpreted as: DRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQ h](j)}(h'If set to 0, then it is interpreted as:h]h'If set to 0, then it is interpreted as:}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj~ubj()}(hhh]h)}(hYDRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQh]hYDRM_PANTHOR_TIMESTAMP_GPU | DRM_PANTHOR_TIMESTAMP_GPU_OFFSET | DRM_PANTHOR_TIMESTAMP_FREQ}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj~ubah}(h]h ]h"]h$]h&]uh1j'hj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hMhj~ubah}(h]h ]h"]h$]h&]uh1j hj|~ubh)}(hNote: these flags are exclusive to each other (only one can be used): - DRM_PANTHOR_TIMESTAMP_CPU_NONE - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAWh]hNote: these flags are exclusive to each other (only one can be used): - DRM_PANTHOR_TIMESTAMP_CPU_NONE - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC - DRM_PANTHOR_TIMESTAMP_CPU_MONOTONIC_RAW}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj|~ubeh}(h]h ]h"]h$]h&]uh1j'hj`~ubeh}(h]h ]h"]h$]h&]uh1jhj{~hMhj}ubj)}(h*``duration_nsec`` Duration of time query. h](j)}(h``duration_nsec``h]j)}(hj~h]h duration_nsec}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj~ubj()}(hhh]h)}(hDuration of time query.h]hDuration of time query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hMhj~ubah}(h]h ]h"]h$]h&]uh1j'hj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hMhj}ubj)}(h*``cycle_count`` Value of GPU_CYCLE_COUNT. h](j)}(h``cycle_count``h]j)}(hj"h]h cycle_count}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(hValue of GPU_CYCLE_COUNT.h]hValue of GPU_CYCLE_COUNT.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj8ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj7hMhj}ubj)}(h5``cpu_timestamp_sec`` Seconds part of CPU timestamp. h](j)}(h``cpu_timestamp_sec``h]j)}(hj[h]hcpu_timestamp_sec}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjUubj()}(hhh]h)}(hSeconds part of CPU timestamp.h]hSeconds part of CPU timestamp.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphMhjqubah}(h]h ]h"]h$]h&]uh1j'hjUubeh}(h]h ]h"]h$]h&]uh1jhjphMhj}ubj)}(h8``cpu_timestamp_nsec`` Nanseconds part of CPU timestamp.h](j)}(h``cpu_timestamp_nsec``h]j)}(hjh]hcpu_timestamp_nsec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h!Nanseconds part of CPU timestamp.h]h!Nanseconds part of CPU timestamp.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj}ubeh}(h]h ]h"]h$]h&]uh1j hji}ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubh)}(hKStructure grouping all queryable information relating to the GPU timestamp.h]hKStructure grouping all queryable information relating to the GPU timestamp.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,drm_panthor_group_priorities_info (C struct)#c.drm_panthor_group_priorities_infohNtauh1jhj'fhhhNhNubj)}(hhh](j)}(h!drm_panthor_group_priorities_infoh]j)}(h(struct drm_panthor_group_priorities_infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj"hMubj)}(h!drm_panthor_group_priorities_infoh]j)}(hjh]h!drm_panthor_group_priorities_info}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhj"hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj"hMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj"hMhj hhubj))}(hhh]h)}(hGroup priorities informationh]hGroup priorities information}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjThhubah}(h]h ]h"]h$]h&]uh1j(hj hhhj"hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjojLjojMjNjOuh1jhhhj'fhNhNubjQ)}(hX"**Definition**:: struct drm_panthor_group_priorities_info { __u8 allowed_mask; __u8 pad[3]; }; **Members** ``allowed_mask`` Bitmask of the allowed group priorities. Each bit represents a variant of the enum drm_panthor_group_priority. ``pad`` Padding fields, MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwubh:}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjsubjt)}(hUstruct drm_panthor_group_priorities_info { __u8 allowed_mask; __u8 pad[3]; };h]hUstruct drm_panthor_group_priorities_info { __u8 allowed_mask; __u8 pad[3]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjsubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjsubj )}(hhh](j)}(h``allowed_mask`` Bitmask of the allowed group priorities. Each bit represents a variant of the enum drm_panthor_group_priority. h](j)}(h``allowed_mask``h]j)}(hjĀh]h allowed_mask}(hjƀhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj€ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(h(Bitmask of the allowed group priorities.h]h(Bitmask of the allowed group priorities.}(hj݀hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjڀubh)}(hEEach bit represents a variant of the enum drm_panthor_group_priority.h]hEEach bit represents a variant of the enum drm_panthor_group_priority.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjـhMhjڀubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjـhMhjubj)}(h``pad`` Padding fields, MBZ.h](j)}(h``pad``h]j)}(hj h]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(hPadding fields, MBZ.h]hPadding fields, MBZ.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj"ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj!hMhjubeh}(h]h ]h"]h$]h&]uh1j hjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubh)}(h**Description**h]h)}(hjOh]h Description}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubh)}(hVStructure grouping all queryable information relating to the allowed group priorities.h]hVStructure grouping all queryable information relating to the allowed group priorities.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_panthor_dev_query (C struct)c.drm_panthor_dev_queryhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_dev_queryh]j)}(hstruct drm_panthor_dev_queryh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_panthor_dev_queryh]j)}(hjh]hdrm_panthor_dev_query}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h/Arguments passed to DRM_PANTHOR_IOCTL_DEV_QUERYh]h/Arguments passed to DRM_PANTHOR_IOCTL_DEV_QUERY}(hjρhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj́hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; }; **Members** ``type`` the query type (see drm_panthor_dev_query_type). ``size`` size of the type being queried. If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace. ``pointer`` user pointer to a query type struct. Pointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubjt)}(hTstruct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; };h]hTstruct drm_panthor_dev_query { __u32 type; __u32 size; __u64 pointer; };}hj sbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(h:``type`` the query type (see drm_panthor_dev_query_type). h](j)}(h``type``h]j)}(hj<h]htype}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj6ubj()}(hhh]h)}(h0the query type (see drm_panthor_dev_query_type).h]h0the query type (see drm_panthor_dev_query_type).}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhMhjRubah}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jhjQhMhj3ubj)}(hXM``size`` size of the type being queried. If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace. h](j)}(h``size``h]j)}(hjuh]hsize}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM hjoubj()}(hhh](h)}(hsize of the type being queried.h]hsize of the type being queried.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hX"If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace.h]hX"If pointer is NULL, size is updated by the driver to provide the output structure size. If pointer is not NULL, the driver will only copy min(size, actual_structure_size) bytes to the pointer, and update the size accordingly. This allows us to extend query types without breaking userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjoubeh}(h]h ]h"]h$]h&]uh1jhjhM hj3ubj)}(h``pointer`` user pointer to a query type struct. Pointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h](j)}(h ``pointer``h]j)}(hjh]hpointer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(h$user pointer to a query type struct.h]h$user pointer to a query type struct.}(hjׂhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjԂubh)}(hPointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that's large enough to hold size bytes.h]hPointer can be NULL, in which case, nothing is copied, but the actual structure size is returned. If not NULL, it must point to a location that’s large enough to hold size bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjԂubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjӂhMhj3ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_panthor_vm_create (C struct)c.drm_panthor_vm_createhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_createh]j)}(hstruct drm_panthor_vm_createh](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhj4hMubj)}(hdrm_panthor_vm_createh]j)}(hj!h]hdrm_panthor_vm_create}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ](j jeh"]h$]h&]jjuh1jhj#hhhj4hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj4hMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj4hMhjhhubj))}(hhh]h)}(h/Arguments passed to DRM_PANTHOR_IOCTL_VM_CREATEh]h/Arguments passed to DRM_PANTHOR_IOCTL_VM_CREATE}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjfhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj4hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; }; **Members** ``flags`` VM flags, MBZ. ``id`` Returned VM ID. ``user_va_range`` Size of the VA space reserved for user objects. The kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel. If user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**. User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubjt)}(hYstruct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; };h]hYstruct drm_panthor_vm_create { __u32 flags; __u32 id; __u64 user_va_range; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM$hjubj )}(hhh](j)}(h``flags`` VM flags, MBZ. h](j)}(h ``flags``h]j)}(hjփh]hflags}(hj؃hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjԃubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjЃubj()}(hhh]h)}(hVM flags, MBZ.h]hVM flags, MBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjЃubeh}(h]h ]h"]h$]h&]uh1jhjhMhj̓ubj)}(h``id`` Returned VM ID. h](j)}(h``id``h]j)}(hjh]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj ubj()}(hhh]h)}(hReturned VM ID.h]hReturned VM ID.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMhj%ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhj̓ubj)}(hX``user_va_range`` Size of the VA space reserved for user objects. The kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel. If user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**. User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h](j)}(h``user_va_range``h]j)}(hjHh]h user_va_range}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM3hjBubj()}(hhh](h)}(h/Size of the VA space reserved for user objects.h]h/Size of the VA space reserved for user objects.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM#hj^ubh)}(hXThe kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel.h]hXThe kernel will pick the remaining space to map kernel-only objects to the VM (heap chunks, heap context, ring buffers, kernel synchronization objects, ...). If the space left for kernel objects is too small, kernel object allocation will fail further down the road. One can use drm_panthor_gpu_info::mmu_features to extract the total virtual address range, and chose a user_va_range that leaves some space to the kernel.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM%hj^ubh)}(hXIf user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in **user_va_range**.h](hXoIf user_va_range is zero, the kernel will pick a sensible value based on TASK_SIZE and the virtual range supported by the GPU MMU (the kernel/user split should leave enough VA space for userspace processes to support SVM, while still allowing the kernel to map some amount of kernel objects in the kernel VA range). The value chosen by the driver will be returned in }(hjhhhNhNubh)}(h**user_va_range**h]h user_va_range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM,hj^ubh)}(h]User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.h]h]User VA space always starts at 0x0, kernel VA space is always placed after the user VA range.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hM3hj^ubeh}(h]h ]h"]h$]h&]uh1j'hjBubeh}(h]h ]h"]h$]h&]uh1jhj]hM3hj̓ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_panthor_vm_destroy (C struct)c.drm_panthor_vm_destroyhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_destroyh]j)}(hstruct drm_panthor_vm_destroyh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj܄hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM:ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj܄hhhjhM:ubj)}(hdrm_panthor_vm_destroyh]j)}(hjڄh]hdrm_panthor_vm_destroy}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhj܄hhhjhM:ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj؄hhhjhM:ubah}(h]jӄah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM:hjՄhhubj))}(hhh]h)}(h0Arguments passed to DRM_PANTHOR_IOCTL_VM_DESTROYh]h0Arguments passed to DRM_PANTHOR_IOCTL_VM_DESTROY}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM9hjhhubah}(h]h ]h"]h$]h&]uh1j(hjՄhhhjhM:ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj:jLj:jMjNjOuh1jhhhj'fhNhNubjQ)}(h**Definition**:: struct drm_panthor_vm_destroy { __u32 id; __u32 pad; }; **Members** ``id`` ID of the VM to destroy. ``pad`` MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBubh:}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM=hj>ubjt)}(h?struct drm_panthor_vm_destroy { __u32 id; __u32 pad; };h]h?struct drm_panthor_vm_destroy { __u32 id; __u32 pad; };}hj_sbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM?hj>ubh)}(h **Members**h]h)}(hjph]hMembers}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMDhj>ubj )}(hhh](j)}(h ``id`` ID of the VM to destroy. h](j)}(h``id``h]j)}(hjh]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM=hjubj()}(hhh]h)}(hID of the VM to destroy.h]hID of the VM to destroy.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM=hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM=hjubj)}(h ``pad`` MBZ.h](j)}(h``pad``h]j)}(hjȅh]hpad}(hjʅhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjƅubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM?hj…ubj()}(hhh]h)}(hMBZ.h]hMBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM@hjޅubah}(h]h ]h"]h$]h&]uh1j'hj…ubeh}(h]h ]h"]h$]h&]uh1jhj݅hM?hjubeh}(h]h ]h"]h$]h&]uh1j hj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_panthor_vm_bind_op_flags (C enum)c.drm_panthor_vm_bind_op_flagshNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_bind_op_flagsh]j)}(h!enum drm_panthor_vm_bind_op_flagsh](j)}(hjSh]henum}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMFubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj/hMFubj)}(hdrm_panthor_vm_bind_op_flagsh]j)}(hjh]hdrm_panthor_vm_bind_op_flags}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhj/hMFubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj/hMFubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj/hMFhjhhubj))}(hhh]h)}(hVM bind operation flagsh]hVM bind operation flags}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMDhjahhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj/hMFubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKj|jLj|jMjNjOuh1jhhhj'fhNhNubjQ)}(hXO**Constants** ``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY`` Map the memory read-only. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC`` Map the memory not-executable. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED`` Map the memory uncached. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. ``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK`` Mask used to determine the type of operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP`` Map operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP`` Unmap operation. ``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY`` No VM operation. Just serves as a synchronization point on a VM queue. Only valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMHhjubj )}(hhh](j)}(ht``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY`` Map the memory read-only. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h'``DRM_PANTHOR_VM_BIND_OP_MAP_READONLY``h]j)}(hjh]h#DRM_PANTHOR_VM_BIND_OP_MAP_READONLY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMMhjubj()}(hhh](h)}(hMap the memory read-only.h]hMap the memory read-only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMKhjubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hj͆hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMMhjubj)}(hw``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC`` Map the memory not-executable. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h%``DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC``h]j)}(hjh]h!DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMRhjubj()}(hhh](h)}(hMap the memory not-executable.h]hMap the memory not-executable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMPhjubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMRhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMRhjubj)}(hs``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED`` Map the memory uncached. Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP. h](j)}(h'``DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED``h]j)}(hj5h]h#DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMWhj/ubj()}(hhh](h)}(hMap the memory uncached.h]hMap the memory uncached.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMUhjKubh)}(h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.h]h0Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMWhjKubeh}(h]h ]h"]h$]h&]uh1j'hj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhMWhjubj)}(hS``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK`` Mask used to determine the type of operation. h](j)}(h$``DRM_PANTHOR_VM_BIND_OP_TYPE_MASK``h]j)}(hj}h]h DRM_PANTHOR_VM_BIND_OP_TYPE_MASK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMZhjwubj()}(hhh]h)}(h-Mask used to determine the type of operation.h]h-Mask used to determine the type of operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMZhjubah}(h]h ]h"]h$]h&]uh1j'hjwubeh}(h]h ]h"]h$]h&]uh1jhjhMZhjubj)}(h3``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP`` Map operation. h](j)}(h#``DRM_PANTHOR_VM_BIND_OP_TYPE_MAP``h]j)}(hjh]hDRM_PANTHOR_VM_BIND_OP_TYPE_MAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM]hjubj()}(hhh]h)}(hMap operation.h]hMap operation.}(hjχhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjˇhM]hj̇ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjˇhM]hjubj)}(h7``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP`` Unmap operation. h](j)}(h%``DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP``h]j)}(hjh]h!DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM`hjubj()}(hhh]h)}(hUnmap operation.h]hUnmap operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM`hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM`hjubj)}(hX``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY`` No VM operation. Just serves as a synchronization point on a VM queue. Only valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](j)}(h)``DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY``h]j)}(hj(h]h%DRM_PANTHOR_VM_BIND_OP_TYPE_SYNC_ONLY}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMghj"ubj()}(hhh](h)}(hNo VM operation.h]hNo VM operation.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMchj>ubh)}(h5Just serves as a synchronization point on a VM queue.h]h5Just serves as a synchronization point on a VM queue.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMehj>ubh)}(hOnly valid if ``DRM_PANTHOR_VM_BIND_ASYNC`` is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.h](hOnly valid if }(hj_hhhNhNubj)}(h``DRM_PANTHOR_VM_BIND_ASYNC``h]hDRM_PANTHOR_VM_BIND_ASYNC}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubhg is set in drm_panthor_vm_bind::flags, and drm_panthor_vm_bind_op::syncs contains at least one element.}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj=hMghj>ubeh}(h]h ]h"]h$]h&]uh1j'hj"ubeh}(h]h ]h"]h$]h&]uh1jhj=hMghjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_panthor_vm_bind_op (C struct)c.drm_panthor_vm_bind_ophNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_bind_oph]j)}(hstruct drm_panthor_vm_bind_oph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMmubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMmubj)}(hdrm_panthor_vm_bind_oph]j)}(hjh]hdrm_panthor_vm_bind_op}(hjшhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj͈ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMmubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMmubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMmhjhhubj))}(hhh]h)}(hVM bind operationh]hVM bind operation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMshjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMmubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj jLj jMjNjOuh1jhhhj'fhNhNubjQ)}(hX`**Definition**:: struct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; }; **Members** ``flags`` Combination of drm_panthor_vm_bind_op_flags flags. ``bo_handle`` Handle of the buffer object to map. MBZ for unmap or sync-only operations. ``bo_offset`` Buffer object offset. MBZ for unmap or sync-only operations. ``va`` Virtual address to map/unmap. MBZ for sync-only operations. ``size`` Size to map/unmap. MBZ for sync-only operations. ``syncs`` Array of struct drm_panthor_sync_op synchronization operations. This array must be empty if ``DRM_PANTHOR_VM_BIND_ASYNC`` is not set on the drm_panthor_vm_bind object containing this VM bind operation. This array shall not be empty for sync-only operations.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMwhjubjt)}(hstruct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; };h]hstruct drm_panthor_vm_bind_op { __u32 flags; __u32 bo_handle; __u64 bo_offset; __u64 va; __u64 size; struct drm_panthor_obj_array syncs; };}hj0sbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMyhjubh)}(h **Members**h]h)}(hjAh]hMembers}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(h=``flags`` Combination of drm_panthor_vm_bind_op_flags flags. h](j)}(h ``flags``h]j)}(hj`h]hflags}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMwhjZubj()}(hhh]h)}(h2Combination of drm_panthor_vm_bind_op_flags flags.h]h2Combination of drm_panthor_vm_bind_op_flags flags.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMwhjvubah}(h]h ]h"]h$]h&]uh1j'hjZubeh}(h]h ]h"]h$]h&]uh1jhjuhMwhjWubj)}(hY``bo_handle`` Handle of the buffer object to map. MBZ for unmap or sync-only operations. h](j)}(h ``bo_handle``h]j)}(hjh]h bo_handle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM|hjubj()}(hhh]h)}(hJHandle of the buffer object to map. MBZ for unmap or sync-only operations.h]hJHandle of the buffer object to map. MBZ for unmap or sync-only operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM{hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM|hjWubj)}(hK``bo_offset`` Buffer object offset. MBZ for unmap or sync-only operations. h](j)}(h ``bo_offset``h]j)}(hjӉh]h bo_offset}(hjՉhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjщubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj͉ubj()}(hhh]h)}(h**Definition**:: struct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; }; **Members** ``vm_id`` VM targeted by the bind request. ``flags`` Combination of drm_panthor_vm_bind_flags flags. ``ops`` Array of struct drm_panthor_vm_bind_op bind operations.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubh:}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjEubjt)}(hgstruct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; };h]hgstruct drm_panthor_vm_bind { __u32 vm_id; __u32 flags; struct drm_panthor_obj_array ops; };}hjfsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjEubh)}(h **Members**h]h)}(hjwh]hMembers}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjEubj )}(hhh](j)}(h+``vm_id`` VM targeted by the bind request. h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h VM targeted by the bind request.h]h VM targeted by the bind request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h:``flags`` Combination of drm_panthor_vm_bind_flags flags. h](j)}(h ``flags``h]j)}(hjόh]hflags}(hjьhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj͌ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjɌubj()}(hhh]h)}(h/Combination of drm_panthor_vm_bind_flags flags.h]h/Combination of drm_panthor_vm_bind_flags flags.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjɌubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h?``ops`` Array of struct drm_panthor_vm_bind_op bind operations.h](j)}(h``ops``h]j)}(hjh]hops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h7Array of struct drm_panthor_vm_bind_op bind operations.h]h7Array of struct drm_panthor_vm_bind_op bind operations.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjEubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_panthor_vm_state (C enum)c.drm_panthor_vm_statehNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_stateh]j)}(henum drm_panthor_vm_stateh](j)}(hjSh]henum}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhjohMubj)}(hdrm_panthor_vm_stateh]j)}(hj\h]hdrm_panthor_vm_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj^hhhjohMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjZhhhjohMubah}(h]jUah ](j j!eh"]h$]h&]j%j&)j'huh1jhjohMhjWhhubj))}(hhh]h)}(h VM states.h]h VM states.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjWhhhjohMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Constants** ``DRM_PANTHOR_VM_STATE_USABLE`` VM is usable. New VM operations will be accepted on this VM. ``DRM_PANTHOR_VM_STATE_UNUSABLE`` VM is unusable. Something put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason). Once the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted. The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h](h)}(h **Constants**h]h)}(hjƍh]h Constants}(hjȍhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjčubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(h^``DRM_PANTHOR_VM_STATE_USABLE`` VM is usable. New VM operations will be accepted on this VM. h](j)}(h``DRM_PANTHOR_VM_STATE_USABLE``h]j)}(hjh]hDRM_PANTHOR_VM_STATE_USABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjߍubj()}(hhh](h)}(h VM is usable.h]h VM is usable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h.New VM operations will be accepted on this VM.h]h.New VM operations will be accepted on this VM.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjߍubeh}(h]h ]h"]h$]h&]uh1jhjhMhj܍ubj)}(hX``DRM_PANTHOR_VM_STATE_UNUSABLE`` VM is unusable. Something put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason). Once the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted. The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h](j)}(h!``DRM_PANTHOR_VM_STATE_UNUSABLE``h]j)}(hj-h]hDRM_PANTHOR_VM_STATE_UNUSABLE}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'ubj()}(hhh](h)}(hVM is unusable.h]hVM is unusable.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjCubh)}(hhSomething put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason).h]hhSomething put the VM in an unusable state (like an asynchronous VM_BIND request failing for any reason).}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjCubh)}(hOnce the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted.h]hOnce the VM is in this state, all new MAP operations will be rejected, and any GPU job targeting this VM will fail. UNMAP operations are still accepted.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjCubh)}(h[The only way to recover from an unusable VM is to create a new VM, and destroy the old one.h]h[The only way to recover from an unusable VM is to create a new VM, and destroy the old one.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMhjCubeh}(h]h ]h"]h$]h&]uh1j'hj'ubeh}(h]h ]h"]h$]h&]uh1jhjBhMhj܍ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_vm_get_state (C struct)c.drm_panthor_vm_get_statehNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_vm_get_stateh]j)}(hstruct drm_panthor_vm_get_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_panthor_vm_get_stateh]j)}(hjh]hdrm_panthor_vm_get_state}(hjӎhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjώubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h Get VM state.h]h Get VM state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj jLj jMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; }; **Members** ``vm_id`` VM targeted by the get_state request. ``state`` state returned by the driver. Must be one of the enum drm_panthor_vm_state values.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubjt)}(hFstruct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; };h]hFstruct drm_panthor_vm_get_state { __u32 vm_id; __u32 state; };}hj2sbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjCh]hMembers}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(h0``vm_id`` VM targeted by the get_state request. h](j)}(h ``vm_id``h]j)}(hjbh]hvm_id}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj\ubj()}(hhh]h)}(h%VM targeted by the get_state request.h]h%VM targeted by the get_state request.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhMhjxubah}(h]h ]h"]h$]h&]uh1j'hj\ubeh}(h]h ]h"]h$]h&]uh1jhjwhMhjYubj)}(h]``state`` state returned by the driver. Must be one of the enum drm_panthor_vm_state values.h](j)}(h ``state``h]j)}(hjh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(hstate returned by the driver.h]hstate returned by the driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h4Must be one of the enum drm_panthor_vm_state values.h]h4Must be one of the enum drm_panthor_vm_state values.}(hjÏhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjYubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_panthor_bo_flags (C enum)c.drm_panthor_bo_flagshNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_flagsh]j)}(henum drm_panthor_bo_flagsh](j)}(hjSh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_panthor_bo_flagsh]j)}(hjh]hdrm_panthor_bo_flags}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h-Buffer object flags, passed at creation time.h]h-Buffer object flags, passed at creation time.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjChhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKj^jLj^jMjNjOuh1jhhhj'fhNhNubjQ)}(hXp**Constants** ``DRM_PANTHOR_BO_NO_MMAP`` The buffer object will never be CPU-mapped in userspace. ``DRM_PANTHOR_BO_WB_MMAP`` Force "Write-Back Cacheable" CPU mapping. CPU map the buffer object in userspace by forcing the "Write-Back Cacheable" cacheability attribute. The mapping otherwise uses the "Non-Cacheable" attribute if the GPU is not IO coherent.h](h)}(h **Constants**h]h)}(hjhh]h Constants}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjbubj )}(hhh](j)}(hT``DRM_PANTHOR_BO_NO_MMAP`` The buffer object will never be CPU-mapped in userspace. h](j)}(h``DRM_PANTHOR_BO_NO_MMAP``h]j)}(hjh]hDRM_PANTHOR_BO_NO_MMAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h8The buffer object will never be CPU-mapped in userspace.h]h8The buffer object will never be CPU-mapped in userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj~ubj)}(hX``DRM_PANTHOR_BO_WB_MMAP`` Force "Write-Back Cacheable" CPU mapping. CPU map the buffer object in userspace by forcing the "Write-Back Cacheable" cacheability attribute. The mapping otherwise uses the "Non-Cacheable" attribute if the GPU is not IO coherent.h](j)}(h``DRM_PANTHOR_BO_WB_MMAP``h]j)}(hjh]hDRM_PANTHOR_BO_WB_MMAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(h)Force "Write-Back Cacheable" CPU mapping.h]h-Force “Write-Back Cacheable” CPU mapping.}(hjِhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj֐ubh)}(hCPU map the buffer object in userspace by forcing the "Write-Back Cacheable" cacheability attribute. The mapping otherwise uses the "Non-Cacheable" attribute if the GPU is not IO coherent.h]hCPU map the buffer object in userspace by forcing the “Write-Back Cacheable” cacheability attribute. The mapping otherwise uses the “Non-Cacheable” attribute if the GPU is not IO coherent.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj֐ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjՐhMhj~ubeh}(h]h ]h"]h$]h&]uh1j hjbubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_panthor_bo_create (C struct)c.drm_panthor_bo_createhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_createh]j)}(hstruct drm_panthor_bo_createh](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhhj6hMubj)}(hdrm_panthor_bo_createh]j)}(hj#h]hdrm_panthor_bo_create}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ](j jeh"]h$]h&]jjuh1jhj%hhhj6hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj!hhhj6hMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj6hMhjhhubj))}(hhh]h)}(h0Arguments passed to DRM_IOCTL_PANTHOR_BO_CREATE.h]h0Arguments passed to DRM_IOCTL_PANTHOR_BO_CREATE.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj6hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; }; **Members** ``size`` Requested size for the object The (page-aligned) allocated size for the object will be returned. ``flags`` Flags. Must be a combination of drm_panthor_bo_flags flags. ``exclusive_vm_id`` Exclusive VM this buffer object will be mapped to. If not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd ``handle`` Returned handle for the object. Object handles are nonzero. ``pad`` MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubjt)}(h~struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; };h]h~struct drm_panthor_bo_create { __u64 size; __u32 flags; __u32 exclusive_vm_id; __u32 handle; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(hk``size`` Requested size for the object The (page-aligned) allocated size for the object will be returned. h](j)}(h``size``h]j)}(hjؑh]hsize}(hjڑhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj֑ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjґubj()}(hhh](h)}(hRequested size for the objecth]hRequested size for the object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hBThe (page-aligned) allocated size for the object will be returned.h]hBThe (page-aligned) allocated size for the object will be returned.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjґubeh}(h]h ]h"]h$]h&]uh1jhjhMhjϑubj)}(hF``flags`` Flags. Must be a combination of drm_panthor_bo_flags flags. h](j)}(h ``flags``h]j)}(hj h]hflags}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h;Flags. Must be a combination of drm_panthor_bo_flags flags.h]h;Flags. Must be a combination of drm_panthor_bo_flags flags.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMhj6ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj5hMhjϑubj)}(h``exclusive_vm_id`` Exclusive VM this buffer object will be mapped to. If not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd h](j)}(h``exclusive_vm_id``h]j)}(hjYh]hexclusive_vm_id}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjSubj()}(hhh](h)}(h2Exclusive VM this buffer object will be mapped to.h]h2Exclusive VM this buffer object will be mapped to.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjoubj )}(hhh]j)}(hIf not zero, the field must refer to a valid VM ID, and implies that: - the buffer object will only ever be bound to that VM - cannot be exported as a PRIME fd h](j)}(hEIf not zero, the field must refer to a valid VM ID, and implies that:h]hEIf not zero, the field must refer to a valid VM ID, and implies that:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnhMhjubj()}(hhh]j )}(hhh](j )}(h4the buffer object will only ever be bound to that VMh]h)}(hjh]h4the buffer object will only ever be bound to that VM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h!cannot be exported as a PRIME fd h]h)}(h cannot be exported as a PRIME fdh]h cannot be exported as a PRIME fd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjubah}(h]h ]h"]h$]h&]uh1j hjoubeh}(h]h ]h"]h$]h&]uh1j'hjSubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjϑubj)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM hj ubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjϑubj)}(h ``pad`` MBZ.h](j)}(h``pad``h]j)}(hj>h]hpad}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj8ubj()}(hhh]h)}(hMBZ.h]hMBZ.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjTubah}(h]h ]h"]h$]h&]uh1j'hj8ubeh}(h]h ]h"]h$]h&]uh1jhjShMhjϑubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_panthor_bo_mmap_offset (C struct)c.drm_panthor_bo_mmap_offsethNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_mmap_offseth]j)}(h!struct drm_panthor_bo_mmap_offseth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_panthor_bo_mmap_offseth]j)}(hjh]hdrm_panthor_bo_mmap_offset}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h5Arguments passed to DRM_IOCTL_PANTHOR_BO_MMAP_OFFSET.h]h5Arguments passed to DRM_IOCTL_PANTHOR_BO_MMAP_OFFSET.}(hjړhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjדhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; }; **Members** ``handle`` Handle of the object we want an mmap offset for. ``pad`` MBZ. ``offset`` The fake offset to use for subsequent mmap calls.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubjt)}(hYstruct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; };h]hYstruct drm_panthor_bo_mmap_offset { __u32 handle; __u32 pad; __u64 offset; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hj(h]hMembers}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM#hjubj )}(hhh](j)}(h<``handle`` Handle of the object we want an mmap offset for. h](j)}(h ``handle``h]j)}(hjGh]hhandle}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjAubj()}(hhh]h)}(h0Handle of the object we want an mmap offset for.h]h0Handle of the object we want an mmap offset for.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMhj]ubah}(h]h ]h"]h$]h&]uh1j'hjAubeh}(h]h ]h"]h$]h&]uh1jhj\hMhj>ubj)}(h ``pad`` MBZ. h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjzubj()}(hhh]h)}(hMBZ.h]hMBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjzubeh}(h]h ]h"]h$]h&]uh1jhjhMhj>ubj)}(h<``offset`` The fake offset to use for subsequent mmap calls.h](j)}(h ``offset``h]j)}(hjh]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM hjubj()}(hhh]h)}(h1The fake offset to use for subsequent mmap calls.h]h1The fake offset to use for subsequent mmap calls.}(hjҔhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM!hjϔubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjΔhM hj>ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_queue_create (C struct)c.drm_panthor_queue_createhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_queue_createh]j)}(hstruct drm_panthor_queue_createh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM'ubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj hM'ubj)}(hdrm_panthor_queue_createh]j)}(hj h]hdrm_panthor_queue_create}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhj hM'ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hM'ubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj hM'hjhhubj))}(hhh]h)}(hQueue creation arguments.h]hQueue creation arguments.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM%hjRhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj hM'ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjmjLjmjMjNjOuh1jhhhj'fhNhNubjQ)}(hXc**Definition**:: struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; }; **Members** ``priority`` Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority. ``pad`` Padding fields, MBZ. ``ringbuf_size`` Size of the ring buffer to allocate to this queue.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuubh:}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM)hjqubjt)}(h`struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; };h]h`struct drm_panthor_queue_create { __u8 priority; __u8 pad[3]; __u32 ringbuf_size; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM+hjqubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM1hjqubj )}(hhh](j)}(hn``priority`` Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority. h](j)}(h ``priority``h]j)}(hj•h]hpriority}(hjĕhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM+hjubj()}(hhh]h)}(h`Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority.h]h`Defines the priority of queues inside a group. Goes from 0 to 15, 15 being the highest priority.}(hjەhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM*hjؕubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjוhM+hjubj)}(h``pad`` Padding fields, MBZ. h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM/hjubj()}(hhh]h)}(hPadding fields, MBZ.h]hPadding fields, MBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM/hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM/hjubj)}(hC``ringbuf_size`` Size of the ring buffer to allocate to this queue.h](j)}(h``ringbuf_size``h]j)}(hj5h]h ringbuf_size}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM1hj/ubj()}(hhh]h)}(h2Size of the ring buffer to allocate to this queue.h]h2Size of the ring buffer to allocate to this queue.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM2hjKubah}(h]h ]h"]h$]h&]uh1j'hj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhM1hjubeh}(h]h ]h"]h$]h&]uh1j hjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_group_priority (C enum)c.drm_panthor_group_priorityhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_priorityh]j)}(henum drm_panthor_group_priorityh](j)}(hjSh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM8ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM8ubj)}(hdrm_panthor_group_priorityh]j)}(hjh]hdrm_panthor_group_priority}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhM8ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM8ubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM8hjhhubj))}(hhh]h)}(hScheduling group priorityh]hScheduling group priority}(hjіhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM6hjΖhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhM8ubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hXG**Constants** ``PANTHOR_GROUP_PRIORITY_LOW`` Low priority group. ``PANTHOR_GROUP_PRIORITY_MEDIUM`` Medium priority group. ``PANTHOR_GROUP_PRIORITY_HIGH`` High priority group. Requires CAP_SYS_NICE or DRM_MASTER. ``PANTHOR_GROUP_PRIORITY_REALTIME`` Realtime priority group. Requires CAP_SYS_NICE or DRM_MASTER.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM:hjubj )}(hhh](j)}(h3``PANTHOR_GROUP_PRIORITY_LOW`` Low priority group. h](j)}(h``PANTHOR_GROUP_PRIORITY_LOW``h]j)}(hjh]hPANTHOR_GROUP_PRIORITY_LOW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM=hj ubj()}(hhh]h)}(hLow priority group.h]hLow priority group.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM=hj(ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj'hM=hj ubj)}(h9``PANTHOR_GROUP_PRIORITY_MEDIUM`` Medium priority group. h](j)}(h!``PANTHOR_GROUP_PRIORITY_MEDIUM``h]j)}(hjKh]hPANTHOR_GROUP_PRIORITY_MEDIUM}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM@hjEubj()}(hhh]h)}(hMedium priority group.h]hMedium priority group.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hM@hjaubah}(h]h ]h"]h$]h&]uh1j'hjEubeh}(h]h ]h"]h$]h&]uh1jhj`hM@hj ubj)}(h[``PANTHOR_GROUP_PRIORITY_HIGH`` High priority group. Requires CAP_SYS_NICE or DRM_MASTER. h](j)}(h``PANTHOR_GROUP_PRIORITY_HIGH``h]j)}(hjh]hPANTHOR_GROUP_PRIORITY_HIGH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMEhj~ubj()}(hhh](h)}(hHigh priority group.h]hHigh priority group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMChjubh)}(h$Requires CAP_SYS_NICE or DRM_MASTER.h]h$Requires CAP_SYS_NICE or DRM_MASTER.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMEhjubeh}(h]h ]h"]h$]h&]uh1j'hj~ubeh}(h]h ]h"]h$]h&]uh1jhjhMEhj ubj)}(hb``PANTHOR_GROUP_PRIORITY_REALTIME`` Realtime priority group. Requires CAP_SYS_NICE or DRM_MASTER.h](j)}(h#``PANTHOR_GROUP_PRIORITY_REALTIME``h]j)}(hj̗h]hPANTHOR_GROUP_PRIORITY_REALTIME}(hjΗhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjʗubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMIhjƗubj()}(hhh](h)}(hRealtime priority group.h]hRealtime priority group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMHhjubh)}(h$Requires CAP_SYS_NICE or DRM_MASTER.h]h$Requires CAP_SYS_NICE or DRM_MASTER.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMJhjubeh}(h]h ]h"]h$]h&]uh1j'hjƗubeh}(h]h ]h"]h$]h&]uh1jhjhMIhj ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_group_create (C struct)c.drm_panthor_group_createhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_createh]j)}(hstruct drm_panthor_group_createh](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMOubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhjBhMOubj)}(hdrm_panthor_group_createh]j)}(hj/h]hdrm_panthor_group_create}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ](j jeh"]h$]h&]jjuh1jhj1hhhjBhMOubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj-hhhjBhMOubah}(h]j(ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjBhMOhj*hhubj))}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_CREATEh]h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_CREATE}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMOhjthhubah}(h]h ]h"]h$]h&]uh1j(hj*hhhjBhMOubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; }; **Members** ``queues`` Array of drm_panthor_queue_create elements. ``max_compute_cores`` Maximum number of cores that can be used by compute jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **compute_core_mask**. ``max_fragment_cores`` Maximum number of cores that can be used by fragment jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **fragment_core_mask**. ``max_tiler_cores`` Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **tiler_core_mask**. ``priority`` Group priority (see enum drm_panthor_group_priority). ``pad`` Padding field, MBZ. ``compute_core_mask`` Mask encoding cores that can be used for compute jobs. This field must have at least **max_compute_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. ``fragment_core_mask`` Mask encoding cores that can be used for fragment jobs. This field must have at least **max_fragment_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. ``tiler_core_mask`` Mask encoding cores that can be used for tiler jobs. This field must have at least **max_tiler_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::tiler_present. ``vm_id`` VM ID to bind this group to. All submission to queues bound to this group will use this VM. ``group_handle`` Returned group handle. Passed back when submitting jobs or destroying a group.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMShjubjt)}(hXAstruct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; };h]hXAstruct drm_panthor_group_create { struct drm_panthor_obj_array queues; __u8 max_compute_cores; __u8 max_fragment_cores; __u8 max_tiler_cores; __u8 priority; __u32 pad; __u64 compute_core_mask; __u64 fragment_core_mask; __u64 tiler_core_mask; __u32 vm_id; __u32 group_handle; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMUhjubh)}(h **Members**h]h)}(hjŘh]hMembers}(hjǘhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjØubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMchjubj )}(hhh](j)}(h7``queues`` Array of drm_panthor_queue_create elements. h](j)}(h ``queues``h]j)}(hjh]hqueues}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMShjޘubj()}(hhh]h)}(h+Array of drm_panthor_queue_create elements.h]h+Array of drm_panthor_queue_create elements.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMShjubah}(h]h ]h"]h$]h&]uh1j'hjޘubeh}(h]h ]h"]h$]h&]uh1jhjhMShjۘubj)}(h``max_compute_cores`` Maximum number of cores that can be used by compute jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **compute_core_mask**. h](j)}(h``max_compute_cores``h]j)}(hjh]hmax_compute_cores}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMZhjubj()}(hhh](h)}(h^Maximum number of cores that can be used by compute jobs across CS queues bound to this group.h]h^Maximum number of cores that can be used by compute jobs across CS queues bound to this group.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMWhj3ubh)}(hIMust be less or equal to the number of bits set in **compute_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjEhhhNhNubh)}(h**compute_core_mask**h]hcompute_core_mask}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEubh.}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj2hMZhj3ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj2hMZhjۘubj)}(h``max_fragment_cores`` Maximum number of cores that can be used by fragment jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **fragment_core_mask**. h](j)}(h``max_fragment_cores``h]j)}(hjwh]hmax_fragment_cores}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMbhjqubj()}(hhh](h)}(h_Maximum number of cores that can be used by fragment jobs across CS queues bound to this group.h]h_Maximum number of cores that can be used by fragment jobs across CS queues bound to this group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM_hjubh)}(hJMust be less or equal to the number of bits set in **fragment_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjhhhNhNubh)}(h**fragment_core_mask**h]hfragment_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMbhjubeh}(h]h ]h"]h$]h&]uh1j'hjqubeh}(h]h ]h"]h$]h&]uh1jhjhMbhjۘubj)}(h``max_tiler_cores`` Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group. Must be less or equal to the number of bits set in **tiler_core_mask**. h](j)}(h``max_tiler_cores``h]j)}(hjљh]hmax_tiler_cores}(hjәhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϙubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMjhj˙ubj()}(hhh](h)}(h]Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group.h]h]Maximum number of tilers that can be used by tiler jobs across CS queues bound to this group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMghjubh)}(hGMust be less or equal to the number of bits set in **tiler_core_mask**.h](h3Must be less or equal to the number of bits set in }(hjhhhNhNubh)}(h**tiler_core_mask**h]htiler_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMjhjubeh}(h]h ]h"]h$]h&]uh1j'hj˙ubeh}(h]h ]h"]h$]h&]uh1jhjhMjhjۘubj)}(hC``priority`` Group priority (see enum drm_panthor_group_priority). h](j)}(h ``priority``h]j)}(hj+h]hpriority}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMnhj%ubj()}(hhh]h)}(h5Group priority (see enum drm_panthor_group_priority).h]h5Group priority (see enum drm_panthor_group_priority).}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMnhjAubah}(h]h ]h"]h$]h&]uh1j'hj%ubeh}(h]h ]h"]h$]h&]uh1jhj@hMnhjۘubj)}(h``pad`` Padding field, MBZ. h](j)}(h``pad``h]j)}(hjdh]hpad}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMqhj^ubj()}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhMqhjzubah}(h]h ]h"]h$]h&]uh1j'hj^ubeh}(h]h ]h"]h$]h&]uh1jhjyhMqhjۘubj)}(h``compute_core_mask`` Mask encoding cores that can be used for compute jobs. This field must have at least **max_compute_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. h](j)}(h``compute_core_mask``h]j)}(hjh]hcompute_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMyhjubj()}(hhh](h)}(h6Mask encoding cores that can be used for compute jobs.h]h6Mask encoding cores that can be used for compute jobs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMuhjubh)}(h=This field must have at least **max_compute_cores** bits set.h](hThis field must have at least }(hjŚhhhNhNubh)}(h**max_compute_cores**h]hmax_compute_cores}(hj͚hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjŚubh bits set.}(hjŚhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMwhjubh)}(hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.h]hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMyhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMyhjۘubj)}(h``fragment_core_mask`` Mask encoding cores that can be used for fragment jobs. This field must have at least **max_fragment_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::shader_present. h](j)}(h``fragment_core_mask``h]j)}(hjh]hfragment_core_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(h7Mask encoding cores that can be used for fragment jobs.h]h7Mask encoding cores that can be used for fragment jobs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM~hjubh)}(h>This field must have at least **max_fragment_cores** bits set.h](hThis field must have at least }(hj.hhhNhNubh)}(h**max_fragment_cores**h]hmax_fragment_cores}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.ubh bits set.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.h]hMThe bits set here should also be set in drm_panthor_gpu_info::shader_present.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjۘubj)}(h``tiler_core_mask`` Mask encoding cores that can be used for tiler jobs. This field must have at least **max_tiler_cores** bits set. The bits set here should also be set in drm_panthor_gpu_info::tiler_present. h](j)}(h``tiler_core_mask``h]j)}(hjoh]htiler_core_mask}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjiubj()}(hhh](h)}(h4Mask encoding cores that can be used for tiler jobs.h]h4Mask encoding cores that can be used for tiler jobs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h;This field must have at least **max_tiler_cores** bits set.h](hThis field must have at least }(hjhhhNhNubh)}(h**max_tiler_cores**h]hmax_tiler_cores}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh bits set.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hLThe bits set here should also be set in drm_panthor_gpu_info::tiler_present.h]hLThe bits set here should also be set in drm_panthor_gpu_info::tiler_present.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjiubeh}(h]h ]h"]h$]h&]uh1jhjhMhjۘubj)}(hg``vm_id`` VM ID to bind this group to. All submission to queues bound to this group will use this VM. h](j)}(h ``vm_id``h]j)}(hj؛h]hvm_id}(hjڛhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj֛ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjқubj()}(hhh](h)}(hVM ID to bind this group to.h]hVM ID to bind this group to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h>All submission to queues bound to this group will use this VM.h]h>All submission to queues bound to this group will use this VM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjқubeh}(h]h ]h"]h$]h&]uh1jhjhMhjۘubj)}(h_``group_handle`` Returned group handle. Passed back when submitting jobs or destroying a group.h](j)}(h``group_handle``h]j)}(hj h]h group_handle}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(hNReturned group handle. Passed back when submitting jobs or destroying a group.h]hNReturned group handle. Passed back when submitting jobs or destroying a group.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMhj6ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj5hMhjۘubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_panthor_group_destroy (C struct)c.drm_panthor_group_destroyhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_destroyh]j)}(h struct drm_panthor_group_destroyh](j)}(hjh]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuhhhjhMubj)}(hdrm_panthor_group_destroyh]j)}(hjsh]hdrm_panthor_group_destroy}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjuhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjqhhhjhMubah}(h]jlah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjnhhubj))}(hhh]h)}(h3Arguments passed to DRM_IOCTL_PANTHOR_GROUP_DESTROYh]h3Arguments passed to DRM_IOCTL_PANTHOR_GROUP_DESTROY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjnhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjӜjLjӜjMjNjOuh1jhhhj'fhNhNubjQ)}(h**Definition**:: struct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; }; **Members** ``group_handle`` Group to destroy ``pad`` Padding field, MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjߜhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjۜubh:}(hjۜhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjלubjt)}(hLstruct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; };h]hLstruct drm_panthor_group_destroy { __u32 group_handle; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjלubh)}(h **Members**h]h)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjלubj )}(hhh](j)}(h"``group_handle`` Group to destroy h](j)}(h``group_handle``h]j)}(hj(h]h group_handle}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj"ubj()}(hhh]h)}(hGroup to destroyh]hGroup to destroy}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMhj>ubah}(h]h ]h"]h$]h&]uh1j'hj"ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhjubj)}(h``pad`` Padding field, MBZ.h](j)}(h``pad``h]j)}(hjah]hpad}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj[ubj()}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjwubah}(h]h ]h"]h$]h&]uh1j'hj[ubeh}(h]h ]h"]h$]h&]uh1jhjvhMhjubeh}(h]h ]h"]h$]h&]uh1j hjלubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_queue_submit (C struct)c.drm_panthor_queue_submithNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_queue_submith]j)}(hstruct drm_panthor_queue_submith](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjɝhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjȝhMubj)}(hdrm_panthor_queue_submith]j)}(hjh]hdrm_panthor_queue_submit}(hj۝hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjםubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjȝhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjȝhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjȝhMhjhhubj))}(hhh]h)}(hJob submission arguments.h]hJob submission arguments.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjȝhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; }; **Members** ``queue_index`` Index of the queue inside a group. ``stream_size`` Size of the command stream to execute. Must be 64-bit/8-byte aligned (the size of a CS instruction) Can be zero if stream_addr is zero too. When the stream size is zero, the queue submit serves as a synchronization point. ``stream_addr`` GPU address of the command stream to execute. Must be aligned on 64-byte. Can be zero is stream_size is zero too. ``latest_flush`` FLUSH_ID read at the time the stream was built. This allows cache flush elimination for the automatic flush+invalidate(all) done at submission time, which is needed to ensure the GPU doesn't get garbage when reading the indirect command stream buffers. If you want the cache flush to happen unconditionally, pass a zero here. Ignored when stream_size is zero. ``pad`` MBZ. ``syncs`` Array of struct drm_panthor_sync_op sync operations.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubjt)}(hstruct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; };h]hstruct drm_panthor_queue_submit { __u32 queue_index; __u32 stream_size; __u64 stream_addr; __u32 latest_flush; __u32 pad; struct drm_panthor_obj_array syncs; };}hj:sbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjKh]hMembers}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(h3``queue_index`` Index of the queue inside a group. h](j)}(h``queue_index``h]j)}(hjjh]h queue_index}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjdubj()}(hhh]h)}(h"Index of the queue inside a group.h]h"Index of the queue inside a group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjdubeh}(h]h ]h"]h$]h&]uh1jhjhMhjaubj)}(h``stream_size`` Size of the command stream to execute. Must be 64-bit/8-byte aligned (the size of a CS instruction) Can be zero if stream_addr is zero too. When the stream size is zero, the queue submit serves as a synchronization point. h](j)}(h``stream_size``h]j)}(hjh]h stream_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(h&Size of the command stream to execute.h]h&Size of the command stream to execute.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h``syncs`` Array of struct drm_panthor_sync_op sync operations.h](j)}(h ``syncs``h]j)}(hjh]hsyncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h4Array of struct drm_panthor_sync_op sync operations.h]h4Array of struct drm_panthor_sync_op sync operations.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjaubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubh)}(h**Description**h]h)}(hj4h]h Description}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubh)}(hThis is describing the userspace command stream to call from the kernel command stream ring-buffer. Queue submission is always part of a group submission, taking one or more jobs to submit to the underlying queues.h]hThis is describing the userspace command stream to call from the kernel command stream ring-buffer. Queue submission is always part of a group submission, taking one or more jobs to submit to the underlying queues.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_group_submit (C struct)c.drm_panthor_group_submithNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_submith]j)}(hstruct drm_panthor_group_submith](j)}(hjh]hstruct}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnhhhjhMubj)}(hdrm_panthor_group_submith]j)}(hjlh]hdrm_panthor_group_submit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjnhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjjhhhjhMubah}(h]jeah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjghhubj))}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_SUBMITh]h2Arguments passed to DRM_IOCTL_PANTHOR_GROUP_SUBMIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjghhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj̠jLj̠jMjNjOuh1jhhhj'fhNhNubjQ)}(hX.**Definition**:: struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; }; **Members** ``group_handle`` Handle of the group to queue jobs to. ``pad`` MBZ. ``queue_submits`` Array of drm_panthor_queue_submit objects.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjؠhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjԠubh:}(hjԠhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjРubjt)}(h{struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; };h]h{struct drm_panthor_group_submit { __u32 group_handle; __u32 pad; struct drm_panthor_obj_array queue_submits; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjРubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjРubj )}(hhh](j)}(h7``group_handle`` Handle of the group to queue jobs to. h](j)}(h``group_handle``h]j)}(hj!h]h group_handle}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h%Handle of the group to queue jobs to.h]h%Handle of the group to queue jobs to.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj7ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj6hMhjubj)}(h ``pad`` MBZ. h](j)}(h``pad``h]j)}(hjZh]hpad}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjTubj()}(hhh]h)}(hMBZ.h]hMBZ.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohMhjpubah}(h]h ]h"]h$]h&]uh1j'hjTubeh}(h]h ]h"]h$]h&]uh1jhjohMhjubj)}(h<``queue_submits`` Array of drm_panthor_queue_submit objects.h](j)}(h``queue_submits``h]j)}(hjh]h queue_submits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h*Array of drm_panthor_queue_submit objects.h]h*Array of drm_panthor_queue_submit objects.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjРubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&drm_panthor_group_state_flags (C enum)c.drm_panthor_group_state_flagshNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_state_flagsh]j)}(h"enum drm_panthor_group_state_flagsh](j)}(hjSh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_panthor_group_state_flagsh]j)}(hjh]hdrm_panthor_group_state_flags}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(hGroup state flagsh]hGroup state flags}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj,hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjGjLjGjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Constants** ``DRM_PANTHOR_GROUP_STATE_TIMEDOUT`` Group had unfinished jobs. When a group ends up with this flag set, no jobs can be submitted to its queues. ``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT`` Group had fatal faults. When a group ends up with this flag set, no jobs can be submitted to its queues. ``DRM_PANTHOR_GROUP_STATE_INNOCENT`` Group was killed during a reset caused by other groups. This flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h](h)}(h **Constants**h]h)}(hjQh]h Constants}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjKubj )}(hhh](j)}(h``DRM_PANTHOR_GROUP_STATE_TIMEDOUT`` Group had unfinished jobs. When a group ends up with this flag set, no jobs can be submitted to its queues. h](j)}(h$``DRM_PANTHOR_GROUP_STATE_TIMEDOUT``h]j)}(hjph]h DRM_PANTHOR_GROUP_STATE_TIMEDOUT}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjjubj()}(hhh](h)}(hGroup had unfinished jobs.h]hGroup had unfinished jobs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.h]hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjgubj)}(h``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT`` Group had fatal faults. When a group ends up with this flag set, no jobs can be submitted to its queues. h](j)}(h'``DRM_PANTHOR_GROUP_STATE_FATAL_FAULT``h]j)}(hjh]h#DRM_PANTHOR_GROUP_STATE_FATAL_FAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(hGroup had fatal faults.h]hGroup had fatal faults.}(hjѢhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj΢ubh)}(hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.h]hPWhen a group ends up with this flag set, no jobs can be submitted to its queues.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj͢hMhj΢ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj͢hMhjgubj)}(h``DRM_PANTHOR_GROUP_STATE_INNOCENT`` Group was killed during a reset caused by other groups. This flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h](j)}(h$``DRM_PANTHOR_GROUP_STATE_INNOCENT``h]j)}(hjh]h DRM_PANTHOR_GROUP_STATE_INNOCENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(h7Group was killed during a reset caused by other groups.h]h7Group was killed during a reset caused by other groups.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(htThis flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.h]htThis flag can only be set if DRM_PANTHOR_GROUP_STATE_TIMEDOUT is set and DRM_PANTHOR_GROUP_STATE_FATAL_FAULT is not.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjgubeh}(h]h ]h"]h$]h&]uh1j hjKubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&drm_panthor_group_get_state (C struct)c.drm_panthor_group_get_statehNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_group_get_stateh]j)}(h"struct drm_panthor_group_get_stateh](j)}(hjh]hstruct}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdhhhjuhMubj)}(hdrm_panthor_group_get_stateh]j)}(hjbh]hdrm_panthor_group_get_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjdhhhjuhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj`hhhjuhMubah}(h]j[ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjuhMhj]hhubj))}(hhh]h)}(h5Arguments passed to DRM_IOCTL_PANTHOR_GROUP_GET_STATEh]h5Arguments passed to DRM_IOCTL_PANTHOR_GROUP_GET_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hj]hhhjuhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj£jLj£jMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; }; **Members** ``group_handle`` Handle of the group to query state on ``state`` Combination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state. ``fatal_queues`` Bitmask of queues that faced fatal faults. ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjΣhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjʣubh:}(hjʣhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM hjƣubjt)}(hwstruct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; };h]hwstruct drm_panthor_group_get_state { __u32 group_handle; __u32 state; __u32 fatal_queues; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM hjƣubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjƣubj )}(hhh](j)}(h7``group_handle`` Handle of the group to query state on h](j)}(h``group_handle``h]j)}(hjh]h group_handle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM hjubj()}(hhh]h)}(h%Handle of the group to query state onh]h%Handle of the group to query state on}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hM hj-ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj,hM hjubj)}(hS``state`` Combination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state. h](j)}(h ``state``h]j)}(hjPh]hstate}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjJubj()}(hhh]h)}(hHCombination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state.h]hHCombination of DRM_PANTHOR_GROUP_STATE_* flags encoding the group state.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjfubah}(h]h ]h"]h$]h&]uh1j'hjJubeh}(h]h ]h"]h$]h&]uh1jhjehMhjubj)}(h<``fatal_queues`` Bitmask of queues that faced fatal faults. h](j)}(h``fatal_queues``h]j)}(hjh]h fatal_queues}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h*Bitmask of queues that faced fatal faults.h]h*Bitmask of queues that faced fatal faults.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hjäh]hpad}(hjŤhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hjܤhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj٤ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjؤhMhjubeh}(h]h ]h"]h$]h&]uh1j hjƣubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubh)}(hbUsed to query the state of a group and decide whether a new group should be created to replace it.h]hbUsed to query the state of a group and decide whether a new group should be created to replace it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(drm_panthor_tiler_heap_create (C struct)c.drm_panthor_tiler_heap_createhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_tiler_heap_createh]j)}(h$struct drm_panthor_tiler_heap_createh](j)}(hjh]hstruct}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM ubj)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@hhhjQhM ubj)}(hdrm_panthor_tiler_heap_createh]j)}(hj>h]hdrm_panthor_tiler_heap_create}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj@hhhjQhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj<hhhjQhM ubah}(h]j7ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjQhM hj9hhubj))}(hhh]h)}(h7Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_CREATEh]h7Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hj9hhhjQhM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hXp**Definition**:: struct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; }; **Members** ``vm_id`` VM ID the tiler heap should be mapped to ``initial_chunk_count`` Initial number of chunks to allocate. Must be at least one. ``chunk_size`` Chunk size. Must be page-aligned and lie in the [128k:8M] range. ``max_chunks`` Maximum number of chunks that can be allocated. Must be at least **initial_chunk_count**. ``target_in_flight`` Maximum number of in-flight render passes. If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs. ``handle`` Returned heap handle. Passed back to DESTROY_TILER_HEAP. ``tiler_heap_ctx_gpu_va`` Returned heap GPU virtual address returned ``first_heap_chunk_gpu_va`` First heap chunk. The tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM!hjubjt)}(hstruct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; };h]hstruct drm_panthor_tiler_heap_create { __u32 vm_id; __u32 initial_chunk_count; __u32 chunk_size; __u32 max_chunks; __u32 target_in_flight; __u32 handle; __u64 tiler_heap_ctx_gpu_va; __u64 first_heap_chunk_gpu_va; };}hjåsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM#hjubh)}(h **Members**h]h)}(hjԥh]hMembers}(hj֥hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjҥubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM.hjubj )}(hhh](j)}(h3``vm_id`` VM ID the tiler heap should be mapped to h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM!hjubj()}(hhh]h)}(h(VM ID the tiler heap should be mapped toh]h(VM ID the tiler heap should be mapped to}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM!hj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM!hjubj)}(hT``initial_chunk_count`` Initial number of chunks to allocate. Must be at least one. h](j)}(h``initial_chunk_count``h]j)}(hj,h]hinitial_chunk_count}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM$hj&ubj()}(hhh]h)}(h;Initial number of chunks to allocate. Must be at least one.h]h;Initial number of chunks to allocate. Must be at least one.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhM$hjBubah}(h]h ]h"]h$]h&]uh1j'hj&ubeh}(h]h ]h"]h$]h&]uh1jhjAhM$hjubj)}(hQ``chunk_size`` Chunk size. Must be page-aligned and lie in the [128k:8M] range. h](j)}(h``chunk_size``h]j)}(hjeh]h chunk_size}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM*hj_ubj()}(hhh](h)}(h Chunk size.h]h Chunk size.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM(hj{ubh)}(h4Must be page-aligned and lie in the [128k:8M] range.h]h4Must be page-aligned and lie in the [128k:8M] range.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhM*hj{ubeh}(h]h ]h"]h$]h&]uh1j'hj_ubeh}(h]h ]h"]h$]h&]uh1jhjzhM*hjubj)}(hj``max_chunks`` Maximum number of chunks that can be allocated. Must be at least **initial_chunk_count**. h](j)}(h``max_chunks``h]j)}(hjh]h max_chunks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM1hjubj()}(hhh](h)}(h/Maximum number of chunks that can be allocated.h]h/Maximum number of chunks that can be allocated.}(hjƦhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM/hjæubh)}(h)Must be at least **initial_chunk_count**.h](hMust be at least }(hjզhhhNhNubh)}(h**initial_chunk_count**h]hinitial_chunk_count}(hjݦhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjզubh.}(hjզhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj¦hM1hjæubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj¦hM1hjubj)}(h``target_in_flight`` Maximum number of in-flight render passes. If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs. h](j)}(h``target_in_flight``h]j)}(hjh]htarget_in_flight}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM9hjubj()}(hhh](h)}(h*Maximum number of in-flight render passes.h]h*Maximum number of in-flight render passes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM6hjubh)}(h{If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs.h]h{If the heap has more than tiler jobs in-flight, the FW will wait for render passes to finish before queuing new tiler jobs.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM8hjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM9hjubj)}(hD``handle`` Returned heap handle. Passed back to DESTROY_TILER_HEAP. h](j)}(h ``handle``h]j)}(hjPh]hhandle}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM=hjJubj()}(hhh]h)}(h8Returned heap handle. Passed back to DESTROY_TILER_HEAP.h]h8Returned heap handle. Passed back to DESTROY_TILER_HEAP.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehM=hjfubah}(h]h ]h"]h$]h&]uh1j'hjJubeh}(h]h ]h"]h$]h&]uh1jhjehM=hjubj)}(hE``tiler_heap_ctx_gpu_va`` Returned heap GPU virtual address returned h](j)}(h``tiler_heap_ctx_gpu_va``h]j)}(hjh]htiler_heap_ctx_gpu_va}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM@hjubj()}(hhh]h)}(h*Returned heap GPU virtual address returnedh]h*Returned heap GPU virtual address returned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM@hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM@hjubj)}(h``first_heap_chunk_gpu_va`` First heap chunk. The tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h](j)}(h``first_heap_chunk_gpu_va``h]j)}(hj§h]hfirst_heap_chunk_gpu_va}(hjħhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMFhjubj()}(hhh](h)}(hFirst heap chunk.h]hFirst heap chunk.}(hjۧhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMDhjاubh)}(hjThe tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.h]hjThe tiler heap is formed of heap chunks forming a single-link list. This is the first element in the list.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjקhMFhjاubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjקhMFhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)drm_panthor_tiler_heap_destroy (C struct) c.drm_panthor_tiler_heap_destroyhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_tiler_heap_destroyh]j)}(h%struct drm_panthor_tiler_heap_destroyh](j)}(hjh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMMubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&hhhj7hMMubj)}(hdrm_panthor_tiler_heap_destroyh]j)}(hj$h]hdrm_panthor_tiler_heap_destroy}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ](j jeh"]h$]h&]jjuh1jhj&hhhj7hMMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj"hhhj7hMMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj7hMMhjhhubj))}(hhh]h)}(h8Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROYh]h8Arguments passed to DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROY}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMLhjihhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj7hMMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; }; **Members** ``handle`` Handle of the tiler heap to destroy. Must be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE. ``pad`` Padding field, MBZ.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMPhjubjt)}(hKstruct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; };h]hKstruct drm_panthor_tiler_heap_destroy { __u32 handle; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMRhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMWhjubj )}(hhh](j)}(h~``handle`` Handle of the tiler heap to destroy. Must be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE. h](j)}(h ``handle``h]j)}(hj٨h]hhandle}(hjۨhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjרubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMShjӨubj()}(hhh](h)}(h$Handle of the tiler heap to destroy.h]h$Handle of the tiler heap to destroy.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMQhjubh)}(hLMust be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE.h]hLMust be a valid heap handle returned by DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMShjubeh}(h]h ]h"]h$]h&]uh1j'hjӨubeh}(h]h ]h"]h$]h&]uh1jhjhMShjШubj)}(h``pad`` Padding field, MBZ.h](j)}(h``pad``h]j)}(hj!h]hpad}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMVhjubj()}(hhh]h)}(hPadding field, MBZ.h]hPadding field, MBZ.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMWhj7ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj6hMVhjШubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_bo_set_label (C struct)c.drm_panthor_bo_set_labelhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_set_labelh]j)}(hstruct drm_panthor_bo_set_labelh](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM]ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwhhhjhM]ubj)}(hdrm_panthor_bo_set_labelh]j)}(hjuh]hdrm_panthor_bo_set_label}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjwhhhjhM]ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjshhhjhM]ubah}(h]jnah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM]hjphhubj))}(hhh]h)}(h2Arguments passed to DRM_IOCTL_PANTHOR_BO_SET_LABELh]h2Arguments passed to DRM_IOCTL_PANTHOR_BO_SET_LABEL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM[hjhhubah}(h]h ]h"]h$]h&]uh1j(hjphhhjhM]ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjթjLjթjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; }; **Members** ``handle`` Handle of the buffer object to label. ``pad`` MBZ. ``label`` User pointer to a NUL-terminated string Length cannot be greater than 4096h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjݩubh:}(hjݩhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM_hj٩ubjt)}(hVstruct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; };h]hVstruct drm_panthor_bo_set_label { __u32 handle; __u32 pad; __u64 label; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMahj٩ubh)}(h **Members**h]h)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMghj٩ubj )}(hhh](j)}(h1``handle`` Handle of the buffer object to label. h](j)}(h ``handle``h]j)}(hj*h]hhandle}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM_hj$ubj()}(hhh]h)}(h%Handle of the buffer object to label.h]h%Handle of the buffer object to label.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hM_hj@ubah}(h]h ]h"]h$]h&]uh1j'hj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hM_hj!ubj)}(h ``pad`` MBZ. h](j)}(h``pad``h]j)}(hjch]hpad}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMbhj]ubj()}(hhh]h)}(hMBZ.h]hMBZ.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMbhjyubah}(h]h ]h"]h$]h&]uh1j'hj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhMbhj!ubj)}(hU``label`` User pointer to a NUL-terminated string Length cannot be greater than 4096h](j)}(h ``label``h]j)}(hjh]hlabel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMghjubj()}(hhh](h)}(h'User pointer to a NUL-terminated stringh]h'User pointer to a NUL-terminated string}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMfhjubh)}(h"Length cannot be greater than 4096h]h"Length cannot be greater than 4096}(hjĪhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMghj!ubeh}(h]h ]h"]h$]h&]uh1j hj٩ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+drm_panthor_set_user_mmio_offset (C struct)"c.drm_panthor_set_user_mmio_offsethNtauh1jhj'fhhhNhNubj)}(hhh](j)}(h drm_panthor_set_user_mmio_offseth]j)}(h'struct drm_panthor_set_user_mmio_offseth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMnubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMnubj)}(h drm_panthor_set_user_mmio_offseth]j)}(hjh]h drm_panthor_set_user_mmio_offset}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMnubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMnubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMnhjhhubj))}(hhh]h)}(h:Arguments passed to DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSETh]h:Arguments passed to DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSET}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMmhjDhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMnubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj_jLj_jMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_set_user_mmio_offset { __u64 offset; }; **Members** ``offset`` User MMIO offset to use. Must be either DRM_PANTHOR_USER_MMIO_OFFSET_32BIT or DRM_PANTHOR_USER_MMIO_OFFSET_64BIT. Use DRM_PANTHOR_USER_MMIO_OFFSET (which selects OFFSET_32BIT or OFFSET_64BIT based on the size of an unsigned long) unless you have a very good reason to overrule this decision.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgubh:}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMqhjcubjt)}(h>struct drm_panthor_set_user_mmio_offset { __u64 offset; };h]h>struct drm_panthor_set_user_mmio_offset { __u64 offset; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMshjcubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMwhjcubj )}(hhh]j)}(hX0``offset`` User MMIO offset to use. Must be either DRM_PANTHOR_USER_MMIO_OFFSET_32BIT or DRM_PANTHOR_USER_MMIO_OFFSET_64BIT. Use DRM_PANTHOR_USER_MMIO_OFFSET (which selects OFFSET_32BIT or OFFSET_64BIT based on the size of an unsigned long) unless you have a very good reason to overrule this decision.h](j)}(h ``offset``h]j)}(hjh]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM}hjubj()}(hhh](h)}(hUser MMIO offset to use.h]hUser MMIO offset to use.}(hjͫhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMwhjʫubh)}(hXMust be either DRM_PANTHOR_USER_MMIO_OFFSET_32BIT or DRM_PANTHOR_USER_MMIO_OFFSET_64BIT.h]hXMust be either DRM_PANTHOR_USER_MMIO_OFFSET_32BIT or DRM_PANTHOR_USER_MMIO_OFFSET_64BIT.}(hjܫhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMyhjʫubh)}(hUse DRM_PANTHOR_USER_MMIO_OFFSET (which selects OFFSET_32BIT or OFFSET_64BIT based on the size of an unsigned long) unless you have a very good reason to overrule this decision.h]hUse DRM_PANTHOR_USER_MMIO_OFFSET (which selects OFFSET_32BIT or OFFSET_64BIT based on the size of an unsigned long) unless you have a very good reason to overrule this decision.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhM|hjʫubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjɫhM}hjubah}(h]h ]h"]h$]h&]uh1j hjcubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubh)}(hThis ioctl is only really useful if you want to support userspace CPU emulation environments where the size of an unsigned long differs between the host and the guest architectures.h]hThis ioctl is only really useful if you want to support userspace CPU emulation environments where the size of an unsigned long differs between the host and the guest architectures.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMnhj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_panthor_bo_sync_op_type (C enum)c.drm_panthor_bo_sync_op_typehNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_sync_op_typeh]j)}(h enum drm_panthor_bo_sync_op_typeh](j)}(hjSh]henum}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMuubj)}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhhj`hMuubj)}(hdrm_panthor_bo_sync_op_typeh]j)}(hjMh]hdrm_panthor_bo_sync_op_type}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ](j jeh"]h$]h&]jjuh1jhjOhhhj`hMuubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjKhhhj`hMuubah}(h]jFah ](j j!eh"]h$]h&]j%j&)j'huh1jhj`hMuhjHhhubj))}(hhh]h)}(h BO sync typeh]h BO sync type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjHhhhj`hMuubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(h**Constants** ``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH`` Flush CPU caches. ``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE`` Flush and invalidate CPU caches.h](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(h:``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH`` Flush CPU caches. h](j)}(h'``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH``h]j)}(hj֬h]h#DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH}(hjجhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjԬubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjЬubj()}(hhh]h)}(hFlush CPU caches.h]hFlush CPU caches.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjЬubeh}(h]h ]h"]h$]h&]uh1jhjhMhjͬubj)}(hW``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE`` Flush and invalidate CPU caches.h](j)}(h6``DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE``h]j)}(hjh]h2DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj ubj()}(hhh]h)}(h Flush and invalidate CPU caches.h]h Flush and invalidate CPU caches.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj%ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhjͬubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_panthor_bo_sync_op (C struct)c.drm_panthor_bo_sync_ophNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_sync_oph]j)}(hstruct drm_panthor_bo_sync_oph](j)}(hjh]hstruct}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjehhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjehhhjvhMubj)}(hdrm_panthor_bo_sync_oph]j)}(hjch]hdrm_panthor_bo_sync_op}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjehhhjvhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjahhhjvhMubah}(h]j\ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjvhMhj^hhubj))}(hhh]h)}(hBO map sync oph]hBO map sync op}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hj^hhhjvhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjíjLjíjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_bo_sync_op { __u32 handle; __u32 type; __u64 offset; __u64 size; }; **Members** ``handle`` Handle of the buffer object to sync. ``type`` Type of operation. ``offset`` Offset into the BO at which the sync range starts. This will be rounded down to the nearest cache line as needed. ``size`` Size of the range to sync **size** + **offset** will be rounded up to the nearest cache line as needed.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjϭhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj˭ubh:}(hj˭hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjǭubjt)}(hfstruct drm_panthor_bo_sync_op { __u32 handle; __u32 type; __u64 offset; __u64 size; };h]hfstruct drm_panthor_bo_sync_op { __u32 handle; __u32 type; __u64 offset; __u64 size; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjǭubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjǭubj )}(hhh](j)}(h0``handle`` Handle of the buffer object to sync. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h$Handle of the buffer object to sync.h]h$Handle of the buffer object to sync.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMhj.ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj-hMhjubj)}(h``type`` Type of operation. h](j)}(h``type``h]j)}(hjQh]htype}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjKubj()}(hhh]h)}(hType of operation.h]hType of operation.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMhjgubah}(h]h ]h"]h$]h&]uh1j'hjKubeh}(h]h ]h"]h$]h&]uh1jhjfhMhjubj)}(h~``offset`` Offset into the BO at which the sync range starts. This will be rounded down to the nearest cache line as needed. h](j)}(h ``offset``h]j)}(hjh]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(h2Offset into the BO at which the sync range starts.h]h2Offset into the BO at which the sync range starts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h>This will be rounded down to the nearest cache line as needed.h]h>This will be rounded down to the nearest cache line as needed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hq``size`` Size of the range to sync **size** + **offset** will be rounded up to the nearest cache line as needed.h](j)}(h``size``h]j)}(hjҮh]hsize}(hjԮhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjЮubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj̮ubj()}(hhh](h)}(hSize of the range to synch]hSize of the range to sync}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hM**size** + **offset** will be rounded up to the nearest cache line as needed.h](h)}(h**size**h]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh + }(hjhhhNhNubh)}(h **offset**h]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh8 will be rounded up to the nearest cache line as needed.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j'hj̮ubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjǭubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_panthor_bo_sync (C struct)c.drm_panthor_bo_synchNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_synch]j)}(hstruct drm_panthor_bo_synch](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVhhhjghMubj)}(hdrm_panthor_bo_synch]j)}(hjTh]hdrm_panthor_bo_sync}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ](j jeh"]h$]h&]jjuh1jhjVhhhjghMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjRhhhjghMubah}(h]jMah ](j j!eh"]h$]h&]j%j&)j'huh1jhjghMhjOhhubj))}(hhh]h)}(hBO map sync requesth]hBO map sync request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjOhhhjghMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(h**Definition**:: struct drm_panthor_bo_sync { struct drm_panthor_obj_array ops; }; **Members** ``ops`` Array of struct drm_panthor_bo_sync_op sync operations.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubjt)}(hEstruct drm_panthor_bo_sync { struct drm_panthor_obj_array ops; };h]hEstruct drm_panthor_bo_sync { struct drm_panthor_obj_array ops; };}hjٯsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh]j)}(h?``ops`` Array of struct drm_panthor_bo_sync_op sync operations.h](j)}(h``ops``h]j)}(hj h]hops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(h7Array of struct drm_panthor_bo_sync_op sync operations.h]h7Array of struct drm_panthor_bo_sync_op sync operations.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_panthor_bo_extra_flags (C enum)c.drm_panthor_bo_extra_flagshNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_extra_flagsh]j)}(henum drm_panthor_bo_extra_flagsh](j)}(hjSh]henum}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhhjphMubj)}(hdrm_panthor_bo_extra_flagsh]j)}(hj]h]hdrm_panthor_bo_extra_flags}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhj_hhhjphMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj[hhhjphMubah}(h]jVah ](j j!eh"]h$]h&]j%j&)j'huh1jhjphMhjXhhubj))}(hhh]h)}(h0Set of flags returned on a BO_QUERY_INFO requesth]h0Set of flags returned on a BO_QUERY_INFO request}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjXhhhjphMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Constants** ``DRM_PANTHOR_BO_IS_IMPORTED`` BO has been imported from an external driver. Note that imported dma-buf handles are not flagged as imported if they where exported by panthor. Only buffers that are coming from other drivers (dma heaps, other GPUs, display controllers, V4L, ...). It's also important to note that all imported BOs are mapped cached and can't be considered IO-coherent even if the GPU is. This means they require explicit syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache maintenance is not allowed in that case, because extra operations might be needed to make changes visible to the CPU/device, like buffer migration when the exporter is a GPU with its own VRAM).h](h)}(h **Constants**h]h)}(hjǰh]h Constants}(hjɰhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjŰubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh]j)}(hX``DRM_PANTHOR_BO_IS_IMPORTED`` BO has been imported from an external driver. Note that imported dma-buf handles are not flagged as imported if they where exported by panthor. Only buffers that are coming from other drivers (dma heaps, other GPUs, display controllers, V4L, ...). It's also important to note that all imported BOs are mapped cached and can't be considered IO-coherent even if the GPU is. This means they require explicit syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache maintenance is not allowed in that case, because extra operations might be needed to make changes visible to the CPU/device, like buffer migration when the exporter is a GPU with its own VRAM).h](j)}(h``DRM_PANTHOR_BO_IS_IMPORTED``h]j)}(hjh]hDRM_PANTHOR_BO_IS_IMPORTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(h-BO has been imported from an external driver.h]h-BO has been imported from an external driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hNote that imported dma-buf handles are not flagged as imported if they where exported by panthor. Only buffers that are coming from other drivers (dma heaps, other GPUs, display controllers, V4L, ...).h]hNote that imported dma-buf handles are not flagged as imported if they where exported by panthor. Only buffers that are coming from other drivers (dma heaps, other GPUs, display controllers, V4L, ...).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hXIt's also important to note that all imported BOs are mapped cached and can't be considered IO-coherent even if the GPU is. This means they require explicit syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache maintenance is not allowed in that case, because extra operations might be needed to make changes visible to the CPU/device, like buffer migration when the exporter is a GPU with its own VRAM).h]hXIt’s also important to note that all imported BOs are mapped cached and can’t be considered IO-coherent even if the GPU is. This means they require explicit syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache maintenance is not allowed in that case, because extra operations might be needed to make changes visible to the CPU/device, like buffer migration when the exporter is a GPU with its own VRAM).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjݰubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubh)}(h**Description**h]h)}(hjGh]h Description}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubh)}(hThose are flags reflecting BO properties that are not directly coming from the flags passed are creation time, or information on BOs that were imported from other drivers.h]hThose are flags reflecting BO properties that are not directly coming from the flags passed are creation time, or information on BOs that were imported from other drivers.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_panthor_bo_query_info (C struct)c.drm_panthor_bo_query_infohNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hdrm_panthor_bo_query_infoh]j)}(h struct drm_panthor_bo_query_infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_panthor_bo_query_infoh]j)}(hjh]hdrm_panthor_bo_query_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj}hhhjhMubah}(h]jxah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjzhhubj))}(hhh]h)}(h Query BO infoh]h Query BO info}(hjDZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjıhhubah}(h]h ]h"]h$]h&]uh1j(hjzhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj߱jLj߱jMjNjOuh1jhhhj'fhNhNubjQ)}(hX**Definition**:: struct drm_panthor_bo_query_info { __u32 handle; __u32 extra_flags; __u32 create_flags; __u32 pad; }; **Members** ``handle`` Handle of the buffer object to query flags on. ``extra_flags`` Combination of enum drm_panthor_bo_extra_flags flags. ``create_flags`` Flags passed at creation time. Combination of enum drm_panthor_bo_flags flags. Will be zero if the buffer comes from a different driver. ``pad`` Will be zero on return.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubjt)}(hustruct drm_panthor_bo_query_info { __u32 handle; __u32 extra_flags; __u32 create_flags; __u32 pad; };h]hustruct drm_panthor_bo_query_info { __u32 handle; __u32 extra_flags; __u32 create_flags; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(h:``handle`` Handle of the buffer object to query flags on. h](j)}(h ``handle``h]j)}(hj4h]hhandle}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj.ubj()}(hhh]h)}(h.Handle of the buffer object to query flags on.h]h.Handle of the buffer object to query flags on.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMhjJubah}(h]h ]h"]h$]h&]uh1j'hj.ubeh}(h]h ]h"]h$]h&]uh1jhjIhMhj+ubj)}(hF``extra_flags`` Combination of enum drm_panthor_bo_extra_flags flags. h](j)}(h``extra_flags``h]j)}(hjmh]h extra_flags}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjgubj()}(hhh]h)}(h5Combination of enum drm_panthor_bo_extra_flags flags.h]h5Combination of enum drm_panthor_bo_extra_flags flags.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjgubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(h``create_flags`` Flags passed at creation time. Combination of enum drm_panthor_bo_flags flags. Will be zero if the buffer comes from a different driver. h](j)}(h``create_flags``h]j)}(hjh]h create_flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh](h)}(hFlags passed at creation time.h]hFlags passed at creation time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hiCombination of enum drm_panthor_bo_flags flags. Will be zero if the buffer comes from a different driver.h]hiCombination of enum drm_panthor_bo_flags flags. Will be zero if the buffer comes from a different driver.}(hjβhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(h``pad`` Will be zero on return.h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(hWill be zero on return.h]hWill be zero on return.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jDRM_IOCTL_PANTHOR (C macro)c.DRM_IOCTL_PANTHORhNtauh1jhj'fhhhNhNubj)}(hhh](j)}(hDRM_IOCTL_PANTHORh]j)}(hDRM_IOCTL_PANTHORh]j)}(hDRM_IOCTL_PANTHORh]j)}(hjCh]hDRM_IOCTL_PANTHOR}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubah}(h]h ](j jeh"]h$]h&]jjuh1jhjEhhh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMubah}(h]h ]h"]h$]h&]jjjuh1jjjhjAhhhj`hMubah}(h]j<ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj`hMhj>hhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hj>hhhj`hMubeh}(h]h ](jEmacroeh"]h$]h&]jJjEjKjyjLjyjMjNjOuh1jhhhj'fhNhNubh)}(h.``DRM_IOCTL_PANTHOR (__access, __id, __type)``h]j)}(hjh]h*DRM_IOCTL_PANTHOR (__access, __id, __type)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj'fhhubj)}(hBuild a Panthor IOCTL number h]h)}(hBuild a Panthor IOCTL numberh]hBuild a Panthor IOCTL number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjhMhj'fhhubjQ)}(hXJ**Parameters** ``__access`` Access type. Must be R, W or RW. ``__id`` One of the DRM_PANTHOR_xxx id. ``__type`` Suffix of the type being passed to the IOCTL. **Description** Don't use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead. **Return** An IOCTL number to be passed to ioctl() from userspace.h](h)}(h**Parameters**h]h)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj )}(hhh](j)}(h.``__access`` Access type. Must be R, W or RW. h](j)}(h ``__access``h]j)}(hjӳh]h__access}(hjճhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjѳubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjͳubj()}(hhh]h)}(h Access type. Must be R, W or RW.h]h Access type. Must be R, W or RW.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjͳubeh}(h]h ]h"]h$]h&]uh1jhjhMhjʳubj)}(h(``__id`` One of the DRM_PANTHOR_xxx id. h](j)}(h``__id``h]j)}(hj h]h__id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubj()}(hhh]h)}(hOne of the DRM_PANTHOR_xxx id.h]hOne of the DRM_PANTHOR_xxx id.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMhj"ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj!hMhjʳubj)}(h9``__type`` Suffix of the type being passed to the IOCTL. h](j)}(h ``__type``h]j)}(hjEh]h__type}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhj?ubj()}(hhh]h)}(h-Suffix of the type being passed to the IOCTL.h]h-Suffix of the type being passed to the IOCTL.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhMhj[ubah}(h]h ]h"]h$]h&]uh1j'hj?ubeh}(h]h ]h"]h$]h&]uh1jhjZhMhjʳubeh}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~ubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(hLDon't use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead.h]hNDon’t use this macro directly, use the DRM_IOCTL_PANTHOR_xxx values instead.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h **Return**h]h)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubh)}(h7An IOCTL number to be passed to ioctl() from userspace.h]h7An IOCTL number to be passed to ioctl() from userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh^/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:24: ./include/uapi/drm/panthor_drm.hhMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj'fhhhNhNubeh}(h]drm-panthor-uapiah ]h"]drm/panthor uapiah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h drm/xe uAPIh]h drm/xe uAPI}(hj޴hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj۴hhhhhKubh)}(h.. _Xe Device Block Diagram:h]h}(h]h ]h"]h$]h&]hxe-device-block-diagramuh1hhKhj۴hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hubh)}(h**Xe Device Block Diagram**h]h)}(hjh]hXe Device Block Diagram}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]jah ]h"]xe device block diagramah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhj}j jsj }jjsubh)}(hXThe diagram below represents a high-level simplification of a discrete GPU supported by the Xe driver. It shows some device components which are necessary to understand this API, as well as how their relations to each other. This diagram does not represent real hardware::h]hXThe diagram below represents a high-level simplification of a discrete GPU supported by the Xe driver. It shows some device components which are necessary to understand this API, as well as how their relations to each other. This diagram does not represent real hardware:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubjt)}(hX┌──────────────────────────────────────────────────────────────────┐ │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ └─────────────────────────────Device0───────┬──────────────────────┘ │ ───────────────────────┴────────── PCI bush]hX┌──────────────────────────────────────────────────────────────────┐ │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ └─────────────────────────────Device0───────┬──────────────────────┘ │ ───────────────────────┴────────── PCI bus}hj"sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubh)}(h.. _Xe uAPI Overview:h]h}(h]h ]h"]h$]h&]hxe-uapi-overviewuh1hhK)hj۴hhhjubh)}(h**Xe uAPI Overview**h]h)}(hj>h]hXe uAPI Overview}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubah}(h]j;ah ]h"]xe uapi overviewah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhK@hj۴hhj}jQj1sj }j;j1subh)}(hThis section aims to describe the Xe's IOCTL entries, its structs, and other Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related entries and usage.h]hThis section aims to describe the Xe’s IOCTL entries, its structs, and other Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related entries and usage.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKAhj۴hhubj )}(hhh]j)}(hXfList of supported IOCTLs: - :c:type:`DRM_IOCTL_XE_DEVICE_QUERY` - :c:type:`DRM_IOCTL_XE_GEM_CREATE` - :c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET` - :c:type:`DRM_IOCTL_XE_VM_CREATE` - :c:type:`DRM_IOCTL_XE_VM_DESTROY` - :c:type:`DRM_IOCTL_XE_VM_BIND` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY` - :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY` - :c:type:`DRM_IOCTL_XE_EXEC` - :c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE` - :c:type:`DRM_IOCTL_XE_OBSERVATION` - :c:type:`DRM_IOCTL_XE_MADVISE` - :c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS` - :c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY` h](j)}(hList of supported IOCTLs:h]hList of supported IOCTLs:}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKUhjiubj()}(hhh]j )}(hhh](j )}(h#:c:type:`DRM_IOCTL_XE_DEVICE_QUERY`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_DEVICE_QUERY}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_DEVICE_QUERYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKFhjubah}(h]h ]h"]h$]h&]uh1hhjhKFhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_GEM_CREATE}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_GEM_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKGhjubah}(h]h ]h"]h$]h&]uh1hhjٵhKGhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h&:c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_GEM_MMAP_OFFSET}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_GEM_MMAP_OFFSETuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKHhjubah}(h]h ]h"]h$]h&]uh1hhj hKHhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h :c:type:`DRM_IOCTL_XE_VM_CREATE`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_VM_CREATE}(hj"hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_VM_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKIhjubah}(h]h ]h"]h$]h&]uh1hhj=hKIhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h!:c:type:`DRM_IOCTL_XE_VM_DESTROY`h]h)}(hjLh]h)}(hjLh]j)}(hjLh]hDRM_IOCTL_XE_VM_DESTROY}(hjThhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_VM_DESTROYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKJhjNubah}(h]h ]h"]h$]h&]uh1hhjohKJhjJubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]h)}(hj~h]h)}(hj~h]j)}(hj~h]hDRM_IOCTL_XE_VM_BIND}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_VM_BINDuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKKhjubah}(h]h ]h"]h$]h&]uh1hhjhKKhj|ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h(:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_EXEC_QUEUE_CREATE}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_EXEC_QUEUE_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKLhjubah}(h]h ]h"]h$]h&]uh1hhjӶhKLhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h):c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_EXEC_QUEUE_DESTROY}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_EXEC_QUEUE_DESTROYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKMhjubah}(h]h ]h"]h$]h&]uh1hhjhKMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h.:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY`h]h)}(hjh]h)}(hjh]j)}(hjh]h$DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) $DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKNhjubah}(h]h ]h"]h$]h&]uh1hhj7hKNhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h:c:type:`DRM_IOCTL_XE_EXEC`h]h)}(hjFh]h)}(hjFh]j)}(hjFh]hDRM_IOCTL_XE_EXEC}(hjNhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_EXECuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKOhjHubah}(h]h ]h"]h$]h&]uh1hhjihKOhjDubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h&:c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE`h]h)}(hjxh]h)}(hjxh]j)}(hjxh]hDRM_IOCTL_XE_WAIT_USER_FENCE}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_WAIT_USER_FENCEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKPhjzubah}(h]h ]h"]h$]h&]uh1hhjhKPhjvubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h":c:type:`DRM_IOCTL_XE_OBSERVATION`h]h)}(hjh]h)}(hjh]j)}(hjh]hDRM_IOCTL_XE_OBSERVATION}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_OBSERVATIONuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKQhjubah}(h]h ]h"]h$]h&]uh1hhjͷhKQhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h:c:type:`DRM_IOCTL_XE_MADVISE`h]h)}(hjܷh]h)}(hjܷh]j)}(hjܷh]hDRM_IOCTL_XE_MADVISE}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_MADVISEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKRhj޷ubah}(h]h ]h"]h$]h&]uh1hhjhKRhjڷubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h/:c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS`h]h)}(hjh]h)}(hjh]j)}(hjh]h%DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) %DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRSuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKShjubah}(h]h ]h"]h$]h&]uh1hhj1hKShj ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h(:c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY` h]h)}(h&:c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY`h]h)}(hjDh]j)}(hjDh]hDRM_IOCTL_XE_VM_GET_PROPERTY}(hjIhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_VM_GET_PROPERTYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKThjBubah}(h]h ]h"]h$]h&]uh1hhjdhKThj>ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhKFhj|ubah}(h]h ]h"]h$]h&]uh1j'hjiubeh}(h]h ]h"]h$]h&]uh1jhj{hKUhjfubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubh)}(h.. _Xe IOCTL Extensions:h]h}(h]h ]h"]h$]h&]hxe-ioctl-extensionsuh1hhKChj۴hhhjubh)}(h**Xe IOCTL Extensions**h]h)}(hjh]hXe IOCTL Extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]jah ]h"]xe ioctl extensionsah$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKYhj۴hhj}jjsj }jjsubh)}(hoBefore detailing the IOCTLs and its structs, it is important to highlight that every IOCTL in Xe is extensible.h]hoBefore detailing the IOCTLs and its structs, it is important to highlight that every IOCTL in Xe is extensible.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubh)}(hX5Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan's approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.h]hX7Many interfaces need to grow over time. In most cases we can simply extend the struct and have userspace pass in more data. Another option, as demonstrated by Vulkan’s approach to providing extensions for forward and backward compatibility, is to use a list of optional structs to provide those extra details.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubh)}(hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.h]hXMThe key advantage to using an extension chain is that it allows us to redefine the interface more easily than an ever growing struct of increasing complexity, and for large parts of that interface to be entirely optional. The downside is more pointer chasing; chasing across the __user boundary with pointers encapsulated inside u64.}(hj͸hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubh)}(hExample chaining:h]hExample chaining:}(hjܸhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubjt)}(hX/struct drm_xe_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct drm_xe_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct drm_xe_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };h]hX/struct drm_xe_user_extension ext3 { .next_extension = 0, // end .name = ..., }; struct drm_xe_user_extension ext2 { .next_extension = (uintptr_t)&ext3, .name = ..., }; struct drm_xe_user_extension ext1 { .next_extension = (uintptr_t)&ext2, .name = ..., };}hjsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubh)}(hTypically the struct drm_xe_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.h]hTypically the struct drm_xe_user_extension would be embedded in some uAPI struct, and in this case we would feed it the head of the chain(i.e ext1), which would then apply all of the above extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_user_extension (C struct)c.drm_xe_user_extensionhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_user_extensionh]j)}(hstruct drm_xe_user_extensionh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj0hKubj)}(hdrm_xe_user_extensionh]j)}(hjh]hdrm_xe_user_extension}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhj0hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj0hKubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj0hKhjhhubj))}(hhh]h)}(h-Base class for defining a chain of extensionsh]h-Base class for defining a chain of extensions}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjbhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj0hKubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj}jLj}jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX3**Definition**:: struct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; }; **Members** ``next_extension`` Pointer to the next struct drm_xe_user_extension, or zero if the end. ``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension. ``pad`` MBZ All undefined bits must be zero.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubjt)}(hZstruct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; };h]hZstruct drm_xe_user_extension { __u64 next_extension; __u32 name; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj )}(hhh](j)}(hY``next_extension`` Pointer to the next struct drm_xe_user_extension, or zero if the end. h](j)}(h``next_extension``h]j)}(hjҹh]hnext_extension}(hjԹhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjйubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj̹ubj()}(hhh]h)}(hEPointer to the next struct drm_xe_user_extension, or zero if the end.h]hEPointer to the next struct drm_xe_user_extension, or zero if the end.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j'hj̹ubeh}(h]h ]h"]h$]h&]uh1jhjhKhjɹubj)}(hX``name`` Name of the extension. Note that the name here is just some integer. Also note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension. h](j)}(h``name``h]j)}(hj h]hname}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj()}(hhh](h)}(hName of the extension.h]hName of the extension.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj!ubh)}(h-Note that the name here is just some integer.h]h-Note that the name here is just some integer.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj!ubh)}(hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension.h]hAlso note that the name space for this is not global for the whole driver, but rather its scope/meaning is limited to the specific piece of uAPI which has embedded the struct drm_xe_user_extension.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj!ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjɹubj)}(h-``pad`` MBZ All undefined bits must be zero.h](j)}(h``pad``h]j)}(hjch]hpad}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj]ubj()}(hhh](h)}(hMBZh]hMBZ}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjyubh)}(h All undefined bits must be zero.h]h All undefined bits must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: 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./include/uapi/drm/xe_drm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjٺhKubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj&jLj&jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; union { __u64 value; __u64 ptr; }; __u64 reserved[2]; }; **Members** ``base`` base user extension ``property`` property to set ``pad`` MBZ ``{unnamed_union}`` anonymous ``value`` property value ``ptr`` pointer to user value ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.ubh:}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj*ubjt)}(hstruct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; union { __u64 value; __u64 ptr; }; __u64 reserved[2]; };h]hstruct drm_xe_ext_set_property { struct drm_xe_user_extension base; __u32 property; __u32 pad; union { __u64 value; __u64 ptr; }; __u64 reserved[2]; };}hjKsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj*ubh)}(h **Members**h]h)}(hj\h]hMembers}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj*ubj )}(hhh](j)}(h``base`` base user extension h](j)}(h``base``h]j)}(hj{h]hbase}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjuubj()}(hhh]h)}(hbase user extensionh]hbase user extension}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j'hjuubeh}(h]h ]h"]h$]h&]uh1jhjhKhjrubj)}(h``property`` property to set h](j)}(h ``property``h]j)}(hjh]hproperty}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj()}(hhh]h)}(hproperty to seth]hproperty to set}(hjͻhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjɻhKhjʻubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjɻhKhjrubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjrubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hj&h]h{unnamed_union}}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubj()}(hhh]h)}(h anonymoush]h anonymous}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hKhj<ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj;hKhjrubj)}(h``value`` property value h](j)}(h ``value``h]j)}(hj_h]hvalue}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjYubj()}(hhh]h)}(hproperty valueh]hproperty value}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthKhjuubah}(h]h ]h"]h$]h&]uh1j'hjYubeh}(h]h ]h"]h$]h&]uh1jhjthKhjrubj)}(h``ptr`` pointer to user value h](j)}(h``ptr``h]j)}(hjh]hptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj()}(hhh]h)}(hpointer to user valueh]hpointer to user value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjrubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjѼh]hreserved}(hjӼhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϼubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj˼ubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1j'hj˼ubeh}(h]h ]h"]h$]h&]uh1jhjhKhjrubeh}(h]h ]h"]h$]h&]uh1j hj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubh)}(h`A generic struct that allows any of the Xe's IOCTL to be extended with a set_property operation.h]hbA generic struct that allows any of the Xe’s IOCTL to be extended with a set_property operation.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'drm_xe_engine_class_instance (C struct)c.drm_xe_engine_class_instancehNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_engine_class_instanceh]j)}(h#struct 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DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; }; **Members** ``engine_class`` engine class id ``engine_instance`` engine instance id ``gt_id`` Unique ID of this GT within the PCI Device ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubjt)}(hXstruct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0; #define DRM_XE_ENGINE_CLASS_COPY 1; #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2; #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; };h]hXstruct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0; #define DRM_XE_ENGINE_CLASS_COPY 1; #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2; #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3; #define DRM_XE_ENGINE_CLASS_COMPUTE 4; #define DRM_XE_ENGINE_CLASS_VM_BIND 5; __u16 engine_class; __u16 engine_instance; __u16 gt_id; __u16 pad; };}hjѽsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj )}(hhh](j)}(h!``engine_class`` engine class id h](j)}(h``engine_class``h]j)}(hjh]h engine_class}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj()}(hhh]h)}(hengine class idh]hengine class id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h'``engine_instance`` engine instance id h](j)}(h``engine_instance``h]j)}(hj:h]hengine_instance}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj4ubj()}(hhh]h)}(hengine instance idh]hengine instance id}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhMhjPubah}(h]h ]h"]h$]h&]uh1j'hj4ubeh}(h]h ]h"]h$]h&]uh1jhjOhMhjubj)}(h5``gt_id`` Unique ID of this GT within the PCI Device h](j)}(h ``gt_id``h]j)}(hjsh]hgt_id}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjmubj()}(hhh]h)}(h*Unique ID of this GT within the PCI Deviceh]h*Unique ID of this GT within the PCI Device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjmubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hjžhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj¾ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hIt is returned as part of the **drm_xe_engine**, but it also is used as the input of engine selection for both **drm_xe_exec_queue_create** and **drm_xe_query_engine_cycles**h](hIt is returned as part of the }(hjhhhNhNubh)}(h**drm_xe_engine**h]h drm_xe_engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh@, but it also is used as the input of engine selection for both }(hjhhhNhNubh)}(h**drm_xe_exec_queue_create**h]hdrm_xe_exec_queue_create}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh and }(hjhhhNhNubh)}(h**drm_xe_query_engine_cycles**h]hdrm_xe_query_engine_cycles}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj۴hhubj )}(hhh]j)}(hXiThe **engine_class** can be: - ``DRM_XE_ENGINE_CLASS_RENDER`` - ``DRM_XE_ENGINE_CLASS_COPY`` - ``DRM_XE_ENGINE_CLASS_VIDEO_DECODE`` - ``DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE`` - ``DRM_XE_ENGINE_CLASS_COMPUTE`` - ``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations. h](j)}(hThe **engine_class** can be:h](hThe }(hjMhhhNhNubh)}(h**engine_class**h]h engine_class}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMubh can be:}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjIubj()}(hhh]j )}(hhh](j )}(h``DRM_XE_ENGINE_CLASS_RENDER``h]h)}(hjvh]j)}(hjvh]hDRM_XE_ENGINE_CLASS_RENDER}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjtubah}(h]h ]h"]h$]h&]uh1j hjqubj )}(h``DRM_XE_ENGINE_CLASS_COPY``h]h)}(hjh]j)}(hjh]hDRM_XE_ENGINE_CLASS_COPY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjqubj )}(h$``DRM_XE_ENGINE_CLASS_VIDEO_DECODE``h]h)}(hjh]j)}(hjh]h DRM_XE_ENGINE_CLASS_VIDEO_DECODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjqubj )}(h%``DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE``h]h)}(hjٿh]j)}(hjٿh]h!DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE}(hj޿hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjۿubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj׿ubah}(h]h ]h"]h$]h&]uh1j hjqubj )}(h``DRM_XE_ENGINE_CLASS_COMPUTE``h]h)}(hjh]j)}(hjh]hDRM_XE_ENGINE_CLASS_COMPUTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjqubj )}(h``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations. h]h)}(h``DRM_XE_ENGINE_CLASS_VM_BIND`` - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations.h](j)}(h``DRM_XE_ENGINE_CLASS_VM_BIND``h]hDRM_XE_ENGINE_CLASS_VM_BIND}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhr - Kernel only classes (not actual hardware engine class). Used for creating ordered queues of VM bind operations.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjqubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhKhjnubah}(h]h ]h"]h$]h&]uh1j'hjIubeh}(h]h ]h"]h$]h&]uh1jhjmhKhjFubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_engine (C struct)c.drm_xe_enginehNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(h drm_xe_engineh]j)}(hstruct drm_xe_engineh](j)}(hjh]hstruct}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhhj~hKubj)}(h drm_xe_engineh]j)}(hjkh]h drm_xe_engine}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjmhhhj~hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjihhhj~hKubah}(h]jdah ](j j!eh"]h$]h&]j%j&)j'huh1jhj~hKhjfhhubj))}(hhh]h)}(hdescribe hardware engineh]hdescribe hardware engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjfhhhj~hKubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(h**Definition**:: struct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; }; **Members** ``instance`` The **drm_xe_engine_class_instance** ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubjt)}(hbstruct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; };h]hbstruct drm_xe_engine { struct drm_xe_engine_class_instance instance; __u64 reserved[3]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h2``instance`` The **drm_xe_engine_class_instance** h](j)}(h ``instance``h]j)}(hj h]hinstance}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubj()}(hhh]h)}(h$The **drm_xe_engine_class_instance**h](hThe }(hj9hhhNhNubh)}(h **drm_xe_engine_class_instance**h]hdrm_xe_engine_class_instance}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9ubeh}(h]h ]h"]h$]h&]uh1hhj5hM hj6ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj5hM hjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjgh]hreserved}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjaubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj}ubah}(h]h ]h"]h$]h&]uh1j'hjaubeh}(h]h ]h"]h$]h&]uh1jhj|hMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_query_engines (C struct)c.drm_xe_query_engineshNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_enginesh]j)}(hstruct drm_xe_query_enginesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_query_enginesh]j)}(hjh]hdrm_xe_query_engines}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(hdescribe enginesh]hdescribe engines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; }; **Members** ``num_engines`` number of engines returned in **engines** ``pad`` MBZ ``engines`` The returned engines for this deviceh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#ubh:}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hjstruct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; };h]hjstruct drm_xe_query_engines { __u32 num_engines; __u32 pad; struct drm_xe_engine engines[]; };}hj@sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjQh]hMembers}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h:``num_engines`` number of engines returned in **engines** h](j)}(h``num_engines``h]j)}(hjph]h num_engines}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjjubj()}(hhh]h)}(h)number of engines returned in **engines**h](hnumber of engines returned in }(hjhhhNhNubh)}(h **engines**h]hengines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjgubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjgubj)}(h0``engines`` The returned engines for this deviceh](j)}(h ``engines``h]j)}(hjh]hengines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h$The returned engines for this deviceh]h$The returned engines for this device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjgubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj3h]h Description}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM"hj۴hhubh)}(hIf a query is made with a struct **drm_xe_device_query** where .query is equal to ``DRM_XE_DEVICE_QUERY_ENGINES``, then the reply uses an array of struct **drm_xe_query_engines** in .data.h](h!If a query is made with a struct }(hjIhhhNhNubh)}(h**drm_xe_device_query**h]hdrm_xe_device_query}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubh where .query is equal to }(hjIhhhNhNubj)}(h``DRM_XE_DEVICE_QUERY_ENGINES``h]hDRM_XE_DEVICE_QUERY_ENGINES}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubh), then the reply uses an array of struct }(hjIhhhNhNubh)}(h**drm_xe_query_engines**h]hdrm_xe_query_engines}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubh in .data.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_memory_class (C enum)c.drm_xe_memory_classhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_memory_classh]j)}(henum drm_xe_memory_classh](j)}(hjSh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_memory_classh]j)}(hjh]hdrm_xe_memory_class}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(hSupported memory classes.h]hSupported memory classes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM#hjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(h**Constants** ``DRM_XE_MEM_REGION_CLASS_SYSMEM`` Represents system memory. ``DRM_XE_MEM_REGION_CLASS_VRAM`` On discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h](h)}(h **Constants**h]h)}(hj h]h Constants}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM'hjubj )}(hhh](j)}(h=``DRM_XE_MEM_REGION_CLASS_SYSMEM`` Represents system memory. h](j)}(h"``DRM_XE_MEM_REGION_CLASS_SYSMEM``h]j)}(hj*h]hDRM_XE_MEM_REGION_CLASS_SYSMEM}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM*hj$ubj()}(hhh]h)}(hRepresents system memory.h]hRepresents system memory.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hM*hj@ubah}(h]h ]h"]h$]h&]uh1j'hj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hM*hj!ubj)}(h``DRM_XE_MEM_REGION_CLASS_VRAM`` On discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h](j)}(h ``DRM_XE_MEM_REGION_CLASS_VRAM``h]j)}(hjch]hDRM_XE_MEM_REGION_CLASS_VRAM}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM.hj]ubj()}(hhh]h)}(hOn discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.h]hOn discrete platforms, this represents the memory that is local to the device, which we call VRAM. Not valid on integrated platforms.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM-hjyubah}(h]h ]h"]h$]h&]uh1j'hj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhM.hj!ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_mem_region (C struct)c.drm_xe_mem_regionhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_mem_regionh]j)}(hstruct drm_xe_mem_regionh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM4ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM4ubj)}(hdrm_xe_mem_regionh]j)}(hjh]hdrm_xe_mem_region}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhM4ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM4ubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM4hjhhubj))}(hhh]h)}(h-Describes some region as known to the driver.h]h-Describes some region as known to the driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM1hjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhM4ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; }; **Members** ``mem_class`` The memory class describing this region. See enum drm_xe_memory_class for supported values. ``instance`` The unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE` ``min_page_size`` Min page-size in bytes for this region. When the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met. ``total_size`` The usable size in bytes for this region. ``used`` Estimate of the memory used in bytes for this region. ``cpu_visible_size`` How much of this region can be CPU accessed, in bytes. This will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system. On systems without small BAR (full BAR), the probed_size will always equal the **total_size**, since all of it will be CPU accessible. Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero). ``cpu_visible_used`` Estimate of CPU visible memory used, in bytes. Note this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero). ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM5hjubjt)}(hstruct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; };h]hstruct drm_xe_mem_region { __u16 mem_class; __u16 instance; __u32 min_page_size; __u64 total_size; __u64 used; __u64 cpu_visible_size; __u64 cpu_visible_used; __u64 reserved[6]; };}hj<sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM7hjubh)}(h **Members**h]h)}(hjMh]hMembers}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMBhjubj )}(hhh](j)}(hk``mem_class`` The memory class describing this region. See enum drm_xe_memory_class for supported values. h](j)}(h ``mem_class``h]j)}(hjlh]h mem_class}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM9hjfubj()}(hhh](h)}(h(The memory class describing this region.h]h(The memory class describing this region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM7hjubh)}(h2See enum drm_xe_memory_class for supported values.h]h2See enum drm_xe_memory_class for supported values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM9hjubeh}(h]h ]h"]h$]h&]uh1j'hjfubeh}(h]h ]h"]h$]h&]uh1jhjhM9hjcubj)}(h``instance`` The unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE` h](j)}(h ``instance``h]j)}(hjh]hinstance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM?hjubj()}(hhh]h)}(hThe unique ID for this region, which serves as the index in the placement bitmask used as argument for :c:type:`DRM_IOCTL_XE_GEM_CREATE`h](hgThe unique ID for this region, which serves as the index in the placement bitmask used as argument for }(hjhhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]j)}(hjh]hDRM_IOCTL_XE_GEM_CREATE}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_GEM_CREATEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=hjubeh}(h]h ]h"]h$]h&]uh1hhjhM=hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM?hjcubj)}(hX``min_page_size`` Min page-size in bytes for this region. When the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met. h](j)}(h``min_page_size``h]j)}(hj h]h min_page_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMMhjubj()}(hhh](h)}(h'Min page-size in bytes for this region.h]h'Min page-size in bytes for this region.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMChj#ubh)}(hXWhen the kernel allocates memory for this region, the underlying pages will be at least **min_page_size** in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return ``-EINVAL`` if alignment restrictions are not met.h](hXWhen the kernel allocates memory for this region, the underlying pages will be at least }(hj5hhhNhNubh)}(h**min_page_size**h]h min_page_size}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5ubhX9 in size. Buffer objects with an allowable placement in this region must be created with a size aligned to this value. GPU virtual address mappings of (parts of) buffer objects that may be placed in this region must also have their GPU virtual address and range aligned to this value. Affected IOCTLS will return }(hj5hhhNhNubj)}(h ``-EINVAL``h]h-EINVAL}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh' if alignment restrictions are not met.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMEhj#ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj"hMMhjcubj)}(h9``total_size`` The usable size in bytes for this region. h](j)}(h``total_size``h]j)}(hjzh]h total_size}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMQhjtubj()}(hhh]h)}(h)The usable size in bytes for this region.h]h)The usable size in bytes for this region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMQhjubah}(h]h ]h"]h$]h&]uh1j'hjtubeh}(h]h ]h"]h$]h&]uh1jhjhMQhjcubj)}(h?``used`` Estimate of the memory used in bytes for this region. h](j)}(h``used``h]j)}(hjh]hused}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMUhjubj()}(hhh]h)}(h5Estimate of the memory used in bytes for this region.h]h5Estimate of the memory used in bytes for this region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMUhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMUhjcubj)}(hX``cpu_visible_size`` How much of this region can be CPU accessed, in bytes. This will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system. On systems without small BAR (full BAR), the probed_size will always equal the **total_size**, since all of it will be CPU accessible. Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero). h](j)}(h``cpu_visible_size``h]j)}(hjh]hcpu_visible_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMghjubj()}(hhh](h)}(h6How much of this region can be CPU accessed, in bytes.h]h6How much of this region can be CPU accessed, in bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMYhjubh)}(hThis will always be <= **total_size**, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than **total_size** then this is referred to as a small BAR system.h](hThis will always be <= }(hjhhhNhNubh)}(h**total_size**h]h total_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhd, and the remainder (if any) will not be CPU accessible. If the CPU accessible part is smaller than }(hjhhhNhNubh)}(h**total_size**h]h total_size}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh0 then this is referred to as a small BAR system.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM\hjubh)}(hOn systems without small BAR (full BAR), the probed_size will always equal the **total_size**, since all of it will be CPU accessible.h](hOOn systems without small BAR (full BAR), the probed_size will always equal the }(hjGhhhNhNubh)}(h**total_size**h]h total_size}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh), since all of it will be CPU accessible.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMahjubh)}(h{Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero).h]h{Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always equal zero).}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMehjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMghjcubj)}(h``cpu_visible_used`` Estimate of CPU visible memory used, in bytes. Note this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero). h](j)}(h``cpu_visible_used``h]j)}(hjh]hcpu_visible_used}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMphjubj()}(hhh](h)}(h.Estimate of CPU visible memory used, in bytes.h]h.Estimate of CPU visible memory used, in bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMkhjubh)}(hNote this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero).h]hNote this is only currently tracked for DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value here will always be zero).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMnhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMphjcubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMrhjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMshjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMrhjcubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_xe_query_mem_regions (C struct)c.drm_xe_query_mem_regionshNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_mem_regionsh]j)}(hstruct drm_xe_query_mem_regionsh](j)}(hjh]hstruct}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMyubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(hhhj9hMyubj)}(hdrm_xe_query_mem_regionsh]j)}(hj&h]hdrm_xe_query_mem_regions}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubah}(h]h ](j jeh"]h$]h&]jjuh1jhj(hhhj9hMyubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj$hhhj9hMyubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj9hMyhj!hhubj))}(hhh]h)}(hdescribe memory regionsh]hdescribe memory regions}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMwhjkhhubah}(h]h ]h"]h$]h&]uh1j(hj!hhhj9hMyubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX=**Definition**:: struct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; }; **Members** ``num_mem_regions`` number of memory regions returned in **mem_regions** ``pad`` MBZ ``mem_regions`` The returned memory regions for this deviceh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM{hjubjt)}(hzstruct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; };h]hzstruct drm_xe_query_mem_regions { __u32 num_mem_regions; __u32 pad; struct drm_xe_mem_region mem_regions[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM}hjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(hI``num_mem_regions`` number of memory regions returned in **mem_regions** h](j)}(h``num_mem_regions``h]j)}(hjh]hnum_mem_regions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h4number of memory regions returned in **mem_regions**h](h%number of memory regions returned in }(hjhhhNhNubh)}(h**mem_regions**h]h mem_regions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj"h]hpad}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj8ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj7hMhjubj)}(h;``mem_regions`` The returned memory regions for this deviceh](j)}(h``mem_regions``h]j)}(hj[h]h mem_regions}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjUubj()}(hhh]h)}(h+The returned memory regions for this deviceh]h+The returned memory regions for this device}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjqubah}(h]h ]h"]h$]h&]uh1j'hjUubeh}(h]h ]h"]h$]h&]uh1jhjphMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses struct drm_xe_query_mem_regions in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses struct drm_xe_query_mem_regions in .data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMxhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_query_config (C struct)c.drm_xe_query_confighNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_configh]j)}(hstruct drm_xe_query_configh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_query_configh]j)}(hjh]hdrm_xe_query_config}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h!describe the device configurationh]h!describe the device configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj6jLj6jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; }; **Members** ``num_params`` number of parameters returned in info ``pad`` MBZ ``info`` array of elements containing the config infoh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>ubh:}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj:ubjt)}(hX struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; };h]hX struct drm_xe_query_config { __u32 num_params; __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0; #define DRM_XE_QUERY_CONFIG_FLAGS 1; #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4); #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5); #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2; #define DRM_XE_QUERY_CONFIG_VA_BITS 3; #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4; __u64 info[]; };}hj[sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj:ubh)}(h **Members**h]h)}(hjlh]hMembers}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj:ubj )}(hhh](j)}(h5``num_params`` number of parameters returned in info h](j)}(h``num_params``h]j)}(hjh]h num_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h%number of parameters returned in infoh]h%number of parameters returned in info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h5``info`` array of elements containing the config infoh](j)}(h``info``h]j)}(hjh]hinfo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h,array of elements containing the config infoh]h,array of elements containing the config info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hj:ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj@h]h Description}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses struct drm_xe_query_config in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses struct drm_xe_query_config in .data.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj )}(hhh]j)}(hXThe index in **info** can be: - ``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits) - ``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list below - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAM - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT`` - Flag is set if the device supports the userspace hint ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``. This is exposed only on Xe2+. - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX`` - Flag is set if a queue can be creaed with ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX`` - ``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64K - ``DRM_XE_QUERY_CONFIG_VA_BITS`` - Maximum bits of a virtual address - ``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priority h](j)}(hThe index in **info** can be:h](h The index in }(hjlhhhNhNubh)}(h**info**h]hinfo}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlubh can be:}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhubj()}(hhh]j )}(hhh](j )}(hk``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits)h]h)}(hk``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID`` - Device ID (lower 16 bits) and the device revision (next 8 bits)h](j)}(h)``DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID``h]h%DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhB - Device ID (lower 16 bits) and the device revision (next 8 bits)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list below - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAM - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring support - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT`` - Flag is set if the device supports the userspace hint ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``. This is exposed only on Xe2+. - ``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX`` - Flag is set if a queue can be creaed with ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h](h)}(hY``DRM_XE_QUERY_CONFIG_FLAGS`` - Flags describing the device configuration, see list belowh](j)}(h``DRM_XE_QUERY_CONFIG_FLAGS``h]hDRM_XE_QUERY_CONFIG_FLAGS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh< - Flags describing the device configuration, see list below}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j )}(hQ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAMh]h)}(hQ``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM`` - Flag is set if the device has usable VRAMh](j)}(h%``DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM``h]h!DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, - Flag is set if the device has usable VRAM}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(he``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint supporth]h)}(he``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY`` - Flag is set if the device has low latency hint supporth](j)}(h,``DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY``h]h(DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh9 - Flag is set if the device has low latency hint support}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hn``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring supporth]h)}(hn``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR`` - Flag is set if the device has CPU address mirroring supporth](j)}(h0``DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR``h]h,DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh> - Flag is set if the device has CPU address mirroring support}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj,ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT`` - Flag is set if the device supports the userspace hint ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``. This is exposed only on Xe2+.h]h)}(h``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT`` - Flag is set if the device supports the userspace hint ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``. This is exposed only on Xe2+.h](j)}(h4``DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT``h]h0DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh9 - Flag is set if the device supports the userspace hint }(hjWhhhNhNubj)}(h)``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``h]h%DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh. This is exposed only on Xe2+.}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjSubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX`` - Flag is set if a queue can be creaed with ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h]h)}(h``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX`` - Flag is set if a queue can be creaed with ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h](j)}(h=``DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX``h]h9DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh- - Flag is set if a queue can be creaed with }(hjhhhNhNubj)}(h6``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h]h2DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hs``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64Kh]h)}(hs``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT`` - Minimal memory alignment required by this device, typically SZ_4K or SZ_64Kh](j)}(h%``DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT``h]h!DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhN - Minimal memory alignment required by this device, typically SZ_4K or SZ_64K}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hC``DRM_XE_QUERY_CONFIG_VA_BITS`` - Maximum bits of a virtual addressh]h)}(hjh](j)}(h``DRM_XE_QUERY_CONFIG_VA_BITS``h]hDRM_XE_QUERY_CONFIG_VA_BITS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh$ - Maximum bits of a virtual address}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hh``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priority h]h)}(hd``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY`` - Value of the highest available exec queue priorityh](j)}(h/``DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY``h]h+DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh5 - Value of the highest available exec queue priority}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjhubeh}(h]h ]h"]h$]h&]uh1jhjhMhjeubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_gt (C struct) c.drm_xe_gthNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(h drm_xe_gth]j)}(hstruct drm_xe_gth](j)}(hjh]hstruct}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnhhhjhMubj)}(h drm_xe_gth]j)}(hjlh]h drm_xe_gt}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjnhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjjhhhjhMubah}(h]jeah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjghhubj))}(hhh]h)}(hdescribe an individual GT.h]hdescribe an individual GT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjghhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; }; **Members** ``type`` GT type: Main or Media ``tile_id`` Tile ID where this GT lives (Information only) ``gt_id`` Unique ID of this GT within the PCI Device ``pad`` MBZ ``reference_clock`` A clock frequency for timestamp ``near_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``far_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``ip_ver_major`` Graphics/media IP major version on GMD_ID platforms ``ip_ver_minor`` Graphics/media IP minor version on GMD_ID platforms ``ip_ver_rev`` Graphics/media IP revision version on GMD_ID platforms ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hXstruct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; };h]hXstruct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0; #define DRM_XE_QUERY_GT_TYPE_MEDIA 1; __u16 type; __u16 tile_id; __u16 gt_id; __u16 pad[3]; __u32 reference_clock; __u64 near_mem_regions; __u64 far_mem_regions; __u16 ip_ver_major; __u16 ip_ver_minor; __u16 ip_ver_rev; __u16 pad2; __u64 reserved[7]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h ``type`` GT type: Main or Media h](j)}(h``type``h]j)}(hj!h]htype}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hGT type: Main or Mediah]hGT type: Main or Media}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj7ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj6hMhjubj)}(h;``tile_id`` Tile ID where this GT lives (Information only) h](j)}(h ``tile_id``h]j)}(hjZh]htile_id}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjTubj()}(hhh]h)}(h.Tile ID where this GT lives (Information only)h]h.Tile ID where this GT lives (Information only)}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohMhjpubah}(h]h ]h"]h$]h&]uh1j'hjTubeh}(h]h ]h"]h$]h&]uh1jhjohMhjubj)}(h5``gt_id`` Unique ID of this GT within the PCI Device h](j)}(h ``gt_id``h]j)}(hjh]hgt_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h*Unique ID of this GT within the PCI Deviceh]h*Unique ID of this GT within the PCI Device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h4``reference_clock`` A clock frequency for timestamp h](j)}(h``reference_clock``h]j)}(hjh]hreference_clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hA clock frequency for timestamph]hA clock frequency for timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hXV``near_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h``near_mem_regions``h]j)}(hj>h]hnear_mem_regions}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj8ubj()}(hhh]h)}(hX@Bit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h]hXDBit mask of instances from drm_xe_query_mem_regions that are nearest to the current engines of this GT. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjTubah}(h]h ]h"]h$]h&]uh1j'hj8ubeh}(h]h ]h"]h$]h&]uh1jhjShMhjubj)}(hX``far_mem_regions`` Bit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h``far_mem_regions``h]j)}(hjxh]hfar_mem_regions}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjrubj()}(hhh]h)}(hXBit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the **near_mem_regions**. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h](hBit mask of instances from drm_xe_query_mem_regions that are far from the engines of this GT. In general, they have extra indirections when compared to the }(hjhhhNhNubh)}(h**near_mem_regions**h]hnear_mem_regions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhX9. For a discrete device this could mean system memory and memory living in a different tile. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjrubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hE``ip_ver_major`` Graphics/media IP major version on GMD_ID platforms h](j)}(h``ip_ver_major``h]j)}(hjh]h ip_ver_major}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h3Graphics/media IP major version on GMD_ID platformsh]h3Graphics/media IP major version on GMD_ID platforms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hE``ip_ver_minor`` Graphics/media IP minor version on GMD_ID platforms h](j)}(h``ip_ver_minor``h]j)}(hjh]h ip_ver_minor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h3Graphics/media IP minor version on GMD_ID platformsh]h3Graphics/media IP minor version on GMD_ID platforms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hF``ip_ver_rev`` Graphics/media IP revision version on GMD_ID platforms h](j)}(h``ip_ver_rev``h]j)}(hj6h]h ip_ver_rev}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj0ubj()}(hhh]h)}(h6Graphics/media IP revision version on GMD_ID platformsh]h6Graphics/media IP revision version on GMD_ID platforms}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMhjLubah}(h]h ]h"]h$]h&]uh1j'hj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMhjubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjoh]hpad2}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjiubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjiubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hTo be used with drm_xe_query_gt_list, which will return a list with all the existing GT individual descriptions. Graphics Technology (GT) is a subset of a GPU/tile that is responsible for implementing graphics and/or media operations.h]hTo be used with drm_xe_query_gt_list, which will return a list with all the existing GT individual descriptions. Graphics Technology (GT) is a subset of a GPU/tile that is responsible for implementing graphics and/or media operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj )}(hhh]j)}(hbThe index in **type** can be: - ``DRM_XE_QUERY_GT_TYPE_MAIN`` - ``DRM_XE_QUERY_GT_TYPE_MEDIA`` h](j)}(hThe index in **type** can be:h](h The index in }(hjhhhNhNubh)}(h**type**h]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]j )}(hhh](j )}(h``DRM_XE_QUERY_GT_TYPE_MAIN``h]h)}(hj@h]j)}(hj@h]hDRM_XE_QUERY_GT_TYPE_MAIN}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj>ubah}(h]h ]h"]h$]h&]uh1j hj;ubj )}(h"``DRM_XE_QUERY_GT_TYPE_MEDIA`` h]h)}(h``DRM_XE_QUERY_GT_TYPE_MEDIA``h]j)}(hjeh]hDRM_XE_QUERY_GT_TYPE_MEDIA}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj_ubah}(h]h ]h"]h$]h&]uh1j hj;ubeh}(h]h ]h"]h$]h&]j) j* uh1j hjXhMhj8ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj7hMhjubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_query_gt_list (C struct)c.drm_xe_query_gt_listhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_gt_listh]j)}(hstruct drm_xe_query_gt_listh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_query_gt_listh]j)}(hjh]hdrm_xe_query_gt_list}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h!A list with GT description items.h]h!A list with GT description items.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj jLj jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; }; **Members** ``num_gt`` number of GT items returned in gt_list ``pad`` MBZ ``gt_list`` The GT list returned for this deviceh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hastruct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; };h]hastruct drm_xe_query_gt_list { __u32 num_gt; __u32 pad; struct drm_xe_gt gt_list[]; };}hj1sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjBh]hMembers}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h2``num_gt`` number of GT items returned in gt_list h](j)}(h ``num_gt``h]j)}(hjah]hnum_gt}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj[ubj()}(hhh]h)}(h&number of GT items returned in gt_listh]h&number of GT items returned in gt_list}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjwubah}(h]h ]h"]h$]h&]uh1j'hj[ubeh}(h]h ]h"]h$]h&]uh1jhjvhMhjXubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjXubj)}(h0``gt_list`` The GT list returned for this deviceh](j)}(h ``gt_list``h]j)}(hjh]hgt_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h$The GT list returned for this deviceh]h$The GT list returned for this device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjXubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct drm_xe_query_gt_list in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct drm_xe_query_gt_list in .data.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_xe_query_topology_mask (C struct)c.drm_xe_query_topology_maskhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_topology_maskh]j)}(h!struct drm_xe_query_topology_maskh](j)}(hjh]hstruct}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhjahMubj)}(hdrm_xe_query_topology_maskh]j)}(hjNh]hdrm_xe_query_topology_mask}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubah}(h]h ](j jeh"]h$]h&]jjuh1jhjPhhhjahMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjLhhhjahMubah}(h]jGah ](j j!eh"]h$]h&]j%j&)j'huh1jhjahMhjIhhubj))}(hhh]h)}(h"describe the topology mask of a GTh]h"describe the topology mask of a GT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjIhhhjahMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX$**Definition**:: struct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; }; **Members** ``gt_id`` GT ID the mask is associated with ``type`` type of mask ``num_bytes`` number of bytes in requested mask ``mask`` little-endian mask of **num_bytes**h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubjt)}(hXDstruct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; };h]hXDstruct drm_xe_query_topology_mask { __u16 gt_id; #define DRM_XE_TOPO_DSS_GEOMETRY 1; #define DRM_XE_TOPO_DSS_COMPUTE 2; #define DRM_XE_TOPO_L3_BANK 3; #define DRM_XE_TOPO_EU_PER_DSS 4; #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5; __u16 type; __u32 num_bytes; __u8 mask[]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h,``gt_id`` GT ID the mask is associated with h](j)}(h ``gt_id``h]j)}(hjh]hgt_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM-hjubj()}(hhh]h)}(h!GT ID the mask is associated withh]h!GT ID the mask is associated with}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM-hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM-hjubj)}(h``type`` type of mask h](j)}(h``type``h]j)}(hj<h]htype}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM5hj6ubj()}(hhh]h)}(h type of maskh]h type of mask}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhM5hjRubah}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jhjQhM5hjubj)}(h0``num_bytes`` number of bytes in requested mask h](j)}(h ``num_bytes``h]j)}(hjuh]h num_bytes}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM8hjoubj()}(hhh]h)}(h!number of bytes in requested maskh]h!number of bytes in requested mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM8hjubah}(h]h ]h"]h$]h&]uh1j'hjoubeh}(h]h ]h"]h$]h&]uh1jhjhM8hjubj)}(h,``mask`` little-endian mask of **num_bytes**h](j)}(h``mask``h]j)}(hjh]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM:hjubj()}(hhh]h)}(h#little-endian mask of **num_bytes**h](hlittle-endian mask of }(hjhhhNhNubh)}(h **num_bytes**h]h num_bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM;hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM:hjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM>hj۴hhubh)}(hXThis is the hardware topology which reflects the internal physical structure of the GPU.h]hXThis is the hardware topology which reflects the internal physical structure of the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses struct drm_xe_query_topology_mask in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses struct drm_xe_query_topology_mask in .data.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj۴hhubj )}(hhh]j)}(hXYThe **type** can be: - ``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry. - ``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute. - ``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware. - ``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs. - ``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs. h](j)}(hThe **type** can be:h](hThe }(hj:hhhNhNubh)}(h**type**h]htype}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh can be:}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM+hj6ubj()}(hhh]j )}(hhh](j )}(hX``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry.h]h)}(hX``DRM_XE_TOPO_DSS_GEOMETRY`` - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` means 32 DSS are available for geometry.h](j)}(h``DRM_XE_TOPO_DSS_GEOMETRY``h]hDRM_XE_TOPO_DSS_GEOMETRY}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh - To query the mask of Dual Sub Slices (DSS) available for geometry operations. For example a query response containing the following in mask: }(hjehhhNhNubj)}(h+``DSS_GEOMETRY ff ff ff ff 00 00 00 00``h]h'DSS_GEOMETRY ff ff ff ff 00 00 00 00}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh) means 32 DSS are available for geometry.}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjaubah}(h]h ]h"]h$]h&]uh1j hj^ubj )}(h``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute.h]h)}(h``DRM_XE_TOPO_DSS_COMPUTE`` - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` means 32 DSS are available for compute.h](j)}(h``DRM_XE_TOPO_DSS_COMPUTE``h]hDRM_XE_TOPO_DSS_COMPUTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - To query the mask of Dual Sub Slices (DSS) available for compute operations. For example a query response containing the following in mask: }(hjhhhNhNubj)}(h*``DSS_COMPUTE ff ff ff ff 00 00 00 00``h]h&DSS_COMPUTE ff ff ff ff 00 00 00 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh( means 32 DSS are available for compute.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hj^ubj )}(h``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.h]h)}(h``DRM_XE_TOPO_L3_BANK`` - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.h](j)}(h``DRM_XE_TOPO_L3_BANK``h]hDRM_XE_TOPO_L3_BANK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - To query the mask of enabled L3 banks. This type may be omitted if the driver is unable to query the mask from the hardware.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hj^ubj )}(hX0``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs.h]h)}(hX0``DRM_XE_TOPO_EU_PER_DSS`` - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn't have SIMD8 EUs.h](j)}(h``DRM_XE_TOPO_EU_PER_DSS``h]hDRM_XE_TOPO_EU_PER_DSS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - To query the mask of Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: }(hjhhhNhNubj)}(h)``EU_PER_DSS ff ff 00 00 00 00 00 00``h]h%EU_PER_DSS ff ff 00 00 00 00 00 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh^ means each DSS has 16 SIMD8 EUs. This type may be omitted if device doesn’t have SIMD8 EUs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hj^ubj )}(hXK``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs. h]h)}(hXG``DRM_XE_TOPO_SIMD16_EU_PER_DSS`` - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn't have SIMD16 EUs.h](j)}(h!``DRM_XE_TOPO_SIMD16_EU_PER_DSS``h]hDRM_XE_TOPO_SIMD16_EU_PER_DSS}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubh - To query the mask of SIMD16 Execution Units (EU) available per Dual Sub Slices (DSS). For example a query response containing the following in mask: }(hj7hhhNhNubj)}(h0``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00``h]h,SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubh` means each DSS has 16 SIMD16 EUs. This type may be omitted if device doesn’t have SIMD16 EUs.}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM#hj3ubah}(h]h ]h"]h$]h&]uh1j hj^ubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhMhj[ubah}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jhjZhM+hj3ubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_xe_query_engine_cycles (C struct)c.drm_xe_query_engine_cycleshNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_engine_cyclesh]j)}(h!struct drm_xe_query_engine_cyclesh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM-ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM-ubj)}(hdrm_xe_query_engine_cyclesh]j)}(hjh]hdrm_xe_query_engine_cycles}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhM-ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM-ubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM-hjhhubj))}(hhh]h)}(h correlate CPU and GPU timestampsh]h correlate CPU and GPU timestamps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM?hjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhM-ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; }; **Members** ``eci`` This is input by the user and is the engine for which command streamer cycles is queried. ``clockid`` This is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. ``width`` Width of the engine cycle counter in bits. ``engine_cycles`` Engine cycles as read from its register at 0x358 offset. ``cpu_timestamp`` CPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user. ``cpu_delta`` Time delta in ns captured around reading the lower dword of the engine_cycles register.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMChjubjt)}(hstruct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; };h]hstruct drm_xe_query_engine_cycles { struct drm_xe_engine_class_instance eci; __s32 clockid; __u32 width; __u64 engine_cycles; __u64 cpu_timestamp; __u64 cpu_delta; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMEhjubh)}(h **Members**h]h)}(hj-h]hMembers}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMNhjubj )}(hhh](j)}(hb``eci`` This is input by the user and is the engine for which command streamer cycles is queried. h](j)}(h``eci``h]j)}(hjLh]heci}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMOhjFubj()}(hhh]h)}(hYThis is input by the user and is the engine for which command streamer cycles is queried.h]hYThis is input by the user and is the engine for which command streamer cycles is queried.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMNhjbubah}(h]h ]h"]h$]h&]uh1j'hjFubeh}(h]h ]h"]h$]h&]uh1jhjahMOhjCubj)}(h``clockid`` This is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. h](j)}(h ``clockid``h]j)}(hjh]hclockid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMWhjubj()}(hhh]h)}(hThis is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.h]hThis is input by the user and is the reference clock id for CPU timestamp. For definition, see clock_gettime(2) and perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMThjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMWhjCubj)}(h5``width`` Width of the engine cycle counter in bits. h](j)}(h ``width``h]j)}(hjh]hwidth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM[hjubj()}(hhh]h)}(h*Width of the engine cycle counter in bits.h]h*Width of the engine cycle counter in bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM[hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM[hjCubj)}(hK``engine_cycles`` Engine cycles as read from its register at 0x358 offset. h](j)}(h``engine_cycles``h]j)}(hjh]h engine_cycles}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM`hjubj()}(hhh]h)}(h8Engine cycles as read from its register at 0x358 offset.h]h8Engine cycles as read from its register at 0x358 offset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM_hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM`hjCubj)}(h``cpu_timestamp`` CPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user. h](j)}(h``cpu_timestamp``h]j)}(hj3h]h cpu_timestamp}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMghj-ubj()}(hhh]h)}(hCPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user.h]hCPU timestamp in ns. The timestamp is captured before reading the engine_cycles register using the reference clockid set by the user.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMehjIubah}(h]h ]h"]h$]h&]uh1j'hj-ubeh}(h]h ]h"]h$]h&]uh1jhjHhMghjCubj)}(he``cpu_delta`` Time delta in ns captured around reading the lower dword of the engine_cycles register.h](j)}(h ``cpu_delta``h]j)}(hjmh]h cpu_delta}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhjgubj()}(hhh]h)}(hWTime delta in ns captured around reading the lower dword of the engine_cycles register.h]hWTime delta in ns captured around reading the lower dword of the engine_cycles register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMlhjubah}(h]h ]h"]h$]h&]uh1j'hjgubeh}(h]h ]h"]h$]h&]uh1jhjhMlhjCubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMphj۴hhubh)}(hXIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles in .data. struct drm_xe_query_engine_cycles is allocated by the user and .data points to this allocated structure.h]hXIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles in .data. struct drm_xe_query_engine_cycles is allocated by the user and .data points to this allocated structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM@hj۴hhubh)}(hThe query returns the engine cycles, which along with GT's **reference_clock**, can be used to calculate the engine timestamp. In addition the query returns a set of cpu timestamps that indicate when the command streamer cycle count was captured.h](h=The query returns the engine cycles, which along with GT’s }(hjhhhNhNubh)}(h**reference_clock**h]hreference_clock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh, can be used to calculate the engine timestamp. In addition the query returns a set of cpu timestamps that indicate when the command streamer cycle count was captured.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMEhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%drm_xe_query_uc_fw_version (C struct)c.drm_xe_query_uc_fw_versionhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_uc_fw_versionh]j)}(h!struct drm_xe_query_uc_fw_versionh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhjhMMubj)}(hdrm_xe_query_uc_fw_versionh]j)}(hjh]hdrm_xe_query_uc_fw_version}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj hhhjhMMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMMhjhhubj))}(hhh]h)}(h)query a micro-controller firmware versionh]h)query a micro-controller firmware version}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMrhjMhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjhjLjhjMjNjOuh1jhhhj۴hjhM ubjQ)}(hXT**Definition**:: struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; }; **Members** ``uc_type`` The micro-controller type to query firmware version ``pad`` MBZ ``branch_ver`` branch uc fw version ``major_ver`` major uc fw version ``minor_ver`` minor uc fw version ``patch_ver`` patch uc fw version ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpubh:}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMvhjlubjt)}(hX struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; };h]hX struct drm_xe_query_uc_fw_version { #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0; #define XE_QUERY_UC_TYPE_HUC 1; __u16 uc_type; __u16 pad; __u32 branch_ver; __u32 major_ver; __u32 minor_ver; __u32 patch_ver; __u32 pad2; __u64 reserved; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMxhjlubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjlubj )}(hhh](j)}(h@``uc_type`` The micro-controller type to query firmware version h](j)}(h ``uc_type``h]j)}(hjh]huc_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMyhjubj()}(hhh]h)}(h3The micro-controller type to query firmware versionh]h3The micro-controller type to query firmware version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMyhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMyhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM~hj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hM~hjubj)}(h$``branch_ver`` branch uc fw version h](j)}(h``branch_ver``h]j)}(hj/h]h branch_ver}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj)ubj()}(hhh]h)}(hbranch uc fw versionh]hbranch uc fw version}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjEubah}(h]h ]h"]h$]h&]uh1j'hj)ubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjubj)}(h"``major_ver`` major uc fw version h](j)}(h ``major_ver``h]j)}(hjhh]h major_ver}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjbubj()}(hhh]h)}(hmajor uc fw versionh]hmajor uc fw version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj~ubah}(h]h ]h"]h$]h&]uh1j'hjbubeh}(h]h ]h"]h$]h&]uh1jhj}hMhjubj)}(h"``minor_ver`` minor uc fw version h](j)}(h ``minor_ver``h]j)}(hjh]h minor_ver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hminor uc fw versionh]hminor uc fw version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h"``patch_ver`` patch uc fw version h](j)}(h ``patch_ver``h]j)}(hjh]h patch_ver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hpatch uc fw versionh]hpatch uc fw version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj()}(hhh]h)}(hMBZh]hMBZ}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hMhj)ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjLh]hreserved}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjFubj()}(hhh]h)}(hReservedh]hReserved}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjbubah}(h]h ]h"]h$]h&]uh1j'hjFubeh}(h]h ]h"]h$]h&]uh1jhjahMhjubeh}(h]h ]h"]h$]h&]uh1j hjlubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hmGiven a uc_type this will return the branch, major, minor and patch version of the micro-controller firmware.h]hmGiven a uc_type this will return the branch, major, minor and patch version of the micro-controller firmware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMshj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_xe_query_pxp_status (C struct)c.drm_xe_query_pxp_statushNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_pxp_statush]j)}(hstruct drm_xe_query_pxp_statush](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMyubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMyubj)}(hdrm_xe_query_pxp_statush]j)}(hjh]hdrm_xe_query_pxp_status}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMyubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMyubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMyhjhhubj))}(hhh]h)}(hquery if PXP is readyh]hquery if PXP is ready}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMyubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj'jLj'jMjNjOuh1jhhhj۴hjhM ubjQ)}(h**Definition**:: struct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; }; **Members** ``status`` current PXP status ``supported_session_types`` bitmask of supported PXP session typesh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/ubh:}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj+ubjt)}(hXstruct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; };h]hXstruct drm_xe_query_pxp_status { __u32 status; __u32 supported_session_types; };}hjLsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj+ubh)}(h **Members**h]h)}(hj]h]hMembers}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj+ubj )}(hhh](j)}(h``status`` current PXP status h](j)}(h ``status``h]j)}(hj|h]hstatus}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjvubj()}(hhh]h)}(hcurrent PXP statush]hcurrent PXP status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjvubeh}(h]h ]h"]h$]h&]uh1jhjhMhjsubj)}(hB``supported_session_types`` bitmask of supported PXP session typesh](j)}(h``supported_session_types``h]j)}(hjh]hsupported_session_types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h&bitmask of supported PXP session typesh]h&bitmask of supported PXP session types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjsubeh}(h]h ]h"]h$]h&]uh1j hj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hIf PXP is enabled and no fatal error has occurred, the status will be set to one of the following values: 0: PXP init still in progress 1: PXP init completeh]hIf PXP is enabled and no fatal error has occurred, the status will be set to one of the following values: 0: PXP init still in progress 1: PXP init complete}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hXXIf PXP is not enabled or something has gone wrong, the query will be failed with one of the following error codes: -ENODEV: PXP not supported or disabled; -EIO: fatal error occurred during init, so PXP will never be enabled; -EINVAL: incorrect value provided as part of the query; -EFAULT: error copying the memory between kernel and userspace.h]hXXIf PXP is not enabled or something has gone wrong, the query will be failed with one of the following error codes: -ENODEV: PXP not supported or disabled; -EIO: fatal error occurred during init, so PXP will never be enabled; -EINVAL: incorrect value provided as part of the query; -EFAULT: error copying the memory between kernel and userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hX.The status can only be 0 in the first few seconds after driver load. If everything works as expected, the status will transition to init complete in less than 1 second, while in case of errors the driver might take longer to start returning an error code, but it should still take less than 10 seconds.h]hX.The status can only be 0 in the first few seconds after driver load. If everything works as expected, the status will transition to init complete in less than 1 second, while in case of errors the driver might take longer to start returning an error code, but it should still take less than 10 seconds.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hThe supported session type bitmask is based on the values in enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore is not reported in the bitmask.h]hThe supported session type bitmask is based on the values in enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore is not reported in the bitmask.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_device_query (C struct)c.drm_xe_device_queryhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_device_queryh]j)}(hstruct drm_xe_device_queryh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhhjphMubj)}(hdrm_xe_device_queryh]j)}(hj]h]hdrm_xe_device_query}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhj_hhhjphMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj[hhhjphMubah}(h]jVah ](j j!eh"]h$]h&]j%j&)j'huh1jhjphMhjXhhubj))}(hhh]h)}(hYInput of :c:type:`DRM_IOCTL_XE_DEVICE_QUERY` - main structure to query device informationh](h Input of }(hjhhhNhNubh)}(h#:c:type:`DRM_IOCTL_XE_DEVICE_QUERY`h]j)}(hjh]hDRM_IOCTL_XE_DEVICE_QUERY}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j" ASTIdentifier)} identifierj]sbc.drm_xe_device_queryasbj) DRM_IOCTL_XE_DEVICE_QUERYuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubh- - main structure to query device information}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjXhhhjphMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``query`` The type of data to query ``size`` Size of the queried data ``data`` Queried data is placed here ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hXstruct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; };h]hXstruct drm_xe_device_query { __u64 extensions; #define DRM_XE_DEVICE_QUERY_ENGINES 0; #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1; #define DRM_XE_DEVICE_QUERY_CONFIG 2; #define DRM_XE_DEVICE_QUERY_GT_LIST 3; #define DRM_XE_DEVICE_QUERY_HWCONFIG 4; #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5; #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6; #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7; #define DRM_XE_DEVICE_QUERY_OA_UNITS 8; #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9; #define DRM_XE_DEVICE_QUERY_EU_STALL 10; __u32 query; __u32 size; __u64 data; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hj!h]hMembers}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj@h]h extensions}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj:ubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjVubah}(h]h ]h"]h$]h&]uh1j'hj:ubeh}(h]h ]h"]h$]h&]uh1jhjUhMhj7ubj)}(h$``query`` The type of data to query h](j)}(h ``query``h]j)}(hjyh]hquery}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjsubj()}(hhh]h)}(hThe type of data to queryh]hThe type of data to query}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjsubeh}(h]h ]h"]h$]h&]uh1jhjhMhj7ubj)}(h"``size`` Size of the queried data h](j)}(h``size``h]j)}(hjh]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hSize of the queried datah]hSize of the queried data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj7ubj)}(h%``data`` Queried data is placed here h](j)}(h``data``h]j)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hQueried data is placed hereh]hQueried data is placed here}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj7ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hj$h]hreserved}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hReservedh]hReserved}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj:ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj7ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjgh]h Description}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjeubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hThe user selects the type of data to query among DRM_XE_DEVICE_QUERY_* and sets the value in the query member. This determines the type of the structure provided by the driver in data, among struct drm_xe_query_*.h]hThe user selects the type of data to query among DRM_XE_DEVICE_QUERY_* and sets the value in the query member. This determines the type of the structure provided by the driver in data, among struct drm_xe_query_*.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj )}(hhh]j)}(hXThe **query** can be: - ``DRM_XE_DEVICE_QUERY_ENGINES`` - ``DRM_XE_DEVICE_QUERY_MEM_REGIONS`` - ``DRM_XE_DEVICE_QUERY_CONFIG`` - ``DRM_XE_DEVICE_QUERY_GT_LIST`` - ``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes. - ``DRM_XE_DEVICE_QUERY_GT_TOPOLOGY`` - ``DRM_XE_DEVICE_QUERY_ENGINE_CYCLES`` - ``DRM_XE_DEVICE_QUERY_PXP_STATUS`` h](j)}(hThe **query** can be:h](hThe }(hjhhhNhNubh)}(h **query**h]hquery}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]j )}(hhh](j )}(h``DRM_XE_DEVICE_QUERY_ENGINES``h]h)}(hjh]j)}(hjh]hDRM_XE_DEVICE_QUERY_ENGINES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h#``DRM_XE_DEVICE_QUERY_MEM_REGIONS``h]h)}(hjh]j)}(hjh]hDRM_XE_DEVICE_QUERY_MEM_REGIONS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_DEVICE_QUERY_CONFIG``h]h)}(hjh]j)}(hjh]hDRM_XE_DEVICE_QUERY_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_DEVICE_QUERY_GT_LIST``h]h)}(hjh]j)}(hjh]hDRM_XE_DEVICE_QUERY_GT_LIST}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.h]h)}(h``DRM_XE_DEVICE_QUERY_HWCONFIG`` - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.h](j)}(h ``DRM_XE_DEVICE_QUERY_HWCONFIG``h]hDRM_XE_DEVICE_QUERY_HWCONFIG}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubh - Query type to retrieve the hardware configuration of the device such as information on slices, memory, caches, and so on. It is provided as a table of key / value attributes.}(hjBhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj>ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h#``DRM_XE_DEVICE_QUERY_GT_TOPOLOGY``h]h)}(hjgh]j)}(hjgh]hDRM_XE_DEVICE_QUERY_GT_TOPOLOGY}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjeubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h%``DRM_XE_DEVICE_QUERY_ENGINE_CYCLES``h]h)}(hjh]j)}(hjh]h!DRM_XE_DEVICE_QUERY_ENGINE_CYCLES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h#``DRM_XE_DEVICE_QUERY_PXP_STATUS`` h]h)}(h"``DRM_XE_DEVICE_QUERY_PXP_STATUS``h]j)}(hjh]hDRM_XE_DEVICE_QUERY_PXP_STATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubh)}(hX-If size is set to 0, the driver fills it with the required size for the requested type of data to query. If size is equal to the required size, the queried information is copied into data. If size is set to a value different from 0 and different from the required size, the IOCTL call returns -EINVAL.h]hX-If size is set to 0, the driver fills it with the required size for the requested type of data to query. If size is equal to the required size, the queried information is copied into data. If size is set to a value different from 0 and different from the required size, the IOCTL call returns -EINVAL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hFor example the following code snippet allows retrieving and printing information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:h]hFor example the following code snippet allows retrieving and printing information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubjt)}(hXstruct drm_xe_query_engines *engines; struct drm_xe_device_query query = { .extensions = 0, .query = DRM_XE_DEVICE_QUERY_ENGINES, .size = 0, .data = 0, }; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); engines = malloc(query.size); query.data = (uintptr_t)engines; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); for (int i = 0; i < engines->num_engines; i++) { printf("Engine %d: %s\n", i, engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": "UNKNOWN"); } free(engines);h]hXstruct drm_xe_query_engines *engines; struct drm_xe_device_query query = { .extensions = 0, .query = DRM_XE_DEVICE_QUERY_ENGINES, .size = 0, .data = 0, }; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); engines = malloc(query.size); query.data = (uintptr_t)engines; ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); for (int i = 0; i < engines->num_engines; i++) { printf("Engine %d: %s\n", i, engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": engines->engines[i].instance.engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": "UNKNOWN"); } free(engines);}hjsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_gem_create (C struct)c.drm_xe_gem_createhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_gem_createh]j)}(hstruct drm_xe_gem_createh](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhj4hMubj)}(hdrm_xe_gem_createh]j)}(hj!h]hdrm_xe_gem_create}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ](j jeh"]h$]h&]jjuh1jhj#hhhj4hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj4hMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj4hMhjhhubj))}(hhh]h)}(hIInput of :c:type:`DRM_IOCTL_XE_GEM_CREATE` - A structure for gem creationh](h Input of }(hjihhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_GEM_CREATE`h]j)}(hjsh]hDRM_IOCTL_XE_GEM_CREATE}(hjuhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jj!sbc.drm_xe_gem_createasbj) DRM_IOCTL_XE_GEM_CREATEuh1hhjhKhjiubh - A structure for gem creation}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjfhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj4hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``size`` Size of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`). ``placement`` A mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. ``flags`` Flags, currently a mask of memory instances of where BO can be placed ``vm_id`` Attached VM, if any If a VM is specified, this BO must: 1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. ``handle`` Returned handle for the object. Object handles are nonzero. ``cpu_caching`` The CPU caching mode to select for this object. If mmaping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients. ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubjt)}(hXstruct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; };h]hXstruct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0; __u64 extensions; __u64 size; __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0); #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1); #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2); #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3); __u32 flags; __u32 vm_id; __u32 handle; #define DRM_XE_GEM_CPU_CACHING_WB 1; #define DRM_XE_GEM_CPU_CACHING_WC 2; __u16 cpu_caching; __u16 pad[3]; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM#hjubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMKhjubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMKhjubj)}(h{``size`` Size of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`). h](j)}(h``size``h]j)}(hj9h]hsize}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMPhj3ubj()}(hhh]h)}(hqSize of the object to be created, must match region (system or vram) minimum alignment (:c:type:`min_page_size`).h](hXSize of the object to be created, must match region (system or vram) minimum alignment (}(hjRhhhNhNubh)}(h:c:type:`min_page_size`h]j)}(hj\h]h min_page_size}(hj^hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) min_page_sizeuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMOhjRubh).}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjyhMOhjOubah}(h]h ]h"]h$]h&]uh1j'hj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhMPhjubj)}(hX``placement`` A mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class. h](j)}(h ``placement``h]j)}(hjh]h placement}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMYhjubj()}(hhh]h)}(hXA mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions' instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions' mem_class.h]hXA mask of memory instances of where BO can be placed. Each index in this mask refers directly to the struct drm_xe_query_mem_regions’ instance, no assumptions should be made about order. The type of each region is described by struct drm_xe_query_mem_regions’ mem_class.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMUhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMYhjubj)}(hP``flags`` Flags, currently a mask of memory instances of where BO can be placed h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMchjubj()}(hhh]h)}(hEFlags, currently a mask of memory instances of where BO can be placedh]hEFlags, currently a mask of memory instances of where BO can be placed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMbhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMchjubj)}(h``vm_id`` Attached VM, if any If a VM is specified, this BO must: 1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. h](j)}(h ``vm_id``h]j)}(hj h]hvm_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMmhjubj()}(hhh](h)}(hAttached VM, if anyh]hAttached VM, if any}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhhj ubh)}(h#If a VM is specified, this BO must:h]h#If a VM is specified, this BO must:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMjhj ubj)}(hG1. Only ever be bound to that VM. 2. Cannot be exported as a PRIME fd. h]j3)}(hhh](j )}(hOnly ever be bound to that VM.h]h)}(hjJh]hOnly ever be bound to that VM.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhjHubah}(h]h ]h"]h$]h&]uh1j hjEubj )}(h"Cannot be exported as a PRIME fd. h]h)}(h!Cannot be exported as a PRIME fd.h]h!Cannot be exported as a PRIME fd.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMmhj`ubah}(h]h ]h"]h$]h&]uh1j hjEubeh}(h]h ]h"]h$]h&]jZ4j[4j\4hj]4j^4uh1j3hjAubah}(h]h ]h"]h$]h&]uh1jhjYhMlhj ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMmhjubj)}(hH``handle`` Returned handle for the object. Object handles are nonzero. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMthjubj()}(hhh](h)}(hReturned handle for the object.h]hReturned handle for the object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMrhjubh)}(hObject handles are nonzero.h]hObject handles are nonzero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMthjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMthjubj)}(hX``cpu_caching`` The CPU caching mode to select for this object. If mmaping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients. h](j)}(h``cpu_caching``h]j)}(hjh]h cpu_caching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hXThe CPU caching mode to select for this object. If mmaping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients.h]hXThe CPU caching mode to select for this object. If mmaping the object the mode selected here will also be used. The exception is when mapping system memory (including data evicted to system) on discrete GPUs. The caching mode selected will then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency between GPU- and CPU is guaranteed. The caching mode of existing CPU-mappings will be updated transparently to user-space clients.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM{hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMhj.ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj-hMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjQh]hreserved}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjKubj()}(hhh]h)}(hReservedh]hReserved}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjgubah}(h]h ]h"]h$]h&]uh1j'hjKubeh}(h]h ]h"]h$]h&]uh1jhjfhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj )}(hhh]j)}(hX'The **flags** can be: - ``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING`` - Modify the GEM object allocation strategy by deferring physical memory allocation until the object is either bound to a virtual memory region via VM_BIND or accessed by the CPU. As a result, no backing memory is reserved at the time of GEM object creation. - ``DRM_XE_GEM_CREATE_FLAG_SCANOUT`` - Indicates that the GEM object is intended for scanout via the display engine. When set, kernel ensures that the allocation is placed in a memory region compatible with the display engine requirements. This may impose restrictions on tiling, alignment, and memory placement to guarantee proper display functionality. - ``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems. - ``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION`` - Allows userspace to hint that compression (CCS) should be disabled for the buffer being created. This can avoid unnecessary memory operations and CCS state management. On pre-Xe2 platforms, this flag is currently rejected as compression control is not supported via PAT index. On Xe2+ platforms, compression is controlled via PAT entries. If this flag is set, the driver will reject any VM bind that requests a PAT index enabling compression for this BO. h](j)}(hThe **flags** can be:h](hThe }(hjhhhNhNubh)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM+hjubj()}(hhh]j )}(hhh](j )}(hX+``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING`` - Modify the GEM object allocation strategy by deferring physical memory allocation until the object is either bound to a virtual memory region via VM_BIND or accessed by the CPU. As a result, no backing memory is reserved at the time of GEM object creation.h]h)}(hX+``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING`` - Modify the GEM object allocation strategy by deferring physical memory allocation until the object is either bound to a virtual memory region via VM_BIND or accessed by the CPU. As a result, no backing memory is reserved at the time of GEM object creation.h](j)}(h(``DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING``h]h$DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX - Modify the GEM object allocation strategy by deferring physical memory allocation until the object is either bound to a virtual memory region via VM_BIND or accessed by the CPU. As a result, no backing memory is reserved at the time of GEM object creation.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX```DRM_XE_GEM_CREATE_FLAG_SCANOUT`` - Indicates that the GEM object is intended for scanout via the display engine. When set, kernel ensures that the allocation is placed in a memory region compatible with the display engine requirements. This may impose restrictions on tiling, alignment, and memory placement to guarantee proper display functionality.h]h)}(hX```DRM_XE_GEM_CREATE_FLAG_SCANOUT`` - Indicates that the GEM object is intended for scanout via the display engine. When set, kernel ensures that the allocation is placed in a memory region compatible with the display engine requirements. This may impose restrictions on tiling, alignment, and memory placement to guarantee proper display functionality.h](j)}(h"``DRM_XE_GEM_CREATE_FLAG_SCANOUT``h]hDRM_XE_GEM_CREATE_FLAG_SCANOUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX> - Indicates that the GEM object is intended for scanout via the display engine. When set, kernel ensures that the allocation is placed in a memory region compatible with the display engine requirements. This may impose restrictions on tiling, alignment, and memory placement to guarantee proper display functionality.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hXN``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems.h]h)}(hXN``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM`` - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can't be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems.h](j)}(h-``DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM``h]h)DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubhX# - When using VRAM as a possible placement, ensure that the corresponding VRAM allocation will always use the CPU accessible part of VRAM. This is important for small-bar systems (on full-bar systems this gets turned into a noop). Note1: System memory can be used as an extra placement if the kernel should spill the allocation to system memory, if space can’t be made available in the CPU accessible part of VRAM (giving the same behaviour as the i915 interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). Note2: For clear-color CCS surfaces the kernel needs to read the clear-color value stored in the buffer, and on discrete platforms we need to use VRAM for display surfaces, therefore the kernel requires setting this flag for such objects, otherwise an error is thrown on small-bar systems.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj&ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION`` - Allows userspace to hint that compression (CCS) should be disabled for the buffer being created. This can avoid unnecessary memory operations and CCS state management. On pre-Xe2 platforms, this flag is currently rejected as compression control is not supported via PAT index. On Xe2+ platforms, compression is controlled via PAT entries. If this flag is set, the driver will reject any VM bind that requests a PAT index enabling compression for this BO. h]h)}(hX``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION`` - Allows userspace to hint that compression (CCS) should be disabled for the buffer being created. This can avoid unnecessary memory operations and CCS state management. On pre-Xe2 platforms, this flag is currently rejected as compression control is not supported via PAT index. On Xe2+ platforms, compression is controlled via PAT entries. If this flag is set, the driver will reject any VM bind that requests a PAT index enabling compression for this BO.h](j)}(h)``DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION``h]h%DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubhX - Allows userspace to hint that compression (CCS) should be disabled for the buffer being created. This can avoid unnecessary memory operations and CCS state management. On pre-Xe2 platforms, this flag is currently rejected as compression control is not supported via PAT index. On Xe2+ platforms, compression is controlled via PAT entries. If this flag is set, the driver will reject any VM bind that requests a PAT index enabling compression for this BO.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM$hjMubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhM hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM+hjubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubh)}(h**Note**h]h)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM-hj۴hhubj )}(hhh](j)}(hOn dGPU platforms, there is currently no change in behavior with this flag, but future improvements may leverage it. The current benefit is primarily applicable to iGPU platforms. h](j)}(h@On dGPU platforms, there is currently no change in behavior withh]h@On dGPU platforms, there is currently no change in behavior with}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM0hjubj()}(hhh]h)}(hrthis flag, but future improvements may leverage it. The current benefit is primarily applicable to iGPU platforms.h]hrthis flag, but future improvements may leverage it. The current benefit is primarily applicable to iGPU platforms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM/hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM0hjubj)}(hX**cpu_caching** supports the following values: - ``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM. - ``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this. h](j)}(h.**cpu_caching** supports the following values:h](h)}(h**cpu_caching**h]h cpu_caching}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh supports the following values:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM8hjubj()}(hhh]j )}(hhh](j )}(h``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM.h]h)}(h``DRM_XE_GEM_CPU_CACHING_WB`` - Allocate the pages with write-back caching. On iGPU this can't be used for scanout surfaces. Currently not allowed for objects placed in VRAM.h](j)}(h``DRM_XE_GEM_CPU_CACHING_WB``h]hDRM_XE_GEM_CPU_CACHING_WB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Allocate the pages with write-back caching. On iGPU this can’t be used for scanout surfaces. Currently not allowed for objects placed in VRAM.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM3hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this. h]h)}(h``DRM_XE_GEM_CPU_CACHING_WC`` - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this.h](j)}(h``DRM_XE_GEM_CPU_CACHING_WC``h]hDRM_XE_GEM_CPU_CACHING_WC}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubh - Allocate the pages as write-combined. This is uncached. Scanout surfaces should likely use this. All objects that can be placed in VRAM must use this.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM6hj&ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhM3hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM8hjubeh}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubh)}(hThis ioctl supports setting the following properties via the ``DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY`` extension, which uses the generic **drm_xe_ext_set_property** struct:h](h=This ioctl supports setting the following properties via the }(hjehhhNhNubj)}(h,``DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY``h]h(DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh# extension, which uses the generic }(hjehhhNhNubh)}(h**drm_xe_ext_set_property**h]hdrm_xe_ext_set_property}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjeubh struct:}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM:hj۴hhubj)}(hX=- ``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected. h]j )}(hhh]j )}(hX-``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected. h]h)}(hX)``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. Objects used with session of type ``DRM_XE_PXP_TYPE_HWDRM`` will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected.h](j)}(h+``DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE``h]h'DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhw - set the type of PXP session this object will be used with. Valid values are listed in enum drm_xe_pxp_session_type. }(hjhhhNhNubj)}(h``DRM_XE_PXP_TYPE_NONE``h]hDRM_XE_PXP_TYPE_NONE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhh is the default behavior, so there is no need to explicitly set that. Objects used with session of type }(hjhhhNhNubj)}(h``DRM_XE_PXP_TYPE_HWDRM``h]hDRM_XE_PXP_TYPE_HWDRM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh will be marked as invalid if a PXP invalidation event occurs after their creation. Attempting to flip an invalid object will cause a black frame to be displayed instead. Submissions with invalid objects mapped in the VM will be rejected.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM>hjubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]j) j* uh1j hjhM>hjubah}(h]h ]h"]h$]h&]uh1jhjhM>hj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_xe_gem_mmap_offset (C struct)c.drm_xe_gem_mmap_offsethNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_gem_mmap_offseth]j)}(hstruct drm_xe_gem_mmap_offseth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMJubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhjhMJubj)}(hdrm_xe_gem_mmap_offseth]j)}(hj h]hdrm_xe_gem_mmap_offset}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj hhhjhMJubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMJubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMJhjhhubj))}(hhh]h)}(h/Input of :c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET`h](h Input of }(hjQhhhNhNubh)}(h&:c:type:`DRM_IOCTL_XE_GEM_MMAP_OFFSET`h]j)}(hj[h]hDRM_IOCTL_XE_GEM_MMAP_OFFSET}(hj]hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jj sbc.drm_xe_gem_mmap_offsetasbj) DRM_IOCTL_XE_GEM_MMAP_OFFSETuh1hhjhKhjQubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjNhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMJubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``handle`` Handle for the object being mapped. ``flags`` Flags ``offset`` The fake offset to use for subsequent mmap call ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hstruct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; };h]hstruct drm_xe_gem_mmap_offset { __u64 extensions; __u32 handle; #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0); __u32 flags; __u64 offset; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]j)}(hjh]hhandle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMhj3ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj2hMhjubj)}(h``flags`` Flags h](j)}(h ``flags``h]j)}(hjVh]hflags}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjPubj()}(hhh]h)}(hFlagsh]hFlags}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhMhjlubah}(h]h ]h"]h$]h&]uh1j'hjPubeh}(h]h ]h"]h$]h&]uh1jhjkhMhjubj)}(h;``offset`` The fake offset to use for subsequent mmap call h](j)}(h ``offset``h]j)}(hjh]hoffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj )}(hhh]j)}(hXUThe **flags** can be: - ``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction. h](j)}(hThe **flags** can be:h](hThe }(hj(hhhNhNubh)}(h **flags**h]hflags}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh can be:}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj$ubj()}(hhh]j )}(hhh]j )}(hX5``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction. h]h)}(hX4``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER`` - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction.h](j)}(h'``DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER``h]h#DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubhX  - For user to query special offset for use in mmap ioctl. Writing to the returned mmap address will generate a PCI memory barrier with low overhead (avoiding IOCTL call as well as writing to VRAM which would also add overhead), acting like an MI_MEM_FENCE instruction.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjOubah}(h]h ]h"]h$]h&]uh1j hjLubah}(h]h ]h"]h$]h&]j) j* uh1j hjohMhjIubah}(h]h ]h"]h$]h&]uh1j'hj$ubeh}(h]h ]h"]h$]h&]uh1jhjHhMhj!ubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubh)}(h**Note**h]h)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hX5The mmap size can be at most 4K, due to HW limitations. As a result this interface is only supported on CPU architectures that support 4K page size. The mmap_offset ioctl will detect this and gracefully return an error, where userspace is expected to have a different fallback method for triggering a barrier.h]hX5The mmap size can be at most 4K, due to HW limitations. As a result this interface is only supported on CPU architectures that support 4K page size. The mmap_offset ioctl will detect this and gracefully return an error, where userspace is expected to have a different fallback method for triggering a barrier.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(h&Roughly the usage would be as follows:h]h&Roughly the usage would be as follows:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubjt)}(hXstruct drm_xe_gem_mmap_offset mmo = { .handle = 0, // must be set to 0 .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, }; err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); map[i] = 0xdeadbeaf; // issue barrierh]hXstruct drm_xe_gem_mmap_offset mmo = { .handle = 0, // must be set to 0 .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, }; err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); map[i] = 0xdeadbeaf; // issue barrier}hjsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_vm_create (C struct)c.drm_xe_vm_createhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_vm_createh]j)}(hstruct drm_xe_vm_createh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_vm_createh]j)}(hjh]hdrm_xe_vm_create}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h)Input of :c:type:`DRM_IOCTL_XE_VM_CREATE`h](h Input of }(hj/hhhNhNubh)}(h :c:type:`DRM_IOCTL_XE_VM_CREATE`h]j)}(hj9h]hDRM_IOCTL_XE_VM_CREATE}(hj;hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjsbc.drm_xe_vm_createasbj) DRM_IOCTL_XE_VM_CREATEuh1hhjhKhj/ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj,hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjmjLjmjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3); __u32 flags; __u32 vm_id; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``flags`` Flags ``vm_id`` Returned VM ID ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuubh:}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjqubjt)}(hXSstruct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3); __u32 flags; __u32 vm_id; __u64 reserved[2]; };h]hXSstruct drm_xe_vm_create { __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0); #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1); #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2); #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3); __u32 flags; __u32 vm_id; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjqubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjqubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``flags`` Flags h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hFlagsh]hFlags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``vm_id`` Returned VM ID h](j)}(h ``vm_id``h]j)}(hj4h]hvm_id}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj.ubj()}(hhh]h)}(hReturned VM IDh]hReturned VM ID}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMhjJubah}(h]h ]h"]h$]h&]uh1j'hj.ubeh}(h]h ]h"]h$]h&]uh1jhjIhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjmh]hreserved}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjgubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjgubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj )}(hhh]j)}(hXThe **flags** can be: - ``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception of on x2 and xe3 platform. - ``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device. - ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this. - ``DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT`` - Requires also DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit but only during a :c:type:`DRM_IOCTL_XE_VM_BIND` operation with the ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` flag set. This may be useful for user-space naively probing the amount of available memory. h](j)}(hThe **flags** can be:h](hThe }(hjhhhNhNubh)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]j )}(hhh](j )}(hX``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception of on x2 and xe3 platform.h]h)}(hX``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE`` - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the ``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` flag, with an exception of on x2 and xe3 platform.h](j)}(h&``DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE``h]h"DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Map the whole virtual address space of the VM to scratch page. A vm_bind would overwrite the scratch page mapping. This flag is mutually exclusive with the }(hjhhhNhNubj)}(h$``DRM_XE_VM_CREATE_FLAG_FAULT_MODE``h]h DRM_XE_VM_CREATE_FLAG_FAULT_MODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh3 flag, with an exception of on x2 and xe3 platform.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.h]h)}(hX``DRM_XE_VM_CREATE_FLAG_LR_MODE`` - An LR, or Long Running VM accepts exec submissions to its exec_queues that don't have an upper time limit on the job execution time. But exec submissions to these don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.h](j)}(h!``DRM_XE_VM_CREATE_FLAG_LR_MODE``h]hDRM_XE_VM_CREATE_FLAG_LR_MODE}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubhX - An LR, or Long Running VM accepts exec submissions to its exec_queues that don’t have an upper time limit on the job execution time. But exec submissions to these don’t allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. LR VMs can be created in recoverable page-fault mode using DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. If that flag is omitted, the UMD can not rely on the slightly different per-VM overcommit semantics that are enabled by DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may still enable recoverable pagefaults if supported by the device.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj-ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this.h]h)}(hX``DRM_XE_VM_CREATE_FLAG_FAULT_MODE`` - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this.h](j)}(h$``DRM_XE_VM_CREATE_FLAG_FAULT_MODE``h]h DRM_XE_VM_CREATE_FLAG_FAULT_MODE}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh - Requires also DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on demand when accessed, and also allows per-VM overcommit of memory. The xe driver internally uses recoverable pagefaults to implement this.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjTubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hXC``DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT`` - Requires also DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit but only during a :c:type:`DRM_IOCTL_XE_VM_BIND` operation with the ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` flag set. This may be useful for user-space naively probing the amount of available memory. h]h)}(hX?``DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT`` - Requires also DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit but only during a :c:type:`DRM_IOCTL_XE_VM_BIND` operation with the ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` flag set. This may be useful for user-space naively probing the amount of available memory.h](j)}(h*``DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT``h]h&DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhf - Requires also DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit but only during a }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]j)}(hjh]hDRM_IOCTL_XE_VM_BIND}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_VM_BINDuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh operation with the }(hjhhhNhNubj)}(h!``DRM_XE_VM_BIND_FLAG_IMMEDIATE``h]hDRM_XE_VM_BIND_FLAG_IMMEDIATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh\ flag set. This may be useful for user-space naively probing the amount of available memory.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhj{ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hj&hMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_vm_destroy (C struct)c.drm_xe_vm_destroyhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_vm_destroyh]j)}(hstruct drm_xe_vm_destroyh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_vm_destroyh]j)}(hjh]hdrm_xe_vm_destroy}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h*Input of :c:type:`DRM_IOCTL_XE_VM_DESTROY`h](h Input of }(hjJhhhNhNubh)}(h!:c:type:`DRM_IOCTL_XE_VM_DESTROY`h]j)}(hjTh]hDRM_IOCTL_XE_VM_DESTROY}(hjVhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjsbc.drm_xe_vm_destroyasbj) DRM_IOCTL_XE_VM_DESTROYuh1hhjhKhjJubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjGhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(h**Definition**:: struct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; }; **Members** ``vm_id`` VM ID ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hTstruct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; };h]hTstruct drm_xe_vm_destroy { __u32 vm_id; __u32 pad; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h``vm_id`` VM ID h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hVM IDh]hVM ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hMhj,ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj+hMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjOh]hreserved}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjIubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjeubah}(h]h ]h"]h$]h&]uh1j'hjIubeh}(h]h ]h"]h$]h&]uh1jhjdhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_vm_bind_op (C struct)c.drm_xe_vm_bind_ophNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_vm_bind_oph]j)}(hstruct drm_xe_vm_bind_oph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_vm_bind_oph]j)}(hjh]hdrm_xe_vm_bind_op}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(hrun bind operationsh]hrun bind operations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6); #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7); __u32 flags; #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``obj`` GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP ``pat_index`` The platform defined **pat_index** to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE. For coherency the **pat_index** needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the **pat_index** and reject if there is a mismatch (see note below for pre-MTL platforms). Note: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It's only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms: ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY In practice UC/WC/WT should only ever used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible. Note: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**. Starting from NVL-P, for userptr, svm, madvise and externally imported dma-buf the kernel expects either 2WAY or 1WAY and XA **pat_index**. For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped. ``pad`` MBZ ``{unnamed_union}`` anonymous ``obj_offset`` Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind ``userptr`` user pointer to bind on ``cpu_addr_mirror_offset`` Offset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported). ``range`` Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL ``addr`` Address to operate on, MBZ for UNMAP_ALL ``op`` Bind operation to perform ``flags`` Bind flags ``prefetch_mem_region_instance`` Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation. ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hXstruct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6); #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7); __u32 flags; #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; };h]hXstruct drm_xe_vm_bind_op { __u64 extensions; __u32 obj; __u16 pat_index; __u16 pad; union { __u64 obj_offset; __u64 userptr; __s64 cpu_addr_mirror_offset; }; __u64 range; __u64 addr; #define DRM_XE_VM_BIND_OP_MAP 0x0; #define DRM_XE_VM_BIND_OP_UNMAP 0x1; #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2; #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3; #define DRM_XE_VM_BIND_OP_PREFETCH 0x4; __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0); #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1); #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2); #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3); #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4); #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5); #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6); #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7); __u32 flags; #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1; __u32 prefetch_mem_region_instance; __u32 pad2; __u64 reserved[3]; };}hj(sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hj9h]hMembers}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM"hjubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjXh]h extensions}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM6hjRubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhM6hjnubah}(h]h ]h"]h$]h&]uh1j'hjRubeh}(h]h ]h"]h$]h&]uh1jhjmhM6hjOubj)}(hE``obj`` GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP h](j)}(h``obj``h]j)}(hjh]hobj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM:hjubj()}(hhh]h)}(h COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY In practice UC/WC/WT should only ever used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible. Note: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**. Starting from NVL-P, for userptr, svm, madvise and externally imported dma-buf the kernel expects either 2WAY or 1WAY and XA **pat_index**. For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped. h](j)}(h ``pat_index``h]j)}(hjh]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhjubj()}(hhh](h)}(hXaThe platform defined **pat_index** to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE.h](hThe platform defined }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhX? to use for this mapping. The index basically maps to some predefined memory attributes, including things like caching, coherency, compression etc. The exact meaning of the pat_index is platform specific and defined in the Bspec and PRMs. When the KMD sets up the binding the index here is encoded into the ppGTT PTE.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM?hjubh)}(hX For coherency the **pat_index** needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the **pat_index** and reject if there is a mismatch (see note below for pre-MTL platforms).h](hFor coherency the }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh needs to be at least 1way coherent when drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD will extract the coherency mode from the }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhJ and reject if there is a mismatch (see note below for pre-MTL platforms).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMFhjubh)}(hXNote: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It's only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms:h]hXNote: On pre-MTL platforms there is only a caching mode and no explicit coherency mode, but on such hardware there is always a shared-LLC (or is dgpu) so all GT memory accesses are coherent with CPU caches even with the caching mode set as uncached. It’s only the display engine that is incoherent (on dgpu it must be in VRAM which is always mapped as WC on the CPU). However to keep the uapi somewhat consistent with newer platforms the KMD groups the different cache levels into the following coherency buckets on all pre-MTL platforms:}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMKhjubj)}(h]ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY h]h)}(h\ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAYh]h\ppGTT UC -> COH_NONE ppGTT WC -> COH_NONE ppGTT WT -> COH_NONE ppGTT WB -> COH_AT_LEAST_1WAY}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMThjFubah}(h]h ]h"]h$]h&]uh1jhjXhMThjubh)}(hXIn practice UC/WC/WT should only ever used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the **pat_index**, where incoherent GT access is possible.h](hXuIn practice UC/WC/WT should only ever used for scanout surfaces on such platforms (or perhaps in general for dma-buf if shared with another device) since it is only the display engine that is actually incoherent. Everything else should typically use WB given that we have a shared-LLC. On MTL+ this completely changes and the HW defines the coherency mode as part of the }(hj_hhhNhNubh)}(h **pat_index**h]h pat_index}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_ubh), where incoherent GT access is possible.}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMYhjubh)}(hNote: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the **pat_index**. Starting from NVL-P, for userptr, svm, madvise and externally imported dma-buf the kernel expects either 2WAY or 1WAY and XA **pat_index**.h](haNote: For userptr and externally imported dma-buf the kernel expects either 1WAY or 2WAY for the }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh. Starting from NVL-P, for userptr, svm, madvise and externally imported dma-buf the kernel expects either 2WAY or 1WAY and XA }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMahjubh)}(hXFor DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the **pat_index**. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped.h](hKFor DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions on the }(hjhhhNhNubh)}(h **pat_index**h]h pat_index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhXS. For such mappings there is no actual memory being mapped (the address in the PTE is invalid), so the various PAT memory attributes likely do not apply. Simply leaving as zero is one option (still a valid pat_index). Same applies to DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping there is no actual memory being mapped.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMfhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMlhjOubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMphjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMphjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMphjOubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjh]h{unnamed_union}}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj()}(hhh]h)}(h anonymoush]h anonymous}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hKhj5ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj4hKhjOubj)}(hO``obj_offset`` Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind h](j)}(h``obj_offset``h]j)}(hjXh]h obj_offset}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMvhjRubj()}(hhh]h)}(h?Offset into the object, MBZ for CLEAR_RANGE, ignored for unbindh]h?Offset into the object, MBZ for CLEAR_RANGE, ignored for unbind}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMuhjnubah}(h]h ]h"]h$]h&]uh1j'hjRubeh}(h]h ]h"]h$]h&]uh1jhjmhMvhjOubj)}(h$``userptr`` user pointer to bind on h](j)}(h ``userptr``h]j)}(hjh]huserptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMzhjubj()}(hhh]h)}(huser pointer to bind onh]huser pointer to bind on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMzhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMzhjOubj)}(h``cpu_addr_mirror_offset`` Offset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported). h](j)}(h``cpu_addr_mirror_offset``h]j)}(hjh]hcpu_addr_mirror_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hOffset from GPU **addr** to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported).h](hOffset from GPU }(hjhhhNhNubh)}(h**addr**h]haddr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh to create CPU address mirror mappings. MBZ with current level of support (e.g. 1 to 1 mapping between GPU and CPU mappings only supported).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(hM``range`` Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL h](j)}(h ``range``h]j)}(hjh]hrange}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hBNumber of bytes from the object to bind to addr, MBZ for UNMAP_ALLh]hBNumber of bytes from the object to bind to addr, MBZ for UNMAP_ALL}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMhj-ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj,hMhjOubj)}(h2``addr`` Address to operate on, MBZ for UNMAP_ALL h](j)}(h``addr``h]j)}(hjPh]haddr}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjJubj()}(hhh]h)}(h(Address to operate on, MBZ for UNMAP_ALLh]h(Address to operate on, MBZ for UNMAP_ALL}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMhjfubah}(h]h ]h"]h$]h&]uh1j'hjJubeh}(h]h ]h"]h$]h&]uh1jhjehMhjOubj)}(h!``op`` Bind operation to perform h](j)}(h``op``h]j)}(hjh]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hBind operation to performh]hBind operation to perform}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(h``flags`` Bind flags h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h Bind flagsh]h Bind flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(h``prefetch_mem_region_instance`` Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation. h](j)}(h ``prefetch_mem_region_instance``h]j)}(hjh]hprefetch_mem_region_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMemory region to prefetch VMA to. It is a region instance, not a mask. To be used only with ``DRM_XE_VM_BIND_OP_PREFETCH`` operation.h](h\Memory region to prefetch VMA to. It is a region instance, not a mask. To be used only with }(hjhhhNhNubj)}(h``DRM_XE_VM_BIND_OP_PREFETCH``h]hDRM_XE_VM_BIND_OP_PREFETCH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh operation.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjGh]hpad2}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjAubj()}(hhh]h)}(hMBZh]hMBZ}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMhj]ubah}(h]h ]h"]h$]h&]uh1j'hjAubeh}(h]h ]h"]h$]h&]uh1jhj\hMhjOubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjzubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjzubeh}(h]h ]h"]h$]h&]uh1jhjhMhjOubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj )}(hhh](j)}(hThe **op** can be: - ``DRM_XE_VM_BIND_OP_MAP`` - ``DRM_XE_VM_BIND_OP_UNMAP`` - ``DRM_XE_VM_BIND_OP_MAP_USERPTR`` - ``DRM_XE_VM_BIND_OP_UNMAP_ALL`` - ``DRM_XE_VM_BIND_OP_PREFETCH`` h](j)}(hThe **op** can be:h](hThe }(hjhhhNhNubh)}(h**op**h]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]j )}(hhh](j )}(h``DRM_XE_VM_BIND_OP_MAP``h]h)}(hj h]j)}(hj h]hDRM_XE_VM_BIND_OP_MAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_VM_BIND_OP_UNMAP``h]h)}(hj*h]j)}(hj*h]hDRM_XE_VM_BIND_OP_UNMAP}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h!``DRM_XE_VM_BIND_OP_MAP_USERPTR``h]h)}(hjKh]j)}(hjKh]hDRM_XE_VM_BIND_OP_MAP_USERPTR}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjIubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_VM_BIND_OP_UNMAP_ALL``h]h)}(hjlh]j)}(hjlh]hDRM_XE_VM_BIND_OP_UNMAP_ALL}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_VM_BIND_OP_PREFETCH`` h]h)}(h``DRM_XE_VM_BIND_OP_PREFETCH``h]j)}(hjh]hDRM_XE_VM_BIND_OP_PREFETCH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hj!hMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hXand the **flags** can be: - ``DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protection - ``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to. - ``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings. - ``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP. - ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. - ``DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET`` - Can be used in combination with ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` to reset madvises when the underlying CPU address space range is unmapped (typically with munmap(2) or brk(2)). The madvise values set with :c:type:`DRM_IOCTL_XE_MADVISE` are reset to the values that were present immediately after the :c:type:`DRM_IOCTL_XE_VM_BIND`. The reset GPU virtual address range is the intersection of the range bound using :c:type:`DRM_IOCTL_XE_VM_BIND` and the virtual CPU address space range unmapped. This functionality is present to mimic the behaviour of CPU address space madvises set using madvise(2), which are typically reset on unmap. h](j)}(hand the **flags** can be:h](hand the }(hjhhhNhNubh)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM"hjubj()}(hhh]j )}(hhh](j )}(h```DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protectionh]h)}(h```DRM_XE_VM_BIND_FLAG_READONLY`` - Setup the page tables as read-only to ensure write protectionh](j)}(h ``DRM_XE_VM_BIND_FLAG_READONLY``h]hDRM_XE_VM_BIND_FLAG_READONLY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh@ - Setup the page tables as read-only to ensure write protection}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.h]h)}(h``DRM_XE_VM_BIND_FLAG_IMMEDIATE`` - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.h](j)}(h!``DRM_XE_VM_BIND_FLAG_IMMEDIATE``h]hDRM_XE_VM_BIND_FLAG_IMMEDIATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - On a faulting VM, do the MAP operation immediately rather than deferring the MAP to the page fault handler. This is implied on a non-faulting VM as there is no fault handler to defer to.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX\``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.h]h)}(hX\``DRM_XE_VM_BIND_FLAG_NULL`` - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.h](j)}(h``DRM_XE_VM_BIND_FLAG_NULL``h]hDRM_XE_VM_BIND_FLAG_NULL}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubhX@ - When the NULL flag is set, the page tables are setup with a special bit which indicates writes are dropped and all reads return zero. In the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ. This flag is intended to implement VK sparse bindings.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj7ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.h]h)}(h``DRM_XE_VM_BIND_FLAG_CHECK_PXP`` - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.h](j)}(h!``DRM_XE_VM_BIND_FLAG_CHECK_PXP``h]hDRM_XE_VM_BIND_FLAG_CHECK_PXP}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubh - If the object is encrypted via PXP, reject the binding if the encryption key is no longer valid. This flag has no effect on BOs that are not marked as using PXP.}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj^ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ.h]h)}(hX``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ.h](j)}(h'``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR``h]h#DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhXl - When the CPU address mirror flag is set, no mappings are created rather the range is reserved for CPU address mirroring which will be populated on GPU page faults or prefetches. Only valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO handle MBZ, and the BO offset MBZ.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX``DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET`` - Can be used in combination with ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` to reset madvises when the underlying CPU address space range is unmapped (typically with munmap(2) or brk(2)). The madvise values set with :c:type:`DRM_IOCTL_XE_MADVISE` are reset to the values that were present immediately after the :c:type:`DRM_IOCTL_XE_VM_BIND`. The reset GPU virtual address range is the intersection of the range bound using :c:type:`DRM_IOCTL_XE_VM_BIND` and the virtual CPU address space range unmapped. This functionality is present to mimic the behaviour of CPU address space madvises set using madvise(2), which are typically reset on unmap. h]h)}(hX``DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET`` - Can be used in combination with ``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR`` to reset madvises when the underlying CPU address space range is unmapped (typically with munmap(2) or brk(2)). The madvise values set with :c:type:`DRM_IOCTL_XE_MADVISE` are reset to the values that were present immediately after the :c:type:`DRM_IOCTL_XE_VM_BIND`. The reset GPU virtual address range is the intersection of the range bound using :c:type:`DRM_IOCTL_XE_VM_BIND` and the virtual CPU address space range unmapped. This functionality is present to mimic the behaviour of CPU address space madvises set using madvise(2), which are typically reset on unmap.h](j)}(h)``DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET``h]h%DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh# - Can be used in combination with }(hjhhhNhNubj)}(h'``DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR``h]h#DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh to reset madvises when the underlying CPU address space range is unmapped (typically with munmap(2) or brk(2)). The madvise values set with }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_MADVISE`h]j)}(hjh]hDRM_IOCTL_XE_MADVISE}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_MADVISEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubhA are reset to the values that were present immediately after the }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]j)}(hjh]hDRM_IOCTL_XE_VM_BIND}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_VM_BINDuh1hhjhMhjubhS. The reset GPU virtual address range is the intersection of the range bound using }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]j)}(hj!h]hDRM_IOCTL_XE_VM_BIND}(hj#hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_VM_BINDuh1hhjhMhjubh and the virtual CPU address space range unmapped. This functionality is present to mimic the behaviour of CPU address space madvises set using madvise(2), which are typically reset on unmap.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hj hMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM"hjubeh}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubh)}(h**Note**h]h)}(hjhh]hNote}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM$hj۴hhubj )}(hhh](j)}(hX'free(3) may or may not call munmap(2) and/or brk(2), and may thus not invoke autoreset. Neither will stack variables going out of scope. Therefore it's recommended to always explicitly reset the madvises when freeing the memory backing a region used in a :c:type:`DRM_IOCTL_XE_MADVISE` call. - ``DRM_XE_VM_BIND_FLAG_DECOMPRESS`` - Request on-device decompression for a MAP. When set on a MAP bind operation, request the driver schedule an on-device in-place decompression (via the migrate/resolve path) for the GPU mapping created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on other ops is rejected. The bind's pat_index must select the device's "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that support Flat CCS and the required HW generation XE2+. h](j)}(hAfree(3) may or may not call munmap(2) and/or brk(2), and may thush]hAfree(3) may or may not call munmap(2) and/or brk(2), and may thus}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM.hjubj()}(hhh](j)}(hnot invoke autoreset. Neither will stack variables going out of scope. Therefore it's recommended to always explicitly reset the madvises when freeing the memory backing a region used in a :c:type:`DRM_IOCTL_XE_MADVISE` call.h]h)}(hnot invoke autoreset. Neither will stack variables going out of scope. Therefore it's recommended to always explicitly reset the madvises when freeing the memory backing a region used in a :c:type:`DRM_IOCTL_XE_MADVISE` call.h](hnot invoke autoreset. Neither will stack variables going out of scope. Therefore it’s recommended to always explicitly reset the madvises when freeing the memory backing a region used in a }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_MADVISE`h]j)}(hjh]hDRM_IOCTL_XE_MADVISE}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_IOCTL_XE_MADVISEuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM%hjubh call.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhM%hjubah}(h]h ]h"]h$]h&]uh1jhjhM%hjubj )}(hhh]j )}(hX``DRM_XE_VM_BIND_FLAG_DECOMPRESS`` - Request on-device decompression for a MAP. When set on a MAP bind operation, request the driver schedule an on-device in-place decompression (via the migrate/resolve path) for the GPU mapping created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on other ops is rejected. The bind's pat_index must select the device's "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that support Flat CCS and the required HW generation XE2+. h]h)}(hX``DRM_XE_VM_BIND_FLAG_DECOMPRESS`` - Request on-device decompression for a MAP. When set on a MAP bind operation, request the driver schedule an on-device in-place decompression (via the migrate/resolve path) for the GPU mapping created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on other ops is rejected. The bind's pat_index must select the device's "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that support Flat CCS and the required HW generation XE2+.h](j)}(h"``DRM_XE_VM_BIND_FLAG_DECOMPRESS``h]hDRM_XE_VM_BIND_FLAG_DECOMPRESS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX - Request on-device decompression for a MAP. When set on a MAP bind operation, request the driver schedule an on-device in-place decompression (via the migrate/resolve path) for the GPU mapping created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on other ops is rejected. The bind’s pat_index must select the device’s “no-compression” PAT. Only meaningful for VRAM-backed BOs on devices that support Flat CCS and the required HW generation XE2+.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM(hjubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]j) j* uh1j hjhM(hjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM.hj~ubj)}(hThe **prefetch_mem_region_instance** for ``DRM_XE_VM_BIND_OP_PREFETCH`` can also be: - ``DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC``, which ensures prefetching occurs in the memory region advised by madvise. h](j)}(hTThe **prefetch_mem_region_instance** for ``DRM_XE_VM_BIND_OP_PREFETCH`` can also be:h](hThe }(hjhhhNhNubh)}(h **prefetch_mem_region_instance**h]hprefetch_mem_region_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh for }(hjhhhNhNubj)}(h``DRM_XE_VM_BIND_OP_PREFETCH``h]hDRM_XE_VM_BIND_OP_PREFETCH}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh can also be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM5hjubj()}(hhh]j )}(hhh]j )}(hu``DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC``, which ensures prefetching occurs in the memory region advised by madvise. h]h)}(hq``DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC``, which ensures prefetching occurs in the memory region advised by madvise.h](j)}(h&``DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC``h]h"DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubhK, which ensures prefetching occurs in the memory region advised by madvise.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM1hjLubah}(h]h ]h"]h$]h&]uh1j hjIubah}(h]h ]h"]h$]h&]j) j* uh1j hjlhM1hjFubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjEhM5hj~ubeh}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_vm_bind (C struct)c.drm_xe_vm_bindhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_vm_bindh]j)}(hstruct drm_xe_vm_bindh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM7ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM7ubj)}(hdrm_xe_vm_bindh]j)}(hjh]hdrm_xe_vm_bind}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhM7ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM7ubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM7hjhhubj))}(hhh]h)}(h'Input of :c:type:`DRM_IOCTL_XE_VM_BIND`h](h Input of }(hjhhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_VM_BIND`h]j)}(hjh]hDRM_IOCTL_XE_VM_BIND}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjsbc.drm_xe_vm_bindasbj) DRM_IOCTL_XE_VM_BINDuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhM7ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj$jLj$jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``vm_id`` The ID of the VM to bind to ``exec_queue_id`` exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used. ``pad`` MBZ ``num_binds`` number of binds in this IOCTL ``{unnamed_union}`` anonymous ``bind`` used if num_binds == 1 ``vector_of_binds`` userptr to array of struct drm_xe_vm_bind_op if num_binds > 1 ``pad2`` MBZ ``num_syncs`` amount of syncs to wait on ``syncs`` pointer to struct drm_xe_sync array ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,ubh:}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubjt)}(hX$struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; };h]hX$struct drm_xe_vm_bind { __u64 extensions; __u32 vm_id; __u32 exec_queue_id; __u32 pad; __u32 num_binds; union { struct drm_xe_vm_bind_op bind; __u64 vector_of_binds; }; __u32 pad2; __u32 num_syncs; __u64 syncs; __u64 reserved[2]; };}hjIsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubh)}(h **Members**h]h)}(hjZh]hMembers}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjyh]h extensions}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjsubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjsubeh}(h]h ]h"]h$]h&]uh1jhjhMhjpubj)}(h&``vm_id`` The ID of the VM to bind to h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hThe ID of the VM to bind toh]hThe ID of the VM to bind to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjpubj)}(h``exec_queue_id`` exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used. h](j)}(h``exec_queue_id``h]j)}(hjh]h exec_queue_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hexec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used.h]hexec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND and exec queue must have same vm_id. If zero, the default VM bind engine is used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjpubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj%h]hpad}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj;ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj:hMhjpubj)}(h,``num_binds`` number of binds in this IOCTL h](j)}(h ``num_binds``h]j)}(hj^h]h num_binds}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjXubj()}(hhh]h)}(hnumber of binds in this IOCTLh]hnumber of binds in this IOCTL}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMhjtubah}(h]h ]h"]h$]h&]uh1j'hjXubeh}(h]h ]h"]h$]h&]uh1jhjshMhjpubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj()}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjpubj)}(h ``bind`` used if num_binds == 1 h](j)}(h``bind``h]j)}(hjh]hbind}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hused if num_binds == 1h]hused if num_binds == 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjpubj)}(hR``vector_of_binds`` userptr to array of struct drm_xe_vm_bind_op if num_binds > 1 h](j)}(h``vector_of_binds``h]j)}(hj h]hvector_of_binds}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h=userptr to array of struct drm_xe_vm_bind_op if num_binds > 1h]h=userptr to array of struct drm_xe_vm_bind_op if num_binds > 1}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjpubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjCh]hpad2}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj=ubj()}(hhh]h)}(hMBZh]hMBZ}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhMhjYubah}(h]h ]h"]h$]h&]uh1j'hj=ubeh}(h]h ]h"]h$]h&]uh1jhjXhMhjpubj)}(h)``num_syncs`` amount of syncs to wait on h](j)}(h ``num_syncs``h]j)}(hj|h]h num_syncs}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjvubj()}(hhh]h)}(hamount of syncs to wait onh]hamount of syncs to wait on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjvubeh}(h]h ]h"]h$]h&]uh1jhjhMhjpubj)}(h.``syncs`` pointer to struct drm_xe_sync array h](j)}(h ``syncs``h]j)}(hjh]hsyncs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h#pointer to struct drm_xe_sync arrayh]h#pointer to struct drm_xe_sync array}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjpubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjpubeh}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj1h]h Description}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hBelow is an example of a minimal use of **drm_xe_vm_bind** to asynchronously bind the buffer `data` at address `BIND_ADDRESS` to illustrate `userptr`. It can be synchronized by using the example provided for **drm_xe_sync**.h](h(Below is an example of a minimal use of }(hjGhhhNhNubh)}(h**drm_xe_vm_bind**h]hdrm_xe_vm_bind}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh# to asynchronously bind the buffer }(hjGhhhNhNubji )}(h`data`h]hdata}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjGubh at address }(hjGhhhNhNubji )}(h`BIND_ADDRESS`h]h BIND_ADDRESS}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjGubh to illustrate }(hjGhhhNhNubji )}(h `userptr`h]huserptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh hjGubh;. It can be synchronized by using the example provided for }(hjGhhhNhNubh)}(h**drm_xe_sync**h]h drm_xe_sync}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubjt)}(hXdata = aligned_alloc(ALIGNMENT, BO_SIZE); struct drm_xe_vm_bind bind = { .vm_id = vm, .num_binds = 1, .bind.obj = 0, .bind.obj_offset = to_user_pointer(data), .bind.range = BO_SIZE, .bind.addr = BIND_ADDRESS, .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, .bind.flags = 0, .num_syncs = 1, .syncs = &sync, .exec_queue_id = 0, }; ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);h]hXdata = aligned_alloc(ALIGNMENT, BO_SIZE); struct drm_xe_vm_bind bind = { .vm_id = vm, .num_binds = 1, .bind.obj = 0, .bind.obj_offset = to_user_pointer(data), .bind.range = BO_SIZE, .bind.addr = BIND_ADDRESS, .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, .bind.flags = 0, .num_syncs = 1, .syncs = &sync, .exec_queue_id = 0, }; ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);}hjsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_xe_vm_get_property (C struct)c.drm_xe_vm_get_propertyhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_vm_get_propertyh]j)}(hstruct drm_xe_vm_get_propertyh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_vm_get_propertyh]j)}(hjh]hdrm_xe_vm_get_property}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h/Input of :c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY`h](h Input of }(hjhhhNhNubh)}(h&:c:type:`DRM_IOCTL_XE_VM_GET_PROPERTY`h]j)}(hj%h]hDRM_IOCTL_XE_VM_GET_PROPERTY}(hj'hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjsbc.drm_xe_vm_get_propertyasbj) DRM_IOCTL_XE_VM_GET_PROPERTYuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjYjLjYjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_vm_get_property { __u64 extensions; __u32 vm_id; #define DRM_XE_VM_GET_PROPERTY_FAULTS 0; __u32 property; __u32 size; __u32 pad; union { __u64 data; __u64 value; }; __u64 reserved[3]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``vm_id`` The ID of the VM to query the properties of ``property`` property to get ``size`` Size to allocate for **data** ``pad`` MBZ ``{unnamed_union}`` anonymous ``data`` Pointer to user-defined array of flexible size and type ``value`` Return value for scalar queries ``reserved`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaubh:}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj]ubjt)}(hXstruct drm_xe_vm_get_property { __u64 extensions; __u32 vm_id; #define DRM_XE_VM_GET_PROPERTY_FAULTS 0; __u32 property; __u32 size; __u32 pad; union { __u64 data; __u64 value; }; __u64 reserved[3]; };h]hXstruct drm_xe_vm_get_property { __u64 extensions; __u32 vm_id; #define DRM_XE_VM_GET_PROPERTY_FAULTS 0; __u32 property; __u32 size; __u32 pad; union { __u64 data; __u64 value; }; __u64 reserved[3]; };}hj~sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj]ubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM(hj]ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM/hjubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM/hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM/hjubj)}(h6``vm_id`` The ID of the VM to query the properties of h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM2hjubj()}(hhh]h)}(h+The ID of the VM to query the properties ofh]h+The ID of the VM to query the properties of}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM2hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM2hjubj)}(h``property`` property to get h](j)}(h ``property``h]j)}(hj h]hproperty}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM6hjubj()}(hhh]h)}(hproperty to geth]hproperty to get}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hM6hj6ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj5hM6hjubj)}(h'``size`` Size to allocate for **data** h](j)}(h``size``h]j)}(hjYh]hsize}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM9hjSubj()}(hhh]h)}(hSize to allocate for **data**h](hSize to allocate for }(hjrhhhNhNubh)}(h**data**h]hdata}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrubeh}(h]h ]h"]h$]h&]uh1hhjnhM9hjoubah}(h]h ]h"]h$]h&]uh1j'hjSubeh}(h]h ]h"]h$]h&]uh1jhjnhM9hjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM<hjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM<hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM<hjubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjubj()}(hhh]h)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hA``data`` Pointer to user-defined array of flexible size and type h](j)}(h``data``h]j)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM@hj ubj()}(hhh]h)}(h7Pointer to user-defined array of flexible size and typeh]h7Pointer to user-defined array of flexible size and type}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM@hj(ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj'hM@hjubj)}(h*``value`` Return value for scalar queries h](j)}(h ``value``h]j)}(hjKh]hvalue}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMBhjEubj()}(hhh]h)}(hReturn value for scalar queriesh]hReturn value for scalar queries}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hMBhjaubah}(h]h ]h"]h$]h&]uh1j'hjEubeh}(h]h ]h"]h$]h&]uh1jhj`hMBhjubj)}(h``reserved`` MBZh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMEhj~ubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMFhjubah}(h]h ]h"]h$]h&]uh1j'hj~ubeh}(h]h ]h"]h$]h&]uh1jhjhMEhjubeh}(h]h ]h"]h$]h&]uh1j hj]ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMIhj۴hhubh)}(hThe user provides a VM and a property to query among DRM_XE_VM_GET_PROPERTY_*, and sets the values in the vm_id and property members, respectively. This determines both the VM to get the property of, as well as the property to report.h]hThe user provides a VM and a property to query among DRM_XE_VM_GET_PROPERTY_*, and sets the values in the vm_id and property members, respectively. This determines both the VM to get the property of, as well as the property to report.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hXIf size is set to 0, the driver fills it with the required size for the requested property. The user is expected here to allocate memory for the property structure and to provide a pointer to the allocated memory using the data member. For some properties, this may be zero, in which case, the value of the property will be saved to the value member and size will remain zero on return.h]hXIf size is set to 0, the driver fills it with the required size for the requested property. The user is expected here to allocate memory for the property structure and to provide a pointer to the allocated memory using the data member. For some properties, this may be zero, in which case, the value of the property will be saved to the value member and size will remain zero on return.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(heIf size is not zero, then the IOCTL will attempt to copy the requested property into the data member.h]heIf size is not zero, then the IOCTL will attempt to copy the requested property into the data member.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM!hj۴hhubh)}(hXThe IOCTL will return -ENOENT if the VM could not be identified from the provided VM ID, or -EINVAL if the IOCTL fails for any other reason, such as providing an invalid size for the given property or if the property data could not be copied to the memory allocated to the data member.h]hXThe IOCTL will return -ENOENT if the VM could not be identified from the provided VM ID, or -EINVAL if the IOCTL fails for any other reason, such as providing an invalid size for the given property or if the property data could not be copied to the memory allocated to the data member.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM$hj۴hhubj )}(hhh]j)}(hCThe property member can be: - ``DRM_XE_VM_GET_PROPERTY_FAULTS`` h](j)}(hThe property member can be:h]hThe property member can be:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM-hjubj()}(hhh]j )}(hhh]j )}(h%``DRM_XE_VM_GET_PROPERTY_FAULTS`` h]h)}(h!``DRM_XE_VM_GET_PROPERTY_FAULTS``h]j)}(hj;h]hDRM_XE_VM_GET_PROPERTY_FAULTS}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM*hj5ubah}(h]h ]h"]h$]h&]uh1j hj2ubah}(h]h ]h"]h$]h&]j) j* uh1j hjPhM*hj/ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj.hM-hjubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_xe_exec_queue_create (C struct)c.drm_xe_exec_queue_createhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_exec_queue_createh]j)}(hstruct drm_xe_exec_queue_createh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM/ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM/ubj)}(hdrm_xe_exec_queue_createh]j)}(hjh]hdrm_xe_exec_queue_create}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhM/ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM/ubah}(h]j{ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhM/hj}hhubj))}(hhh]h)}(h1Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h](h Input of }(hjhhhNhNubh)}(h(:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_CREATE`h]j)}(hjh]hDRM_IOCTL_XE_EXEC_QUEUE_CREATE}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjsbc.drm_xe_exec_queue_createasbj) DRM_IOCTL_XE_EXEC_QUEUE_CREATEuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMJhjhhubah}(h]h ]h"]h$]h&]uh1j(hj}hhhjhM/ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4; #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63); #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5; #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``width`` submission width (number BB per exec) for this exec queue ``num_placements`` number of valid placements for this exec queue ``vm_id`` VM to use for this exec queue ``flags`` flags to use for this exec queue ``exec_queue_id`` Returned exec queue ID ``instances`` user pointer to a 2-d array of struct drm_xe_engine_class_instance length = width (i) * num_placements (j) index = j + i * width ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMNhj ubjt)}(hXZstruct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4; #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63); #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5; #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; };h]hXZstruct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2; #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3; #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4; #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63); #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5; #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6; __u64 extensions; __u16 width; __u16 num_placements; __u32 vm_id; #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0); __u32 flags; __u32 exec_queue_id; __u64 instances; __u64 reserved[2]; };}hj-sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMPhj ubh)}(h **Members**h]h)}(hj>h]hMembers}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMehj ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj]h]h extensions}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjWubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjsubah}(h]h ]h"]h$]h&]uh1j'hjWubeh}(h]h ]h"]h$]h&]uh1jhjrhMhjTubj)}(hD``width`` submission width (number BB per exec) for this exec queue h](j)}(h ``width``h]j)}(hjh]hwidth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h9submission width (number BB per exec) for this exec queueh]h9submission width (number BB per exec) for this exec queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjTubj)}(hB``num_placements`` number of valid placements for this exec queue h](j)}(h``num_placements``h]j)}(hjh]hnum_placements}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h.number of valid placements for this exec queueh]h.number of valid placements for this exec queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjTubj)}(h(``vm_id`` VM to use for this exec queue h](j)}(h ``vm_id``h]j)}(hjh]hvm_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hVM to use for this exec queueh]hVM to use for this exec queue}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjTubj)}(h+``flags`` flags to use for this exec queue h](j)}(h ``flags``h]j)}(hjAh]hflags}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj;ubj()}(hhh]h)}(h flags to use for this exec queueh]h flags to use for this exec queue}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhMhjWubah}(h]h ]h"]h$]h&]uh1j'hj;ubeh}(h]h ]h"]h$]h&]uh1jhjVhMhjTubj)}(h)``exec_queue_id`` Returned exec queue ID h](j)}(h``exec_queue_id``h]j)}(hjzh]h exec_queue_id}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjtubj()}(hhh]h)}(hReturned exec queue IDh]hReturned exec queue ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjtubeh}(h]h ]h"]h$]h&]uh1jhjhMhjTubj)}(h``instances`` user pointer to a 2-d array of struct drm_xe_engine_class_instance length = width (i) * num_placements (j) index = j + i * width h](j)}(h ``instances``h]j)}(hjh]h instances}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh](h)}(hBuser pointer to a 2-d array of struct drm_xe_engine_class_instanceh]hBuser pointer to a 2-d array of struct drm_xe_engine_class_instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h=length = width (i) * num_placements (j) index = j + i * widthh]h=length = width (i) * num_placements (j) index = j + i * width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjTubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjTubeh}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj?h]h Description}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(hThis ioctl supports setting the following properties via the ``DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY`` extension, which uses the generic **drm_xe_ext_set_property** struct:h](h=This ioctl supports setting the following properties via the }(hjUhhhNhNubj)}(h,``DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY``h]h(DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubh# extension, which uses the generic }(hjUhhhNhNubh)}(h**drm_xe_ext_set_property**h]hdrm_xe_ext_set_property}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUubh struct:}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMKhj۴hhubj)}(hX- ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP`` - Create a multi-queue group or add secondary queues to a multi-queue group. If the extension's 'value' field has ``DRM_XE_MULTI_GROUP_CREATE`` flag set, then a new multi-queue group is created with this queue as the primary queue (Q0). Otherwise, the queue gets added to the multi-queue group whose primary queue's exec_queue_id is specified in the lower 32 bits of the 'value' field. All the other non-relevant bits of extension's 'value' field while adding the primary or the secondary queues of the group must be set to 0. - ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY`` - Set the queue priority within the multi-queue group. Current valid priority values are 0–2 (default is 1), with higher values indicating higher priority. - ``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX`` - Set the queue to enable render color cache keying on BTP+BTI instead of just BTI (only valid for render queues). h]j )}(hhh](j )}(h{``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal.h]h)}(h{``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY`` - set the queue priority. CAP_SYS_NICE is required to set a value above normal.h](j)}(h+``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY``h]h'DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhP - set the queue priority. CAP_SYS_NICE is required to set a value above normal.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMOhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h```DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds.h]h)}(h```DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE`` - set the queue timeslice duration in microseconds.h](j)}(h,``DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE``h]h(DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh4 - set the queue timeslice duration in microseconds.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMQhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs.h]h)}(hX``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE`` - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. ``DRM_XE_PXP_TYPE_NONE`` is the default behavior, so there is no need to explicitly set that. When a queue of type ``DRM_XE_PXP_TYPE_HWDRM`` is created, the PXP default HWDRM session (``XE_PXP_HWDRM_DEFAULT_SESSION``) will be started, if isn't already running. The user is expected to query the PXP status via the query ioctl (see ``DRM_XE_DEVICE_QUERY_PXP_STATUS``) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs.h](j)}(h+``DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE``h]h'DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhv - set the type of PXP session this queue will be used with. Valid values are listed in enum drm_xe_pxp_session_type. }(hjhhhNhNubj)}(h``DRM_XE_PXP_TYPE_NONE``h]hDRM_XE_PXP_TYPE_NONE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh[ is the default behavior, so there is no need to explicitly set that. When a queue of type }(hjhhhNhNubj)}(h``DRM_XE_PXP_TYPE_HWDRM``h]hDRM_XE_PXP_TYPE_HWDRM}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, is created, the PXP default HWDRM session (}(hjhhhNhNubj)}(h ``XE_PXP_HWDRM_DEFAULT_SESSION``h]hXE_PXP_HWDRM_DEFAULT_SESSION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhu) will be started, if isn’t already running. The user is expected to query the PXP status via the query ioctl (see }(hjhhhNhNubj)}(h"``DRM_XE_DEVICE_QUERY_PXP_STATUS``h]hDRM_XE_DEVICE_QUERY_PXP_STATUS}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX) and to wait for PXP to be ready before attempting to create a queue with this property. When a queue is created before PXP is ready, the ioctl will return -EBUSY if init is still in progress or -EIO if init failed. Given that going into a power-saving state kills PXP HWDRM sessions, runtime PM will be blocked while queues of this type are alive. All PXP queues will be killed if a PXP invalidation event occurs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMShjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hX=``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP`` - Create a multi-queue group or add secondary queues to a multi-queue group. If the extension's 'value' field has ``DRM_XE_MULTI_GROUP_CREATE`` flag set, then a new multi-queue group is created with this queue as the primary queue (Q0). Otherwise, the queue gets added to the multi-queue group whose primary queue's exec_queue_id is specified in the lower 32 bits of the 'value' field. All the other non-relevant bits of extension's 'value' field while adding the primary or the secondary queues of the group must be set to 0.h]h)}(hX=``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP`` - Create a multi-queue group or add secondary queues to a multi-queue group. If the extension's 'value' field has ``DRM_XE_MULTI_GROUP_CREATE`` flag set, then a new multi-queue group is created with this queue as the primary queue (Q0). Otherwise, the queue gets added to the multi-queue group whose primary queue's exec_queue_id is specified in the lower 32 bits of the 'value' field. All the other non-relevant bits of extension's 'value' field while adding the primary or the secondary queues of the group must be set to 0.h](j)}(h.``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP``h]h*DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubhy - Create a multi-queue group or add secondary queues to a multi-queue group. If the extension’s ‘value’ field has }(hjPhhhNhNubj)}(h``DRM_XE_MULTI_GROUP_CREATE``h]hDRM_XE_MULTI_GROUP_CREATE}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubhX flag set, then a new multi-queue group is created with this queue as the primary queue (Q0). Otherwise, the queue gets added to the multi-queue group whose primary queue’s exec_queue_id is specified in the lower 32 bits of the ‘value’ field. All the other non-relevant bits of extension’s ‘value’ field while adding the primary or the secondary queues of the group must be set to 0.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMahjLubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY`` - Set the queue priority within the multi-queue group. Current valid priority values are 0–2 (default is 1), with higher values indicating higher priority.h]h)}(h``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY`` - Set the queue priority within the multi-queue group. Current valid priority values are 0–2 (default is 1), with higher values indicating higher priority.h](j)}(h7``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY``h]h3DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Set the queue priority within the multi-queue group. Current valid priority values are 0–2 (default is 1), with higher values indicating higher priority.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMihjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX`` - Set the queue to enable render color cache keying on BTP+BTI instead of just BTI (only valid for render queues). h]h)}(h``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX`` - Set the queue to enable render color cache keying on BTP+BTI instead of just BTI (only valid for render queues).h](j)}(h6``DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX``h]h2DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhs - Set the queue to enable render color cache keying on BTP+BTI instead of just BTI (only valid for render queues).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhMOhjubah}(h]h ]h"]h$]h&]uh1jhjhMOhj۴hhubh)}(hThe example below shows how to use **drm_xe_exec_queue_create** to create a simple exec_queue (no parallel submission) of class :c:type:`DRM_XE_ENGINE_CLASS_RENDER`.h](h#The example below shows how to use }(hjhhhNhNubh)}(h**drm_xe_exec_queue_create**h]hdrm_xe_exec_queue_create}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhA to create a simple exec_queue (no parallel submission) of class }(hjhhhNhNubh)}(h$:c:type:`DRM_XE_ENGINE_CLASS_RENDER`h]j)}(hjh]hDRM_XE_ENGINE_CLASS_RENDER}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j% j) DRM_XE_ENGINE_CLASS_RENDERuh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMphjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMphj۴hhubjt)}(hXstruct drm_xe_engine_class_instance instance = { .engine_class = DRM_XE_ENGINE_CLASS_RENDER, }; struct drm_xe_exec_queue_create exec_queue_create = { .extensions = 0, .vm_id = vm, .num_bb_per_exec = 1, .num_eng_per_bb = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); Allow users to provide a hint to kernel for cases demanding low latency profile. Please note it will have impact on power consumption. User can indicate low latency hint with flag while creating exec queue as mentioned below, struct drm_xe_exec_queue_create exec_queue_create = { .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, .extensions = 0, .vm_id = vm, .num_bb_per_exec = 1, .num_eng_per_bb = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);h]hXstruct drm_xe_engine_class_instance instance = { .engine_class = DRM_XE_ENGINE_CLASS_RENDER, }; struct drm_xe_exec_queue_create exec_queue_create = { .extensions = 0, .vm_id = vm, .num_bb_per_exec = 1, .num_eng_per_bb = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); Allow users to provide a hint to kernel for cases demanding low latency profile. Please note it will have impact on power consumption. User can indicate low latency hint with flag while creating exec queue as mentioned below, struct drm_xe_exec_queue_create exec_queue_create = { .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, .extensions = 0, .vm_id = vm, .num_bb_per_exec = 1, .num_eng_per_bb = 1, .instances = to_user_pointer(&instance), }; ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);}hj#sbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMthj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_xe_exec_queue_destroy (C struct)c.drm_xe_exec_queue_destroyhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_exec_queue_destroyh]j)}(h struct drm_xe_exec_queue_destroyh](j)}(hjh]hstruct}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHhhhjYhMubj)}(hdrm_xe_exec_queue_destroyh]j)}(hjFh]hdrm_xe_exec_queue_destroy}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubah}(h]h ](j jeh"]h$]h&]jjuh1jhjHhhhjYhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjDhhhjYhMubah}(h]j?ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjYhMhjAhhubj))}(hhh]h)}(h2Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY`h](h Input of }(hjhhhNhNubh)}(h):c:type:`DRM_IOCTL_XE_EXEC_QUEUE_DESTROY`h]j)}(hjh]hDRM_IOCTL_XE_EXEC_QUEUE_DESTROY}(hjhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjFsbc.drm_xe_exec_queue_destroyasbj) DRM_IOCTL_XE_EXEC_QUEUE_DESTROYuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjAhhhjYhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(h**Definition**:: struct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; }; **Members** ``exec_queue_id`` Exec queue ID ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hdstruct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; };h]hdstruct drm_xe_exec_queue_destroy { __u32 exec_queue_id; __u32 pad; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h ``exec_queue_id`` Exec queue ID h](j)}(h``exec_queue_id``h]j)}(hj!h]h exec_queue_id}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h Exec queue IDh]h Exec queue ID}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj7ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj6hMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjZh]hpad}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjTubj()}(hhh]h)}(hMBZh]hMBZ}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohMhjpubah}(h]h ]h"]h$]h&]uh1j'hjTubeh}(h]h ]h"]h$]h&]uh1jhjohMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)drm_xe_exec_queue_get_property (C struct) c.drm_xe_exec_queue_get_propertyhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_exec_queue_get_propertyh]j)}(h%struct drm_xe_exec_queue_get_propertyh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_exec_queue_get_propertyh]j)}(hjh]hdrm_xe_exec_queue_get_property}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h7Input of :c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY`h](h Input of }(hj/hhhNhNubh)}(h.:c:type:`DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY`h]j)}(hj9h]h$DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY}(hj;hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjsb c.drm_xe_exec_queue_get_propertyasbj) $DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTYuh1hhjhKhj/ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj,hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjmjLjmjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``exec_queue_id`` Exec queue ID ``property`` property to get ``value`` property value ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuubh:}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjqubjt)}(hstruct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; };h]hstruct drm_xe_exec_queue_get_property { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0; __u32 property; __u64 value; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjqubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjqubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h ``exec_queue_id`` Exec queue ID h](j)}(h``exec_queue_id``h]j)}(hjh]h exec_queue_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h Exec queue IDh]h Exec queue ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``property`` property to get h](j)}(h ``property``h]j)}(hj4h]hproperty}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj.ubj()}(hhh]h)}(hproperty to geth]hproperty to get}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMhjJubah}(h]h ]h"]h$]h&]uh1j'hj.ubeh}(h]h ]h"]h$]h&]uh1jhjIhMhjubj)}(h``value`` property value h](j)}(h ``value``h]j)}(hjmh]hvalue}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjgubj()}(hhh]h)}(hproperty valueh]hproperty value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjgubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj )}(hhh]j)}(hEThe **property** can be: - ``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN`` h](j)}(hThe **property** can be:h](hThe }(hjhhhNhNubh)}(h **property**h]hproperty}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh can be:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]j )}(hhh]j )}(h*``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN`` h]h)}(h&``DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN``h]j)}(hj3h]h"DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj-ubah}(h]h ]h"]h$]h&]uh1j hj*ubah}(h]h ]h"]h$]h&]j) j* uh1j hjHhMhj'ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj&hMhjubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_sync (C struct) c.drm_xe_synchNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(h drm_xe_synch]j)}(hstruct drm_xe_synch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|hhhjhMubj)}(h drm_xe_synch]j)}(hjzh]h drm_xe_sync}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhj|hhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjxhhhjhMubah}(h]jsah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjuhhubj))}(hhh]h)}(h sync objecth]h sync object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjuhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hXr**Definition**:: struct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``type`` Type of the this sync object ``flags`` Sync Flags ``{unnamed_union}`` anonymous ``handle`` Handle for the object ``addr`` Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync passed in via VM bind IOCTL this is a user pointer. In either case, it is the users responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned. ``timeline_value`` Input for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``. ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hXstruct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; };h]hXstruct drm_xe_sync { __u64 extensions; #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0; #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1; #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2; __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0); __u32 flags; union { __u32 handle; __u64 addr; }; __u64 timeline_value; __u64 reserved[2]; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj/ h]h extensions}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj- ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj) ubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjD hMhjE ubah}(h]h ]h"]h$]h&]uh1j'hj) ubeh}(h]h ]h"]h$]h&]uh1jhjD hMhj& ubj)}(h&``type`` Type of the this sync object h](j)}(h``type``h]j)}(hjh h]htype}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjb ubj()}(hhh]h)}(hType of the this sync objecth]hType of the this sync object}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj} hMhj~ ubah}(h]h ]h"]h$]h&]uh1j'hjb ubeh}(h]h ]h"]h$]h&]uh1jhj} hMhj& ubj)}(h``flags`` Sync Flags h](j)}(h ``flags``h]j)}(hj h]hflags}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj()}(hhh]h)}(h Sync Flagsh]h Sync Flags}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj& ubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hj h]h{unnamed_union}}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhj ubj()}(hhh]h)}(h anonymoush]h anonymous}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj& ubj)}(h!``handle`` Handle for the object h](j)}(h ``handle``h]j)}(hj h]hhandle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj()}(hhh]h)}(hHandle for the objecth]hHandle for the object}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj( hMhj) ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj( hMhj& ubj)}(hX5``addr`` Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync passed in via VM bind IOCTL this is a user pointer. In either case, it is the users responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned. h](j)}(h``addr``h]j)}(hjL h]haddr}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJ ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjF ubj()}(hhh]h)}(hX+Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync passed in via VM bind IOCTL this is a user pointer. In either case, it is the users responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned.h]hX+Address of user fence. When sync is passed in via exec IOCTL this is a GPU address in the VM. When sync passed in via VM bind IOCTL this is a user pointer. In either case, it is the users responsibility that this address is present and mapped when the user fence is signalled. Must be qword aligned.}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjb ubah}(h]h ]h"]h$]h&]uh1j'hjF ubeh}(h]h ]h"]h$]h&]uh1jhja hMhj& ubj)}(h``timeline_value`` Input for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``. h](j)}(h``timeline_value``h]j)}(hj h]htimeline_value}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM&hj ubj()}(hhh]h)}(hvInput for the timeline sync object. Needs to be different than 0 when used with ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``.h](hPInput for the timeline sync object. Needs to be different than 0 when used with }(hj hhhNhNubj)}(h%``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``h]h!DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM%hj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM&hj& ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hj h]hreserved}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM)hj ubj()}(hhh]h)}(hReservedh]hReserved}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM*hj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM)hj& ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM-hj۴hhubj )}(hhh](j)}(h~The **type** can be: - ``DRM_XE_SYNC_TYPE_SYNCOBJ`` - ``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ`` - ``DRM_XE_SYNC_TYPE_USER_FENCE`` h](j)}(hThe **type** can be:h](hThe }(hj2 hhhNhNubh)}(h**type**h]htype}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2 ubh can be:}(hj2 hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj. ubj()}(hhh]j )}(hhh](j )}(h``DRM_XE_SYNC_TYPE_SYNCOBJ``h]h)}(hj[ h]j)}(hj[ h]hDRM_XE_SYNC_TYPE_SYNCOBJ}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj] ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjY ubah}(h]h ]h"]h$]h&]uh1j hjV ubj )}(h%``DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ``h]h)}(hj| h]j)}(hj| h]h!DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjz ubah}(h]h ]h"]h$]h&]uh1j hjV ubj )}(h ``DRM_XE_SYNC_TYPE_USER_FENCE`` h]h)}(h``DRM_XE_SYNC_TYPE_USER_FENCE``h]j)}(hj h]hDRM_XE_SYNC_TYPE_USER_FENCE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhjR hMhj ubah}(h]h ]h"]h$]h&]uh1j hjV ubeh}(h]h ]h"]h$]h&]j) j* uh1j hjs hMhjS ubah}(h]h ]h"]h$]h&]uh1j'hj. ubeh}(h]h ]h"]h$]h&]uh1jhjR hMhj+ ubj)}(h8and the **flags** can be: - ``DRM_XE_SYNC_FLAG_SIGNAL`` h](j)}(hand the **flags** can be:h](hand the }(hj hhhNhNubh)}(h **flags**h]hflags}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh can be:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj()}(hhh]j )}(hhh]j )}(h``DRM_XE_SYNC_FLAG_SIGNAL`` h]h)}(h``DRM_XE_SYNC_FLAG_SIGNAL``h]j)}(hj h]hDRM_XE_SYNC_FLAG_SIGNAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]j) j* uh1j hj hMhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMhj+ ubeh}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubh)}(h1A minimal use of **drm_xe_sync** looks like this:h](hA minimal use of }(hj2 hhhNhNubh)}(h**drm_xe_sync**h]h drm_xe_sync}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2 ubh looks like this:}(hj2 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubjt)}(hXstruct drm_xe_sync sync = { .flags = DRM_XE_SYNC_FLAG_SIGNAL, .type = DRM_XE_SYNC_TYPE_SYNCOBJ, }; struct drm_syncobj_create syncobj_create = { 0 }; ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); sync.handle = syncobj_create.handle; ... use of &sync in drm_xe_exec or drm_xe_vm_bind ... struct drm_syncobj_wait wait = { .handles = &sync.handle, .timeout_nsec = INT64_MAX, .count_handles = 1, .flags = 0, .first_signaled = 0, .pad = 0, }; ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);h]hXstruct drm_xe_sync sync = { .flags = DRM_XE_SYNC_FLAG_SIGNAL, .type = DRM_XE_SYNC_TYPE_SYNCOBJ, }; struct drm_syncobj_create syncobj_create = { 0 }; ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); sync.handle = syncobj_create.handle; ... use of &sync in drm_xe_exec or drm_xe_vm_bind ... struct drm_syncobj_wait wait = { .handles = &sync.handle, .timeout_nsec = INT64_MAX, .count_handles = 1, .flags = 0, .first_signaled = 0, .pad = 0, }; ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);}hjS sbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_exec (C struct) c.drm_xe_exechNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(h drm_xe_exech]j)}(hstruct drm_xe_exech](j)}(hjh]hstruct}(hj| hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx hhhj hMubj)}(h drm_xe_exech]j)}(hjv h]h drm_xe_exec}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjx hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjt hhhj hMubah}(h]jo ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj hMhjq hhubj))}(hhh]h)}(h$Input of :c:type:`DRM_IOCTL_XE_EXEC`h](h Input of }(hj hhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_EXEC`h]j)}(hj h]hDRM_IOCTL_XE_EXEC}(hj hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjv sb c.drm_xe_execasbj) DRM_IOCTL_XE_EXECuh1hhjhKhj ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM.hj hhubah}(h]h ]h"]h$]h&]uh1j(hjq hhhj hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj jLj jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_MAX_SYNCS 1024; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``exec_queue_id`` Exec queue ID for the batch buffer ``num_syncs`` Amount of struct drm_xe_sync in array. ``syncs`` Pointer to struct drm_xe_sync array. ``address`` address of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses ``num_batch_buffer`` number of batch buffer in this exec, must match the width of the engine ``pad`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM2hj ubjt)}(hstruct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_MAX_SYNCS 1024; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; };h]hstruct drm_xe_exec { __u64 extensions; __u32 exec_queue_id; #define DRM_XE_MAX_SYNCS 1024; __u32 num_syncs; __u64 syncs; __u64 address; __u16 num_batch_buffer; __u16 pad[3]; __u64 reserved[2]; };}hj! sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM4hj ubh)}(h **Members**h]h)}(hj2 h]hMembers}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0 ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM@hj ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjQ h]h extensions}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjO ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMChjK ubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf hMChjg ubah}(h]h ]h"]h$]h&]uh1j'hjK ubeh}(h]h ]h"]h$]h&]uh1jhjf hMChjH ubj)}(h5``exec_queue_id`` Exec queue ID for the batch buffer h](j)}(h``exec_queue_id``h]j)}(hj h]h exec_queue_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMFhj ubj()}(hhh]h)}(h"Exec queue ID for the batch bufferh]h"Exec queue ID for the batch buffer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMFhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMFhjH ubj)}(h5``num_syncs`` Amount of struct drm_xe_sync in array. h](j)}(h ``num_syncs``h]j)}(hj h]h num_syncs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMJhj ubj()}(hhh]h)}(h&Amount of struct drm_xe_sync in array.h]h&Amount of struct drm_xe_sync in array.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMJhj ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMJhjH ubj)}(h/``syncs`` Pointer to struct drm_xe_sync array. h](j)}(h ``syncs``h]j)}(hj h]hsyncs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMMhj ubj()}(hhh]h)}(h$Pointer to struct drm_xe_sync array.h]h$Pointer to struct drm_xe_sync array.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMMhjubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhjhMMhjH ubj)}(hc``address`` address of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses h](j)}(h ``address``h]j)}(hj5h]haddress}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMRhj/ubj()}(hhh]h)}(hVaddress of batch buffer if num_batch_buffer == 1 or an array of batch buffer addressesh]hVaddress of batch buffer if num_batch_buffer == 1 or an array of batch buffer addresses}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMQhjKubah}(h]h ]h"]h$]h&]uh1j'hj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhMRhjH ubj)}(h]``num_batch_buffer`` number of batch buffer in this exec, must match the width of the engine h](j)}(h``num_batch_buffer``h]j)}(hjoh]hnum_batch_buffer}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMXhjiubj()}(hhh]h)}(hGnumber of batch buffer in this exec, must match the width of the engineh]hGnumber of batch buffer in this exec, must match the width of the engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMWhjubah}(h]h ]h"]h$]h&]uh1j'hjiubeh}(h]h ]h"]h$]h&]uh1jhjhMXhjH ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjh]hpad}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM\hjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM\hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM\hjH ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM^hjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM_hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM^hjH ubeh}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj%h]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMbhj۴hhubh)}(hXThis is an example to use **drm_xe_exec** for execution of the object at BIND_ADDRESS (see example in **drm_xe_vm_bind**) by an exec_queue (see example in **drm_xe_exec_queue_create**). It can be synchronized by using the example provided for **drm_xe_sync**.h](hThis is an example to use }(hj;hhhNhNubh)}(h**drm_xe_exec**h]h drm_xe_exec}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;ubh= for execution of the object at BIND_ADDRESS (see example in }(hj;hhhNhNubh)}(h**drm_xe_vm_bind**h]hdrm_xe_vm_bind}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;ubh#) by an exec_queue (see example in }(hj;hhhNhNubh)}(h**drm_xe_exec_queue_create**h]hdrm_xe_exec_queue_create}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;ubh<). It can be synchronized by using the example provided for }(hj;hhhNhNubh)}(h**drm_xe_sync**h]h drm_xe_sync}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;ubh.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM/hj۴hhubjt)}(hstruct drm_xe_exec exec = { .exec_queue_id = exec_queue, .syncs = &sync, .num_syncs = 1, .address = BIND_ADDRESS, .num_batch_buffer = 1, }; ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);h]hstruct drm_xe_exec exec = { .exec_queue_id = exec_queue, .syncs = &sync, .num_syncs = 1, .address = BIND_ADDRESS, .num_batch_buffer = 1, }; ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);}hjsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM4hj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!drm_xe_wait_user_fence (C struct)c.drm_xe_wait_user_fencehNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_wait_user_fenceh]j)}(hstruct drm_xe_wait_user_fenceh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMBubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMBubj)}(hdrm_xe_wait_user_fenceh]j)}(hjh]hdrm_xe_wait_user_fence}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMBubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMBubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMBhjhhubj))}(hhh]h)}(h/Input of :c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE`h](h Input of }(hjhhhNhNubh)}(h&:c:type:`DRM_IOCTL_XE_WAIT_USER_FENCE`h]j)}(hjh]hDRM_IOCTL_XE_WAIT_USER_FENCE}(hj hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjsbc.drm_xe_wait_user_fenceasbj) DRM_IOCTL_XE_WAIT_USER_FENCEuh1hhjhKhjubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMchjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMBubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj;jLj;jMjNjOuh1jhhhj۴hjhM ubjQ)}(hXu**Definition**:: struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``addr`` user pointer address to wait on, must qword aligned ``op`` wait operation (type of comparison) ``flags`` wait flags ``pad`` MBZ ``value`` compare value ``mask`` comparison mask ``timeout`` how long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait will end at timeout (uses system MONOTONIC_CLOCK). Passing negative timeout leads to neverending wait. On relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time). ``exec_queue_id`` exec_queue_id returned from xe_exec_queue_create_ioctl ``pad2`` MBZ ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCubh:}(hjChhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMghj?ubjt)}(hX*struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; };h]hX*struct drm_xe_wait_user_fence { __u64 extensions; __u64 addr; #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0; #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1; #define DRM_XE_UFENCE_WAIT_OP_GT 0x2; #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3; #define DRM_XE_UFENCE_WAIT_OP_LT 0x4; #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5; __u16 op; #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0); __u16 flags; __u32 pad; __u64 value; __u64 mask; __s64 timeout; __u32 exec_queue_id; __u32 pad2; __u64 reserved[2]; };}hj`sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMihj?ubh)}(h **Members**h]h)}(hjqh]hMembers}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjoubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hj?ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h=``addr`` user pointer address to wait on, must qword aligned h](j)}(h``addr``h]j)}(hjh]haddr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h3user pointer address to wait on, must qword alignedh]h3user pointer address to wait on, must qword aligned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h+``op`` wait operation (type of comparison) h](j)}(h``op``h]j)}(hjh]hop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h#wait operation (type of comparison)h]h#wait operation (type of comparison)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``flags`` wait flags h](j)}(h ``flags``h]j)}(hj;h]hflags}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj5ubj()}(hhh]h)}(h wait flagsh]h wait flags}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjQubah}(h]h ]h"]h$]h&]uh1j'hj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjth]hpad}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjnubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjnubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``value`` compare value h](j)}(h ``value``h]j)}(hjh]hvalue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h compare valueh]h compare value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``mask`` comparison mask h](j)}(h``mask``h]j)}(hjh]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hcomparison maskh]hcomparison mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hXl``timeout`` how long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait will end at timeout (uses system MONOTONIC_CLOCK). Passing negative timeout leads to neverending wait. On relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time). h](j)}(h ``timeout``h]j)}(hjh]htimeout}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh](h)}(hXhow long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait will end at timeout (uses system MONOTONIC_CLOCK). Passing negative timeout leads to neverending wait.h]hXhow long to wait before bailing, value in nanoseconds. Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) it contains timeout expressed in nanoseconds to wait (fence will expire at now() + timeout). When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait will end at timeout (uses system MONOTONIC_CLOCK). Passing negative timeout leads to neverending wait.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj5ubh)}(hOn relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time).h]hOn relative timeout this value is updated with timeout left (for restarting the call in case of signal delivery). On absolute timeout this value stays intact (restarted call still expire at the same point of time).}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj5ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj4hMhjubj)}(hI``exec_queue_id`` exec_queue_id returned from xe_exec_queue_create_ioctl h](j)}(h``exec_queue_id``h]j)}(hjhh]h exec_queue_id}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjbubj()}(hhh]h)}(h6exec_queue_id returned from xe_exec_queue_create_ioctlh]h6exec_queue_id returned from xe_exec_queue_create_ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj~ubah}(h]h ]h"]h$]h&]uh1j'hjbubeh}(h]h ]h"]h$]h&]uh1jhj}hMhjubj)}(h ``pad2`` MBZ h](j)}(h``pad2``h]j)}(hjh]hpad2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hj?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubh)}(h|Wait on user fence, XE will wake-up on every HW engine interrupt in the instances list and check if user fence is complete::h]h{Wait on user fence, XE will wake-up on every HW engine interrupt in the instances list and check if user fence is complete:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMdhj۴hhubjt)}(h (*addr & MASK) OP (VALUE & MASK)h]h (*addr & MASK) OP (VALUE & MASK)}hjBsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMghj۴hhubh)}(h4Returns to user on user fence completion or timeout.h]h4Returns to user on user fence completion or timeout.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMihj۴hhubj )}(hhh](j)}(hThe **op** can be: - ``DRM_XE_UFENCE_WAIT_OP_EQ`` - ``DRM_XE_UFENCE_WAIT_OP_NEQ`` - ``DRM_XE_UFENCE_WAIT_OP_GT`` - ``DRM_XE_UFENCE_WAIT_OP_GTE`` - ``DRM_XE_UFENCE_WAIT_OP_LT`` - ``DRM_XE_UFENCE_WAIT_OP_LTE`` h](j)}(hThe **op** can be:h](hThe }(hjghhhNhNubh)}(h**op**h]hop}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgubh can be:}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMqhjcubj()}(hhh]j )}(hhh](j )}(h``DRM_XE_UFENCE_WAIT_OP_EQ``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_EQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMlhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_UFENCE_WAIT_OP_NEQ``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_NEQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMmhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_UFENCE_WAIT_OP_GT``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_GT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMnhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_UFENCE_WAIT_OP_GTE``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_GTE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMohjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_UFENCE_WAIT_OP_LT``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_OP_LT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMphjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h``DRM_XE_UFENCE_WAIT_OP_LTE`` h]h)}(h``DRM_XE_UFENCE_WAIT_OP_LTE``h]j)}(hj9h]hDRM_XE_UFENCE_WAIT_OP_LTE}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1hhjhMqhj3ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhMlhjubah}(h]h ]h"]h$]h&]uh1j'hjcubeh}(h]h ]h"]h$]h&]uh1jhjhMqhj`ubj)}(hfand the **flags** can be: - ``DRM_XE_UFENCE_WAIT_FLAG_ABSTIME`` - ``DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP`` h](j)}(hand the **flags** can be:h](hand the }(hjjhhhNhNubh)}(h **flags**h]hflags}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjubh can be:}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMuhjfubj()}(hhh]j )}(hhh](j )}(h#``DRM_XE_UFENCE_WAIT_FLAG_ABSTIME``h]h)}(hjh]j)}(hjh]hDRM_XE_UFENCE_WAIT_FLAG_ABSTIME}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMthjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(h$``DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP`` h]h)}(h#``DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP``h]j)}(hjh]hDRM_XE_UFENCE_WAIT_FLAG_SOFT_OP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhjhMuhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]j) j* uh1j hjhMthjubah}(h]h ]h"]h$]h&]uh1j'hjfubeh}(h]h ]h"]h$]h&]uh1jhjhMuhj`ubj)}(hThe **mask** values can be for example: - 0xffu for u8 - 0xffffu for u16 - 0xffffffffu for u32 - 0xffffffffffffffffu for u64 h](j)}(h'The **mask** values can be for example:h](hThe }(hjhhhNhNubh)}(h**mask**h]hmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh values can be for example:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hjubj()}(hhh]j )}(hhh](j )}(h 0xffu for u8h]h)}(hjh]h 0xffu for u8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMxhjubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(h0xffffu for u16h]h)}(hj*h]h0xffffu for u16}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMyhj(ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(h0xffffffffu for u32h]h)}(hjBh]h0xffffffffu for u32}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMzhj@ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(h0xffffffffffffffffu for u64 h]h)}(h0xffffffffffffffffu for u64h]h0xffffffffffffffffu for u64}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM{hjXubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]j) j* uh1j hj!hMxhj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hM~hj`ubeh}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_observation_type (C enum)c.drm_xe_observation_typehNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_observation_typeh]j)}(henum drm_xe_observation_typeh](j)}(hjSh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_observation_typeh]j)}(hjh]hdrm_xe_observation_type}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(hObservation stream typesh]hObservation stream types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(h**Constants** ``DRM_XE_OBSERVATION_TYPE_OA`` OA observation stream type ``DRM_XE_OBSERVATION_TYPE_EU_STALL`` EU stall sampling observation stream typeh](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h:``DRM_XE_OBSERVATION_TYPE_OA`` OA observation stream type h](j)}(h``DRM_XE_OBSERVATION_TYPE_OA``h]j)}(hj%h]hDRM_XE_OBSERVATION_TYPE_OA}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hOA observation stream typeh]hOA observation stream type}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj;ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj:hMhjubj)}(hN``DRM_XE_OBSERVATION_TYPE_EU_STALL`` EU stall sampling observation stream typeh](j)}(h$``DRM_XE_OBSERVATION_TYPE_EU_STALL``h]j)}(hj^h]h DRM_XE_OBSERVATION_TYPE_EU_STALL}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjXubj()}(hhh]h)}(h)EU stall sampling observation stream typeh]h)EU stall sampling observation stream type}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjtubah}(h]h ]h"]h$]h&]uh1j'hjXubeh}(h]h ]h"]h$]h&]uh1jhjshMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_observation_op (C enum)c.drm_xe_observation_ophNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_observation_oph]j)}(henum drm_xe_observation_oph](j)}(hjSh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_observation_oph]j)}(hjh]hdrm_xe_observation_op}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(hObservation stream opsh]hObservation stream ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(h**Constants** ``DRM_XE_OBSERVATION_OP_STREAM_OPEN`` Open an observation stream ``DRM_XE_OBSERVATION_OP_ADD_CONFIG`` Add observation stream config ``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG`` Remove observation stream configh](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(hA``DRM_XE_OBSERVATION_OP_STREAM_OPEN`` Open an observation stream h](j)}(h%``DRM_XE_OBSERVATION_OP_STREAM_OPEN``h]j)}(hj;h]h!DRM_XE_OBSERVATION_OP_STREAM_OPEN}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj5ubj()}(hhh]h)}(hOpen an observation streamh]hOpen an observation stream}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjQubah}(h]h ]h"]h$]h&]uh1j'hj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhMhj2ubj)}(hC``DRM_XE_OBSERVATION_OP_ADD_CONFIG`` Add observation stream config h](j)}(h$``DRM_XE_OBSERVATION_OP_ADD_CONFIG``h]j)}(hjth]h DRM_XE_OBSERVATION_OP_ADD_CONFIG}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjnubj()}(hhh]h)}(hAdd observation stream configh]hAdd observation stream config}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjnubeh}(h]h ]h"]h$]h&]uh1jhjhMhj2ubj)}(hH``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG`` Remove observation stream configh](j)}(h'``DRM_XE_OBSERVATION_OP_REMOVE_CONFIG``h]j)}(hjh]h#DRM_XE_OBSERVATION_OP_REMOVE_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h Remove observation stream configh]h Remove observation stream config}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj2ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_xe_observation_param (C struct)c.drm_xe_observation_paramhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_observation_paramh]j)}(hstruct drm_xe_observation_paramh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_observation_paramh]j)}(hjh]hdrm_xe_observation_param}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(h%Input of :c:type:`DRM_XE_OBSERVATION`h](h Input of }(hjIhhhNhNubh)}(h:c:type:`DRM_XE_OBSERVATION`h]j)}(hjSh]hDRM_XE_OBSERVATION}(hjUhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjsbc.drm_xe_observation_paramasbj) DRM_XE_OBSERVATIONuh1hhjhKhjIubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjFhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``observation_type`` observation stream type, of enum **drm_xe_observation_type** ``observation_op`` observation stream op, of enum **drm_xe_observation_op** ``param`` Pointer to actual stream paramsh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hstruct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; };h]hstruct drm_xe_observation_param { __u64 extensions; __u64 observation_type; __u64 observation_op; __u64 param; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjh]h extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hR``observation_type`` observation stream type, of enum **drm_xe_observation_type** h](j)}(h``observation_type``h]j)}(hjh]hobservation_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhj+hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj+hMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj+hMhjhhubj))}(hhh]h)}(h OA unit typesh]h OA unit types}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj]hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj+hMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjxjLjxjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Constants** ``DRM_XE_OA_UNIT_TYPE_OAG`` OAG OA unit. OAR/OAC are considered sub-types of OAG. For OAR/OAC, use OAG. ``DRM_XE_OA_UNIT_TYPE_OAM`` OAM OA unit ``DRM_XE_OA_UNIT_TYPE_OAM_SAG`` OAM_SAG OA unit ``DRM_XE_OA_UNIT_TYPE_MERT`` MERT OA unith](h)}(h **Constants**h]h)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj|ubj )}(hhh](j)}(hh``DRM_XE_OA_UNIT_TYPE_OAG`` OAG OA unit. OAR/OAC are considered sub-types of OAG. For OAR/OAC, use OAG. h](j)}(h``DRM_XE_OA_UNIT_TYPE_OAG``h]j)}(hjh]hDRM_XE_OA_UNIT_TYPE_OAG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hKOAG OA unit. OAR/OAC are considered sub-types of OAG. For OAR/OAC, use OAG.h]hKOAG OA unit. OAR/OAC are considered sub-types of OAG. For OAR/OAC, use OAG.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h(``DRM_XE_OA_UNIT_TYPE_OAM`` OAM OA unit h](j)}(h``DRM_XE_OA_UNIT_TYPE_OAM``h]j)}(hjh]hDRM_XE_OA_UNIT_TYPE_OAM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h OAM OA unith]h OAM OA unit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h0``DRM_XE_OA_UNIT_TYPE_OAM_SAG`` OAM_SAG OA unit h](j)}(h``DRM_XE_OA_UNIT_TYPE_OAM_SAG``h]j)}(hjh]hDRM_XE_OA_UNIT_TYPE_OAM_SAG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(hOAM_SAG OA unith]hOAM_SAG OA unit}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hMhj*ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj)hMhjubj)}(h)``DRM_XE_OA_UNIT_TYPE_MERT`` MERT OA unith](j)}(h``DRM_XE_OA_UNIT_TYPE_MERT``h]j)}(hjMh]hDRM_XE_OA_UNIT_TYPE_MERT}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjGubj()}(hhh]h)}(h MERT OA unith]h MERT OA unit}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjcubah}(h]h ]h"]h$]h&]uh1j'hjGubeh}(h]h ]h"]h$]h&]uh1jhjbhM hjubeh}(h]h ]h"]h$]h&]uh1j hj|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_oa_unit (C struct)c.drm_xe_oa_unithNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_oa_unith]j)}(hstruct drm_xe_oa_unith](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hdrm_xe_oa_unith]j)}(hjh]hdrm_xe_oa_unit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMhjhhubj))}(hhh]h)}(hdescribe OA unith]hdescribe OA unit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX(**Definition**:: struct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); #define DRM_XE_OA_CAPS_OAM (1 << 4); #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5); __u64 oa_timestamp_freq; __u16 gt_id; __u16 reserved1[3]; __u64 reserved[3]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``oa_unit_id`` OA unit ID ``oa_unit_type`` OA unit type of **drm_xe_oa_unit_type** ``capabilities`` OA capabilities bit-mask ``oa_timestamp_freq`` OA timestamp freq ``gt_id`` gt id for this OA unit ``reserved1`` MBZ ``reserved`` MBZ ``num_engines`` number of engines in **eci** array ``eci`` engines attached to this OA unith](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubjt)}(hXEstruct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); #define DRM_XE_OA_CAPS_OAM (1 << 4); #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5); __u64 oa_timestamp_freq; __u16 gt_id; __u16 reserved1[3]; __u64 reserved[3]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; };h]hXEstruct drm_xe_oa_unit { __u64 extensions; __u32 oa_unit_id; __u32 oa_unit_type; __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0); #define DRM_XE_OA_CAPS_SYNCS (1 << 1); #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2); #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3); #define DRM_XE_OA_CAPS_OAM (1 << 4); #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5); __u64 oa_timestamp_freq; __u16 gt_id; __u16 reserved1[3]; __u64 reserved[3]; __u64 num_engines; struct drm_xe_engine_class_instance eci[]; };}hj&sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubh)}(h **Members**h]h)}(hj7h]hMembers}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM'hjubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjVh]h extensions}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjPubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhMhjlubah}(h]h ]h"]h$]h&]uh1j'hjPubeh}(h]h ]h"]h$]h&]uh1jhjkhMhjMubj)}(h``oa_unit_id`` OA unit ID h](j)}(h``oa_unit_id``h]j)}(hjh]h oa_unit_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h OA unit IDh]h OA unit ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjMubj)}(h9``oa_unit_type`` OA unit type of **drm_xe_oa_unit_type** h](j)}(h``oa_unit_type``h]j)}(hjh]h oa_unit_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjubj()}(hhh]h)}(h'OA unit type of **drm_xe_oa_unit_type**h](hOA unit type of }(hjhhhNhNubh)}(h**drm_xe_oa_unit_type**h]hdrm_xe_oa_unit_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjMubj)}(h*``capabilities`` OA capabilities bit-mask h](j)}(h``capabilities``h]j)}(hjh]h capabilities}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj ubj()}(hhh]h)}(hOA capabilities bit-maskh]hOA capabilities bit-mask}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMhj%ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhjMubj)}(h(``oa_timestamp_freq`` OA timestamp freq h](j)}(h``oa_timestamp_freq``h]j)}(hjHh]hoa_timestamp_freq}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM$hjBubj()}(hhh]h)}(hOA timestamp freqh]hOA timestamp freq}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hM$hj^ubah}(h]h ]h"]h$]h&]uh1j'hjBubeh}(h]h ]h"]h$]h&]uh1jhj]hM$hjMubj)}(h!``gt_id`` gt id for this OA unit h](j)}(h ``gt_id``h]j)}(hjh]hgt_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM'hj{ubj()}(hhh]h)}(hgt id for this OA unith]hgt id for this OA unit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM'hjubah}(h]h ]h"]h$]h&]uh1j'hj{ubeh}(h]h ]h"]h$]h&]uh1jhjhM'hjMubj)}(h``reserved1`` MBZ h](j)}(h ``reserved1``h]j)}(hjh]h reserved1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM*hjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM*hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM*hjMubj)}(h``reserved`` MBZ h](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM-hjubj()}(hhh]h)}(hMBZh]hMBZ}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM-hj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hM-hjMubj)}(h3``num_engines`` number of engines in **eci** array h](j)}(h``num_engines``h]j)}(hj, h]h num_engines}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj* ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM0hj& ubj()}(hhh]h)}(h"number of engines in **eci** arrayh](hnumber of engines in }(hjE hhhNhNubh)}(h**eci**h]heci}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE ubh array}(hjE hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjA hM0hjB ubah}(h]h ]h"]h$]h&]uh1j'hj& ubeh}(h]h ]h"]h$]h&]uh1jhjA hM0hjMubj)}(h(``eci`` engines attached to this OA unith](j)}(h``eci``h]j)}(hjw h]heci}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM2hjq ubj()}(hhh]h)}(h engines attached to this OA unith]h engines attached to this OA unit}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM3hj ubah}(h]h ]h"]h$]h&]uh1j'hjq ubeh}(h]h ]h"]h$]h&]uh1jhj hM2hjMubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_query_oa_units (C struct)c.drm_xe_query_oa_unitshNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_oa_unitsh]j)}(hstruct drm_xe_query_oa_unitsh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM9ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hM9ubj)}(hdrm_xe_query_oa_unitsh]j)}(hj h]hdrm_xe_query_oa_units}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj hhhj hM9ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hM9ubah}(h]j ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj hM9hj hhubj))}(hhh]h)}(hdescribe OA unitsh]hdescribe OA units}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM7hj!hhubah}(h]h ]h"]h$]h&]uh1j(hj hhhj hM9ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj+!jLj+!jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``num_oa_units`` number of OA units returned in oau[] ``pad`` MBZ ``oa_units`` struct **drm_xe_oa_unit** array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj7!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3!ubh:}(hj3!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM;hj/!ubjt)}(htstruct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; };h]htstruct drm_xe_query_oa_units { __u64 extensions; __u32 num_oa_units; __u32 pad; __u64 oa_units[]; };}hjP!sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=hj/!ubh)}(h **Members**h]h)}(hja!h]hMembers}(hjc!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_!ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMDhj/!ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj!h]h extensions}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~!ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMPhjz!ubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMPhj!ubah}(h]h ]h"]h$]h&]uh1j'hjz!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMPhjw!ubj)}(h6``num_oa_units`` number of OA units returned in oau[] h](j)}(h``num_oa_units``h]j)}(hj!h]h num_oa_units}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMRhj!ubj()}(hhh]h)}(h$number of OA units returned in oau[]h]h$number of OA units returned in oau[]}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMRhj!ubah}(h]h ]h"]h$]h&]uh1j'hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMRhjw!ubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hj!h]hpad}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMThj!ubj()}(hhh]h)}(hMBZh]hMBZ}(hj "hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMThj"ubah}(h]h ]h"]h$]h&]uh1j'hj!ubeh}(h]h ]h"]h$]h&]uh1jhj"hMThjw!ubj)}(h``oa_units`` struct **drm_xe_oa_unit** array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](j)}(h ``oa_units``h]j)}(hj+"h]hoa_units}(hj-"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)"ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMXhj%"ubj()}(hhh]h)}(hstruct **drm_xe_oa_unit** array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilersh](hstruct }(hjD"hhhNhNubh)}(h**drm_xe_oa_unit**h]hdrm_xe_oa_unit}(hjL"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjD"ubh array returned for this device. Written below as a u64 array to avoid problems with nested flexible arrays with some compilers}(hjD"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMWhjA"ubah}(h]h ]h"]h$]h&]uh1j'hj%"ubeh}(h]h ]h"]h$]h&]uh1jhj@"hMXhjw!ubeh}(h]h ]h"]h$]h&]uh1j hj/!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj"h]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~"ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM\hj۴hhubh)}(hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct drm_xe_query_oa_units in .data.h]hIf a query is made with a struct drm_xe_device_query where .query is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct drm_xe_query_oa_units in .data.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM8hj۴hhubh)}(h]OA unit properties for all OA units can be accessed using a code block such as the one below:h]h]OA unit properties for all OA units can be accessed using a code block such as the one below:}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM<hj۴hhubjt)}(hXstruct drm_xe_query_oa_units *qoa; struct drm_xe_oa_unit *oau; u8 *poau; // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: poau = (u8 *)&qoa->oa_units[0]; for (int i = 0; i < qoa->num_oa_units; i++) { oau = (struct drm_xe_oa_unit *)poau; // Access 'struct drm_xe_oa_unit' fields here poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); }h]hXstruct drm_xe_query_oa_units *qoa; struct drm_xe_oa_unit *oau; u8 *poau; // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: poau = (u8 *)&qoa->oa_units[0]; for (int i = 0; i < qoa->num_oa_units; i++) { oau = (struct drm_xe_oa_unit *)poau; // Access 'struct drm_xe_oa_unit' fields here poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); }}hj"sbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM?hj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_oa_format_type (C enum)c.drm_xe_oa_format_typehNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_oa_format_typeh]j)}(henum drm_xe_oa_format_typeh](j)}(hjSh]henum}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMPubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"hhhj"hMPubj)}(hdrm_xe_oa_format_typeh]j)}(hj"h]hdrm_xe_oa_format_type}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj"hhhj"hMPubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj"hhhj"hMPubah}(h]j"ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj"hMPhj"hhubj))}(hhh]h)}(h5OA format types as specified in PRM/Bspec 52198/60942h]h5OA format types as specified in PRM/Bspec 52198/60942}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM^hj#hhubah}(h]h ]h"]h$]h&]uh1j(hj"hhhj"hMPubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKj7#jLj7#jMjNjOuh1jhhhj۴hjhM ubjQ)}(hXF**Constants** ``DRM_XE_OA_FMT_TYPE_OAG`` OAG report format ``DRM_XE_OA_FMT_TYPE_OAR`` OAR report format ``DRM_XE_OA_FMT_TYPE_OAM`` OAM report format ``DRM_XE_OA_FMT_TYPE_OAC`` OAC report format ``DRM_XE_OA_FMT_TYPE_OAM_MPEC`` OAM SAMEDIA or OAM MPEC report format ``DRM_XE_OA_FMT_TYPE_PEC`` PEC report formath](h)}(h **Constants**h]h)}(hjA#h]h Constants}(hjC#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?#ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMbhj;#ubj )}(hhh](j)}(h-``DRM_XE_OA_FMT_TYPE_OAG`` OAG report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAG``h]j)}(hj`#h]hDRM_XE_OA_FMT_TYPE_OAG}(hjb#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^#ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMehjZ#ubj()}(hhh]h)}(hOAG report formath]hOAG report format}(hjy#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju#hMehjv#ubah}(h]h ]h"]h$]h&]uh1j'hjZ#ubeh}(h]h ]h"]h$]h&]uh1jhju#hMehjW#ubj)}(h-``DRM_XE_OA_FMT_TYPE_OAR`` OAR report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAR``h]j)}(hj#h]hDRM_XE_OA_FMT_TYPE_OAR}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhhj#ubj()}(hhh]h)}(hOAR report formath]hOAR report format}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMhhj#ubah}(h]h ]h"]h$]h&]uh1j'hj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMhhjW#ubj)}(h-``DRM_XE_OA_FMT_TYPE_OAM`` OAM report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAM``h]j)}(hj#h]hDRM_XE_OA_FMT_TYPE_OAM}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMkhj#ubj()}(hhh]h)}(hOAM report formath]hOAM report format}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMkhj#ubah}(h]h ]h"]h$]h&]uh1j'hj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMkhjW#ubj)}(h-``DRM_XE_OA_FMT_TYPE_OAC`` OAC report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAC``h]j)}(hj $h]hDRM_XE_OA_FMT_TYPE_OAC}(hj $hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj $ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMnhj$ubj()}(hhh]h)}(hOAC report formath]hOAC report format}(hj$$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj $hMnhj!$ubah}(h]h ]h"]h$]h&]uh1j'hj$ubeh}(h]h ]h"]h$]h&]uh1jhj $hMnhjW#ubj)}(hF``DRM_XE_OA_FMT_TYPE_OAM_MPEC`` OAM SAMEDIA or OAM MPEC report format h](j)}(h``DRM_XE_OA_FMT_TYPE_OAM_MPEC``h]j)}(hjD$h]hDRM_XE_OA_FMT_TYPE_OAM_MPEC}(hjF$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB$ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMqhj>$ubj()}(hhh]h)}(h%OAM SAMEDIA or OAM MPEC report formath]h%OAM SAMEDIA or OAM MPEC report format}(hj]$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjY$hMqhjZ$ubah}(h]h ]h"]h$]h&]uh1j'hj>$ubeh}(h]h ]h"]h$]h&]uh1jhjY$hMqhjW#ubj)}(h,``DRM_XE_OA_FMT_TYPE_PEC`` PEC report formath](j)}(h``DRM_XE_OA_FMT_TYPE_PEC``h]j)}(hj}$h]hDRM_XE_OA_FMT_TYPE_PEC}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{$ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMshjw$ubj()}(hhh]h)}(hPEC report formath]hPEC report format}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMthj$ubah}(h]h ]h"]h$]h&]uh1j'hjw$ubeh}(h]h ]h"]h$]h&]uh1jhj$hMshjW#ubeh}(h]h ]h"]h$]h&]uh1j hj;#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_oa_property_id (C enum)c.drm_xe_oa_property_idhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_oa_property_idh]j)}(henum drm_xe_oa_property_idh](j)}(hjSh]henum}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMyubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$hhhj$hMyubj)}(hdrm_xe_oa_property_idh]j)}(hj$h]hdrm_xe_oa_property_id}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj$hhhj$hMyubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj$hhhj$hMyubah}(h]j$ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj$hMyhj$hhubj))}(hhh]h)}(hOA stream property id'sh]hOA stream property id’s}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMqhj%hhubah}(h]h ]h"]h$]h&]uh1j(hj$hhhj$hMyubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKj1%jLj1%jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Constants** ``DRM_XE_OA_PROPERTY_OA_UNIT_ID`` ID of the OA unit on which to open the OA stream, see **oa_unit_id** in 'struct drm_xe_query_oa_units'. Defaults to 0 if not provided. ``DRM_XE_OA_PROPERTY_SAMPLE_OA`` A value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit. ``DRM_XE_OA_PROPERTY_OA_METRIC_SET`` OA metrics defining contents of OA reports, previously added via **DRM_XE_OBSERVATION_OP_ADD_CONFIG**. ``DRM_XE_OA_PROPERTY_OA_FORMAT`` OA counter report format ``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT`` Requests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1) ``DRM_XE_OA_PROPERTY_OA_DISABLED`` A value of 1 will open the OA stream in a DISABLED state (see **DRM_XE_OBSERVATION_IOCTL_ENABLE**). ``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` Open the stream for a specific **exec_queue_id**. OA queries can be executed on this exec queue. ``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE`` Optional engine instance to pass along with **DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID** or will default to 0. ``DRM_XE_OA_PROPERTY_NO_PREEMPT`` Allow preemption and timeslicing to be disabled for the stream exec queue. ``DRM_XE_OA_PROPERTY_NUM_SYNCS`` Number of syncs in the sync array specified in **DRM_XE_OA_PROPERTY_SYNCS** ``DRM_XE_OA_PROPERTY_SYNCS`` Pointer to struct **drm_xe_sync** array with array size specified via **DRM_XE_OA_PROPERTY_NUM_SYNCS**. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For **DRM_XE_SYNC_TYPE_USER_FENCE**, **addr** is a user pointer, similar to the VM bind case. ``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE`` Size of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default. ``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS`` Number of reports to wait for before unblocking poll or readh](h)}(h **Constants**h]h)}(hj;%h]h Constants}(hj=%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9%ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMuhj5%ubj )}(hhh](j)}(h``DRM_XE_OA_PROPERTY_OA_UNIT_ID`` ID of the OA unit on which to open the OA stream, see **oa_unit_id** in 'struct drm_xe_query_oa_units'. Defaults to 0 if not provided. h](j)}(h!``DRM_XE_OA_PROPERTY_OA_UNIT_ID``h]j)}(hjZ%h]hDRM_XE_OA_PROPERTY_OA_UNIT_ID}(hj\%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX%ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMzhjT%ubj()}(hhh]h)}(hID of the OA unit on which to open the OA stream, see **oa_unit_id** in 'struct drm_xe_query_oa_units'. Defaults to 0 if not provided.h](h6ID of the OA unit on which to open the OA stream, see }(hjs%hhhNhNubh)}(h**oa_unit_id**h]h oa_unit_id}(hj{%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs%ubhF in ‘struct drm_xe_query_oa_units’. Defaults to 0 if not provided.}(hjs%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMxhjp%ubah}(h]h ]h"]h$]h&]uh1j'hjT%ubeh}(h]h ]h"]h$]h&]uh1jhjo%hMzhjQ%ubj)}(h``DRM_XE_OA_PROPERTY_SAMPLE_OA`` A value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit. h](j)}(h ``DRM_XE_OA_PROPERTY_SAMPLE_OA``h]j)}(hj%h]hDRM_XE_OA_PROPERTY_SAMPLE_OA}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj%ubj()}(hhh]h)}(hsA value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit.h]hsA value of 1 requests inclusion of raw OA unit reports or stream samples in a global buffer attached to an OA unit.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM}hj%ubah}(h]h ]h"]h$]h&]uh1j'hj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hMhjQ%ubj)}(h``DRM_XE_OA_PROPERTY_OA_METRIC_SET`` OA metrics defining contents of OA reports, previously added via **DRM_XE_OBSERVATION_OP_ADD_CONFIG**. h](j)}(h$``DRM_XE_OA_PROPERTY_OA_METRIC_SET``h]j)}(hj%h]h DRM_XE_OA_PROPERTY_OA_METRIC_SET}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj%ubj()}(hhh]h)}(hfOA metrics defining contents of OA reports, previously added via **DRM_XE_OBSERVATION_OP_ADD_CONFIG**.h](hAOA metrics defining contents of OA reports, previously added via }(hj%hhhNhNubh)}(h$**DRM_XE_OBSERVATION_OP_ADD_CONFIG**h]h DRM_XE_OBSERVATION_OP_ADD_CONFIG}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%ubh.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj%ubah}(h]h ]h"]h$]h&]uh1j'hj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hMhjQ%ubj)}(h:``DRM_XE_OA_PROPERTY_OA_FORMAT`` OA counter report format h](j)}(h ``DRM_XE_OA_PROPERTY_OA_FORMAT``h]j)}(hj,&h]hDRM_XE_OA_PROPERTY_OA_FORMAT}(hj.&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*&ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj&&ubj()}(hhh]h)}(hOA counter report formath]hOA counter report format}(hjE&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjA&hMhjB&ubah}(h]h ]h"]h$]h&]uh1j'hj&&ubeh}(h]h ]h"]h$]h&]uh1jhjA&hMhjQ%ubj)}(h``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT`` Requests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1) h](j)}(h)``DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT``h]j)}(hje&h]h%DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT}(hjg&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc&ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj_&ubj()}(hhh]h)}(hbRequests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1)h]hbRequests periodic OA unit sampling with sampling frequency proportional to 2^(period_exponent + 1)}(hj~&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj{&ubah}(h]h ]h"]h$]h&]uh1j'hj_&ubeh}(h]h ]h"]h$]h&]uh1jhjz&hMhjQ%ubj)}(h``DRM_XE_OA_PROPERTY_OA_DISABLED`` A value of 1 will open the OA stream in a DISABLED state (see **DRM_XE_OBSERVATION_IOCTL_ENABLE**). h](j)}(h"``DRM_XE_OA_PROPERTY_OA_DISABLED``h]j)}(hj&h]hDRM_XE_OA_PROPERTY_OA_DISABLED}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj&ubj()}(hhh]h)}(hcA value of 1 will open the OA stream in a DISABLED state (see **DRM_XE_OBSERVATION_IOCTL_ENABLE**).h](h>A value of 1 will open the OA stream in a DISABLED state (see }(hj&hhhNhNubh)}(h#**DRM_XE_OBSERVATION_IOCTL_ENABLE**h]hDRM_XE_OBSERVATION_IOCTL_ENABLE}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&ubh).}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj&ubah}(h]h ]h"]h$]h&]uh1j'hj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMhjQ%ubj)}(h``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID`` Open the stream for a specific **exec_queue_id**. OA queries can be executed on this exec queue. h](j)}(h$``DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID``h]j)}(hj&h]h DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj&ubj()}(hhh]h)}(h`Open the stream for a specific **exec_queue_id**. OA queries can be executed on this exec queue.h](hOpen the stream for a specific }(hj'hhhNhNubh)}(h**exec_queue_id**h]h exec_queue_id}(hj 'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubh0. OA queries can be executed on this exec queue.}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj'ubah}(h]h ]h"]h$]h&]uh1j'hj&ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhjQ%ubj)}(h``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE`` Optional engine instance to pass along with **DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID** or will default to 0. h](j)}(h)``DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE``h]j)}(hj7'h]h%DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE}(hj9'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5'ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj1'ubj()}(hhh]h)}(hfOptional engine instance to pass along with **DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID** or will default to 0.h](h,Optional engine instance to pass along with }(hjP'hhhNhNubh)}(h$**DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID**h]h DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID}(hjX'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP'ubh or will default to 0.}(hjP'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjM'ubah}(h]h ]h"]h$]h&]uh1j'hj1'ubeh}(h]h ]h"]h$]h&]uh1jhjL'hMhjQ%ubj)}(hm``DRM_XE_OA_PROPERTY_NO_PREEMPT`` Allow preemption and timeslicing to be disabled for the stream exec queue. h](j)}(h!``DRM_XE_OA_PROPERTY_NO_PREEMPT``h]j)}(hj'h]hDRM_XE_OA_PROPERTY_NO_PREEMPT}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj}'ubj()}(hhh]h)}(hJAllow preemption and timeslicing to be disabled for the stream exec queue.h]hJAllow preemption and timeslicing to be disabled for the stream exec queue.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj'ubah}(h]h ]h"]h$]h&]uh1j'hj}'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhjQ%ubj)}(hm``DRM_XE_OA_PROPERTY_NUM_SYNCS`` Number of syncs in the sync array specified in **DRM_XE_OA_PROPERTY_SYNCS** h](j)}(h ``DRM_XE_OA_PROPERTY_NUM_SYNCS``h]j)}(hj'h]hDRM_XE_OA_PROPERTY_NUM_SYNCS}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj'ubj()}(hhh]h)}(hKNumber of syncs in the sync array specified in **DRM_XE_OA_PROPERTY_SYNCS**h](h/Number of syncs in the sync array specified in }(hj'hhhNhNubh)}(h**DRM_XE_OA_PROPERTY_SYNCS**h]hDRM_XE_OA_PROPERTY_SYNCS}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj'ubah}(h]h ]h"]h$]h&]uh1j'hj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhjQ%ubj)}(hX_``DRM_XE_OA_PROPERTY_SYNCS`` Pointer to struct **drm_xe_sync** array with array size specified via **DRM_XE_OA_PROPERTY_NUM_SYNCS**. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For **DRM_XE_SYNC_TYPE_USER_FENCE**, **addr** is a user pointer, similar to the VM bind case. h](j)}(h``DRM_XE_OA_PROPERTY_SYNCS``h]j)}(hj(h]hDRM_XE_OA_PROPERTY_SYNCS}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj'ubj()}(hhh]h)}(hXAPointer to struct **drm_xe_sync** array with array size specified via **DRM_XE_OA_PROPERTY_NUM_SYNCS**. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For **DRM_XE_SYNC_TYPE_USER_FENCE**, **addr** is a user pointer, similar to the VM bind case.h](hPointer to struct }(hj(hhhNhNubh)}(h**drm_xe_sync**h]h drm_xe_sync}(hj&(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh% array with array size specified via }(hj(hhhNhNubh)}(h **DRM_XE_OA_PROPERTY_NUM_SYNCS**h]hDRM_XE_OA_PROPERTY_NUM_SYNCS}(hj8(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh. OA configuration will wait till input fences signal. Output fences will signal after the new OA configuration takes effect. For }(hj(hhhNhNubh)}(h**DRM_XE_SYNC_TYPE_USER_FENCE**h]hDRM_XE_SYNC_TYPE_USER_FENCE}(hjJ(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh, }(hj(hhhNhNubh)}(h**addr**h]haddr}(hj\(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(ubh0 is a user pointer, similar to the VM bind case.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubah}(h]h ]h"]h$]h&]uh1j'hj'ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhjQ%ubj)}(h``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE`` Size of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default. h](j)}(h%``DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE``h]j)}(hj(h]h!DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubj()}(hhh]h)}(hSize of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default.h]hSize of OA buffer to be allocated by the driver in bytes. Supported sizes are powers of 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA buffer is allocated by default.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubah}(h]h ]h"]h$]h&]uh1j'hj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhjQ%ubj)}(hd``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS`` Number of reports to wait for before unblocking poll or readh](j)}(h'``DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS``h]j)}(hj(h]h#DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj(ubj()}(hhh]h)}(h0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_xe_eu_stall_property_id (C enum)c.drm_xe_eu_stall_property_idhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_eu_stall_property_idh]j)}(h enum drm_xe_eu_stall_property_idh](j)}(hjSh]henum}(hjf0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjb0hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM"ubj)}(h h]h }(hjt0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjb0hhhjs0hM"ubj)}(hdrm_xe_eu_stall_property_idh]j)}(hj`0h]hdrm_xe_eu_stall_property_id}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjb0hhhjs0hM"ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj^0hhhjs0hM"ubah}(h]jY0ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjs0hM"hj[0hhubj))}(hhh]h)}(h%EU stall sampling input property ids.h]h%EU stall sampling input property ids.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM.hj0hhubah}(h]h ]h"]h$]h&]uh1j(hj[0hhhjs0hM"ubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKj0jLj0jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Constants** ``DRM_XE_EU_STALL_PROP_GT_ID`` **gt_id** of the GT on which EU stall data will be captured. ``DRM_XE_EU_STALL_PROP_SAMPLE_RATE`` Sampling rate in GPU cycles from **sampling_rates** in struct **drm_xe_query_eu_stall** ``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS`` Minimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h](h)}(h **Constants**h]h)}(hj0h]h Constants}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM2hj0ubj )}(hhh](j)}(h\``DRM_XE_EU_STALL_PROP_GT_ID`` **gt_id** of the GT on which EU stall data will be captured. h](j)}(h``DRM_XE_EU_STALL_PROP_GT_ID``h]j)}(hj0h]hDRM_XE_EU_STALL_PROP_GT_ID}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM6hj0ubj()}(hhh]h)}(h<**gt_id** of the GT on which EU stall data will be captured.h](h)}(h **gt_id**h]hgt_id}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh3 of the GT on which EU stall data will be captured.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM5hj0ubah}(h]h ]h"]h$]h&]uh1j'hj0ubeh}(h]h ]h"]h$]h&]uh1jhj0hM6hj0ubj)}(h}``DRM_XE_EU_STALL_PROP_SAMPLE_RATE`` Sampling rate in GPU cycles from **sampling_rates** in struct **drm_xe_query_eu_stall** h](j)}(h$``DRM_XE_EU_STALL_PROP_SAMPLE_RATE``h]j)}(hj11h]h DRM_XE_EU_STALL_PROP_SAMPLE_RATE}(hj31hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/1ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM:hj+1ubj()}(hhh]h)}(hWSampling rate in GPU cycles from **sampling_rates** in struct **drm_xe_query_eu_stall**h](h!Sampling rate in GPU cycles from }(hjJ1hhhNhNubh)}(h**sampling_rates**h]hsampling_rates}(hjR1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ1ubh in struct }(hjJ1hhhNhNubh)}(h**drm_xe_query_eu_stall**h]hdrm_xe_query_eu_stall}(hjd1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ1ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM9hjG1ubah}(h]h ]h"]h$]h&]uh1j'hj+1ubeh}(h]h ]h"]h$]h&]uh1jhjF1hM:hj0ubj)}(h``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS`` Minimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h](j)}(h)``DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS``h]j)}(hj1h]h%DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM>hj1ubj()}(hhh]h)}(htMinimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.h]htMinimum number of EU stall data reports to be present in the kernel buffer before unblocking a blocked poll or read.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=hj1ubah}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hM>hj0ubeh}(h]h ]h"]h$]h&]uh1j hj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj1h]h Description}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMAhj۴hhubh)}(hX;These properties are passed to the driver at open as a chain of **drm_xe_ext_set_property** structures with **property** set to these properties' enums and **value** set to the corresponding values of these properties. **drm_xe_user_extension** base.name should be set to **DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY**.h](h@These properties are passed to the driver at open as a chain of }(hj1hhhNhNubh)}(h**drm_xe_ext_set_property**h]hdrm_xe_ext_set_property}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh structures with }(hj1hhhNhNubh)}(h **property**h]hproperty}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh& set to these properties’ enums and }(hj1hhhNhNubh)}(h **value**h]hvalue}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh6 set to the corresponding values of these properties. }(hj1hhhNhNubh)}(h**drm_xe_user_extension**h]hdrm_xe_user_extension}(hj"2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh base.name should be set to }(hj1hhhNhNubh)}(h***DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY**h]h&DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY}(hj42hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1ubh.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM/hj۴hhubh)}(hWith the file descriptor obtained from open, user space must enable the EU stall stream fd with **DRM_XE_OBSERVATION_IOCTL_ENABLE** before calling read(). EIO errno from read() indicates HW dropped data due to full buffer.h](h`With the file descriptor obtained from open, user space must enable the EU stall stream fd with }(hjM2hhhNhNubh)}(h#**DRM_XE_OBSERVATION_IOCTL_ENABLE**h]hDRM_XE_OBSERVATION_IOCTL_ENABLE}(hjU2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM2ubh[ before calling read(). EIO errno from read() indicates HW dropped data due to full buffer.}(hjM2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM5hj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_query_eu_stall (C struct)c.drm_xe_query_eu_stallhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_query_eu_stallh]j)}(hstruct drm_xe_query_eu_stallh](j)}(hjh]hstruct}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM=ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhj2hM=ubj)}(hdrm_xe_query_eu_stallh]j)}(hj2h]hdrm_xe_query_eu_stall}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj2hhhj2hM=ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj2hhhj2hM=ubah}(h]jz2ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj2hM=hj|2hhubj))}(hhh]h)}(h$Information about EU stall sampling.h]h$Information about EU stall sampling.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMRhj2hhubah}(h]h ]h"]h$]h&]uh1j(hj|2hhhj2hM=ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj2jLj2jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX#**Definition**:: struct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``capabilities`` EU stall capabilities bit-mask ``record_size`` size of each EU stall data record ``per_xecore_buf_size`` internal per XeCore buffer size ``reserved`` Reserved ``num_sampling_rates`` Number of sampling rates in **sampling_rates** array ``sampling_rates`` Flexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ubh:}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMVhj2ubjt)}(hXstruct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; };h]hXstruct drm_xe_query_eu_stall { __u64 extensions; __u64 capabilities; #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0); __u64 record_size; __u64 per_xecore_buf_size; __u64 reserved[5]; __u64 num_sampling_rates; __u64 sampling_rates[]; };}hj3sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMXhj2ubh)}(h **Members**h]h)}(hj3h]hMembers}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMchj2ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj63h]h extensions}(hj83hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj43ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMZhj03ubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjO3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjK3hMZhjL3ubah}(h]h ]h"]h$]h&]uh1j'hj03ubeh}(h]h ]h"]h$]h&]uh1jhjK3hMZhj-3ubj)}(h0``capabilities`` EU stall capabilities bit-mask h](j)}(h``capabilities``h]j)}(hjo3h]h capabilities}(hjq3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm3ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM]hji3ubj()}(hhh]h)}(hEU stall capabilities bit-maskh]hEU stall capabilities bit-mask}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hM]hj3ubah}(h]h ]h"]h$]h&]uh1j'hji3ubeh}(h]h ]h"]h$]h&]uh1jhj3hM]hj-3ubj)}(h2``record_size`` size of each EU stall data record h](j)}(h``record_size``h]j)}(hj3h]h record_size}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMahj3ubj()}(hhh]h)}(h!size of each EU stall data recordh]h!size of each EU stall data record}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMahj3ubah}(h]h ]h"]h$]h&]uh1j'hj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMahj-3ubj)}(h8``per_xecore_buf_size`` internal per XeCore buffer size h](j)}(h``per_xecore_buf_size``h]j)}(hj3h]hper_xecore_buf_size}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMdhj3ubj()}(hhh]h)}(hinternal per XeCore buffer sizeh]hinternal per XeCore buffer size}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMdhj3ubah}(h]h ]h"]h$]h&]uh1j'hj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMdhj-3ubj)}(h``reserved`` Reserved h](j)}(h ``reserved``h]j)}(hj4h]hreserved}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMghj4ubj()}(hhh]h)}(hReservedh]hReserved}(hj34hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/4hMghj04ubah}(h]h ]h"]h$]h&]uh1j'hj4ubeh}(h]h ]h"]h$]h&]uh1jhj/4hMghj-3ubj)}(hL``num_sampling_rates`` Number of sampling rates in **sampling_rates** array h](j)}(h``num_sampling_rates``h]j)}(hjS4h]hnum_sampling_rates}(hjU4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ4ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMjhjM4ubj()}(hhh]h)}(h4Number of sampling rates in **sampling_rates** arrayh](hNumber of sampling rates in }(hjl4hhhNhNubh)}(h**sampling_rates**h]hsampling_rates}(hjt4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl4ubh array}(hjl4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjh4hMjhji4ubah}(h]h ]h"]h$]h&]uh1j'hjM4ubeh}(h]h ]h"]h$]h&]uh1jhjh4hMjhj-3ubj)}(h``sampling_rates`` Flexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h](j)}(h``sampling_rates``h]j)}(hj4h]hsampling_rates}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMohj4ubj()}(hhh]h)}(hzFlexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.h]hzFlexible array of sampling rates sorted in the fastest to slowest order. Sampling rates are specified in GPU clock cycles.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMnhj4ubah}(h]h ]h"]h$]h&]uh1j'hj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMohj-3ubeh}(h]h ]h"]h$]h&]uh1j hj2ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴ hhhjhM ubh)}(h**Description**h]h)}(hj4h]h Description}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMshj۴hhubh)}(hIf a query is made with a struct **drm_xe_device_query** where .query is equal to **DRM_XE_DEVICE_QUERY_EU_STALL**, then the reply uses struct **drm_xe_query_eu_stall** in .data.h](h!If a query is made with a struct }(hj4hhhNhNubh)}(h**drm_xe_device_query**h]hdrm_xe_device_query}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubh where .query is equal to }(hj4hhhNhNubh)}(h **DRM_XE_DEVICE_QUERY_EU_STALL**h]hDRM_XE_DEVICE_QUERY_EU_STALL}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubh, then the reply uses struct }(hj4hhhNhNubh)}(h**drm_xe_query_eu_stall**h]hdrm_xe_query_eu_stall}(hj#5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4ubh in .data.}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMShj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_xe_madvise (C struct)c.drm_xe_madvisehNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_madviseh]j)}(hstruct drm_xe_madviseh](j)}(hjh]hstruct}(hjU5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ5hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMZubj)}(h h]h }(hjc5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ5hhhjb5hMZubj)}(hdrm_xe_madviseh]j)}(hjO5h]hdrm_xe_madvise}(hju5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjq5ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjQ5hhhjb5hMZubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjM5hhhjb5hMZubah}(h]jH5ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjb5hMZhjJ5hhubj))}(hhh]h)}(h'Input of :c:type:`DRM_IOCTL_XE_MADVISE`h](h Input of }(hj5hhhNhNubh)}(h:c:type:`DRM_IOCTL_XE_MADVISE`h]j)}(hj5h]hDRM_IOCTL_XE_MADVISE}(hj5hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjO5sbc.drm_xe_madviseasbj) DRM_IOCTL_XE_MADVISEuh1hhjhKhj5ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMuhj5hhubah}(h]h ]h"]h$]h&]uh1j(hjJ5hhhjb5hMZubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj5jLj5jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_madvise { __u64 extensions; __u64 start; __u64 range; __u32 vm_id; #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0; #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1; #define DRM_XE_MEM_RANGE_ATTR_PAT 2; #define DRM_XE_VMA_ATTR_PURGEABLE_STATE 3; __u32 type; union { struct { #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0; #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1; __u32 devmem_fd; #define DRM_XE_MIGRATE_ALL_PAGES 0; #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1; __u16 migration_policy; __u16 region_instance; __u64 reserved; } preferred_mem_loc; struct { #define DRM_XE_ATOMIC_UNDEFINED 0; #define DRM_XE_ATOMIC_DEVICE 1; #define DRM_XE_ATOMIC_GLOBAL 2; #define DRM_XE_ATOMIC_CPU 3; __u32 val; __u32 pad; __u64 reserved; } atomic; struct { __u32 val; __u32 pad; __u64 reserved; } pat_index; struct { #define DRM_XE_VMA_PURGEABLE_STATE_WILLNEED 0; #define DRM_XE_VMA_PURGEABLE_STATE_DONTNEED 1; __u32 val; __u32 pad; __u64 retained_ptr; } purge_state_val; }; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``start`` start of the virtual address range ``range`` size of the virtual address range ``vm_id`` vm_id of the virtual range ``type`` type of attribute ``{unnamed_union}`` anonymous ``preferred_mem_loc`` preferred memory location Used when **type** == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC Supported values for **preferred_mem_loc.devmem_fd**: - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc Supported values for **preferred_mem_loc.migration_policy**: - DRM_XE_MIGRATE_ALL_PAGES - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES ``preferred_mem_loc.devmem_fd`` Device file-descriptor of the device where the preferred memory is located, or one of the above special values. Please also see **preferred_mem_loc.region_instance** below. ``preferred_mem_loc.migration_policy`` Page migration policy ``preferred_mem_loc.region_instance`` Region instance. MBZ if **devmem_fd** <= :c:type:`DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE`. Otherwise should point to the desired device VRAM instance of the device indicated by **preferred_mem_loc.devmem_fd**. ``preferred_mem_loc.reserved`` Reserved ``atomic`` Atomic access policy Used when **type** == DRM_XE_MEM_RANGE_ATTR_ATOMIC. Supported values for **atomic.val**: - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. Support both GPU and CPU atomic operations for system allocator. Support GPU atomic operations for normal(bo) allocator. - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations. - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations. - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported. ``atomic.val`` value of atomic operation ``atomic.pad`` MBZ ``atomic.reserved`` Reserved ``pat_index`` Page attribute table index Used when **type** == DRM_XE_MEM_RANGE_ATTR_PAT. ``pat_index.val`` PAT index value ``pat_index.pad`` MBZ ``pat_index.reserved`` Reserved ``purge_state_val`` Purgeable state configuration Used when **type** == DRM_XE_VMA_ATTR_PURGEABLE_STATE. Configures the purgeable state of buffer objects in the specified virtual address range. This allows applications to hint to the kernel about bo's usage patterns for better memory management. By default all VMAs are in WILLNEED state. Supported values for **purge_state_val.val**: - DRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed. If the BO was previously purged, the kernel sets the __u32 at **retained_ptr** to 0 (backing store lost) so the application knows it must recreate the BO. - DRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at **retained_ptr** to 1 if the backing store still exists (not yet purged), or 0 if it was already purged. Important: Once marked as DONTNEED, touching the BO's memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state. To transition back: use WILLNEED and check **retained_ptr** — if 0, backing store was lost and the BO must be recreated. The following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCES ``purge_state_val.val`` value for DRM_XE_VMA_ATTR_PURGEABLE_STATE ``purge_state_val.pad`` MBZ ``purge_state_val.retained_ptr`` Pointer to a __u32 output field for backing store status. Userspace must initialize the __u32 value at this address to 0 before the ioctl. Kernel writes a __u32 after the operation: - 1 if backing store exists (not purged) - 0 if backing store was purged If userspace fails to initialize to 0, ioctl returns -EINVAL. This ensures a safe default (0 = assume purged) if kernel cannot write the result. Similar to i915's drm_i915_gem_madvise.retained field. ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5ubh:}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMyhj5ubjt)}(hX-struct drm_xe_madvise { __u64 extensions; __u64 start; __u64 range; __u32 vm_id; #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0; #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1; #define DRM_XE_MEM_RANGE_ATTR_PAT 2; #define DRM_XE_VMA_ATTR_PURGEABLE_STATE 3; __u32 type; union { struct { #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0; #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1; __u32 devmem_fd; #define DRM_XE_MIGRATE_ALL_PAGES 0; #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1; __u16 migration_policy; __u16 region_instance; __u64 reserved; } preferred_mem_loc; struct { #define DRM_XE_ATOMIC_UNDEFINED 0; #define DRM_XE_ATOMIC_DEVICE 1; #define DRM_XE_ATOMIC_GLOBAL 2; #define DRM_XE_ATOMIC_CPU 3; __u32 val; __u32 pad; __u64 reserved; } atomic; struct { __u32 val; __u32 pad; __u64 reserved; } pat_index; struct { #define DRM_XE_VMA_PURGEABLE_STATE_WILLNEED 0; #define DRM_XE_VMA_PURGEABLE_STATE_DONTNEED 1; __u32 val; __u32 pad; __u64 retained_ptr; } purge_state_val; }; __u64 reserved[2]; };h]hX-struct drm_xe_madvise { __u64 extensions; __u64 start; __u64 range; __u32 vm_id; #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0; #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1; #define DRM_XE_MEM_RANGE_ATTR_PAT 2; #define DRM_XE_VMA_ATTR_PURGEABLE_STATE 3; __u32 type; union { struct { #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0; #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1; __u32 devmem_fd; #define DRM_XE_MIGRATE_ALL_PAGES 0; #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1; __u16 migration_policy; __u16 region_instance; __u64 reserved; } preferred_mem_loc; struct { #define DRM_XE_ATOMIC_UNDEFINED 0; #define DRM_XE_ATOMIC_DEVICE 1; #define DRM_XE_ATOMIC_GLOBAL 2; #define DRM_XE_ATOMIC_CPU 3; __u32 val; __u32 pad; __u64 reserved; } atomic; struct { __u32 val; __u32 pad; __u64 reserved; } pat_index; struct { #define DRM_XE_VMA_PURGEABLE_STATE_WILLNEED 0; #define DRM_XE_VMA_PURGEABLE_STATE_DONTNEED 1; __u32 val; __u32 pad; __u64 retained_ptr; } purge_state_val; }; __u64 reserved[2]; };}hj5sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM{hj5ubh)}(h **Members**h]h)}(hj 6h]hMembers}(hj 6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 6ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj5ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hj*6h]h extensions}(hj,6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj$6ubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjC6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?6hMhj@6ubah}(h]h ]h"]h$]h&]uh1j'hj$6ubeh}(h]h ]h"]h$]h&]uh1jhj?6hMhj!6ubj)}(h-``start`` start of the virtual address range h](j)}(h ``start``h]j)}(hjc6h]hstart}(hje6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj]6ubj()}(hhh]h)}(h"start of the virtual address rangeh]h"start of the virtual address range}(hj|6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx6hMhjy6ubah}(h]h ]h"]h$]h&]uh1j'hj]6ubeh}(h]h ]h"]h$]h&]uh1jhjx6hMhj!6ubj)}(h,``range`` size of the virtual address range h](j)}(h ``range``h]j)}(hj6h]hrange}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj6ubj()}(hhh]h)}(h!size of the virtual address rangeh]h!size of the virtual address range}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj!6ubj)}(h%``vm_id`` vm_id of the virtual range h](j)}(h ``vm_id``h]j)}(hj6h]hvm_id}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj6ubj()}(hhh]h)}(hvm_id of the virtual rangeh]hvm_id of the virtual range}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1j'hj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj!6ubj)}(h``type`` type of attribute h](j)}(h``type``h]j)}(hj7h]htype}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 7ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj7ubj()}(hhh]h)}(htype of attributeh]htype of attribute}(hj'7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#7hMhj$7ubah}(h]h ]h"]h$]h&]uh1j'hj7ubeh}(h]h ]h"]h$]h&]uh1jhj#7hMhj!6ubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjG7h]h{unnamed_union}}(hjI7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE7ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhKhjA7ubj()}(hhh]h)}(h anonymoush]h anonymous}(hj`7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\7hKhj]7ubah}(h]h ]h"]h$]h&]uh1j'hjA7ubeh}(h]h ]h"]h$]h&]uh1jhj\7hKhj!6ubj)}(hX``preferred_mem_loc`` preferred memory location Used when **type** == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC Supported values for **preferred_mem_loc.devmem_fd**: - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc Supported values for **preferred_mem_loc.migration_policy**: - DRM_XE_MIGRATE_ALL_PAGES - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES h](j)}(h``preferred_mem_loc``h]j)}(hj7h]hpreferred_mem_loc}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~7ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhjz7ubj()}(hhh](h)}(hpreferred memory locationh]hpreferred memory location}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj7ubh)}(h9Used when **type** == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOCh](h Used when }(hj7hhhNhNubh)}(h**type**h]htype}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubh' == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj7ubj )}(hhh](j)}(hSupported values for **preferred_mem_loc.devmem_fd**: - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc h](j)}(h5Supported values for **preferred_mem_loc.devmem_fd**:h](hSupported values for }(hj7hhhNhNubh)}(h**preferred_mem_loc.devmem_fd**h]hpreferred_mem_loc.devmem_fd}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7ubh:}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj7ubj()}(hhh]j )}(hhh](j )}(hLDRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loch]h)}(hj7h]hLDRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj7ubah}(h]h ]h"]h$]h&]uh1j hj7ubj )}(h?DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc h]h)}(h>DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loch]h>DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj8ubah}(h]h ]h"]h$]h&]uh1j hj7ubeh}(h]h ]h"]h$]h&]j) j* uh1j hj8hMhj7ubah}(h]h ]h"]h$]h&]uh1j'hj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMhj7ubj)}(h{Supported values for **preferred_mem_loc.migration_policy**: - DRM_XE_MIGRATE_ALL_PAGES - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES h](j)}(h=ubj )}(hXDRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at **retained_ptr** to 1 if the backing store still exists (not yet purged), or 0 if it was already purged. Important: Once marked as DONTNEED, touching the BO's memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state. To transition back: use WILLNEED and check **retained_ptr** — if 0, backing store was lost and the BO must be recreated. The following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCES h](h)}(hX-DRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at **retained_ptr** to 1 if the backing store still exists (not yet purged), or 0 if it was already purged.h](hDRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently needed. Kernel may purge it under memory pressure to reclaim memory. Only applies to non-shared BOs. The kernel sets the __u32 at }(hjp=hhhNhNubh)}(h**retained_ptr**h]h retained_ptr}(hjx=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp=ubhX to 1 if the backing store still exists (not yet purged), or 0 if it was already purged.}(hjp=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjl=ubh)}(hImportant: Once marked as DONTNEED, touching the BO's memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state.h]hImportant: Once marked as DONTNEED, touching the BO’s memory is undefined behavior. It may succeed temporarily (before the kernel purges the backing store) but will suddenly fail once the BO transitions to PURGED state.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjl=ubh)}(hzTo transition back: use WILLNEED and check **retained_ptr** — if 0, backing store was lost and the BO must be recreated.h](h+To transition back: use WILLNEED and check }(hj=hhhNhNubh)}(h**retained_ptr**h]h retained_ptr}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubh? — if 0, backing store was lost and the BO must be recreated.}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjl=ubh)}(hXJThe following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCESh]hXJThe following operations are blocked in DONTNEED state to prevent the BO from being re-mapped after madvise: - New mmap() calls: Fail with -EBUSY - VM_BIND operations: Fail with -EBUSY - New dma-buf exports: Fail with -EBUSY - CPU page faults (existing mmap): Fail with SIGBUS - GPU page faults (fault-mode VMs): Fail with -EACCES}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjl=ubeh}(h]h ]h"]h$]h&]uh1j hj>=ubeh}(h]h ]h"]h$]h&]j) j* uh1j hje=hM hj;=ubah}(h]h ]h"]h$]h&]uh1j'hj=ubeh}(h]h ]h"]h$]h&]uh1jhj<hM" hj=ubah}(h]h ]h"]h$]h&]uh1j hj<ubeh}(h]h ]h"]h$]h&]uh1j'hj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hM" hj!6ubj)}(hB``purge_state_val.val`` value for DRM_XE_VMA_ATTR_PURGEABLE_STATE h](j)}(h``purge_state_val.val``h]j)}(hj>h]hpurge_state_val.val}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM' hj=ubj()}(hhh]h)}(h)value for DRM_XE_VMA_ATTR_PURGEABLE_STATEh]h)value for DRM_XE_VMA_ATTR_PURGEABLE_STATE}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hM' hj>ubah}(h]h ]h"]h$]h&]uh1j'hj=ubeh}(h]h ]h"]h$]h&]uh1jhj>hM' hj!6ubj)}(h``purge_state_val.pad`` MBZ h](j)}(h``purge_state_val.pad``h]j)}(hj9>h]hpurge_state_val.pad}(hj;>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM* hj3>ubj()}(hhh]h)}(hMBZh]hMBZ}(hjR>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjN>hM* hjO>ubah}(h]h ]h"]h$]h&]uh1j'hj3>ubeh}(h]h ]h"]h$]h&]uh1jhjN>hM* hj!6ubj)}(hX``purge_state_val.retained_ptr`` Pointer to a __u32 output field for backing store status. Userspace must initialize the __u32 value at this address to 0 before the ioctl. Kernel writes a __u32 after the operation: - 1 if backing store exists (not purged) - 0 if backing store was purged If userspace fails to initialize to 0, ioctl returns -EINVAL. This ensures a safe default (0 = assume purged) if kernel cannot write the result. Similar to i915's drm_i915_gem_madvise.retained field. h](j)}(h ``purge_state_val.retained_ptr``h]j)}(hjr>h]hpurge_state_val.retained_ptr}(hjt>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjp>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM: hjl>ubj()}(hhh](h)}(h9Pointer to a __u32 output field for backing store status.h]h9Pointer to a __u32 output field for backing store status.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM- hj>ubh)}(hUserspace must initialize the __u32 value at this address to 0 before the ioctl. Kernel writes a __u32 after the operation: - 1 if backing store exists (not purged) - 0 if backing store was purgedh]hUserspace must initialize the __u32 value at this address to 0 before the ioctl. Kernel writes a __u32 after the operation: - 1 if backing store exists (not purged) - 0 if backing store was purged}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM0 hj>ubh)}(hIf userspace fails to initialize to 0, ioctl returns -EINVAL. This ensures a safe default (0 = assume purged) if kernel cannot write the result.h]hIf userspace fails to initialize to 0, ioctl returns -EINVAL. This ensures a safe default (0 = assume purged) if kernel cannot write the result.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM6 hj>ubh)}(h6Similar to i915's drm_i915_gem_madvise.retained field.h]h8Similar to i915’s drm_i915_gem_madvise.retained field.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hM: hj>ubeh}(h]h ]h"]h$]h&]uh1j'hjl>ubeh}(h]h ]h"]h$]h&]uh1jhj>hM: hj!6ubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hj>h]hreserved}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM? hj>ubj()}(hhh]h)}(hReservedh]hReserved}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM@ hj>ubah}(h]h ]h"]h$]h&]uh1j'hj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hM? hj!6ubeh}(h]h ]h"]h$]h&]uh1j hj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hj?h]h Description}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMC hj۴hhubh)}(hThis structure is used to set memory attributes for a virtual address range in a VM. The type of attribute is specified by **type**, and the corresponding union member is used to provide additional parameters for **type**.h](h{This structure is used to set memory attributes for a virtual address range in a VM. The type of attribute is specified by }(hj1?hhhNhNubh)}(h**type**h]htype}(hj9?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1?ubhR, and the corresponding union member is used to provide additional parameters for }(hj1?hhhNhNubh)}(h**type**h]htype}(hjK?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1?ubh.}(hj1?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMvhj۴hhubj )}(hhh]j)}(hXSupported attribute types: - DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location. - DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy. - DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index. - DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs. h](j)}(hSupported attribute types:h]hSupported attribute types:}(hjk?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~hjg?ubj()}(hhh]j )}(hhh](j )}(hCDRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location.h]h)}(hj?h]hCDRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM{hj?ubah}(h]h ]h"]h$]h&]uh1j hj}?ubj )}(h7DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy.h]h)}(hj?h]h7DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM|hj?ubah}(h]h ]h"]h$]h&]uh1j hj}?ubj )}(h:DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index.h]h)}(hj?h]h:DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM}hj?ubah}(h]h ]h"]h$]h&]uh1j hj}?ubj )}(h>DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs. h]h)}(h=DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs.h]h=DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjy?hM~hj?ubah}(h]h ]h"]h$]h&]uh1j hj}?ubeh}(h]h ]h"]h$]h&]j) j* uh1j hj?hM{hjz?ubah}(h]h ]h"]h$]h&]uh1j'hjg?ubeh}(h]h ]h"]h$]h&]uh1jhjy?hM~hjd?ubah}(h]h ]h"]h$]h&]uh1j hj۴hhhjhM ubh)}(h **Example**h]h)}(hj?h]hExample}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubjt)}(hstruct drm_xe_madvise madvise = { .vm_id = vm_id, .start = 0x100000, .range = 0x2000, .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC, .atomic_val = DRM_XE_ATOMIC_DEVICE, }; ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise);h]hstruct drm_xe_madvise madvise = { .vm_id = vm_id, .start = 0x100000, .range = 0x2000, .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC, .atomic_val = DRM_XE_ATOMIC_DEVICE, }; ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise);}hj@sbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMhj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_xe_mem_range_attr (C struct)c.drm_xe_mem_range_attrhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_mem_range_attrh]j)}(hstruct drm_xe_mem_range_attrh](j)}(hjh]hstruct}(hj9@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5@hhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMubj)}(h h]h }(hjG@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5@hhhjF@hMubj)}(hdrm_xe_mem_range_attrh]j)}(hj3@h]hdrm_xe_mem_range_attr}(hjY@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU@ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj5@hhhjF@hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj1@hhhjF@hMubah}(h]j,@ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjF@hMhj.@hhubj))}(hhh]h)}(h:Output of :c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS`h](h Output of }(hj{@hhhNhNubh)}(h0:c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS`h]j)}(hj@h]h&DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS}(hj@hhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jj3@sbc.drm_xe_mem_range_attrasbj) &DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRSuh1hhjhKhj{@ubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMD hjx@hhubah}(h]h ]h"]h$]h&]uh1j(hj.@hhhjF@hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj@jLj@jMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_mem_range_attr { __u64 extensions; __u64 start; __u64 end; struct { __u32 devmem_fd; __u32 migration_policy; } preferred_mem_loc; struct { __u32 val; __u32 reserved; } atomic; struct { __u32 val; __u32 reserved; } pat_index; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``start`` start of the memory range ``end`` end of the memory range ``preferred_mem_loc`` preferred memory location ``preferred_mem_loc.devmem_fd`` fd for preferred loc ``preferred_mem_loc.migration_policy`` Page migration policy ``atomic`` Atomic access policy ``atomic.val`` atomic attribute ``atomic.reserved`` Reserved ``pat_index`` Page attribute table index ``pat_index.val`` PAT index ``pat_index.reserved`` Reserved ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubh:}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMH hj@ubjt)}(hX\struct drm_xe_mem_range_attr { __u64 extensions; __u64 start; __u64 end; struct { __u32 devmem_fd; __u32 migration_policy; } preferred_mem_loc; struct { __u32 val; __u32 reserved; } atomic; struct { __u32 val; __u32 reserved; } pat_index; __u64 reserved[2]; };h]hX\struct drm_xe_mem_range_attr { __u64 extensions; __u64 start; __u64 end; struct { __u32 devmem_fd; __u32 migration_policy; } preferred_mem_loc; struct { __u32 val; __u32 reserved; } atomic; struct { __u32 val; __u32 reserved; } pat_index; __u64 reserved[2]; };}hj@sbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMJ hj@ubh)}(h **Members**h]h)}(hj@h]hMembers}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM] hj@ubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjAh]h extensions}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Aubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMV hjAubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj'AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#AhMV hj$Aubah}(h]h ]h"]h$]h&]uh1j'hjAubeh}(h]h ]h"]h$]h&]uh1jhj#AhMV hjAubj)}(h$``start`` start of the memory range h](j)}(h ``start``h]j)}(hjGAh]hstart}(hjIAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMY hjAAubj()}(hhh]h)}(hstart of the memory rangeh]hstart of the memory range}(hj`AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\AhMY hj]Aubah}(h]h ]h"]h$]h&]uh1j'hjAAubeh}(h]h ]h"]h$]h&]uh1jhj\AhMY hjAubj)}(h ``end`` end of the memory range h](j)}(h``end``h]j)}(hjAh]hend}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~Aubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM\ hjzAubj()}(hhh]h)}(hend of the memory rangeh]hend of the memory range}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhM\ hjAubah}(h]h ]h"]h$]h&]uh1j'hjzAubeh}(h]h ]h"]h$]h&]uh1jhjAhM\ hjAubj)}(h0``preferred_mem_loc`` preferred memory location h](j)}(h``preferred_mem_loc``h]j)}(hjAh]hpreferred_mem_loc}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM_ hjAubj()}(hhh]h)}(hpreferred memory locationh]hpreferred memory location}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhM_ hjAubah}(h]h ]h"]h$]h&]uh1j'hjAubeh}(h]h ]h"]h$]h&]uh1jhjAhM_ hjAubj)}(h5``preferred_mem_loc.devmem_fd`` fd for preferred loc h](j)}(h``preferred_mem_loc.devmem_fd``h]j)}(hjAh]hpreferred_mem_loc.devmem_fd}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMa hjAubj()}(hhh]h)}(hfd for preferred loch]hfd for preferred loc}(hj BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMa hjBubah}(h]h ]h"]h$]h&]uh1j'hjAubeh}(h]h ]h"]h$]h&]uh1jhjBhMa hjAubj)}(h=``preferred_mem_loc.migration_policy`` Page migration policy h](j)}(h&``preferred_mem_loc.migration_policy``h]j)}(hj+Bh]h"preferred_mem_loc.migration_policy}(hj-BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)Bubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMd hj%Bubj()}(hhh]h)}(hPage migration policyh]hPage migration policy}(hjDBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@BhMd hjABubah}(h]h ]h"]h$]h&]uh1j'hj%Bubeh}(h]h ]h"]h$]h&]uh1jhj@BhMd hjAubj)}(h ``atomic`` Atomic access policy h](j)}(h ``atomic``h]j)}(hjdBh]hatomic}(hjfBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbBubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMh hj^Bubj()}(hhh]h)}(hAtomic access policyh]hAtomic access policy}(hj}BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyBhMh hjzBubah}(h]h ]h"]h$]h&]uh1j'hj^Bubeh}(h]h ]h"]h$]h&]uh1jhjyBhMh hjAubj)}(h ``atomic.val`` atomic attribute h](j)}(h``atomic.val``h]j)}(hjBh]h atomic.val}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMj hjBubj()}(hhh]h)}(hatomic attributeh]hatomic attribute}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMj hjBubah}(h]h ]h"]h$]h&]uh1j'hjBubeh}(h]h ]h"]h$]h&]uh1jhjBhMj hjAubj)}(h``atomic.reserved`` Reserved h](j)}(h``atomic.reserved``h]j)}(hjBh]hatomic.reserved}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMm hjBubj()}(hhh]h)}(hReservedh]hReserved}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMm hjBubah}(h]h ]h"]h$]h&]uh1j'hjBubeh}(h]h ]h"]h$]h&]uh1jhjBhMm hjAubj)}(h)``pat_index`` Page attribute table index h](j)}(h ``pat_index``h]j)}(hjCh]h pat_index}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Cubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMq hj Cubj()}(hhh]h)}(hPage attribute table indexh]hPage attribute table index}(hj(ChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$ChMq hj%Cubah}(h]h ]h"]h$]h&]uh1j'hj Cubeh}(h]h ]h"]h$]h&]uh1jhj$ChMq hjAubj)}(h``pat_index.val`` PAT index h](j)}(h``pat_index.val``h]j)}(hjHCh]h pat_index.val}(hjJChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMs hjBCubj()}(hhh]h)}(h PAT indexh]h PAT index}(hjaChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]ChMs hj^Cubah}(h]h ]h"]h$]h&]uh1j'hjBCubeh}(h]h ]h"]h$]h&]uh1jhj]ChMs hjAubj)}(h ``pat_index.reserved`` Reserved h](j)}(h``pat_index.reserved``h]j)}(hjCh]hpat_index.reserved}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMv hj{Cubj()}(hhh]h)}(hReservedh]hReserved}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMv hjCubah}(h]h ]h"]h$]h&]uh1j'hj{Cubeh}(h]h ]h"]h$]h&]uh1jhjChMv hjAubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjCh]hreserved&}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMy hjCubj()}(hhh]h)}(hReservedh]hReserved}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMz hjCubah}(h]h ]h"]h$]h&]uh1j'hjCubeh}(h]h ]h"]h$]h&]uh1jhjChMy hjAubeh}(h]h ]h"]h$]h&]uh1j hj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjCh]h Description}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM} hj۴hhubh)}(hThis structure is provided by userspace and filled by KMD in response to the DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS ioctl. It describes memory attributes of a memory ranges within a user specified address range in a VM.h]hThis structure is provided by userspace and filled by KMD in response to the DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS ioctl. It describes memory attributes of a memory ranges within a user specified address range in a VM.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhME hj۴hhubh)}(hXThe structure includes information such as atomic access policy, page attribute table (PAT) index, and preferred memory location. Userspace allocates an array of these structures and passes a pointer to the ioctl to retrieve attributes for each memory rangesh]hXThe structure includes information such as atomic access policy, page attribute table (PAT) index, and preferred memory location. Userspace allocates an array of these structures and passes a pointer to the ioctl to retrieve attributes for each memory ranges}(hj"DhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMI hj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)drm_xe_vm_query_mem_range_attr (C struct) c.drm_xe_vm_query_mem_range_attrhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_vm_query_mem_range_attrh]j)}(h%struct drm_xe_vm_query_mem_range_attrh](j)}(hjh]hstruct}(hjJDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFDhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhMQ ubj)}(h h]h }(hjXDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFDhhhjWDhMQ ubj)}(hdrm_xe_vm_query_mem_range_attrh]j)}(hjDDh]hdrm_xe_vm_query_mem_range_attr}(hjjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfDubah}(h]h ](j jeh"]h$]h&]jjuh1jhjFDhhhjWDhMQ ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjBDhhhjWDhMQ ubah}(h]j=Dah ](j j!eh"]h$]h&]j%j&)j'huh1jhjWDhMQ hj?Dhhubj))}(hhh]h)}(h7Input of :c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES`h](h Input of }(hjDhhhNhNubh)}(h.:c:type:`DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES`h]j)}(hjDh]h$DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES}(hjDhhhNhNubah}(h]h ](j jEc-typeeh"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]refdocj refdomainjEreftypetype refexplicitrefwarnj! j$ )}j' ]j)}jjDDsb c.drm_xe_vm_query_mem_range_attrasbj) $DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTESuh1hhjhKhjDubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM~ hjDhhubah}(h]h ]h"]h$]h&]uh1j(hj?DhhhjWDhMQ ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjDjLjDjMjNjOuh1jhhhj۴hjhM ubjQ)}(hX**Definition**:: struct drm_xe_vm_query_mem_range_attr { __u64 extensions; __u32 vm_id; __u32 num_mem_ranges; __u64 start; __u64 range; __u64 sizeof_mem_range_attr; __u64 vector_of_mem_attr; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``vm_id`` vm_id of the virtual range ``num_mem_ranges`` number of mem_ranges in range ``start`` start of the virtual address range ``range`` size of the virtual address range ``sizeof_mem_range_attr`` size of struct drm_xe_mem_range_attr ``vector_of_mem_attr`` userptr to array of struct drm_xe_mem_range_attr ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDubh:}(hjDhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjDubjt)}(hstruct drm_xe_vm_query_mem_range_attr { __u64 extensions; __u32 vm_id; __u32 num_mem_ranges; __u64 start; __u64 range; __u64 sizeof_mem_range_attr; __u64 vector_of_mem_attr; __u64 reserved[2]; };h]hstruct drm_xe_vm_query_mem_range_attr { __u64 extensions; __u32 vm_id; __u32 num_mem_ranges; __u64 start; __u64 range; __u64 sizeof_mem_range_attr; __u64 vector_of_mem_attr; __u64 reserved[2]; };}hjDsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjDubh)}(h **Members**h]h)}(hjEh]hMembers}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjDubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjEh]h extensions}(hj!EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjEubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hj8EhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4EhM hj5Eubah}(h]h ]h"]h$]h&]uh1j'hjEubeh}(h]h ]h"]h$]h&]uh1jhj4EhM hjEubj)}(h%``vm_id`` vm_id of the virtual range h](j)}(h ``vm_id``h]j)}(hjXEh]hvm_id}(hjZEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVEubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjREubj()}(hhh]h)}(hvm_id of the virtual rangeh]hvm_id of the virtual range}(hjqEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmEhM hjnEubah}(h]h ]h"]h$]h&]uh1j'hjREubeh}(h]h ]h"]h$]h&]uh1jhjmEhM hjEubj)}(h1``num_mem_ranges`` number of mem_ranges in range h](j)}(h``num_mem_ranges``h]j)}(hjEh]hnum_mem_ranges}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjEubj()}(hhh]h)}(hnumber of mem_ranges in rangeh]hnumber of mem_ranges in range}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhM hjEubah}(h]h ]h"]h$]h&]uh1j'hjEubeh}(h]h ]h"]h$]h&]uh1jhjEhM hjEubj)}(h-``start`` start of the virtual address range h](j)}(h ``start``h]j)}(hjEh]hstart}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjEubj()}(hhh]h)}(h"start of the virtual address rangeh]h"start of the virtual address range}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhM hjEubah}(h]h ]h"]h$]h&]uh1j'hjEubeh}(h]h ]h"]h$]h&]uh1jhjEhM hjEubj)}(h,``range`` size of the virtual address range h](j)}(h ``range``h]j)}(hjFh]hrange}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjEubj()}(hhh]h)}(h!size of the virtual address rangeh]h!size of the virtual address range}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhM hjFubah}(h]h ]h"]h$]h&]uh1j'hjEubeh}(h]h ]h"]h$]h&]uh1jhjFhM hjEubj)}(h?``sizeof_mem_range_attr`` size of struct drm_xe_mem_range_attr h](j)}(h``sizeof_mem_range_attr``h]j)}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:Fubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj6Fubj()}(hhh]h)}(h$size of struct drm_xe_mem_range_attrh]h$size of struct drm_xe_mem_range_attr}(hjUFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQFhM hjRFubah}(h]h ]h"]h$]h&]uh1j'hj6Fubeh}(h]h ]h"]h$]h&]uh1jhjQFhM hjEubj)}(hH``vector_of_mem_attr`` userptr to array of struct drm_xe_mem_range_attr h](j)}(h``vector_of_mem_attr``h]j)}(hjuFh]hvector_of_mem_attr}(hjwFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsFubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjoFubj()}(hhh]h)}(h0userptr to array of struct drm_xe_mem_range_attrh]h0userptr to array of struct drm_xe_mem_range_attr}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhM hjFubah}(h]h ]h"]h$]h&]uh1j'hjoFubeh}(h]h ]h"]h$]h&]uh1jhjFhM hjEubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjFh]hreserved}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjFubj()}(hhh]h)}(hReservedh]hReserved}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjFubah}(h]h ]h"]h$]h&]uh1j'hjFubeh}(h]h ]h"]h$]h&]uh1jhjFhM hjEubeh}(h]h ]h"]h$]h&]uh1j hjDubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjFh]h Description}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj۴hhubh)}(hX This structure is used to query memory attributes of memory regions within a user specified address range in a VM. It provides detailed information about each memory range, including atomic access policy, page attribute table (PAT) index, and preferred memory location.h]hX This structure is used to query memory attributes of memory regions within a user specified address range in a VM. It provides detailed information about each memory range, including atomic access policy, page attribute table (PAT) index, and preferred memory location.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj۴hhubh)}(hXGUserspace first calls the ioctl with **num_mem_ranges** = 0, **sizeof_mem_ranges_attr** = 0 and **vector_of_vma_mem_attr** = NULL to retrieve the number of memory regions and size of each memory range attribute. Then, it allocates a buffer of that size and calls the ioctl again to fill the buffer with memory range attributes.h](h%Userspace first calls the ioctl with }(hjGhhhNhNubh)}(h**num_mem_ranges**h]hnum_mem_ranges}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh = 0, }(hjGhhhNhNubh)}(h**sizeof_mem_ranges_attr**h]hsizeof_mem_ranges_attr}(hj0GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh = 0 and }(hjGhhhNhNubh)}(h**vector_of_vma_mem_attr**h]hvector_of_vma_mem_attr}(hjBGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubh = NULL to retrieve the number of memory regions and size of each memory range attribute. Then, it allocates a buffer of that size and calls the ioctl again to fill the buffer with memory range attributes.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj۴hhubh)}(hIf second call fails with -ENOSPC, it means memory ranges changed between first call and now, retry IOCTL again with **num_mem_ranges** = 0, **sizeof_mem_ranges_attr** = 0 and **vector_of_vma_mem_attr** = NULL followed by Second ioctl call.h](huIf second call fails with -ENOSPC, it means memory ranges changed between first call and now, retry IOCTL again with }(hj[GhhhNhNubh)}(h**num_mem_ranges**h]hnum_mem_ranges}(hjcGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[Gubh = 0, }(hj[GhhhNhNubh)}(h**sizeof_mem_ranges_attr**h]hsizeof_mem_ranges_attr}(hjuGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[Gubh = 0 and }(hj[GhhhNhNubh)}(h**vector_of_vma_mem_attr**h]hvector_of_vma_mem_attr}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[Gubh& = NULL followed by Second ioctl call.}(hj[GhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj۴hhubh)}(h **Example**h]h)}(hjGh]hExample}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj۴hhubjt)}(hXistruct drm_xe_vm_query_mem_range_attr query = { .vm_id = vm_id, .start = 0x100000, .range = 0x2000, }; // First ioctl call to get num of mem regions and sizeof each attribute ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query); // Allocate buffer for the memory region attributes void *ptr = malloc(query.num_mem_ranges * query.sizeof_mem_range_attr); void *ptr_start = ptr; query.vector_of_mem_attr = (uintptr_t)ptr; // Second ioctl call to actually fill the memory attributes ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query); // Iterate over the returned memory region attributes for (unsigned int i = 0; i < query.num_mem_ranges; ++i) { struct drm_xe_mem_range_attr *attr = (struct drm_xe_mem_range_attr *)ptr; // Do something with attr // Move pointer by one entry ptr += query.sizeof_mem_range_attr; } free(ptr_start);h]hXistruct drm_xe_vm_query_mem_range_attr query = { .vm_id = vm_id, .start = 0x100000, .range = 0x2000, }; // First ioctl call to get num of mem regions and sizeof each attribute ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query); // Allocate buffer for the memory region attributes void *ptr = malloc(query.num_mem_ranges * query.sizeof_mem_range_attr); void *ptr_start = ptr; query.vector_of_mem_attr = (uintptr_t)ptr; // Second ioctl call to actually fill the memory attributes ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query); // Iterate over the returned memory region attributes for (unsigned int i = 0; i < query.num_mem_ranges; ++i) { struct drm_xe_mem_range_attr *attr = (struct drm_xe_mem_range_attr *)ptr; // Do something with attr // Move pointer by one entry ptr += query.sizeof_mem_range_attr; } free(ptr_start);}hjGsbah}(h]h ]h"]h$]h&]jjj#j$j%j&}uh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj۴hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)drm_xe_exec_queue_set_property (C struct) c.drm_xe_exec_queue_set_propertyhNtauh1jhj۴hhhjhM ubj)}(hhh](j)}(hdrm_xe_exec_queue_set_propertyh]j)}(h%struct drm_xe_exec_queue_set_propertyh](j)}(hjh]hstruct}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM ubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhjGhM ubj)}(hdrm_xe_exec_queue_set_propertyh]j)}(hjGh]hdrm_xe_exec_queue_set_property}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubah}(h]h ](j jeh"]h$]h&]jjuh1jhjGhhhjGhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjGhhhjGhM ubah}(h]jGah ](j j!eh"]h$]h&]j%j&)j'huh1jhjGhM hjGhhubj))}(hhh]h)}(hexec queue set propertyh]hexec queue set property}(hj#HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj Hhhubah}(h]h ]h"]h$]h&]uh1j(hjGhhhjGhM ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj;HjLj;HjMjNjOuh1jhhhj۴hjhM ubjQ)}(hXz**Definition**:: struct drm_xe_exec_queue_set_property { __u64 extensions; __u32 exec_queue_id; __u32 property; __u64 value; __u64 reserved[2]; }; **Members** ``extensions`` Pointer to the first extension struct, if any ``exec_queue_id`` Exec queue ID ``property`` property to set ``value`` property value ``reserved`` Reservedh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjGHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCHubh:}(hjCHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj?Hubjt)}(hstruct drm_xe_exec_queue_set_property { __u64 extensions; __u32 exec_queue_id; __u32 property; __u64 value; __u64 reserved[2]; };h]hstruct drm_xe_exec_queue_set_property { __u64 extensions; __u32 exec_queue_id; __u32 property; __u64 value; __u64 reserved[2]; };}hj`Hsbah}(h]h ]h"]h$]h&]jjuh1jshY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj?Hubh)}(h **Members**h]h)}(hjqHh]hMembers}(hjsHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjoHubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj?Hubj )}(hhh](j)}(h=``extensions`` Pointer to the first extension struct, if any h](j)}(h``extensions``h]j)}(hjHh]h extensions}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjHubj()}(hhh]h)}(h-Pointer to the first extension struct, if anyh]h-Pointer to the first extension struct, if any}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhM hjHubah}(h]h ]h"]h$]h&]uh1j'hjHubeh}(h]h ]h"]h$]h&]uh1jhjHhM hjHubj)}(h ``exec_queue_id`` Exec queue ID h](j)}(h``exec_queue_id``h]j)}(hjHh]h exec_queue_id}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjHubj()}(hhh]h)}(h Exec queue IDh]h Exec queue ID}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhM hjHubah}(h]h ]h"]h$]h&]uh1j'hjHubeh}(h]h ]h"]h$]h&]uh1jhjHhM hjHubj)}(h``property`` property to set h](j)}(h ``property``h]j)}(hjIh]hproperty}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjHubj()}(hhh]h)}(hproperty to seth]hproperty to set}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhM hjIubah}(h]h ]h"]h$]h&]uh1j'hjHubeh}(h]h ]h"]h$]h&]uh1jhjIhM hjHubj)}(h``value`` property value h](j)}(h ``value``h]j)}(hj;Ih]hvalue}(hj=IhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9Iubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj5Iubj()}(hhh]h)}(hproperty valueh]hproperty value}(hjTIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPIhM hjQIubah}(h]h ]h"]h$]h&]uh1j'hj5Iubeh}(h]h ]h"]h$]h&]uh1jhjPIhM hjHubj)}(h``reserved`` Reservedh](j)}(h ``reserved``h]j)}(hjtIh]hreserved}(hjvIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrIubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjnIubj()}(hhh]h)}(hReservedh]hReserved}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hjIubah}(h]h ]h"]h$]h&]uh1j'hjnIubeh}(h]h ]h"]h$]h&]uh1jhjIhM hjHubeh}(h]h ]h"]h$]h&]uh1j hj?Hubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj۴hhhjhM ubh)}(h**Description**h]h)}(hjIh]h Description}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubah}(h]h ]h"]h$]h&]uh1hhY/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:29: ./include/uapi/drm/xe_drm.hhM hj۴hhubh)}(hSets execution queue properties dynamically. Currently only ``DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY`` property can be dynamically set.h](h``DRM_ASAHI_GEM_BIND_OBJECT`` Bind memory as a special object h](j)}(h``DRM_ASAHI_GEM_BIND_OBJECT``h]j)}(hjMh]hDRM_ASAHI_GEM_BIND_OBJECT}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKRhjMubj()}(hhh]h)}(hBind memory as a special objecth]hBind memory as a special object}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhKRhjMubah}(h]h ]h"]h$]h&]uh1j'hjMubeh}(h]h ]h"]h$]h&]uh1jhjMhKRhj.Lubj)}(h6``DRM_ASAHI_QUEUE_CREATE`` Create a scheduling queue. h](j)}(h``DRM_ASAHI_QUEUE_CREATE``h]j)}(hjNh]hDRM_ASAHI_QUEUE_CREATE}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKUhjMubj()}(hhh]h)}(hCreate a scheduling queue.h]hCreate a scheduling queue.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhKUhjNubah}(h]h ]h"]h$]h&]uh1j'hjMubeh}(h]h ]h"]h$]h&]uh1jhjNhKUhj.Lubj)}(h8``DRM_ASAHI_QUEUE_DESTROY`` Destroy a scheduling queue. h](j)}(h``DRM_ASAHI_QUEUE_DESTROY``h]j)}(hj9Nh]hDRM_ASAHI_QUEUE_DESTROY}(hj;NhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7Nubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKXhj3Nubj()}(hhh]h)}(hDestroy a scheduling queue.h]hDestroy a scheduling queue.}(hjRNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNNhKXhjONubah}(h]h ]h"]h$]h&]uh1j'hj3Nubeh}(h]h ]h"]h$]h&]uh1jhjNNhKXhj.Lubj)}(h0``DRM_ASAHI_SUBMIT`` Submit commands to a queue.h](j)}(h``DRM_ASAHI_SUBMIT``h]j)}(hjrNh]hDRM_ASAHI_SUBMIT}(hjtNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpNubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKZhjlNubj()}(hhh]h)}(hSubmit commands to a queue.h]hSubmit commands to a queue.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK[hjNubah}(h]h ]h"]h$]h&]uh1j'hjlNubeh}(h]h ]h"]h$]h&]uh1jhjNhKZhj.Lubeh}(h]h ]h"]h$]h&]uh1j hjLubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hjNh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK]hj+Jhhubh)}(hMPlace new ioctls at the end, don't re-order, don't replace or remove entries.h]hQPlace new ioctls at the end, don’t re-order, don’t replace or remove entries.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK6hj+Jhhubh)}(h]These IDs are not meant to be used directly. Use the DRM_IOCTL_ASAHI_xxx definitions instead.h]h]These IDs are not meant to be used directly. Use the DRM_IOCTL_ASAHI_xxx definitions instead.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK8hj+Jhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_asahi_params_global (C struct)c.drm_asahi_params_globalhNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_params_globalh]j)}(hstruct drm_asahi_params_globalh](j)}(hjh]hstruct}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK>ubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNhhhjOhK>ubj)}(hdrm_asahi_params_globalh]j)}(hjNh]hdrm_asahi_params_global}(hj"OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ](j jeh"]h$]h&]jjuh1jhjNhhhjOhK>ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjNhhhjOhK>ubah}(h]jNah ](j j!eh"]h$]h&]j%j&)j'huh1jhjOhK>hjNhhubj))}(hhh]h)}(hGlobal parameters.h]hGlobal parameters.}(hjDOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKehjAOhhubah}(h]h ]h"]h$]h&]uh1j(hjNhhhjOhK>ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj\OjLj\OjMjNjOuh1jhhhj+JhNhNubjQ)}(hX **Definition**:: struct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; }; **Members** ``features`` Feature bits from drm_asahi_feature ``gpu_generation`` GPU generation, e.g. 13 for G13G ``gpu_variant`` GPU variant as a character, e.g. 'C' for G13C ``gpu_revision`` GPU revision in BCD, e.g. 0x00 for 'A0' or 0x21 for 'C1' ``chip_id`` Chip ID in BCD, e.g. 0x8103 for T8103 ``num_dies`` Number of dies in the SoC ``num_clusters_total`` Number of GPU clusters (across all dies) ``num_cores_per_cluster`` Number of logical cores per cluster (including inactive/nonexistent) ``max_frequency_khz`` Maximum GPU core clock frequency ``core_masks`` Bitmask of present/enabled cores per cluster ``vm_start`` VM range start VMA. Together with **vm_end**, this defines the window of valid GPU VAs. Userspace is expected to subdivide VAs out of this window. This window contains all virtual addresses that userspace needs to know about. There may be kernel-internal GPU VAs outside this range, but that detail is not relevant here. ``vm_end`` VM range end VMA ``vm_kernel_min_size`` Minimum kernel VMA window size. When creating a VM, userspace is required to carve out a section of virtual addresses (within the range given by **vm_start** and **vm_end**). The kernel will allocate various internal structures within the specified VA range. Allowing userspace to choose the VA range for the kernel, rather than the kernel reserving VAs and requiring userspace to cope, can assist in implementing SVM. ``max_commands_per_submission`` Maximum number of supported commands per submission. This mirrors firmware limits. Userspace must split up larger command buffers, which may require inserting additional synchronization. ``max_attachments`` Maximum number of drm_asahi_attachment's per command ``command_timestamp_frequency_hz`` Timebase frequency for timestamps written during command execution, specified via drm_asahi_timestamp structures. As this rate is controlled by the firmware, it is a queryable parameter. Userspace must divide by this frequency to convert timestamps to seconds, rather than hardcoding a particular firmware's rate.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdOubh:}(hjdOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKihj`Oubjt)}(hXstruct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; };h]hXstruct drm_asahi_params_global { __u64 features; __u32 gpu_generation; __u32 gpu_variant; __u32 gpu_revision; __u32 chip_id; __u32 num_dies; __u32 num_clusters_total; __u32 num_cores_per_cluster; __u32 max_frequency_khz; __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS]; __u64 vm_start; __u64 vm_end; __u64 vm_kernel_min_size; __u32 max_commands_per_submission; __u32 max_attachments; __u64 command_timestamp_frequency_hz; };}hjOsbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKkhj`Oubh)}(h **Members**h]h)}(hjOh]hMembers}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhK~hj`Oubj )}(hhh](j)}(h1``features`` Feature bits from drm_asahi_feature h](j)}(h ``features``h]j)}(hjOh]hfeatures}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKkhjOubj()}(hhh]h)}(h#Feature bits from drm_asahi_featureh]h#Feature bits from drm_asahi_feature}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhKkhjOubah}(h]h ]h"]h$]h&]uh1j'hjOubeh}(h]h ]h"]h$]h&]uh1jhjOhKkhjOubj)}(h4``gpu_generation`` GPU generation, e.g. 13 for G13G h](j)}(h``gpu_generation``h]j)}(hjOh]hgpu_generation}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKnhjOubj()}(hhh]h)}(h GPU generation, e.g. 13 for G13Gh]h GPU generation, e.g. 13 for G13G}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhKnhjPubah}(h]h ]h"]h$]h&]uh1j'hjOubeh}(h]h ]h"]h$]h&]uh1jhjOhKnhjOubj)}(h>``gpu_variant`` GPU variant as a character, e.g. 'C' for G13C h](j)}(h``gpu_variant``h]j)}(hj#Ph]h gpu_variant}(hj%PhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!Pubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhKqhjPubj()}(hhh]h)}(h-GPU variant as a character, e.g. 'C' for G13Ch]h1GPU variant as a character, e.g. ‘C’ for G13C}(hjhj\ubj()}(hhh]h)}(hMBZh]hMBZ}(hj ]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM?hj]ubah}(h]h ]h"]h$]h&]uh1j'hj\ubeh}(h]h ]h"]h$]h&]uh1jhj]hM>hj\ubeh}(h]h ]h"]h$]h&]uh1j hj[ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$drm_asahi_gem_mmap_offset (C struct)c.drm_asahi_gem_mmap_offsethNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_gem_mmap_offseth]j)}(h struct drm_asahi_gem_mmap_offseth](j)}(hjh]hstruct}(hjJ]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjF]hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMEubj)}(h h]h }(hjX]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjF]hhhjW]hMEubj)}(hdrm_asahi_gem_mmap_offseth]j)}(hjD]h]hdrm_asahi_gem_mmap_offset}(hjj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjf]ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjF]hhhjW]hMEubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjB]hhhjW]hMEubah}(h]j=]ah ](j j!eh"]h$]h&]j%j&)j'huh1jhjW]hMEhj?]hhubj))}(hhh]h)}(h3Arguments passed to DRM_IOCTL_ASAHI_GEM_MMAP_OFFSETh]h3Arguments passed to DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMChj]hhubah}(h]h ]h"]h$]h&]uh1j(hj?]hhhjW]hMEubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj]jLj]jMjNjOuh1jhhhj+JhNhNubjQ)}(hX **Definition**:: struct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; }; **Members** ``handle`` Handle for the object being mapped. ``flags`` Must be zero ``offset`` The fake offset to use for subsequent mmap callh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]ubh:}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMGhj]ubjt)}(hZstruct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; };h]hZstruct drm_asahi_gem_mmap_offset { __u32 handle; __u32 flags; __u64 offset; };}hj]sbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMIhj]ubh)}(h **Members**h]h)}(hj]h]hMembers}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMOhj]ubj )}(hhh](j)}(h/``handle`` Handle for the object being mapped. h](j)}(h ``handle``h]j)}(hj]h]hhandle}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMHhj]ubj()}(hhh]h)}(h#Handle for the object being mapped.h]h#Handle for the object being mapped.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hMHhj^ubah}(h]h ]h"]h$]h&]uh1j'hj]ubeh}(h]h ]h"]h$]h&]uh1jhj^hMHhj]ubj)}(h``flags`` Must be zero h](j)}(h ``flags``h]j)}(hj2^h]hflags}(hj4^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMKhj,^ubj()}(hhh]h)}(h Must be zeroh]h Must be zero}(hjK^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjG^hMKhjH^ubah}(h]h ]h"]h$]h&]uh1j'hj,^ubeh}(h]h ]h"]h$]h&]uh1jhjG^hMKhj]ubj)}(h:``offset`` The fake offset to use for subsequent mmap callh](j)}(h ``offset``h]j)}(hjk^h]hoffset}(hjm^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji^ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMMhje^ubj()}(hhh]h)}(h/The fake offset to use for subsequent mmap callh]h/The fake offset to use for subsequent mmap call}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMNhj^ubah}(h]h ]h"]h$]h&]uh1j'hje^ubeh}(h]h ]h"]h$]h&]uh1jhj^hMMhj]ubeh}(h]h ]h"]h$]h&]uh1j hj]ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_bind_flags (C enum)c.drm_asahi_bind_flagshNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_bind_flagsh]j)}(henum drm_asahi_bind_flagsh](j)}(hjSh]henum}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMTubj)}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhj^hMTubj)}(hdrm_asahi_bind_flagsh]j)}(hj^h]hdrm_asahi_bind_flags}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubah}(h]h ](j jeh"]h$]h&]jjuh1jhj^hhhj^hMTubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj^hhhj^hMTubah}(h]j^ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj^hMThj^hhubj))}(hhh]h)}(hFlags for GEM bindingh]hFlags for GEM binding}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMRhj_hhubah}(h]h ]h"]h$]h&]uh1j(hj^hhhj^hMTubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKj_jLj_jMjNjOuh1jhhhj+JhNhNubjQ)}(hX**Constants** ``DRM_ASAHI_BIND_UNBIND`` Instead of binding a GEM object to the range, simply unbind the GPU VMA range. ``DRM_ASAHI_BIND_READ`` Map BO with GPU read permission ``DRM_ASAHI_BIND_WRITE`` Map BO with GPU write permission ``DRM_ASAHI_BIND_SINGLE_PAGE`` Map a single page of the BO repeatedly across the VA range. This is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h](h)}(h **Constants**h]h)}(hj)_h]h Constants}(hj+_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'_ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMVhj#_ubj )}(hhh](j)}(hi``DRM_ASAHI_BIND_UNBIND`` Instead of binding a GEM object to the range, simply unbind the GPU VMA range. h](j)}(h``DRM_ASAHI_BIND_UNBIND``h]j)}(hjH_h]hDRM_ASAHI_BIND_UNBIND}(hjJ_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjF_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMZhjB_ubj()}(hhh]h)}(hNInstead of binding a GEM object to the range, simply unbind the GPU VMA range.h]hNInstead of binding a GEM object to the range, simply unbind the GPU VMA range.}(hja_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMYhj^_ubah}(h]h ]h"]h$]h&]uh1j'hjB_ubeh}(h]h ]h"]h$]h&]uh1jhj]_hMZhj?_ubj)}(h8``DRM_ASAHI_BIND_READ`` Map BO with GPU read permission h](j)}(h``DRM_ASAHI_BIND_READ``h]j)}(hj_h]hDRM_ASAHI_BIND_READ}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM]hj|_ubj()}(hhh]h)}(hMap BO with GPU read permissionh]hMap BO with GPU read permission}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM]hj_ubah}(h]h ]h"]h$]h&]uh1j'hj|_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM]hj?_ubj)}(h:``DRM_ASAHI_BIND_WRITE`` Map BO with GPU write permission h](j)}(h``DRM_ASAHI_BIND_WRITE``h]j)}(hj_h]hDRM_ASAHI_BIND_WRITE}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM`hj_ubj()}(hhh]h)}(h Map BO with GPU write permissionh]h Map BO with GPU write permission}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM`hj_ubah}(h]h ]h"]h$]h&]uh1j'hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM`hj?_ubj)}(h``DRM_ASAHI_BIND_SINGLE_PAGE`` Map a single page of the BO repeatedly across the VA range. This is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h](j)}(h``DRM_ASAHI_BIND_SINGLE_PAGE``h]j)}(hj_h]hDRM_ASAHI_BIND_SINGLE_PAGE}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMfhj_ubj()}(hhh](h)}(h;Map a single page of the BO repeatedly across the VA range.h]h;Map a single page of the BO repeatedly across the VA range.}(hj `hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMchj `ubh)}(hwThis is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.h]hwThis is useful to fill a VA range with scratch pages or zero pages. It is intended as a mechanism to accelerate sparse.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj `hMfhj `ubeh}(h]h ]h"]h$]h&]uh1j'hj_ubeh}(h]h ]h"]h$]h&]uh1jhj `hMfhj?_ubeh}(h]h ]h"]h$]h&]uh1j hj#_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_asahi_gem_bind_op (C struct)c.drm_asahi_gem_bind_ophNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_gem_bind_oph]j)}(hstruct drm_asahi_gem_bind_oph](j)}(hjh]hstruct}(hj\`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX`hhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMlubj)}(h h]h }(hjj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX`hhhji`hMlubj)}(hdrm_asahi_gem_bind_oph]j)}(hjV`h]hdrm_asahi_gem_bind_op}(hj|`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx`ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjX`hhhji`hMlubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjT`hhhji`hMlubah}(h]jO`ah ](j j!eh"]h$]h&]j%j&)j'huh1jhji`hMlhjQ`hhubj))}(hhh]h)}(h+Description of a single GEM bind operation.h]h+Description of a single GEM bind operation.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMlhj`hhubah}(h]h ]h"]h$]h&]uh1j(hjQ`hhhji`hMlubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj`jLj`jMjNjOuh1jhhhj+JhNhNubjQ)}(hX**Definition**:: struct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; }; **Members** ``flags`` Combination of drm_asahi_bind_flags flags. ``handle`` GEM object to bind (except for UNBIND) ``offset`` Offset into the object (except for UNBIND). For a regular bind, this is the beginning of the region of the GEM object to bind. For a single-page bind, this is the offset to the single page that will be repeatedly bound. Must be page-size aligned. ``range`` Number of bytes to bind/unbind to **addr**. Must be page-size aligned. ``addr`` Address to bind to. Must be page-size aligned.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`ubh:}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMphj`ubjt)}(hwstruct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; };h]hwstruct drm_asahi_gem_bind_op { __u32 flags; __u32 handle; __u64 offset; __u64 range; __u64 addr; };}hj`sbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMrhj`ubh)}(h **Members**h]h)}(hj`h]hMembers}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMzhj`ubj )}(hhh](j)}(h5``flags`` Combination of drm_asahi_bind_flags flags. h](j)}(h ``flags``h]j)}(hj ah]hflags}(hj ahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj aubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMphjaubj()}(hhh]h)}(h*Combination of drm_asahi_bind_flags flags.h]h*Combination of drm_asahi_bind_flags flags.}(hj$ahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ahMphj!aubah}(h]h ]h"]h$]h&]uh1j'hjaubeh}(h]h ]h"]h$]h&]uh1jhj ahMphjaubj)}(h2``handle`` GEM object to bind (except for UNBIND) h](j)}(h ``handle``h]j)}(hjDah]hhandle}(hjFahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMshj>aubj()}(hhh]h)}(h&GEM object to bind (except for UNBIND)h]h&GEM object to bind (except for UNBIND)}(hj]ahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYahMshjZaubah}(h]h ]h"]h$]h&]uh1j'hj>aubeh}(h]h ]h"]h$]h&]uh1jhjYahMshjaubj)}(hX``offset`` Offset into the object (except for UNBIND). For a regular bind, this is the beginning of the region of the GEM object to bind. For a single-page bind, this is the offset to the single page that will be repeatedly bound. Must be page-size aligned. h](j)}(h ``offset``h]j)}(hj}ah]hoffset}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{aubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjwaubj()}(hhh](h)}(h+Offset into the object (except for UNBIND).h]h+Offset into the object (except for UNBIND).}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMwhjaubh)}(hRFor a regular bind, this is the beginning of the region of the GEM object to bind.h]hRFor a regular bind, this is the beginning of the region of the GEM object to bind.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMyhjaubh)}(h\For a single-page bind, this is the offset to the single page that will be repeatedly bound.h]h\For a single-page bind, this is the offset to the single page that will be repeatedly bound.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM|hjaubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahMhjaubeh}(h]h ]h"]h$]h&]uh1j'hjwaubeh}(h]h ]h"]h$]h&]uh1jhjahMhjaubj)}(hR``range`` Number of bytes to bind/unbind to **addr**. Must be page-size aligned. h](j)}(h ``range``h]j)}(hjah]hrange}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjaubj()}(hhh](h)}(h+Number of bytes to bind/unbind to **addr**.h](h"Number of bytes to bind/unbind to }(hjahhhNhNubh)}(h**addr**h]haddr}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjaubh.}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjaubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahMhjaubeh}(h]h ]h"]h$]h&]uh1j'hjaubeh}(h]h ]h"]h$]h&]uh1jhjahMhjaubj)}(h8``addr`` Address to bind to. Must be page-size aligned.h](j)}(h``addr``h]j)}(hj=bh]haddr}(hj?bhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;bubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj7bubj()}(hhh](h)}(hAddress to bind to.h]hAddress to bind to.}(hjVbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjSbubh)}(hMust be page-size aligned.h]hMust be page-size aligned.}(hjebhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjSbubeh}(h]h ]h"]h$]h&]uh1j'hj7bubeh}(h]h ]h"]h$]h&]uh1jhjRbhMhjaubeh}(h]h ]h"]h$]h&]uh1j hj`ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_vm_bind (C struct)c.drm_asahi_vm_bindhNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_vm_bindh]j)}(hstruct drm_asahi_vm_bindh](j)}(hjh]hstruct}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhjbhMubj)}(hdrm_asahi_vm_bindh]j)}(hjbh]hdrm_asahi_vm_bind}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubah}(h]h ](j jeh"]h$]h&]jjuh1jhjbhhhjbhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjbhhhjbhMubah}(h]jbah ](j j!eh"]h$]h&]j%j&)j'huh1jhjbhMhjbhhubj))}(hhh]h)}(h+Arguments passed to DRM_IOCTL_ASAHI_VM_BINDh]h+Arguments passed to DRM_IOCTL_ASAHI_VM_BIND}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjbhhubah}(h]h ]h"]h$]h&]uh1j(hjbhhhjbhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjcjLjcjMjNjOuh1jhhhj+JhNhNubjQ)}(hX**Definition**:: struct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; }; **Members** ``vm_id`` The ID of the VM to bind to ``num_binds`` number of binds in this IOCTL. ``stride`` Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op. ``pad`` MBZ ``userptr`` User pointer to an array of **num_binds** structures of type **drm_asahi_gem_bind_op** and size **stride** bytes.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj chhhNhNubah}(h]h ]h"]h$]h&]uh1hhjcubh:}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubjt)}(hwstruct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; };h]hwstruct drm_asahi_vm_bind { __u32 vm_id; __u32 num_binds; __u32 stride; __u32 pad; __u64 userptr; };}hj%csbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubh)}(h **Members**h]h)}(hj6ch]hMembers}(hj8chhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4cubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubj )}(hhh](j)}(h&``vm_id`` The ID of the VM to bind to h](j)}(h ``vm_id``h]j)}(hjUch]hvm_id}(hjWchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjScubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjOcubj()}(hhh]h)}(hThe ID of the VM to bind toh]hThe ID of the VM to bind to}(hjnchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjchMhjkcubah}(h]h ]h"]h$]h&]uh1j'hjOcubeh}(h]h ]h"]h$]h&]uh1jhjjchMhjLcubj)}(h-``num_binds`` number of binds in this IOCTL. h](j)}(h ``num_binds``h]j)}(hjch]h num_binds}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubj()}(hhh]h)}(hnumber of binds in this IOCTL.h]hnumber of binds in this IOCTL.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjcubah}(h]h ]h"]h$]h&]uh1j'hjcubeh}(h]h ]h"]h$]h&]uh1jhjchMhjLcubj)}(hj``stride`` Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op. h](j)}(h ``stride``h]j)}(hjch]hstride}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubj()}(hhh]h)}(h^Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op.h]h^Stride in bytes between consecutive binds. This allows extensibility of drm_asahi_gem_bind_op.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubah}(h]h ]h"]h$]h&]uh1j'hjcubeh}(h]h ]h"]h$]h&]uh1jhjchMhjLcubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjdh]hpad}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjcubj()}(hhh]h)}(hMBZh]hMBZ}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjdubah}(h]h ]h"]h$]h&]uh1j'hjcubeh}(h]h ]h"]h$]h&]uh1jhjdhMhjLcubj)}(h}``userptr`` User pointer to an array of **num_binds** structures of type **drm_asahi_gem_bind_op** and size **stride** bytes.h](j)}(h ``userptr``h]j)}(hj:dh]huserptr}(hj``object_handle`` Object handle (out for BIND, in for UNBIND) h](j)}(h``object_handle``h]j)}(hjhh]h object_handle}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjhubj()}(hhh]h)}(h+Object handle (out for BIND, in for UNBIND)h]h+Object handle (out for BIND, in for UNBIND)}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMhjhubah}(h]h ]h"]h$]h&]uh1j'hjhubeh}(h]h ]h"]h$]h&]uh1jhjhhMhjagubj)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hjhh]hpad}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjhubj()}(hhh]h)}(hMBZh]hMBZ}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjiubah}(h]h ]h"]h$]h&]uh1j'hjhubeh}(h]h ]h"]h$]h&]uh1jhjihMhjagubeh}(h]h ]h"]h$]h&]uh1j hjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_cmd_type (C enum)c.drm_asahi_cmd_typehNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_cmd_typeh]j)}(henum drm_asahi_cmd_typeh](j)}(hjSh]henum}(hjSihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOihhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjaihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOihhhj`ihMubj)}(hdrm_asahi_cmd_typeh]j)}(hjMih]hdrm_asahi_cmd_type}(hjsihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoiubah}(h]h ](j jeh"]h$]h&]jjuh1jhjOihhhj`ihMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjKihhhj`ihMubah}(h]jFiah ](j j!eh"]h$]h&]j%j&)j'huh1jhj`ihMhjHihhubj))}(hhh]h)}(h Command typeh]h Command type}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjihhubah}(h]h ]h"]h$]h&]uh1j(hjHihhhj`ihMubeh}(h]h ](jEenumeh"]h$]h&]jJjEjKjijLjijMjNjOuh1jhhhj+JhNhNubjQ)}(hX**Constants** ``DRM_ASAHI_CMD_RENDER`` Render command, executing on the render subqueue. Combined vertex and fragment operation. Followed by a **drm_asahi_cmd_render** payload. ``DRM_ASAHI_CMD_COMPUTE`` Compute command on the compute subqueue. Followed by a **drm_asahi_cmd_compute** payload. ``DRM_ASAHI_SET_VERTEX_ATTACHMENTS`` Software command to set attachments for subsequent vertex shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. ``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS`` Software command to set attachments for subsequent fragment shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. ``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS`` Software command to set attachments for subsequent compute shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads.h](h)}(h **Constants**h]h)}(hjih]h Constants}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjiubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjiubj )}(hhh](j)}(h``DRM_ASAHI_CMD_RENDER`` Render command, executing on the render subqueue. Combined vertex and fragment operation. Followed by a **drm_asahi_cmd_render** payload. h](j)}(h``DRM_ASAHI_CMD_RENDER``h]j)}(hjih]hDRM_ASAHI_CMD_RENDER}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjiubj()}(hhh](h)}(hYRender command, executing on the render subqueue. Combined vertex and fragment operation.h]hYRender command, executing on the render subqueue. Combined vertex and fragment operation.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjiubh)}(h/Followed by a **drm_asahi_cmd_render** payload.h](hFollowed by a }(hjihhhNhNubh)}(h**drm_asahi_cmd_render**h]hdrm_asahi_cmd_render}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjiubh payload.}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjihMhjiubeh}(h]h ]h"]h$]h&]uh1j'hjiubeh}(h]h ]h"]h$]h&]uh1jhjihMhjiubj)}(hu``DRM_ASAHI_CMD_COMPUTE`` Compute command on the compute subqueue. Followed by a **drm_asahi_cmd_compute** payload. h](j)}(h``DRM_ASAHI_CMD_COMPUTE``h]j)}(hj0jh]hDRM_ASAHI_CMD_COMPUTE}(hj2jhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.jubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj*jubj()}(hhh](h)}(h(Compute command on the compute subqueue.h]h(Compute command on the compute subqueue.}(hjIjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjFjubh)}(h0Followed by a **drm_asahi_cmd_compute** payload.h](hFollowed by a }(hjXjhhhNhNubh)}(h**drm_asahi_cmd_compute**h]hdrm_asahi_cmd_compute}(hj`jhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXjubh payload.}(hjXjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjEjhMhjFjubeh}(h]h ]h"]h$]h&]uh1j'hj*jubeh}(h]h ]h"]h$]h&]uh1jhjEjhMhjiubj)}(h``DRM_ASAHI_SET_VERTEX_ATTACHMENTS`` Software command to set attachments for subsequent vertex shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. h](j)}(h$``DRM_ASAHI_SET_VERTEX_ATTACHMENTS``h]j)}(hjjh]h DRM_ASAHI_SET_VERTEX_ATTACHMENTS}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjjubj()}(hhh](h)}(hUSoftware command to set attachments for subsequent vertex shaders in the same submit.h]hUSoftware command to set attachments for subsequent vertex shaders in the same submit.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjjubh)}(hBFollowed by (possibly multiple) **drm_asahi_attachment** payloads.h](h Followed by (possibly multiple) }(hjjhhhNhNubh)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjubh payloads.}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjjhMhjjubeh}(h]h ]h"]h$]h&]uh1j'hjjubeh}(h]h ]h"]h$]h&]uh1jhjjhMhjiubj)}(h``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS`` Software command to set attachments for subsequent fragment shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads. h](j)}(h&``DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS``h]j)}(hjjh]h"DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjjubj()}(hhh](h)}(hWSoftware command to set attachments for subsequent fragment shaders in the same submit.h]hWSoftware command to set attachments for subsequent fragment shaders in the same submit.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjjubh)}(hBFollowed by (possibly multiple) **drm_asahi_attachment** payloads.h](h Followed by (possibly multiple) }(hj khhhNhNubh)}(h**drm_asahi_attachment**h]hdrm_asahi_attachment}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj kubh payloads.}(hj khhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjjhMhjjubeh}(h]h ]h"]h$]h&]uh1j'hjjubeh}(h]h ]h"]h$]h&]uh1jhjjhMhjiubj)}(h``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS`` Software command to set attachments for subsequent compute shaders in the same submit. Followed by (possibly multiple) **drm_asahi_attachment** payloads.h](j)}(h%``DRM_ASAHI_SET_COMPUTE_ATTACHMENTS``h]j)}(hj>kh]h!DRM_ASAHI_SET_COMPUTE_ATTACHMENTS}(hj@khhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:lubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj6lubj()}(hhh]h)}(hLow priority queue.h]hLow priority queue.}(hjUlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQlhMhjRlubah}(h]h ]h"]h$]h&]uh1j'hj6lubeh}(h]h ]h"]h$]h&]uh1jhjQlhMhj3lubj)}(h5``DRM_ASAHI_PRIORITY_MEDIUM`` Medium priority queue. h](j)}(h``DRM_ASAHI_PRIORITY_MEDIUM``h]j)}(hjulh]hDRM_ASAHI_PRIORITY_MEDIUM}(hjwlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjslubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjolubj()}(hhh]h)}(hMedium priority queue.h]hMedium priority queue.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMhjlubah}(h]h ]h"]h$]h&]uh1j'hjolubeh}(h]h ]h"]h$]h&]uh1jhjlhMhj3lubj)}(hQ``DRM_ASAHI_PRIORITY_HIGH`` High priority queue. Reserved for future extension. h](j)}(h``DRM_ASAHI_PRIORITY_HIGH``h]j)}(hjlh]hDRM_ASAHI_PRIORITY_HIGH}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjlubj()}(hhh](h)}(hHigh priority queue.h]hHigh priority queue.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjlubh)}(hReserved for future extension.h]hReserved for future extension.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMhjlubeh}(h]h ]h"]h$]h&]uh1j'hjlubeh}(h]h ]h"]h$]h&]uh1jhjlhMhj3lubj)}(hY``DRM_ASAHI_PRIORITY_REALTIME`` Real-time priority queue. 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USC addresses are 32-bit relative to this 64-bit base. This sets the following registers on all queue commands: USC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) While the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmubh:}(hjmhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM.hjmubjt)}(hstruct drm_asahi_queue_create { __u32 flags; __u32 vm_id; __u32 priority; __u32 queue_id; __u64 usc_exec_base; };h]hstruct drm_asahi_queue_create { __u32 flags; __u32 vm_id; __u32 priority; __u32 queue_id; __u64 usc_exec_base; };}hjnsbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM0hjmubh)}(h **Members**h]h)}(hjnh]hMembers}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM8hjmubj )}(hhh](j)}(h``flags`` MBZ h](j)}(h ``flags``h]j)}(hj5nh]hflags}(hj7nhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3nubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM/hj/nubj()}(hhh]h)}(hMBZh]hMBZ}(hjNnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJnhM/hjKnubah}(h]h ]h"]h$]h&]uh1j'hj/nubeh}(h]h ]h"]h$]h&]uh1jhjJnhM/hj,nubj)}(h2``vm_id`` The ID of the VM this queue is bound to h](j)}(h ``vm_id``h]j)}(hjnnh]hvm_id}(hjpnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlnubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM2hjhnubj()}(hhh]h)}(h'The ID of the VM this queue is bound toh]h'The ID of the VM this queue is bound to}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhM2hjnubah}(h]h ]h"]h$]h&]uh1j'hjhnubeh}(h]h ]h"]h$]h&]uh1jhjnhM2hj,nubj)}(h'``priority`` One of drm_asahi_priority h](j)}(h ``priority``h]j)}(hjnh]hpriority}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM5hjnubj()}(hhh]h)}(hOne of drm_asahi_priorityh]hOne of drm_asahi_priority}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhM5hjnubah}(h]h ]h"]h$]h&]uh1j'hjnubeh}(h]h ]h"]h$]h&]uh1jhjnhM5hj,nubj)}(h#``queue_id`` The returned queue ID h](j)}(h ``queue_id``h]j)}(hjnh]hqueue_id}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM8hjnubj()}(hhh]h)}(hThe returned queue IDh]hThe returned queue ID}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhM8hjnubah}(h]h ]h"]h$]h&]uh1j'hjnubeh}(h]h ]h"]h$]h&]uh1jhjnhM8hj,nubj)}(hX``usc_exec_base`` GPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base. This sets the following registers on all queue commands: USC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) While the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h](j)}(h``usc_exec_base``h]j)}(hjoh]h usc_exec_base}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMFhjoubj()}(hhh](h)}(huGPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base.h]huGPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base.}(hj2ohhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM<hj/oubh)}(h8This sets the following registers on all queue commands:h]h8This sets the following registers on all queue commands:}(hjAohhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM?hj/oubj)}(hTUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute) h]h)}(hSUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute)h]hSUSC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute)}(hjTohhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMAhjPoubah}(h]h ]h"]h$]h&]uh1jhjbohMAhj/oubh)}(hWhile the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.h]hWhile the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.}(hjiohhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMEhj/oubeh}(h]h ]h"]h$]h&]uh1j'hjoubeh}(h]h ]h"]h$]h&]uh1jhj.ohMFhj,nubeh}(h]h ]h"]h$]h&]uh1j hjmubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"drm_asahi_queue_destroy (C struct)c.drm_asahi_queue_destroyhNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_queue_destroyh]j)}(hstruct drm_asahi_queue_destroyh](j)}(hjh]hstruct}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjohhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMMubj)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjohhhjohMMubj)}(hdrm_asahi_queue_destroyh]j)}(hjoh]hdrm_asahi_queue_destroy}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ](j jeh"]h$]h&]jjuh1jhjohhhjohMMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjohhhjohMMubah}(h]joah ](j j!eh"]h$]h&]j%j&)j'huh1jhjohMMhjohhubj))}(hhh]h)}(h1Arguments passed to DRM_IOCTL_ASAHI_QUEUE_DESTROYh]h1Arguments passed to DRM_IOCTL_ASAHI_QUEUE_DESTROY}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMLhjohhubah}(h]h ]h"]h$]h&]uh1j(hjohhhjohMMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjpjLjpjMjNjOuh1jhhhj+JhNhNubjQ)}(h**Definition**:: struct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; }; **Members** ``queue_id`` The queue ID to be destroyed ``pad`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhj pubh:}(hj phhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMPhjpubjt)}(hFstruct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; };h]hFstruct drm_asahi_queue_destroy { __u32 queue_id; __u32 pad; };}hj)psbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMRhjpubh)}(h **Members**h]h)}(hj:ph]hMembers}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:yubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj6yubj()}(hhh]h)}(hCommand buffer size in bytesh]hCommand buffer size in bytes}(hjUyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQyhMhjRyubah}(h]h ]h"]h$]h&]uh1j'hj6yubeh}(h]h ]h"]h$]h&]uh1jhjQyhMhjvwubj)}(h ``pad`` MBZh](j)}(h``pad``h]j)}(hjuyh]hpad}(hjwyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsyubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjoyubj()}(hhh]h)}(hMBZh]hMBZ}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjyubah}(h]h ]h"]h$]h&]uh1j'hjoyubeh}(h]h ]h"]h$]h&]uh1jhjyhMhjvwubeh}(h]h ]h"]h$]h&]uh1j hj.wubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_attachment (C struct)c.drm_asahi_attachmenthNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_attachmenth]j)}(hstruct drm_asahi_attachmenth](j)}(hjh]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyhhhjyhMubj)}(hdrm_asahi_attachmenth]j)}(hjyh]hdrm_asahi_attachment}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubah}(h]h ](j jeh"]h$]h&]jjuh1jhjyhhhjyhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjyhhhjyhMubah}(h]jyah ](j j!eh"]h$]h&]j%j&)j'huh1jhjyhMhjyhhubj))}(hhh]h)}(hDescribe an "attachment".h]hDescribe an “attachment”.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjzhhubah}(h]h ]h"]h$]h&]uh1j(hjyhhhjyhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj)zjLj)zjMjNjOuh1jhhhj+JhNhNubjQ)}(hX**Definition**:: struct drm_asahi_attachment { __u64 pointer; __u64 size; __u32 pad; __u32 flags; }; **Members** ``pointer`` Base address of the attachment ``size`` Size of the attachment in bytes ``pad`` MBZ ``flags`` MBZh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj5zhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1zubh:}(hj1zhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj-zubjt)}(hcstruct drm_asahi_attachment { __u64 pointer; __u64 size; __u32 pad; __u32 flags; };h]hcstruct drm_asahi_attachment { __u64 pointer; __u64 size; __u32 pad; __u32 flags; };}hjNzsbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj-zubh)}(h **Members**h]h)}(hj_zh]hMembers}(hjazhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]zubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj-zubj )}(hhh](j)}(h+``pointer`` Base address of the attachment h](j)}(h ``pointer``h]j)}(hj~zh]hpointer}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|zubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjxzubj()}(hhh]h)}(hBase address of the attachmenth]hBase address of the attachment}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMhjzubah}(h]h ]h"]h$]h&]uh1j'hjxzubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjuzubj)}(h)``size`` Size of the attachment in bytes h](j)}(h``size``h]j)}(hjzh]hsize}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjzubj()}(hhh]h)}(hSize of the attachment in bytesh]hSize of the attachment in bytes}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMhjzubah}(h]h ]h"]h$]h&]uh1j'hjzubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjuzubj)}(h ``pad`` MBZ h](j)}(h``pad``h]j)}(hjzh]hpad}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjzubj()}(hhh]h)}(hMBZh]hMBZ}(hj {hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hMhj{ubah}(h]h ]h"]h$]h&]uh1j'hjzubeh}(h]h ]h"]h$]h&]uh1jhj{hMhjuzubj)}(h ``flags`` MBZh](j)}(h ``flags``h]j)}(hj){h]hflags}(hj+{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'{ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj#{ubj()}(hhh]h)}(hMBZh]hMBZ}(hjB{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj?{ubah}(h]h ]h"]h$]h&]uh1j'hj#{ubeh}(h]h ]h"]h$]h&]uh1jhj>{hMhjuzubeh}(h]h ]h"]h$]h&]uh1j hj-zubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hjl{h]h Description}(hjn{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj{ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubh)}(hXAttachments are any memory written by shaders, notably including render target attachments written by the end-of-tile program. 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__u64 comp_base; __u32 stride; __u32 comp_stride; }; **Members** ``base`` Base address of the buffer ``comp_base`` If the load buffer is compressed, address of the compression metadata section. ``stride`` If layered rendering is enabled, the number of bytes between each layer of the buffer. ``comp_stride`` If layered rendering is enabled, the number of bytes between each layer of the compression metadata.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|ubh:}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM,hj|ubjt)}(hnstruct drm_asahi_zls_buffer { __u64 base; __u64 comp_base; __u32 stride; __u32 comp_stride; };h]hnstruct drm_asahi_zls_buffer { __u64 base; __u64 comp_base; __u32 stride; __u32 comp_stride; };}hj8|sbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM.hj|ubh)}(h **Members**h]h)}(hjI|h]hMembers}(hjK|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjG|ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM5hj|ubj )}(hhh](j)}(h$``base`` Base address of the buffer h](j)}(h``base``h]j)}(hjh|h]hbase}(hjj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM4hjb|ubj()}(hhh]h)}(hBase address of the bufferh]hBase address of the buffer}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}|hM4hj~|ubah}(h]h ]h"]h$]h&]uh1j'hjb|ubeh}(h]h ]h"]h$]h&]uh1jhj}|hM4hj_|ubj)}(h]``comp_base`` If the load buffer is compressed, address of the compression metadata section. h](j)}(h ``comp_base``h]j)}(hj|h]h comp_base}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM9hj|ubj()}(hhh]h)}(hNIf the load buffer is compressed, address of the compression metadata section.h]hNIf the load buffer is compressed, address of the compression metadata section.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM8hj|ubah}(h]h ]h"]h$]h&]uh1j'hj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hM9hj_|ubj)}(hb``stride`` If layered rendering is enabled, the number of bytes between each layer of the buffer. h](j)}(h ``stride``h]j)}(hj|h]hstride}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM?hj|ubj()}(hhh]h)}(hVIf layered rendering is enabled, the number of bytes between each layer of the buffer.h]hVIf layered rendering is enabled, the number of bytes between each layer of the buffer.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM>hj|ubah}(h]h ]h"]h$]h&]uh1j'hj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hM?hj_|ubj)}(ht``comp_stride`` If layered rendering is enabled, the number of bytes between each layer of the compression metadata.h](j)}(h``comp_stride``h]j)}(hj}h]h comp_stride}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMDhj}ubj()}(hhh]h)}(hdIf layered rendering is enabled, the number of bytes between each layer of the compression metadata.h]hdIf layered rendering is enabled, the number of bytes between each layer of the compression metadata.}(hj.}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*}hMDhj+}ubah}(h]h ]h"]h$]h&]uh1j'hj}ubeh}(h]h ]h"]h$]h&]uh1jhj*}hMDhj_|ubeh}(h]h ]h"]h$]h&]uh1j hj|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hjW}h]h Description}(hjY}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU}ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMHhj+Jhhubh)}(hXdThese fields correspond to hardware registers in the ZLS (Z Load/Store) unit. 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If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle. h](j)}(h ``handle``h]j)}(hjS~h]hhandle}(hjU~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ~ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMXhjM~ubj()}(hhh]h)}(hHandle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle.h]hHandle of the timestamp buffer, or 0 to skip this timestamp. If nonzero, this must equal the value returned in drm_asahi_gem_bind_object::object_handle.}(hjl~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMVhji~ubah}(h]h ]h"]h$]h&]uh1j'hjM~ubeh}(h]h ]h"]h$]h&]uh1jhjh~hMXhjJ~ubj)}(h4``offset`` Offset to write into the timestamp bufferh](j)}(h ``offset``h]j)}(hj~h]hoffset}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM[hj~ubj()}(hhh]h)}(h)Offset to write into the timestamp bufferh]h)Offset to write into the timestamp buffer}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM\hj~ubah}(h]h ]h"]h$]h&]uh1j'hj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hM[hjJ~ubeh}(h]h ]h"]h$]h&]uh1j hj~ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hj~h]h Description}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM_hj+Jhhubh)}(hX The firmware can optionally write the GPU timestamp at render pass granularities, but it needs to be mapped specially via DRM_IOCTL_ASAHI_GEM_BIND_OBJECT. This structure therefore describes where to write as a handle-offset pair, rather than a GPU address like normal.h]hX The firmware can optionally write the GPU timestamp at render pass granularities, but it needs to be mapped specially via DRM_IOCTL_ASAHI_GEM_BIND_OBJECT. This structure therefore describes where to write as a handle-offset pair, rather than a GPU address like normal.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMKhj+Jhhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMPhj+Jhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_timestamps (C struct)c.drm_asahi_timestampshNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_timestampsh]j)}(hstruct drm_asahi_timestampsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMUubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj*hMUubj)}(hdrm_asahi_timestampsh]j)}(hjh]hdrm_asahi_timestamps}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhj*hMUubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj*hMUubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhj*hMUhjhhubj))}(hhh]h)}(hDescribe timestamp writes.h]hDescribe timestamp writes.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM`hj\hhubah}(h]h ]h"]h$]h&]uh1j(hjhhhj*hMUubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjwjLjwjMjNjOuh1jhhhj+JhNhNubjQ)}(hX **Definition**:: struct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; }; **Members** ``start`` Timestamp recorded at the start of the operation ``end`` Timestamp recorded at the end of the operationh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMdhj{ubjt)}(hjstruct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; };h]hjstruct drm_asahi_timestamps { struct drm_asahi_timestamp start; struct drm_asahi_timestamp end; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMfhj{ubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMkhj{ubj )}(hhh](j)}(h;``start`` Timestamp recorded at the start of the operation h](j)}(h ``start``h]j)}(hjh]hstart}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMjhjubj()}(hhh]h)}(h0Timestamp recorded at the start of the operationh]h0Timestamp recorded at the start of the operation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMjhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMjhjubj)}(h6``end`` Timestamp recorded at the end of the operationh](j)}(h``end``h]j)}(hjh]hend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMlhjubj()}(hhh]h)}(h.Timestamp recorded at the end of the operationh]h.Timestamp recorded at the end of the operation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMmhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMlhjubeh}(h]h ]h"]h$]h&]uh1j hj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hjHh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMphj+Jhhubh)}(hEach operation that can be timestamped, can be timestamped at the start and end. Therefore, drm_asahi_timestamp structs always come in pairs, bundled together into drm_asahi_timestamps.h]hEach operation that can be timestamped, can be timestamped at the start and end. Therefore, drm_asahi_timestamp structs always come in pairs, bundled together into drm_asahi_timestamps.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMahj+Jhhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMehj+Jhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#drm_asahi_helper_program (C struct)c.drm_asahi_helper_programhNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_helper_programh]j)}(hstruct drm_asahi_helper_programh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMjubj)}(hdrm_asahi_helper_programh]j)}(hjh]hdrm_asahi_helper_program}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhhjhMjubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMjubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMjhjhhubj))}(hhh]h)}(h&Describe helper program configuration.h]h&Describe helper program configuration.}(hj׀hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMqhjԀhhubah}(h]h ]h"]h$]h&]uh1j(hjhhhjhMjubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj+JhNhNubjQ)}(hX**Definition**:: struct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; }; **Members** ``binary`` USC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits. ``cfg`` Additional configuration bits for the helper program. ``data`` Data passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program. In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMuhjubjt)}(hUstruct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; };h]hUstruct drm_asahi_helper_program { __u32 binary; __u32 cfg; __u64 data; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMwhjubh)}(h **Members**h]h)}(hj%h]hMembers}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM}hjubj )}(hhh](j)}(hu``binary`` USC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits. h](j)}(h ``binary``h]j)}(hjDh]hbinary}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj>ubj()}(hhh]h)}(hiUSC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits.h]hiUSC address to the helper program binary. This is a tagged pointer with configuration in the bottom bits.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM~hjZubah}(h]h ]h"]h$]h&]uh1j'hj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhMhj;ubj)}(h>``cfg`` Additional configuration bits for the helper program. h](j)}(h``cfg``h]j)}(hj~h]hcfg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjxubj()}(hhh]h)}(h5Additional configuration bits for the helper program.h]h5Additional configuration bits for the helper program.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjxubeh}(h]h ]h"]h$]h&]uh1jhjhMhj;ubj)}(hXu``data`` Data passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program. In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h](j)}(h``data``h]j)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh](h)}(hData passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program.h]hData passed to the helper program. This value is not interpreted by the kernel, firmware, or hardware in any way. It is simply a sideband for userspace, set with the submit ioctl and read via special registers inside the helper program.}(hjЁhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj́ubh)}(h~In practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don't fit in 64-bits.h]hIn practice, userspace will pass a 64-bit GPU VA here pointing to the actual arguments, which presumably don’t fit in 64-bits.}(hj߁hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj́hMhj́ubeh}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj́hMhj;ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubh)}(hXhThe helper program is a compute-like kernel required for various hardware functionality. Its most important role is dynamically allocating scratch/stack memory for individual subgroups, by partitioning a static allocation shared for the whole device. It is supplied by userspace via drm_asahi_helper_program and internally dispatched by the hardware as needed.h]hXhThe helper program is a compute-like kernel required for various hardware functionality. Its most important role is dynamically allocating scratch/stack memory for individual subgroups, by partitioning a static allocation shared for the whole device. It is supplied by userspace via drm_asahi_helper_program and internally dispatched by the hardware as needed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMrhj+Jhhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMxhj+Jhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_bg_eot (C struct)c.drm_asahi_bg_eothNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_bg_eoth]j)}(hstruct drm_asahi_bg_eoth](j)}(hjh]hstruct}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM}ubj)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQhhhjbhM}ubj)}(hdrm_asahi_bg_eoth]j)}(hjOh]hdrm_asahi_bg_eot}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubah}(h]h ](j jeh"]h$]h&]jjuh1jhjQhhhjbhM}ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjMhhhjbhM}ubah}(h]jHah ](j j!eh"]h$]h&]j%j&)j'huh1jhjbhM}hjJhhubj))}(hhh]h)}(h-Describe a background or end-of-tile program.h]h-Describe a background or end-of-tile program.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1j(hjJhhhjbhM}ubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj+JhNhNubjQ)}(hXm**Definition**:: struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; }; **Members** ``usc`` USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits. ``rsrc_spec`` Resource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubjt)}(h@struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; };h]h@struct drm_asahi_bg_eot { __u32 usc; __u32 rsrc_spec; };}hjԂsbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubh)}(h **Members**h]h)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj )}(hhh](j)}(hX>``usc`` USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits. h](j)}(h``usc``h]j)}(hjh]husc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(hX5USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits.h]hX5USC address of the hardware USC words binding resources (including images and uniforms) and the program itself. Note this is an additional layer of indirection compared to the helper program, avoiding the need for a sideband for data. This is a tagged pointer with additional configuration in the bottom bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``rsrc_spec`` Resource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h](j)}(h ``rsrc_spec``h]j)}(hj>h]h rsrc_spec}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj8ubj()}(hhh]h)}(hResource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.h]hResource specifier for the program. This is a packed hardware data structure describing the required number of registers, uniforms, bound textures, and bound samplers.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjTubah}(h]h ]h"]h$]h&]uh1j'hj8ubeh}(h]h ]h"]h$]h&]uh1jhjShMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubh)}(hXThe background and end-of-tile programs are dispatched by the hardware at the beginning and end of rendering. As the hardware "tilebuffer" is simply local memory, these programs are necessary to implement API-level render targets. The fragment-like background program is responsible for loading either the clear colour or the existing render target contents, while the compute-like end-of-tile program stores the tilebuffer contents to memory.h]hXThe background and end-of-tile programs are dispatched by the hardware at the beginning and end of rendering. As the hardware “tilebuffer” is simply local memory, these programs are necessary to implement API-level render targets. The fragment-like background program is responsible for loading either the clear colour or the existing render target contents, while the compute-like end-of-tile program stores the tilebuffer contents to memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubh)}(hIThis struct is embedded in other structs and therefore is not extensible.h]hIThis struct is embedded in other structs and therefore is not extensible.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_cmd_render (C struct)c.drm_asahi_cmd_renderhNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_cmd_renderh]j)}(hstruct drm_asahi_cmd_renderh](j)}(hjh]hstruct}(hj΃hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʃhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj܃hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʃhhhjۃhMubj)}(hdrm_asahi_cmd_renderh]j)}(hjȃh]hdrm_asahi_cmd_render}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjʃhhhjۃhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjƃhhhjۃhMubah}(h]jah ](j j!eh"]h$]h&]j%j&)j'huh1jhjۃhMhjÃhhubj))}(hhh]h)}(hCommand to submit 3Dh]hCommand to submit 3D}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj hhubah}(h]h ]h"]h$]h&]uh1j(hjÃhhhjۃhMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj(jLj(jMjNjOuh1jhhhj+JhNhNubjQ)}(hXh**Definition**:: struct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; }; **Members** ``flags`` Combination of drm_asahi_render_flags flags. ``isp_zls_pixels`` ISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height. ``vdm_ctrl_stream_base`` VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream. ``vertex_helper`` Helper program used for the vertex shader ``fragment_helper`` Helper program used for the fragment shader ``isp_scissor_base`` ISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass. ``isp_dbias_base`` ISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass. ``isp_oclqry_base`` ISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass. ``depth`` Depth buffer ``stencil`` Stencil buffer ``zls_ctrl`` ZLS_CTRL register value ``ppp_multisamplectl`` PPP_MULTISAMPLECTL register value ``sampler_heap`` Base address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps. ``ppp_ctrl`` PPP_CTRL register value ``width_px`` Framebuffer width in pixels ``height_px`` Framebuffer height in pixels ``layers`` Number of layers in the framebuffer ``sampler_count`` Number of samplers in the sampler heap. ``utile_width_px`` Width of a logical tilebuffer tile in pixels ``utile_height_px`` Height of a logical tilebuffer tile in pixels ``samples`` # of samples in the framebuffer. Must be 1, 2, or 4. ``sample_size_B`` # of bytes in the tilebuffer required per sample. ``isp_merge_upper_x`` 32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width. Making these values UAPI avoids requiring floating-point calculations in the kernel in the hot path. ``isp_merge_upper_y`` 32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**. ``bg`` Background program run for each tile at the start ``eot`` End-of-tile program ran for each tile at the end ``partial_bg`` Background program ran at the start of each tile when resuming the render pass during a partial render. ``partial_eot`` End-of-tile program ran at the end of each tile when pausing the render pass during a partial render. ``isp_bgobjdepth`` ISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed). ``isp_bgobjvals`` ISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value. ``ts_vtx`` Timestamps for the vertex portion of the render ``ts_frag`` Timestamps for the fragment portion of the renderh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubh:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj,ubjt)}(hXstruct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; };h]hXstruct drm_asahi_cmd_render { __u32 flags; __u32 isp_zls_pixels; __u64 vdm_ctrl_stream_base; struct drm_asahi_helper_program vertex_helper; struct drm_asahi_helper_program fragment_helper; __u64 isp_scissor_base; __u64 isp_dbias_base; __u64 isp_oclqry_base; struct drm_asahi_zls_buffer depth; struct drm_asahi_zls_buffer stencil; __u64 zls_ctrl; __u64 ppp_multisamplectl; __u64 sampler_heap; __u32 ppp_ctrl; __u16 width_px; __u16 height_px; __u16 layers; __u16 sampler_count; __u8 utile_width_px; __u8 utile_height_px; __u8 samples; __u8 sample_size_B; __u32 isp_merge_upper_x; __u32 isp_merge_upper_y; struct drm_asahi_bg_eot bg; struct drm_asahi_bg_eot eot; struct drm_asahi_bg_eot partial_bg; struct drm_asahi_bg_eot partial_eot; __u32 isp_bgobjdepth; __u32 isp_bgobjvals; struct drm_asahi_timestamps ts_vtx; struct drm_asahi_timestamps ts_frag; };}hjMsbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj,ubh)}(h **Members**h]h)}(hj^h]hMembers}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj,ubj )}(hhh](j)}(h7``flags`` Combination of drm_asahi_render_flags flags. h](j)}(h ``flags``h]j)}(hj}h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjwubj()}(hhh]h)}(h,Combination of drm_asahi_render_flags flags.h]h,Combination of drm_asahi_render_flags flags.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjwubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(h``isp_zls_pixels`` ISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height. h](j)}(h``isp_zls_pixels``h]j)}(hjh]hisp_zls_pixels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(hISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height.h]hISP_ZLS_PIXELS register value. This contains the depth/stencil width/height, which may differ from the framebuffer width/height.}(hjτhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj̄ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj˄hMhjtubj)}(hv``vdm_ctrl_stream_base`` VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream. h](j)}(h``vdm_ctrl_stream_base``h]j)}(hjh]hvdm_ctrl_stream_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(h\VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream.h]h\VDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the VDM control stream.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(h<``vertex_helper`` Helper program used for the vertex shader h](j)}(h``vertex_helper``h]j)}(hj*h]h vertex_helper}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj$ubj()}(hhh]h)}(h)Helper program used for the vertex shaderh]h)Helper program used for the vertex shader}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj@ubah}(h]h ]h"]h$]h&]uh1j'hGj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhjtubj)}(h@``fragment_helper`` Helper program used for the fragment shader h](j)}(h``fragment_helper``h]j)}(hjch]hfragment_helper}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj]ubj()}(hhh]h)}(h+Helper program used for the fragment shaderh]h+Helper program used for the fragment shader}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMhjyubah}(h]h ]h"]h$]h&]uh1j'hj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhMhjtubj)}(h``isp_scissor_base`` ISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass. h](j)}(h``isp_scissor_base``h]j)}(hjh]hisp_scissor_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(hkISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass.h]hkISP_SCISSOR_BASE register value. GPU address of an array of scissor descriptors indexed in the render pass.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(h{``isp_dbias_base`` ISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass. h](j)}(h``isp_dbias_base``h]j)}(hjօh]hisp_dbias_base}(hj؅hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjԅubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjЅubj()}(hhh]h)}(hgISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass.h]hgISP_DBIAS_BASE register value. GPU address of an array of depth bias values indexed in the render pass.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubah}(h]h ]h"]h$]h&]uh1j'hjЅubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(h``isp_oclqry_base`` ISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass. h](j)}(h``isp_oclqry_base``h]j)}(hjh]hisp_oclqry_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj ubj()}(hhh]h)}(hnISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass.h]hnISP_OCLQRY_BASE register value. GPU address of an array of occlusion query results written by the render pass.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj&ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj%hMhjtubj)}(h``depth`` Depth buffer h](j)}(h ``depth``h]j)}(hjJh]hdepth}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjDubj()}(hhh]h)}(h Depth bufferh]h Depth buffer}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hMhj`ubah}(h]h ]h"]h$]h&]uh1j'hjDubeh}(h]h ]h"]h$]h&]uh1jhj_hMhjtubj)}(h``stencil`` Stencil buffer h](j)}(h ``stencil``h]j)}(hjh]hstencil}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj}ubj()}(hhh]h)}(hStencil bufferh]hStencil buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hj}ubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(h%``zls_ctrl`` ZLS_CTRL register value h](j)}(h ``zls_ctrl``h]j)}(hjh]hzls_ctrl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(hZLS_CTRL register valueh]hZLS_CTRL register value}(hjՆhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjцhMhj҆ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjцhMhjtubj)}(h9``ppp_multisamplectl`` PPP_MULTISAMPLECTL register value h](j)}(h``ppp_multisamplectl``h]j)}(hjh]hppp_multisamplectl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(h!PPP_MULTISAMPLECTL register valueh]h!PPP_MULTISAMPLECTL register value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjtubj)}(h``sampler_heap`` Base address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps. h](j)}(h``sampler_heap``h]j)}(hj.h]h sampler_heap}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj(ubj()}(hhh]h)}(hBase address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps.h]hBase address of the sampler heap. This heap is used for both vertex shaders and fragment shaders. The registers are per-stage, but there is no known use case for separate heaps.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjDubah}(h]h ]h"]h$]h&]uh1j'hj(ubeh}(h]h ]h"]h$]h&]uh1jhjChMhjtubj)}(h%``ppp_ctrl`` PPP_CTRL register value h](j)}(h ``ppp_ctrl``h]j)}(hjhh]hppp_ctrl}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM hjbubj()}(hhh]h)}(hPPP_CTRL register valueh]hPPP_CTRL register value}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hM hj~ubah}(h]h ]h"]h$]h&]uh1j'hjbubeh}(h]h ]h"]h$]h&]uh1jhj}hM hjtubj)}(h)``width_px`` Framebuffer width in pixels h](j)}(h ``width_px``h]j)}(hjh]hwidth_px}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM hjubj()}(hhh]h)}(hFramebuffer width in pixelsh]hFramebuffer width in pixels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjtubj)}(h+``height_px`` Framebuffer height in pixels h](j)}(h ``height_px``h]j)}(hjڇh]h height_px}(hj܇hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj؇ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjԇubj()}(hhh]h)}(hFramebuffer height in pixelsh]hFramebuffer height in pixels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjԇubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(h/``layers`` Number of layers in the framebuffer h](j)}(h ``layers``h]j)}(hjh]hlayers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj ubj()}(hhh]h)}(h#Number of layers in the framebufferh]h#Number of layers in the framebuffer}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hMhj)ubah}(h]h ]h"]h$]h&]uh1j'hj ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhjtubj)}(h:``sampler_count`` Number of samplers in the sampler heap. h](j)}(h``sampler_count``h]j)}(hjLh]h sampler_count}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjFubj()}(hhh]h)}(h'Number of samplers in the sampler heap.h]h'Number of samplers in the sampler heap.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahMhjbubah}(h]h ]h"]h$]h&]uh1j'hjFubeh}(h]h ]h"]h$]h&]uh1jhjahMhjtubj)}(h@``utile_width_px`` Width of a logical tilebuffer tile in pixels h](j)}(h``utile_width_px``h]j)}(hjh]hutile_width_px}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(h,Width of a logical tilebuffer tile in pixelsh]h,Width of a logical tilebuffer tile in pixels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjtubj)}(hB``utile_height_px`` Height of a logical tilebuffer tile in pixels h](j)}(h``utile_height_px``h]j)}(hjh]hutile_height_px}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(h-Height of a logical tilebuffer tile in pixelsh]h-Height of a logical tilebuffer tile in pixels}(hj׈hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjӈhMhjԈubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjӈhMhjtubj)}(hA``samples`` # of samples in the framebuffer. Must be 1, 2, or 4. h](j)}(h ``samples``h]j)}(hjh]hsamples}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(h4# of samples in the framebuffer. Must be 1, 2, or 4.h]h4# of samples in the framebuffer. Must be 1, 2, or 4.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjtubj)}(hD``sample_size_B`` # of bytes in the tilebuffer required per sample. h](j)}(h``sample_size_B``h]j)}(hj0h]h sample_size_B}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM!hj*ubj()}(hhh]h)}(h1# of bytes in the tilebuffer required per sample.h]h1# of bytes in the tilebuffer required per sample.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhM!hjFubah}(h]h ]h"]h$]h&]uh1j'hj*ubeh}(h]h ]h"]h$]h&]uh1jhjEhM!hjtubj)}(h``isp_merge_upper_x`` 32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width. Making these values UAPI avoids requiring floating-point calculations in the kernel in the hot path. h](j)}(h``isp_merge_upper_x``h]j)}(hjih]hisp_merge_upper_x}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM)hjcubj()}(hhh](h)}(hV32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width.h]hV32-bit float used in the hardware triangle merging. Calculate as: tan(60 deg) * width.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM%hjubh)}(hdMaking these values UAPI avoids requiring floating-point calculations in the kernel in the hot path.h]hdMaking these values UAPI avoids requiring floating-point calculations in the kernel in the hot path.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM(hjubeh}(h]h ]h"]h$]h&]uh1j'hjcubeh}(h]h ]h"]h$]h&]uh1jhj~hM)hjtubj)}(hc``isp_merge_upper_y`` 32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**. h](j)}(h``isp_merge_upper_y``h]j)}(hjh]hisp_merge_upper_y}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM/hjubj()}(hhh]h)}(hL32-bit float. Calculate as: tan(60 deg) * height. See **isp_merge_upper_x**.h](h632-bit float. Calculate as: tan(60 deg) * height. See }(hjˉhhhNhNubh)}(h**isp_merge_upper_x**h]hisp_merge_upper_x}(hjӉhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjˉubh.}(hjˉhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM.hjȉubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjljhM/hjtubj)}(h9``bg`` Background program run for each tile at the start h](j)}(h``bg``h]j)}(hjh]hbg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM3hjubj()}(hhh]h)}(h1Background program run for each tile at the starth]h1Background program run for each tile at the start}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM3hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhM3hjtubj)}(h9``eot`` End-of-tile program ran for each tile at the end h](j)}(h``eot``h]j)}(hj7h]heot}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM6hj1ubj()}(hhh]h)}(h0End-of-tile program ran for each tile at the endh]h0End-of-tile program ran for each tile at the end}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM6hjMubah}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhM6hjtubj)}(hw``partial_bg`` Background program ran at the start of each tile when resuming the render pass during a partial render. h](j)}(h``partial_bg``h]j)}(hjph]h partial_bg}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM;hjjubj()}(hhh]h)}(hgBackground program ran at the start of each tile when resuming the render pass during a partial render.h]hgBackground program ran at the start of each tile when resuming the render pass during a partial render.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM:hjubah}(h]h ]h"]h$]h&]uh1j'hjjubeh}(h]h ]h"]h$]h&]uh1jhjhM;hjtubj)}(hv``partial_eot`` End-of-tile program ran at the end of each tile when pausing the render pass during a partial render. h](j)}(h``partial_eot``h]j)}(hjh]h partial_eot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMAhjubj()}(hhh]h)}(heEnd-of-tile program ran at the end of each tile when pausing the render pass during a partial render.h]heEnd-of-tile program ran at the end of each tile when pausing the render pass during a partial render.}(hjÊhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM@hjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMAhjtubj)}(h``isp_bgobjdepth`` ISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed). h](j)}(h``isp_bgobjdepth``h]j)}(hjh]hisp_bgobjdepth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMHhjފubj()}(hhh]h)}(hISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer's format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed).h]hISP_BGOBJDEPTH register value. This is the depth buffer clear value, encoded in the depth buffer’s format: either a 32-bit float or a 16-bit unorm (with upper bits zeroed).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMFhjubah}(h]h ]h"]h$]h&]uh1j'hjފubeh}(h]h ]h"]h$]h&]uh1jhjhMHhjtubj)}(hj``isp_bgobjvals`` ISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value. h](j)}(h``isp_bgobjvals``h]j)}(hjh]h isp_bgobjvals}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMNhjubj()}(hhh]h)}(hWISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value.h]hWISP_BGOBJVALS register value. The bottom 8-bits contain the stencil buffer clear value.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMMhj4ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj3hMNhjtubj)}(h;``ts_vtx`` Timestamps for the vertex portion of the render h](j)}(h ``ts_vtx``h]j)}(hjXh]hts_vtx}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMRhjRubj()}(hhh]h)}(h/Timestamps for the vertex portion of the renderh]h/Timestamps for the vertex portion of the render}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhMRhjnubah}(h]h ]h"]h$]h&]uh1j'hjRubeh}(h]h ]h"]h$]h&]uh1jhjmhMRhjtubj)}(h=``ts_frag`` Timestamps for the fragment portion of the renderh](j)}(h ``ts_frag``h]j)}(hjh]hts_frag}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMThjubj()}(hhh]h)}(h1Timestamps for the fragment portion of the renderh]h1Timestamps for the fragment portion of the render}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMUhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMThjtubeh}(h]h ]h"]h$]h&]uh1j hj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hjԋh]h Description}(hj֋hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjҋubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMXhj+Jhhubh)}(hThis command submits a single render pass. The hardware control stream may include many draws and subpasses, but within the command, the framebuffer dimensions and attachments are fixed.h]hThis command submits a single render pass. The hardware control stream may include many draws and subpasses, but within the command, the framebuffer dimensions and attachments are fixed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubh)}(hXBThe hardware requires the firmware to set a large number of Control Registers setting up state at render pass granularity before each command rendering 3D. The firmware bundles this state into data structures. Unfortunately, we cannot expose either any of that directly to userspace, because the kernel-firmware ABI is not stable. Although we can guarantee the firmware updates in tandem with the kernel, we cannot break old userspace when upgrading the firmware and kernel. Therefore, we need to abstract well the data structures to avoid tying our hands with future firmwares.h]hXBThe hardware requires the firmware to set a large number of Control Registers setting up state at render pass granularity before each command rendering 3D. The firmware bundles this state into data structures. Unfortunately, we cannot expose either any of that directly to userspace, because the kernel-firmware ABI is not stable. Although we can guarantee the firmware updates in tandem with the kernel, we cannot break old userspace when upgrading the firmware and kernel. Therefore, we need to abstract well the data structures to avoid tying our hands with future firmwares.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubh)}(hThe bulk of drm_asahi_cmd_render therefore consists of values of hardware control registers, marshalled via the firmware interface.h]hThe bulk of drm_asahi_cmd_render therefore consists of values of hardware control registers, marshalled via the firmware interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubh)}(hXThe framebuffer/tilebuffer dimensions are also specified here. In addition to being passed to the firmware/hardware, the kernel requires these dimensions to calculate various essential tiling-related data structures. It is unfortunate that our submits are heavier than on vendors with saner hardware-software interfaces. The upshot is all of this information is readily available to userspace with all current APIs.h]hXThe framebuffer/tilebuffer dimensions are also specified here. In addition to being passed to the firmware/hardware, the kernel requires these dimensions to calculate various essential tiling-related data structures. It is unfortunate that our submits are heavier than on vendors with saner hardware-software interfaces. The upshot is all of this information is readily available to userspace with all current APIs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubh)}(hiIt looks odd - but it's not overly burdensome and it ensures we can remain compatible with old userspace.h]hkIt looks odd - but it’s not overly burdensome and it ensures we can remain compatible with old userspace.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j drm_asahi_cmd_compute (C struct)c.drm_asahi_cmd_computehNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_cmd_computeh]j)}(hstruct drm_asahi_cmd_computeh](j)}(hjh]hstruct}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubj)}(h h]h }(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJhhhj[hMubj)}(hdrm_asahi_cmd_computeh]j)}(hjHh]hdrm_asahi_cmd_compute}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjJhhhj[hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjFhhhj[hMubah}(h]jAah ](j j!eh"]h$]h&]j%j&)j'huh1jhj[hMhjChhubj))}(hhh]h)}(hCommand to submit computeh]hCommand to submit compute}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMYhjhhubah}(h]h ]h"]h$]h&]uh1j(hjChhhj[hMubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKjjLjjMjNjOuh1jhhhj+JhNhNubjQ)}(hXV**Definition**:: struct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; }; **Members** ``flags`` MBZ ``sampler_count`` Number of samplers in the sampler heap. ``cdm_ctrl_stream_base`` CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream. ``cdm_ctrl_stream_end`` GPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere. ``sampler_heap`` Base address of the sampler heap. ``helper`` Helper program used for this compute command ``ts`` Timestamps for the compute commandh](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM]hjubjt)}(hstruct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; };h]hstruct drm_asahi_cmd_compute { __u32 flags; __u32 sampler_count; __u64 cdm_ctrl_stream_base; __u64 cdm_ctrl_stream_end; __u64 sampler_heap; struct drm_asahi_helper_program helper; struct drm_asahi_timestamps ts; };}hj͌sbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM_hjubh)}(h **Members**h]h)}(hjތh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj܌ubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMihjubj )}(hhh](j)}(h``flags`` MBZ h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMahjubj()}(hhh]h)}(hMBZh]hMBZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMahjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMahjubj)}(h:``sampler_count`` Number of samplers in the sampler heap. h](j)}(h``sampler_count``h]j)}(hj6h]h sampler_count}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMdhj0ubj()}(hhh]h)}(h'Number of samplers in the sampler heap.h]h'Number of samplers in the sampler heap.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMdhjLubah}(h]h ]h"]h$]h&]uh1j'hj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMdhjubj)}(hv``cdm_ctrl_stream_base`` CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream. h](j)}(h``cdm_ctrl_stream_base``h]j)}(hjoh]hcdm_ctrl_stream_base}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMihjiubj()}(hhh]h)}(h\CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream.h]h\CDM_CTRL_STREAM_BASE register value. GPU address to the beginning of the CDM control stream.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhhjubah}(h]h ]h"]h$]h&]uh1j'hjiubeh}(h]h ]h"]h$]h&]uh1jhjhMihjubj)}(h``cdm_ctrl_stream_end`` GPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere. h](j)}(h``cdm_ctrl_stream_end``h]j)}(hjh]hcdm_ctrl_stream_end}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMphjubj()}(hhh]h)}(hGPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere.h]hGPU base address to the end of the hardware control stream. Note this only considers the first contiguous segment of the control stream, as the stream might jump elsewhere.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMnhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMphjubj)}(h3``sampler_heap`` Base address of the sampler heap. h](j)}(h``sampler_heap``h]j)}(hjh]h sampler_heap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMthjݍubj()}(hhh]h)}(h!Base address of the sampler heap.h]h!Base address of the sampler heap.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMthjubah}(h]h ]h"]h$]h&]uh1j'hjݍubeh}(h]h ]h"]h$]h&]uh1jhjhMthjubj)}(h8``helper`` Helper program used for this compute command h](j)}(h ``helper``h]j)}(hjh]hhelper}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMwhjubj()}(hhh]h)}(h,Helper program used for this compute commandh]h,Helper program used for this compute command}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMwhj2ubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhj1hMwhjubj)}(h)``ts`` Timestamps for the compute commandh](j)}(h``ts``h]j)}(hjUh]hts}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMyhjOubj()}(hhh]h)}(h"Timestamps for the compute commandh]h"Timestamps for the compute command}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMzhjkubah}(h]h ]h"]h$]h&]uh1j'hjOubeh}(h]h ]h"]h$]h&]uh1jhjjhMyhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubh)}(h**Description**h]h)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM}hj+Jhhubh)}(hThis command submits a control stream consisting of compute dispatches. There is essentially no limit on how many compute dispatches may be included in a single compute command, although timestamps are at command granularity.h]hThis command submits a control stream consisting of compute dispatches. There is essentially no limit on how many compute dispatches may be included in a single compute command, although timestamps are at command granularity.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMZhj+Jhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdrm_asahi_get_time (C struct)c.drm_asahi_get_timehNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hdrm_asahi_get_timeh]j)}(hstruct drm_asahi_get_timeh](j)}(hjh]hstruct}(hj֎hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҎhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMaubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҎhhhjhMaubj)}(hdrm_asahi_get_timeh]j)}(hjЎh]hdrm_asahi_get_time}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjҎhhhjhMaubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjΎhhhjhMaubah}(h]jɎah ](j j!eh"]h$]h&]j%j&)j'huh1jhjhMahjˎhhubj))}(hhh]h)}(h,Arguments passed to DRM_IOCTL_ASAHI_GET_TIMEh]h,Arguments passed to DRM_IOCTL_ASAHI_GET_TIME}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhM~hjhhubah}(h]h ]h"]h$]h&]uh1j(hjˎhhhjhMaubeh}(h]h ](jEstructeh"]h$]h&]jJjEjKj0jLj0jMjNjOuh1jhhhj+JhNhNubjQ)}(h**Definition**:: struct drm_asahi_get_time { __u64 flags; __u64 gpu_timestamp; }; **Members** ``flags`` MBZ. ``gpu_timestamp`` On return, the GPU timestamp in nanoseconds.h](h)}(h**Definition**::h](h)}(h**Definition**h]h Definition}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8ubh:}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj4ubjt)}(hHstruct drm_asahi_get_time { __u64 flags; __u64 gpu_timestamp; };h]hHstruct drm_asahi_get_time { __u64 flags; __u64 gpu_timestamp; };}hjUsbah}(h]h ]h"]h$]h&]jjuh1jsh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj4ubh)}(h **Members**h]h)}(hjfh]hMembers}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj4ubj )}(hhh](j)}(h``flags`` MBZ. h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(hMBZ.h]hMBZ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj|ubj)}(h>``gpu_timestamp`` On return, the GPU timestamp in nanoseconds.h](j)}(h``gpu_timestamp``h]j)}(hjh]h gpu_timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(h,On return, the GPU timestamp in nanoseconds.h]h,On return, the GPU timestamp in nanoseconds.}(hj׏hhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjԏubah}(h]h ]h"]h$]h&]uh1j'hjubeh}(h]h ]h"]h$]h&]uh1jhjӏhMhj|ubeh}(h]h ]h"]h$]h&]uh1j hj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jPhj+JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jDRM_IOCTL_ASAHI (C macro)c.DRM_IOCTL_ASAHIhNtauh1jhj+JhhhNhNubj)}(hhh](j)}(hDRM_IOCTL_ASAHIh]j)}(hDRM_IOCTL_ASAHIh]j)}(hDRM_IOCTL_ASAHIh]j)}(hjh]hDRM_IOCTL_ASAHI}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j jeh"]h$]h&]jjuh1jhjhhh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMubah}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj/hMubah}(h]j ah ](j j!eh"]h$]h&]j%j&)j'huh1jhj/hMhj hhubj))}(hhh]h}(h]h ]h"]h$]h&]uh1j(hj hhhj/hMubeh}(h]h ](jEmacroeh"]h$]h&]jJjEjKjHjLjHjMjNjOuh1jhhhj+JhNhNubh)}(h,``DRM_IOCTL_ASAHI (__access, __id, __type)``h]j)}(hjNh]h(DRM_IOCTL_ASAHI (__access, __id, __type)}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj+Jhhubj)}(hBuild an Asahi IOCTL number h]h)}(hBuild an Asahi IOCTL numberh]hBuild an Asahi IOCTL number}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjdubah}(h]h ]h"]h$]h&]uh1jhjvhMhj+JhhubjQ)}(hXF**Parameters** ``__access`` Access type. Must be R, W or RW. ``__id`` One of the DRM_ASAHI_xxx id. ``__type`` Suffix of the type being passed to the IOCTL. **Description** Don't use this macro directly, use the DRM_IOCTL_ASAHI_xxx values instead. **Return** An IOCTL number to be passed to ioctl() from userspace.h](h)}(h**Parameters**h]h)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhj}ubj )}(hhh](j)}(h.``__access`` Access type. Must be R, W or RW. h](j)}(h ``__access``h]j)}(hjh]h__access}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh\/var/lib/git/docbuild/linux/Documentation/gpu/driver-uapi:34: ./include/uapi/drm/asahi_drm.hhMhjubj()}(hhh]h)}(h Access type. Must be R, W or RW.h]h Access type. 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