sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/gpu/amdgpu/ring-buffermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h Ring Bufferh]h Ring Buffer}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer.rsthKubh paragraph)}(hTo handle communication between user space and kernel space, AMD GPUs use a ring buffer design to feed the engines (GFX, Compute, SDMA, UVD, VCE, VCN, VPE, etc.). See the figure below that illustrates how this communication works:h]hTo handle communication between user space and kernel space, AMD GPUs use a ring buffer design to feed the engines (GFX, Compute, SDMA, UVD, VCE, VCN, VPE, etc.). See the figure below that illustrates how this communication works:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubkfigure kernel_figure)}(hhh]hfigure)}(hhh]himage)}(h$.. kernel-figure:: ring_buffers.svg h]h}(h]h ]h"]h$]h&]urigpu/amdgpu/ring_buffers.svg candidates}*hsuh1hhhhhhKubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hXERing buffers in the amdgpu work as a producer-consumer model, where userspace acts as the producer, constantly filling the ring buffer with GPU commands to be executed. Meanwhile, the GPU retrieves the information from the ring, parses it, and distributes the specific set of instructions between the different amdgpu blocks.h]hXERing buffers in the amdgpu work as a producer-consumer model, where userspace acts as the producer, constantly filling the ring buffer with GPU commands to be executed. Meanwhile, the GPU retrieves the information from the ring, parses it, and distributes the specific set of instructions between the different amdgpu blocks.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXNotice from the diagram that the ring has a Read Pointer (rptr), which indicates where the engine is currently reading packets from the ring, and a Write Pointer (wptr), which indicates how many packets software has added to the ring. When the rptr and wptr are equal, the ring is idle. When software adds packets to the ring, it updates the wptr, this causes the engine to start fetching and processing packets. As the engine processes packets, the rptr gets updates until the rptr catches up to the wptr and they are equal again.h]hXNotice from the diagram that the ring has a Read Pointer (rptr), which indicates where the engine is currently reading packets from the ring, and a Write Pointer (wptr), which indicates how many packets software has added to the ring. When the rptr and wptr are equal, the ring is idle. When software adds packets to the ring, it updates the wptr, this causes the engine to start fetching and processing packets. As the engine processes packets, the rptr gets updates until the rptr catches up to the wptr and they are equal again.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXUsually, ring buffers in the driver have a limited size (search for occurrences of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is that CP (Command Processor) is capable of following addresses inserted into the ring; this is illustrated in the image by the reference to the IB (Indirect Buffer). The IB gives userspace the possibility to have an area in memory that CP can read and feed the hardware with extra instructions.h](hSUsually, ring buffers in the driver have a limited size (search for occurrences of }(hj hhhNhNubhtitle_reference)}(h`amdgpu_ring_init()`h]hamdgpu_ring_init()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhX]). One of the reasons for the small ring buffer size is that CP (Command Processor) is capable of following addresses inserted into the ring; this is illustrated in the image by the reference to the IB (Indirect Buffer). The IB gives userspace the possibility to have an area in memory that CP can read and feed the hardware with extra instructions.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXAll ASICs pre-GFX11 use what is called a kernel queue, which means the ring is allocated in kernel space and has some restrictions, such as not being able to be :ref:`preempted directly by the scheduler`. GFX11 and newer support kernel queues, but also provide a new mechanism named :ref:`user queues`, where the queue is moved to the user space and can be mapped and unmapped via the scheduler. In practice, both queues insert user-space-generated GPU commands from different jobs into the requested component ring.h](hAll ASICs pre-GFX11 use what is called a kernel queue, which means the ring is allocated in kernel space and has some restrictions, such as not being able to be }(hj-hhhNhNubh)}(h6:ref:`preempted directly by the scheduler`h]hinline)}(hj7h]h#preempted directly by the scheduler}(hj;hhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1j9hj5ubah}(h]h ]h"]h$]h&]refdocgpu/amdgpu/ring-buffer refdomainjFreftyperef refexplicitrefwarn reftarget amdgpu-mesuh1hhhhK hj-ubhP. GFX11 and newer support kernel queues, but also provide a new mechanism named }(hj-hhhNhNubh)}(h :ref:`user queues`h]j:)}(hj`h]h user queues}(hjbhhhNhNubah}(h]h ](jEstdstd-refeh"]h$]h&]uh1j9hj^ubah}(h]h ]h"]h$]h&]refdocjR refdomainjlreftyperef refexplicitrefwarnjX amdgpu-userquh1hhhhK hj-ubh, where the queue is moved to the user space and can be mapped and unmapped via the scheduler. In practice, both queues insert user-space-generated GPU commands from different jobs into the requested component ring.}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hEnforce Isolationh]hEnforce Isolation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK*ubhnote)}(hAfter reading this section, you might want to check the :ref:`Process Isolation` page for more details.h]h)}(hAfter reading this section, you might want to check the :ref:`Process Isolation` page for more details.h](h8After reading this section, you might want to check the }(hjhhhNhNubh)}(h2:ref:`Process Isolation`h]j:)}(hjh]hProcess Isolation}(hjhhhNhNubah}(h]h ](jEstdstd-refeh"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]refdocjR refdomainjreftyperef refexplicitrefwarnjXamdgpu-process-isolationuh1hhhhK,hjubh page for more details.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubh)}(hXBefore examining the Enforce Isolation mechanism in the ring buffer context, it is helpful to briefly discuss how instructions from the ring buffer are processed in the graphics pipeline. Let’s expand on this topic by checking the diagram below that illustrates the graphics pipeline:h]hXBefore examining the Enforce Isolation mechanism in the ring buffer context, it is helpful to briefly discuss how instructions from the ring buffer are processed in the graphics pipeline. Let’s expand on this topic by checking the diagram below that illustrates the graphics pipeline:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjhhubh)}(hhh]h)}(hhh]h)}(h(.. kernel-figure:: gfx_pipeline_seq.svg h]h}(h]h ]h"]h$]h&]urigpu/amdgpu/gfx_pipeline_seq.svgh}hjsuh1hhjhhhKubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK5ubh)}(hXIn terms of executing instructions, the GFX pipeline follows the sequence: Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan Converter (SC), Primitive Assembler (PA), and cache manipulation (which may vary across ASICs). Another common way to describe the pipeline is to use Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages. Now, with this pipeline in mind, let's assume that Job B causes a hang issue, but Job C's instruction might already be executing, leading developers to incorrectly identify Job C as the problematic one. This problem can be mitigated on multiple levels; the diagram below illustrates how to minimize part of this problem:h]hXIn terms of executing instructions, the GFX pipeline follows the sequence: Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan Converter (SC), Primitive Assembler (PA), and cache manipulation (which may vary across ASICs). Another common way to describe the pipeline is to use Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages. Now, with this pipeline in mind, let’s assume that Job B causes a hang issue, but Job C’s instruction might already be executing, leading developers to incorrectly identify Job C as the problematic one. This problem can be mitigated on multiple levels; the diagram below illustrates how to minimize part of this problem:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjhhubh)}(hhh]h)}(hhh]h)}(h,.. kernel-figure:: no_enforce_isolation.svg h]h}(h]h ]h"]h$]h&]uri#gpu/amdgpu/no_enforce_isolation.svgh}hj#suh1hhjhhhKubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKBubh)}(hXNote from the diagram that there is no guarantee of order or a clear separation between instructions, which is not a problem most of the time, and is also good for performance. Furthermore, notice some circles between jobs in the diagram that represent a **fence wait** used to avoid overlapping work in the ring. At the end of the fence, a cache flush occurs, ensuring that when the next job starts, it begins in a clean state and, if issues arise, the developer can pinpoint the problematic process more precisely.h](hNote from the diagram that there is no guarantee of order or a clear separation between instructions, which is not a problem most of the time, and is also good for performance. Furthermore, notice some circles between jobs in the diagram that represent a }(hj1hhhNhNubhstrong)}(h**fence wait**h]h fence wait}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj1ubh used to avoid overlapping work in the ring. At the end of the fence, a cache flush occurs, ensuring that when the next job starts, it begins in a clean state and, if issues arise, the developer can pinpoint the problematic process more precisely.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKChjhhubh)}(hxTo increase the level of isolation between jobs, there is the "Enforce Isolation" method described in the picture below:h]h|To increase the level of isolation between jobs, there is the “Enforce Isolation” method described in the picture below:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjhhubh)}(hhh]h)}(hhh]h)}(h).. kernel-figure:: enforce_isolation.svg h]h}(h]h ]h"]h$]h&]uri gpu/amdgpu/enforce_isolation.svgh}hjrsuh1hhjdhhhKubah}(h]h ]h"]h$]h&]uh1hhjaubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKOubh)}(hXAs shown in the diagram, enforcing isolation introduces ordering between submissions, since the access to GFX/Compute is serialized, think about it as single process at a time mode for gfx/compute. Notice that this approach has a significant performance impact, as it allows only one job to submit commands at a time. However, this option can help pinpoint the job that caused the problem. Although enforcing isolation improves the situation, it does not fully resolve the issue of precisely pinpointing bad jobs, since isolation might mask the problem. In summary, identifying which job caused the issue may not be precise, but enforcing isolation might help with the debugging.h]hXAs shown in the diagram, enforcing isolation introduces ordering between submissions, since the access to GFX/Compute is serialized, think about it as single process at a time mode for gfx/compute. Notice that this approach has a significant performance impact, as it allows only one job to submit commands at a time. However, this option can help pinpoint the job that caused the problem. Although enforcing isolation improves the situation, it does not fully resolve the issue of precisely pinpointing bad jobs, since isolation might mask the problem. In summary, identifying which job caused the issue may not be precise, but enforcing isolation might help with the debugging.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjhhubeh}(h]enforce-isolationah ]h"]enforce isolationah$]h&]uh1hhhhhhhhK*ubh)}(hhh](h)}(hRing Operationsh]hRing Operations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK[ubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single amdgpu_ring_max_ibs (C function)c.amdgpu_ring_max_ibshNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(h=unsigned int amdgpu_ring_max_ibs (enum amdgpu_ring_type type)h]hdesc_signature_line)}(hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hndwh]hndw}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubeh}(h]h ]h"]h$]h&]j'j(uh1j)hjkhhhj}hKJubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjghhhj}hKJubah}(h]jbah ](jjeh"]h$]h&]jj)jhuh1jhj}hKJhjdhhubj)}(hhh]h)}(h!allocate space on the ring bufferh]h!allocate space on the ring buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKJhjhhubah}(h]h ]h"]h$]h&]uh1jhjdhhhj}hKJubeh}(h]h ](jlfunctioneh"]h$]h&]jjljjjjjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``unsigned int ndw`` number of dwords to allocate in the ring buffer **Description** Allocate **ndw** dwords in the ring buffer. The number of dwords should be the sum of all commands written to the ring. **Return** 0 on success, otherwise -ENOMEM if it tries to allocate more than the maximum dword allowed for one submission.h](h)}(h**Parameters**h]j:)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKNhjubj)}(hhh](j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKLhjubj*)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKLhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhKLhjubj)}(hE``unsigned int ndw`` number of dwords to allocate in the ring buffer h](j)}(h``unsigned int ndw``h]j)}(hjh]hunsigned int ndw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKMhjubj*)}(hhh]h)}(h/number of dwords to allocate in the ring bufferh]h/number of dwords to allocate in the ring buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKMhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhKMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j:)}(hj9h]h Description}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj7ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKOhjubh)}(hwAllocate **ndw** dwords in the ring buffer. The number of dwords should be the sum of all commands written to the ring.h](h Allocate }(hjOhhhNhNubj:)}(h**ndw**h]hndw}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjOubhg dwords in the ring buffer. The number of dwords should be the sum of all commands written to the ring.}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKNhjubh)}(h **Return**h]j:)}(hjrh]hReturn}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjpubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKQhjubh)}(ho0 on success, otherwise -ENOMEM if it tries to allocate more than the maximum dword allowed for one submission.h]ho0 on success, otherwise -ENOMEM if it tries to allocate more than the maximum dword allowed for one submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKRhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%amdgpu_ring_alloc_reemit (C function)c.amdgpu_ring_alloc_reemithNtauh1jhjhhhNhNubj)}(hhh](j)}(hJvoid amdgpu_ring_alloc_reemit (struct amdgpu_ring *ring, unsigned int ndw)h]j)}(hIvoid amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKlubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKlubj )}(hamdgpu_ring_alloc_reemith]j)}(hamdgpu_ring_alloc_reemith]hamdgpu_ring_alloc_reemit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhjhhhjhKlubj*)}(h,(struct amdgpu_ring *ring, unsigned int ndw)h](j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]j{)}jnjsbc.amdgpu_ring_alloc_reemitasbuh1hhjubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hringh]hring}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubj0)}(hunsigned int ndwh](j)}(hunsignedh]hunsigned}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubj)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubj)}(hndwh]hndw}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubeh}(h]h ]h"]h$]h&]j'j(uh1j)hjhhhjhKlubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjhhhjhKlubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKlhjhhubj)}(hhh]h)}(h,allocate space on the ring buffer for reemith]h,allocate space on the ring buffer for reemit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKlhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKlubeh}(h]h ](jlfunctioneh"]h$]h&]jjljjjjjjjuh1jhhhjhNhNubj)}(hX;**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``unsigned int ndw`` number of dwords to allocate in the ring buffer **Description** Allocate **ndw** dwords in the ring buffer (all asics). doesn't check the max_dw limit as we may be reemitting several submissions.h](h)}(h**Parameters**h]j:)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKphjubj)}(hhh](j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j)}(h``struct amdgpu_ring *ring``h]j)}(hj h]hstruct amdgpu_ring *ring}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKnhjubj*)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKnhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhKnhjubj)}(hE``unsigned int ndw`` number of dwords to allocate in the ring buffer h](j)}(h``unsigned int ndw``h]j)}(hjBh]hunsigned int ndw}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKohj<ubj*)}(hhh]h)}(h/number of dwords to allocate in the ring bufferh]h/number of dwords to allocate in the ring buffer}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhKohjXubah}(h]h ]h"]h$]h&]uh1j)hj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhKohjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j:)}(hj}h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj{ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKqhjubh)}(hAllocate **ndw** dwords in the ring buffer (all asics). doesn't check the max_dw limit as we may be reemitting several submissions.h](h Allocate }(hjhhhNhNubj:)}(h**ndw**h]hndw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubhu dwords in the ring buffer (all asics). doesn’t check the max_dw limit as we may be reemitting several submissions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKphjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_ring_insert_nop (C function)c.amdgpu_ring_insert_nophNtauh1jhjhhhNhNubj)}(hhh](j)}(hFvoid amdgpu_ring_insert_nop (struct amdgpu_ring *ring, uint32_t count)h]j)}(hEvoid amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj )}(hamdgpu_ring_insert_noph]j)}(hamdgpu_ring_insert_noph]hamdgpu_ring_insert_nop}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhjhhhjhKubj*)}(h*(struct amdgpu_ring *ring, uint32_t count)h](j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hj/ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj, ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj1 modnameN classnameNjrju)}jx]j{)}jnjsbc.amdgpu_ring_insert_nopasbuh1hhj ubj)}(h h]h }(hjO hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hhh]h*}(hj] hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hringh]hring}(hjj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj ubj0)}(huint32_t counth](h)}(hhh]j)}(huint32_th]huint32_t}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj modnameN classnameNjrju)}jx]jK c.amdgpu_ring_insert_nopasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hcounth]hcount}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj ubeh}(h]h ]h"]h$]h&]j'j(uh1j)hjhhhjhKubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hinsert NOP packetsh]hinsert NOP packets}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jlfunctioneh"]h$]h&]jjljj jj jjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``uint32_t count`` the number of NOP packets to insert **Description** This is the generic insert_nop function for rings except SDMAh](h)}(h**Parameters**h]j:)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubj)}(hhh](j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j)}(h``struct amdgpu_ring *ring``h]j)}(hj h]hstruct amdgpu_ring *ring}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubj*)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2 hKhj3 ubah}(h]h ]h"]h$]h&]uh1j)hj ubeh}(h]h ]h"]h$]h&]uh1jhj2 hKhj ubj)}(h7``uint32_t count`` the number of NOP packets to insert h](j)}(h``uint32_t count``h]j)}(hjV h]huint32_t count}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjP ubj*)}(hhh]h)}(h#the number of NOP packets to inserth]h#the number of NOP packets to insert}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk hKhjl ubah}(h]h ]h"]h$]h&]uh1j)hjP ubeh}(h]h ]h"]h$]h&]uh1jhjk hKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j:)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubh)}(h=This is the generic insert_nop function for rings except SDMAh]h=This is the generic insert_nop function for rings except SDMA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'amdgpu_ring_generic_pad_ib (C function)c.amdgpu_ring_generic_pad_ibhNtauh1jhjhhhNhNubj)}(hhh](j)}(hPvoid amdgpu_ring_generic_pad_ib (struct amdgpu_ring *ring, struct amdgpu_ib *ib)h]j)}(hOvoid amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj )}(hamdgpu_ring_generic_pad_ibh]j)}(hamdgpu_ring_generic_pad_ibh]hamdgpu_ring_generic_pad_ib}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhj hhhj hKubj*)}(h0(struct amdgpu_ring *ring, struct amdgpu_ib *ib)h](j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hj1 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj. ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj3 modnameN classnameNjrju)}jx]j{)}jnj sbc.amdgpu_ring_generic_pad_ibasbuh1hhj ubj)}(h h]h }(hjQ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hhh]h*}(hj_ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hringh]hring}(hjl hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj ubj0)}(hstruct amdgpu_ib *ibh](j6)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h amdgpu_ibh]h amdgpu_ib}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj modnameN classnameNjrju)}jx]jM c.amdgpu_ring_generic_pad_ibasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hhh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hibh]hib}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj ubeh}(h]h ]h"]h$]h&]j'j(uh1j)hj hhhj hKubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj)}(hhh]h)}(hpad IB with NOP packetsh]hpad IB with NOP packets}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jlfunctioneh"]h$]h&]jjljj jj jjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``struct amdgpu_ib *ib`` IB to add NOP packets to **Description** This is the generic pad_ib function for rings except SDMAh](h)}(h**Parameters**h]j:)}(hj( h]h Parameters}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj& ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj" ubj)}(hhh](j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjG h]hstruct amdgpu_ring *ring}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjA ubj*)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\ hKhj] ubah}(h]h ]h"]h$]h&]uh1j)hjA ubeh}(h]h ]h"]h$]h&]uh1jhj\ hKhj> ubj)}(h2``struct amdgpu_ib *ib`` IB to add NOP packets to h](j)}(h``struct amdgpu_ib *ib``h]j)}(hj h]hstruct amdgpu_ib *ib}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjz ubj*)}(hhh]h)}(hIB to add NOP packets toh]hIB to add NOP packets to}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j)hjz ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj> ubeh}(h]h ]h"]h$]h&]uh1jhj" ubh)}(h**Description**h]j:)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj" ubh)}(h9This is the generic pad_ib function for rings except SDMAh]h9This is the generic pad_ib function for rings except SDMA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj" ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_ring_commit (C function)c.amdgpu_ring_commithNtauh1jhjhhhNhNubj)}(hhh](j)}(h2void amdgpu_ring_commit (struct amdgpu_ring *ring)h]j)}(h1void amdgpu_ring_commit(struct amdgpu_ring *ring)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj )}(hamdgpu_ring_commith]j)}(hamdgpu_ring_commith]hamdgpu_ring_commit}(hj! hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhj hhhj hKubj*)}(h(struct amdgpu_ring *ring)h]j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hj= hhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hj9 ubj)}(h h]h }(hjJ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9 ubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hj[ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj] modnameN classnameNjrju)}jx]j{)}jnj# sbc.amdgpu_ring_commitasbuh1hhj9 ubj)}(h h]h }(hj{ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9 ubj)}(hhh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9 ubj)}(hringh]hring}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9 ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj5 ubah}(h]h ]h"]h$]h&]j'j(uh1j)hj hhhj hKubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj)}(hhh]h)}(h;tell the GPU to execute the new commands on the ring bufferh]h;tell the GPU to execute the new commands on the ring buffer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jlfunctioneh"]h$]h&]jjljj jj jjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information **Description** Update the wptr (write pointer) to tell the GPU to execute new commands on the ring buffer (all asics).h](h)}(h**Parameters**h]j:)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubj)}(hhh]j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubj*)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j)hj ubeh}(h]h ]h"]h$]h&]uh1jhjhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j:)}(hj<h]h Description}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj:ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubh)}(hgUpdate the wptr (write pointer) to tell the GPU to execute new commands on the ring buffer (all asics).h]hgUpdate the wptr (write pointer) to tell the GPU to execute new commands on the ring buffer (all asics).}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_ring_undo (C function)c.amdgpu_ring_undohNtauh1jhjhhhNhNubj)}(hhh](j)}(h0void amdgpu_ring_undo (struct amdgpu_ring *ring)h]j)}(h/void amdgpu_ring_undo(struct amdgpu_ring *ring)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhhjhKubj )}(hamdgpu_ring_undoh]j)}(hamdgpu_ring_undoh]hamdgpu_ring_undo}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhj}hhhjhKubj*)}(h(struct amdgpu_ring *ring)h]j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]j{)}jnjsbc.amdgpu_ring_undoasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hringh]hring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubah}(h]h ]h"]h$]h&]j'j(uh1j)hj}hhhjhKubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjyhhhjhKubah}(h]jtah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjvhhubj)}(hhh]h)}(hreset the wptrh]hreset the wptr}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj>hhubah}(h]h ]h"]h$]h&]uh1jhjvhhhjhKubeh}(h]h ](jlfunctioneh"]h$]h&]jjljjYjjYjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information **Description** Reset the driver's copy of the wptr (all asics).h](h)}(h**Parameters**h]j:)}(hjch]h Parameters}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjaubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj]ubj)}(hhh]j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj|ubj*)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j)hj|ubeh}(h]h ]h"]h$]h&]uh1jhjhKhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubh)}(h**Description**h]j:)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj]ubh)}(h0Reset the driver's copy of the wptr (all asics).h]h2Reset the driver’s copy of the wptr (all asics).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj]ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_ring_init (C function)c.amdgpu_ring_inithNtauh1jhjhhhNhNubj)}(hhh](j)}(hint amdgpu_ring_init (struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int max_dw, struct amdgpu_irq_src *irq_src, unsigned int irq_type, unsigned int hw_prio, atomic_t *sched_score)h]j)}(hint amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int max_dw, struct amdgpu_irq_src *irq_src, unsigned int irq_type, unsigned int hw_prio, atomic_t *sched_score)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj )}(hamdgpu_ring_inith]j)}(hamdgpu_ring_inith]hamdgpu_ring_init}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhjhhhjhKubj*)}(h(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int max_dw, struct amdgpu_irq_src *irq_src, unsigned int irq_type, unsigned int hw_prio, atomic_t *sched_score)h](j0)}(hstruct amdgpu_device *adevh](j6)}(hjh]hstruct}(hj?hhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hj;ubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubh)}(hhh]j)}(h amdgpu_deviceh]h amdgpu_device}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj_modnameN classnameNjrju)}jx]j{)}jnj%sbc.amdgpu_ring_initasbuh1hhj;ubj)}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj)}(hadevh]hadev}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj7ubj0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]jyc.amdgpu_ring_initasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hringh]hring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj7ubj0)}(hunsigned int max_dwh](j)}(hunsignedh]hunsigned}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hinth]hint}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hmax_dwh]hmax_dw}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj7ubj0)}(hstruct amdgpu_irq_src *irq_srch](j6)}(hjh]hstruct}(hjrhhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hjnubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubh)}(hhh]j)}(hamdgpu_irq_srch]hamdgpu_irq_src}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]jyc.amdgpu_ring_initasbuh1hhjnubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubj)}(hirq_srch]hirq_src}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj7ubj0)}(hunsigned int irq_typeh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hirq_typeh]hirq_type}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj7ubj0)}(hunsigned int hw_prioh](j)}(hunsignedh]hunsigned}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj)}(hinth]hint}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj)}(hhw_prioh]hhw_prio}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj7ubj0)}(hatomic_t *sched_scoreh](h)}(hhh]j)}(hatomic_th]hatomic_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]jyc.amdgpu_ring_initasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h sched_scoreh]h sched_score}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj7ubeh}(h]h ]h"]h$]h&]j'j(uh1j)hjhhhjhKubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hinit driver ring struct.h]hinit driver ring struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jlfunctioneh"]h$]h&]jjljjjjjjjuh1jhhhjhNhNubj)}(hXh**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``unsigned int max_dw`` maximum number of dw for ring alloc ``struct amdgpu_irq_src *irq_src`` interrupt source to use for this ring ``unsigned int irq_type`` interrupt type to use for this ring ``unsigned int hw_prio`` ring priority (NORMAL/HIGH) ``atomic_t *sched_score`` optional score atomic shared with other schedulers **Description** Initialize the driver information for the selected ring (all asics). Returns 0 on success, error on failure.h](h)}(h**Parameters**h]j:)}(hj h]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubj)}(hhh](j)}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j)}(h``struct amdgpu_device *adev``h]j)}(hj+h]hstruct amdgpu_device *adev}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj%ubj*)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hKhjAubah}(h]h ]h"]h$]h&]uh1j)hj%ubeh}(h]h ]h"]h$]h&]uh1jhj@hKhj"ubj)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjdh]hstruct amdgpu_ring *ring}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj^ubj*)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhKhjzubah}(h]h ]h"]h$]h&]uh1j)hj^ubeh}(h]h ]h"]h$]h&]uh1jhjyhKhj"ubj)}(h<``unsigned int max_dw`` maximum number of dw for ring alloc h](j)}(h``unsigned int max_dw``h]j)}(hjh]hunsigned int max_dw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjub)j*)}(hhh]h)}(h#maximum number of dw for ring alloch]h#maximum number of dw for ring alloc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj"ubj)}(hI``struct amdgpu_irq_src *irq_src`` interrupt source to use for this ring h](j)}(h"``struct amdgpu_irq_src *irq_src``h]j)}(hjh]hstruct amdgpu_irq_src *irq_src}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubj*)}(hhh]h)}(h%interrupt source to use for this ringh]h%interrupt source to use for this ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj"ubj)}(h>``unsigned int irq_type`` interrupt type to use for this ring h](j)}(h``unsigned int irq_type``h]j)}(hjh]hunsigned int irq_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubj*)}(hhh]h)}(h#interrupt type to use for this ringh]h#interrupt type to use for this ring}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hKhj%ubah}(h]h ]h"]h$]h&]uh1j)hj ubeh}(h]h ]h"]h$]h&]uh1jhj$hKhj"ubj)}(h5``unsigned int hw_prio`` ring priority (NORMAL/HIGH) h](j)}(h``unsigned int hw_prio``h]j)}(hjHh]hunsigned int hw_prio}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjBubj*)}(hhh]h)}(hring priority (NORMAL/HIGH)h]hring priority (NORMAL/HIGH)}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hKhj^ubah}(h]h ]h"]h$]h&]uh1j)hjBubeh}(h]h ]h"]h$]h&]uh1jhj]hKhj"ubj)}(hM``atomic_t *sched_score`` optional score atomic shared with other schedulers h](j)}(h``atomic_t *sched_score``h]j)}(hjh]hatomic_t *sched_score}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj{ubj*)}(hhh]h)}(h2optional score atomic shared with other schedulersh]h2optional score atomic shared with other schedulers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j)hj{ubeh}(h]h ]h"]h$]h&]uh1jhjhKhj"ubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j:)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubh)}(hlInitialize the driver information for the selected ring (all asics). Returns 0 on success, error on failure.h]hlInitialize the driver information for the selected ring (all asics). Returns 0 on success, error on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_ring_fini (C function)c.amdgpu_ring_finihNtauh1jhjhhhNhNubj)}(hhh](j)}(h0void amdgpu_ring_fini (struct amdgpu_ring *ring)h]j)}(h/void amdgpu_ring_fini(struct amdgpu_ring *ring)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj )}(hamdgpu_ring_finih]j)}(hamdgpu_ring_finih]hamdgpu_ring_fini}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhjhhhjhMubj*)}(h(struct amdgpu_ring *ring)h]j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hj>hhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hj:ubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj^modnameN classnameNjrju)}jx]j{)}jnj$sbc.amdgpu_ring_finiasbuh1hhj:ubj)}(h h]h }(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hringh]hring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj6ubah}(h]h ]h"]h$]h&]j'j(uh1j)hjhhhjhMubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h!tear down the driver ring struct.h]h!tear down the driver ring struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jlfunctioneh"]h$]h&]jjljjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information **Description** Tear down the driver information for the selected ring (all asics).h](h)}(h**Parameters**h]j:)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj)}(hhh]j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj*)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j:)}(hj=h]h Description}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj;ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(hCTear down the driver information for the selected ring (all asics).h]hCTear down the driver information for the selected ring (all asics).}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j7amdgpu_ring_emit_reg_write_reg_wait_helper (C function),c.amdgpu_ring_emit_reg_write_reg_wait_helperhNtauh1jhjhhhNhNubj)}(hhh](j)}(hvoid amdgpu_ring_emit_reg_write_reg_wait_helper (struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask)h]j)}(hvoid amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhhjhMubj )}(h*amdgpu_ring_emit_reg_write_reg_wait_helperh]j)}(h*amdgpu_ring_emit_reg_write_reg_wait_helperh]h*amdgpu_ring_emit_reg_write_reg_wait_helper}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhj~hhhjhMubj*)}(hU(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask)h](j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]j{)}jnjsb,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hringh]hring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubj0)}(h uint32_t reg0h](h)}(hhh]j)}(huint32_th]huint32_t}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj6modnameN classnameNjrju)}jx]j,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhj-ubj)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubj)}(hreg0h]hreg0}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubj0)}(h uint32_t reg1h](h)}(hhh]j)}(huint32_th]huint32_t}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj~modnameN classnameNjrju)}jx]j,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhjuubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubj)}(hreg1h]hreg1}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubj0)}(h uint32_t refh](h)}(hhh]j)}(huint32_th]huint32_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]j,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hrefh]href}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubj0)}(h uint32_t maskh](h)}(hhh]j)}(huint32_th]huint32_t}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]j,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhjubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hmaskh]hmask}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubeh}(h]h ]h"]h$]h&]j'j(uh1j)hj~hhhjhMubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjzhhhjhMubah}(h]juah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjwhhubj)}(hhh]h)}(h ring helperh]h ring helper}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj_hhubah}(h]h ]h"]h$]h&]uh1jhjwhhhjhMubeh}(h]h ](jlfunctioneh"]h$]h&]jjljjzjjzjjjuh1jhhhjhNhNubj)}(hXJ**Parameters** ``struct amdgpu_ring *ring`` ring to write to ``uint32_t reg0`` register to write ``uint32_t reg1`` register to wait on ``uint32_t ref`` reference value to write/wait on ``uint32_t mask`` mask to wait on **Description** Helper for rings that don't support write and wait in a single oneshot packet.h](h)}(h**Parameters**h]j:)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj~ubj)}(hhh](j)}(h.``struct amdgpu_ring *ring`` ring to write to h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj*)}(hhh]h)}(hring to write toh]hring to write to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h$``uint32_t reg0`` register to write h](j)}(h``uint32_t reg0``h]j)}(hjh]h uint32_t reg0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj*)}(hhh]h)}(hregister to writeh]hregister to write}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h&``uint32_t reg1`` register to wait on h](j)}(h``uint32_t reg1``h]j)}(hjh]h uint32_t reg1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj*)}(hhh]h)}(hregister to wait onh]hregister to wait on}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMhj+ubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhj*hMhjubj)}(h2``uint32_t ref`` reference value to write/wait on h](j)}(h``uint32_t ref``h]j)}(hjNh]h uint32_t ref}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjHubj*)}(hhh]h)}(h reference value to write/wait onh]h reference value to write/wait on}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjdubah}(h]h ]h"]h$]h&]uh1j)hjHubeh}(h]h ]h"]h$]h&]uh1jhjchMhjubj)}(h"``uint32_t mask`` mask to wait on h](j)}(h``uint32_t mask``h]j)}(hjh]h uint32_t mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj*)}(hhh]h)}(hmask to wait onh]hmask to wait on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhj~ubh)}(h**Description**h]j:)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj~ubh)}(hNHelper for rings that don't support write and wait in a single oneshot packet.h]hPHelper for rings that don’t support write and wait in a single oneshot packet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj~ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&amdgpu_ring_soft_recovery (C function)c.amdgpu_ring_soft_recoveryhNtauh1jhjhhhNhNubj)}(hhh](j)}(hebool amdgpu_ring_soft_recovery (struct amdgpu_ring *ring, unsigned int vmid, struct dma_fence *fence)h]j)}(hdbool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, struct dma_fence *fence)h](j)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj )}(hamdgpu_ring_soft_recoveryh]j)}(hamdgpu_ring_soft_recoveryh]hamdgpu_ring_soft_recovery}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhjhhhjhMubj*)}(hF(struct amdgpu_ring *ring, unsigned int vmid, struct dma_fence *fence)h](j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hjDhhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hj@ubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjdmodnameN classnameNjrju)}jx]j{)}jnj*sbc.amdgpu_ring_soft_recoveryasbuh1hhj@ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubj)}(hringh]hring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj<ubj0)}(hunsigned int vmidh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hvmidh]hvmid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj<ubj0)}(hstruct dma_fence *fenceh](j6)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h dma_fenceh]h dma_fence}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetj'modnameN classnameNjrju)}jx]j~c.amdgpu_ring_soft_recoveryasbuh1hhjubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hfenceh]hfence}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hj<ubeh}(h]h ]h"]h$]h&]j'j(uh1j)hjhhhjhMubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h!try to soft recover a ring lockuph]h!try to soft recover a ring lockup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jlfunctioneh"]h$]h&]jjljjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` ring to try the recovery on ``unsigned int vmid`` VMID we try to get going again ``struct dma_fence *fence`` timedout fence **Description** Tries to get a ring proceeding again when it is stuck.h](h)}(h**Parameters**h]j:)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj)}(hhh](j)}(h9``struct amdgpu_ring *ring`` ring to try the recovery on h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj*)}(hhh]h)}(hring to try the recovery onh]hring to try the recovery on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h5``unsigned int vmid`` VMID we try to get going again h](j)}(h``unsigned int vmid``h]j)}(hjh]hunsigned int vmid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj*)}(hhh]h)}(hVMID we try to get going againh]hVMID we try to get going again}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h+``struct dma_fence *fence`` timedout fence h](j)}(h``struct dma_fence *fence``h]j)}(hj;h]hstruct dma_fence *fence}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj5ubj*)}(hhh]h)}(htimedout fenceh]htimedout fence}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjQubah}(h]h ]h"]h$]h&]uh1j)hj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j:)}(hjvh]h Description}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjtubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(h6Tries to get a ring proceeding again when it is stuck.h]h6Tries to get a ring proceeding again when it is stuck.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$amdgpu_ring_test_helper (C function)c.amdgpu_ring_test_helperhNtauh1jhjhhhNhNubj)}(hhh](j)}(h6int amdgpu_ring_test_helper (struct amdgpu_ring *ring)h]j)}(h5int amdgpu_ring_test_helper(struct amdgpu_ring *ring)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj )}(hamdgpu_ring_test_helperh]j)}(hamdgpu_ring_test_helperh]hamdgpu_ring_test_helper}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](j"j#eh"]h$]h&]j'j(uh1jhjhhhjhMubj*)}(h(struct amdgpu_ring *ring)h]j0)}(hstruct amdgpu_ring *ringh](j6)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jBah"]h$]h&]uh1j5hjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjlreftypejn reftargetjmodnameN classnameNjrju)}jx]j{)}jnjsbc.amdgpu_ring_test_helperasbuh1hhjubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hringh]hring}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphj'j(uh1j/hjubah}(h]h ]h"]h$]h&]j'j(uh1j)hjhhhjhMubeh}(h]h ]h"]h$]h&]j'j(juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h)tests ring and set sched readiness statush]h)tests ring and set sched readiness status}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjxhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jlfunctioneh"]h$]h&]jjljjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` ring to try the recovery on **Description** Tests ring and set sched readiness status Returns 0 on success, error on failure.h](h)}(h**Parameters**h]j:)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj)}(hhh]j)}(h9``struct amdgpu_ring *ring`` ring to try the recovery on h](j)}(h``struct amdgpu_ring *ring``h]j)}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj*)}(hhh]h)}(hring to try the recovery onh]hring to try the recovery on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j:)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(h)Tests ring and set sched readiness statush]h)Tests ring and set sched readiness status}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(h'Returns 0 on success, error on failure.h]h'Returns 0 on success, error on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h]ring-operationsah ]h"]ring operationsah$]h&]uh1hhhhhhhhK[ubeh}(h] ring-bufferah ]h"] ring bufferah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjeerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j?j<jjj7j4u nametypes}(j?jj7uh}(j<hjjj4jjjjbjgjjjjj j j j jtjyjjjjjujzjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.