[sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/gpu/amdgpu/ring-buffermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/pt_BR/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/gpu/amdgpu/ring-buffermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h Ring Bufferh]h Ring Buffer}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer.rsthKubh paragraph)}(hTo handle communication between user space and kernel space, AMD GPUs use a ring buffer design to feed the engines (GFX, Compute, SDMA, UVD, VCE, VCN, VPE, etc.). See the figure below that illustrates how this communication works:h]hTo handle communication between user space and kernel space, AMD GPUs use a ring buffer design to feed the engines (GFX, Compute, SDMA, UVD, VCE, VCN, VPE, etc.). See the figure below that illustrates how this communication works:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubkfigure kernel_figure)}(hhh]hfigure)}(hhh]himage)}(h$.. kernel-figure:: ring_buffers.svg h]h}(h]h ]h"]h$]h&]urigpu/amdgpu/ring_buffers.svg candidates}*hsuh1hhhhhhKubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hXERing buffers in the amdgpu work as a producer-consumer model, where userspace acts as the producer, constantly filling the ring buffer with GPU commands to be executed. Meanwhile, the GPU retrieves the information from the ring, parses it, and distributes the specific set of instructions between the different amdgpu blocks.h]hXERing buffers in the amdgpu work as a producer-consumer model, where userspace acts as the producer, constantly filling the ring buffer with GPU commands to be executed. Meanwhile, the GPU retrieves the information from the ring, parses it, and distributes the specific set of instructions between the different amdgpu blocks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXNotice from the diagram that the ring has a Read Pointer (rptr), which indicates where the engine is currently reading packets from the ring, and a Write Pointer (wptr), which indicates how many packets software has added to the ring. When the rptr and wptr are equal, the ring is idle. When software adds packets to the ring, it updates the wptr, this causes the engine to start fetching and processing packets. As the engine processes packets, the rptr gets updates until the rptr catches up to the wptr and they are equal again.h]hXNotice from the diagram that the ring has a Read Pointer (rptr), which indicates where the engine is currently reading packets from the ring, and a Write Pointer (wptr), which indicates how many packets software has added to the ring. When the rptr and wptr are equal, the ring is idle. When software adds packets to the ring, it updates the wptr, this causes the engine to start fetching and processing packets. As the engine processes packets, the rptr gets updates until the rptr catches up to the wptr and they are equal again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXUsually, ring buffers in the driver have a limited size (search for occurrences of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is that CP (Command Processor) is capable of following addresses inserted into the ring; this is illustrated in the image by the reference to the IB (Indirect Buffer). The IB gives userspace the possibility to have an area in memory that CP can read and feed the hardware with extra instructions.h](hSUsually, ring buffers in the driver have a limited size (search for occurrences of }(hjhhhNhNubhtitle_reference)}(h`amdgpu_ring_init()`h]hamdgpu_ring_init()}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubhX]). One of the reasons for the small ring buffer size is that CP (Command Processor) is capable of following addresses inserted into the ring; this is illustrated in the image by the reference to the IB (Indirect Buffer). The IB gives userspace the possibility to have an area in memory that CP can read and feed the hardware with extra instructions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXAll ASICs pre-GFX11 use what is called a kernel queue, which means the ring is allocated in kernel space and has some restrictions, such as not being able to be :ref:`preempted directly by the scheduler`. GFX11 and newer support kernel queues, but also provide a new mechanism named :ref:`user queues`, where the queue is moved to the user space and can be mapped and unmapped via the scheduler. In practice, both queues insert user-space-generated GPU commands from different jobs into the requested component ring.h](hAll ASICs pre-GFX11 use what is called a kernel queue, which means the ring is allocated in kernel space and has some restrictions, such as not being able to be }(hjAhhhNhNubh)}(h6:ref:`preempted directly by the scheduler`h]hinline)}(hjKh]h#preempted directly by the scheduler}(hjOhhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jMhjIubah}(h]h ]h"]h$]h&]refdocgpu/amdgpu/ring-buffer refdomainjZreftyperef refexplicitrefwarn reftarget amdgpu-mesuh1hhhhK hjAubhP. GFX11 and newer support kernel queues, but also provide a new mechanism named }(hjAhhhNhNubh)}(h :ref:`user queues`h]jN)}(hjth]h user queues}(hjvhhhNhNubah}(h]h ](jYstdstd-refeh"]h$]h&]uh1jMhjrubah}(h]h ]h"]h$]h&]refdocjf refdomainjreftyperef refexplicitrefwarnjl amdgpu-userquh1hhhhK hjAubh, where the queue is moved to the user space and can be mapped and unmapped via the scheduler. In practice, both queues insert user-space-generated GPU commands from different jobs into the requested component ring.}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hEnforce Isolationh]hEnforce Isolation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK*ubhnote)}(hAfter reading this section, you might want to check the :ref:`Process Isolation` page for more details.h]h)}(hAfter reading this section, you might want to check the :ref:`Process Isolation` page for more details.h](h8After reading this section, you might want to check the }(hjhhhNhNubh)}(h2:ref:`Process Isolation`h]jN)}(hjh]hProcess Isolation}(hjhhhNhNubah}(h]h ](jYstdstd-refeh"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]refdocjf refdomainjreftyperef refexplicitrefwarnjlamdgpu-process-isolationuh1hhhhK,hjubh page for more details.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubh)}(hXBefore examining the Enforce Isolation mechanism in the ring buffer context, it is helpful to briefly discuss how instructions from the ring buffer are processed in the graphics pipeline. Let’s expand on this topic by checking the diagram below that illustrates the graphics pipeline:h]hXBefore examining the Enforce Isolation mechanism in the ring buffer context, it is helpful to briefly discuss how instructions from the ring buffer are processed in the graphics pipeline. Let’s expand on this topic by checking the diagram below that illustrates the graphics pipeline:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjhhubh)}(hhh]h)}(hhh]h)}(h(.. kernel-figure:: gfx_pipeline_seq.svg h]h}(h]h ]h"]h$]h&]urigpu/amdgpu/gfx_pipeline_seq.svgh}hj suh1hhjhhhKubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK5ubh)}(hXIn terms of executing instructions, the GFX pipeline follows the sequence: Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan Converter (SC), Primitive Assembler (PA), and cache manipulation (which may vary across ASICs). Another common way to describe the pipeline is to use Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages. Now, with this pipeline in mind, let's assume that Job B causes a hang issue, but Job C's instruction might already be executing, leading developers to incorrectly identify Job C as the problematic one. This problem can be mitigated on multiple levels; the diagram below illustrates how to minimize part of this problem:h]hXIn terms of executing instructions, the GFX pipeline follows the sequence: Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan Converter (SC), Primitive Assembler (PA), and cache manipulation (which may vary across ASICs). Another common way to describe the pipeline is to use Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages. Now, with this pipeline in mind, let’s assume that Job B causes a hang issue, but Job C’s instruction might already be executing, leading developers to incorrectly identify Job C as the problematic one. This problem can be mitigated on multiple levels; the diagram below illustrates how to minimize part of this problem:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjhhubh)}(hhh]h)}(hhh]h)}(h,.. kernel-figure:: no_enforce_isolation.svg h]h}(h]h ]h"]h$]h&]uri#gpu/amdgpu/no_enforce_isolation.svgh}hj7suh1hhj)hhhKubah}(h]h ]h"]h$]h&]uh1hhj&ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKBubh)}(hXNote from the diagram that there is no guarantee of order or a clear separation between instructions, which is not a problem most of the time, and is also good for performance. Furthermore, notice some circles between jobs in the diagram that represent a **fence wait** used to avoid overlapping work in the ring. At the end of the fence, a cache flush occurs, ensuring that when the next job starts, it begins in a clean state and, if issues arise, the developer can pinpoint the problematic process more precisely.h](hNote from the diagram that there is no guarantee of order or a clear separation between instructions, which is not a problem most of the time, and is also good for performance. Furthermore, notice some circles between jobs in the diagram that represent a }(hjEhhhNhNubhstrong)}(h**fence wait**h]h fence wait}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjEubh used to avoid overlapping work in the ring. At the end of the fence, a cache flush occurs, ensuring that when the next job starts, it begins in a clean state and, if issues arise, the developer can pinpoint the problematic process more precisely.}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKChjhhubh)}(hxTo increase the level of isolation between jobs, there is the "Enforce Isolation" method described in the picture below:h]h|To increase the level of isolation between jobs, there is the “Enforce Isolation” method described in the picture below:}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjhhubh)}(hhh]h)}(hhh]h)}(h).. kernel-figure:: enforce_isolation.svg h]h}(h]h ]h"]h$]h&]uri gpu/amdgpu/enforce_isolation.svgh}hjsuh1hhjxhhhKubah}(h]h ]h"]h$]h&]uh1hhjuubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKOubh)}(hXAs shown in the diagram, enforcing isolation introduces ordering between submissions, since the access to GFX/Compute is serialized, think about it as single process at a time mode for gfx/compute. Notice that this approach has a significant performance impact, as it allows only one job to submit commands at a time. However, this option can help pinpoint the job that caused the problem. Although enforcing isolation improves the situation, it does not fully resolve the issue of precisely pinpointing bad jobs, since isolation might mask the problem. In summary, identifying which job caused the issue may not be precise, but enforcing isolation might help with the debugging.h]hXAs shown in the diagram, enforcing isolation introduces ordering between submissions, since the access to GFX/Compute is serialized, think about it as single process at a time mode for gfx/compute. Notice that this approach has a significant performance impact, as it allows only one job to submit commands at a time. However, this option can help pinpoint the job that caused the problem. Although enforcing isolation improves the situation, it does not fully resolve the issue of precisely pinpointing bad jobs, since isolation might mask the problem. In summary, identifying which job caused the issue may not be precise, but enforcing isolation might help with the debugging.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjhhubeh}(h]enforce-isolationah ]h"]enforce isolationah$]h&]uh1hhhhhhhhK*ubh)}(hhh](h)}(hRing Operationsh]hRing Operations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK[ubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single amdgpu_ring_max_ibs (C function)c.amdgpu_ring_max_ibshNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(h=unsigned int amdgpu_ring_max_ibs (enum amdgpu_ring_type type)h]hdesc_signature_line)}(h)}(h,(struct amdgpu_ring *ring, unsigned int ndw)h](jD)}(hstruct amdgpu_ring *ringh](jJ)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.amdgpu_ring_allocasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubhdesc_sig_punctuation)}(hhh]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1j hjubj#)}(hringh]hring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubjD)}(hunsigned int ndwh](j)}(hunsignedh]hunsigned}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(h h]h }(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(hinth]hint}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj#)}(hndwh]hndw}(hjnhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj2ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubeh}(h]h ]h"]h$]h&]j;j<uh1j=hjhhhjhKJubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhj{hhhjhKJubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1jhjhKJhjxhhubj)}(hhh]h)}(h!allocate space on the ring bufferh]h!allocate space on the ring buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKJhjhhubah}(h]h ]h"]h$]h&]uh1jhjxhhhjhKJubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``unsigned int ndw`` number of dwords to allocate in the ring buffer **Description** Allocate **ndw** dwords in the ring buffer. The number of dwords should be the sum of all commands written to the ring. **Return** 0 on success, otherwise -ENOMEM if it tries to allocate more than the maximum dword allowed for one submission.h](h)}(h**Parameters**h]jN)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKNhjubj)}(hhh](j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j")}(h``struct amdgpu_ring *ring``h]j()}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKLhjubj>)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKLhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhKLhjubj)}(hE``unsigned int ndw`` number of dwords to allocate in the ring buffer h](j")}(h``unsigned int ndw``h]j()}(hjh]hunsigned int ndw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKMhj ubj>)}(hhh]h)}(h/number of dwords to allocate in the ring bufferh]h/number of dwords to allocate in the ring buffer}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hKMhj(ubah}(h]h ]h"]h$]h&]uh1j=hj ubeh}(h]h ]h"]h$]h&]uh1jhj'hKMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jN)}(hjMh]h Description}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjKubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKOhjubh)}(hwAllocate **ndw** dwords in the ring buffer. The number of dwords should be the sum of all commands written to the ring.h](h Allocate }(hjchhhNhNubjN)}(h**ndw**h]hndw}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjcubhg dwords in the ring buffer. The number of dwords should be the sum of all commands written to the ring.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKNhjubh)}(h **Return**h]jN)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKQhjubh)}(ho0 on success, otherwise -ENOMEM if it tries to allocate more than the maximum dword allowed for one submission.h]ho0 on success, otherwise -ENOMEM if it tries to allocate more than the maximum dword allowed for one submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKRhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_ring_insert_nop (C function)c.amdgpu_ring_insert_nophNtauh1jhjhhhNhNubj)}(hhh](j)}(hFvoid amdgpu_ring_insert_nop (struct amdgpu_ring *ring, uint32_t count)h]j)}(hEvoid amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKoubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKoubj)}(hamdgpu_ring_insert_noph]j#)}(hamdgpu_ring_insert_noph]hamdgpu_ring_insert_nop}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhjhhhjhKoubj>)}(h*(struct amdgpu_ring *ring, uint32_t count)h](jD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hj&hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj#ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj(modnameN classnameNjj)}j]j)}jjsbc.amdgpu_ring_insert_nopasbuh1hhjubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj#)}(hringh]hring}(hjahhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubjD)}(huint32_t counth](h)}(hhh]j#)}(huint32_th]huint32_t}(hj}hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjzubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jBc.amdgpu_ring_insert_nopasbuh1hhjvubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj#)}(hcounth]hcount}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjvubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubeh}(h]h ]h"]h$]h&]j;j<uh1j=hjhhhjhKoubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhjhhhjhKoubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKohjhhubj)}(hhh]h)}(hinsert NOP packetsh]hinsert NOP packets}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKohjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKoubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``uint32_t count`` the number of NOP packets to insert **Description** This is the generic insert_nop function for rings except SDMAh](h)}(h**Parameters**h]jN)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKshjubj)}(hhh](j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j")}(h``struct amdgpu_ring *ring``h]j()}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKqhjubj>)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hKqhj*ubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhj)hKqhj ubj)}(h7``uint32_t count`` the number of NOP packets to insert h](j")}(h``uint32_t count``h]j()}(hjMh]huint32_t count}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjKubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKrhjGubj>)}(hhh]h)}(h#the number of NOP packets to inserth]h#the number of NOP packets to insert}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhKrhjcubah}(h]h ]h"]h$]h&]uh1j=hjGubeh}(h]h ]h"]h$]h&]uh1jhjbhKrhj ubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jN)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKthjubh)}(h=This is the generic insert_nop function for rings except SDMAh]h=This is the generic insert_nop function for rings except SDMA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKshjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'amdgpu_ring_generic_pad_ib (C function)c.amdgpu_ring_generic_pad_ibhNtauh1jhjhhhNhNubj)}(hhh](j)}(hPvoid amdgpu_ring_generic_pad_ib (struct amdgpu_ring *ring, struct amdgpu_ib *ib)h]j)}(hOvoid amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hamdgpu_ring_generic_pad_ibh]j#)}(hamdgpu_ring_generic_pad_ibh]hamdgpu_ring_generic_pad_ib}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhjhhhjhKubj>)}(h0(struct amdgpu_ring *ring, struct amdgpu_ib *ib)h](jD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hj( hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj% ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj* modnameN classnameNjj)}j]j)}jjsbc.amdgpu_ring_generic_pad_ibasbuh1hhj ubj)}(h h]h }(hjH hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hhh]h*}(hjV hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj#)}(hringh]hring}(hjc hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj ubjD)}(hstruct amdgpu_ib *ibh](jJ)}(hjh]hstruct}(hj| hhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjx ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx ubh)}(hhh]j#)}(h amdgpu_ibh]h amdgpu_ib}(hj hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jD c.amdgpu_ring_generic_pad_ibasbuh1hhjx ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx ubj)}(hhh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjx ubj#)}(hibh]hib}(hj hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjx ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj ubeh}(h]h ]h"]h$]h&]j;j<uh1j=hjhhhjhKubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hpad IB with NOP packetsh]hpad IB with NOP packets}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``struct amdgpu_ib *ib`` IB to add NOP packets to **Description** This is the generic pad_ib function for rings except SDMAh](h)}(h**Parameters**h]jN)}(hj h]h Parameters}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubj)}(hhh](j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j")}(h``struct amdgpu_ring *ring``h]j()}(hj> h]hstruct amdgpu_ring *ring}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj< ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj8 ubj>)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjS hKhjT ubah}(h]h ]h"]h$]h&]uh1j=hj8 ubeh}(h]h ]h"]h$]h&]uh1jhjS hKhj5 ubj)}(h2``struct amdgpu_ib *ib`` IB to add NOP packets to h](j")}(h``struct amdgpu_ib *ib``h]j()}(hjw h]hstruct amdgpu_ib *ib}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hju ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjq ubj>)}(hhh]h)}(hIB to add NOP packets toh]hIB to add NOP packets to}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j=hjq ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj5 ubeh}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]jN)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubh)}(h9This is the generic pad_ib function for rings except SDMAh]h9This is the generic pad_ib function for rings except SDMA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_ring_commit (C function)c.amdgpu_ring_commithNtauh1jhjhhhNhNubj)}(hhh](j)}(h2void amdgpu_ring_commit (struct amdgpu_ring *ring)h]j)}(h1void amdgpu_ring_commit(struct amdgpu_ring *ring)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hamdgpu_ring_commith]j#)}(hamdgpu_ring_commith]hamdgpu_ring_commit}(hj hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj ubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhj hhhj hKubj>)}(h(struct amdgpu_ring *ring)h]jD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hj4 hhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhj0 ubj)}(h h]h }(hjA hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0 ubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hjR hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjO ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjT modnameN classnameNjj)}j]j)}jj sbc.amdgpu_ring_commitasbuh1hhj0 ubj)}(h h]h }(hjr hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0 ubj)}(hhh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj0 ubj#)}(hringh]hring}(hj hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj0 ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj, ubah}(h]h ]h"]h$]h&]j;j<uh1j=hj hhhj hKubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj)}(hhh]h)}(h;tell the GPU to execute the new commands on the ring bufferh]h;tell the GPU to execute the new commands on the ring buffer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information **Description** Update the wptr (write pointer) to tell the GPU to execute new commands on the ring buffer (all asics).h](h)}(h**Parameters**h]jN)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubj)}(hhh]j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j")}(h``struct amdgpu_ring *ring``h]j()}(hj h]hstruct amdgpu_ring *ring}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubj>)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j=hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]jN)}(hj3 h]h Description}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhj1 ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubh)}(hgUpdate the wptr (write pointer) to tell the GPU to execute new commands on the ring buffer (all asics).h]hgUpdate the wptr (write pointer) to tell the GPU to execute new commands on the ring buffer (all asics).}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_ring_undo (C function)c.amdgpu_ring_undohNtauh1jhjhhhNhNubj)}(hhh](j)}(h0void amdgpu_ring_undo (struct amdgpu_ring *ring)h]j)}(h/void amdgpu_ring_undo(struct amdgpu_ring *ring)h](j)}(hvoidh]hvoid}(hjx hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjt hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjt hhhj hKubj)}(hamdgpu_ring_undoh]j#)}(hamdgpu_ring_undoh]hamdgpu_ring_undo}(hj hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj ubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhjt hhhj hKubj>)}(h(struct amdgpu_ring *ring)h]jD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hj hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jj sbc.amdgpu_ring_undoasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hhh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj ubj#)}(hringh]hring}(hj hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj ubah}(h]h ]h"]h$]h&]j;j<uh1j=hjt hhhj hKubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhjp hhhj hKubah}(h]jk ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhjm hhubj)}(hhh]h)}(hreset the wptrh]hreset the wptr}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj5 hhubah}(h]h ]h"]h$]h&]uh1jhjm hhhj hKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjP jjP jjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information **Description** Reset the driver's copy of the wptr (all asics).h](h)}(h**Parameters**h]jN)}(hjZ h]h Parameters}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjX ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjT ubj)}(hhh]j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j")}(h``struct amdgpu_ring *ring``h]j()}(hjy h]hstruct amdgpu_ring *ring}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjw ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjs ubj>)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j=hjs ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjp ubah}(h]h ]h"]h$]h&]uh1jhjT ubh)}(h**Description**h]jN)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjT ubh)}(h0Reset the driver's copy of the wptr (all asics).h]h2Reset the driver’s copy of the wptr (all asics).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjT ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_ring_init (C function)c.amdgpu_ring_inithNtauh1jhjhhhNhNubj)}(hhh](j)}(hint amdgpu_ring_init (struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int max_dw, struct amdgpu_irq_src *irq_src, unsigned int irq_type, unsigned int hw_prio, atomic_t *sched_score)h]j)}(hint amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int max_dw, struct amdgpu_irq_src *irq_src, unsigned int irq_type, unsigned int hw_prio, atomic_t *sched_score)h](j)}(hinth]hint}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhjhKubj)}(hamdgpu_ring_inith]j#)}(hamdgpu_ring_inith]hamdgpu_ring_init}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhj hhhjhKubj>)}(h(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int max_dw, struct amdgpu_irq_src *irq_src, unsigned int irq_type, unsigned int hw_prio, atomic_t *sched_score)h](jD)}(hstruct amdgpu_device *adevh](jJ)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhj2ubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubh)}(hhh]j#)}(h amdgpu_deviceh]h amdgpu_device}(hjThhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjQubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjVmodnameN classnameNjj)}j]j)}jjsbc.amdgpu_ring_initasbuh1hhj2ubj)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj2ubj#)}(hadevh]hadev}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj2ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj.ubjD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jpc.amdgpu_ring_initasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj#)}(hringh]hring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj.ubjD)}(hunsigned int max_dwh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hinth]hint}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj#)}(hmax_dwh]hmax_dw}(hjPhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj.ubjD)}(hstruct amdgpu_irq_src *irq_srch](jJ)}(hjh]hstruct}(hjihhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjeubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubh)}(hhh]j#)}(hamdgpu_irq_srch]hamdgpu_irq_src}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jpc.amdgpu_ring_initasbuh1hhjeubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjeubj#)}(hirq_srch]hirq_src}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjeubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj.ubjD)}(hunsigned int irq_typeh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj#)}(hirq_typeh]hirq_type}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj.ubjD)}(hunsigned int hw_prioh](j)}(hunsignedh]hunsigned}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(hinth]hint}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj#)}(hhw_prioh]hhw_prio}(hjbhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj&ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj.ubjD)}(hatomic_t *sched_scoreh](h)}(hhh]j#)}(hatomic_th]hatomic_t}(hj~hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jpc.amdgpu_ring_initasbuh1hhjwubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjwubj#)}(h sched_scoreh]h sched_score}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjwubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj.ubeh}(h]h ]h"]h$]h&]j;j<uh1j=hj hhhjhKubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhj hhhjhKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhjhKhj hhubj)}(hhh]h)}(hinit driver ring struct.h]hinit driver ring struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhj hhhjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hXh**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information ``unsigned int max_dw`` maximum number of dw for ring alloc ``struct amdgpu_irq_src *irq_src`` interrupt source to use for this ring ``unsigned int irq_type`` interrupt type to use for this ring ``unsigned int hw_prio`` ring priority (NORMAL/HIGH) ``atomic_t *sched_score`` optional score atomic shared with other schedulers **Description** Initialize the driver information for the selected ring (all asics). Returns 0 on success, error on failure.h](h)}(h**Parameters**h]jN)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubj)}(hhh](j)}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j")}(h``struct amdgpu_device *adev``h]j()}(hj"h]hstruct amdgpu_device *adev}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubj>)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hKhj8ubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhj7hKhjubj)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j")}(h``struct amdgpu_ring *ring``h]j()}(hj[h]hstruct amdgpu_ring *ring}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjYubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjUubj>)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphKhjqubah}(h]h ]h"]h$]h&]uh1j=hjUubeh}(h]h ]h"]h$]h&]uh1jhjphKhjubj)}(h<``unsigned int max_dw`` maximum number of dw for ring alloc h](j")}(h``unsigned int max_dw``h]j()}(hjh]hunsigned int max_dw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubj>)}(hhh]h)}(h#maximum number of dw for ring alloch]h#maximum number of dw for ring alloc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hI``struct amdgpu_irq_src *irq_src`` interrupt source to use for this ring h](j")}(h"``struct amdgpu_irq_src *irq_src``h]j()}(hjh]hstruct amdgpu_irq_src *irq_src}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubj>)}(hhh]h)}(h%interrupt source to use for this ringh]h%interrupt source to use for this ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h>``unsigned int irq_type`` interrupt type to use for this ring h](j")}(h``unsigned int irq_type``h]j()}(hjh]hunsigned int irq_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubj>)}(hhh]h)}(h#interrupt type to use for this ringh]h#interrupt type to use for this ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h5``unsigned int hw_prio`` ring priority (NORMAL/HIGH) h](j")}(h``unsigned int hw_prio``h]j()}(hj?h]hunsigned int hw_prio}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj=ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhj9ubj>)}(hhh]h)}(hring priority (NORMAL/HIGH)h]hring priority (NORMAL/HIGH)}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThKhjUubah}(h]h ]h"]h$]h&]uh1j=hj9ubeh}(h]h ]h"]h$]h&]uh1jhjThKhjubj)}(hM``atomic_t *sched_score`` optional score atomic shared with other schedulers h](j")}(h``atomic_t *sched_score``h]j()}(hjxh]hatomic_t *sched_score}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjvubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjrubj>)}(hhh]h)}(h2optional score atomic shared with other schedulersh]h2optional score atomic shared with other schedulers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j=hjrubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jN)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubh)}(hlInitialize the driver information for the selected ring (all asics). Returns 0 on success, error on failure.h]hlInitialize the driver information for the selected ring (all asics). Returns 0 on success, error on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_ring_fini (C function)c.amdgpu_ring_finihNtauh1jhjhhhNhNubj)}(hhh](j)}(h0void amdgpu_ring_fini (struct amdgpu_ring *ring)h]j)}(h/void amdgpu_ring_fini(struct amdgpu_ring *ring)h](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hamdgpu_ring_finih]j#)}(hamdgpu_ring_finih]hamdgpu_ring_fini}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhjhhhjhMubj>)}(h(struct amdgpu_ring *ring)h]jD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhj1ubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hjShhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjPubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]j)}jjsbc.amdgpu_ring_finiasbuh1hhj1ubj)}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj1ubj#)}(hringh]hring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj1ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj-ubah}(h]h ]h"]h$]h&]j;j<uh1j=hjhhhjhMubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h!tear down the driver ring struct.h]h!tear down the driver ring struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c hMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information **Description** Tear down the driver information for the selected ring (all asics).h](h)}(h**Parameters**h]jN)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj)}(hhh]j)}(hL``struct amdgpu_ring *ring`` amdgpu_ring structure holding ring information h](j")}(h``struct amdgpu_ring *ring``h]j()}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj>)}(hhh]h)}(h.amdgpu_ring structure holding ring informationh]h.amdgpu_ring structure holding ring information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jN)}(hj4h]h Description}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhj2ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(hCTear down the driver information for the selected ring (all asics).h]hCTear down the driver information for the selected ring (all asics).}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j7amdgpu_ring_emit_reg_write_reg_wait_helper (C function),c.amdgpu_ring_emit_reg_write_reg_wait_helperhNtauh1jhjhhhNhNubj)}(hhh](j)}(hvoid amdgpu_ring_emit_reg_write_reg_wait_helper (struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask)h]j)}(hvoid amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask)h](j)}(hvoidh]hvoid}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuhhhjhMubj)}(h*amdgpu_ring_emit_reg_write_reg_wait_helperh]j#)}(h*amdgpu_ring_emit_reg_write_reg_wait_helperh]h*amdgpu_ring_emit_reg_write_reg_wait_helper}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhjuhhhjhMubj>)}(hU(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask)h](jD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj#)}(hringh]hring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubjD)}(h uint32_t reg0h](h)}(hhh]j#)}(huint32_th]huint32_t}(hj+hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj(ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj-modnameN classnameNjj)}j]j,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhj$ubj)}(h h]h }(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj#)}(hreg0h]hreg0}(hjWhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj$ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubjD)}(h uint32_t reg1h](h)}(hhh]j#)}(huint32_th]huint32_t}(hjshhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjpubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjumodnameN classnameNjj)}j]j,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhjlubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubj#)}(hreg1h]hreg1}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjlubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubjD)}(h uint32_t refh](h)}(hhh]j#)}(huint32_th]huint32_t}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj#)}(hrefh]href}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubjD)}(h uint32_t maskh](h)}(hhh]j#)}(huint32_th]huint32_t}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j,c.amdgpu_ring_emit_reg_write_reg_wait_helperasbuh1hhjubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj#)}(hmaskh]hmask}(hj/hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubeh}(h]h ]h"]h$]h&]j;j<uh1j=hjuhhhjhMubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhjqhhhjhMubah}(h]jlah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjnhhubj)}(hhh]h)}(h ring helperh]h ring helper}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjVhhubah}(h]h ]h"]h$]h&]uh1jhjnhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjqjjqjjjuh1jhhhjhNhNubj)}(hXJ**Parameters** ``struct amdgpu_ring *ring`` ring to write to ``uint32_t reg0`` register to write ``uint32_t reg1`` register to wait on ``uint32_t ref`` reference value to write/wait on ``uint32_t mask`` mask to wait on **Description** Helper for rings that don't support write and wait in a single oneshot packet.h](h)}(h**Parameters**h]jN)}(hj{h]h Parameters}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjyubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjuubj)}(hhh](j)}(h.``struct amdgpu_ring *ring`` ring to write to h](j")}(h``struct amdgpu_ring *ring``h]j()}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj>)}(hhh]h)}(hring to write toh]hring to write to}(hjhhhNhNubah}(h]h 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h](j")}(h``uint32_t ref``h]j()}(hjEh]h uint32_t ref}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjCubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj?ubj>)}(hhh]h)}(h reference value to write/wait onh]h reference value to write/wait on}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhMhj[ubah}(h]h ]h"]h$]h&]uh1j=hj?ubeh}(h]h ]h"]h$]h&]uh1jhjZhMhjubj)}(h"``uint32_t mask`` mask to wait on h](j")}(h``uint32_t mask``h]j()}(hj~h]h uint32_t mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj|ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjxubj>)}(hhh]h)}(hmask to wait onh]hmask to wait on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j=hjxubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjuubh)}(h**Description**h]jN)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjuubh)}(hNHelper for rings that don't support write and wait in a single oneshot packet.h]hPHelper for rings that don’t support write and wait in a single oneshot packet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjuubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&amdgpu_ring_soft_recovery (C function)c.amdgpu_ring_soft_recoveryhNtauh1jhjhhhNhNubj)}(hhh](j)}(hebool amdgpu_ring_soft_recovery (struct amdgpu_ring *ring, unsigned int vmid, struct dma_fence *fence)h]j)}(hdbool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, struct dma_fence *fence)h](j)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj hMubj)}(hamdgpu_ring_soft_recoveryh]j#)}(hamdgpu_ring_soft_recoveryh]hamdgpu_ring_soft_recovery}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhjhhhj hMubj>)}(hF(struct amdgpu_ring *ring, unsigned int vmid, struct dma_fence *fence)h](jD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hj;hhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhj7ubj)}(h h]h }(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hjYhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjVubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj[modnameN classnameNjj)}j]j)}jj!sbc.amdgpu_ring_soft_recoveryasbuh1hhj7ubj)}(h h]h }(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj7ubj#)}(hringh]hring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj7ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChj3ubjD)}(hunsigned int vmidh](j)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h 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a ring lockup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj|hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` ring to try the recovery on ``unsigned int vmid`` VMID we try to get going again ``struct dma_fence *fence`` timedout fence **Description** Tries to get a ring proceeding again when it is stuck.h](h)}(h**Parameters**h]jN)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj)}(hhh](j)}(h9``struct amdgpu_ring *ring`` ring to try the recovery on h](j")}(h``struct amdgpu_ring *ring``h]j()}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj>)}(hhh]h)}(hring to try the recovery onh]hring to try the recovery on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h5``unsigned int vmid`` VMID we try to get going again h](j")}(h``unsigned int vmid``h]j()}(hjh]hunsigned int vmid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj>)}(hhh]h)}(hVMID we try to get going againh]hVMID we try to get going again}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h+``struct dma_fence *fence`` timedout fence h](j")}(h``struct dma_fence *fence``h]j()}(hj2h]hstruct dma_fence *fence}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj0ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj,ubj>)}(hhh]h)}(htimedout fenceh]htimedout fence}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhMhjHubah}(h]h ]h"]h$]h&]uh1j=hj,ubeh}(h]h ]h"]h$]h&]uh1jhjGhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jN)}(hjmh]h Description}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjkubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(h6Tries to get a ring proceeding again when it is stuck.h]h6Tries to get a ring proceeding again when it is stuck.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$amdgpu_ring_test_helper (C function)c.amdgpu_ring_test_helperhNtauh1jhjhhhNhNubj)}(hhh](j)}(h6int amdgpu_ring_test_helper (struct amdgpu_ring *ring)h]j)}(h5int amdgpu_ring_test_helper(struct amdgpu_ring *ring)h](j)}(hinth]hint}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hamdgpu_ring_test_helperh]j#)}(hamdgpu_ring_test_helperh]hamdgpu_ring_test_helper}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhjhhhjhMubj>)}(h(struct amdgpu_ring *ring)h]jD)}(hstruct amdgpu_ring *ringh](jJ)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hj hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.amdgpu_ring_test_helperasbuh1hhjubj)}(h h]h }(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj#)}(hringh]hring}(hjHhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjubah}(h]h ]h"]h$]h&]j;j<uh1j=hjhhhjhMubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h)tests ring and set sched readiness statush]h)tests ring and set sched readiness status}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjohhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct amdgpu_ring *ring`` ring to try the recovery on **Description** Tests ring and set sched readiness status Returns 0 on success, error on failure.h](h)}(h**Parameters**h]jN)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM!hjubj)}(hhh]j)}(h9``struct amdgpu_ring *ring`` ring to try the recovery on h](j")}(h``struct amdgpu_ring *ring``h]j()}(hjh]hstruct amdgpu_ring *ring}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj>)}(hhh]h)}(hring to try the recovery onh]hring to try the recovery on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jN)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM!hjubh)}(h)Tests ring and set sched readiness statush]h)Tests ring and set sched readiness status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM hjubh)}(h'Returns 0 on success, error on failure.h]h'Returns 0 on success, error on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM"hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j1amdgpu_multi_ring_reset_helper_begin (C function)&c.amdgpu_multi_ring_reset_helper_beginhNtauh1jhjhhhNhNubj)}(hhh](j)}(hvoid amdgpu_multi_ring_reset_helper_begin (const u32 ring_type_mask, struct amdgpu_ring *guilty_ring, struct amdgpu_fence *guilty_fence)h]j)}(hvoid amdgpu_multi_ring_reset_helper_begin(const u32 ring_type_mask, struct amdgpu_ring *guilty_ring, struct amdgpu_fence *guilty_fence)h](j)}(hvoidh]hvoid}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>hhhjPhMubj)}(h$amdgpu_multi_ring_reset_helper_beginh]j#)}(h$amdgpu_multi_ring_reset_helper_beginh]h$amdgpu_multi_ring_reset_helper_begin}(hjchhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj_ubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhj>hhhjPhMubj>)}(h^(const u32 ring_type_mask, struct amdgpu_ring *guilty_ring, struct amdgpu_fence *guilty_fence)h](jD)}(hconst u32 ring_type_maskh](jJ)}(hconsth]hconst}(hjhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhj{ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubh)}(hhh]j#)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjesb&c.amdgpu_multi_ring_reset_helper_beginasbuh1hhj{ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj#)}(hring_type_maskh]hring_type_mask}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hj{ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjwubjD)}(hstruct amdgpu_ring *guilty_ringh](jJ)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j&c.amdgpu_multi_ring_reset_helper_beginasbuh1hhjubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj#)}(h guilty_ringh]h guilty_ring}(hj<hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjwubjD)}(h!struct amdgpu_fence *guilty_fenceh](jJ)}(hjh]hstruct}(hjUhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjQubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubh)}(hhh]j#)}(h amdgpu_fenceh]h amdgpu_fence}(hjshhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjpubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjumodnameN classnameNjj)}j]j&c.amdgpu_multi_ring_reset_helper_beginasbuh1hhjQubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj)}(hhh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjQubj#)}(h guilty_fenceh]h guilty_fence}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjQubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjwubeh}(h]h ]h"]h$]h&]j;j<uh1j=hj>hhhjPhMubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhj:hhhjPhMubah}(h]j5ah ](jjeh"]h$]h&]jj)jhuh1jhjPhMhj7hhubj)}(hhh]h)}(h#Prepare multiple rings for a reset.h]h#Prepare multiple rings for a reset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj7hhhjPhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhjhNhNubj)}(hXB**Parameters** ``const u32 ring_type_mask`` Bitmask of affected ring types ``struct amdgpu_ring *guilty_ring`` The ring which is guilty of causing a reset. ``struct amdgpu_fence *guilty_fence`` The fence which didn't signal on the guilty ring. **Description** Useful when performing a GPU reset method that affects multiple rings at the same time, such as an IP block soft reset. For example, a GFX IP block soft reset will affect every graphics and compute queue. This function should be called before such a reset. Prepare the affected rings before the reset, make sure to minimize collateral damage, and backup the contents of the rings. Then the caller can call the actual HW specific reset function. After the reset is complete, the caller should then call amdgpu_multi_ring_reset_helper_end() to restore the rings.h](h)}(h**Parameters**h]jN)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj)}(hhh](j)}(h<``const u32 ring_type_mask`` Bitmask of affected ring types h](j")}(h``const u32 ring_type_mask``h]j()}(hjh]hconst u32 ring_type_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj>)}(hhh]h)}(hBitmask of affected ring typesh]hBitmask of affected ring types}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMhj-ubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhj,hMhjubj)}(hQ``struct amdgpu_ring *guilty_ring`` The ring which is guilty of causing a reset. h](j")}(h#``struct amdgpu_ring *guilty_ring``h]j()}(hjPh]hstruct amdgpu_ring *guilty_ring}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjNubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjJubj>)}(hhh]h)}(h,The ring which is guilty of causing a reset.h]h,The ring which is guilty of causing a reset.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMhjfubah}(h]h ]h"]h$]h&]uh1j=hjJubeh}(h]h ]h"]h$]h&]uh1jhjehMhjubj)}(hX``struct amdgpu_fence *guilty_fence`` The fence which didn't signal on the guilty ring. h](j")}(h%``struct amdgpu_fence *guilty_fence``h]j()}(hjh]h!struct amdgpu_fence *guilty_fence}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubj>)}(hhh]h)}(h1The fence which didn't signal on the guilty ring.h]h3The fence which didn’t signal on the guilty ring.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j=hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]jN)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(hUseful when performing a GPU reset method that affects multiple rings at the same time, such as an IP block soft reset. For example, a GFX IP block soft reset will affect every graphics and compute queue.h]hUseful when performing a GPU reset method that affects multiple rings at the same time, such as an IP block soft reset. For example, a GFX IP block soft reset will affect every graphics and compute queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(h3This function should be called before such a reset.h]h3This function should be called before such a reset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(hPrepare the affected rings before the reset, make sure to minimize collateral damage, and backup the contents of the rings. Then the caller can call the actual HW specific reset function.h]hPrepare the affected rings before the reset, make sure to minimize collateral damage, and backup the contents of the rings. Then the caller can call the actual HW specific reset function.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubh)}(hsAfter the reset is complete, the caller should then call amdgpu_multi_ring_reset_helper_end() to restore the rings.h]hsAfter the reset is complete, the caller should then call amdgpu_multi_ring_reset_helper_end() to restore the rings.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/amdgpu_multi_ring_reset_helper_end (C function)$c.amdgpu_multi_ring_reset_helper_endhNtauh1jhjhhhNhNubj)}(hhh](j)}(hkint amdgpu_multi_ring_reset_helper_end (const u32 ring_type_mask, struct amdgpu_ring *guilty_ring, int ret)h]j)}(hjint amdgpu_multi_ring_reset_helper_end(const u32 ring_type_mask, struct amdgpu_ring *guilty_ring, int ret)h](j)}(hinth]hint}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMubj)}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhjDhMubj)}(h"amdgpu_multi_ring_reset_helper_endh]j#)}(h"amdgpu_multi_ring_reset_helper_endh]h"amdgpu_multi_ring_reset_helper_end}(hjWhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjSubah}(h]h ](j6j7eh"]h$]h&]j;j<uh1jhj2hhhjDhMubj>)}(hD(const u32 ring_type_mask, struct amdgpu_ring *guilty_ring, int ret)h](jD)}(hconst u32 ring_type_maskh](jJ)}(hjh]hconst}(hjshhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjoubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubh)}(hhh]j#)}(hu32h]hu32}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjYsb$c.amdgpu_multi_ring_reset_helper_endasbuh1hhjoubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj#)}(hring_type_maskh]hring_type_mask}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjoubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjkubjD)}(hstruct amdgpu_ring *guilty_ringh](jJ)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jVah"]h$]h&]uh1jIhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j#)}(h amdgpu_ringh]h amdgpu_ring}(hjhhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j$c.amdgpu_multi_ring_reset_helper_endasbuh1hhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hhh]h*}(hj" hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj#)}(h guilty_ringh]h guilty_ring}(hj/ hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjkubjD)}(hint reth](j)}(hinth]hint}(hjH hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjD ubj)}(h h]h }(hjV hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjD ubj#)}(hreth]hret}(hjd hhhNhNubah}(h]h ]j/ah"]h$]h&]uh1j"hjD ubeh}(h]h ]h"]h$]h&]noemphj;j<uh1jChjkubeh}(h]h ]h"]h$]h&]j;j<uh1j=hj2hhhjDhMubeh}(h]h ]h"]h$]h&]j;j<juh1jjjhj.hhhjDhMubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1jhjDhMhj+hhubj)}(hhh]h)}(h#Prepare multiple rings for a reset.h]h#Prepare multiple rings for a reset.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj+hhhjDhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhjhNhNubj)}(hX **Parameters** ``const u32 ring_type_mask`` Bitmask of affected ring types ``struct amdgpu_ring *guilty_ring`` The ring which is guilty of causing a reset. ``int ret`` Return code from the reset function. **Description** After calling amdgpu_multi_ring_reset_helper_begin() and executing the actual reset method, call this function to restore normal operation. In case the reset failed, this function should still be called to restore preemption state, but it won't attempt to fully restore the ring contents.h](h)}(h**Parameters**h]jN)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhj ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM"hj ubj)}(hhh](j)}(h<``const u32 ring_type_mask`` Bitmask of affected ring types h](j")}(h``const u32 ring_type_mask``h]j()}(hj h]hconst u32 ring_type_mask}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM hj ubj>)}(hhh]h)}(hBitmask of affected ring typesh]hBitmask of affected ring types}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM hj ubah}(h]h ]h"]h$]h&]uh1j=hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM hj ubj)}(hQ``struct amdgpu_ring *guilty_ring`` The ring which is guilty of causing a reset. h](j")}(h#``struct amdgpu_ring *guilty_ring``h]j()}(hj!h]hstruct amdgpu_ring *guilty_ring}(hj !hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj!ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM!hj!ubj>)}(hhh]h)}(h,The ring which is guilty of causing a reset.h]h,The ring which is guilty of causing a reset.}(hj!!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM!hj!ubah}(h]h ]h"]h$]h&]uh1j=hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hM!hj ubj)}(h1``int ret`` Return code from the reset function. h](j")}(h ``int ret``h]j()}(hjA!h]hint ret}(hjC!hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj?!ubah}(h]h ]h"]h$]h&]uh1j!ho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM"hj;!ubj>)}(hhh]h)}(h$Return code from the reset function.h]h$Return code from the reset function.}(hjZ!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV!hM"hjW!ubah}(h]h ]h"]h$]h&]uh1j=hj;!ubeh}(h]h ]h"]h$]h&]uh1jhjV!hM"hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]jN)}(hj|!h]h Description}(hj~!hhhNhNubah}(h]h ]h"]h$]h&]uh1jMhjz!ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM$hj ubh)}(hAfter calling amdgpu_multi_ring_reset_helper_begin() and executing the actual reset method, call this function to restore normal operation.h]hAfter calling amdgpu_multi_ring_reset_helper_begin() and executing the actual reset method, call this function to restore normal operation.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM#hj ubh)}(hIn case the reset failed, this function should still be called to restore preemption state, but it won't attempt to fully restore the ring contents.h]hIn case the reset failed, this function should still be called to restore preemption state, but it won’t attempt to fully restore the ring contents.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/ring-buffer:93: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ring.chM'hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h]ring-operationsah ]h"]ring operationsah$]h&]uh1hhhhhhhhK[ubeh}(h] ring-bufferah ]h"] ring bufferah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj!error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehʌ _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j!j!jjj!j!u nametypes}(j!jj!uh}(j!hjjj!jjjjvj{jjjjj j jk jp j j jjjljqjjjjj5j:j)j.u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.