€•|5Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ'/translations/zh_CN/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/zh_TW/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/it_IT/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ja_JP/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ko_KR/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/pt_BR/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/sp_SP/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒtarget”“”)”}”(hŒ.. _amdgpu-gc:”h]”h}”(h]”h ]”h"]”h$]”h&]”Œrefid”Œ amdgpu-gc”uh1hµh´Khhh²hh³ŒA/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/gc/index.rst”ubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ&drm/amdgpu - Graphics and Compute (GC)”h]”hŒ&drm/amdgpu - Graphics and Compute (GC)”…””}”(hhËh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhhÆh²hh³hÃh´KubhŒ paragraph”“”)”}”(hXpThe relationship between the CPU and GPU can be described as the producer-consumer problem, where the CPU fills out a buffer with operations (producer) to be executed by the GPU (consumer). The requested operations in the buffer are called **Command Packets**, which can be summarized as a compressed way of transmitting command information to the graphics controller.”h]”(hŒðThe relationship between the CPU and GPU can be described as the producer-consumer problem, where the CPU fills out a buffer with operations (producer) to be executed by the GPU (consumer). The requested operations in the buffer are called ”…””}”(hhÛh²hh³Nh´NubhŒstrong”“”)”}”(hŒ**Command Packets**”h]”hŒCommand Packets”…””}”(hhåh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhhÛubhŒm, which can be summarized as a compressed way of transmitting command information to the graphics controller.”…””}”(hhÛh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÙh³hÃh´KhhÆh²hubhÚ)”}”(hXThe component that acts as the front end between the CPU and the GPU is called **Command Processor (CP)**. This component is responsible for providing greater flexibility to the **Graphics and Compute (GC)** since CP makes it possible to program various aspects of the GPU pipeline. CP also coordinates the communication between the CPU and GPU via a mechanism named **Ring Buffers**, where the CPU appends information to the buffer while the GPU removes operations. CP is also responsible for handling **Indirect Buffers (IB)**.”h]”(hŒOThe component that acts as the front end between the CPU and the GPU is called ”…””}”(hhýh²hh³Nh´Nubhä)”}”(hŒ**Command Processor (CP)**”h]”hŒCommand Processor (CP)”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhhýubhŒI. This component is responsible for providing greater flexibility to the ”…””}”(hhýh²hh³Nh´Nubhä)”}”(hŒ**Graphics and Compute (GC)**”h]”hŒGraphics and Compute (GC)”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhhýubhŒ  since CP makes it possible to program various aspects of the GPU pipeline. CP also coordinates the communication between the CPU and GPU via a mechanism named ”…””}”(hhýh²hh³Nh´Nubhä)”}”(hŒ**Ring Buffers**”h]”hŒ Ring Buffers”…””}”(hj)h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhhýubhŒx, where the CPU appends information to the buffer while the GPU removes operations. CP is also responsible for handling ”…””}”(hhýh²hh³Nh´Nubhä)”}”(hŒ**Indirect Buffers (IB)**”h]”hŒIndirect Buffers (IB)”…””}”(hj;h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhhýubhŒ.”…””}”(hhýh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÙh³hÃh´K hhÆh²hubhÚ)”}”(hX#For reference, internally the CP consists of several sub-blocks (CPC - CP compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms appear in register names, but this is more of an implementation detail and not something that directly impacts driver programming or debugging.”h]”hX#For reference, internally the CP consists of several sub-blocks (CPC - CP compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms appear in register names, but this is more of an implementation detail and not something that directly impacts driver programming or debugging.”…””}”(hjSh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÙh³hÃh´KhhÆh²hubhÅ)”}”(hhh]”(hÊ)”}”(hŒ+Graphics (GFX) and Compute Microcontrollers”h]”hŒ+Graphics (GFX) and Compute Microcontrollers”…””}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhjah²hh³hÃh´KubhÚ)”}”(hŒdGC is a large block, and as a result, it has multiple firmware associated with it. Some of them are:”h]”hŒdGC is a large block, and as a result, it has multiple firmware associated with it. Some of them are:”…””}”(hjrh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÙh³hÃh´Khjah²hubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hX>CP (Command Processor) The name for the hardware block that encompasses the front end of the GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers provides the driver interface to interact with the GFX/Compute engine. MEC (MicroEngine Compute) This is the microcontroller that controls the compute queues on the GFX/compute engine. MES (MicroEngine Scheduler) This is the engine for managing queues. For more details check :ref:`MicroEngine Scheduler (MES) `. ”h]”(hŒterm”“”)”}”(hŒCP (Command Processor)”h]”hŒCP (Command Processor)”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³hÃh´K,hj‡ubhŒ definition”“”)”}”(hhh]”(hÚ)”}”(hXThe name for the hardware block that encompasses the front end of the GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers provides the driver interface to interact with the GFX/Compute engine.”h]”hXThe name for the hardware block that encompasses the front end of the GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers provides the driver interface to interact with the GFX/Compute engine.”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÙh³hÃh´K!hjubj)”}”(hhh]”(j†)”}”(hŒrMEC (MicroEngine Compute) This is the microcontroller that controls the compute queues on the GFX/compute engine. ”h]”(jŒ)”}”(hŒMEC (MicroEngine Compute)”h]”hŒMEC (MicroEngine Compute)”…””}”(hjµh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³hÃh´K(hj±ubjœ)”}”(hhh]”hÚ)”}”(hŒWThis is the microcontroller that controls the compute queues on the GFX/compute engine.”h]”hŒWThis is the microcontroller that controls the compute queues on the GFX/compute engine.”…””}”(hjÆh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÙh³hÃh´K'hjÃubah}”(h]”h ]”h"]”h$]”h&]”uh1j›hj±ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³hÃh´K(hj®ubj†)”}”(hŒŒMES (MicroEngine Scheduler) This is the engine for managing queues. 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