€•52Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ'/translations/zh_CN/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/zh_TW/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/it_IT/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ja_JP/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ko_KR/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/sp_SP/gpu/amdgpu/gc/index”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒtarget”“”)”}”(hŒ.. _amdgpu-gc:”h]”h}”(h]”h ]”h"]”h$]”h&]”Œrefid”Œ amdgpu-gc”uh1h¡h KhhhžhhŸŒA/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/gc/index.rst”ubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ&drm/amdgpu - Graphics and Compute (GC)”h]”hŒ&drm/amdgpu - Graphics and Compute (GC)”…””}”(hh·hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hµhh²hžhhŸh¯h KubhŒ paragraph”“”)”}”(hXlThe relationship between the CPU and GPU can be described as the producer-consumer problem, where the CPU fills out a buffer with operations (producer) to be executed by the GPU (consumer). The requested operations in the buffer are called Command Packets, which can be summarized as a compressed way of transmitting command information to the graphics controller.”h]”hXlThe relationship between the CPU and GPU can be described as the producer-consumer problem, where the CPU fills out a buffer with operations (producer) to be executed by the GPU (consumer). The requested operations in the buffer are called Command Packets, which can be summarized as a compressed way of transmitting command information to the graphics controller.”…””}”(hhÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h Khh²hžhubhÆ)”}”(hXøThe component that acts as the front end between the CPU and the GPU is called the Command Processor (CP). This component is responsible for providing greater flexibility to the GC since CP makes it possible to program various aspects of the GPU pipeline. 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CP also coordinates the communication between the CPU and GPU via a mechanism named ”…””}”(hhÕhžhhŸNh NubhŒstrong”“”)”}”(hŒ**Ring Buffers**”h]”hŒ Ring Buffers”…””}”(hhßhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhhÕubhX, where the CPU appends information to the buffer while the GPU removes operations. It is relevant to highlight that a CPU can add a pointer to the Ring Buffer that points to another region of memory outside the Ring Buffer, and CP can handle it; this mechanism is called ”…””}”(hhÕhžhhŸNh NubhÞ)”}”(hŒ**Indirect Buffer (IB)**”h]”hŒIndirect Buffer (IB)”…””}”(hhñhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhhÕubhŒl. CP receives and parses the Command Streams (CS), and writes the operations to the correct hardware blocks.”…””}”(hhÕhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K hh²hžhubh±)”}”(hhh]”(h¶)”}”(hŒ+Graphics (GFX) and Compute Microcontrollers”h]”hŒ+Graphics (GFX) and Compute Microcontrollers”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hµhj hžhhŸh¯h KubhÆ)”}”(hŒdGC is a large block, and as a result, it has multiple firmware associated with it. Some of them are:”h]”hŒdGC is a large block, and as a result, it has multiple firmware associated with it. Some of them are:”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h Khj hžhubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hX>CP (Command Processor) The name for the hardware block that encompasses the front end of the GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers provides the driver interface to interact with the GFX/Compute engine. MEC (MicroEngine Compute) This is the microcontroller that controls the compute queues on the GFX/compute engine. MES (MicroEngine Scheduler) This is the engine for managing queues. For more details check :ref:`MicroEngine Scheduler (MES) `. ”h]”(hŒterm”“”)”}”(hŒCP (Command Processor)”h]”hŒCP (Command Processor)”…””}”(hj5hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3hŸh¯h K*hj/ubhŒ definition”“”)”}”(hhh]”(hÆ)”}”(hXThe name for the hardware block that encompasses the front end of the GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers provides the driver interface to interact with the GFX/Compute engine.”h]”hXThe name for the hardware block that encompasses the front end of the GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers provides the driver interface to interact with the GFX/Compute engine.”…””}”(hjHhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KhjEubj))”}”(hhh]”(j.)”}”(hŒrMEC (MicroEngine Compute) This is the microcontroller that controls the compute queues on the GFX/compute engine. ”h]”(j4)”}”(hŒMEC (MicroEngine Compute)”h]”hŒMEC (MicroEngine Compute)”…””}”(hj]hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3hŸh¯h K&hjYubjD)”}”(hhh]”hÆ)”}”(hŒWThis is the microcontroller that controls the compute queues on the GFX/compute engine.”h]”hŒWThis is the microcontroller that controls the compute queues on the GFX/compute engine.”…””}”(hjnhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K%hjkubah}”(h]”h ]”h"]”h$]”h&]”uh1jChjYubeh}”(h]”h ]”h"]”h$]”h&]”uh1j-hŸh¯h K&hjVubj.)”}”(hŒŒMES (MicroEngine Scheduler) This is the engine for managing queues. For more details check :ref:`MicroEngine Scheduler (MES) `. ”h]”(j4)”}”(hŒMES (MicroEngine Scheduler)”h]”hŒMES (MicroEngine Scheduler)”…””}”(hjŒhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3hŸh¯h K*hjˆubjD)”}”(hhh]”hÆ)”}”(hŒoThis is the engine for managing queues. For more details check :ref:`MicroEngine Scheduler (MES) `.”h]”(hŒ?This is the engine for managing queues. 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