4sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget3/translations/zh_CN/gpu/amdgpu/display/mpo-overviewmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/zh_TW/gpu/amdgpu/display/mpo-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/it_IT/gpu/amdgpu/display/mpo-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ja_JP/gpu/amdgpu/display/mpo-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ko_KR/gpu/amdgpu/display/mpo-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/pt_BR/gpu/amdgpu/display/mpo-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/sp_SP/gpu/amdgpu/display/mpo-overviewmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hMultiplane Overlay (MPO)h]hMultiplane Overlay (MPO)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhM/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/mpo-overview.rsthKubhnote)}(hrYou will get more from this page if you have already read the 'Documentation/gpu/amdgpu/display/dcn-overview.rst'.h]h paragraph)}(hrYou will get more from this page if you have already read the 'Documentation/gpu/amdgpu/display/dcn-overview.rst'.h]hvYou will get more from this page if you have already read the ‘Documentation/gpu/amdgpu/display/dcn-overview.rst’.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hX`Multiplane Overlay (MPO) allows for multiple framebuffers to be composited via fixed-function hardware in the display controller rather than using graphics or compute shaders for composition. This can yield some power savings if it means the graphics/compute pipelines can be put into low-power states. In summary, MPO can bring the following benefits:h]hX`Multiplane Overlay (MPO) allows for multiple framebuffers to be composited via fixed-function hardware in the display controller rather than using graphics or compute shaders for composition. This can yield some power savings if it means the graphics/compute pipelines can be put into low-power states. In summary, MPO can bring the following benefits:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh bullet_list)}(hhh](h list_item)}(hqDecreased GPU and CPU workload - no composition shaders needed, no extra buffer copy needed, GPU can remain idle.h]h)}(hqDecreased GPU and CPU workload - no composition shaders needed, no extra buffer copy needed, GPU can remain idle.h]hqDecreased GPU and CPU workload - no composition shaders needed, no extra buffer copy needed, GPU can remain idle.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hPlane independent page flips - No need to be tied to global compositor page-flip present rate, reduced latency, independent timing. h]h)}(hPlane independent page flips - No need to be tied to global compositor page-flip present rate, reduced latency, independent timing.h]hPlane independent page flips - No need to be tied to global compositor page-flip present rate, reduced latency, independent timing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1hhhhKhhhhubh)}(hKeep in mind that MPO is all about power-saving; if you want to learn more about power-save in the display context, check the link: `Power `__.h]h)}(hKeep in mind that MPO is all about power-saving; if you want to learn more about power-save in the display context, check the link: `Power `__.h](hKeep in mind that MPO is all about power-saving; if you want to learn more about power-save in the display context, check the link: }(hj8hhhNhNubh reference)}(hU`Power `__h]hPower}(hjBhhhNhNubah}(h]h ]h"]h$]h&]namePowerrefuriIhttps://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rstuh1j@hj8ubh.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj4ubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hXMultiplane Overlay is only available using the DRM atomic model. The atomic model only uses a single userspace IOCTL for configuring the display hardware (modesetting, page-flipping, etc) - drmModeAtomicCommit. To query hardware resources and limitations userspace also calls into drmModeGetResources which reports back the number of planes, CRTCs, and connectors. There are three types of DRM planes that the driver can register and work with:h]hXMultiplane Overlay is only available using the DRM atomic model. The atomic model only uses a single userspace IOCTL for configuring the display hardware (modesetting, page-flipping, etc) - drmModeAtomicCommit. To query hardware resources and limitations userspace also calls into drmModeGetResources which reports back the number of planes, CRTCs, and connectors. There are three types of DRM planes that the driver can register and work with:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(h``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a CRTC, primary planes are the planes operated upon by CRTC modesetting and flipping operations.h]h)}(h``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a CRTC, primary planes are the planes operated upon by CRTC modesetting and flipping operations.h](hliteral)}(h``DRM_PLANE_TYPE_PRIMARY``h]hDRM_PLANE_TYPE_PRIMARY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjyubh: Primary planes represent a “main” plane for a CRTC, primary planes are the planes operated upon by CRTC modesetting and flipping operations.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjuubah}(h]h ]h"]h$]h&]uh1hhjrhhhhhNubh)}(h``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a CRTC. Cursor planes are the planes operated upon by the cursor IOCTLsh]h)}(h``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a CRTC. Cursor planes are the planes operated upon by the cursor IOCTLsh](j~)}(h``DRM_PLANE_TYPE_CURSOR``h]hDRM_PLANE_TYPE_CURSOR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubhz: Cursor planes represent a “cursor” plane for a CRTC. Cursor planes are the planes operated upon by the cursor IOCTLs}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1hhjrhhhhhNubh)}(h``DRM_PLANE_TYPE_OVERLAY``: Overlay planes represent all non-primary, non-cursor planes. Some drivers refer to these types of planes as "sprites" internally. h]h)}(h``DRM_PLANE_TYPE_OVERLAY``: Overlay planes represent all non-primary, non-cursor planes. Some drivers refer to these types of planes as "sprites" internally.h](j~)}(h``DRM_PLANE_TYPE_OVERLAY``h]hDRM_PLANE_TYPE_OVERLAY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh: Overlay planes represent all non-primary, non-cursor planes. Some drivers refer to these types of planes as “sprites” internally.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK$hjubah}(h]h ]h"]h$]h&]uh1hhjrhhhhhNubeh}(h]h ]h"]h$]h&]j2j3uh1hhhhKhhhhubh)}(hiTo illustrate how it works, let's take a look at a device that exposes the following planes to userspace:h]hkTo illustrate how it works, let’s take a look at a device that exposes the following planes to userspace:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hhhhubh)}(hhh](h)}(h4 Primary planes (1 per CRTC).h]h)}(hjh]h4 Primary planes (1 per CRTC).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h4 Cursor planes (1 per CRTC).h]h)}(hjh]h4 Cursor planes (1 per CRTC).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h&1 Overlay plane (shared among CRTCs). h]h)}(h%1 Overlay plane (shared among CRTCs).h]h%1 Overlay plane (shared among CRTCs).}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hj.ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j2j3uh1hhhhK+hhhhubh)}(hGKeep in mind that different ASICs might expose other numbers of planes.h]h)}(hGKeep in mind that different ASICs might expose other numbers of planes.h]hGKeep in mind that different ASICs might expose other numbers of planes.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjLubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hX/For this hardware example, we have 4 pipes (if you don't know what AMD pipe means, look at 'Documentation/gpu/amdgpu/display/dcn-overview.rst', section "AMD Hardware Pipeline"). Typically most AMD devices operate in a pipe-split configuration for optimal single display output (e.g., 2 pipes per plane).h]hX9For this hardware example, we have 4 pipes (if you don’t know what AMD pipe means, look at ‘Documentation/gpu/amdgpu/display/dcn-overview.rst’, section “AMD Hardware Pipeline”). Typically most AMD devices operate in a pipe-split configuration for optimal single display output (e.g., 2 pipes per plane).}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hhhhubh)}(h~A typical MPO configuration from userspace - 1 primary + 1 overlay on a single display - will see 4 pipes in use, 2 per plane.h]h~A typical MPO configuration from userspace - 1 primary + 1 overlay on a single display - will see 4 pipes in use, 2 per plane.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hhhhubh)}(hXAt least 1 pipe must be used per plane (primary and overlay), so for this hypothetical hardware that we are using as an example, we have an absolute limit of 4 planes across all CRTCs. Atomic commits will be rejected for display configurations using more than 4 planes. Again, it is important to stress that every DCN has different restrictions; here, we are just trying to provide the concept idea.h]hXAt least 1 pipe must be used per plane (primary and overlay), so for this hypothetical hardware that we are using as an example, we have an absolute limit of 4 planes across all CRTCs. Atomic commits will be rejected for display configurations using more than 4 planes. Again, it is important to stress that every DCN has different restrictions; here, we are just trying to provide the concept idea.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hhhhubh)}(hhh](h)}(hPlane Restrictionsh]hPlane Restrictions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKBubh)}(hCAMDGPU imposes restrictions on the use of DRM planes in the driver.h]hCAMDGPU imposes restrictions on the use of DRM planes in the driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjhhubh)}(hSAtomic commits will be rejected for commits which do not follow these restrictions:h]hSAtomic commits will be rejected for commits which do not follow these restrictions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhjhhubh)}(hhh](h)}(h5Overlay planes must be in ARGB8888 or XRGB8888 formath]h)}(hjh]h5Overlay planes must be in ARGB8888 or XRGB8888 format}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hAPlanes cannot be placed outside of the CRTC destination rectangleh]h)}(hjh]hAPlanes cannot be placed outside of the CRTC destination rectangle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hAPlanes cannot be downscaled more than 1/4x of their original sizeh]h)}(hjh]hAPlanes cannot be downscaled more than 1/4x of their original size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h?Planes cannot be upscaled more than 16x of their original size h]h)}(h>Planes cannot be upscaled more than 16x of their original sizeh]h>Planes cannot be upscaled more than 16x of their original size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j2j3uh1hhhhKIhjhhubh)}(h/Not every property is available on every plane:h]h/Not every property is available on every plane:}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjhhubh)}(hhh](h)}(h?Only primary planes have color-space and non-RGB format supporth]h)}(hj4h]h?Only primary planes have color-space and non-RGB format support}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhj2ubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhNubh)}(h0Only overlay planes have alpha blending support h]h)}(h/Only overlay planes have alpha blending supporth]h/Only overlay planes have alpha blending support}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjIubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhNubeh}(h]h ]h"]h$]h&]j2j3uh1hhhhKPhjhhubeh}(h]plane-restrictionsah ]h"]plane restrictionsah$]h&]uh1hhhhhhhhKBubh)}(hhh](h)}(hCursor Restrictionsh]hCursor Restrictions}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohhhhhKTubh)}(hYBefore we start to describe some restrictions around cursor and MPO, see the below image:h]hYBefore we start to describe some restrictions around cursor and MPO, see the below image:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjohhubkfigure kernel_figure)}(hhh]hfigure)}(hhh]himage)}(h".. kernel-figure:: mpo-cursor.svg h]h}(h]h ]h"]h$]h&]uri!gpu/amdgpu/display/mpo-cursor.svg candidates}j3jsuh1jhjhhhKubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjohhhhhKZubh)}(hXwThe image on the left side represents how DRM expects the cursor and planes to be blended. However, AMD hardware handles cursors differently, as you can see on the right side; basically, our cursor cannot be drawn outside its associated plane as it is being treated as part of the plane. Another consequence of that is that cursors inherit the color and scale from the plane.h]hXwThe image on the left side represents how DRM expects the cursor and planes to be blended. However, AMD hardware handles cursors differently, as you can see on the right side; basically, our cursor cannot be drawn outside its associated plane as it is being treated as part of the plane. Another consequence of that is that cursors inherit the color and scale from the plane.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjohhubh)}(hAs a result of the above behavior, do not use legacy API to set up the cursor plane when working with MPO; otherwise, you might encounter unexpected behavior.h]hAs a result of the above behavior, do not use legacy API to set up the cursor plane when working with MPO; otherwise, you might encounter unexpected behavior.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjohhubh)}(hIn short, AMD HW has no dedicated cursor planes. A cursor is attached to another plane and therefore inherits any scaling or color processing from its parent plane.h]hIn short, AMD HW has no dedicated cursor planes. A cursor is attached to another plane and therefore inherits any scaling or color processing from its parent plane.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjohhubeh}(h]cursor-restrictionsah ]h"]cursor restrictionsah$]h&]uh1hhhhhhhhKTubh)}(hhh](h)}(h Use Casesh]h Use Cases}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKjubh)}(hhh](h)}(h5Picture-in-Picture (PIP) playback - Underlay strategyh]h5Picture-in-Picture (PIP) playback - Underlay strategy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKmubh)}(hsVideo playback should be done using the "primary plane as underlay" MPO strategy. This is a 2 planes configuration:h]hwVideo playback should be done using the “primary plane as underlay” MPO strategy. This is a 2 planes configuration:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjhhubh)}(hhh](h)}(h)1 YUV DRM Primary Plane (e.g. NV12 Video)h]h)}(hjh]h)1 YUV DRM Primary Plane (e.g. NV12 Video)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hX1 RGBA DRM Overlay Plane (e.g. ARGB8888 desktop). The compositor should prepare the framebuffers for the planes as follows: - The overlay plane contains general desktop UI, video player controls, and video subtitles - Primary plane contains one or more videos h]h)}(hX1 RGBA DRM Overlay Plane (e.g. ARGB8888 desktop). The compositor should prepare the framebuffers for the planes as follows: - The overlay plane contains general desktop UI, video player controls, and video subtitles - Primary plane contains one or more videosh]hX1 RGBA DRM Overlay Plane (e.g. ARGB8888 desktop). The compositor should prepare the framebuffers for the planes as follows: - The overlay plane contains general desktop UI, video player controls, and video subtitles - Primary plane contains one or more videos}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshj1ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j2j3uh1hhhhKrhjhhubh)}(hKeep in mind that we could extend this configuration to more planes, but that is currently not supported by our driver yet (maybe if we have a userspace request in the future, we can change that).h]h)}(hKeep in mind that we could extend this configuration to more planes, but that is currently not supported by our driver yet (maybe if we have a userspace request in the future, we can change that).h]hKeep in mind that we could extend this configuration to more planes, but that is currently not supported by our driver yet (maybe if we have a userspace request in the future, we can change that).}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjOubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h!See below a single-video example:h]h!See below a single-video example:}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjhhubj)}(hhh]j)}(hhh]j)}(h*.. kernel-figure:: single-display-mpo.svg h]h}(h]h ]h"]h$]h&]uri)gpu/amdgpu/display/single-display-mpo.svgj}j3jsuh1jhjxhhhKubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubh)}(h`We could extend this behavior to more planes, but that is currently not supported by our driver.h]h)}(h`We could extend this behavior to more planes, but that is currently not supported by our driver.h]h`We could extend this behavior to more planes, but that is currently not supported by our driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hX"The video buffer should be used directly for the primary plane. The video can be scaled and positioned for the desktop using the properties: CRTC_X, CRTC_Y, CRTC_W, and CRTC_H. The primary plane should also have the color encoding and color range properties set based on the source content:h]hX"The video buffer should be used directly for the primary plane. The video can be scaled and positioned for the desktop using the properties: CRTC_X, CRTC_Y, CRTC_W, and CRTC_H. The primary plane should also have the color encoding and color range properties set based on the source content:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh]h)}(h$``COLOR_RANGE``, ``COLOR_ENCODING`` h]h)}(h#``COLOR_RANGE``, ``COLOR_ENCODING``h](j~)}(h``COLOR_RANGE``h]h COLOR_RANGE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh, }(hjhhhNhNubj~)}(h``COLOR_ENCODING``h]hCOLOR_ENCODING}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubah}(h]h ]h"]h$]h&]j2j3uh1hhhhKhjhhubh)}(hXyThe overlay plane should be the native size of the CRTC. The compositor must draw a transparent cutout for where the video should be placed on the desktop (i.e., set the alpha to zero). The primary plane video will be visible through the underlay. The overlay plane's buffer may remain static while the primary plane's framebuffer is used for standard double-buffered playback.h]hX}The overlay plane should be the native size of the CRTC. The compositor must draw a transparent cutout for where the video should be placed on the desktop (i.e., set the alpha to zero). The primary plane video will be visible through the underlay. The overlay plane’s buffer may remain static while the primary plane’s framebuffer is used for standard double-buffered playback.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXThe compositor should create a YUV buffer matching the native size of the CRTC. Each video buffer should be composited onto this YUV buffer for direct YUV scanout. The primary plane should have the color encoding and color range properties set based on the source content: ``COLOR_RANGE``, ``COLOR_ENCODING``. However, be mindful that the source color space and encoding match for each video since it affect the entire plane.h](hXThe compositor should create a YUV buffer matching the native size of the CRTC. Each video buffer should be composited onto this YUV buffer for direct YUV scanout. The primary plane should have the color encoding and color range properties set based on the source content: }(hjhhhNhNubj~)}(h``COLOR_RANGE``h]h COLOR_RANGE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh, }(hjhhhNhNubj~)}(h``COLOR_ENCODING``h]hCOLOR_ENCODING}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubhu. However, be mindful that the source color space and encoding match for each video since it affect the entire plane.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXxThe overlay plane should be the native size of the CRTC. The compositor must draw a transparent cutout for where each video should be placed on the desktop (i.e., set the alpha to zero). The primary plane videos will be visible through the underlay. The overlay plane's buffer may remain static while compositing operations for video playback will be done on the video buffer.h]hXzThe overlay plane should be the native size of the CRTC. The compositor must draw a transparent cutout for where each video should be placed on the desktop (i.e., set the alpha to zero). The primary plane videos will be visible through the underlay. The overlay plane’s buffer may remain static while compositing operations for video playback will be done on the video buffer.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThis kernel interface is validated using IGT GPU Tools. The following tests can be run to validate positioning, blending, scaling under a variety of sequences and interactions with operations such as DPMS and S3:h]hThis kernel interface is validated using IGT GPU Tools. The following tests can be run to validate positioning, blending, scaling under a variety of sequences and interactions with operations such as DPMS and S3:}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(h6``kms_plane@plane-panning-bottom-right-pipe-*-planes``h]h)}(hjXh]j~)}(hjXh]h2kms_plane@plane-panning-bottom-right-pipe-*-planes}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjZubah}(h]h ]h"]h$]h&]uh1hhhhKhjVubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h8``kms_plane@plane-panning-bottom-right-suspend-pipe-*-``h]h)}(hjxh]j~)}(hjxh]h4kms_plane@plane-panning-bottom-right-suspend-pipe-*-}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjzubah}(h]h ]h"]h$]h&]uh1hhhhKhjvubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h,``kms_plane@plane-panning-top-left-pipe-*-``h]h)}(hjh]j~)}(hjh]h(kms_plane@plane-panning-top-left-pipe-*-}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h,``kms_plane@plane-position-covered-pipe-*-``h]h)}(hjh]j~)}(hjh]h(kms_plane@plane-position-covered-pipe-*-}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h.``kms_plane@plane-position-hole-dpms-pipe-*-``h]h)}(hjh]j~)}(hjh]h*kms_plane@plane-position-hole-dpms-pipe-*-}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h)``kms_plane@plane-position-hole-pipe-*-``h]h)}(hjh]j~)}(hjh]h%kms_plane@plane-position-hole-pipe-*-}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h,``kms_plane_multiple@atomic-pipe-*-tiling-``h]h)}(hjh]j~)}(hjh]h(kms_plane_multiple@atomic-pipe-*-tiling-}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h*``kms_plane_scaling@pipe-*-plane-scaling``h]h)}(hj8h]j~)}(hj8h]h&kms_plane_scaling@pipe-*-plane-scaling}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj:ubah}(h]h ]h"]h$]h&]uh1hhhhKhj6ubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h,``kms_plane_alpha_blend@pipe-*-alpha-basic``h]h)}(hjXh]j~)}(hjXh]h(kms_plane_alpha_blend@pipe-*-alpha-basic}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjZubah}(h]h ]h"]h$]h&]uh1hhhhKhjVubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h5``kms_plane_alpha_blend@pipe-*-alpha-transparant-fb``h]h)}(hjxh]j~)}(hjxh]h1kms_plane_alpha_blend@pipe-*-alpha-transparant-fb}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjzubah}(h]h ]h"]h$]h&]uh1hhhhKhjvubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h0``kms_plane_alpha_blend@pipe-*-alpha-opaque-fb``h]h)}(hjh]j~)}(hjh]h,kms_plane_alpha_blend@pipe-*-alpha-opaque-fb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h3``kms_plane_alpha_blend@pipe-*-constant-alpha-min``h]h)}(hjh]j~)}(hjh]h/kms_plane_alpha_blend@pipe-*-constant-alpha-min}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h3``kms_plane_alpha_blend@pipe-*-constant-alpha-mid``h]h)}(hjh]j~)}(hjh]h/kms_plane_alpha_blend@pipe-*-constant-alpha-mid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h4``kms_plane_alpha_blend@pipe-*-constant-alpha-max`` h]h)}(h3``kms_plane_alpha_blend@pipe-*-constant-alpha-max``h]j~)}(hjh]h/kms_plane_alpha_blend@pipe-*-constant-alpha-max}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubeh}(h]h ]h"]h$]h&]j2-uh1hhhhKhjhhubeh}(h]1picture-in-picture-pip-playback-underlay-strategyah ]h"]5picture-in-picture (pip) playback - underlay strategyah$]h&]uh1hhjhhhhhKmubh)}(hhh](h)}(hMultiple Display MPOh]hMultiple Display MPO}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhKubh)}(hXJAMDGPU supports display MPO when using multiple displays; however, this feature behavior heavily relies on the compositor implementation. Keep in mind that userspace can define different policies. For example, some OSes can use MPO to protect the plane that handles the video playback; notice that we don't have many limitations for a single display. Nonetheless, this manipulation can have many more restrictions for a multi-display scenario. The below example shows a video playback in the middle of two displays, and it is up to the compositor to define a policy on how to handle it:h]hXLAMDGPU supports display MPO when using multiple displays; however, this feature behavior heavily relies on the compositor implementation. Keep in mind that userspace can define different policies. For example, some OSes can use MPO to protect the plane that handles the video playback; notice that we don’t have many limitations for a single display. Nonetheless, this manipulation can have many more restrictions for a multi-display scenario. The below example shows a video playback in the middle of two displays, and it is up to the compositor to define a policy on how to handle it:}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj&hhubj)}(hhh]j)}(hhh]j)}(h... kernel-figure:: multi-display-hdcp-mpo.svg h]h}(h]h ]h"]h$]h&]uri-gpu/amdgpu/display/multi-display-hdcp-mpo.svgj}j3jVsuh1jhjHhhhKubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhj&hhhhhKubh)}(h`Let's discuss some of the hardware limitations we have when dealing with multi-display with MPO.h]hbLet’s discuss some of the hardware limitations we have when dealing with multi-display with MPO.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj&hhubh)}(hhh](h)}(h Limitationsh]h Limitations}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhhhhhKubh)}(hFor simplicity's sake, for discussing the hardware limitation, this documentation supposes an example where we have two displays and video playback that will be moved around different displays.h]hFor simplicity’s sake, for discussing the hardware limitation, this documentation supposes an example where we have two displays and video playback that will be moved around different displays.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubh)}(hhh]h)}(h**Hardware limitations** h]h)}(h**Hardware limitations**h]hstrong)}(hjh]hHardware limitations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubah}(h]h ]h"]h$]h&]j2j3uh1hhhhKhjrhhubh)}(hFrom the DCN overview page, each display requires at least one pipe and each MPO plane needs another pipe. As a result, when the video is in the middle of the two displays, we need to use 2 pipes. See the example below where we avoid pipe split:h]hFrom the DCN overview page, each display requires at least one pipe and each MPO plane needs another pipe. As a result, when the video is in the middle of the two displays, we need to use 2 pipes. See the example below where we avoid pipe split:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubh)}(hhh](h)}(h81 display (1 pipe) + MPO (1 pipe), we will use two pipesh]h)}(hjh]h81 display (1 pipe) + MPO (1 pipe), we will use two pipes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hn2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the middle of both displays needs 2 pipes.h]h)}(hn2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the middle of both displays needs 2 pipes.h]hn2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the middle of both displays needs 2 pipes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h93 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes. h]h)}(h83 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.h]h83 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j2juh1hhhhKhjrhhubh)}(hIf we use MPO with multiple displays, the userspace has to decide to enable multiple MPO by the price of limiting the number of external displays supported or disable it in favor of multiple displays; it is a policy decision. For example:h]hIf we use MPO with multiple displays, the userspace has to decide to enable multiple MPO by the price of limiting the number of external displays supported or disable it in favor of multiple displays; it is a policy decision. For example:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubh)}(hhh](h)}(hGWhen ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPOh]h)}(hj.h]hGWhen ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj,ubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhNubh)}(hHWhen ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO h]h)}(hGWhen ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPOh]hGWhen ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhNubeh}(h]h ]h"]h$]h&]j2j3uh1hhhhKhjrhhubh)}(hLet's briefly explore how userspace can handle these two display configurations on an ASIC that only supports three pipes. We can have:h]hLet’s briefly explore how userspace can handle these two display configurations on an ASIC that only supports three pipes. We can have:}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubj)}(hhh]j)}(hhh]j)}(h;.. kernel-figure:: multi-display-hdcp-mpo-less-pipe-ex.svg h]h}(h]h ]h"]h$]h&]uri:gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svgj}j3jsuh1jhjrhhhKubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jhjrhhhhhKubh)}(hhh](h)}(hTotal pipes are 3h]h)}(hjh]hTotal pipes are 3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h5User lights up 2 displays (2 out of 3 pipes are used)h]h)}(hjh]h5User lights up 2 displays (2 out of 3 pipes are used)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h)User launches video (1 pipe used for MPO)h]h)}(hjh]h)User launches video (1 pipe used for MPO)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hNow, if the user moves the video in the middle of 2 displays, one part of the video won't be MPO since we have used 3/3 pipes. h]h)}(h~Now, if the user moves the video in the middle of 2 displays, one part of the video won't be MPO since we have used 3/3 pipes.h]hNow, if the user moves the video in the middle of 2 displays, one part of the video won’t be MPO since we have used 3/3 pipes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j2juh1hhhhKhjrhhubh)}(hhh]h)}(h**Scaling limitation** h]h)}(h**Scaling limitation**h]j)}(hjh]hScaling limitation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubah}(h]h ]h"]h$]h&]j2j3uh1hhhhKhjrhhubh)}(hHMPO cannot handle scaling less than 0.25 and more than x16. For example:h]hHMPO cannot handle scaling less than 0.25 and more than x16. For example:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubh)}(hvIf 4k video (3840x2160) is playing in windowed mode, the physical size of the window cannot be smaller than (960x540).h]hvIf 4k video (3840x2160) is playing in windowed mode, the physical size of the window cannot be smaller than (960x540).}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubh)}(h7These scaling limitations might vary from ASIC to ASIC.h]h)}(hj< h]h7These scaling limitations might vary from ASIC to ASIC.}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj: ubah}(h]h ]h"]h$]h&]uh1hhjrhhhhhNubh)}(hhh]h)}(h**Size Limitation** h]h)}(h**Size Limitation**h]j)}(hjZ h]hSize Limitation}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX ubah}(h]h ]h"]h$]h&]uh1hhhhKhjT ubah}(h]h ]h"]h$]h&]uh1hhjQ hhhhhNubah}(h]h ]h"]h$]h&]j2j3uh1hhhhKhjrhhubh)}(hThe minimum MPO size is 12px.h]hThe minimum MPO size is 12px.}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubeh}(h] limitationsah ]h"] limitationsah$]h&]uh1hhj&hhhhhKubeh}(h]multiple-display-mpoah ]h"]multiple display mpoah$]h&]uh1hhjhhhhhKubeh}(h] use-casesah ]h"] use casesah$]h&]uh1hhhhhhhhKjubeh}(h]multiplane-overlay-mpoah ]h"]multiplane overlay (mpo)ah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehʌ _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j j jljijjj j j#j j j j j u nametypes}(j jljj j#j j uh}(j hjijjjoj jj jj j&j jru footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.